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net: dsa: mv88e6xxx: factorize GLOBAL_CONTROL_2 setup
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
19b2f97e 18#include <linux/jiffies.h>
91da11f8 19#include <linux/list.h>
2bbba277 20#include <linux/module.h>
91da11f8 21#include <linux/netdevice.h>
c8c1b39a 22#include <linux/gpio/consumer.h>
91da11f8 23#include <linux/phy.h>
c8f0b869 24#include <net/dsa.h>
1f36faf2 25#include <net/switchdev.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
158bc065 28static void assert_smi_lock(struct mv88e6xxx_priv_state *ps)
3996a4ff 29{
3996a4ff 30 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
158bc065 31 dev_err(ps->dev, "SMI lock not held!\n");
3996a4ff
VD		 32 dump_stack();
33 }
34}
35
3675c8d7 36/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 37 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
38 * will be directly accessible on some {device address,register address}
39 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
40 * will only respond to SMI transactions to that specific address, and
41 * an indirect addressing mechanism needs to be used to access its
42 * registers.
43 */
44static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
45{
46 int ret;
47 int i;
48
49 for (i = 0; i < 16; i++) {
6e899e6c 50 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 51 if (ret < 0)
52 return ret;
53
cca8b133 54 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 55 return 0;
56 }
57
58 return -ETIMEDOUT;
59}
60
b9b37713
VD		 61static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
62 int reg)
91da11f8
LB		 63{
64 int ret;
65
66 if (sw_addr == 0)
6e899e6c 67 return mdiobus_read_nested(bus, addr, reg);
91da11f8 68
3675c8d7 69 /* Wait for the bus to become free. */
91da11f8
LB		 70 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
71 if (ret < 0)
72 return ret;
73
3675c8d7 74 /* Transmit the read command. */
6e899e6c
NA		 75 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
76 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 77 if (ret < 0)
78 return ret;
79
3675c8d7 80 /* Wait for the read command to complete. */
91da11f8
LB		 81 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
82 if (ret < 0)
83 return ret;
84
3675c8d7 85 /* Read the data. */
6e899e6c 86 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 87 if (ret < 0)
88 return ret;
89
90 return ret & 0xffff;
91}
92
158bc065
AL		 93static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps,
94 int addr, int reg)
91da11f8 95{
91da11f8
LB		 96 int ret;
97
158bc065 98 assert_smi_lock(ps);
3996a4ff 99
a77d43f1 100 ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
bb92ea5e
VD		 101 if (ret < 0)
102 return ret;
103
158bc065 104 dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 105 addr, reg, ret);
106
91da11f8
LB		 107 return ret;
108}
109
158bc065 110int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, int reg)
8d6d09e7 111{
8d6d09e7
GR		 112 int ret;
113
114 mutex_lock(&ps->smi_mutex);
158bc065 115 ret = _mv88e6xxx_reg_read(ps, addr, reg);
8d6d09e7
GR		 116 mutex_unlock(&ps->smi_mutex);
117
118 return ret;
119}
120
b9b37713
VD		 121static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
122 int reg, u16 val)
91da11f8
LB		 123{
124 int ret;
125
126 if (sw_addr == 0)
6e899e6c 127 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 128
3675c8d7 129 /* Wait for the bus to become free. */
91da11f8
LB		 130 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
131 if (ret < 0)
132 return ret;
133
3675c8d7 134 /* Transmit the data to write. */
6e899e6c 135 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the write command. */
6e899e6c
NA		 140 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
141 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the write command to complete. */
91da11f8
LB		 146 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
147 if (ret < 0)
148 return ret;
149
150 return 0;
151}
152
158bc065
AL		 153static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
154 int reg, u16 val)
91da11f8 155{
158bc065 156 assert_smi_lock(ps);
91da11f8 157
158bc065 158 dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 159 addr, reg, val);
160
a77d43f1 161 return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
8d6d09e7
GR		 162}
163
158bc065
AL		 164int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
165 int reg, u16 val)
8d6d09e7 166{
8d6d09e7
GR		 167 int ret;
168
91da11f8 169 mutex_lock(&ps->smi_mutex);
158bc065 170 ret = _mv88e6xxx_reg_write(ps, addr, reg, val);
91da11f8
LB		 171 mutex_unlock(&ps->smi_mutex);
172
173 return ret;
174}
175
1d13a06e 176static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
2e5f0320 177{
158bc065 178 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
48ace4ef 179 int err;
2e5f0320 180
158bc065 181 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01,
48ace4ef
AL		 182 (addr[0] << 8) | addr[1]);
183 if (err)
184 return err;
185
158bc065 186 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23,
48ace4ef
AL		 187 (addr[2] << 8) | addr[3]);
188 if (err)
189 return err;
190
158bc065 191 return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45,
48ace4ef 192 (addr[4] << 8) | addr[5]);
2e5f0320
LB		 193}
194
1d13a06e 195static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
91da11f8 196{
158bc065 197 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8 198 int ret;
48ace4ef 199 int i;
91da11f8
LB		 200
201 for (i = 0; i < 6; i++) {
202 int j;
203
3675c8d7 204 /* Write the MAC address byte. */
158bc065 205 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
48ace4ef
AL		 206 GLOBAL2_SWITCH_MAC_BUSY |
207 (i << 8) | addr[i]);
208 if (ret)
209 return ret;
91da11f8 210
3675c8d7 211 /* Wait for the write to complete. */
91da11f8 212 for (j = 0; j < 16; j++) {
158bc065 213 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2,
48ace4ef
AL		 214 GLOBAL2_SWITCH_MAC);
215 if (ret < 0)
216 return ret;
217
cca8b133 218 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 219 break;
220 }
221 if (j == 16)
222 return -ETIMEDOUT;
223 }
224
225 return 0;
226}
227
1d13a06e
VD		 228int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
229{
230 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
231
232 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC))
233 return mv88e6xxx_set_addr_indirect(ds, addr);
234 else
235 return mv88e6xxx_set_addr_direct(ds, addr);
236}
237
158bc065
AL		 238static int _mv88e6xxx_phy_read(struct mv88e6xxx_priv_state *ps, int addr,
239 int regnum)
91da11f8
LB		 240{
241 if (addr >= 0)
158bc065 242 return _mv88e6xxx_reg_read(ps, addr, regnum);
91da11f8
LB		 243 return 0xffff;
244}
245
158bc065
AL		 246static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state *ps, int addr,
247 int regnum, u16 val)
91da11f8
LB		 248{
249 if (addr >= 0)
158bc065 250 return _mv88e6xxx_reg_write(ps, addr, regnum, val);
91da11f8
LB		 251 return 0;
252}
253
158bc065 254static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
2e5f0320
LB		 255{
256 int ret;
19b2f97e 257 unsigned long timeout;
2e5f0320 258
8c9983a2 259 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 260 if (ret < 0)
261 return ret;
262
8c9983a2
VD		 263 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
264 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 265 if (ret)
266 return ret;
2e5f0320 267
19b2f97e
BG		 268 timeout = jiffies + 1 * HZ;
269 while (time_before(jiffies, timeout)) {
8c9983a2 270 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 271 if (ret < 0)
272 return ret;
273
19b2f97e 274 usleep_range(1000, 2000);
cca8b133
AL		 275 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
276 GLOBAL_STATUS_PPU_POLLING)
85686581 277 return 0;
2e5f0320
LB		 278 }
279
280 return -ETIMEDOUT;
281}
282
158bc065 283static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps)
2e5f0320 284{
48ace4ef 285 int ret, err;
19b2f97e 286 unsigned long timeout;
2e5f0320 287
158bc065 288 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 289 if (ret < 0)
290 return ret;
291
158bc065 292 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
48ace4ef
AL		 293 ret | GLOBAL_CONTROL_PPU_ENABLE);
294 if (err)
295 return err;
2e5f0320 296
19b2f97e
BG		 297 timeout = jiffies + 1 * HZ;
298 while (time_before(jiffies, timeout)) {
158bc065 299 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 300 if (ret < 0)
301 return ret;
302
19b2f97e 303 usleep_range(1000, 2000);
cca8b133
AL		 304 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
305 GLOBAL_STATUS_PPU_POLLING)
85686581 306 return 0;
2e5f0320
LB		 307 }
308
309 return -ETIMEDOUT;
310}
311
312static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
313{
314 struct mv88e6xxx_priv_state *ps;
315
316 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
317 if (mutex_trylock(&ps->ppu_mutex)) {
158bc065 318 if (mv88e6xxx_ppu_enable(ps) == 0)
85686581
BG		 319 ps->ppu_disabled = 0;
320 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 321 }
322}
323
324static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
325{
326 struct mv88e6xxx_priv_state *ps = (void *)_ps;
327
328 schedule_work(&ps->ppu_work);
329}
330
158bc065 331static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps)
2e5f0320 332{
2e5f0320
LB		 333 int ret;
334
335 mutex_lock(&ps->ppu_mutex);
336
3675c8d7 337 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 338 * we can access the PHY registers. If it was already
339 * disabled, cancel the timer that is going to re-enable
340 * it.
341 */
342 if (!ps->ppu_disabled) {
158bc065 343 ret = mv88e6xxx_ppu_disable(ps);
85686581
BG		 344 if (ret < 0) {
345 mutex_unlock(&ps->ppu_mutex);
346 return ret;
347 }
348 ps->ppu_disabled = 1;
2e5f0320 349 } else {
85686581
BG		 350 del_timer(&ps->ppu_timer);
351 ret = 0;
2e5f0320
LB		 352 }
353
354 return ret;
355}
356
158bc065 357static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps)
2e5f0320 358{
3675c8d7 359 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 360 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
361 mutex_unlock(&ps->ppu_mutex);
362}
363
158bc065 364void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps)
2e5f0320 365{
2e5f0320
LB		 366 mutex_init(&ps->ppu_mutex);
367 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
368 init_timer(&ps->ppu_timer);
369 ps->ppu_timer.data = (unsigned long)ps;
370 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
371}
372
8c9983a2
VD		 373static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state *ps, int addr,
374 int regnum)
2e5f0320
LB		 375{
376 int ret;
377
158bc065 378 ret = mv88e6xxx_ppu_access_get(ps);
2e5f0320 379 if (ret >= 0) {
8c9983a2 380 ret = _mv88e6xxx_reg_read(ps, addr, regnum);
158bc065 381 mv88e6xxx_ppu_access_put(ps);
2e5f0320
LB		 382 }
383
384 return ret;
385}
386
8c9983a2
VD		 387static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state *ps, int addr,
388 int regnum, u16 val)
2e5f0320
LB		 389{
390 int ret;
391
158bc065 392 ret = mv88e6xxx_ppu_access_get(ps);
2e5f0320 393 if (ret >= 0) {
8c9983a2 394 ret = _mv88e6xxx_reg_write(ps, addr, regnum, val);
158bc065 395 mv88e6xxx_ppu_access_put(ps);
2e5f0320
LB		 396 }
397
398 return ret;
399}
2e5f0320 400
158bc065 401static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps)
54d792f2 402{
22356476 403 return ps->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 404}
405
158bc065 406static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps)
54d792f2 407{
22356476 408 return ps->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 409}
410
158bc065 411static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps)
54d792f2 412{
22356476 413 return ps->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 414}
415
158bc065 416static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps)
54d792f2 417{
22356476 418 return ps->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 419}
420
158bc065 421static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps)
54d792f2 422{
22356476 423 return ps->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 424}
425
158bc065 426static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps)
7c3d0d67 427{
22356476 428 return ps->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 429}
430
158bc065 431static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps)
54d792f2 432{
22356476 433 return ps->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 434}
435
158bc065 436static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps)
f3a8b6b6 437{
22356476 438 return ps->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 439}
440
158bc065 441static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps)
f74df0be 442{
cd5a2c82 443 return ps->info->num_databases;
f74df0be
VD		 444}
445
158bc065 446static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps)
b426e5f7
VD		 447{
448 /* Does the device have dedicated FID registers for ATU and VTU ops? */
158bc065
AL		 449 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
450 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
b426e5f7
VD		 451 return true;
452
453 return false;
454}
455
158bc065 456static bool mv88e6xxx_has_stu(struct mv88e6xxx_priv_state *ps)
2e7bd5ef
VD		 457{
458 /* Does the device have STU and dedicated SID registers for VTU ops? */
158bc065
AL		 459 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
460 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
2e7bd5ef
VD		 461 return true;
462
463 return false;
464}
465
dea87024
AL		 466/* We expect the switch to perform auto negotiation if there is a real
467 * phy. However, in the case of a fixed link phy, we force the port
468 * settings from the fixed link settings.
469 */
470void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
471 struct phy_device *phydev)
472{
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 474 u32 reg;
475 int ret;
dea87024
AL		 476
477 if (!phy_is_pseudo_fixed_link(phydev))
478 return;
479
480 mutex_lock(&ps->smi_mutex);
481
158bc065 482 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 483 if (ret < 0)
484 goto out;
485
486 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
487 PORT_PCS_CTRL_FORCE_LINK |
488 PORT_PCS_CTRL_DUPLEX_FULL |
489 PORT_PCS_CTRL_FORCE_DUPLEX |
490 PORT_PCS_CTRL_UNFORCED);
491
492 reg |= PORT_PCS_CTRL_FORCE_LINK;
493 if (phydev->link)
494 reg |= PORT_PCS_CTRL_LINK_UP;
495
158bc065 496 if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100)
dea87024
AL		 497 goto out;
498
499 switch (phydev->speed) {
500 case SPEED_1000:
501 reg |= PORT_PCS_CTRL_1000;
502 break;
503 case SPEED_100:
504 reg |= PORT_PCS_CTRL_100;
505 break;
506 case SPEED_10:
507 reg |= PORT_PCS_CTRL_10;
508 break;
509 default:
510 pr_info("Unknown speed");
511 goto out;
512 }
513
514 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
515 if (phydev->duplex == DUPLEX_FULL)
516 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
517
158bc065 518 if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) &&
009a2b98 519 (port >= ps->info->num_ports - 2)) {
e7e72ac0
AL		 520 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
521 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
522 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
523 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
524 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
525 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
526 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
527 }
158bc065 528 _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 529
530out:
531 mutex_unlock(&ps->smi_mutex);
532}
533
158bc065 534static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps)
91da11f8
LB		 535{
536 int ret;
537 int i;
538
539 for (i = 0; i < 10; i++) {
158bc065 540 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 541 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 542 return 0;
543 }
544
545 return -ETIMEDOUT;
546}
547
158bc065
AL		 548static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps,
549 int port)
91da11f8
LB		 550{
551 int ret;
552
158bc065 553 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
f3a8b6b6
AL		 554 port = (port + 1) << 5;
555
3675c8d7 556 /* Snapshot the hardware statistics counters for this port. */
158bc065 557 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 558 GLOBAL_STATS_OP_CAPTURE_PORT |
559 GLOBAL_STATS_OP_HIST_RX_TX | port);
560 if (ret < 0)
561 return ret;
91da11f8 562
3675c8d7 563 /* Wait for the snapshotting to complete. */
158bc065 564 ret = _mv88e6xxx_stats_wait(ps);
91da11f8
LB		 565 if (ret < 0)
566 return ret;
567
568 return 0;
569}
570
158bc065
AL		 571static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps,
572 int stat, u32 *val)
91da11f8
LB		 573{
574 u32 _val;
575 int ret;
576
577 *val = 0;
578
158bc065 579 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 580 GLOBAL_STATS_OP_READ_CAPTURED |
581 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 582 if (ret < 0)
583 return;
584
158bc065 585 ret = _mv88e6xxx_stats_wait(ps);
91da11f8
LB		 586 if (ret < 0)
587 return;
588
158bc065 589 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 590 if (ret < 0)
591 return;
592
593 _val = ret << 16;
594
158bc065 595 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 596 if (ret < 0)
597 return;
598
599 *val = _val | ret;
600}
601
e413e7e1 602static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 603 { "in_good_octets", 8, 0x00, BANK0, },
604 { "in_bad_octets", 4, 0x02, BANK0, },
605 { "in_unicast", 4, 0x04, BANK0, },
606 { "in_broadcasts", 4, 0x06, BANK0, },
607 { "in_multicasts", 4, 0x07, BANK0, },
608 { "in_pause", 4, 0x16, BANK0, },
609 { "in_undersize", 4, 0x18, BANK0, },
610 { "in_fragments", 4, 0x19, BANK0, },
611 { "in_oversize", 4, 0x1a, BANK0, },
612 { "in_jabber", 4, 0x1b, BANK0, },
613 { "in_rx_error", 4, 0x1c, BANK0, },
614 { "in_fcs_error", 4, 0x1d, BANK0, },
615 { "out_octets", 8, 0x0e, BANK0, },
616 { "out_unicast", 4, 0x10, BANK0, },
617 { "out_broadcasts", 4, 0x13, BANK0, },
618 { "out_multicasts", 4, 0x12, BANK0, },
619 { "out_pause", 4, 0x15, BANK0, },
620 { "excessive", 4, 0x11, BANK0, },
621 { "collisions", 4, 0x1e, BANK0, },
622 { "deferred", 4, 0x05, BANK0, },
623 { "single", 4, 0x14, BANK0, },
624 { "multiple", 4, 0x17, BANK0, },
625 { "out_fcs_error", 4, 0x03, BANK0, },
626 { "late", 4, 0x1f, BANK0, },
627 { "hist_64bytes", 4, 0x08, BANK0, },
628 { "hist_65_127bytes", 4, 0x09, BANK0, },
629 { "hist_128_255bytes", 4, 0x0a, BANK0, },
630 { "hist_256_511bytes", 4, 0x0b, BANK0, },
631 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
632 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
633 { "sw_in_discards", 4, 0x10, PORT, },
634 { "sw_in_filtered", 2, 0x12, PORT, },
635 { "sw_out_filtered", 2, 0x13, PORT, },
636 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
637 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
638 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
639 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
640 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
641 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
642 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
643 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
644 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
645 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
646 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
647 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
648 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
649 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
650 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
651 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
652 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
653 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 662};
663
158bc065 664static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps,
f5e2ed02 665 struct mv88e6xxx_hw_stat *stat)
e413e7e1 666{
f5e2ed02
AL		 667 switch (stat->type) {
668 case BANK0:
e413e7e1 669 return true;
f5e2ed02 670 case BANK1:
158bc065 671 return mv88e6xxx_6320_family(ps);
f5e2ed02 672 case PORT:
158bc065
AL		 673 return mv88e6xxx_6095_family(ps) ||
674 mv88e6xxx_6185_family(ps) ||
675 mv88e6xxx_6097_family(ps) ||
676 mv88e6xxx_6165_family(ps) ||
677 mv88e6xxx_6351_family(ps) ||
678 mv88e6xxx_6352_family(ps);
91da11f8 679 }
f5e2ed02 680 return false;
91da11f8
LB		 681}
682
158bc065 683static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
f5e2ed02 684 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 685 int port)
686{
80c4627b
AL		 687 u32 low;
688 u32 high = 0;
689 int ret;
690 u64 value;
691
f5e2ed02
AL		 692 switch (s->type) {
693 case PORT:
158bc065 694 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg);
80c4627b
AL		 695 if (ret < 0)
696 return UINT64_MAX;
697
698 low = ret;
699 if (s->sizeof_stat == 4) {
158bc065 700 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port),
f5e2ed02 701 s->reg + 1);
80c4627b
AL		 702 if (ret < 0)
703 return UINT64_MAX;
704 high = ret;
705 }
f5e2ed02
AL		 706 break;
707 case BANK0:
708 case BANK1:
158bc065 709 _mv88e6xxx_stats_read(ps, s->reg, &low);
80c4627b 710 if (s->sizeof_stat == 8)
158bc065 711 _mv88e6xxx_stats_read(ps, s->reg + 1, &high);
80c4627b
AL		 712 }
713 value = (((u64)high) << 16) | low;
714 return value;
715}
716
f5e2ed02 717void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
91da11f8 718{
158bc065 719 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f5e2ed02
AL		 720 struct mv88e6xxx_hw_stat *stat;
721 int i, j;
91da11f8 722
f5e2ed02
AL		 723 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
724 stat = &mv88e6xxx_hw_stats[i];
158bc065 725 if (mv88e6xxx_has_stat(ps, stat)) {
f5e2ed02
AL		 726 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
727 ETH_GSTRING_LEN);
728 j++;
729 }
91da11f8 730 }
e413e7e1
AL		 731}
732
733int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
734{
158bc065 735 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f5e2ed02
AL		 736 struct mv88e6xxx_hw_stat *stat;
737 int i, j;
738
739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
158bc065 741 if (mv88e6xxx_has_stat(ps, stat))
f5e2ed02
AL		 742 j++;
743 }
744 return j;
e413e7e1
AL		 745}
746
747void
748mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
749 int port, uint64_t *data)
750{
f5e2ed02
AL		 751 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
752 struct mv88e6xxx_hw_stat *stat;
753 int ret;
754 int i, j;
755
756 mutex_lock(&ps->smi_mutex);
757
158bc065 758 ret = _mv88e6xxx_stats_snapshot(ps, port);
f5e2ed02
AL		 759 if (ret < 0) {
760 mutex_unlock(&ps->smi_mutex);
761 return;
762 }
763 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
764 stat = &mv88e6xxx_hw_stats[i];
158bc065
AL		 765 if (mv88e6xxx_has_stat(ps, stat)) {
766 data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port);
f5e2ed02
AL		 767 j++;
768 }
769 }
770
771 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 772}
773
a1ab91f3
GR		 774int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
775{
776 return 32 * sizeof(u16);
777}
778
779void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
780 struct ethtool_regs *regs, void *_p)
781{
158bc065 782 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
a1ab91f3
GR		 783 u16 *p = _p;
784 int i;
785
786 regs->version = 0;
787
788 memset(p, 0xff, 32 * sizeof(u16));
789
23062513
VD		 790 mutex_lock(&ps->smi_mutex);
791
a1ab91f3
GR		 792 for (i = 0; i < 32; i++) {
793 int ret;
794
23062513 795 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i);
a1ab91f3
GR		 796 if (ret >= 0)
797 p[i] = ret;
798 }
23062513
VD		 799
800 mutex_unlock(&ps->smi_mutex);
a1ab91f3
GR		 801}
802
158bc065 803static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
3898c148 804 u16 mask)
f3044683
AL		 805{
806 unsigned long timeout = jiffies + HZ / 10;
807
808 while (time_before(jiffies, timeout)) {
809 int ret;
810
158bc065 811 ret = _mv88e6xxx_reg_read(ps, reg, offset);
3898c148
AL		 812 if (ret < 0)
813 return ret;
f3044683
AL		 814 if (!(ret & mask))
815 return 0;
816
817 usleep_range(1000, 2000);
818 }
819 return -ETIMEDOUT;
820}
821
158bc065
AL		 822static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg,
823 int offset, u16 mask)
3898c148 824{
3898c148
AL		 825 int ret;
826
827 mutex_lock(&ps->smi_mutex);
158bc065 828 ret = _mv88e6xxx_wait(ps, reg, offset, mask);
3898c148
AL		 829 mutex_unlock(&ps->smi_mutex);
830
831 return ret;
832}
833
158bc065 834static int _mv88e6xxx_phy_wait(struct mv88e6xxx_priv_state *ps)
f3044683 835{
158bc065 836 return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148 837 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 838}
839
d24645be 840static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
f3044683 841{
158bc065
AL		 842 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
843
844 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 845 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 846}
847
d24645be 848static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
f3044683 849{
158bc065
AL		 850 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
851
852 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 853 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 854}
855
d24645be
VD		 856static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
857{
858 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
859 int ret;
860
861 mutex_lock(&ps->eeprom_mutex);
862
863 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
864 GLOBAL2_EEPROM_OP_READ |
865 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
866 if (ret < 0)
867 goto error;
868
869 ret = mv88e6xxx_eeprom_busy_wait(ds);
870 if (ret < 0)
871 goto error;
872
873 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
874error:
875 mutex_unlock(&ps->eeprom_mutex);
876 return ret;
877}
878
879int mv88e6xxx_get_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
880 u8 *data)
881{
882 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
883 int offset;
884 int len;
885 int ret;
886
887 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
888 return -EOPNOTSUPP;
889
890 offset = eeprom->offset;
891 len = eeprom->len;
892 eeprom->len = 0;
893
894 eeprom->magic = 0xc3ec4951;
895
896 ret = mv88e6xxx_eeprom_load_wait(ds);
897 if (ret < 0)
898 return ret;
899
900 if (offset & 1) {
901 int word;
902
903 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
904 if (word < 0)
905 return word;
906
907 *data++ = (word >> 8) & 0xff;
908
909 offset++;
910 len--;
911 eeprom->len++;
912 }
913
914 while (len >= 2) {
915 int word;
916
917 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
918 if (word < 0)
919 return word;
920
921 *data++ = word & 0xff;
922 *data++ = (word >> 8) & 0xff;
923
924 offset += 2;
925 len -= 2;
926 eeprom->len += 2;
927 }
928
929 if (len) {
930 int word;
931
932 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
933 if (word < 0)
934 return word;
935
936 *data++ = word & 0xff;
937
938 offset++;
939 len--;
940 eeprom->len++;
941 }
942
943 return 0;
944}
945
946static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
947{
948 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
949 int ret;
950
951 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
952 if (ret < 0)
953 return ret;
954
955 if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
956 return -EROFS;
957
958 return 0;
959}
960
961static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
962 u16 data)
963{
964 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
965 int ret;
966
967 mutex_lock(&ps->eeprom_mutex);
968
969 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
970 if (ret < 0)
971 goto error;
972
973 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
974 GLOBAL2_EEPROM_OP_WRITE |
975 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
976 if (ret < 0)
977 goto error;
978
979 ret = mv88e6xxx_eeprom_busy_wait(ds);
980error:
981 mutex_unlock(&ps->eeprom_mutex);
982 return ret;
983}
984
985int mv88e6xxx_set_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
986 u8 *data)
987{
988 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
989 int offset;
990 int ret;
991 int len;
992
993 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
994 return -EOPNOTSUPP;
995
996 if (eeprom->magic != 0xc3ec4951)
997 return -EINVAL;
998
999 ret = mv88e6xxx_eeprom_is_readonly(ds);
1000 if (ret)
1001 return ret;
1002
1003 offset = eeprom->offset;
1004 len = eeprom->len;
1005 eeprom->len = 0;
1006
1007 ret = mv88e6xxx_eeprom_load_wait(ds);
1008 if (ret < 0)
1009 return ret;
1010
1011 if (offset & 1) {
1012 int word;
1013
1014 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1015 if (word < 0)
1016 return word;
1017
1018 word = (*data++ << 8) | (word & 0xff);
1019
1020 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1021 if (ret < 0)
1022 return ret;
1023
1024 offset++;
1025 len--;
1026 eeprom->len++;
1027 }
1028
1029 while (len >= 2) {
1030 int word;
1031
1032 word = *data++;
1033 word |= *data++ << 8;
1034
1035 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1036 if (ret < 0)
1037 return ret;
1038
1039 offset += 2;
1040 len -= 2;
1041 eeprom->len += 2;
1042 }
1043
1044 if (len) {
1045 int word;
1046
1047 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1048 if (word < 0)
1049 return word;
1050
1051 word = (word & 0xff00) | *data++;
1052
1053 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1054 if (ret < 0)
1055 return ret;
1056
1057 offset++;
1058 len--;
1059 eeprom->len++;
1060 }
1061
1062 return 0;
1063}
1064
158bc065 1065static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps)
facd95b2 1066{
158bc065 1067 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP,
cca8b133 1068 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1069}
1070
158bc065
AL		 1071static int _mv88e6xxx_phy_read_indirect(struct mv88e6xxx_priv_state *ps,
1072 int addr, int regnum)
f3044683
AL		 1073{
1074 int ret;
1075
158bc065 1076 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1077 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1078 regnum);
1079 if (ret < 0)
1080 return ret;
f3044683 1081
158bc065 1082 ret = _mv88e6xxx_phy_wait(ps);
f3044683
AL		 1083 if (ret < 0)
1084 return ret;
1085
158bc065
AL		 1086 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1087
1088 return ret;
f3044683
AL		 1089}
1090
158bc065
AL		 1091static int _mv88e6xxx_phy_write_indirect(struct mv88e6xxx_priv_state *ps,
1092 int addr, int regnum, u16 val)
f3044683 1093{
3898c148
AL		 1094 int ret;
1095
158bc065 1096 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
3898c148
AL		 1097 if (ret < 0)
1098 return ret;
f3044683 1099
158bc065 1100 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1101 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1102 regnum);
1103
158bc065 1104 return _mv88e6xxx_phy_wait(ps);
f3044683
AL		 1105}
1106
11b3b45d
GR		 1107int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1108{
2f40c698 1109 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 1110 int reg;
1111
aadbdb8a
VD		 1112 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1113 return -EOPNOTSUPP;
1114
3898c148 1115 mutex_lock(&ps->smi_mutex);
2f40c698 1116
158bc065 1117 reg = _mv88e6xxx_phy_read_indirect(ps, port, 16);
11b3b45d 1118 if (reg < 0)
2f40c698 1119 goto out;
11b3b45d
GR		 1120
1121 e->eee_enabled = !!(reg & 0x0200);
1122 e->tx_lpi_enabled = !!(reg & 0x0100);
1123
158bc065 1124 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
11b3b45d 1125 if (reg < 0)
2f40c698 1126 goto out;
11b3b45d 1127
cca8b133 1128 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1129 reg = 0;
11b3b45d 1130
2f40c698 1131out:
3898c148 1132 mutex_unlock(&ps->smi_mutex);
2f40c698 1133 return reg;
11b3b45d
GR		 1134}
1135
1136int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1137 struct phy_device *phydev, struct ethtool_eee *e)
1138{
2f40c698
AL		 1139 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1140 int reg;
11b3b45d
GR		 1141 int ret;
1142
aadbdb8a
VD		 1143 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1144 return -EOPNOTSUPP;
1145
3898c148 1146 mutex_lock(&ps->smi_mutex);
11b3b45d 1147
158bc065 1148 ret = _mv88e6xxx_phy_read_indirect(ps, port, 16);
2f40c698
AL		 1149 if (ret < 0)
1150 goto out;
1151
1152 reg = ret & ~0x0300;
1153 if (e->eee_enabled)
1154 reg |= 0x0200;
1155 if (e->tx_lpi_enabled)
1156 reg |= 0x0100;
1157
158bc065 1158 ret = _mv88e6xxx_phy_write_indirect(ps, port, 16, reg);
2f40c698 1159out:
3898c148 1160 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 1161
1162 return ret;
11b3b45d
GR		 1163}
1164
158bc065 1165static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd)
facd95b2
GR		 1166{
1167 int ret;
1168
158bc065
AL		 1169 if (mv88e6xxx_has_fid_reg(ps)) {
1170 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid);
b426e5f7
VD		 1171 if (ret < 0)
1172 return ret;
158bc065 1173 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f 1174 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
158bc065 1175 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 1176 if (ret < 0)
1177 return ret;
1178
158bc065 1179 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 1180 (ret & 0xfff) |
1181 ((fid << 8) & 0xf000));
1182 if (ret < 0)
1183 return ret;
1184
1185 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1186 cmd |= fid & 0xf;
b426e5f7
VD		 1187 }
1188
158bc065 1189 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1190 if (ret < 0)
1191 return ret;
1192
158bc065 1193 return _mv88e6xxx_atu_wait(ps);
facd95b2
GR		 1194}
1195
158bc065 1196static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps,
37705b73
VD		 1197 struct mv88e6xxx_atu_entry *entry)
1198{
1199 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1200
1201 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1202 unsigned int mask, shift;
1203
1204 if (entry->trunk) {
1205 data |= GLOBAL_ATU_DATA_TRUNK;
1206 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1207 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1208 } else {
1209 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1210 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1211 }
1212
1213 data |= (entry->portv_trunkid << shift) & mask;
1214 }
1215
158bc065 1216 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1217}
1218
158bc065 1219static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps,
7fb5e755
VD		 1220 struct mv88e6xxx_atu_entry *entry,
1221 bool static_too)
facd95b2 1222{
7fb5e755
VD		 1223 int op;
1224 int err;
facd95b2 1225
158bc065 1226 err = _mv88e6xxx_atu_wait(ps);
7fb5e755
VD		 1227 if (err)
1228 return err;
facd95b2 1229
158bc065 1230 err = _mv88e6xxx_atu_data_write(ps, entry);
7fb5e755
VD		 1231 if (err)
1232 return err;
1233
1234 if (entry->fid) {
7fb5e755
VD		 1235 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1236 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1237 } else {
1238 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1239 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1240 }
1241
158bc065 1242 return _mv88e6xxx_atu_cmd(ps, entry->fid, op);
7fb5e755
VD		 1243}
1244
158bc065
AL		 1245static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps,
1246 u16 fid, bool static_too)
7fb5e755
VD		 1247{
1248 struct mv88e6xxx_atu_entry entry = {
1249 .fid = fid,
1250 .state = 0, /* EntryState bits must be 0 */
1251 };
70cc99d1 1252
158bc065 1253 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
7fb5e755
VD		 1254}
1255
158bc065
AL		 1256static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid,
1257 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1258{
1259 struct mv88e6xxx_atu_entry entry = {
1260 .trunk = false,
1261 .fid = fid,
1262 };
1263
1264 /* EntryState bits must be 0xF */
1265 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1266
1267 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1268 entry.portv_trunkid = (to_port & 0x0f) << 4;
1269 entry.portv_trunkid |= from_port & 0x0f;
1270
158bc065 1271 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
9f4d55d2
VD		 1272}
1273
158bc065
AL		 1274static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid,
1275 int port, bool static_too)
9f4d55d2
VD		 1276{
1277 /* Destination port 0xF means remove the entries */
158bc065 1278 return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1279}
1280
2d9deae4
VD		 1281static const char * const mv88e6xxx_port_state_names[] = {
1282 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1283 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1284 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1285 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1286};
1287
158bc065
AL		 1288static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1289 u8 state)
facd95b2 1290{
158bc065 1291 struct dsa_switch *ds = ps->ds;
c3ffe6d2 1292 int reg, ret = 0;
facd95b2
GR		 1293 u8 oldstate;
1294
158bc065 1295 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1296 if (reg < 0)
1297 return reg;
facd95b2 1298
cca8b133 1299 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1300
facd95b2
GR		 1301 if (oldstate != state) {
1302 /* Flush forwarding database if we're moving a port
1303 * from Learning or Forwarding state to Disabled or
1304 * Blocking or Listening state.
1305 */
2d9deae4
VD		 1306 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1307 oldstate == PORT_CONTROL_STATE_FORWARDING)
1308 && (state == PORT_CONTROL_STATE_DISABLED ||
1309 state == PORT_CONTROL_STATE_BLOCKING)) {
158bc065 1310 ret = _mv88e6xxx_atu_remove(ps, 0, port, false);
facd95b2 1311 if (ret)
2d9deae4 1312 return ret;
facd95b2 1313 }
2d9deae4 1314
cca8b133 1315 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
158bc065 1316 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL,
cca8b133 1317 reg);
2d9deae4
VD		 1318 if (ret)
1319 return ret;
1320
1321 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1322 mv88e6xxx_port_state_names[state],
1323 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1324 }
1325
facd95b2
GR		 1326 return ret;
1327}
1328
158bc065
AL		 1329static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1330 int port)
facd95b2 1331{
b7666efe 1332 struct net_device *bridge = ps->ports[port].bridge_dev;
009a2b98 1333 const u16 mask = (1 << ps->info->num_ports) - 1;
158bc065 1334 struct dsa_switch *ds = ps->ds;
b7666efe 1335 u16 output_ports = 0;
ede8098d 1336 int reg;
b7666efe
VD		 1337 int i;
1338
1339 /* allow CPU port or DSA link(s) to send frames to every port */
1340 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1341 output_ports = mask;
1342 } else {
009a2b98 1343 for (i = 0; i < ps->info->num_ports; ++i) {
b7666efe
VD		 1344 /* allow sending frames to every group member */
1345 if (bridge && ps->ports[i].bridge_dev == bridge)
1346 output_ports |= BIT(i);
1347
1348 /* allow sending frames to CPU port and DSA link(s) */
1349 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1350 output_ports |= BIT(i);
1351 }
1352 }
1353
1354 /* prevent frames from going back out of the port they came in on */
1355 output_ports &= ~BIT(port);
facd95b2 1356
158bc065 1357 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1358 if (reg < 0)
1359 return reg;
facd95b2 1360
ede8098d
VD		 1361 reg &= ~mask;
1362 reg |= output_ports & mask;
facd95b2 1363
158bc065 1364 return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1365}
1366
43c44a9f 1367void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
facd95b2
GR		 1368{
1369 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1370 int stp_state;
1371
936f234a
VD		 1372 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE))
1373 return;
1374
facd95b2
GR		 1375 switch (state) {
1376 case BR_STATE_DISABLED:
cca8b133 1377 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1378 break;
1379 case BR_STATE_BLOCKING:
1380 case BR_STATE_LISTENING:
cca8b133 1381 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1382 break;
1383 case BR_STATE_LEARNING:
cca8b133 1384 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1385 break;
1386 case BR_STATE_FORWARDING:
1387 default:
cca8b133 1388 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1389 break;
1390 }
1391
43c44a9f 1392 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
facd95b2
GR		 1393 * so we can not update the port state directly but need to schedule it.
1394 */
d715fa64 1395 ps->ports[port].state = stp_state;
2d9deae4 1396 set_bit(port, ps->port_state_update_mask);
facd95b2 1397 schedule_work(&ps->bridge_work);
facd95b2
GR		 1398}
1399
158bc065
AL		 1400static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1401 u16 *new, u16 *old)
76e398a6 1402{
158bc065 1403 struct dsa_switch *ds = ps->ds;
5da96031 1404 u16 pvid;
76e398a6
VD		 1405 int ret;
1406
158bc065 1407 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1408 if (ret < 0)
1409 return ret;
1410
5da96031
VD		 1411 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1412
1413 if (new) {
1414 ret &= ~PORT_DEFAULT_VLAN_MASK;
1415 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1416
158bc065 1417 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
5da96031
VD		 1418 PORT_DEFAULT_VLAN, ret);
1419 if (ret < 0)
1420 return ret;
1421
1422 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1423 pvid);
1424 }
1425
1426 if (old)
1427 *old = pvid;
76e398a6
VD		 1428
1429 return 0;
1430}
1431
158bc065
AL		 1432static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps,
1433 int port, u16 *pvid)
5da96031 1434{
158bc065 1435 return _mv88e6xxx_port_pvid(ps, port, NULL, pvid);
5da96031
VD		 1436}
1437
158bc065
AL		 1438static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps,
1439 int port, u16 pvid)
0d3b33e6 1440{
158bc065 1441 return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL);
0d3b33e6
VD		 1442}
1443
158bc065 1444static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps)
6b17e864 1445{
158bc065 1446 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP,
6b17e864
VD		 1447 GLOBAL_VTU_OP_BUSY);
1448}
1449
158bc065 1450static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op)
6b17e864
VD		 1451{
1452 int ret;
1453
158bc065 1454 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1455 if (ret < 0)
1456 return ret;
1457
158bc065 1458 return _mv88e6xxx_vtu_wait(ps);
6b17e864
VD		 1459}
1460
158bc065 1461static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps)
6b17e864
VD		 1462{
1463 int ret;
1464
158bc065 1465 ret = _mv88e6xxx_vtu_wait(ps);
6b17e864
VD		 1466 if (ret < 0)
1467 return ret;
1468
158bc065 1469 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1470}
1471
158bc065 1472static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
b8fee957
VD		 1473 struct mv88e6xxx_vtu_stu_entry *entry,
1474 unsigned int nibble_offset)
1475{
b8fee957
VD		 1476 u16 regs[3];
1477 int i;
1478 int ret;
1479
1480 for (i = 0; i < 3; ++i) {
158bc065 1481 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1482 GLOBAL_VTU_DATA_0_3 + i);
1483 if (ret < 0)
1484 return ret;
1485
1486 regs[i] = ret;
1487 }
1488
009a2b98 1489 for (i = 0; i < ps->info->num_ports; ++i) {
b8fee957
VD		 1490 unsigned int shift = (i % 4) * 4 + nibble_offset;
1491 u16 reg = regs[i / 4];
1492
1493 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1494 }
1495
1496 return 0;
1497}
1498
158bc065 1499static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
7dad08d7
VD		 1500 struct mv88e6xxx_vtu_stu_entry *entry,
1501 unsigned int nibble_offset)
1502{
7dad08d7
VD		 1503 u16 regs[3] = { 0 };
1504 int i;
1505 int ret;
1506
009a2b98 1507 for (i = 0; i < ps->info->num_ports; ++i) {
7dad08d7
VD		 1508 unsigned int shift = (i % 4) * 4 + nibble_offset;
1509 u8 data = entry->data[i];
1510
1511 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1512 }
1513
1514 for (i = 0; i < 3; ++i) {
158bc065 1515 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL,
7dad08d7
VD		 1516 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1517 if (ret < 0)
1518 return ret;
1519 }
1520
1521 return 0;
1522}
1523
158bc065 1524static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid)
36d04ba1 1525{
158bc065 1526 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1527 vid & GLOBAL_VTU_VID_MASK);
1528}
1529
158bc065 1530static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
b8fee957
VD		 1531 struct mv88e6xxx_vtu_stu_entry *entry)
1532{
1533 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1534 int ret;
1535
158bc065 1536 ret = _mv88e6xxx_vtu_wait(ps);
b8fee957
VD		 1537 if (ret < 0)
1538 return ret;
1539
158bc065 1540 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1541 if (ret < 0)
1542 return ret;
1543
158bc065 1544 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1545 if (ret < 0)
1546 return ret;
1547
1548 next.vid = ret & GLOBAL_VTU_VID_MASK;
1549 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1550
1551 if (next.valid) {
158bc065 1552 ret = _mv88e6xxx_vtu_stu_data_read(ps, &next, 0);
b8fee957
VD		 1553 if (ret < 0)
1554 return ret;
1555
158bc065
AL		 1556 if (mv88e6xxx_has_fid_reg(ps)) {
1557 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1558 GLOBAL_VTU_FID);
1559 if (ret < 0)
1560 return ret;
1561
1562 next.fid = ret & GLOBAL_VTU_FID_MASK;
158bc065 1563 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f
VD		 1564 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1565 * VTU DBNum[3:0] are located in VTU Operation 3:0
1566 */
158bc065 1567 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
11ea809f
VD		 1568 GLOBAL_VTU_OP);
1569 if (ret < 0)
1570 return ret;
1571
1572 next.fid = (ret & 0xf00) >> 4;
1573 next.fid |= ret & 0xf;
2e7bd5ef 1574 }
b8fee957 1575
158bc065
AL		 1576 if (mv88e6xxx_has_stu(ps)) {
1577 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1578 GLOBAL_VTU_SID);
1579 if (ret < 0)
1580 return ret;
1581
1582 next.sid = ret & GLOBAL_VTU_SID_MASK;
1583 }
1584 }
1585
1586 *entry = next;
1587 return 0;
1588}
1589
ceff5eff
VD		 1590int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1591 struct switchdev_obj_port_vlan *vlan,
1592 int (*cb)(struct switchdev_obj *obj))
1593{
1594 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1595 struct mv88e6xxx_vtu_stu_entry next;
1596 u16 pvid;
1597 int err;
1598
54d77b5b
VD		 1599 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
1600 return -EOPNOTSUPP;
1601
ceff5eff
VD		 1602 mutex_lock(&ps->smi_mutex);
1603
158bc065 1604 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
ceff5eff
VD		 1605 if (err)
1606 goto unlock;
1607
158bc065 1608 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1609 if (err)
1610 goto unlock;
1611
1612 do {
158bc065 1613 err = _mv88e6xxx_vtu_getnext(ps, &next);
ceff5eff
VD		 1614 if (err)
1615 break;
1616
1617 if (!next.valid)
1618 break;
1619
1620 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1621 continue;
1622
1623 /* reinit and dump this VLAN obj */
1624 vlan->vid_begin = vlan->vid_end = next.vid;
1625 vlan->flags = 0;
1626
1627 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1628 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1629
1630 if (next.vid == pvid)
1631 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1632
1633 err = cb(&vlan->obj);
1634 if (err)
1635 break;
1636 } while (next.vid < GLOBAL_VTU_VID_MASK);
1637
1638unlock:
1639 mutex_unlock(&ps->smi_mutex);
1640
1641 return err;
1642}
1643
158bc065 1644static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
7dad08d7
VD		 1645 struct mv88e6xxx_vtu_stu_entry *entry)
1646{
11ea809f 1647 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1648 u16 reg = 0;
1649 int ret;
1650
158bc065 1651 ret = _mv88e6xxx_vtu_wait(ps);
7dad08d7
VD		 1652 if (ret < 0)
1653 return ret;
1654
1655 if (!entry->valid)
1656 goto loadpurge;
1657
1658 /* Write port member tags */
158bc065 1659 ret = _mv88e6xxx_vtu_stu_data_write(ps, entry, 0);
7dad08d7
VD		 1660 if (ret < 0)
1661 return ret;
1662
158bc065 1663 if (mv88e6xxx_has_stu(ps)) {
7dad08d7 1664 reg = entry->sid & GLOBAL_VTU_SID_MASK;
158bc065 1665 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
7dad08d7
VD		 1666 if (ret < 0)
1667 return ret;
b426e5f7 1668 }
7dad08d7 1669
158bc065 1670 if (mv88e6xxx_has_fid_reg(ps)) {
7dad08d7 1671 reg = entry->fid & GLOBAL_VTU_FID_MASK;
158bc065 1672 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg);
7dad08d7
VD		 1673 if (ret < 0)
1674 return ret;
158bc065 1675 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f
VD		 1676 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1677 * VTU DBNum[3:0] are located in VTU Operation 3:0
1678 */
1679 op |= (entry->fid & 0xf0) << 8;
1680 op |= entry->fid & 0xf;
7dad08d7
VD		 1681 }
1682
1683 reg = GLOBAL_VTU_VID_VALID;
1684loadpurge:
1685 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
158bc065 1686 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1687 if (ret < 0)
1688 return ret;
1689
158bc065 1690 return _mv88e6xxx_vtu_cmd(ps, op);
7dad08d7
VD		 1691}
1692
158bc065 1693static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid,
0d3b33e6
VD		 1694 struct mv88e6xxx_vtu_stu_entry *entry)
1695{
1696 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1697 int ret;
1698
158bc065 1699 ret = _mv88e6xxx_vtu_wait(ps);
0d3b33e6
VD		 1700 if (ret < 0)
1701 return ret;
1702
158bc065 1703 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1704 sid & GLOBAL_VTU_SID_MASK);
1705 if (ret < 0)
1706 return ret;
1707
158bc065 1708 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1709 if (ret < 0)
1710 return ret;
1711
158bc065 1712 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1713 if (ret < 0)
1714 return ret;
1715
1716 next.sid = ret & GLOBAL_VTU_SID_MASK;
1717
158bc065 1718 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1719 if (ret < 0)
1720 return ret;
1721
1722 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1723
1724 if (next.valid) {
158bc065 1725 ret = _mv88e6xxx_vtu_stu_data_read(ps, &next, 2);
0d3b33e6
VD		 1726 if (ret < 0)
1727 return ret;
1728 }
1729
1730 *entry = next;
1731 return 0;
1732}
1733
158bc065 1734static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps,
0d3b33e6
VD		 1735 struct mv88e6xxx_vtu_stu_entry *entry)
1736{
1737 u16 reg = 0;
1738 int ret;
1739
158bc065 1740 ret = _mv88e6xxx_vtu_wait(ps);
0d3b33e6
VD		 1741 if (ret < 0)
1742 return ret;
1743
1744 if (!entry->valid)
1745 goto loadpurge;
1746
1747 /* Write port states */
158bc065 1748 ret = _mv88e6xxx_vtu_stu_data_write(ps, entry, 2);
0d3b33e6
VD		 1749 if (ret < 0)
1750 return ret;
1751
1752 reg = GLOBAL_VTU_VID_VALID;
1753loadpurge:
158bc065 1754 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1755 if (ret < 0)
1756 return ret;
1757
1758 reg = entry->sid & GLOBAL_VTU_SID_MASK;
158bc065 1759 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1760 if (ret < 0)
1761 return ret;
1762
158bc065 1763 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1764}
1765
158bc065
AL		 1766static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1767 u16 *new, u16 *old)
2db9ce1f 1768{
158bc065 1769 struct dsa_switch *ds = ps->ds;
f74df0be 1770 u16 upper_mask;
2db9ce1f
VD		 1771 u16 fid;
1772 int ret;
1773
158bc065 1774 if (mv88e6xxx_num_databases(ps) == 4096)
f74df0be 1775 upper_mask = 0xff;
158bc065 1776 else if (mv88e6xxx_num_databases(ps) == 256)
11ea809f 1777 upper_mask = 0xf;
f74df0be
VD		 1778 else
1779 return -EOPNOTSUPP;
1780
2db9ce1f 1781 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
158bc065 1782 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1783 if (ret < 0)
1784 return ret;
1785
1786 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1787
1788 if (new) {
1789 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1790 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1791
158bc065 1792 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1793 ret);
1794 if (ret < 0)
1795 return ret;
1796 }
1797
1798 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
158bc065 1799 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1800 if (ret < 0)
1801 return ret;
1802
f74df0be 1803 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1804
1805 if (new) {
f74df0be
VD		 1806 ret &= ~upper_mask;
1807 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1808
158bc065 1809 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1810 ret);
1811 if (ret < 0)
1812 return ret;
1813
1814 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1815 }
1816
1817 if (old)
1818 *old = fid;
1819
1820 return 0;
1821}
1822
158bc065
AL		 1823static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps,
1824 int port, u16 *fid)
2db9ce1f 1825{
158bc065 1826 return _mv88e6xxx_port_fid(ps, port, NULL, fid);
2db9ce1f
VD		 1827}
1828
158bc065
AL		 1829static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps,
1830 int port, u16 fid)
2db9ce1f 1831{
158bc065 1832 return _mv88e6xxx_port_fid(ps, port, &fid, NULL);
2db9ce1f
VD		 1833}
1834
158bc065 1835static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
3285f9e8
VD		 1836{
1837 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1838 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1839 int i, err;
3285f9e8
VD		 1840
1841 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1842
2db9ce1f 1843 /* Set every FID bit used by the (un)bridged ports */
009a2b98 1844 for (i = 0; i < ps->info->num_ports; ++i) {
158bc065 1845 err = _mv88e6xxx_port_fid_get(ps, i, fid);
2db9ce1f
VD		 1846 if (err)
1847 return err;
1848
1849 set_bit(*fid, fid_bitmap);
1850 }
1851
3285f9e8 1852 /* Set every FID bit used by the VLAN entries */
158bc065 1853 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1854 if (err)
1855 return err;
1856
1857 do {
158bc065 1858 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
3285f9e8
VD		 1859 if (err)
1860 return err;
1861
1862 if (!vlan.valid)
1863 break;
1864
1865 set_bit(vlan.fid, fid_bitmap);
1866 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1867
1868 /* The reset value 0x000 is used to indicate that multiple address
1869 * databases are not needed. Return the next positive available.
1870 */
1871 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
158bc065 1872 if (unlikely(*fid >= mv88e6xxx_num_databases(ps)))
3285f9e8
VD		 1873 return -ENOSPC;
1874
1875 /* Clear the database */
158bc065 1876 return _mv88e6xxx_atu_flush(ps, *fid, true);
3285f9e8
VD		 1877}
1878
158bc065 1879static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
2fb5ef09 1880 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1881{
158bc065 1882 struct dsa_switch *ds = ps->ds;
0d3b33e6
VD		 1883 struct mv88e6xxx_vtu_stu_entry vlan = {
1884 .valid = true,
1885 .vid = vid,
1886 };
3285f9e8
VD		 1887 int i, err;
1888
158bc065 1889 err = _mv88e6xxx_fid_new(ps, &vlan.fid);
3285f9e8
VD		 1890 if (err)
1891 return err;
0d3b33e6 1892
3d131f07 1893 /* exclude all ports except the CPU and DSA ports */
009a2b98 1894 for (i = 0; i < ps->info->num_ports; ++i)
3d131f07
VD		 1895 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1896 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1897 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1898
158bc065
AL		 1899 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
1900 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) {
0d3b33e6 1901 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1902
1903 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1904 * implemented, only one STU entry is needed to cover all VTU
1905 * entries. Thus, validate the SID 0.
1906 */
1907 vlan.sid = 0;
158bc065 1908 err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1909 if (err)
1910 return err;
1911
1912 if (vstp.sid != vlan.sid || !vstp.valid) {
1913 memset(&vstp, 0, sizeof(vstp));
1914 vstp.valid = true;
1915 vstp.sid = vlan.sid;
1916
158bc065 1917 err = _mv88e6xxx_stu_loadpurge(ps, &vstp);
0d3b33e6
VD		 1918 if (err)
1919 return err;
1920 }
0d3b33e6
VD		 1921 }
1922
1923 *entry = vlan;
1924 return 0;
1925}
1926
158bc065 1927static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
2fb5ef09
VD		 1928 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1929{
1930 int err;
1931
1932 if (!vid)
1933 return -EINVAL;
1934
158bc065 1935 err = _mv88e6xxx_vtu_vid_write(ps, vid - 1);
2fb5ef09
VD		 1936 if (err)
1937 return err;
1938
158bc065 1939 err = _mv88e6xxx_vtu_getnext(ps, entry);
2fb5ef09
VD		 1940 if (err)
1941 return err;
1942
1943 if (entry->vid != vid || !entry->valid) {
1944 if (!creat)
1945 return -EOPNOTSUPP;
1946 /* -ENOENT would've been more appropriate, but switchdev expects
1947 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1948 */
1949
158bc065 1950 err = _mv88e6xxx_vtu_new(ps, vid, entry);
2fb5ef09
VD		 1951 }
1952
1953 return err;
1954}
1955
da9c359e
VD		 1956static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1957 u16 vid_begin, u16 vid_end)
1958{
1959 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1960 struct mv88e6xxx_vtu_stu_entry vlan;
1961 int i, err;
1962
1963 if (!vid_begin)
1964 return -EOPNOTSUPP;
1965
1966 mutex_lock(&ps->smi_mutex);
1967
158bc065 1968 err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1);
da9c359e
VD		 1969 if (err)
1970 goto unlock;
1971
1972 do {
158bc065 1973 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
da9c359e
VD		 1974 if (err)
1975 goto unlock;
1976
1977 if (!vlan.valid)
1978 break;
1979
1980 if (vlan.vid > vid_end)
1981 break;
1982
009a2b98 1983 for (i = 0; i < ps->info->num_ports; ++i) {
da9c359e
VD		 1984 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1985 continue;
1986
1987 if (vlan.data[i] ==
1988 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1989 continue;
1990
1991 if (ps->ports[i].bridge_dev ==
1992 ps->ports[port].bridge_dev)
1993 break; /* same bridge, check next VLAN */
1994
1995 netdev_warn(ds->ports[port],
1996 "hardware VLAN %d already used by %s\n",
1997 vlan.vid,
1998 netdev_name(ps->ports[i].bridge_dev));
1999 err = -EOPNOTSUPP;
2000 goto unlock;
2001 }
2002 } while (vlan.vid < vid_end);
2003
2004unlock:
2005 mutex_unlock(&ps->smi_mutex);
2006
2007 return err;
2008}
2009
214cdb99
VD		 2010static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2011 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2012 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2013 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2014 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2015};
2016
2017int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2018 bool vlan_filtering)
2019{
2020 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2021 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2022 PORT_CONTROL_2_8021Q_DISABLED;
2023 int ret;
2024
54d77b5b
VD		 2025 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2026 return -EOPNOTSUPP;
2027
214cdb99
VD		 2028 mutex_lock(&ps->smi_mutex);
2029
158bc065 2030 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 2031 if (ret < 0)
2032 goto unlock;
2033
2034 old = ret & PORT_CONTROL_2_8021Q_MASK;
2035
5220ef1e
VD		 2036 if (new != old) {
2037 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2038 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 2039
158bc065 2040 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 2041 ret);
2042 if (ret < 0)
2043 goto unlock;
2044
2045 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
2046 mv88e6xxx_port_8021q_mode_names[new],
2047 mv88e6xxx_port_8021q_mode_names[old]);
2048 }
214cdb99 2049
5220ef1e 2050 ret = 0;
214cdb99
VD		 2051unlock:
2052 mutex_unlock(&ps->smi_mutex);
2053
2054 return ret;
2055}
2056
76e398a6
VD		 2057int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2058 const struct switchdev_obj_port_vlan *vlan,
2059 struct switchdev_trans *trans)
2060{
54d77b5b 2061 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
da9c359e
VD		 2062 int err;
2063
54d77b5b
VD		 2064 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2065 return -EOPNOTSUPP;
2066
da9c359e
VD		 2067 /* If the requested port doesn't belong to the same bridge as the VLAN
2068 * members, do not support it (yet) and fallback to software VLAN.
2069 */
2070 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2071 vlan->vid_end);
2072 if (err)
2073 return err;
2074
76e398a6
VD		 2075 /* We don't need any dynamic resource from the kernel (yet),
2076 * so skip the prepare phase.
2077 */
2078 return 0;
2079}
2080
158bc065
AL		 2081static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port,
2082 u16 vid, bool untagged)
0d3b33e6 2083{
0d3b33e6
VD		 2084 struct mv88e6xxx_vtu_stu_entry vlan;
2085 int err;
2086
158bc065 2087 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true);
0d3b33e6 2088 if (err)
76e398a6 2089 return err;
0d3b33e6 2090
0d3b33e6
VD		 2091 vlan.data[port] = untagged ?
2092 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2093 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2094
158bc065 2095 return _mv88e6xxx_vtu_loadpurge(ps, &vlan);
76e398a6
VD		 2096}
2097
4d5770b3
VD		 2098void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2099 const struct switchdev_obj_port_vlan *vlan,
2100 struct switchdev_trans *trans)
76e398a6
VD		 2101{
2102 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2103 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2104 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2105 u16 vid;
76e398a6 2106
54d77b5b
VD		 2107 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2108 return;
2109
76e398a6
VD		 2110 mutex_lock(&ps->smi_mutex);
2111
4d5770b3 2112 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
158bc065 2113 if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged))
4d5770b3
VD		 2114 netdev_err(ds->ports[port], "failed to add VLAN %d%c\n",
2115 vid, untagged ? 'u' : 't');
76e398a6 2116
158bc065 2117 if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end))
4d5770b3
VD		 2118 netdev_err(ds->ports[port], "failed to set PVID %d\n",
2119 vlan->vid_end);
0d3b33e6 2120
4d5770b3 2121 mutex_unlock(&ps->smi_mutex);
0d3b33e6
VD		 2122}
2123
158bc065
AL		 2124static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2125 int port, u16 vid)
7dad08d7 2126{
158bc065 2127 struct dsa_switch *ds = ps->ds;
7dad08d7 2128 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 2129 int i, err;
2130
158bc065 2131 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
7dad08d7 2132 if (err)
76e398a6 2133 return err;
7dad08d7 2134
2fb5ef09
VD		 2135 /* Tell switchdev if this VLAN is handled in software */
2136 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 2137 return -EOPNOTSUPP;
7dad08d7
VD		 2138
2139 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2140
2141 /* keep the VLAN unless all ports are excluded */
f02bdffc 2142 vlan.valid = false;
009a2b98 2143 for (i = 0; i < ps->info->num_ports; ++i) {
3d131f07 2144 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 2145 continue;
2146
2147 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 2148 vlan.valid = true;
7dad08d7
VD		 2149 break;
2150 }
2151 }
2152
158bc065 2153 err = _mv88e6xxx_vtu_loadpurge(ps, &vlan);
76e398a6
VD		 2154 if (err)
2155 return err;
2156
158bc065 2157 return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false);
76e398a6
VD		 2158}
2159
2160int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2161 const struct switchdev_obj_port_vlan *vlan)
2162{
2163 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2164 u16 pvid, vid;
2165 int err = 0;
2166
54d77b5b
VD		 2167 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2168 return -EOPNOTSUPP;
2169
76e398a6
VD		 2170 mutex_lock(&ps->smi_mutex);
2171
158bc065 2172 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
7dad08d7
VD		 2173 if (err)
2174 goto unlock;
2175
76e398a6 2176 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
158bc065 2177 err = _mv88e6xxx_port_vlan_del(ps, port, vid);
76e398a6
VD		 2178 if (err)
2179 goto unlock;
2180
2181 if (vid == pvid) {
158bc065 2182 err = _mv88e6xxx_port_pvid_set(ps, port, 0);
76e398a6
VD		 2183 if (err)
2184 goto unlock;
2185 }
2186 }
2187
7dad08d7
VD		 2188unlock:
2189 mutex_unlock(&ps->smi_mutex);
2190
2191 return err;
2192}
2193
158bc065 2194static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps,
c5723ac5 2195 const unsigned char *addr)
defb05b9
GR		 2196{
2197 int i, ret;
2198
2199 for (i = 0; i < 3; i++) {
cca8b133 2200 ret = _mv88e6xxx_reg_write(
158bc065 2201 ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2202 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2203 if (ret < 0)
2204 return ret;
2205 }
2206
2207 return 0;
2208}
2209
158bc065
AL		 2210static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps,
2211 unsigned char *addr)
defb05b9
GR		 2212{
2213 int i, ret;
2214
2215 for (i = 0; i < 3; i++) {
158bc065 2216 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
cca8b133 2217 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2218 if (ret < 0)
2219 return ret;
2220 addr[i * 2] = ret >> 8;
2221 addr[i * 2 + 1] = ret & 0xff;
2222 }
2223
2224 return 0;
2225}
2226
158bc065 2227static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps,
fd231c82 2228 struct mv88e6xxx_atu_entry *entry)
defb05b9 2229{
6630e236
VD		 2230 int ret;
2231
158bc065 2232 ret = _mv88e6xxx_atu_wait(ps);
defb05b9
GR		 2233 if (ret < 0)
2234 return ret;
2235
158bc065 2236 ret = _mv88e6xxx_atu_mac_write(ps, entry->mac);
defb05b9
GR		 2237 if (ret < 0)
2238 return ret;
2239
158bc065 2240 ret = _mv88e6xxx_atu_data_write(ps, entry);
fd231c82 2241 if (ret < 0)
87820510
VD		 2242 return ret;
2243
158bc065 2244 return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2245}
87820510 2246
158bc065 2247static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
fd231c82
VD		 2248 const unsigned char *addr, u16 vid,
2249 u8 state)
2250{
2251 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2252 struct mv88e6xxx_vtu_stu_entry vlan;
2253 int err;
2254
2db9ce1f
VD		 2255 /* Null VLAN ID corresponds to the port private database */
2256 if (vid == 0)
158bc065 2257 err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid);
2db9ce1f 2258 else
158bc065 2259 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
3285f9e8
VD		 2260 if (err)
2261 return err;
fd231c82 2262
3285f9e8 2263 entry.fid = vlan.fid;
fd231c82
VD		 2264 entry.state = state;
2265 ether_addr_copy(entry.mac, addr);
2266 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2267 entry.trunk = false;
2268 entry.portv_trunkid = BIT(port);
2269 }
2270
158bc065 2271 return _mv88e6xxx_atu_load(ps, &entry);
87820510
VD		 2272}
2273
146a3206
VD		 2274int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2275 const struct switchdev_obj_port_fdb *fdb,
2276 struct switchdev_trans *trans)
2277{
2672f825
VD		 2278 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2279
2280 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2281 return -EOPNOTSUPP;
2282
146a3206
VD		 2283 /* We don't need any dynamic resource from the kernel (yet),
2284 * so skip the prepare phase.
2285 */
2286 return 0;
2287}
2288
8497aa61
VD		 2289void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2290 const struct switchdev_obj_port_fdb *fdb,
2291 struct switchdev_trans *trans)
87820510 2292{
1f36faf2 2293 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2294 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2295 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 2296 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510 2297
2672f825
VD		 2298 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2299 return;
2300
87820510 2301 mutex_lock(&ps->smi_mutex);
158bc065 2302 if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state))
8497aa61 2303 netdev_err(ds->ports[port], "failed to load MAC address\n");
87820510 2304 mutex_unlock(&ps->smi_mutex);
87820510
VD		 2305}
2306
cdf09697 2307int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 2308 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 2309{
2310 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2311 int ret;
2312
2672f825
VD		 2313 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2314 return -EOPNOTSUPP;
2315
87820510 2316 mutex_lock(&ps->smi_mutex);
158bc065 2317 ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid,
cdf09697 2318 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 2319 mutex_unlock(&ps->smi_mutex);
2320
2321 return ret;
2322}
2323
158bc065 2324static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
1d194046 2325 struct mv88e6xxx_atu_entry *entry)
6630e236 2326{
1d194046
VD		 2327 struct mv88e6xxx_atu_entry next = { 0 };
2328 int ret;
2329
2330 next.fid = fid;
defb05b9 2331
158bc065 2332 ret = _mv88e6xxx_atu_wait(ps);
cdf09697
DM		 2333 if (ret < 0)
2334 return ret;
6630e236 2335
158bc065 2336 ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2337 if (ret < 0)
2338 return ret;
6630e236 2339
158bc065 2340 ret = _mv88e6xxx_atu_mac_read(ps, next.mac);
1d194046
VD		 2341 if (ret < 0)
2342 return ret;
6630e236 2343
158bc065 2344 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2345 if (ret < 0)
2346 return ret;
6630e236 2347
1d194046
VD		 2348 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2349 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2350 unsigned int mask, shift;
2351
2352 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2353 next.trunk = true;
2354 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2355 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2356 } else {
2357 next.trunk = false;
2358 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2359 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2360 }
2361
2362 next.portv_trunkid = (ret & mask) >> shift;
2363 }
cdf09697 2364
1d194046 2365 *entry = next;
cdf09697
DM		 2366 return 0;
2367}
2368
158bc065
AL		 2369static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps,
2370 u16 fid, u16 vid, int port,
74b6ba0d
VD		 2371 struct switchdev_obj_port_fdb *fdb,
2372 int (*cb)(struct switchdev_obj *obj))
2373{
2374 struct mv88e6xxx_atu_entry addr = {
2375 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2376 };
2377 int err;
2378
158bc065 2379 err = _mv88e6xxx_atu_mac_write(ps, addr.mac);
74b6ba0d
VD		 2380 if (err)
2381 return err;
2382
2383 do {
158bc065 2384 err = _mv88e6xxx_atu_getnext(ps, fid, &addr);
74b6ba0d
VD		 2385 if (err)
2386 break;
2387
2388 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2389 break;
2390
2391 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2392 bool is_static = addr.state ==
2393 (is_multicast_ether_addr(addr.mac) ?
2394 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2395 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2396
2397 fdb->vid = vid;
2398 ether_addr_copy(fdb->addr, addr.mac);
2399 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2400
2401 err = cb(&fdb->obj);
2402 if (err)
2403 break;
2404 }
2405 } while (!is_broadcast_ether_addr(addr.mac));
2406
2407 return err;
2408}
2409
f33475bd
VD		 2410int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2411 struct switchdev_obj_port_fdb *fdb,
2412 int (*cb)(struct switchdev_obj *obj))
2413{
2414 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2415 struct mv88e6xxx_vtu_stu_entry vlan = {
2416 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2417 };
2db9ce1f 2418 u16 fid;
f33475bd
VD		 2419 int err;
2420
2672f825
VD		 2421 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2422 return -EOPNOTSUPP;
2423
f33475bd
VD		 2424 mutex_lock(&ps->smi_mutex);
2425
2db9ce1f 2426 /* Dump port's default Filtering Information Database (VLAN ID 0) */
158bc065 2427 err = _mv88e6xxx_port_fid_get(ps, port, &fid);
2db9ce1f
VD		 2428 if (err)
2429 goto unlock;
2430
158bc065 2431 err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb);
2db9ce1f
VD		 2432 if (err)
2433 goto unlock;
2434
74b6ba0d 2435 /* Dump VLANs' Filtering Information Databases */
158bc065 2436 err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid);
f33475bd
VD		 2437 if (err)
2438 goto unlock;
2439
2440 do {
158bc065 2441 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
f33475bd 2442 if (err)
74b6ba0d 2443 break;
f33475bd
VD		 2444
2445 if (!vlan.valid)
2446 break;
2447
158bc065 2448 err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port,
74b6ba0d 2449 fdb, cb);
f33475bd 2450 if (err)
74b6ba0d 2451 break;
f33475bd
VD		 2452 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2453
2454unlock:
2455 mutex_unlock(&ps->smi_mutex);
2456
2457 return err;
2458}
2459
a6692754
VD		 2460int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2461 struct net_device *bridge)
e79a8bcb 2462{
a6692754 2463 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1d9619d5 2464 int i, err = 0;
466dfa07 2465
936f234a
VD		 2466 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2467 return -EOPNOTSUPP;
2468
466dfa07
VD		 2469 mutex_lock(&ps->smi_mutex);
2470
b7666efe 2471 /* Assign the bridge and remap each port's VLANTable */
a6692754 2472 ps->ports[port].bridge_dev = bridge;
b7666efe 2473
009a2b98 2474 for (i = 0; i < ps->info->num_ports; ++i) {
b7666efe 2475 if (ps->ports[i].bridge_dev == bridge) {
158bc065 2476 err = _mv88e6xxx_port_based_vlan_map(ps, i);
b7666efe
VD		 2477 if (err)
2478 break;
2479 }
2480 }
2481
466dfa07 2482 mutex_unlock(&ps->smi_mutex);
a6692754 2483
466dfa07 2484 return err;
e79a8bcb
VD		 2485}
2486
16bfa702 2487void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2488{
a6692754 2489 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 2490 struct net_device *bridge = ps->ports[port].bridge_dev;
16bfa702 2491 int i;
466dfa07 2492
936f234a
VD		 2493 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2494 return;
2495
466dfa07
VD		 2496 mutex_lock(&ps->smi_mutex);
2497
b7666efe 2498 /* Unassign the bridge and remap each port's VLANTable */
a6692754 2499 ps->ports[port].bridge_dev = NULL;
b7666efe 2500
009a2b98 2501 for (i = 0; i < ps->info->num_ports; ++i)
16bfa702 2502 if (i == port || ps->ports[i].bridge_dev == bridge)
158bc065 2503 if (_mv88e6xxx_port_based_vlan_map(ps, i))
16bfa702 2504 netdev_warn(ds->ports[i], "failed to remap\n");
b7666efe 2505
466dfa07 2506 mutex_unlock(&ps->smi_mutex);
66d9cd0f
VD		 2507}
2508
facd95b2
GR		 2509static void mv88e6xxx_bridge_work(struct work_struct *work)
2510{
2511 struct mv88e6xxx_priv_state *ps;
2512 struct dsa_switch *ds;
2513 int port;
2514
2515 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
7543a6d5 2516 ds = ps->ds;
facd95b2 2517
2d9deae4
VD		 2518 mutex_lock(&ps->smi_mutex);
2519
009a2b98 2520 for (port = 0; port < ps->info->num_ports; ++port)
2d9deae4 2521 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
158bc065
AL		 2522 _mv88e6xxx_port_state(ps, port, ps->ports[port].state))
2523 netdev_warn(ds->ports[port],
2524 "failed to update state to %s\n",
2d9deae4
VD		 2525 mv88e6xxx_port_state_names[ps->ports[port].state]);
2526
2527 mutex_unlock(&ps->smi_mutex);
facd95b2
GR		 2528}
2529
158bc065
AL		 2530static int _mv88e6xxx_phy_page_write(struct mv88e6xxx_priv_state *ps,
2531 int port, int page, int reg, int val)
75baacf0
PU		 2532{
2533 int ret;
2534
158bc065 2535 ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
75baacf0
PU		 2536 if (ret < 0)
2537 goto restore_page_0;
2538
158bc065 2539 ret = _mv88e6xxx_phy_write_indirect(ps, port, reg, val);
75baacf0 2540restore_page_0:
158bc065 2541 _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
75baacf0
PU		 2542
2543 return ret;
2544}
2545
158bc065
AL		 2546static int _mv88e6xxx_phy_page_read(struct mv88e6xxx_priv_state *ps,
2547 int port, int page, int reg)
75baacf0
PU		 2548{
2549 int ret;
2550
158bc065 2551 ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
75baacf0
PU		 2552 if (ret < 0)
2553 goto restore_page_0;
2554
158bc065 2555 ret = _mv88e6xxx_phy_read_indirect(ps, port, reg);
75baacf0 2556restore_page_0:
158bc065 2557 _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
75baacf0
PU		 2558
2559 return ret;
2560}
2561
552238b5
VD		 2562static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps)
2563{
2564 bool ppu_active = mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE);
2565 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2566 struct gpio_desc *gpiod = ps->ds->pd->reset;
2567 unsigned long timeout;
2568 int ret;
2569 int i;
2570
2571 /* Set all ports to the disabled state. */
2572 for (i = 0; i < ps->info->num_ports; i++) {
2573 ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL);
2574 if (ret < 0)
2575 return ret;
2576
2577 ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL,
2578 ret & 0xfffc);
2579 if (ret)
2580 return ret;
2581 }
2582
2583 /* Wait for transmit queues to drain. */
2584 usleep_range(2000, 4000);
2585
2586 /* If there is a gpio connected to the reset pin, toggle it */
2587 if (gpiod) {
2588 gpiod_set_value_cansleep(gpiod, 1);
2589 usleep_range(10000, 20000);
2590 gpiod_set_value_cansleep(gpiod, 0);
2591 usleep_range(10000, 20000);
2592 }
2593
2594 /* Reset the switch. Keep the PPU active if requested. The PPU
2595 * needs to be active to support indirect phy register access
2596 * through global registers 0x18 and 0x19.
2597 */
2598 if (ppu_active)
2599 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000);
2600 else
2601 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400);
2602 if (ret)
2603 return ret;
2604
2605 /* Wait up to one second for reset to complete. */
2606 timeout = jiffies + 1 * HZ;
2607 while (time_before(jiffies, timeout)) {
2608 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00);
2609 if (ret < 0)
2610 return ret;
2611
2612 if ((ret & is_reset) == is_reset)
2613 break;
2614 usleep_range(1000, 2000);
2615 }
2616 if (time_after(jiffies, timeout))
2617 ret = -ETIMEDOUT;
2618 else
2619 ret = 0;
2620
2621 return ret;
2622}
2623
158bc065 2624static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps)
13a7ebb3
PU		 2625{
2626 int ret;
2627
158bc065 2628 ret = _mv88e6xxx_phy_page_read(ps, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
13a7ebb3
PU		 2629 MII_BMCR);
2630 if (ret < 0)
2631 return ret;
2632
2633 if (ret & BMCR_PDOWN) {
2634 ret &= ~BMCR_PDOWN;
158bc065 2635 ret = _mv88e6xxx_phy_page_write(ps, REG_FIBER_SERDES,
13a7ebb3
PU		 2636 PAGE_FIBER_SERDES, MII_BMCR,
2637 ret);
2638 }
2639
2640 return ret;
2641}
2642
dbde9e66 2643static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 2644{
2645 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 2646 int ret;
54d792f2 2647 u16 reg;
d827e88a
GR		 2648
2649 mutex_lock(&ps->smi_mutex);
2650
158bc065
AL		 2651 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2652 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2653 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2654 mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2655 /* MAC Forcing register: don't force link, speed,
2656 * duplex or flow control state to any particular
2657 * values on physical ports, but force the CPU port
2658 * and all DSA ports to their maximum bandwidth and
2659 * full duplex.
2660 */
158bc065 2661 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2662 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2663 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2664 reg |= PORT_PCS_CTRL_FORCE_LINK |
2665 PORT_PCS_CTRL_LINK_UP |
2666 PORT_PCS_CTRL_DUPLEX_FULL |
2667 PORT_PCS_CTRL_FORCE_DUPLEX;
158bc065 2668 if (mv88e6xxx_6065_family(ps))
54d792f2
AL		 2669 reg |= PORT_PCS_CTRL_100;
2670 else
2671 reg |= PORT_PCS_CTRL_1000;
2672 } else {
2673 reg |= PORT_PCS_CTRL_UNFORCED;
2674 }
2675
158bc065 2676 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2677 PORT_PCS_CTRL, reg);
2678 if (ret)
2679 goto abort;
2680 }
2681
2682 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2683 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2684 * tunneling, determine priority by looking at 802.1p and IP
2685 * priority fields (IP prio has precedence), and set STP state
2686 * to Forwarding.
2687 *
2688 * If this is the CPU link, use DSA or EDSA tagging depending
2689 * on which tagging mode was configured.
2690 *
2691 * If this is a link to another switch, use DSA tagging mode.
2692 *
2693 * If this is the upstream port for this switch, enable
2694 * forwarding of unknown unicasts and multicasts.
2695 */
2696 reg = 0;
158bc065
AL		 2697 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2698 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2699 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2700 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps))
54d792f2
AL		 2701 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2702 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2703 PORT_CONTROL_STATE_FORWARDING;
2704 if (dsa_is_cpu_port(ds, port)) {
158bc065 2705 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
54d792f2 2706 reg |= PORT_CONTROL_DSA_TAG;
158bc065
AL		 2707 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2708 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2709 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2710 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2711 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2712 else
2713 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2714 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2715 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2716 }
2717
158bc065
AL		 2718 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2719 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2720 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2721 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2722 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2723 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2724 }
2725 }
6083ce71 2726 if (dsa_is_dsa_port(ds, port)) {
158bc065 2727 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
6083ce71 2728 reg |= PORT_CONTROL_DSA_TAG;
158bc065
AL		 2729 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2730 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2731 mv88e6xxx_6320_family(ps)) {
54d792f2 2732 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2733 }
2734
54d792f2
AL		 2735 if (port == dsa_upstream_port(ds))
2736 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2737 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2738 }
2739 if (reg) {
158bc065 2740 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2741 PORT_CONTROL, reg);
2742 if (ret)
2743 goto abort;
2744 }
2745
13a7ebb3
PU		 2746 /* If this port is connected to a SerDes, make sure the SerDes is not
2747 * powered down.
2748 */
158bc065
AL		 2749 if (mv88e6xxx_6352_family(ps)) {
2750 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
13a7ebb3
PU		 2751 if (ret < 0)
2752 goto abort;
2753 ret &= PORT_STATUS_CMODE_MASK;
2754 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2755 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2756 (ret == PORT_STATUS_CMODE_SGMII)) {
158bc065 2757 ret = mv88e6xxx_power_on_serdes(ps);
13a7ebb3
PU		 2758 if (ret < 0)
2759 goto abort;
2760 }
2761 }
2762
8efdda4a 2763 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2764 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2765 * untagged frames on this port, do a destination address lookup on all
2766 * received packets as usual, disable ARP mirroring and don't send a
2767 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2768 */
2769 reg = 0;
158bc065
AL		 2770 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2771 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2772 mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) ||
2773 mv88e6xxx_6185_family(ps))
54d792f2
AL		 2774 reg = PORT_CONTROL_2_MAP_DA;
2775
158bc065
AL		 2776 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2777 mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps))
54d792f2
AL		 2778 reg |= PORT_CONTROL_2_JUMBO_10240;
2779
158bc065 2780 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) {
54d792f2
AL		 2781 /* Set the upstream port this port should use */
2782 reg |= dsa_upstream_port(ds);
2783 /* enable forwarding of unknown multicast addresses to
2784 * the upstream port
2785 */
2786 if (port == dsa_upstream_port(ds))
2787 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2788 }
2789
46fbe5e5 2790 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2791
54d792f2 2792 if (reg) {
158bc065 2793 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2794 PORT_CONTROL_2, reg);
2795 if (ret)
2796 goto abort;
2797 }
2798
2799 /* Port Association Vector: when learning source addresses
2800 * of packets, add the address to the address database using
2801 * a port bitmap that has only the bit for this port set and
2802 * the other bits clear.
2803 */
4c7ea3c0 2804 reg = 1 << port;
996ecb82
VD		 2805 /* Disable learning for CPU port */
2806 if (dsa_is_cpu_port(ds, port))
65fa4027 2807 reg = 0;
4c7ea3c0 2808
158bc065 2809 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2
AL		 2810 if (ret)
2811 goto abort;
2812
2813 /* Egress rate control 2: disable egress rate control. */
158bc065 2814 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2815 0x0000);
2816 if (ret)
2817 goto abort;
2818
158bc065
AL		 2819 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2820 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2821 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2822 /* Do not limit the period of time that this port can
2823 * be paused for by the remote end or the period of
2824 * time that this port can pause the remote end.
2825 */
158bc065 2826 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2827 PORT_PAUSE_CTRL, 0x0000);
2828 if (ret)
2829 goto abort;
2830
2831 /* Port ATU control: disable limiting the number of
2832 * address database entries that this port is allowed
2833 * to use.
2834 */
158bc065 2835 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2836 PORT_ATU_CONTROL, 0x0000);
2837 /* Priority Override: disable DA, SA and VTU priority
2838 * override.
2839 */
158bc065 2840 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2841 PORT_PRI_OVERRIDE, 0x0000);
2842 if (ret)
2843 goto abort;
2844
2845 /* Port Ethertype: use the Ethertype DSA Ethertype
2846 * value.
2847 */
158bc065 2848 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2849 PORT_ETH_TYPE, ETH_P_EDSA);
2850 if (ret)
2851 goto abort;
2852 /* Tag Remap: use an identity 802.1p prio -> switch
2853 * prio mapping.
2854 */
158bc065 2855 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2856 PORT_TAG_REGMAP_0123, 0x3210);
2857 if (ret)
2858 goto abort;
2859
2860 /* Tag Remap 2: use an identity 802.1p prio -> switch
2861 * prio mapping.
2862 */
158bc065 2863 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2864 PORT_TAG_REGMAP_4567, 0x7654);
2865 if (ret)
2866 goto abort;
2867 }
2868
158bc065
AL		 2869 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2870 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2871 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2872 mv88e6xxx_6320_family(ps)) {
54d792f2 2873 /* Rate Control: disable ingress rate limiting. */
158bc065 2874 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2875 PORT_RATE_CONTROL, 0x0001);
2876 if (ret)
2877 goto abort;
2878 }
2879
366f0a0f
GR		 2880 /* Port Control 1: disable trunking, disable sending
2881 * learning messages to this port.
d827e88a 2882 */
158bc065 2883 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2884 if (ret)
2885 goto abort;
2886
207afda1 2887 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2888 * database, and allow bidirectional communication between the
2889 * CPU and DSA port(s), and the other ports.
d827e88a 2890 */
158bc065 2891 ret = _mv88e6xxx_port_fid_set(ps, port, 0);
2db9ce1f
VD		 2892 if (ret)
2893 goto abort;
2894
158bc065 2895 ret = _mv88e6xxx_port_based_vlan_map(ps, port);
d827e88a
GR		 2896 if (ret)
2897 goto abort;
2898
2899 /* Default VLAN ID and priority: don't set a default VLAN
2900 * ID, and set the default packet priority to zero.
2901 */
158bc065 2902 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2903 0x0000);
d827e88a
GR		 2904abort:
2905 mutex_unlock(&ps->smi_mutex);
2906 return ret;
2907}
2908
dbde9e66
AL		 2909int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2910{
2911 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2912 int ret;
2913 int i;
2914
009a2b98 2915 for (i = 0; i < ps->info->num_ports; i++) {
dbde9e66
AL		 2916 ret = mv88e6xxx_setup_port(ds, i);
2917 if (ret < 0)
2918 return ret;
2919 }
2920 return 0;
2921}
2922
08a01261 2923static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
acdaffcc 2924{
b0745e87
VD		 2925 struct dsa_switch *ds = ps->ds;
2926 u32 upstream_port = dsa_upstream_port(ds);
119477bd 2927 u16 reg;
552238b5 2928 int err;
54d792f2
AL		 2929 int i;
2930
119477bd
VD		 2931 /* Enable the PHY Polling Unit if present, don't discard any packets,
2932 * and mask all interrupt sources.
2933 */
2934 reg = 0;
2935 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) ||
2936 mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE))
2937 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2938
2939 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg);
2940 if (err)
2941 return err;
2942
b0745e87
VD		 2943 /* Configure the upstream port, and configure it as the port to which
2944 * ingress and egress and ARP monitor frames are to be sent.
2945 */
2946 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2947 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2948 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2949 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
2950 if (err)
2951 return err;
2952
50484ff4
VD		 2953 /* Disable remote management, and set the switch's DSA device number. */
2954 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2,
2955 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2956 (ds->index & 0x1f));
2957 if (err)
2958 return err;
2959
54d792f2
AL		 2960 /* Set the default address aging time to 5 minutes, and
2961 * enable address learn messages to be sent to all message
2962 * ports.
2963 */
158bc065 2964 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
48ace4ef
AL		 2965 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2966 if (err)
08a01261 2967 return err;
54d792f2
AL		 2968
2969 /* Configure the IP ToS mapping registers. */
158bc065 2970 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef 2971 if (err)
08a01261 2972 return err;
158bc065 2973 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef 2974 if (err)
08a01261 2975 return err;
158bc065 2976 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef 2977 if (err)
08a01261 2978 return err;
158bc065 2979 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef 2980 if (err)
08a01261 2981 return err;
158bc065 2982 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef 2983 if (err)
08a01261 2984 return err;
158bc065 2985 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef 2986 if (err)
08a01261 2987 return err;
158bc065 2988 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef 2989 if (err)
08a01261 2990 return err;
158bc065 2991 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef 2992 if (err)
08a01261 2993 return err;
54d792f2
AL		 2994
2995 /* Configure the IEEE 802.1p priority mapping register. */
158bc065 2996 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef 2997 if (err)
08a01261 2998 return err;
54d792f2
AL		 2999
3000 /* Send all frames with destination addresses matching
3001 * 01:80:c2:00:00:0x to the CPU port.
3002 */
158bc065 3003 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
48ace4ef 3004 if (err)
08a01261 3005 return err;
54d792f2
AL		 3006
3007 /* Ignore removed tag data on doubly tagged packets, disable
3008 * flow control messages, force flow control priority to the
3009 * highest, and send all special multicast frames to the CPU
3010 * port at the highest priority.
3011 */
158bc065 3012 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
48ace4ef
AL		 3013 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
3014 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
3015 if (err)
08a01261 3016 return err;
54d792f2
AL		 3017
3018 /* Program the DSA routing table. */
3019 for (i = 0; i < 32; i++) {
3020 int nexthop = 0x1f;
3021
08a01261
VD		 3022 if (ps->ds->pd->rtable &&
3023 i != ps->ds->index && i < ps->ds->dst->pd->nr_chips)
3024 nexthop = ps->ds->pd->rtable[i] & 0x1f;
54d792f2 3025
48ace4ef 3026 err = _mv88e6xxx_reg_write(
158bc065 3027 ps, REG_GLOBAL2,
48ace4ef
AL		 3028 GLOBAL2_DEVICE_MAPPING,
3029 GLOBAL2_DEVICE_MAPPING_UPDATE |
3030 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
3031 if (err)
08a01261 3032 return err;
54d792f2
AL		 3033 }
3034
3035 /* Clear all trunk masks. */
48ace4ef 3036 for (i = 0; i < 8; i++) {
158bc065 3037 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
48ace4ef
AL		 3038 0x8000 |
3039 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
009a2b98 3040 ((1 << ps->info->num_ports) - 1));
48ace4ef 3041 if (err)
08a01261 3042 return err;
48ace4ef 3043 }
54d792f2
AL		 3044
3045 /* Clear all trunk mappings. */
48ace4ef
AL		 3046 for (i = 0; i < 16; i++) {
3047 err = _mv88e6xxx_reg_write(
158bc065 3048 ps, REG_GLOBAL2,
48ace4ef
AL		 3049 GLOBAL2_TRUNK_MAPPING,
3050 GLOBAL2_TRUNK_MAPPING_UPDATE |
3051 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
3052 if (err)
08a01261 3053 return err;
48ace4ef 3054 }
54d792f2 3055
158bc065
AL		 3056 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3057 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3058 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 3059 /* Send all frames with destination addresses matching
3060 * 01:80:c2:00:00:2x to the CPU port.
3061 */
158bc065 3062 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 3063 GLOBAL2_MGMT_EN_2X, 0xffff);
3064 if (err)
08a01261 3065 return err;
54d792f2
AL		 3066
3067 /* Initialise cross-chip port VLAN table to reset
3068 * defaults.
3069 */
158bc065 3070 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 3071 GLOBAL2_PVT_ADDR, 0x9000);
3072 if (err)
08a01261 3073 return err;
54d792f2
AL		 3074
3075 /* Clear the priority override table. */
48ace4ef 3076 for (i = 0; i < 16; i++) {
158bc065 3077 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 3078 GLOBAL2_PRIO_OVERRIDE,
3079 0x8000 | (i << 8));
3080 if (err)
08a01261 3081 return err;
48ace4ef 3082 }
54d792f2
AL		 3083 }
3084
158bc065
AL		 3085 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3086 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3087 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
3088 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 3089 /* Disable ingress rate limiting by resetting all
3090 * ingress rate limit registers to their initial
3091 * state.
3092 */
009a2b98 3093 for (i = 0; i < ps->info->num_ports; i++) {
158bc065 3094 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 3095 GLOBAL2_INGRESS_OP,
3096 0x9000 | (i << 8));
3097 if (err)
08a01261 3098 return err;
48ace4ef 3099 }
54d792f2
AL		 3100 }
3101
db687a56 3102 /* Clear the statistics counters for all ports */
158bc065 3103 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
48ace4ef
AL		 3104 GLOBAL_STATS_OP_FLUSH_ALL);
3105 if (err)
08a01261 3106 return err;
db687a56
AL		 3107
3108 /* Wait for the flush to complete. */
158bc065 3109 err = _mv88e6xxx_stats_wait(ps);
08a01261
VD		 3110 if (err)
3111 return err;
6b17e864 3112
c161d0a5 3113 /* Clear all ATU entries */
158bc065 3114 err = _mv88e6xxx_atu_flush(ps, 0, true);
08a01261
VD		 3115 if (err)
3116 return err;
c161d0a5 3117
6b17e864 3118 /* Clear all the VTU and STU entries */
158bc065 3119 err = _mv88e6xxx_vtu_stu_flush(ps);
08a01261
VD		 3120 if (err < 0)
3121 return err;
3122
3123 return err;
3124}
3125
3126int mv88e6xxx_setup_common(struct mv88e6xxx_priv_state *ps)
3127{
3128 int err;
3129
3130 mutex_init(&ps->smi_mutex);
3131
3132 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
3133
3134 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
3135 mutex_init(&ps->eeprom_mutex);
3136
3137 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3138 mv88e6xxx_ppu_state_init(ps);
3139
3140 mutex_lock(&ps->smi_mutex);
3141
3142 err = mv88e6xxx_switch_reset(ps);
3143 if (err)
3144 goto unlock;
3145
3146 err = mv88e6xxx_setup_global(ps);
3147
6b17e864 3148unlock:
24751e29 3149 mutex_unlock(&ps->smi_mutex);
db687a56 3150
48ace4ef 3151 return err;
54d792f2
AL		 3152}
3153
49143585
AL		 3154int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
3155{
3156 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3157 int ret;
3158
3898c148 3159 mutex_lock(&ps->smi_mutex);
158bc065 3160 ret = _mv88e6xxx_phy_page_read(ps, port, page, reg);
3898c148 3161 mutex_unlock(&ps->smi_mutex);
75baacf0 3162
49143585
AL		 3163 return ret;
3164}
3165
3166int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
3167 int reg, int val)
3168{
3169 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3170 int ret;
3171
3898c148 3172 mutex_lock(&ps->smi_mutex);
158bc065 3173 ret = _mv88e6xxx_phy_page_write(ps, port, page, reg, val);
3898c148 3174 mutex_unlock(&ps->smi_mutex);
75baacf0 3175
fd3a0ee4
AL		 3176 return ret;
3177}
3178
158bc065
AL		 3179static int mv88e6xxx_port_to_phy_addr(struct mv88e6xxx_priv_state *ps,
3180 int port)
fd3a0ee4 3181{
009a2b98 3182 if (port >= 0 && port < ps->info->num_ports)
fd3a0ee4
AL		 3183 return port;
3184 return -EINVAL;
3185}
3186
3187int
3188mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
3189{
3190 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158bc065 3191 int addr = mv88e6xxx_port_to_phy_addr(ps, port);
fd3a0ee4
AL		 3192 int ret;
3193
3194 if (addr < 0)
158bc065 3195 return 0xffff;
fd3a0ee4 3196
3898c148 3197 mutex_lock(&ps->smi_mutex);
8c9983a2
VD		 3198
3199 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3200 ret = mv88e6xxx_phy_read_ppu(ps, addr, regnum);
6d5834a1
VD		 3201 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3202 ret = _mv88e6xxx_phy_read_indirect(ps, addr, regnum);
8c9983a2
VD		 3203 else
3204 ret = _mv88e6xxx_phy_read(ps, addr, regnum);
3205
3898c148 3206 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 3207 return ret;
3208}
3209
3210int
3211mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
3212{
3213 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158bc065 3214 int addr = mv88e6xxx_port_to_phy_addr(ps, port);
fd3a0ee4
AL		 3215 int ret;
3216
3217 if (addr < 0)
158bc065 3218 return 0xffff;
fd3a0ee4 3219
3898c148 3220 mutex_lock(&ps->smi_mutex);
8c9983a2
VD		 3221
3222 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3223 ret = mv88e6xxx_phy_write_ppu(ps, addr, regnum, val);
6d5834a1
VD		 3224 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3225 ret = _mv88e6xxx_phy_write_indirect(ps, addr, regnum, val);
8c9983a2
VD		 3226 else
3227 ret = _mv88e6xxx_phy_write(ps, addr, regnum, val);
3228
3898c148 3229 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 3230 return ret;
3231}
3232
c22995c5
GR		 3233#ifdef CONFIG_NET_DSA_HWMON
3234
3235static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3236{
3237 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3238 int ret;
3239 int val;
3240
3241 *temp = 0;
3242
3243 mutex_lock(&ps->smi_mutex);
3244
158bc065 3245 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x6);
c22995c5
GR		 3246 if (ret < 0)
3247 goto error;
3248
3249 /* Enable temperature sensor */
158bc065 3250 ret = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
c22995c5
GR		 3251 if (ret < 0)
3252 goto error;
3253
158bc065 3254 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret | (1 << 5));
c22995c5
GR		 3255 if (ret < 0)
3256 goto error;
3257
3258 /* Wait for temperature to stabilize */
3259 usleep_range(10000, 12000);
3260
158bc065 3261 val = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
c22995c5
GR		 3262 if (val < 0) {
3263 ret = val;
3264 goto error;
3265 }
3266
3267 /* Disable temperature sensor */
158bc065 3268 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret & ~(1 << 5));
c22995c5
GR		 3269 if (ret < 0)
3270 goto error;
3271
3272 *temp = ((val & 0x1f) - 5) * 5;
3273
3274error:
158bc065 3275 _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x0);
c22995c5
GR		 3276 mutex_unlock(&ps->smi_mutex);
3277 return ret;
3278}
3279
3280static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3281{
158bc065
AL		 3282 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3283 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3284 int ret;
3285
3286 *temp = 0;
3287
3288 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3289 if (ret < 0)
3290 return ret;
3291
3292 *temp = (ret & 0xff) - 25;
3293
3294 return 0;
3295}
3296
3297int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3298{
158bc065
AL		 3299 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3300
6594f615
VD		 3301 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP))
3302 return -EOPNOTSUPP;
3303
158bc065 3304 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
c22995c5
GR		 3305 return mv88e63xx_get_temp(ds, temp);
3306
3307 return mv88e61xx_get_temp(ds, temp);
3308}
3309
3310int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3311{
158bc065
AL		 3312 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3313 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3314 int ret;
3315
6594f615 3316 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3317 return -EOPNOTSUPP;
3318
3319 *temp = 0;
3320
3321 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3322 if (ret < 0)
3323 return ret;
3324
3325 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3326
3327 return 0;
3328}
3329
3330int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3331{
158bc065
AL		 3332 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3333 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3334 int ret;
3335
6594f615 3336 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3337 return -EOPNOTSUPP;
3338
3339 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3340 if (ret < 0)
3341 return ret;
3342 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3343 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3344 (ret & 0xe0ff) | (temp << 8));
3345}
3346
3347int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3348{
158bc065
AL		 3349 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3350 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3351 int ret;
3352
6594f615 3353 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3354 return -EOPNOTSUPP;
3355
3356 *alarm = false;
3357
3358 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3359 if (ret < 0)
3360 return ret;
3361
3362 *alarm = !!(ret & 0x40);
3363
3364 return 0;
3365}
3366#endif /* CONFIG_NET_DSA_HWMON */
3367
f6271e67
VD		 3368static const struct mv88e6xxx_info *
3369mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table,
0209d144 3370 unsigned int num)
b9b37713 3371{
a439c061 3372 int i;
b9b37713 3373
b9b37713 3374 for (i = 0; i < num; ++i)
f6271e67
VD		 3375 if (table[i].prod_num == prod_num)
3376 return &table[i];
b9b37713 3377
b9b37713
VD		 3378 return NULL;
3379}
3380
0209d144
VD		 3381const char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev,
3382 int sw_addr, void **priv,
f6271e67 3383 const struct mv88e6xxx_info *table,
0209d144 3384 unsigned int num)
a77d43f1 3385{
f6271e67 3386 const struct mv88e6xxx_info *info;
a77d43f1 3387 struct mv88e6xxx_priv_state *ps;
a439c061 3388 struct mii_bus *bus;
0209d144 3389 const char *name;
a439c061 3390 int id, prod_num, rev;
a77d43f1 3391
a439c061 3392 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3393 if (!bus)
3394 return NULL;
3395
a439c061
VD		 3396 id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3397 if (id < 0)
3398 return NULL;
3399
3400 prod_num = (id & 0xfff0) >> 4;
3401 rev = id & 0x000f;
3402
f6271e67
VD		 3403 info = mv88e6xxx_lookup_info(prod_num, table, num);
3404 if (!info)
a439c061
VD		 3405 return NULL;
3406
f6271e67
VD		 3407 name = info->name;
3408
a439c061
VD		 3409 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3410 if (!ps)
3411 return NULL;
3412
3413 ps->bus = bus;
3414 ps->sw_addr = sw_addr;
f6271e67 3415 ps->info = info;
a439c061
VD		 3416
3417 *priv = ps;
3418
3419 dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3420 prod_num, name, rev);
3421
a77d43f1
AL		 3422 return name;
3423}
3424
98e67308
BH		 3425static int __init mv88e6xxx_init(void)
3426{
3427#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3428 register_switch_driver(&mv88e6131_switch_driver);
3429#endif
ca3dfa51
AL		 3430#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3431 register_switch_driver(&mv88e6123_switch_driver);
42f27253 3432#endif
3ad50cca
GR		 3433#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3434 register_switch_driver(&mv88e6352_switch_driver);
3435#endif
42f27253
AL		 3436#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3437 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 3438#endif
3439 return 0;
3440}
3441module_init(mv88e6xxx_init);
3442
3443static void __exit mv88e6xxx_cleanup(void)
3444{
42f27253
AL		 3445#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3446 unregister_switch_driver(&mv88e6171_switch_driver);
3447#endif
4212b543
VD		 3448#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3449 unregister_switch_driver(&mv88e6352_switch_driver);
3450#endif
ca3dfa51
AL		 3451#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3452 unregister_switch_driver(&mv88e6123_switch_driver);
98e67308
BH		 3453#endif
3454#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3455 unregister_switch_driver(&mv88e6131_switch_driver);
3456#endif
3457}
3458module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3459
3460MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3461MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3462MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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