Commit | Line | Data |
---|---|---|
91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support | |
3 | * Copyright (c) 2008 Marvell Semiconductor | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
19b2f97e | 11 | #include <linux/delay.h> |
defb05b9 | 12 | #include <linux/etherdevice.h> |
facd95b2 | 13 | #include <linux/if_bridge.h> |
19b2f97e | 14 | #include <linux/jiffies.h> |
91da11f8 | 15 | #include <linux/list.h> |
2bbba277 | 16 | #include <linux/module.h> |
91da11f8 LB |
17 | #include <linux/netdevice.h> |
18 | #include <linux/phy.h> | |
c8f0b869 | 19 | #include <net/dsa.h> |
91da11f8 LB |
20 | #include "mv88e6xxx.h" |
21 | ||
3675c8d7 | 22 | /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will |
91da11f8 LB |
23 | * use all 32 SMI bus addresses on its SMI bus, and all switch registers |
24 | * will be directly accessible on some {device address,register address} | |
25 | * pair. If the ADDR[4:0] pins are not strapped to zero, the switch | |
26 | * will only respond to SMI transactions to that specific address, and | |
27 | * an indirect addressing mechanism needs to be used to access its | |
28 | * registers. | |
29 | */ | |
30 | static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr) | |
31 | { | |
32 | int ret; | |
33 | int i; | |
34 | ||
35 | for (i = 0; i < 16; i++) { | |
cca8b133 | 36 | ret = mdiobus_read(bus, sw_addr, SMI_CMD); |
91da11f8 LB |
37 | if (ret < 0) |
38 | return ret; | |
39 | ||
cca8b133 | 40 | if ((ret & SMI_CMD_BUSY) == 0) |
91da11f8 LB |
41 | return 0; |
42 | } | |
43 | ||
44 | return -ETIMEDOUT; | |
45 | } | |
46 | ||
47 | int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg) | |
48 | { | |
49 | int ret; | |
50 | ||
51 | if (sw_addr == 0) | |
52 | return mdiobus_read(bus, addr, reg); | |
53 | ||
3675c8d7 | 54 | /* Wait for the bus to become free. */ |
91da11f8 LB |
55 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
56 | if (ret < 0) | |
57 | return ret; | |
58 | ||
3675c8d7 | 59 | /* Transmit the read command. */ |
cca8b133 AL |
60 | ret = mdiobus_write(bus, sw_addr, SMI_CMD, |
61 | SMI_CMD_OP_22_READ | (addr << 5) | reg); | |
91da11f8 LB |
62 | if (ret < 0) |
63 | return ret; | |
64 | ||
3675c8d7 | 65 | /* Wait for the read command to complete. */ |
91da11f8 LB |
66 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
67 | if (ret < 0) | |
68 | return ret; | |
69 | ||
3675c8d7 | 70 | /* Read the data. */ |
cca8b133 | 71 | ret = mdiobus_read(bus, sw_addr, SMI_DATA); |
91da11f8 LB |
72 | if (ret < 0) |
73 | return ret; | |
74 | ||
75 | return ret & 0xffff; | |
76 | } | |
77 | ||
8d6d09e7 GR |
78 | /* Must be called with SMI mutex held */ |
79 | static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) | |
91da11f8 | 80 | { |
b184e497 | 81 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 LB |
82 | int ret; |
83 | ||
b184e497 GR |
84 | if (bus == NULL) |
85 | return -EINVAL; | |
86 | ||
b184e497 | 87 | ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg); |
bb92ea5e VD |
88 | if (ret < 0) |
89 | return ret; | |
90 | ||
91 | dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", | |
92 | addr, reg, ret); | |
93 | ||
91da11f8 LB |
94 | return ret; |
95 | } | |
96 | ||
8d6d09e7 GR |
97 | int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg) |
98 | { | |
99 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
100 | int ret; | |
101 | ||
102 | mutex_lock(&ps->smi_mutex); | |
103 | ret = _mv88e6xxx_reg_read(ds, addr, reg); | |
104 | mutex_unlock(&ps->smi_mutex); | |
105 | ||
106 | return ret; | |
107 | } | |
108 | ||
91da11f8 LB |
109 | int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr, |
110 | int reg, u16 val) | |
111 | { | |
112 | int ret; | |
113 | ||
114 | if (sw_addr == 0) | |
115 | return mdiobus_write(bus, addr, reg, val); | |
116 | ||
3675c8d7 | 117 | /* Wait for the bus to become free. */ |
91da11f8 LB |
118 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
119 | if (ret < 0) | |
120 | return ret; | |
121 | ||
3675c8d7 | 122 | /* Transmit the data to write. */ |
cca8b133 | 123 | ret = mdiobus_write(bus, sw_addr, SMI_DATA, val); |
91da11f8 LB |
124 | if (ret < 0) |
125 | return ret; | |
126 | ||
3675c8d7 | 127 | /* Transmit the write command. */ |
cca8b133 AL |
128 | ret = mdiobus_write(bus, sw_addr, SMI_CMD, |
129 | SMI_CMD_OP_22_WRITE | (addr << 5) | reg); | |
91da11f8 LB |
130 | if (ret < 0) |
131 | return ret; | |
132 | ||
3675c8d7 | 133 | /* Wait for the write command to complete. */ |
91da11f8 LB |
134 | ret = mv88e6xxx_reg_wait_ready(bus, sw_addr); |
135 | if (ret < 0) | |
136 | return ret; | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
8d6d09e7 GR |
141 | /* Must be called with SMI mutex held */ |
142 | static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, | |
143 | u16 val) | |
91da11f8 | 144 | { |
b184e497 | 145 | struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev); |
91da11f8 | 146 | |
b184e497 GR |
147 | if (bus == NULL) |
148 | return -EINVAL; | |
149 | ||
bb92ea5e VD |
150 | dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", |
151 | addr, reg, val); | |
152 | ||
8d6d09e7 GR |
153 | return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val); |
154 | } | |
155 | ||
156 | int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val) | |
157 | { | |
158 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
159 | int ret; | |
160 | ||
91da11f8 | 161 | mutex_lock(&ps->smi_mutex); |
8d6d09e7 | 162 | ret = _mv88e6xxx_reg_write(ds, addr, reg, val); |
91da11f8 LB |
163 | mutex_unlock(&ps->smi_mutex); |
164 | ||
165 | return ret; | |
166 | } | |
167 | ||
168 | int mv88e6xxx_config_prio(struct dsa_switch *ds) | |
169 | { | |
3675c8d7 | 170 | /* Configure the IP ToS mapping registers. */ |
cca8b133 AL |
171 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); |
172 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); | |
173 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); | |
174 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); | |
175 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); | |
176 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); | |
177 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); | |
178 | REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); | |
91da11f8 | 179 | |
3675c8d7 | 180 | /* Configure the IEEE 802.1p priority mapping register. */ |
cca8b133 | 181 | REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); |
91da11f8 LB |
182 | |
183 | return 0; | |
184 | } | |
185 | ||
2e5f0320 LB |
186 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) |
187 | { | |
cca8b133 AL |
188 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); |
189 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); | |
190 | REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); | |
2e5f0320 LB |
191 | |
192 | return 0; | |
193 | } | |
194 | ||
91da11f8 LB |
195 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) |
196 | { | |
197 | int i; | |
198 | int ret; | |
199 | ||
200 | for (i = 0; i < 6; i++) { | |
201 | int j; | |
202 | ||
3675c8d7 | 203 | /* Write the MAC address byte. */ |
cca8b133 AL |
204 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC, |
205 | GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]); | |
91da11f8 | 206 | |
3675c8d7 | 207 | /* Wait for the write to complete. */ |
91da11f8 | 208 | for (j = 0; j < 16; j++) { |
cca8b133 AL |
209 | ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); |
210 | if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0) | |
91da11f8 LB |
211 | break; |
212 | } | |
213 | if (j == 16) | |
214 | return -ETIMEDOUT; | |
215 | } | |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
fd3a0ee4 AL |
220 | /* Must be called with phy mutex held */ |
221 | static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum) | |
91da11f8 LB |
222 | { |
223 | if (addr >= 0) | |
224 | return mv88e6xxx_reg_read(ds, addr, regnum); | |
225 | return 0xffff; | |
226 | } | |
227 | ||
fd3a0ee4 AL |
228 | /* Must be called with phy mutex held */ |
229 | static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, | |
230 | u16 val) | |
91da11f8 LB |
231 | { |
232 | if (addr >= 0) | |
233 | return mv88e6xxx_reg_write(ds, addr, regnum, val); | |
234 | return 0; | |
235 | } | |
236 | ||
2e5f0320 LB |
237 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
238 | static int mv88e6xxx_ppu_disable(struct dsa_switch *ds) | |
239 | { | |
240 | int ret; | |
19b2f97e | 241 | unsigned long timeout; |
2e5f0320 | 242 | |
cca8b133 AL |
243 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
244 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, | |
245 | ret & ~GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 246 | |
19b2f97e BG |
247 | timeout = jiffies + 1 * HZ; |
248 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 249 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 250 | usleep_range(1000, 2000); |
cca8b133 AL |
251 | if ((ret & GLOBAL_STATUS_PPU_MASK) != |
252 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 253 | return 0; |
2e5f0320 LB |
254 | } |
255 | ||
256 | return -ETIMEDOUT; | |
257 | } | |
258 | ||
259 | static int mv88e6xxx_ppu_enable(struct dsa_switch *ds) | |
260 | { | |
261 | int ret; | |
19b2f97e | 262 | unsigned long timeout; |
2e5f0320 | 263 | |
cca8b133 AL |
264 | ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); |
265 | REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE); | |
2e5f0320 | 266 | |
19b2f97e BG |
267 | timeout = jiffies + 1 * HZ; |
268 | while (time_before(jiffies, timeout)) { | |
cca8b133 | 269 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); |
19b2f97e | 270 | usleep_range(1000, 2000); |
cca8b133 AL |
271 | if ((ret & GLOBAL_STATUS_PPU_MASK) == |
272 | GLOBAL_STATUS_PPU_POLLING) | |
85686581 | 273 | return 0; |
2e5f0320 LB |
274 | } |
275 | ||
276 | return -ETIMEDOUT; | |
277 | } | |
278 | ||
279 | static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) | |
280 | { | |
281 | struct mv88e6xxx_priv_state *ps; | |
282 | ||
283 | ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); | |
284 | if (mutex_trylock(&ps->ppu_mutex)) { | |
85686581 | 285 | struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1; |
2e5f0320 | 286 | |
85686581 BG |
287 | if (mv88e6xxx_ppu_enable(ds) == 0) |
288 | ps->ppu_disabled = 0; | |
289 | mutex_unlock(&ps->ppu_mutex); | |
2e5f0320 LB |
290 | } |
291 | } | |
292 | ||
293 | static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) | |
294 | { | |
295 | struct mv88e6xxx_priv_state *ps = (void *)_ps; | |
296 | ||
297 | schedule_work(&ps->ppu_work); | |
298 | } | |
299 | ||
300 | static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds) | |
301 | { | |
a22adce5 | 302 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
303 | int ret; |
304 | ||
305 | mutex_lock(&ps->ppu_mutex); | |
306 | ||
3675c8d7 | 307 | /* If the PHY polling unit is enabled, disable it so that |
2e5f0320 LB |
308 | * we can access the PHY registers. If it was already |
309 | * disabled, cancel the timer that is going to re-enable | |
310 | * it. | |
311 | */ | |
312 | if (!ps->ppu_disabled) { | |
85686581 BG |
313 | ret = mv88e6xxx_ppu_disable(ds); |
314 | if (ret < 0) { | |
315 | mutex_unlock(&ps->ppu_mutex); | |
316 | return ret; | |
317 | } | |
318 | ps->ppu_disabled = 1; | |
2e5f0320 | 319 | } else { |
85686581 BG |
320 | del_timer(&ps->ppu_timer); |
321 | ret = 0; | |
2e5f0320 LB |
322 | } |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
327 | static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds) | |
328 | { | |
a22adce5 | 329 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 | 330 | |
3675c8d7 | 331 | /* Schedule a timer to re-enable the PHY polling unit. */ |
2e5f0320 LB |
332 | mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); |
333 | mutex_unlock(&ps->ppu_mutex); | |
334 | } | |
335 | ||
336 | void mv88e6xxx_ppu_state_init(struct dsa_switch *ds) | |
337 | { | |
a22adce5 | 338 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
2e5f0320 LB |
339 | |
340 | mutex_init(&ps->ppu_mutex); | |
341 | INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); | |
342 | init_timer(&ps->ppu_timer); | |
343 | ps->ppu_timer.data = (unsigned long)ps; | |
344 | ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; | |
345 | } | |
346 | ||
347 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum) | |
348 | { | |
349 | int ret; | |
350 | ||
351 | ret = mv88e6xxx_ppu_access_get(ds); | |
352 | if (ret >= 0) { | |
85686581 BG |
353 | ret = mv88e6xxx_reg_read(ds, addr, regnum); |
354 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
355 | } |
356 | ||
357 | return ret; | |
358 | } | |
359 | ||
360 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
361 | int regnum, u16 val) | |
362 | { | |
363 | int ret; | |
364 | ||
365 | ret = mv88e6xxx_ppu_access_get(ds); | |
366 | if (ret >= 0) { | |
85686581 BG |
367 | ret = mv88e6xxx_reg_write(ds, addr, regnum, val); |
368 | mv88e6xxx_ppu_access_put(ds); | |
2e5f0320 LB |
369 | } |
370 | ||
371 | return ret; | |
372 | } | |
373 | #endif | |
374 | ||
91da11f8 LB |
375 | void mv88e6xxx_poll_link(struct dsa_switch *ds) |
376 | { | |
377 | int i; | |
378 | ||
379 | for (i = 0; i < DSA_MAX_PORTS; i++) { | |
380 | struct net_device *dev; | |
2a9e7978 | 381 | int uninitialized_var(port_status); |
91da11f8 LB |
382 | int link; |
383 | int speed; | |
384 | int duplex; | |
385 | int fc; | |
386 | ||
387 | dev = ds->ports[i]; | |
388 | if (dev == NULL) | |
389 | continue; | |
390 | ||
391 | link = 0; | |
392 | if (dev->flags & IFF_UP) { | |
cca8b133 AL |
393 | port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), |
394 | PORT_STATUS); | |
91da11f8 LB |
395 | if (port_status < 0) |
396 | continue; | |
397 | ||
cca8b133 | 398 | link = !!(port_status & PORT_STATUS_LINK); |
91da11f8 LB |
399 | } |
400 | ||
401 | if (!link) { | |
402 | if (netif_carrier_ok(dev)) { | |
ab381a93 | 403 | netdev_info(dev, "link down\n"); |
91da11f8 LB |
404 | netif_carrier_off(dev); |
405 | } | |
406 | continue; | |
407 | } | |
408 | ||
cca8b133 AL |
409 | switch (port_status & PORT_STATUS_SPEED_MASK) { |
410 | case PORT_STATUS_SPEED_10: | |
91da11f8 LB |
411 | speed = 10; |
412 | break; | |
cca8b133 | 413 | case PORT_STATUS_SPEED_100: |
91da11f8 LB |
414 | speed = 100; |
415 | break; | |
cca8b133 | 416 | case PORT_STATUS_SPEED_1000: |
91da11f8 LB |
417 | speed = 1000; |
418 | break; | |
419 | default: | |
420 | speed = -1; | |
421 | break; | |
422 | } | |
cca8b133 AL |
423 | duplex = (port_status & PORT_STATUS_DUPLEX) ? 1 : 0; |
424 | fc = (port_status & PORT_STATUS_PAUSE_EN) ? 1 : 0; | |
91da11f8 LB |
425 | |
426 | if (!netif_carrier_ok(dev)) { | |
ab381a93 BG |
427 | netdev_info(dev, |
428 | "link up, %d Mb/s, %s duplex, flow control %sabled\n", | |
429 | speed, | |
430 | duplex ? "full" : "half", | |
431 | fc ? "en" : "dis"); | |
91da11f8 LB |
432 | netif_carrier_on(dev); |
433 | } | |
434 | } | |
435 | } | |
436 | ||
f3a8b6b6 AL |
437 | static bool mv88e6xxx_6352_family(struct dsa_switch *ds) |
438 | { | |
439 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
440 | ||
441 | switch (ps->id) { | |
442 | case PORT_SWITCH_ID_6352: | |
443 | case PORT_SWITCH_ID_6172: | |
444 | case PORT_SWITCH_ID_6176: | |
445 | return true; | |
446 | } | |
447 | return false; | |
448 | } | |
449 | ||
91da11f8 LB |
450 | static int mv88e6xxx_stats_wait(struct dsa_switch *ds) |
451 | { | |
452 | int ret; | |
453 | int i; | |
454 | ||
455 | for (i = 0; i < 10; i++) { | |
cca8b133 AL |
456 | ret = REG_READ(REG_GLOBAL, GLOBAL_STATS_OP); |
457 | if ((ret & GLOBAL_STATS_OP_BUSY) == 0) | |
91da11f8 LB |
458 | return 0; |
459 | } | |
460 | ||
461 | return -ETIMEDOUT; | |
462 | } | |
463 | ||
464 | static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port) | |
465 | { | |
466 | int ret; | |
467 | ||
f3a8b6b6 AL |
468 | if (mv88e6xxx_6352_family(ds)) |
469 | port = (port + 1) << 5; | |
470 | ||
3675c8d7 | 471 | /* Snapshot the hardware statistics counters for this port. */ |
cca8b133 AL |
472 | REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, |
473 | GLOBAL_STATS_OP_CAPTURE_PORT | | |
474 | GLOBAL_STATS_OP_HIST_RX_TX | port); | |
91da11f8 | 475 | |
3675c8d7 | 476 | /* Wait for the snapshotting to complete. */ |
91da11f8 LB |
477 | ret = mv88e6xxx_stats_wait(ds); |
478 | if (ret < 0) | |
479 | return ret; | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val) | |
485 | { | |
486 | u32 _val; | |
487 | int ret; | |
488 | ||
489 | *val = 0; | |
490 | ||
cca8b133 AL |
491 | ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP, |
492 | GLOBAL_STATS_OP_READ_CAPTURED | | |
493 | GLOBAL_STATS_OP_HIST_RX_TX | stat); | |
91da11f8 LB |
494 | if (ret < 0) |
495 | return; | |
496 | ||
497 | ret = mv88e6xxx_stats_wait(ds); | |
498 | if (ret < 0) | |
499 | return; | |
500 | ||
cca8b133 | 501 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); |
91da11f8 LB |
502 | if (ret < 0) |
503 | return; | |
504 | ||
505 | _val = ret << 16; | |
506 | ||
cca8b133 | 507 | ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); |
91da11f8 LB |
508 | if (ret < 0) |
509 | return; | |
510 | ||
511 | *val = _val | ret; | |
512 | } | |
513 | ||
e413e7e1 AL |
514 | static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { |
515 | { "in_good_octets", 8, 0x00, }, | |
516 | { "in_bad_octets", 4, 0x02, }, | |
517 | { "in_unicast", 4, 0x04, }, | |
518 | { "in_broadcasts", 4, 0x06, }, | |
519 | { "in_multicasts", 4, 0x07, }, | |
520 | { "in_pause", 4, 0x16, }, | |
521 | { "in_undersize", 4, 0x18, }, | |
522 | { "in_fragments", 4, 0x19, }, | |
523 | { "in_oversize", 4, 0x1a, }, | |
524 | { "in_jabber", 4, 0x1b, }, | |
525 | { "in_rx_error", 4, 0x1c, }, | |
526 | { "in_fcs_error", 4, 0x1d, }, | |
527 | { "out_octets", 8, 0x0e, }, | |
528 | { "out_unicast", 4, 0x10, }, | |
529 | { "out_broadcasts", 4, 0x13, }, | |
530 | { "out_multicasts", 4, 0x12, }, | |
531 | { "out_pause", 4, 0x15, }, | |
532 | { "excessive", 4, 0x11, }, | |
533 | { "collisions", 4, 0x1e, }, | |
534 | { "deferred", 4, 0x05, }, | |
535 | { "single", 4, 0x14, }, | |
536 | { "multiple", 4, 0x17, }, | |
537 | { "out_fcs_error", 4, 0x03, }, | |
538 | { "late", 4, 0x1f, }, | |
539 | { "hist_64bytes", 4, 0x08, }, | |
540 | { "hist_65_127bytes", 4, 0x09, }, | |
541 | { "hist_128_255bytes", 4, 0x0a, }, | |
542 | { "hist_256_511bytes", 4, 0x0b, }, | |
543 | { "hist_512_1023bytes", 4, 0x0c, }, | |
544 | { "hist_1024_max_bytes", 4, 0x0d, }, | |
545 | /* Not all devices have the following counters */ | |
546 | { "sw_in_discards", 4, 0x110, }, | |
547 | { "sw_in_filtered", 2, 0x112, }, | |
548 | { "sw_out_filtered", 2, 0x113, }, | |
549 | ||
550 | }; | |
551 | ||
552 | static bool have_sw_in_discards(struct dsa_switch *ds) | |
553 | { | |
554 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
555 | ||
556 | switch (ps->id) { | |
cca8b133 AL |
557 | case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161: |
558 | case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171: | |
559 | case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176: | |
560 | case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185: | |
561 | case PORT_SWITCH_ID_6352: | |
e413e7e1 AL |
562 | return true; |
563 | default: | |
564 | return false; | |
565 | } | |
566 | } | |
567 | ||
568 | static void _mv88e6xxx_get_strings(struct dsa_switch *ds, | |
569 | int nr_stats, | |
570 | struct mv88e6xxx_hw_stat *stats, | |
571 | int port, uint8_t *data) | |
91da11f8 LB |
572 | { |
573 | int i; | |
574 | ||
575 | for (i = 0; i < nr_stats; i++) { | |
576 | memcpy(data + i * ETH_GSTRING_LEN, | |
577 | stats[i].string, ETH_GSTRING_LEN); | |
578 | } | |
579 | } | |
580 | ||
e413e7e1 AL |
581 | static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, |
582 | int nr_stats, | |
583 | struct mv88e6xxx_hw_stat *stats, | |
584 | int port, uint64_t *data) | |
91da11f8 | 585 | { |
a22adce5 | 586 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
91da11f8 LB |
587 | int ret; |
588 | int i; | |
589 | ||
590 | mutex_lock(&ps->stats_mutex); | |
591 | ||
592 | ret = mv88e6xxx_stats_snapshot(ds, port); | |
593 | if (ret < 0) { | |
594 | mutex_unlock(&ps->stats_mutex); | |
595 | return; | |
596 | } | |
597 | ||
3675c8d7 | 598 | /* Read each of the counters. */ |
91da11f8 LB |
599 | for (i = 0; i < nr_stats; i++) { |
600 | struct mv88e6xxx_hw_stat *s = stats + i; | |
601 | u32 low; | |
17ee3e04 GR |
602 | u32 high = 0; |
603 | ||
604 | if (s->reg >= 0x100) { | |
17ee3e04 GR |
605 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), |
606 | s->reg - 0x100); | |
607 | if (ret < 0) | |
608 | goto error; | |
609 | low = ret; | |
610 | if (s->sizeof_stat == 4) { | |
611 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), | |
612 | s->reg - 0x100 + 1); | |
613 | if (ret < 0) | |
614 | goto error; | |
615 | high = ret; | |
616 | } | |
617 | data[i] = (((u64)high) << 16) | low; | |
618 | continue; | |
619 | } | |
91da11f8 LB |
620 | mv88e6xxx_stats_read(ds, s->reg, &low); |
621 | if (s->sizeof_stat == 8) | |
622 | mv88e6xxx_stats_read(ds, s->reg + 1, &high); | |
91da11f8 LB |
623 | |
624 | data[i] = (((u64)high) << 32) | low; | |
625 | } | |
17ee3e04 | 626 | error: |
91da11f8 LB |
627 | mutex_unlock(&ps->stats_mutex); |
628 | } | |
98e67308 | 629 | |
e413e7e1 AL |
630 | /* All the statistics in the table */ |
631 | void | |
632 | mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data) | |
633 | { | |
634 | if (have_sw_in_discards(ds)) | |
635 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
636 | mv88e6xxx_hw_stats, port, data); | |
637 | else | |
638 | _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
639 | mv88e6xxx_hw_stats, port, data); | |
640 | } | |
641 | ||
642 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds) | |
643 | { | |
644 | if (have_sw_in_discards(ds)) | |
645 | return ARRAY_SIZE(mv88e6xxx_hw_stats); | |
646 | return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3; | |
647 | } | |
648 | ||
649 | void | |
650 | mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, | |
651 | int port, uint64_t *data) | |
652 | { | |
653 | if (have_sw_in_discards(ds)) | |
654 | _mv88e6xxx_get_ethtool_stats( | |
655 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats), | |
656 | mv88e6xxx_hw_stats, port, data); | |
657 | else | |
658 | _mv88e6xxx_get_ethtool_stats( | |
659 | ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3, | |
660 | mv88e6xxx_hw_stats, port, data); | |
661 | } | |
662 | ||
a1ab91f3 GR |
663 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) |
664 | { | |
665 | return 32 * sizeof(u16); | |
666 | } | |
667 | ||
668 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
669 | struct ethtool_regs *regs, void *_p) | |
670 | { | |
671 | u16 *p = _p; | |
672 | int i; | |
673 | ||
674 | regs->version = 0; | |
675 | ||
676 | memset(p, 0xff, 32 * sizeof(u16)); | |
677 | ||
678 | for (i = 0; i < 32; i++) { | |
679 | int ret; | |
680 | ||
681 | ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i); | |
682 | if (ret >= 0) | |
683 | p[i] = ret; | |
684 | } | |
685 | } | |
686 | ||
eaa23765 AL |
687 | #ifdef CONFIG_NET_DSA_HWMON |
688 | ||
689 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) | |
690 | { | |
691 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
692 | int ret; | |
693 | int val; | |
694 | ||
695 | *temp = 0; | |
696 | ||
697 | mutex_lock(&ps->phy_mutex); | |
698 | ||
fd3a0ee4 | 699 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6); |
eaa23765 AL |
700 | if (ret < 0) |
701 | goto error; | |
702 | ||
703 | /* Enable temperature sensor */ | |
fd3a0ee4 | 704 | ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); |
eaa23765 AL |
705 | if (ret < 0) |
706 | goto error; | |
707 | ||
fd3a0ee4 | 708 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5)); |
eaa23765 AL |
709 | if (ret < 0) |
710 | goto error; | |
711 | ||
712 | /* Wait for temperature to stabilize */ | |
713 | usleep_range(10000, 12000); | |
714 | ||
fd3a0ee4 | 715 | val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a); |
eaa23765 AL |
716 | if (val < 0) { |
717 | ret = val; | |
718 | goto error; | |
719 | } | |
720 | ||
721 | /* Disable temperature sensor */ | |
fd3a0ee4 | 722 | ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5)); |
eaa23765 AL |
723 | if (ret < 0) |
724 | goto error; | |
725 | ||
726 | *temp = ((val & 0x1f) - 5) * 5; | |
727 | ||
728 | error: | |
fd3a0ee4 | 729 | _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0); |
eaa23765 AL |
730 | mutex_unlock(&ps->phy_mutex); |
731 | return ret; | |
732 | } | |
733 | #endif /* CONFIG_NET_DSA_HWMON */ | |
734 | ||
f3044683 AL |
735 | static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) |
736 | { | |
737 | unsigned long timeout = jiffies + HZ / 10; | |
738 | ||
739 | while (time_before(jiffies, timeout)) { | |
740 | int ret; | |
741 | ||
742 | ret = REG_READ(reg, offset); | |
743 | if (!(ret & mask)) | |
744 | return 0; | |
745 | ||
746 | usleep_range(1000, 2000); | |
747 | } | |
748 | return -ETIMEDOUT; | |
749 | } | |
750 | ||
751 | int mv88e6xxx_phy_wait(struct dsa_switch *ds) | |
752 | { | |
cca8b133 AL |
753 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP, |
754 | GLOBAL2_SMI_OP_BUSY); | |
f3044683 AL |
755 | } |
756 | ||
757 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) | |
758 | { | |
cca8b133 AL |
759 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
760 | GLOBAL2_EEPROM_OP_LOAD); | |
f3044683 AL |
761 | } |
762 | ||
763 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) | |
764 | { | |
cca8b133 AL |
765 | return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP, |
766 | GLOBAL2_EEPROM_OP_BUSY); | |
f3044683 AL |
767 | } |
768 | ||
facd95b2 GR |
769 | /* Must be called with SMI lock held */ |
770 | static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask) | |
771 | { | |
772 | unsigned long timeout = jiffies + HZ / 10; | |
773 | ||
774 | while (time_before(jiffies, timeout)) { | |
775 | int ret; | |
776 | ||
777 | ret = _mv88e6xxx_reg_read(ds, reg, offset); | |
778 | if (ret < 0) | |
779 | return ret; | |
780 | if (!(ret & mask)) | |
781 | return 0; | |
782 | ||
783 | usleep_range(1000, 2000); | |
784 | } | |
785 | return -ETIMEDOUT; | |
786 | } | |
787 | ||
788 | /* Must be called with SMI lock held */ | |
789 | static int _mv88e6xxx_atu_wait(struct dsa_switch *ds) | |
790 | { | |
cca8b133 AL |
791 | return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP, |
792 | GLOBAL_ATU_OP_BUSY); | |
facd95b2 GR |
793 | } |
794 | ||
fd3a0ee4 AL |
795 | /* Must be called with phy mutex held */ |
796 | static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, | |
797 | int regnum) | |
f3044683 AL |
798 | { |
799 | int ret; | |
800 | ||
cca8b133 AL |
801 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_OP, |
802 | GLOBAL2_SMI_OP_22_READ | (addr << 5) | regnum); | |
f3044683 AL |
803 | |
804 | ret = mv88e6xxx_phy_wait(ds); | |
805 | if (ret < 0) | |
806 | return ret; | |
807 | ||
cca8b133 | 808 | return REG_READ(REG_GLOBAL2, GLOBAL2_SMI_DATA); |
f3044683 AL |
809 | } |
810 | ||
fd3a0ee4 AL |
811 | /* Must be called with phy mutex held */ |
812 | static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, | |
813 | int regnum, u16 val) | |
f3044683 | 814 | { |
cca8b133 AL |
815 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_DATA, val); |
816 | REG_WRITE(REG_GLOBAL2, GLOBAL2_SMI_OP, | |
817 | GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | regnum); | |
f3044683 AL |
818 | |
819 | return mv88e6xxx_phy_wait(ds); | |
820 | } | |
821 | ||
11b3b45d GR |
822 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e) |
823 | { | |
2f40c698 | 824 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
11b3b45d GR |
825 | int reg; |
826 | ||
2f40c698 AL |
827 | mutex_lock(&ps->phy_mutex); |
828 | ||
829 | reg = _mv88e6xxx_phy_read_indirect(ds, port, 16); | |
11b3b45d | 830 | if (reg < 0) |
2f40c698 | 831 | goto out; |
11b3b45d GR |
832 | |
833 | e->eee_enabled = !!(reg & 0x0200); | |
834 | e->tx_lpi_enabled = !!(reg & 0x0100); | |
835 | ||
cca8b133 | 836 | reg = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS); |
11b3b45d | 837 | if (reg < 0) |
2f40c698 | 838 | goto out; |
11b3b45d | 839 | |
cca8b133 | 840 | e->eee_active = !!(reg & PORT_STATUS_EEE); |
2f40c698 | 841 | reg = 0; |
11b3b45d | 842 | |
2f40c698 AL |
843 | out: |
844 | mutex_unlock(&ps->phy_mutex); | |
845 | return reg; | |
11b3b45d GR |
846 | } |
847 | ||
848 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
849 | struct phy_device *phydev, struct ethtool_eee *e) | |
850 | { | |
2f40c698 AL |
851 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
852 | int reg; | |
11b3b45d GR |
853 | int ret; |
854 | ||
2f40c698 | 855 | mutex_lock(&ps->phy_mutex); |
11b3b45d | 856 | |
2f40c698 AL |
857 | ret = _mv88e6xxx_phy_read_indirect(ds, port, 16); |
858 | if (ret < 0) | |
859 | goto out; | |
860 | ||
861 | reg = ret & ~0x0300; | |
862 | if (e->eee_enabled) | |
863 | reg |= 0x0200; | |
864 | if (e->tx_lpi_enabled) | |
865 | reg |= 0x0100; | |
866 | ||
867 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg); | |
868 | out: | |
869 | mutex_unlock(&ps->phy_mutex); | |
870 | ||
871 | return ret; | |
11b3b45d GR |
872 | } |
873 | ||
facd95b2 GR |
874 | static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, int fid, u16 cmd) |
875 | { | |
876 | int ret; | |
877 | ||
878 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x01, fid); | |
879 | if (ret < 0) | |
880 | return ret; | |
881 | ||
cca8b133 | 882 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd); |
facd95b2 GR |
883 | if (ret < 0) |
884 | return ret; | |
885 | ||
886 | return _mv88e6xxx_atu_wait(ds); | |
887 | } | |
888 | ||
889 | static int _mv88e6xxx_flush_fid(struct dsa_switch *ds, int fid) | |
890 | { | |
891 | int ret; | |
892 | ||
893 | ret = _mv88e6xxx_atu_wait(ds); | |
894 | if (ret < 0) | |
895 | return ret; | |
896 | ||
cca8b133 | 897 | return _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB); |
facd95b2 GR |
898 | } |
899 | ||
900 | static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state) | |
901 | { | |
902 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
c3ffe6d2 | 903 | int reg, ret = 0; |
facd95b2 GR |
904 | u8 oldstate; |
905 | ||
906 | mutex_lock(&ps->smi_mutex); | |
907 | ||
cca8b133 | 908 | reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL); |
538cc282 GR |
909 | if (reg < 0) { |
910 | ret = reg; | |
facd95b2 | 911 | goto abort; |
538cc282 | 912 | } |
facd95b2 | 913 | |
cca8b133 | 914 | oldstate = reg & PORT_CONTROL_STATE_MASK; |
facd95b2 GR |
915 | if (oldstate != state) { |
916 | /* Flush forwarding database if we're moving a port | |
917 | * from Learning or Forwarding state to Disabled or | |
918 | * Blocking or Listening state. | |
919 | */ | |
cca8b133 AL |
920 | if (oldstate >= PORT_CONTROL_STATE_LEARNING && |
921 | state <= PORT_CONTROL_STATE_BLOCKING) { | |
facd95b2 GR |
922 | ret = _mv88e6xxx_flush_fid(ds, ps->fid[port]); |
923 | if (ret) | |
924 | goto abort; | |
925 | } | |
cca8b133 AL |
926 | reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; |
927 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL, | |
928 | reg); | |
facd95b2 GR |
929 | } |
930 | ||
931 | abort: | |
932 | mutex_unlock(&ps->smi_mutex); | |
933 | return ret; | |
934 | } | |
935 | ||
936 | /* Must be called with smi lock held */ | |
937 | static int _mv88e6xxx_update_port_config(struct dsa_switch *ds, int port) | |
938 | { | |
939 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
940 | u8 fid = ps->fid[port]; | |
941 | u16 reg = fid << 12; | |
942 | ||
943 | if (dsa_is_cpu_port(ds, port)) | |
944 | reg |= ds->phys_port_mask; | |
945 | else | |
946 | reg |= (ps->bridge_mask[fid] | | |
947 | (1 << dsa_upstream_port(ds))) & ~(1 << port); | |
948 | ||
cca8b133 | 949 | return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg); |
facd95b2 GR |
950 | } |
951 | ||
952 | /* Must be called with smi lock held */ | |
953 | static int _mv88e6xxx_update_bridge_config(struct dsa_switch *ds, int fid) | |
954 | { | |
955 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
956 | int port; | |
957 | u32 mask; | |
958 | int ret; | |
959 | ||
960 | mask = ds->phys_port_mask; | |
961 | while (mask) { | |
962 | port = __ffs(mask); | |
963 | mask &= ~(1 << port); | |
964 | if (ps->fid[port] != fid) | |
965 | continue; | |
966 | ||
967 | ret = _mv88e6xxx_update_port_config(ds, port); | |
968 | if (ret) | |
969 | return ret; | |
970 | } | |
971 | ||
972 | return _mv88e6xxx_flush_fid(ds, fid); | |
973 | } | |
974 | ||
975 | /* Bridge handling functions */ | |
976 | ||
977 | int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
978 | { | |
979 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
980 | int ret = 0; | |
981 | u32 nmask; | |
982 | int fid; | |
983 | ||
984 | /* If the bridge group is not empty, join that group. | |
985 | * Otherwise create a new group. | |
986 | */ | |
987 | fid = ps->fid[port]; | |
988 | nmask = br_port_mask & ~(1 << port); | |
989 | if (nmask) | |
990 | fid = ps->fid[__ffs(nmask)]; | |
991 | ||
992 | nmask = ps->bridge_mask[fid] | (1 << port); | |
993 | if (nmask != br_port_mask) { | |
994 | netdev_err(ds->ports[port], | |
995 | "join: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
996 | fid, br_port_mask, nmask); | |
997 | return -EINVAL; | |
998 | } | |
999 | ||
1000 | mutex_lock(&ps->smi_mutex); | |
1001 | ||
1002 | ps->bridge_mask[fid] = br_port_mask; | |
1003 | ||
1004 | if (fid != ps->fid[port]) { | |
1005 | ps->fid_mask |= 1 << ps->fid[port]; | |
1006 | ps->fid[port] = fid; | |
1007 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1008 | } | |
1009 | ||
1010 | mutex_unlock(&ps->smi_mutex); | |
1011 | ||
1012 | return ret; | |
1013 | } | |
1014 | ||
1015 | int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask) | |
1016 | { | |
1017 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1018 | u8 fid, newfid; | |
1019 | int ret; | |
1020 | ||
1021 | fid = ps->fid[port]; | |
1022 | ||
1023 | if (ps->bridge_mask[fid] != br_port_mask) { | |
1024 | netdev_err(ds->ports[port], | |
1025 | "leave: Bridge port mask mismatch fid=%d mask=0x%x expected 0x%x\n", | |
1026 | fid, br_port_mask, ps->bridge_mask[fid]); | |
1027 | return -EINVAL; | |
1028 | } | |
1029 | ||
1030 | /* If the port was the last port of a bridge, we are done. | |
1031 | * Otherwise assign a new fid to the port, and fix up | |
1032 | * the bridge configuration. | |
1033 | */ | |
1034 | if (br_port_mask == (1 << port)) | |
1035 | return 0; | |
1036 | ||
1037 | mutex_lock(&ps->smi_mutex); | |
1038 | ||
1039 | newfid = __ffs(ps->fid_mask); | |
1040 | ps->fid[port] = newfid; | |
1041 | ps->fid_mask &= (1 << newfid); | |
1042 | ps->bridge_mask[fid] &= ~(1 << port); | |
1043 | ps->bridge_mask[newfid] = 1 << port; | |
1044 | ||
1045 | ret = _mv88e6xxx_update_bridge_config(ds, fid); | |
1046 | if (!ret) | |
1047 | ret = _mv88e6xxx_update_bridge_config(ds, newfid); | |
1048 | ||
1049 | mutex_unlock(&ps->smi_mutex); | |
1050 | ||
1051 | return ret; | |
1052 | } | |
1053 | ||
1054 | int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state) | |
1055 | { | |
1056 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1057 | int stp_state; | |
1058 | ||
1059 | switch (state) { | |
1060 | case BR_STATE_DISABLED: | |
cca8b133 | 1061 | stp_state = PORT_CONTROL_STATE_DISABLED; |
facd95b2 GR |
1062 | break; |
1063 | case BR_STATE_BLOCKING: | |
1064 | case BR_STATE_LISTENING: | |
cca8b133 | 1065 | stp_state = PORT_CONTROL_STATE_BLOCKING; |
facd95b2 GR |
1066 | break; |
1067 | case BR_STATE_LEARNING: | |
cca8b133 | 1068 | stp_state = PORT_CONTROL_STATE_LEARNING; |
facd95b2 GR |
1069 | break; |
1070 | case BR_STATE_FORWARDING: | |
1071 | default: | |
cca8b133 | 1072 | stp_state = PORT_CONTROL_STATE_FORWARDING; |
facd95b2 GR |
1073 | break; |
1074 | } | |
1075 | ||
1076 | netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state); | |
1077 | ||
1078 | /* mv88e6xxx_port_stp_update may be called with softirqs disabled, | |
1079 | * so we can not update the port state directly but need to schedule it. | |
1080 | */ | |
1081 | ps->port_state[port] = stp_state; | |
1082 | set_bit(port, &ps->port_state_update_mask); | |
1083 | schedule_work(&ps->bridge_work); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
defb05b9 GR |
1088 | static int __mv88e6xxx_write_addr(struct dsa_switch *ds, |
1089 | const unsigned char *addr) | |
1090 | { | |
1091 | int i, ret; | |
1092 | ||
1093 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1094 | ret = _mv88e6xxx_reg_write( |
1095 | ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, | |
1096 | (addr[i * 2] << 8) | addr[i * 2 + 1]); | |
defb05b9 GR |
1097 | if (ret < 0) |
1098 | return ret; | |
1099 | } | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | static int __mv88e6xxx_read_addr(struct dsa_switch *ds, unsigned char *addr) | |
1105 | { | |
1106 | int i, ret; | |
1107 | ||
1108 | for (i = 0; i < 3; i++) { | |
cca8b133 AL |
1109 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, |
1110 | GLOBAL_ATU_MAC_01 + i); | |
defb05b9 GR |
1111 | if (ret < 0) |
1112 | return ret; | |
1113 | addr[i * 2] = ret >> 8; | |
1114 | addr[i * 2 + 1] = ret & 0xff; | |
1115 | } | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | static int __mv88e6xxx_port_fdb_cmd(struct dsa_switch *ds, int port, | |
1121 | const unsigned char *addr, int state) | |
1122 | { | |
1123 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1124 | u8 fid = ps->fid[port]; | |
1125 | int ret; | |
1126 | ||
1127 | ret = _mv88e6xxx_atu_wait(ds); | |
1128 | if (ret < 0) | |
1129 | return ret; | |
1130 | ||
1131 | ret = __mv88e6xxx_write_addr(ds, addr); | |
1132 | if (ret < 0) | |
1133 | return ret; | |
1134 | ||
cca8b133 | 1135 | ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, |
defb05b9 GR |
1136 | (0x10 << port) | state); |
1137 | if (ret) | |
1138 | return ret; | |
1139 | ||
cca8b133 | 1140 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_LOAD_DB); |
defb05b9 GR |
1141 | |
1142 | return ret; | |
1143 | } | |
1144 | ||
1145 | int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, | |
1146 | const unsigned char *addr, u16 vid) | |
1147 | { | |
1148 | int state = is_multicast_ether_addr(addr) ? | |
cca8b133 AL |
1149 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1150 | GLOBAL_ATU_DATA_STATE_UC_STATIC; | |
defb05b9 GR |
1151 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); |
1152 | int ret; | |
1153 | ||
1154 | mutex_lock(&ps->smi_mutex); | |
1155 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, state); | |
1156 | mutex_unlock(&ps->smi_mutex); | |
1157 | ||
1158 | return ret; | |
1159 | } | |
1160 | ||
1161 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, | |
1162 | const unsigned char *addr, u16 vid) | |
1163 | { | |
1164 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1165 | int ret; | |
1166 | ||
1167 | mutex_lock(&ps->smi_mutex); | |
cca8b133 AL |
1168 | ret = __mv88e6xxx_port_fdb_cmd(ds, port, addr, |
1169 | GLOBAL_ATU_DATA_STATE_UNUSED); | |
defb05b9 GR |
1170 | mutex_unlock(&ps->smi_mutex); |
1171 | ||
1172 | return ret; | |
1173 | } | |
1174 | ||
1175 | static int __mv88e6xxx_port_getnext(struct dsa_switch *ds, int port, | |
1176 | unsigned char *addr, bool *is_static) | |
1177 | { | |
1178 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1179 | u8 fid = ps->fid[port]; | |
1180 | int ret, state; | |
1181 | ||
1182 | ret = _mv88e6xxx_atu_wait(ds); | |
1183 | if (ret < 0) | |
1184 | return ret; | |
1185 | ||
1186 | ret = __mv88e6xxx_write_addr(ds, addr); | |
1187 | if (ret < 0) | |
1188 | return ret; | |
1189 | ||
1190 | do { | |
cca8b133 | 1191 | ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB); |
defb05b9 GR |
1192 | if (ret < 0) |
1193 | return ret; | |
1194 | ||
cca8b133 | 1195 | ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA); |
defb05b9 GR |
1196 | if (ret < 0) |
1197 | return ret; | |
cca8b133 AL |
1198 | state = ret & GLOBAL_ATU_DATA_STATE_MASK; |
1199 | if (state == GLOBAL_ATU_DATA_STATE_UNUSED) | |
defb05b9 GR |
1200 | return -ENOENT; |
1201 | } while (!(((ret >> 4) & 0xff) & (1 << port))); | |
1202 | ||
1203 | ret = __mv88e6xxx_read_addr(ds, addr); | |
1204 | if (ret < 0) | |
1205 | return ret; | |
1206 | ||
1207 | *is_static = state == (is_multicast_ether_addr(addr) ? | |
cca8b133 AL |
1208 | GLOBAL_ATU_DATA_STATE_MC_STATIC : |
1209 | GLOBAL_ATU_DATA_STATE_UC_STATIC); | |
defb05b9 GR |
1210 | |
1211 | return 0; | |
1212 | } | |
1213 | ||
1214 | /* get next entry for port */ | |
1215 | int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port, | |
1216 | unsigned char *addr, bool *is_static) | |
1217 | { | |
1218 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1219 | int ret; | |
1220 | ||
1221 | mutex_lock(&ps->smi_mutex); | |
1222 | ret = __mv88e6xxx_port_getnext(ds, port, addr, is_static); | |
1223 | mutex_unlock(&ps->smi_mutex); | |
1224 | ||
1225 | return ret; | |
1226 | } | |
1227 | ||
facd95b2 GR |
1228 | static void mv88e6xxx_bridge_work(struct work_struct *work) |
1229 | { | |
1230 | struct mv88e6xxx_priv_state *ps; | |
1231 | struct dsa_switch *ds; | |
1232 | int port; | |
1233 | ||
1234 | ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work); | |
1235 | ds = ((struct dsa_switch *)ps) - 1; | |
1236 | ||
1237 | while (ps->port_state_update_mask) { | |
1238 | port = __ffs(ps->port_state_update_mask); | |
1239 | clear_bit(port, &ps->port_state_update_mask); | |
1240 | mv88e6xxx_set_port_state(ds, port, ps->port_state[port]); | |
1241 | } | |
1242 | } | |
1243 | ||
d827e88a GR |
1244 | int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port) |
1245 | { | |
1246 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
facd95b2 | 1247 | int ret, fid; |
d827e88a GR |
1248 | |
1249 | mutex_lock(&ps->smi_mutex); | |
1250 | ||
366f0a0f GR |
1251 | /* Port Control 1: disable trunking, disable sending |
1252 | * learning messages to this port. | |
d827e88a | 1253 | */ |
cca8b133 AL |
1254 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN, |
1255 | 0x0000); | |
d827e88a GR |
1256 | if (ret) |
1257 | goto abort; | |
1258 | ||
1259 | /* Port based VLAN map: give each port its own address | |
1260 | * database, allow the CPU port to talk to each of the 'real' | |
1261 | * ports, and allow each of the 'real' ports to only talk to | |
1262 | * the upstream port. | |
1263 | */ | |
facd95b2 GR |
1264 | fid = __ffs(ps->fid_mask); |
1265 | ps->fid[port] = fid; | |
1266 | ps->fid_mask &= ~(1 << fid); | |
1267 | ||
1268 | if (!dsa_is_cpu_port(ds, port)) | |
1269 | ps->bridge_mask[fid] = 1 << port; | |
d827e88a | 1270 | |
facd95b2 | 1271 | ret = _mv88e6xxx_update_port_config(ds, port); |
d827e88a GR |
1272 | if (ret) |
1273 | goto abort; | |
1274 | ||
1275 | /* Default VLAN ID and priority: don't set a default VLAN | |
1276 | * ID, and set the default packet priority to zero. | |
1277 | */ | |
1278 | ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), 0x07, 0x0000); | |
1279 | abort: | |
1280 | mutex_unlock(&ps->smi_mutex); | |
1281 | return ret; | |
1282 | } | |
1283 | ||
acdaffcc GR |
1284 | int mv88e6xxx_setup_common(struct dsa_switch *ds) |
1285 | { | |
1286 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1287 | ||
1288 | mutex_init(&ps->smi_mutex); | |
1289 | mutex_init(&ps->stats_mutex); | |
1290 | mutex_init(&ps->phy_mutex); | |
1291 | ||
cca8b133 | 1292 | ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; |
a8f064c6 | 1293 | |
facd95b2 GR |
1294 | ps->fid_mask = (1 << DSA_MAX_PORTS) - 1; |
1295 | ||
1296 | INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work); | |
1297 | ||
acdaffcc GR |
1298 | return 0; |
1299 | } | |
1300 | ||
143a8307 AL |
1301 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active) |
1302 | { | |
1303 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1304 | u16 is_reset = (ppu_active ? 0x8800 : 0xc800); | |
1305 | unsigned long timeout; | |
1306 | int ret; | |
1307 | int i; | |
1308 | ||
1309 | /* Set all ports to the disabled state. */ | |
1310 | for (i = 0; i < ps->num_ports; i++) { | |
cca8b133 AL |
1311 | ret = REG_READ(REG_PORT(i), PORT_CONTROL); |
1312 | REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc); | |
143a8307 AL |
1313 | } |
1314 | ||
1315 | /* Wait for transmit queues to drain. */ | |
1316 | usleep_range(2000, 4000); | |
1317 | ||
1318 | /* Reset the switch. Keep the PPU active if requested. The PPU | |
1319 | * needs to be active to support indirect phy register access | |
1320 | * through global registers 0x18 and 0x19. | |
1321 | */ | |
1322 | if (ppu_active) | |
1323 | REG_WRITE(REG_GLOBAL, 0x04, 0xc000); | |
1324 | else | |
1325 | REG_WRITE(REG_GLOBAL, 0x04, 0xc400); | |
1326 | ||
1327 | /* Wait up to one second for reset to complete. */ | |
1328 | timeout = jiffies + 1 * HZ; | |
1329 | while (time_before(jiffies, timeout)) { | |
1330 | ret = REG_READ(REG_GLOBAL, 0x00); | |
1331 | if ((ret & is_reset) == is_reset) | |
1332 | break; | |
1333 | usleep_range(1000, 2000); | |
1334 | } | |
1335 | if (time_after(jiffies, timeout)) | |
1336 | return -ETIMEDOUT; | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
49143585 AL |
1341 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg) |
1342 | { | |
1343 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1344 | int ret; | |
1345 | ||
1346 | mutex_lock(&ps->phy_mutex); | |
fd3a0ee4 | 1347 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
1348 | if (ret < 0) |
1349 | goto error; | |
fd3a0ee4 | 1350 | ret = _mv88e6xxx_phy_read_indirect(ds, port, reg); |
49143585 | 1351 | error: |
fd3a0ee4 | 1352 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
49143585 AL |
1353 | mutex_unlock(&ps->phy_mutex); |
1354 | return ret; | |
1355 | } | |
1356 | ||
1357 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
1358 | int reg, int val) | |
1359 | { | |
1360 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1361 | int ret; | |
1362 | ||
1363 | mutex_lock(&ps->phy_mutex); | |
fd3a0ee4 | 1364 | ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page); |
49143585 AL |
1365 | if (ret < 0) |
1366 | goto error; | |
1367 | ||
fd3a0ee4 | 1368 | ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val); |
49143585 | 1369 | error: |
fd3a0ee4 AL |
1370 | _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0); |
1371 | mutex_unlock(&ps->phy_mutex); | |
1372 | return ret; | |
1373 | } | |
1374 | ||
1375 | static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port) | |
1376 | { | |
1377 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1378 | ||
1379 | if (port >= 0 && port < ps->num_ports) | |
1380 | return port; | |
1381 | return -EINVAL; | |
1382 | } | |
1383 | ||
1384 | int | |
1385 | mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum) | |
1386 | { | |
1387 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1388 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1389 | int ret; | |
1390 | ||
1391 | if (addr < 0) | |
1392 | return addr; | |
1393 | ||
1394 | mutex_lock(&ps->phy_mutex); | |
1395 | ret = _mv88e6xxx_phy_read(ds, addr, regnum); | |
1396 | mutex_unlock(&ps->phy_mutex); | |
1397 | return ret; | |
1398 | } | |
1399 | ||
1400 | int | |
1401 | mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) | |
1402 | { | |
1403 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1404 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1405 | int ret; | |
1406 | ||
1407 | if (addr < 0) | |
1408 | return addr; | |
1409 | ||
1410 | mutex_lock(&ps->phy_mutex); | |
1411 | ret = _mv88e6xxx_phy_write(ds, addr, regnum, val); | |
1412 | mutex_unlock(&ps->phy_mutex); | |
1413 | return ret; | |
1414 | } | |
1415 | ||
1416 | int | |
1417 | mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum) | |
1418 | { | |
1419 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1420 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1421 | int ret; | |
1422 | ||
1423 | if (addr < 0) | |
1424 | return addr; | |
1425 | ||
1426 | mutex_lock(&ps->phy_mutex); | |
1427 | ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum); | |
1428 | mutex_unlock(&ps->phy_mutex); | |
1429 | return ret; | |
1430 | } | |
1431 | ||
1432 | int | |
1433 | mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
1434 | u16 val) | |
1435 | { | |
1436 | struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); | |
1437 | int addr = mv88e6xxx_port_to_phy_addr(ds, port); | |
1438 | int ret; | |
1439 | ||
1440 | if (addr < 0) | |
1441 | return addr; | |
1442 | ||
1443 | mutex_lock(&ps->phy_mutex); | |
1444 | ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val); | |
49143585 AL |
1445 | mutex_unlock(&ps->phy_mutex); |
1446 | return ret; | |
1447 | } | |
1448 | ||
98e67308 BH |
1449 | static int __init mv88e6xxx_init(void) |
1450 | { | |
1451 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
1452 | register_switch_driver(&mv88e6131_switch_driver); | |
1453 | #endif | |
1454 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) | |
1455 | register_switch_driver(&mv88e6123_61_65_switch_driver); | |
42f27253 | 1456 | #endif |
3ad50cca GR |
1457 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352) |
1458 | register_switch_driver(&mv88e6352_switch_driver); | |
1459 | #endif | |
42f27253 AL |
1460 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
1461 | register_switch_driver(&mv88e6171_switch_driver); | |
98e67308 BH |
1462 | #endif |
1463 | return 0; | |
1464 | } | |
1465 | module_init(mv88e6xxx_init); | |
1466 | ||
1467 | static void __exit mv88e6xxx_cleanup(void) | |
1468 | { | |
42f27253 AL |
1469 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171) |
1470 | unregister_switch_driver(&mv88e6171_switch_driver); | |
1471 | #endif | |
98e67308 BH |
1472 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65) |
1473 | unregister_switch_driver(&mv88e6123_61_65_switch_driver); | |
1474 | #endif | |
1475 | #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131) | |
1476 | unregister_switch_driver(&mv88e6131_switch_driver); | |
1477 | #endif | |
1478 | } | |
1479 | module_exit(mv88e6xxx_cleanup); | |
3d825ede BH |
1480 | |
1481 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); | |
1482 | MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); | |
1483 | MODULE_LICENSE("GPL"); |