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net: dsa: mv88e6xxx: factorize bridge support
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
19b2f97e 18#include <linux/jiffies.h>
91da11f8 19#include <linux/list.h>
2bbba277 20#include <linux/module.h>
91da11f8 21#include <linux/netdevice.h>
c8c1b39a 22#include <linux/gpio/consumer.h>
91da11f8 23#include <linux/phy.h>
c8f0b869 24#include <net/dsa.h>
1f36faf2 25#include <net/switchdev.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
158bc065 28static void assert_smi_lock(struct mv88e6xxx_priv_state *ps)
3996a4ff 29{
3996a4ff 30 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
158bc065 31 dev_err(ps->dev, "SMI lock not held!\n");
3996a4ff
VD		 32 dump_stack();
33 }
34}
35
3675c8d7 36/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 37 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
38 * will be directly accessible on some {device address,register address}
39 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
40 * will only respond to SMI transactions to that specific address, and
41 * an indirect addressing mechanism needs to be used to access its
42 * registers.
43 */
44static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
45{
46 int ret;
47 int i;
48
49 for (i = 0; i < 16; i++) {
6e899e6c 50 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 51 if (ret < 0)
52 return ret;
53
cca8b133 54 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 55 return 0;
56 }
57
58 return -ETIMEDOUT;
59}
60
b9b37713
VD		 61static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
62 int reg)
91da11f8
LB		 63{
64 int ret;
65
66 if (sw_addr == 0)
6e899e6c 67 return mdiobus_read_nested(bus, addr, reg);
91da11f8 68
3675c8d7 69 /* Wait for the bus to become free. */
91da11f8
LB		 70 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
71 if (ret < 0)
72 return ret;
73
3675c8d7 74 /* Transmit the read command. */
6e899e6c
NA		 75 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
76 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 77 if (ret < 0)
78 return ret;
79
3675c8d7 80 /* Wait for the read command to complete. */
91da11f8
LB		 81 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
82 if (ret < 0)
83 return ret;
84
3675c8d7 85 /* Read the data. */
6e899e6c 86 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 87 if (ret < 0)
88 return ret;
89
90 return ret & 0xffff;
91}
92
158bc065
AL		 93static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps,
94 int addr, int reg)
91da11f8 95{
91da11f8
LB		 96 int ret;
97
158bc065 98 assert_smi_lock(ps);
3996a4ff 99
a77d43f1 100 ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
bb92ea5e
VD		 101 if (ret < 0)
102 return ret;
103
158bc065 104 dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 105 addr, reg, ret);
106
91da11f8
LB		 107 return ret;
108}
109
158bc065 110int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, int reg)
8d6d09e7 111{
8d6d09e7
GR		 112 int ret;
113
114 mutex_lock(&ps->smi_mutex);
158bc065 115 ret = _mv88e6xxx_reg_read(ps, addr, reg);
8d6d09e7
GR		 116 mutex_unlock(&ps->smi_mutex);
117
118 return ret;
119}
120
b9b37713
VD		 121static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
122 int reg, u16 val)
91da11f8
LB		 123{
124 int ret;
125
126 if (sw_addr == 0)
6e899e6c 127 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 128
3675c8d7 129 /* Wait for the bus to become free. */
91da11f8
LB		 130 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
131 if (ret < 0)
132 return ret;
133
3675c8d7 134 /* Transmit the data to write. */
6e899e6c 135 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 136 if (ret < 0)
137 return ret;
138
3675c8d7 139 /* Transmit the write command. */
6e899e6c
NA		 140 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
141 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Wait for the write command to complete. */
91da11f8
LB		 146 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
147 if (ret < 0)
148 return ret;
149
150 return 0;
151}
152
158bc065
AL		 153static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
154 int reg, u16 val)
91da11f8 155{
158bc065 156 assert_smi_lock(ps);
91da11f8 157
158bc065 158 dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
bb92ea5e
VD		 159 addr, reg, val);
160
a77d43f1 161 return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
8d6d09e7
GR		 162}
163
158bc065
AL		 164int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
165 int reg, u16 val)
8d6d09e7 166{
8d6d09e7
GR		 167 int ret;
168
91da11f8 169 mutex_lock(&ps->smi_mutex);
158bc065 170 ret = _mv88e6xxx_reg_write(ps, addr, reg, val);
91da11f8
LB		 171 mutex_unlock(&ps->smi_mutex);
172
173 return ret;
174}
175
1d13a06e 176static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
2e5f0320 177{
158bc065 178 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
48ace4ef 179 int err;
2e5f0320 180
158bc065 181 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01,
48ace4ef
AL		 182 (addr[0] << 8) | addr[1]);
183 if (err)
184 return err;
185
158bc065 186 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23,
48ace4ef
AL		 187 (addr[2] << 8) | addr[3]);
188 if (err)
189 return err;
190
158bc065 191 return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45,
48ace4ef 192 (addr[4] << 8) | addr[5]);
2e5f0320
LB		 193}
194
1d13a06e 195static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
91da11f8 196{
158bc065 197 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8 198 int ret;
48ace4ef 199 int i;
91da11f8
LB		 200
201 for (i = 0; i < 6; i++) {
202 int j;
203
3675c8d7 204 /* Write the MAC address byte. */
158bc065 205 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
48ace4ef
AL		 206 GLOBAL2_SWITCH_MAC_BUSY |
207 (i << 8) | addr[i]);
208 if (ret)
209 return ret;
91da11f8 210
3675c8d7 211 /* Wait for the write to complete. */
91da11f8 212 for (j = 0; j < 16; j++) {
158bc065 213 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2,
48ace4ef
AL		 214 GLOBAL2_SWITCH_MAC);
215 if (ret < 0)
216 return ret;
217
cca8b133 218 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 219 break;
220 }
221 if (j == 16)
222 return -ETIMEDOUT;
223 }
224
225 return 0;
226}
227
1d13a06e
VD		 228int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
229{
230 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
231
232 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC))
233 return mv88e6xxx_set_addr_indirect(ds, addr);
234 else
235 return mv88e6xxx_set_addr_direct(ds, addr);
236}
237
158bc065
AL		 238static int _mv88e6xxx_phy_read(struct mv88e6xxx_priv_state *ps, int addr,
239 int regnum)
91da11f8
LB		 240{
241 if (addr >= 0)
158bc065 242 return _mv88e6xxx_reg_read(ps, addr, regnum);
91da11f8
LB		 243 return 0xffff;
244}
245
158bc065
AL		 246static int _mv88e6xxx_phy_write(struct mv88e6xxx_priv_state *ps, int addr,
247 int regnum, u16 val)
91da11f8
LB		 248{
249 if (addr >= 0)
158bc065 250 return _mv88e6xxx_reg_write(ps, addr, regnum, val);
91da11f8
LB		 251 return 0;
252}
253
158bc065 254static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
2e5f0320
LB		 255{
256 int ret;
19b2f97e 257 unsigned long timeout;
2e5f0320 258
8c9983a2 259 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 260 if (ret < 0)
261 return ret;
262
8c9983a2
VD		 263 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
264 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
48ace4ef
AL		 265 if (ret)
266 return ret;
2e5f0320 267
19b2f97e
BG		 268 timeout = jiffies + 1 * HZ;
269 while (time_before(jiffies, timeout)) {
8c9983a2 270 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 271 if (ret < 0)
272 return ret;
273
19b2f97e 274 usleep_range(1000, 2000);
cca8b133
AL		 275 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
276 GLOBAL_STATUS_PPU_POLLING)
85686581 277 return 0;
2e5f0320
LB		 278 }
279
280 return -ETIMEDOUT;
281}
282
158bc065 283static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps)
2e5f0320 284{
48ace4ef 285 int ret, err;
19b2f97e 286 unsigned long timeout;
2e5f0320 287
158bc065 288 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
48ace4ef
AL		 289 if (ret < 0)
290 return ret;
291
158bc065 292 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
48ace4ef
AL		 293 ret | GLOBAL_CONTROL_PPU_ENABLE);
294 if (err)
295 return err;
2e5f0320 296
19b2f97e
BG		 297 timeout = jiffies + 1 * HZ;
298 while (time_before(jiffies, timeout)) {
158bc065 299 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
48ace4ef
AL		 300 if (ret < 0)
301 return ret;
302
19b2f97e 303 usleep_range(1000, 2000);
cca8b133
AL		 304 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
305 GLOBAL_STATUS_PPU_POLLING)
85686581 306 return 0;
2e5f0320
LB		 307 }
308
309 return -ETIMEDOUT;
310}
311
312static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
313{
314 struct mv88e6xxx_priv_state *ps;
315
316 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
317 if (mutex_trylock(&ps->ppu_mutex)) {
158bc065 318 if (mv88e6xxx_ppu_enable(ps) == 0)
85686581
BG		 319 ps->ppu_disabled = 0;
320 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 321 }
322}
323
324static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
325{
326 struct mv88e6xxx_priv_state *ps = (void *)_ps;
327
328 schedule_work(&ps->ppu_work);
329}
330
158bc065 331static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps)
2e5f0320 332{
2e5f0320
LB		 333 int ret;
334
335 mutex_lock(&ps->ppu_mutex);
336
3675c8d7 337 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 338 * we can access the PHY registers. If it was already
339 * disabled, cancel the timer that is going to re-enable
340 * it.
341 */
342 if (!ps->ppu_disabled) {
158bc065 343 ret = mv88e6xxx_ppu_disable(ps);
85686581
BG		 344 if (ret < 0) {
345 mutex_unlock(&ps->ppu_mutex);
346 return ret;
347 }
348 ps->ppu_disabled = 1;
2e5f0320 349 } else {
85686581
BG		 350 del_timer(&ps->ppu_timer);
351 ret = 0;
2e5f0320
LB		 352 }
353
354 return ret;
355}
356
158bc065 357static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps)
2e5f0320 358{
3675c8d7 359 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 360 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
361 mutex_unlock(&ps->ppu_mutex);
362}
363
158bc065 364void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps)
2e5f0320 365{
2e5f0320
LB		 366 mutex_init(&ps->ppu_mutex);
367 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
368 init_timer(&ps->ppu_timer);
369 ps->ppu_timer.data = (unsigned long)ps;
370 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
371}
372
8c9983a2
VD		 373static int mv88e6xxx_phy_read_ppu(struct mv88e6xxx_priv_state *ps, int addr,
374 int regnum)
2e5f0320
LB		 375{
376 int ret;
377
158bc065 378 ret = mv88e6xxx_ppu_access_get(ps);
2e5f0320 379 if (ret >= 0) {
8c9983a2 380 ret = _mv88e6xxx_reg_read(ps, addr, regnum);
158bc065 381 mv88e6xxx_ppu_access_put(ps);
2e5f0320
LB		 382 }
383
384 return ret;
385}
386
8c9983a2
VD		 387static int mv88e6xxx_phy_write_ppu(struct mv88e6xxx_priv_state *ps, int addr,
388 int regnum, u16 val)
2e5f0320
LB		 389{
390 int ret;
391
158bc065 392 ret = mv88e6xxx_ppu_access_get(ps);
2e5f0320 393 if (ret >= 0) {
8c9983a2 394 ret = _mv88e6xxx_reg_write(ps, addr, regnum, val);
158bc065 395 mv88e6xxx_ppu_access_put(ps);
2e5f0320
LB		 396 }
397
398 return ret;
399}
2e5f0320 400
158bc065 401static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps)
54d792f2 402{
22356476 403 return ps->info->family == MV88E6XXX_FAMILY_6065;
54d792f2
AL		 404}
405
158bc065 406static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps)
54d792f2 407{
22356476 408 return ps->info->family == MV88E6XXX_FAMILY_6095;
54d792f2
AL		 409}
410
158bc065 411static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps)
54d792f2 412{
22356476 413 return ps->info->family == MV88E6XXX_FAMILY_6097;
54d792f2
AL		 414}
415
158bc065 416static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps)
54d792f2 417{
22356476 418 return ps->info->family == MV88E6XXX_FAMILY_6165;
54d792f2
AL		 419}
420
158bc065 421static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps)
54d792f2 422{
22356476 423 return ps->info->family == MV88E6XXX_FAMILY_6185;
54d792f2
AL		 424}
425
158bc065 426static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps)
7c3d0d67 427{
22356476 428 return ps->info->family == MV88E6XXX_FAMILY_6320;
7c3d0d67
AK		 429}
430
158bc065 431static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps)
54d792f2 432{
22356476 433 return ps->info->family == MV88E6XXX_FAMILY_6351;
54d792f2
AL		 434}
435
158bc065 436static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps)
f3a8b6b6 437{
22356476 438 return ps->info->family == MV88E6XXX_FAMILY_6352;
f3a8b6b6
AL		 439}
440
158bc065 441static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps)
f74df0be 442{
cd5a2c82 443 return ps->info->num_databases;
f74df0be
VD		 444}
445
158bc065 446static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps)
b426e5f7
VD		 447{
448 /* Does the device have dedicated FID registers for ATU and VTU ops? */
158bc065
AL		 449 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
450 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
b426e5f7
VD		 451 return true;
452
453 return false;
454}
455
158bc065 456static bool mv88e6xxx_has_stu(struct mv88e6xxx_priv_state *ps)
2e7bd5ef
VD		 457{
458 /* Does the device have STU and dedicated SID registers for VTU ops? */
158bc065
AL		 459 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
460 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
2e7bd5ef
VD		 461 return true;
462
463 return false;
464}
465
dea87024
AL		 466/* We expect the switch to perform auto negotiation if there is a real
467 * phy. However, in the case of a fixed link phy, we force the port
468 * settings from the fixed link settings.
469 */
470void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
471 struct phy_device *phydev)
472{
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 474 u32 reg;
475 int ret;
dea87024
AL		 476
477 if (!phy_is_pseudo_fixed_link(phydev))
478 return;
479
480 mutex_lock(&ps->smi_mutex);
481
158bc065 482 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
dea87024
AL		 483 if (ret < 0)
484 goto out;
485
486 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
487 PORT_PCS_CTRL_FORCE_LINK |
488 PORT_PCS_CTRL_DUPLEX_FULL |
489 PORT_PCS_CTRL_FORCE_DUPLEX |
490 PORT_PCS_CTRL_UNFORCED);
491
492 reg |= PORT_PCS_CTRL_FORCE_LINK;
493 if (phydev->link)
494 reg |= PORT_PCS_CTRL_LINK_UP;
495
158bc065 496 if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100)
dea87024
AL		 497 goto out;
498
499 switch (phydev->speed) {
500 case SPEED_1000:
501 reg |= PORT_PCS_CTRL_1000;
502 break;
503 case SPEED_100:
504 reg |= PORT_PCS_CTRL_100;
505 break;
506 case SPEED_10:
507 reg |= PORT_PCS_CTRL_10;
508 break;
509 default:
510 pr_info("Unknown speed");
511 goto out;
512 }
513
514 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
515 if (phydev->duplex == DUPLEX_FULL)
516 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
517
158bc065 518 if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) &&
009a2b98 519 (port >= ps->info->num_ports - 2)) {
e7e72ac0
AL		 520 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
521 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
522 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
523 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
524 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
525 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
526 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
527 }
158bc065 528 _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg);
dea87024
AL		 529
530out:
531 mutex_unlock(&ps->smi_mutex);
532}
533
158bc065 534static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps)
91da11f8
LB		 535{
536 int ret;
537 int i;
538
539 for (i = 0; i < 10; i++) {
158bc065 540 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 541 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 542 return 0;
543 }
544
545 return -ETIMEDOUT;
546}
547
158bc065
AL		 548static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps,
549 int port)
91da11f8
LB		 550{
551 int ret;
552
158bc065 553 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
f3a8b6b6
AL		 554 port = (port + 1) << 5;
555
3675c8d7 556 /* Snapshot the hardware statistics counters for this port. */
158bc065 557 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 558 GLOBAL_STATS_OP_CAPTURE_PORT |
559 GLOBAL_STATS_OP_HIST_RX_TX | port);
560 if (ret < 0)
561 return ret;
91da11f8 562
3675c8d7 563 /* Wait for the snapshotting to complete. */
158bc065 564 ret = _mv88e6xxx_stats_wait(ps);
91da11f8
LB		 565 if (ret < 0)
566 return ret;
567
568 return 0;
569}
570
158bc065
AL		 571static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps,
572 int stat, u32 *val)
91da11f8
LB		 573{
574 u32 _val;
575 int ret;
576
577 *val = 0;
578
158bc065 579 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
31888234
AL		 580 GLOBAL_STATS_OP_READ_CAPTURED |
581 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 582 if (ret < 0)
583 return;
584
158bc065 585 ret = _mv88e6xxx_stats_wait(ps);
91da11f8
LB		 586 if (ret < 0)
587 return;
588
158bc065 589 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 590 if (ret < 0)
591 return;
592
593 _val = ret << 16;
594
158bc065 595 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 596 if (ret < 0)
597 return;
598
599 *val = _val | ret;
600}
601
e413e7e1 602static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 603 { "in_good_octets", 8, 0x00, BANK0, },
604 { "in_bad_octets", 4, 0x02, BANK0, },
605 { "in_unicast", 4, 0x04, BANK0, },
606 { "in_broadcasts", 4, 0x06, BANK0, },
607 { "in_multicasts", 4, 0x07, BANK0, },
608 { "in_pause", 4, 0x16, BANK0, },
609 { "in_undersize", 4, 0x18, BANK0, },
610 { "in_fragments", 4, 0x19, BANK0, },
611 { "in_oversize", 4, 0x1a, BANK0, },
612 { "in_jabber", 4, 0x1b, BANK0, },
613 { "in_rx_error", 4, 0x1c, BANK0, },
614 { "in_fcs_error", 4, 0x1d, BANK0, },
615 { "out_octets", 8, 0x0e, BANK0, },
616 { "out_unicast", 4, 0x10, BANK0, },
617 { "out_broadcasts", 4, 0x13, BANK0, },
618 { "out_multicasts", 4, 0x12, BANK0, },
619 { "out_pause", 4, 0x15, BANK0, },
620 { "excessive", 4, 0x11, BANK0, },
621 { "collisions", 4, 0x1e, BANK0, },
622 { "deferred", 4, 0x05, BANK0, },
623 { "single", 4, 0x14, BANK0, },
624 { "multiple", 4, 0x17, BANK0, },
625 { "out_fcs_error", 4, 0x03, BANK0, },
626 { "late", 4, 0x1f, BANK0, },
627 { "hist_64bytes", 4, 0x08, BANK0, },
628 { "hist_65_127bytes", 4, 0x09, BANK0, },
629 { "hist_128_255bytes", 4, 0x0a, BANK0, },
630 { "hist_256_511bytes", 4, 0x0b, BANK0, },
631 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
632 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
633 { "sw_in_discards", 4, 0x10, PORT, },
634 { "sw_in_filtered", 2, 0x12, PORT, },
635 { "sw_out_filtered", 2, 0x13, PORT, },
636 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
637 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
638 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
639 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
640 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
641 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
642 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
643 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
644 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
645 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
646 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
647 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
648 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
649 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
650 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
651 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
652 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
653 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 662};
663
158bc065 664static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps,
f5e2ed02 665 struct mv88e6xxx_hw_stat *stat)
e413e7e1 666{
f5e2ed02
AL		 667 switch (stat->type) {
668 case BANK0:
e413e7e1 669 return true;
f5e2ed02 670 case BANK1:
158bc065 671 return mv88e6xxx_6320_family(ps);
f5e2ed02 672 case PORT:
158bc065
AL		 673 return mv88e6xxx_6095_family(ps) ||
674 mv88e6xxx_6185_family(ps) ||
675 mv88e6xxx_6097_family(ps) ||
676 mv88e6xxx_6165_family(ps) ||
677 mv88e6xxx_6351_family(ps) ||
678 mv88e6xxx_6352_family(ps);
91da11f8 679 }
f5e2ed02 680 return false;
91da11f8
LB		 681}
682
158bc065 683static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
f5e2ed02 684 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 685 int port)
686{
80c4627b
AL		 687 u32 low;
688 u32 high = 0;
689 int ret;
690 u64 value;
691
f5e2ed02
AL		 692 switch (s->type) {
693 case PORT:
158bc065 694 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg);
80c4627b
AL		 695 if (ret < 0)
696 return UINT64_MAX;
697
698 low = ret;
699 if (s->sizeof_stat == 4) {
158bc065 700 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port),
f5e2ed02 701 s->reg + 1);
80c4627b
AL		 702 if (ret < 0)
703 return UINT64_MAX;
704 high = ret;
705 }
f5e2ed02
AL		 706 break;
707 case BANK0:
708 case BANK1:
158bc065 709 _mv88e6xxx_stats_read(ps, s->reg, &low);
80c4627b 710 if (s->sizeof_stat == 8)
158bc065 711 _mv88e6xxx_stats_read(ps, s->reg + 1, &high);
80c4627b
AL		 712 }
713 value = (((u64)high) << 16) | low;
714 return value;
715}
716
f5e2ed02 717void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
91da11f8 718{
158bc065 719 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f5e2ed02
AL		 720 struct mv88e6xxx_hw_stat *stat;
721 int i, j;
91da11f8 722
f5e2ed02
AL		 723 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
724 stat = &mv88e6xxx_hw_stats[i];
158bc065 725 if (mv88e6xxx_has_stat(ps, stat)) {
f5e2ed02
AL		 726 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
727 ETH_GSTRING_LEN);
728 j++;
729 }
91da11f8 730 }
e413e7e1
AL		 731}
732
733int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
734{
158bc065 735 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f5e2ed02
AL		 736 struct mv88e6xxx_hw_stat *stat;
737 int i, j;
738
739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
158bc065 741 if (mv88e6xxx_has_stat(ps, stat))
f5e2ed02
AL		 742 j++;
743 }
744 return j;
e413e7e1
AL		 745}
746
747void
748mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
749 int port, uint64_t *data)
750{
f5e2ed02
AL		 751 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
752 struct mv88e6xxx_hw_stat *stat;
753 int ret;
754 int i, j;
755
756 mutex_lock(&ps->smi_mutex);
757
158bc065 758 ret = _mv88e6xxx_stats_snapshot(ps, port);
f5e2ed02
AL		 759 if (ret < 0) {
760 mutex_unlock(&ps->smi_mutex);
761 return;
762 }
763 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
764 stat = &mv88e6xxx_hw_stats[i];
158bc065
AL		 765 if (mv88e6xxx_has_stat(ps, stat)) {
766 data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port);
f5e2ed02
AL		 767 j++;
768 }
769 }
770
771 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 772}
773
a1ab91f3
GR		 774int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
775{
776 return 32 * sizeof(u16);
777}
778
779void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
780 struct ethtool_regs *regs, void *_p)
781{
158bc065 782 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
a1ab91f3
GR		 783 u16 *p = _p;
784 int i;
785
786 regs->version = 0;
787
788 memset(p, 0xff, 32 * sizeof(u16));
789
23062513
VD		 790 mutex_lock(&ps->smi_mutex);
791
a1ab91f3
GR		 792 for (i = 0; i < 32; i++) {
793 int ret;
794
23062513 795 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i);
a1ab91f3
GR		 796 if (ret >= 0)
797 p[i] = ret;
798 }
23062513
VD		 799
800 mutex_unlock(&ps->smi_mutex);
a1ab91f3
GR		 801}
802
158bc065 803static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
3898c148 804 u16 mask)
f3044683
AL		 805{
806 unsigned long timeout = jiffies + HZ / 10;
807
808 while (time_before(jiffies, timeout)) {
809 int ret;
810
158bc065 811 ret = _mv88e6xxx_reg_read(ps, reg, offset);
3898c148
AL		 812 if (ret < 0)
813 return ret;
f3044683
AL		 814 if (!(ret & mask))
815 return 0;
816
817 usleep_range(1000, 2000);
818 }
819 return -ETIMEDOUT;
820}
821
158bc065
AL		 822static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg,
823 int offset, u16 mask)
3898c148 824{
3898c148
AL		 825 int ret;
826
827 mutex_lock(&ps->smi_mutex);
158bc065 828 ret = _mv88e6xxx_wait(ps, reg, offset, mask);
3898c148
AL		 829 mutex_unlock(&ps->smi_mutex);
830
831 return ret;
832}
833
158bc065 834static int _mv88e6xxx_phy_wait(struct mv88e6xxx_priv_state *ps)
f3044683 835{
158bc065 836 return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148 837 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 838}
839
d24645be 840static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
f3044683 841{
158bc065
AL		 842 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
843
844 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 845 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 846}
847
d24645be 848static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
f3044683 849{
158bc065
AL		 850 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
851
852 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
cca8b133 853 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 854}
855
d24645be
VD		 856static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
857{
858 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
859 int ret;
860
861 mutex_lock(&ps->eeprom_mutex);
862
863 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
864 GLOBAL2_EEPROM_OP_READ |
865 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
866 if (ret < 0)
867 goto error;
868
869 ret = mv88e6xxx_eeprom_busy_wait(ds);
870 if (ret < 0)
871 goto error;
872
873 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
874error:
875 mutex_unlock(&ps->eeprom_mutex);
876 return ret;
877}
878
879int mv88e6xxx_get_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
880 u8 *data)
881{
882 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
883 int offset;
884 int len;
885 int ret;
886
887 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
888 return -EOPNOTSUPP;
889
890 offset = eeprom->offset;
891 len = eeprom->len;
892 eeprom->len = 0;
893
894 eeprom->magic = 0xc3ec4951;
895
896 ret = mv88e6xxx_eeprom_load_wait(ds);
897 if (ret < 0)
898 return ret;
899
900 if (offset & 1) {
901 int word;
902
903 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
904 if (word < 0)
905 return word;
906
907 *data++ = (word >> 8) & 0xff;
908
909 offset++;
910 len--;
911 eeprom->len++;
912 }
913
914 while (len >= 2) {
915 int word;
916
917 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
918 if (word < 0)
919 return word;
920
921 *data++ = word & 0xff;
922 *data++ = (word >> 8) & 0xff;
923
924 offset += 2;
925 len -= 2;
926 eeprom->len += 2;
927 }
928
929 if (len) {
930 int word;
931
932 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
933 if (word < 0)
934 return word;
935
936 *data++ = word & 0xff;
937
938 offset++;
939 len--;
940 eeprom->len++;
941 }
942
943 return 0;
944}
945
946static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
947{
948 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
949 int ret;
950
951 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
952 if (ret < 0)
953 return ret;
954
955 if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
956 return -EROFS;
957
958 return 0;
959}
960
961static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
962 u16 data)
963{
964 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
965 int ret;
966
967 mutex_lock(&ps->eeprom_mutex);
968
969 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
970 if (ret < 0)
971 goto error;
972
973 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
974 GLOBAL2_EEPROM_OP_WRITE |
975 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
976 if (ret < 0)
977 goto error;
978
979 ret = mv88e6xxx_eeprom_busy_wait(ds);
980error:
981 mutex_unlock(&ps->eeprom_mutex);
982 return ret;
983}
984
985int mv88e6xxx_set_eeprom(struct dsa_switch *ds, struct ethtool_eeprom *eeprom,
986 u8 *data)
987{
988 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
989 int offset;
990 int ret;
991 int len;
992
993 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
994 return -EOPNOTSUPP;
995
996 if (eeprom->magic != 0xc3ec4951)
997 return -EINVAL;
998
999 ret = mv88e6xxx_eeprom_is_readonly(ds);
1000 if (ret)
1001 return ret;
1002
1003 offset = eeprom->offset;
1004 len = eeprom->len;
1005 eeprom->len = 0;
1006
1007 ret = mv88e6xxx_eeprom_load_wait(ds);
1008 if (ret < 0)
1009 return ret;
1010
1011 if (offset & 1) {
1012 int word;
1013
1014 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1015 if (word < 0)
1016 return word;
1017
1018 word = (*data++ << 8) | (word & 0xff);
1019
1020 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1021 if (ret < 0)
1022 return ret;
1023
1024 offset++;
1025 len--;
1026 eeprom->len++;
1027 }
1028
1029 while (len >= 2) {
1030 int word;
1031
1032 word = *data++;
1033 word |= *data++ << 8;
1034
1035 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1036 if (ret < 0)
1037 return ret;
1038
1039 offset += 2;
1040 len -= 2;
1041 eeprom->len += 2;
1042 }
1043
1044 if (len) {
1045 int word;
1046
1047 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1048 if (word < 0)
1049 return word;
1050
1051 word = (word & 0xff00) | *data++;
1052
1053 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1054 if (ret < 0)
1055 return ret;
1056
1057 offset++;
1058 len--;
1059 eeprom->len++;
1060 }
1061
1062 return 0;
1063}
1064
158bc065 1065static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps)
facd95b2 1066{
158bc065 1067 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP,
cca8b133 1068 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 1069}
1070
158bc065
AL		 1071static int _mv88e6xxx_phy_read_indirect(struct mv88e6xxx_priv_state *ps,
1072 int addr, int regnum)
f3044683
AL		 1073{
1074 int ret;
1075
158bc065 1076 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1077 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1078 regnum);
1079 if (ret < 0)
1080 return ret;
f3044683 1081
158bc065 1082 ret = _mv88e6xxx_phy_wait(ps);
f3044683
AL		 1083 if (ret < 0)
1084 return ret;
1085
158bc065
AL		 1086 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1087
1088 return ret;
f3044683
AL		 1089}
1090
158bc065
AL		 1091static int _mv88e6xxx_phy_write_indirect(struct mv88e6xxx_priv_state *ps,
1092 int addr, int regnum, u16 val)
f3044683 1093{
3898c148
AL		 1094 int ret;
1095
158bc065 1096 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
3898c148
AL		 1097 if (ret < 0)
1098 return ret;
f3044683 1099
158bc065 1100 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
3898c148
AL		 1101 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1102 regnum);
1103
158bc065 1104 return _mv88e6xxx_phy_wait(ps);
f3044683
AL		 1105}
1106
11b3b45d
GR		 1107int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1108{
2f40c698 1109 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 1110 int reg;
1111
aadbdb8a
VD		 1112 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1113 return -EOPNOTSUPP;
1114
3898c148 1115 mutex_lock(&ps->smi_mutex);
2f40c698 1116
158bc065 1117 reg = _mv88e6xxx_phy_read_indirect(ps, port, 16);
11b3b45d 1118 if (reg < 0)
2f40c698 1119 goto out;
11b3b45d
GR		 1120
1121 e->eee_enabled = !!(reg & 0x0200);
1122 e->tx_lpi_enabled = !!(reg & 0x0100);
1123
158bc065 1124 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
11b3b45d 1125 if (reg < 0)
2f40c698 1126 goto out;
11b3b45d 1127
cca8b133 1128 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 1129 reg = 0;
11b3b45d 1130
2f40c698 1131out:
3898c148 1132 mutex_unlock(&ps->smi_mutex);
2f40c698 1133 return reg;
11b3b45d
GR		 1134}
1135
1136int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1137 struct phy_device *phydev, struct ethtool_eee *e)
1138{
2f40c698
AL		 1139 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1140 int reg;
11b3b45d
GR		 1141 int ret;
1142
aadbdb8a
VD		 1143 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1144 return -EOPNOTSUPP;
1145
3898c148 1146 mutex_lock(&ps->smi_mutex);
11b3b45d 1147
158bc065 1148 ret = _mv88e6xxx_phy_read_indirect(ps, port, 16);
2f40c698
AL		 1149 if (ret < 0)
1150 goto out;
1151
1152 reg = ret & ~0x0300;
1153 if (e->eee_enabled)
1154 reg |= 0x0200;
1155 if (e->tx_lpi_enabled)
1156 reg |= 0x0100;
1157
158bc065 1158 ret = _mv88e6xxx_phy_write_indirect(ps, port, 16, reg);
2f40c698 1159out:
3898c148 1160 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 1161
1162 return ret;
11b3b45d
GR		 1163}
1164
158bc065 1165static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd)
facd95b2
GR		 1166{
1167 int ret;
1168
158bc065
AL		 1169 if (mv88e6xxx_has_fid_reg(ps)) {
1170 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid);
b426e5f7
VD		 1171 if (ret < 0)
1172 return ret;
158bc065 1173 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f 1174 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
158bc065 1175 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL);
11ea809f
VD		 1176 if (ret < 0)
1177 return ret;
1178
158bc065 1179 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
11ea809f
VD		 1180 (ret & 0xfff) |
1181 ((fid << 8) & 0xf000));
1182 if (ret < 0)
1183 return ret;
1184
1185 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1186 cmd |= fid & 0xf;
b426e5f7
VD		 1187 }
1188
158bc065 1189 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 1190 if (ret < 0)
1191 return ret;
1192
158bc065 1193 return _mv88e6xxx_atu_wait(ps);
facd95b2
GR		 1194}
1195
158bc065 1196static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps,
37705b73
VD		 1197 struct mv88e6xxx_atu_entry *entry)
1198{
1199 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1200
1201 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1202 unsigned int mask, shift;
1203
1204 if (entry->trunk) {
1205 data |= GLOBAL_ATU_DATA_TRUNK;
1206 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1207 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1208 } else {
1209 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1210 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1211 }
1212
1213 data |= (entry->portv_trunkid << shift) & mask;
1214 }
1215
158bc065 1216 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data);
37705b73
VD		 1217}
1218
158bc065 1219static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps,
7fb5e755
VD		 1220 struct mv88e6xxx_atu_entry *entry,
1221 bool static_too)
facd95b2 1222{
7fb5e755
VD		 1223 int op;
1224 int err;
facd95b2 1225
158bc065 1226 err = _mv88e6xxx_atu_wait(ps);
7fb5e755
VD		 1227 if (err)
1228 return err;
facd95b2 1229
158bc065 1230 err = _mv88e6xxx_atu_data_write(ps, entry);
7fb5e755
VD		 1231 if (err)
1232 return err;
1233
1234 if (entry->fid) {
7fb5e755
VD		 1235 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1236 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1237 } else {
1238 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1239 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1240 }
1241
158bc065 1242 return _mv88e6xxx_atu_cmd(ps, entry->fid, op);
7fb5e755
VD		 1243}
1244
158bc065
AL		 1245static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps,
1246 u16 fid, bool static_too)
7fb5e755
VD		 1247{
1248 struct mv88e6xxx_atu_entry entry = {
1249 .fid = fid,
1250 .state = 0, /* EntryState bits must be 0 */
1251 };
70cc99d1 1252
158bc065 1253 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
7fb5e755
VD		 1254}
1255
158bc065
AL		 1256static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid,
1257 int from_port, int to_port, bool static_too)
9f4d55d2
VD		 1258{
1259 struct mv88e6xxx_atu_entry entry = {
1260 .trunk = false,
1261 .fid = fid,
1262 };
1263
1264 /* EntryState bits must be 0xF */
1265 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1266
1267 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1268 entry.portv_trunkid = (to_port & 0x0f) << 4;
1269 entry.portv_trunkid |= from_port & 0x0f;
1270
158bc065 1271 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
9f4d55d2
VD		 1272}
1273
158bc065
AL		 1274static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid,
1275 int port, bool static_too)
9f4d55d2
VD		 1276{
1277 /* Destination port 0xF means remove the entries */
158bc065 1278 return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too);
9f4d55d2
VD		 1279}
1280
2d9deae4
VD		 1281static const char * const mv88e6xxx_port_state_names[] = {
1282 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1283 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1284 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1285 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1286};
1287
158bc065
AL		 1288static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1289 u8 state)
facd95b2 1290{
158bc065 1291 struct dsa_switch *ds = ps->ds;
c3ffe6d2 1292 int reg, ret = 0;
facd95b2
GR		 1293 u8 oldstate;
1294
158bc065 1295 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL);
2d9deae4
VD		 1296 if (reg < 0)
1297 return reg;
facd95b2 1298
cca8b133 1299 oldstate = reg & PORT_CONTROL_STATE_MASK;
2d9deae4 1300
facd95b2
GR		 1301 if (oldstate != state) {
1302 /* Flush forwarding database if we're moving a port
1303 * from Learning or Forwarding state to Disabled or
1304 * Blocking or Listening state.
1305 */
2d9deae4
VD		 1306 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1307 oldstate == PORT_CONTROL_STATE_FORWARDING)
1308 && (state == PORT_CONTROL_STATE_DISABLED ||
1309 state == PORT_CONTROL_STATE_BLOCKING)) {
158bc065 1310 ret = _mv88e6xxx_atu_remove(ps, 0, port, false);
facd95b2 1311 if (ret)
2d9deae4 1312 return ret;
facd95b2 1313 }
2d9deae4 1314
cca8b133 1315 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
158bc065 1316 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL,
cca8b133 1317 reg);
2d9deae4
VD		 1318 if (ret)
1319 return ret;
1320
1321 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1322 mv88e6xxx_port_state_names[state],
1323 mv88e6xxx_port_state_names[oldstate]);
facd95b2
GR		 1324 }
1325
facd95b2
GR		 1326 return ret;
1327}
1328
158bc065
AL		 1329static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1330 int port)
facd95b2 1331{
b7666efe 1332 struct net_device *bridge = ps->ports[port].bridge_dev;
009a2b98 1333 const u16 mask = (1 << ps->info->num_ports) - 1;
158bc065 1334 struct dsa_switch *ds = ps->ds;
b7666efe 1335 u16 output_ports = 0;
ede8098d 1336 int reg;
b7666efe
VD		 1337 int i;
1338
1339 /* allow CPU port or DSA link(s) to send frames to every port */
1340 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1341 output_ports = mask;
1342 } else {
009a2b98 1343 for (i = 0; i < ps->info->num_ports; ++i) {
b7666efe
VD		 1344 /* allow sending frames to every group member */
1345 if (bridge && ps->ports[i].bridge_dev == bridge)
1346 output_ports |= BIT(i);
1347
1348 /* allow sending frames to CPU port and DSA link(s) */
1349 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1350 output_ports |= BIT(i);
1351 }
1352 }
1353
1354 /* prevent frames from going back out of the port they came in on */
1355 output_ports &= ~BIT(port);
facd95b2 1356
158bc065 1357 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
ede8098d
VD		 1358 if (reg < 0)
1359 return reg;
facd95b2 1360
ede8098d
VD		 1361 reg &= ~mask;
1362 reg |= output_ports & mask;
facd95b2 1363
158bc065 1364 return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1365}
1366
43c44a9f 1367void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
facd95b2
GR		 1368{
1369 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1370 int stp_state;
1371
936f234a
VD		 1372 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE))
1373 return;
1374
facd95b2
GR		 1375 switch (state) {
1376 case BR_STATE_DISABLED:
cca8b133 1377 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1378 break;
1379 case BR_STATE_BLOCKING:
1380 case BR_STATE_LISTENING:
cca8b133 1381 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1382 break;
1383 case BR_STATE_LEARNING:
cca8b133 1384 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1385 break;
1386 case BR_STATE_FORWARDING:
1387 default:
cca8b133 1388 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1389 break;
1390 }
1391
43c44a9f 1392 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
facd95b2
GR		 1393 * so we can not update the port state directly but need to schedule it.
1394 */
d715fa64 1395 ps->ports[port].state = stp_state;
2d9deae4 1396 set_bit(port, ps->port_state_update_mask);
facd95b2 1397 schedule_work(&ps->bridge_work);
facd95b2
GR		 1398}
1399
158bc065
AL		 1400static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1401 u16 *new, u16 *old)
76e398a6 1402{
158bc065 1403 struct dsa_switch *ds = ps->ds;
5da96031 1404 u16 pvid;
76e398a6
VD		 1405 int ret;
1406
158bc065 1407 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN);
76e398a6
VD		 1408 if (ret < 0)
1409 return ret;
1410
5da96031
VD		 1411 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1412
1413 if (new) {
1414 ret &= ~PORT_DEFAULT_VLAN_MASK;
1415 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1416
158bc065 1417 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
5da96031
VD		 1418 PORT_DEFAULT_VLAN, ret);
1419 if (ret < 0)
1420 return ret;
1421
1422 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1423 pvid);
1424 }
1425
1426 if (old)
1427 *old = pvid;
76e398a6
VD		 1428
1429 return 0;
1430}
1431
158bc065
AL		 1432static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps,
1433 int port, u16 *pvid)
5da96031 1434{
158bc065 1435 return _mv88e6xxx_port_pvid(ps, port, NULL, pvid);
5da96031
VD		 1436}
1437
158bc065
AL		 1438static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps,
1439 int port, u16 pvid)
0d3b33e6 1440{
158bc065 1441 return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL);
0d3b33e6
VD		 1442}
1443
158bc065 1444static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps)
6b17e864 1445{
158bc065 1446 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP,
6b17e864
VD		 1447 GLOBAL_VTU_OP_BUSY);
1448}
1449
158bc065 1450static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op)
6b17e864
VD		 1451{
1452 int ret;
1453
158bc065 1454 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op);
6b17e864
VD		 1455 if (ret < 0)
1456 return ret;
1457
158bc065 1458 return _mv88e6xxx_vtu_wait(ps);
6b17e864
VD		 1459}
1460
158bc065 1461static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps)
6b17e864
VD		 1462{
1463 int ret;
1464
158bc065 1465 ret = _mv88e6xxx_vtu_wait(ps);
6b17e864
VD		 1466 if (ret < 0)
1467 return ret;
1468
158bc065 1469 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL);
6b17e864
VD		 1470}
1471
158bc065 1472static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
b8fee957
VD		 1473 struct mv88e6xxx_vtu_stu_entry *entry,
1474 unsigned int nibble_offset)
1475{
b8fee957
VD		 1476 u16 regs[3];
1477 int i;
1478 int ret;
1479
1480 for (i = 0; i < 3; ++i) {
158bc065 1481 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1482 GLOBAL_VTU_DATA_0_3 + i);
1483 if (ret < 0)
1484 return ret;
1485
1486 regs[i] = ret;
1487 }
1488
009a2b98 1489 for (i = 0; i < ps->info->num_ports; ++i) {
b8fee957
VD		 1490 unsigned int shift = (i % 4) * 4 + nibble_offset;
1491 u16 reg = regs[i / 4];
1492
1493 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1494 }
1495
1496 return 0;
1497}
1498
158bc065 1499static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
7dad08d7
VD		 1500 struct mv88e6xxx_vtu_stu_entry *entry,
1501 unsigned int nibble_offset)
1502{
7dad08d7
VD		 1503 u16 regs[3] = { 0 };
1504 int i;
1505 int ret;
1506
009a2b98 1507 for (i = 0; i < ps->info->num_ports; ++i) {
7dad08d7
VD		 1508 unsigned int shift = (i % 4) * 4 + nibble_offset;
1509 u8 data = entry->data[i];
1510
1511 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1512 }
1513
1514 for (i = 0; i < 3; ++i) {
158bc065 1515 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL,
7dad08d7
VD		 1516 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1517 if (ret < 0)
1518 return ret;
1519 }
1520
1521 return 0;
1522}
1523
158bc065 1524static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid)
36d04ba1 1525{
158bc065 1526 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID,
36d04ba1
VD		 1527 vid & GLOBAL_VTU_VID_MASK);
1528}
1529
158bc065 1530static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
b8fee957
VD		 1531 struct mv88e6xxx_vtu_stu_entry *entry)
1532{
1533 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1534 int ret;
1535
158bc065 1536 ret = _mv88e6xxx_vtu_wait(ps);
b8fee957
VD		 1537 if (ret < 0)
1538 return ret;
1539
158bc065 1540 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT);
b8fee957
VD		 1541 if (ret < 0)
1542 return ret;
1543
158bc065 1544 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
b8fee957
VD		 1545 if (ret < 0)
1546 return ret;
1547
1548 next.vid = ret & GLOBAL_VTU_VID_MASK;
1549 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1550
1551 if (next.valid) {
158bc065 1552 ret = _mv88e6xxx_vtu_stu_data_read(ps, &next, 0);
b8fee957
VD		 1553 if (ret < 0)
1554 return ret;
1555
158bc065
AL		 1556 if (mv88e6xxx_has_fid_reg(ps)) {
1557 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1558 GLOBAL_VTU_FID);
1559 if (ret < 0)
1560 return ret;
1561
1562 next.fid = ret & GLOBAL_VTU_FID_MASK;
158bc065 1563 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f
VD		 1564 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1565 * VTU DBNum[3:0] are located in VTU Operation 3:0
1566 */
158bc065 1567 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
11ea809f
VD		 1568 GLOBAL_VTU_OP);
1569 if (ret < 0)
1570 return ret;
1571
1572 next.fid = (ret & 0xf00) >> 4;
1573 next.fid |= ret & 0xf;
2e7bd5ef 1574 }
b8fee957 1575
158bc065
AL		 1576 if (mv88e6xxx_has_stu(ps)) {
1577 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
b8fee957
VD		 1578 GLOBAL_VTU_SID);
1579 if (ret < 0)
1580 return ret;
1581
1582 next.sid = ret & GLOBAL_VTU_SID_MASK;
1583 }
1584 }
1585
1586 *entry = next;
1587 return 0;
1588}
1589
ceff5eff
VD		 1590int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1591 struct switchdev_obj_port_vlan *vlan,
1592 int (*cb)(struct switchdev_obj *obj))
1593{
1594 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1595 struct mv88e6xxx_vtu_stu_entry next;
1596 u16 pvid;
1597 int err;
1598
1599 mutex_lock(&ps->smi_mutex);
1600
158bc065 1601 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
ceff5eff
VD		 1602 if (err)
1603 goto unlock;
1604
158bc065 1605 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
ceff5eff
VD		 1606 if (err)
1607 goto unlock;
1608
1609 do {
158bc065 1610 err = _mv88e6xxx_vtu_getnext(ps, &next);
ceff5eff
VD		 1611 if (err)
1612 break;
1613
1614 if (!next.valid)
1615 break;
1616
1617 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1618 continue;
1619
1620 /* reinit and dump this VLAN obj */
1621 vlan->vid_begin = vlan->vid_end = next.vid;
1622 vlan->flags = 0;
1623
1624 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1625 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1626
1627 if (next.vid == pvid)
1628 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1629
1630 err = cb(&vlan->obj);
1631 if (err)
1632 break;
1633 } while (next.vid < GLOBAL_VTU_VID_MASK);
1634
1635unlock:
1636 mutex_unlock(&ps->smi_mutex);
1637
1638 return err;
1639}
1640
158bc065 1641static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
7dad08d7
VD		 1642 struct mv88e6xxx_vtu_stu_entry *entry)
1643{
11ea809f 1644 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
7dad08d7
VD		 1645 u16 reg = 0;
1646 int ret;
1647
158bc065 1648 ret = _mv88e6xxx_vtu_wait(ps);
7dad08d7
VD		 1649 if (ret < 0)
1650 return ret;
1651
1652 if (!entry->valid)
1653 goto loadpurge;
1654
1655 /* Write port member tags */
158bc065 1656 ret = _mv88e6xxx_vtu_stu_data_write(ps, entry, 0);
7dad08d7
VD		 1657 if (ret < 0)
1658 return ret;
1659
158bc065 1660 if (mv88e6xxx_has_stu(ps)) {
7dad08d7 1661 reg = entry->sid & GLOBAL_VTU_SID_MASK;
158bc065 1662 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
7dad08d7
VD		 1663 if (ret < 0)
1664 return ret;
b426e5f7 1665 }
7dad08d7 1666
158bc065 1667 if (mv88e6xxx_has_fid_reg(ps)) {
7dad08d7 1668 reg = entry->fid & GLOBAL_VTU_FID_MASK;
158bc065 1669 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg);
7dad08d7
VD		 1670 if (ret < 0)
1671 return ret;
158bc065 1672 } else if (mv88e6xxx_num_databases(ps) == 256) {
11ea809f
VD		 1673 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1674 * VTU DBNum[3:0] are located in VTU Operation 3:0
1675 */
1676 op |= (entry->fid & 0xf0) << 8;
1677 op |= entry->fid & 0xf;
7dad08d7
VD		 1678 }
1679
1680 reg = GLOBAL_VTU_VID_VALID;
1681loadpurge:
1682 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
158bc065 1683 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
7dad08d7
VD		 1684 if (ret < 0)
1685 return ret;
1686
158bc065 1687 return _mv88e6xxx_vtu_cmd(ps, op);
7dad08d7
VD		 1688}
1689
158bc065 1690static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid,
0d3b33e6
VD		 1691 struct mv88e6xxx_vtu_stu_entry *entry)
1692{
1693 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1694 int ret;
1695
158bc065 1696 ret = _mv88e6xxx_vtu_wait(ps);
0d3b33e6
VD		 1697 if (ret < 0)
1698 return ret;
1699
158bc065 1700 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID,
0d3b33e6
VD		 1701 sid & GLOBAL_VTU_SID_MASK);
1702 if (ret < 0)
1703 return ret;
1704
158bc065 1705 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT);
0d3b33e6
VD		 1706 if (ret < 0)
1707 return ret;
1708
158bc065 1709 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID);
0d3b33e6
VD		 1710 if (ret < 0)
1711 return ret;
1712
1713 next.sid = ret & GLOBAL_VTU_SID_MASK;
1714
158bc065 1715 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
0d3b33e6
VD		 1716 if (ret < 0)
1717 return ret;
1718
1719 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1720
1721 if (next.valid) {
158bc065 1722 ret = _mv88e6xxx_vtu_stu_data_read(ps, &next, 2);
0d3b33e6
VD		 1723 if (ret < 0)
1724 return ret;
1725 }
1726
1727 *entry = next;
1728 return 0;
1729}
1730
158bc065 1731static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps,
0d3b33e6
VD		 1732 struct mv88e6xxx_vtu_stu_entry *entry)
1733{
1734 u16 reg = 0;
1735 int ret;
1736
158bc065 1737 ret = _mv88e6xxx_vtu_wait(ps);
0d3b33e6
VD		 1738 if (ret < 0)
1739 return ret;
1740
1741 if (!entry->valid)
1742 goto loadpurge;
1743
1744 /* Write port states */
158bc065 1745 ret = _mv88e6xxx_vtu_stu_data_write(ps, entry, 2);
0d3b33e6
VD		 1746 if (ret < 0)
1747 return ret;
1748
1749 reg = GLOBAL_VTU_VID_VALID;
1750loadpurge:
158bc065 1751 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
0d3b33e6
VD		 1752 if (ret < 0)
1753 return ret;
1754
1755 reg = entry->sid & GLOBAL_VTU_SID_MASK;
158bc065 1756 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
0d3b33e6
VD		 1757 if (ret < 0)
1758 return ret;
1759
158bc065 1760 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE);
0d3b33e6
VD		 1761}
1762
158bc065
AL		 1763static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1764 u16 *new, u16 *old)
2db9ce1f 1765{
158bc065 1766 struct dsa_switch *ds = ps->ds;
f74df0be 1767 u16 upper_mask;
2db9ce1f
VD		 1768 u16 fid;
1769 int ret;
1770
158bc065 1771 if (mv88e6xxx_num_databases(ps) == 4096)
f74df0be 1772 upper_mask = 0xff;
158bc065 1773 else if (mv88e6xxx_num_databases(ps) == 256)
11ea809f 1774 upper_mask = 0xf;
f74df0be
VD		 1775 else
1776 return -EOPNOTSUPP;
1777
2db9ce1f 1778 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
158bc065 1779 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
2db9ce1f
VD		 1780 if (ret < 0)
1781 return ret;
1782
1783 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1784
1785 if (new) {
1786 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1787 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1788
158bc065 1789 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN,
2db9ce1f
VD		 1790 ret);
1791 if (ret < 0)
1792 return ret;
1793 }
1794
1795 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
158bc065 1796 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1);
2db9ce1f
VD		 1797 if (ret < 0)
1798 return ret;
1799
f74df0be 1800 fid |= (ret & upper_mask) << 4;
2db9ce1f
VD		 1801
1802 if (new) {
f74df0be
VD		 1803 ret &= ~upper_mask;
1804 ret |= (*new >> 4) & upper_mask;
2db9ce1f 1805
158bc065 1806 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1,
2db9ce1f
VD		 1807 ret);
1808 if (ret < 0)
1809 return ret;
1810
1811 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1812 }
1813
1814 if (old)
1815 *old = fid;
1816
1817 return 0;
1818}
1819
158bc065
AL		 1820static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps,
1821 int port, u16 *fid)
2db9ce1f 1822{
158bc065 1823 return _mv88e6xxx_port_fid(ps, port, NULL, fid);
2db9ce1f
VD		 1824}
1825
158bc065
AL		 1826static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps,
1827 int port, u16 fid)
2db9ce1f 1828{
158bc065 1829 return _mv88e6xxx_port_fid(ps, port, &fid, NULL);
2db9ce1f
VD		 1830}
1831
158bc065 1832static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
3285f9e8
VD		 1833{
1834 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1835 struct mv88e6xxx_vtu_stu_entry vlan;
2db9ce1f 1836 int i, err;
3285f9e8
VD		 1837
1838 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1839
2db9ce1f 1840 /* Set every FID bit used by the (un)bridged ports */
009a2b98 1841 for (i = 0; i < ps->info->num_ports; ++i) {
158bc065 1842 err = _mv88e6xxx_port_fid_get(ps, i, fid);
2db9ce1f
VD		 1843 if (err)
1844 return err;
1845
1846 set_bit(*fid, fid_bitmap);
1847 }
1848
3285f9e8 1849 /* Set every FID bit used by the VLAN entries */
158bc065 1850 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
3285f9e8
VD		 1851 if (err)
1852 return err;
1853
1854 do {
158bc065 1855 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
3285f9e8
VD		 1856 if (err)
1857 return err;
1858
1859 if (!vlan.valid)
1860 break;
1861
1862 set_bit(vlan.fid, fid_bitmap);
1863 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1864
1865 /* The reset value 0x000 is used to indicate that multiple address
1866 * databases are not needed. Return the next positive available.
1867 */
1868 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
158bc065 1869 if (unlikely(*fid >= mv88e6xxx_num_databases(ps)))
3285f9e8
VD		 1870 return -ENOSPC;
1871
1872 /* Clear the database */
158bc065 1873 return _mv88e6xxx_atu_flush(ps, *fid, true);
3285f9e8
VD		 1874}
1875
158bc065 1876static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
2fb5ef09 1877 struct mv88e6xxx_vtu_stu_entry *entry)
0d3b33e6 1878{
158bc065 1879 struct dsa_switch *ds = ps->ds;
0d3b33e6
VD		 1880 struct mv88e6xxx_vtu_stu_entry vlan = {
1881 .valid = true,
1882 .vid = vid,
1883 };
3285f9e8
VD		 1884 int i, err;
1885
158bc065 1886 err = _mv88e6xxx_fid_new(ps, &vlan.fid);
3285f9e8
VD		 1887 if (err)
1888 return err;
0d3b33e6 1889
3d131f07 1890 /* exclude all ports except the CPU and DSA ports */
009a2b98 1891 for (i = 0; i < ps->info->num_ports; ++i)
3d131f07
VD		 1892 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1893 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1894 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6 1895
158bc065
AL		 1896 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
1897 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) {
0d3b33e6 1898 struct mv88e6xxx_vtu_stu_entry vstp;
0d3b33e6
VD		 1899
1900 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1901 * implemented, only one STU entry is needed to cover all VTU
1902 * entries. Thus, validate the SID 0.
1903 */
1904 vlan.sid = 0;
158bc065 1905 err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp);
0d3b33e6
VD		 1906 if (err)
1907 return err;
1908
1909 if (vstp.sid != vlan.sid || !vstp.valid) {
1910 memset(&vstp, 0, sizeof(vstp));
1911 vstp.valid = true;
1912 vstp.sid = vlan.sid;
1913
158bc065 1914 err = _mv88e6xxx_stu_loadpurge(ps, &vstp);
0d3b33e6
VD		 1915 if (err)
1916 return err;
1917 }
0d3b33e6
VD		 1918 }
1919
1920 *entry = vlan;
1921 return 0;
1922}
1923
158bc065 1924static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
2fb5ef09
VD		 1925 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1926{
1927 int err;
1928
1929 if (!vid)
1930 return -EINVAL;
1931
158bc065 1932 err = _mv88e6xxx_vtu_vid_write(ps, vid - 1);
2fb5ef09
VD		 1933 if (err)
1934 return err;
1935
158bc065 1936 err = _mv88e6xxx_vtu_getnext(ps, entry);
2fb5ef09
VD		 1937 if (err)
1938 return err;
1939
1940 if (entry->vid != vid || !entry->valid) {
1941 if (!creat)
1942 return -EOPNOTSUPP;
1943 /* -ENOENT would've been more appropriate, but switchdev expects
1944 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1945 */
1946
158bc065 1947 err = _mv88e6xxx_vtu_new(ps, vid, entry);
2fb5ef09
VD		 1948 }
1949
1950 return err;
1951}
1952
da9c359e
VD		 1953static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1954 u16 vid_begin, u16 vid_end)
1955{
1956 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1957 struct mv88e6xxx_vtu_stu_entry vlan;
1958 int i, err;
1959
1960 if (!vid_begin)
1961 return -EOPNOTSUPP;
1962
1963 mutex_lock(&ps->smi_mutex);
1964
158bc065 1965 err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1);
da9c359e
VD		 1966 if (err)
1967 goto unlock;
1968
1969 do {
158bc065 1970 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
da9c359e
VD		 1971 if (err)
1972 goto unlock;
1973
1974 if (!vlan.valid)
1975 break;
1976
1977 if (vlan.vid > vid_end)
1978 break;
1979
009a2b98 1980 for (i = 0; i < ps->info->num_ports; ++i) {
da9c359e
VD		 1981 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1982 continue;
1983
1984 if (vlan.data[i] ==
1985 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1986 continue;
1987
1988 if (ps->ports[i].bridge_dev ==
1989 ps->ports[port].bridge_dev)
1990 break; /* same bridge, check next VLAN */
1991
1992 netdev_warn(ds->ports[port],
1993 "hardware VLAN %d already used by %s\n",
1994 vlan.vid,
1995 netdev_name(ps->ports[i].bridge_dev));
1996 err = -EOPNOTSUPP;
1997 goto unlock;
1998 }
1999 } while (vlan.vid < vid_end);
2000
2001unlock:
2002 mutex_unlock(&ps->smi_mutex);
2003
2004 return err;
2005}
2006
214cdb99
VD		 2007static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2008 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2009 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2010 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2011 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2012};
2013
2014int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2015 bool vlan_filtering)
2016{
2017 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2018 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2019 PORT_CONTROL_2_8021Q_DISABLED;
2020 int ret;
2021
2022 mutex_lock(&ps->smi_mutex);
2023
158bc065 2024 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2);
214cdb99
VD		 2025 if (ret < 0)
2026 goto unlock;
2027
2028 old = ret & PORT_CONTROL_2_8021Q_MASK;
2029
5220ef1e
VD		 2030 if (new != old) {
2031 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2032 ret |= new & PORT_CONTROL_2_8021Q_MASK;
214cdb99 2033
158bc065 2034 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2,
5220ef1e
VD		 2035 ret);
2036 if (ret < 0)
2037 goto unlock;
2038
2039 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
2040 mv88e6xxx_port_8021q_mode_names[new],
2041 mv88e6xxx_port_8021q_mode_names[old]);
2042 }
214cdb99 2043
5220ef1e 2044 ret = 0;
214cdb99
VD		 2045unlock:
2046 mutex_unlock(&ps->smi_mutex);
2047
2048 return ret;
2049}
2050
76e398a6
VD		 2051int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2052 const struct switchdev_obj_port_vlan *vlan,
2053 struct switchdev_trans *trans)
2054{
da9c359e
VD		 2055 int err;
2056
da9c359e
VD		 2057 /* If the requested port doesn't belong to the same bridge as the VLAN
2058 * members, do not support it (yet) and fallback to software VLAN.
2059 */
2060 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2061 vlan->vid_end);
2062 if (err)
2063 return err;
2064
76e398a6
VD		 2065 /* We don't need any dynamic resource from the kernel (yet),
2066 * so skip the prepare phase.
2067 */
2068 return 0;
2069}
2070
158bc065
AL		 2071static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port,
2072 u16 vid, bool untagged)
0d3b33e6 2073{
0d3b33e6
VD		 2074 struct mv88e6xxx_vtu_stu_entry vlan;
2075 int err;
2076
158bc065 2077 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true);
0d3b33e6 2078 if (err)
76e398a6 2079 return err;
0d3b33e6 2080
0d3b33e6
VD		 2081 vlan.data[port] = untagged ?
2082 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2083 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2084
158bc065 2085 return _mv88e6xxx_vtu_loadpurge(ps, &vlan);
76e398a6
VD		 2086}
2087
4d5770b3
VD		 2088void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2089 const struct switchdev_obj_port_vlan *vlan,
2090 struct switchdev_trans *trans)
76e398a6
VD		 2091{
2092 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2093 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2094 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2095 u16 vid;
76e398a6
VD		 2096
2097 mutex_lock(&ps->smi_mutex);
2098
4d5770b3 2099 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
158bc065 2100 if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged))
4d5770b3
VD		 2101 netdev_err(ds->ports[port], "failed to add VLAN %d%c\n",
2102 vid, untagged ? 'u' : 't');
76e398a6 2103
158bc065 2104 if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end))
4d5770b3
VD		 2105 netdev_err(ds->ports[port], "failed to set PVID %d\n",
2106 vlan->vid_end);
0d3b33e6 2107
4d5770b3 2108 mutex_unlock(&ps->smi_mutex);
0d3b33e6
VD		 2109}
2110
158bc065
AL		 2111static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2112 int port, u16 vid)
7dad08d7 2113{
158bc065 2114 struct dsa_switch *ds = ps->ds;
7dad08d7 2115 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 2116 int i, err;
2117
158bc065 2118 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
7dad08d7 2119 if (err)
76e398a6 2120 return err;
7dad08d7 2121
2fb5ef09
VD		 2122 /* Tell switchdev if this VLAN is handled in software */
2123 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 2124 return -EOPNOTSUPP;
7dad08d7
VD		 2125
2126 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2127
2128 /* keep the VLAN unless all ports are excluded */
f02bdffc 2129 vlan.valid = false;
009a2b98 2130 for (i = 0; i < ps->info->num_ports; ++i) {
3d131f07 2131 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 2132 continue;
2133
2134 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 2135 vlan.valid = true;
7dad08d7
VD		 2136 break;
2137 }
2138 }
2139
158bc065 2140 err = _mv88e6xxx_vtu_loadpurge(ps, &vlan);
76e398a6
VD		 2141 if (err)
2142 return err;
2143
158bc065 2144 return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false);
76e398a6
VD		 2145}
2146
2147int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2148 const struct switchdev_obj_port_vlan *vlan)
2149{
2150 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2151 u16 pvid, vid;
2152 int err = 0;
2153
2154 mutex_lock(&ps->smi_mutex);
2155
158bc065 2156 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
7dad08d7
VD		 2157 if (err)
2158 goto unlock;
2159
76e398a6 2160 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
158bc065 2161 err = _mv88e6xxx_port_vlan_del(ps, port, vid);
76e398a6
VD		 2162 if (err)
2163 goto unlock;
2164
2165 if (vid == pvid) {
158bc065 2166 err = _mv88e6xxx_port_pvid_set(ps, port, 0);
76e398a6
VD		 2167 if (err)
2168 goto unlock;
2169 }
2170 }
2171
7dad08d7
VD		 2172unlock:
2173 mutex_unlock(&ps->smi_mutex);
2174
2175 return err;
2176}
2177
158bc065 2178static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps,
c5723ac5 2179 const unsigned char *addr)
defb05b9
GR		 2180{
2181 int i, ret;
2182
2183 for (i = 0; i < 3; i++) {
cca8b133 2184 ret = _mv88e6xxx_reg_write(
158bc065 2185 ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
cca8b133 2186 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 2187 if (ret < 0)
2188 return ret;
2189 }
2190
2191 return 0;
2192}
2193
158bc065
AL		 2194static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps,
2195 unsigned char *addr)
defb05b9
GR		 2196{
2197 int i, ret;
2198
2199 for (i = 0; i < 3; i++) {
158bc065 2200 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
cca8b133 2201 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 2202 if (ret < 0)
2203 return ret;
2204 addr[i * 2] = ret >> 8;
2205 addr[i * 2 + 1] = ret & 0xff;
2206 }
2207
2208 return 0;
2209}
2210
158bc065 2211static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps,
fd231c82 2212 struct mv88e6xxx_atu_entry *entry)
defb05b9 2213{
6630e236
VD		 2214 int ret;
2215
158bc065 2216 ret = _mv88e6xxx_atu_wait(ps);
defb05b9
GR		 2217 if (ret < 0)
2218 return ret;
2219
158bc065 2220 ret = _mv88e6xxx_atu_mac_write(ps, entry->mac);
defb05b9
GR		 2221 if (ret < 0)
2222 return ret;
2223
158bc065 2224 ret = _mv88e6xxx_atu_data_write(ps, entry);
fd231c82 2225 if (ret < 0)
87820510
VD		 2226 return ret;
2227
158bc065 2228 return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 2229}
87820510 2230
158bc065 2231static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
fd231c82
VD		 2232 const unsigned char *addr, u16 vid,
2233 u8 state)
2234{
2235 struct mv88e6xxx_atu_entry entry = { 0 };
3285f9e8
VD		 2236 struct mv88e6xxx_vtu_stu_entry vlan;
2237 int err;
2238
2db9ce1f
VD		 2239 /* Null VLAN ID corresponds to the port private database */
2240 if (vid == 0)
158bc065 2241 err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid);
2db9ce1f 2242 else
158bc065 2243 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
3285f9e8
VD		 2244 if (err)
2245 return err;
fd231c82 2246
3285f9e8 2247 entry.fid = vlan.fid;
fd231c82
VD		 2248 entry.state = state;
2249 ether_addr_copy(entry.mac, addr);
2250 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2251 entry.trunk = false;
2252 entry.portv_trunkid = BIT(port);
2253 }
2254
158bc065 2255 return _mv88e6xxx_atu_load(ps, &entry);
87820510
VD		 2256}
2257
146a3206
VD		 2258int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2259 const struct switchdev_obj_port_fdb *fdb,
2260 struct switchdev_trans *trans)
2261{
2262 /* We don't need any dynamic resource from the kernel (yet),
2263 * so skip the prepare phase.
2264 */
2265 return 0;
2266}
2267
8497aa61
VD		 2268void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2269 const struct switchdev_obj_port_fdb *fdb,
2270 struct switchdev_trans *trans)
87820510 2271{
1f36faf2 2272 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 2273 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2274 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 2275 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2276
2277 mutex_lock(&ps->smi_mutex);
158bc065 2278 if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state))
8497aa61 2279 netdev_err(ds->ports[port], "failed to load MAC address\n");
87820510 2280 mutex_unlock(&ps->smi_mutex);
87820510
VD		 2281}
2282
cdf09697 2283int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 2284 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 2285{
2286 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 2287 int ret;
2288
2289 mutex_lock(&ps->smi_mutex);
158bc065 2290 ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid,
cdf09697 2291 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 2292 mutex_unlock(&ps->smi_mutex);
2293
2294 return ret;
2295}
2296
158bc065 2297static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
1d194046 2298 struct mv88e6xxx_atu_entry *entry)
6630e236 2299{
1d194046
VD		 2300 struct mv88e6xxx_atu_entry next = { 0 };
2301 int ret;
2302
2303 next.fid = fid;
defb05b9 2304
158bc065 2305 ret = _mv88e6xxx_atu_wait(ps);
cdf09697
DM		 2306 if (ret < 0)
2307 return ret;
6630e236 2308
158bc065 2309 ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 2310 if (ret < 0)
2311 return ret;
6630e236 2312
158bc065 2313 ret = _mv88e6xxx_atu_mac_read(ps, next.mac);
1d194046
VD		 2314 if (ret < 0)
2315 return ret;
6630e236 2316
158bc065 2317 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 2318 if (ret < 0)
2319 return ret;
6630e236 2320
1d194046
VD		 2321 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2322 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2323 unsigned int mask, shift;
2324
2325 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2326 next.trunk = true;
2327 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2328 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2329 } else {
2330 next.trunk = false;
2331 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2332 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2333 }
2334
2335 next.portv_trunkid = (ret & mask) >> shift;
2336 }
cdf09697 2337
1d194046 2338 *entry = next;
cdf09697
DM		 2339 return 0;
2340}
2341
158bc065
AL		 2342static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps,
2343 u16 fid, u16 vid, int port,
74b6ba0d
VD		 2344 struct switchdev_obj_port_fdb *fdb,
2345 int (*cb)(struct switchdev_obj *obj))
2346{
2347 struct mv88e6xxx_atu_entry addr = {
2348 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2349 };
2350 int err;
2351
158bc065 2352 err = _mv88e6xxx_atu_mac_write(ps, addr.mac);
74b6ba0d
VD		 2353 if (err)
2354 return err;
2355
2356 do {
158bc065 2357 err = _mv88e6xxx_atu_getnext(ps, fid, &addr);
74b6ba0d
VD		 2358 if (err)
2359 break;
2360
2361 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2362 break;
2363
2364 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2365 bool is_static = addr.state ==
2366 (is_multicast_ether_addr(addr.mac) ?
2367 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2368 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2369
2370 fdb->vid = vid;
2371 ether_addr_copy(fdb->addr, addr.mac);
2372 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2373
2374 err = cb(&fdb->obj);
2375 if (err)
2376 break;
2377 }
2378 } while (!is_broadcast_ether_addr(addr.mac));
2379
2380 return err;
2381}
2382
f33475bd
VD		 2383int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2384 struct switchdev_obj_port_fdb *fdb,
2385 int (*cb)(struct switchdev_obj *obj))
2386{
2387 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2388 struct mv88e6xxx_vtu_stu_entry vlan = {
2389 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2390 };
2db9ce1f 2391 u16 fid;
f33475bd
VD		 2392 int err;
2393
2394 mutex_lock(&ps->smi_mutex);
2395
2db9ce1f 2396 /* Dump port's default Filtering Information Database (VLAN ID 0) */
158bc065 2397 err = _mv88e6xxx_port_fid_get(ps, port, &fid);
2db9ce1f
VD		 2398 if (err)
2399 goto unlock;
2400
158bc065 2401 err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb);
2db9ce1f
VD		 2402 if (err)
2403 goto unlock;
2404
74b6ba0d 2405 /* Dump VLANs' Filtering Information Databases */
158bc065 2406 err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid);
f33475bd
VD		 2407 if (err)
2408 goto unlock;
2409
2410 do {
158bc065 2411 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
f33475bd 2412 if (err)
74b6ba0d 2413 break;
f33475bd
VD		 2414
2415 if (!vlan.valid)
2416 break;
2417
158bc065 2418 err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port,
74b6ba0d 2419 fdb, cb);
f33475bd 2420 if (err)
74b6ba0d 2421 break;
f33475bd
VD		 2422 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2423
2424unlock:
2425 mutex_unlock(&ps->smi_mutex);
2426
2427 return err;
2428}
2429
a6692754
VD		 2430int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2431 struct net_device *bridge)
e79a8bcb 2432{
a6692754 2433 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1d9619d5 2434 int i, err = 0;
466dfa07 2435
936f234a
VD		 2436 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2437 return -EOPNOTSUPP;
2438
466dfa07
VD		 2439 mutex_lock(&ps->smi_mutex);
2440
b7666efe 2441 /* Assign the bridge and remap each port's VLANTable */
a6692754 2442 ps->ports[port].bridge_dev = bridge;
b7666efe 2443
009a2b98 2444 for (i = 0; i < ps->info->num_ports; ++i) {
b7666efe 2445 if (ps->ports[i].bridge_dev == bridge) {
158bc065 2446 err = _mv88e6xxx_port_based_vlan_map(ps, i);
b7666efe
VD		 2447 if (err)
2448 break;
2449 }
2450 }
2451
466dfa07 2452 mutex_unlock(&ps->smi_mutex);
a6692754 2453
466dfa07 2454 return err;
e79a8bcb
VD		 2455}
2456
16bfa702 2457void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 2458{
a6692754 2459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
b7666efe 2460 struct net_device *bridge = ps->ports[port].bridge_dev;
16bfa702 2461 int i;
466dfa07 2462
936f234a
VD		 2463 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2464 return;
2465
466dfa07
VD		 2466 mutex_lock(&ps->smi_mutex);
2467
b7666efe 2468 /* Unassign the bridge and remap each port's VLANTable */
a6692754 2469 ps->ports[port].bridge_dev = NULL;
b7666efe 2470
009a2b98 2471 for (i = 0; i < ps->info->num_ports; ++i)
16bfa702 2472 if (i == port || ps->ports[i].bridge_dev == bridge)
158bc065 2473 if (_mv88e6xxx_port_based_vlan_map(ps, i))
16bfa702 2474 netdev_warn(ds->ports[i], "failed to remap\n");
b7666efe 2475
466dfa07 2476 mutex_unlock(&ps->smi_mutex);
66d9cd0f
VD		 2477}
2478
facd95b2
GR		 2479static void mv88e6xxx_bridge_work(struct work_struct *work)
2480{
2481 struct mv88e6xxx_priv_state *ps;
2482 struct dsa_switch *ds;
2483 int port;
2484
2485 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
7543a6d5 2486 ds = ps->ds;
facd95b2 2487
2d9deae4
VD		 2488 mutex_lock(&ps->smi_mutex);
2489
009a2b98 2490 for (port = 0; port < ps->info->num_ports; ++port)
2d9deae4 2491 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
158bc065
AL		 2492 _mv88e6xxx_port_state(ps, port, ps->ports[port].state))
2493 netdev_warn(ds->ports[port],
2494 "failed to update state to %s\n",
2d9deae4
VD		 2495 mv88e6xxx_port_state_names[ps->ports[port].state]);
2496
2497 mutex_unlock(&ps->smi_mutex);
facd95b2
GR		 2498}
2499
158bc065
AL		 2500static int _mv88e6xxx_phy_page_write(struct mv88e6xxx_priv_state *ps,
2501 int port, int page, int reg, int val)
75baacf0
PU		 2502{
2503 int ret;
2504
158bc065 2505 ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
75baacf0
PU		 2506 if (ret < 0)
2507 goto restore_page_0;
2508
158bc065 2509 ret = _mv88e6xxx_phy_write_indirect(ps, port, reg, val);
75baacf0 2510restore_page_0:
158bc065 2511 _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
75baacf0
PU		 2512
2513 return ret;
2514}
2515
158bc065
AL		 2516static int _mv88e6xxx_phy_page_read(struct mv88e6xxx_priv_state *ps,
2517 int port, int page, int reg)
75baacf0
PU		 2518{
2519 int ret;
2520
158bc065 2521 ret = _mv88e6xxx_phy_write_indirect(ps, port, 0x16, page);
75baacf0
PU		 2522 if (ret < 0)
2523 goto restore_page_0;
2524
158bc065 2525 ret = _mv88e6xxx_phy_read_indirect(ps, port, reg);
75baacf0 2526restore_page_0:
158bc065 2527 _mv88e6xxx_phy_write_indirect(ps, port, 0x16, 0x0);
75baacf0
PU		 2528
2529 return ret;
2530}
2531
158bc065 2532static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps)
13a7ebb3
PU		 2533{
2534 int ret;
2535
158bc065 2536 ret = _mv88e6xxx_phy_page_read(ps, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
13a7ebb3
PU		 2537 MII_BMCR);
2538 if (ret < 0)
2539 return ret;
2540
2541 if (ret & BMCR_PDOWN) {
2542 ret &= ~BMCR_PDOWN;
158bc065 2543 ret = _mv88e6xxx_phy_page_write(ps, REG_FIBER_SERDES,
13a7ebb3
PU		 2544 PAGE_FIBER_SERDES, MII_BMCR,
2545 ret);
2546 }
2547
2548 return ret;
2549}
2550
dbde9e66 2551static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 2552{
2553 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 2554 int ret;
54d792f2 2555 u16 reg;
d827e88a
GR		 2556
2557 mutex_lock(&ps->smi_mutex);
2558
158bc065
AL		 2559 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2560 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2561 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2562 mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2563 /* MAC Forcing register: don't force link, speed,
2564 * duplex or flow control state to any particular
2565 * values on physical ports, but force the CPU port
2566 * and all DSA ports to their maximum bandwidth and
2567 * full duplex.
2568 */
158bc065 2569 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2570 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2571 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2572 reg |= PORT_PCS_CTRL_FORCE_LINK |
2573 PORT_PCS_CTRL_LINK_UP |
2574 PORT_PCS_CTRL_DUPLEX_FULL |
2575 PORT_PCS_CTRL_FORCE_DUPLEX;
158bc065 2576 if (mv88e6xxx_6065_family(ps))
54d792f2
AL		 2577 reg |= PORT_PCS_CTRL_100;
2578 else
2579 reg |= PORT_PCS_CTRL_1000;
2580 } else {
2581 reg |= PORT_PCS_CTRL_UNFORCED;
2582 }
2583
158bc065 2584 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2585 PORT_PCS_CTRL, reg);
2586 if (ret)
2587 goto abort;
2588 }
2589
2590 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2591 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2592 * tunneling, determine priority by looking at 802.1p and IP
2593 * priority fields (IP prio has precedence), and set STP state
2594 * to Forwarding.
2595 *
2596 * If this is the CPU link, use DSA or EDSA tagging depending
2597 * on which tagging mode was configured.
2598 *
2599 * If this is a link to another switch, use DSA tagging mode.
2600 *
2601 * If this is the upstream port for this switch, enable
2602 * forwarding of unknown unicasts and multicasts.
2603 */
2604 reg = 0;
158bc065
AL		 2605 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2606 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2607 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2608 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps))
54d792f2
AL		 2609 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2610 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2611 PORT_CONTROL_STATE_FORWARDING;
2612 if (dsa_is_cpu_port(ds, port)) {
158bc065 2613 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
54d792f2 2614 reg |= PORT_CONTROL_DSA_TAG;
158bc065
AL		 2615 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2616 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2617 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2618 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2619 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2620 else
2621 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2622 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2623 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2624 }
2625
158bc065
AL		 2626 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2627 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2628 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2629 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2630 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2631 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2632 }
2633 }
6083ce71 2634 if (dsa_is_dsa_port(ds, port)) {
158bc065 2635 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
6083ce71 2636 reg |= PORT_CONTROL_DSA_TAG;
158bc065
AL		 2637 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2638 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2639 mv88e6xxx_6320_family(ps)) {
54d792f2 2640 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2641 }
2642
54d792f2
AL		 2643 if (port == dsa_upstream_port(ds))
2644 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2645 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2646 }
2647 if (reg) {
158bc065 2648 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2649 PORT_CONTROL, reg);
2650 if (ret)
2651 goto abort;
2652 }
2653
13a7ebb3
PU		 2654 /* If this port is connected to a SerDes, make sure the SerDes is not
2655 * powered down.
2656 */
158bc065
AL		 2657 if (mv88e6xxx_6352_family(ps)) {
2658 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
13a7ebb3
PU		 2659 if (ret < 0)
2660 goto abort;
2661 ret &= PORT_STATUS_CMODE_MASK;
2662 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2663 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2664 (ret == PORT_STATUS_CMODE_SGMII)) {
158bc065 2665 ret = mv88e6xxx_power_on_serdes(ps);
13a7ebb3
PU		 2666 if (ret < 0)
2667 goto abort;
2668 }
2669 }
2670
8efdda4a 2671 /* Port Control 2: don't force a good FCS, set the maximum frame size to
46fbe5e5 2672 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
8efdda4a
VD		 2673 * untagged frames on this port, do a destination address lookup on all
2674 * received packets as usual, disable ARP mirroring and don't send a
2675 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2676 */
2677 reg = 0;
158bc065
AL		 2678 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2679 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2680 mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) ||
2681 mv88e6xxx_6185_family(ps))
54d792f2
AL		 2682 reg = PORT_CONTROL_2_MAP_DA;
2683
158bc065
AL		 2684 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2685 mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps))
54d792f2
AL		 2686 reg |= PORT_CONTROL_2_JUMBO_10240;
2687
158bc065 2688 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) {
54d792f2
AL		 2689 /* Set the upstream port this port should use */
2690 reg |= dsa_upstream_port(ds);
2691 /* enable forwarding of unknown multicast addresses to
2692 * the upstream port
2693 */
2694 if (port == dsa_upstream_port(ds))
2695 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2696 }
2697
46fbe5e5 2698 reg |= PORT_CONTROL_2_8021Q_DISABLED;
8efdda4a 2699
54d792f2 2700 if (reg) {
158bc065 2701 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2702 PORT_CONTROL_2, reg);
2703 if (ret)
2704 goto abort;
2705 }
2706
2707 /* Port Association Vector: when learning source addresses
2708 * of packets, add the address to the address database using
2709 * a port bitmap that has only the bit for this port set and
2710 * the other bits clear.
2711 */
4c7ea3c0 2712 reg = 1 << port;
996ecb82
VD		 2713 /* Disable learning for CPU port */
2714 if (dsa_is_cpu_port(ds, port))
65fa4027 2715 reg = 0;
4c7ea3c0 2716
158bc065 2717 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2
AL		 2718 if (ret)
2719 goto abort;
2720
2721 /* Egress rate control 2: disable egress rate control. */
158bc065 2722 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2,
54d792f2
AL		 2723 0x0000);
2724 if (ret)
2725 goto abort;
2726
158bc065
AL		 2727 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2728 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2729 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2730 /* Do not limit the period of time that this port can
2731 * be paused for by the remote end or the period of
2732 * time that this port can pause the remote end.
2733 */
158bc065 2734 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2735 PORT_PAUSE_CTRL, 0x0000);
2736 if (ret)
2737 goto abort;
2738
2739 /* Port ATU control: disable limiting the number of
2740 * address database entries that this port is allowed
2741 * to use.
2742 */
158bc065 2743 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2744 PORT_ATU_CONTROL, 0x0000);
2745 /* Priority Override: disable DA, SA and VTU priority
2746 * override.
2747 */
158bc065 2748 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2749 PORT_PRI_OVERRIDE, 0x0000);
2750 if (ret)
2751 goto abort;
2752
2753 /* Port Ethertype: use the Ethertype DSA Ethertype
2754 * value.
2755 */
158bc065 2756 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2757 PORT_ETH_TYPE, ETH_P_EDSA);
2758 if (ret)
2759 goto abort;
2760 /* Tag Remap: use an identity 802.1p prio -> switch
2761 * prio mapping.
2762 */
158bc065 2763 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2764 PORT_TAG_REGMAP_0123, 0x3210);
2765 if (ret)
2766 goto abort;
2767
2768 /* Tag Remap 2: use an identity 802.1p prio -> switch
2769 * prio mapping.
2770 */
158bc065 2771 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2772 PORT_TAG_REGMAP_4567, 0x7654);
2773 if (ret)
2774 goto abort;
2775 }
2776
158bc065
AL		 2777 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2778 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2779 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2780 mv88e6xxx_6320_family(ps)) {
54d792f2 2781 /* Rate Control: disable ingress rate limiting. */
158bc065 2782 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
54d792f2
AL		 2783 PORT_RATE_CONTROL, 0x0001);
2784 if (ret)
2785 goto abort;
2786 }
2787
366f0a0f
GR		 2788 /* Port Control 1: disable trunking, disable sending
2789 * learning messages to this port.
d827e88a 2790 */
158bc065 2791 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2792 if (ret)
2793 goto abort;
2794
207afda1 2795 /* Port based VLAN map: give each port the same default address
b7666efe
VD		 2796 * database, and allow bidirectional communication between the
2797 * CPU and DSA port(s), and the other ports.
d827e88a 2798 */
158bc065 2799 ret = _mv88e6xxx_port_fid_set(ps, port, 0);
2db9ce1f
VD		 2800 if (ret)
2801 goto abort;
2802
158bc065 2803 ret = _mv88e6xxx_port_based_vlan_map(ps, port);
d827e88a
GR		 2804 if (ret)
2805 goto abort;
2806
2807 /* Default VLAN ID and priority: don't set a default VLAN
2808 * ID, and set the default packet priority to zero.
2809 */
158bc065 2810 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN,
47cf1e65 2811 0x0000);
d827e88a
GR		 2812abort:
2813 mutex_unlock(&ps->smi_mutex);
2814 return ret;
2815}
2816
dbde9e66
AL		 2817int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2818{
2819 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2820 int ret;
2821 int i;
2822
009a2b98 2823 for (i = 0; i < ps->info->num_ports; i++) {
dbde9e66
AL		 2824 ret = mv88e6xxx_setup_port(ds, i);
2825 if (ret < 0)
2826 return ret;
2827 }
2828 return 0;
2829}
2830
158bc065 2831int mv88e6xxx_setup_common(struct mv88e6xxx_priv_state *ps)
acdaffcc 2832{
acdaffcc 2833 mutex_init(&ps->smi_mutex);
acdaffcc 2834
facd95b2
GR		 2835 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2836
d24645be
VD		 2837 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
2838 mutex_init(&ps->eeprom_mutex);
2839
8c9983a2
VD		 2840 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
2841 mv88e6xxx_ppu_state_init(ps);
2842
acdaffcc
GR		 2843 return 0;
2844}
2845
54d792f2
AL		 2846int mv88e6xxx_setup_global(struct dsa_switch *ds)
2847{
2848 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
48ace4ef 2849 int err;
54d792f2
AL		 2850 int i;
2851
48ace4ef 2852 mutex_lock(&ps->smi_mutex);
54d792f2
AL		 2853 /* Set the default address aging time to 5 minutes, and
2854 * enable address learn messages to be sent to all message
2855 * ports.
2856 */
158bc065 2857 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
48ace4ef
AL		 2858 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2859 if (err)
2860 goto unlock;
54d792f2
AL		 2861
2862 /* Configure the IP ToS mapping registers. */
158bc065 2863 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
48ace4ef
AL		 2864 if (err)
2865 goto unlock;
158bc065 2866 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
48ace4ef
AL		 2867 if (err)
2868 goto unlock;
158bc065 2869 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
48ace4ef
AL		 2870 if (err)
2871 goto unlock;
158bc065 2872 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
48ace4ef
AL		 2873 if (err)
2874 goto unlock;
158bc065 2875 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
48ace4ef
AL		 2876 if (err)
2877 goto unlock;
158bc065 2878 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
48ace4ef
AL		 2879 if (err)
2880 goto unlock;
158bc065 2881 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
48ace4ef
AL		 2882 if (err)
2883 goto unlock;
158bc065 2884 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
48ace4ef
AL		 2885 if (err)
2886 goto unlock;
54d792f2
AL		 2887
2888 /* Configure the IEEE 802.1p priority mapping register. */
158bc065 2889 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
48ace4ef
AL		 2890 if (err)
2891 goto unlock;
54d792f2
AL		 2892
2893 /* Send all frames with destination addresses matching
2894 * 01:80:c2:00:00:0x to the CPU port.
2895 */
158bc065 2896 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
48ace4ef
AL		 2897 if (err)
2898 goto unlock;
54d792f2
AL		 2899
2900 /* Ignore removed tag data on doubly tagged packets, disable
2901 * flow control messages, force flow control priority to the
2902 * highest, and send all special multicast frames to the CPU
2903 * port at the highest priority.
2904 */
158bc065 2905 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
48ace4ef
AL		 2906 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2907 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2908 if (err)
2909 goto unlock;
54d792f2
AL		 2910
2911 /* Program the DSA routing table. */
2912 for (i = 0; i < 32; i++) {
2913 int nexthop = 0x1f;
2914
2915 if (ds->pd->rtable &&
2916 i != ds->index && i < ds->dst->pd->nr_chips)
2917 nexthop = ds->pd->rtable[i] & 0x1f;
2918
48ace4ef 2919 err = _mv88e6xxx_reg_write(
158bc065 2920 ps, REG_GLOBAL2,
48ace4ef
AL		 2921 GLOBAL2_DEVICE_MAPPING,
2922 GLOBAL2_DEVICE_MAPPING_UPDATE |
2923 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
2924 if (err)
2925 goto unlock;
54d792f2
AL		 2926 }
2927
2928 /* Clear all trunk masks. */
48ace4ef 2929 for (i = 0; i < 8; i++) {
158bc065 2930 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
48ace4ef
AL		 2931 0x8000 |
2932 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
009a2b98 2933 ((1 << ps->info->num_ports) - 1));
48ace4ef
AL		 2934 if (err)
2935 goto unlock;
2936 }
54d792f2
AL		 2937
2938 /* Clear all trunk mappings. */
48ace4ef
AL		 2939 for (i = 0; i < 16; i++) {
2940 err = _mv88e6xxx_reg_write(
158bc065 2941 ps, REG_GLOBAL2,
48ace4ef
AL		 2942 GLOBAL2_TRUNK_MAPPING,
2943 GLOBAL2_TRUNK_MAPPING_UPDATE |
2944 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2945 if (err)
2946 goto unlock;
2947 }
54d792f2 2948
158bc065
AL		 2949 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2950 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2951 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2952 /* Send all frames with destination addresses matching
2953 * 01:80:c2:00:00:2x to the CPU port.
2954 */
158bc065 2955 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 2956 GLOBAL2_MGMT_EN_2X, 0xffff);
2957 if (err)
2958 goto unlock;
54d792f2
AL		 2959
2960 /* Initialise cross-chip port VLAN table to reset
2961 * defaults.
2962 */
158bc065 2963 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 2964 GLOBAL2_PVT_ADDR, 0x9000);
2965 if (err)
2966 goto unlock;
54d792f2
AL		 2967
2968 /* Clear the priority override table. */
48ace4ef 2969 for (i = 0; i < 16; i++) {
158bc065 2970 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 2971 GLOBAL2_PRIO_OVERRIDE,
2972 0x8000 | (i << 8));
2973 if (err)
2974 goto unlock;
2975 }
54d792f2
AL		 2976 }
2977
158bc065
AL		 2978 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2979 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2980 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2981 mv88e6xxx_6320_family(ps)) {
54d792f2
AL		 2982 /* Disable ingress rate limiting by resetting all
2983 * ingress rate limit registers to their initial
2984 * state.
2985 */
009a2b98 2986 for (i = 0; i < ps->info->num_ports; i++) {
158bc065 2987 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
48ace4ef
AL		 2988 GLOBAL2_INGRESS_OP,
2989 0x9000 | (i << 8));
2990 if (err)
2991 goto unlock;
2992 }
54d792f2
AL		 2993 }
2994
db687a56 2995 /* Clear the statistics counters for all ports */
158bc065 2996 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
48ace4ef
AL		 2997 GLOBAL_STATS_OP_FLUSH_ALL);
2998 if (err)
2999 goto unlock;
db687a56
AL		 3000
3001 /* Wait for the flush to complete. */
158bc065 3002 err = _mv88e6xxx_stats_wait(ps);
48ace4ef 3003 if (err < 0)
6b17e864
VD		 3004 goto unlock;
3005
c161d0a5 3006 /* Clear all ATU entries */
158bc065 3007 err = _mv88e6xxx_atu_flush(ps, 0, true);
48ace4ef 3008 if (err < 0)
c161d0a5
VD		 3009 goto unlock;
3010
6b17e864 3011 /* Clear all the VTU and STU entries */
158bc065 3012 err = _mv88e6xxx_vtu_stu_flush(ps);
6b17e864 3013unlock:
24751e29 3014 mutex_unlock(&ps->smi_mutex);
db687a56 3015
48ace4ef 3016 return err;
54d792f2
AL		 3017}
3018
158bc065 3019int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps, bool ppu_active)
143a8307 3020{
143a8307 3021 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
158bc065 3022 struct gpio_desc *gpiod = ps->ds->pd->reset;
143a8307
AL		 3023 unsigned long timeout;
3024 int ret;
3025 int i;
3026
48ace4ef
AL		 3027 mutex_lock(&ps->smi_mutex);
3028
143a8307 3029 /* Set all ports to the disabled state. */
009a2b98 3030 for (i = 0; i < ps->info->num_ports; i++) {
158bc065 3031 ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL);
48ace4ef
AL		 3032 if (ret < 0)
3033 goto unlock;
3034
158bc065 3035 ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL,
48ace4ef
AL		 3036 ret & 0xfffc);
3037 if (ret)
3038 goto unlock;
143a8307
AL		 3039 }
3040
3041 /* Wait for transmit queues to drain. */
3042 usleep_range(2000, 4000);
3043
c8c1b39a
AL		 3044 /* If there is a gpio connected to the reset pin, toggle it */
3045 if (gpiod) {
3046 gpiod_set_value_cansleep(gpiod, 1);
3047 usleep_range(10000, 20000);
3048 gpiod_set_value_cansleep(gpiod, 0);
3049 usleep_range(10000, 20000);
3050 }
3051
143a8307
AL		 3052 /* Reset the switch. Keep the PPU active if requested. The PPU
3053 * needs to be active to support indirect phy register access
3054 * through global registers 0x18 and 0x19.
3055 */
3056 if (ppu_active)
158bc065 3057 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000);
143a8307 3058 else
158bc065 3059 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400);
48ace4ef
AL		 3060 if (ret)
3061 goto unlock;
143a8307
AL		 3062
3063 /* Wait up to one second for reset to complete. */
3064 timeout = jiffies + 1 * HZ;
3065 while (time_before(jiffies, timeout)) {
158bc065 3066 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00);
48ace4ef
AL		 3067 if (ret < 0)
3068 goto unlock;
3069
143a8307
AL		 3070 if ((ret & is_reset) == is_reset)
3071 break;
3072 usleep_range(1000, 2000);
3073 }
3074 if (time_after(jiffies, timeout))
48ace4ef
AL		 3075 ret = -ETIMEDOUT;
3076 else
3077 ret = 0;
3078unlock:
3079 mutex_unlock(&ps->smi_mutex);
143a8307 3080
48ace4ef 3081 return ret;
143a8307
AL		 3082}
3083
49143585
AL		 3084int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
3085{
3086 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3087 int ret;
3088
3898c148 3089 mutex_lock(&ps->smi_mutex);
158bc065 3090 ret = _mv88e6xxx_phy_page_read(ps, port, page, reg);
3898c148 3091 mutex_unlock(&ps->smi_mutex);
75baacf0 3092
49143585
AL		 3093 return ret;
3094}
3095
3096int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
3097 int reg, int val)
3098{
3099 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3100 int ret;
3101
3898c148 3102 mutex_lock(&ps->smi_mutex);
158bc065 3103 ret = _mv88e6xxx_phy_page_write(ps, port, page, reg, val);
3898c148 3104 mutex_unlock(&ps->smi_mutex);
75baacf0 3105
fd3a0ee4
AL		 3106 return ret;
3107}
3108
158bc065
AL		 3109static int mv88e6xxx_port_to_phy_addr(struct mv88e6xxx_priv_state *ps,
3110 int port)
fd3a0ee4 3111{
009a2b98 3112 if (port >= 0 && port < ps->info->num_ports)
fd3a0ee4
AL		 3113 return port;
3114 return -EINVAL;
3115}
3116
3117int
3118mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
3119{
3120 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158bc065 3121 int addr = mv88e6xxx_port_to_phy_addr(ps, port);
fd3a0ee4
AL		 3122 int ret;
3123
3124 if (addr < 0)
158bc065 3125 return 0xffff;
fd3a0ee4 3126
3898c148 3127 mutex_lock(&ps->smi_mutex);
8c9983a2
VD		 3128
3129 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3130 ret = mv88e6xxx_phy_read_ppu(ps, addr, regnum);
6d5834a1
VD		 3131 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3132 ret = _mv88e6xxx_phy_read_indirect(ps, addr, regnum);
8c9983a2
VD		 3133 else
3134 ret = _mv88e6xxx_phy_read(ps, addr, regnum);
3135
3898c148 3136 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 3137 return ret;
3138}
3139
3140int
3141mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
3142{
3143 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
158bc065 3144 int addr = mv88e6xxx_port_to_phy_addr(ps, port);
fd3a0ee4
AL		 3145 int ret;
3146
3147 if (addr < 0)
158bc065 3148 return 0xffff;
fd3a0ee4 3149
3898c148 3150 mutex_lock(&ps->smi_mutex);
8c9983a2
VD		 3151
3152 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3153 ret = mv88e6xxx_phy_write_ppu(ps, addr, regnum, val);
6d5834a1
VD		 3154 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3155 ret = _mv88e6xxx_phy_write_indirect(ps, addr, regnum, val);
8c9983a2
VD		 3156 else
3157 ret = _mv88e6xxx_phy_write(ps, addr, regnum, val);
3158
3898c148 3159 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 3160 return ret;
3161}
3162
c22995c5
GR		 3163#ifdef CONFIG_NET_DSA_HWMON
3164
3165static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3166{
3167 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3168 int ret;
3169 int val;
3170
3171 *temp = 0;
3172
3173 mutex_lock(&ps->smi_mutex);
3174
158bc065 3175 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x6);
c22995c5
GR		 3176 if (ret < 0)
3177 goto error;
3178
3179 /* Enable temperature sensor */
158bc065 3180 ret = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
c22995c5
GR		 3181 if (ret < 0)
3182 goto error;
3183
158bc065 3184 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret | (1 << 5));
c22995c5
GR		 3185 if (ret < 0)
3186 goto error;
3187
3188 /* Wait for temperature to stabilize */
3189 usleep_range(10000, 12000);
3190
158bc065 3191 val = _mv88e6xxx_phy_read(ps, 0x0, 0x1a);
c22995c5
GR		 3192 if (val < 0) {
3193 ret = val;
3194 goto error;
3195 }
3196
3197 /* Disable temperature sensor */
158bc065 3198 ret = _mv88e6xxx_phy_write(ps, 0x0, 0x1a, ret & ~(1 << 5));
c22995c5
GR		 3199 if (ret < 0)
3200 goto error;
3201
3202 *temp = ((val & 0x1f) - 5) * 5;
3203
3204error:
158bc065 3205 _mv88e6xxx_phy_write(ps, 0x0, 0x16, 0x0);
c22995c5
GR		 3206 mutex_unlock(&ps->smi_mutex);
3207 return ret;
3208}
3209
3210static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3211{
158bc065
AL		 3212 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3213 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3214 int ret;
3215
3216 *temp = 0;
3217
3218 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3219 if (ret < 0)
3220 return ret;
3221
3222 *temp = (ret & 0xff) - 25;
3223
3224 return 0;
3225}
3226
3227int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3228{
158bc065
AL		 3229 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3230
6594f615
VD		 3231 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP))
3232 return -EOPNOTSUPP;
3233
158bc065 3234 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
c22995c5
GR		 3235 return mv88e63xx_get_temp(ds, temp);
3236
3237 return mv88e61xx_get_temp(ds, temp);
3238}
3239
3240int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3241{
158bc065
AL		 3242 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3243 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3244 int ret;
3245
6594f615 3246 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3247 return -EOPNOTSUPP;
3248
3249 *temp = 0;
3250
3251 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3252 if (ret < 0)
3253 return ret;
3254
3255 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3256
3257 return 0;
3258}
3259
3260int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3261{
158bc065
AL		 3262 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3263 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3264 int ret;
3265
6594f615 3266 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3267 return -EOPNOTSUPP;
3268
3269 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3270 if (ret < 0)
3271 return ret;
3272 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3273 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3274 (ret & 0xe0ff) | (temp << 8));
3275}
3276
3277int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3278{
158bc065
AL		 3279 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3280 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
c22995c5
GR		 3281 int ret;
3282
6594f615 3283 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
c22995c5
GR		 3284 return -EOPNOTSUPP;
3285
3286 *alarm = false;
3287
3288 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3289 if (ret < 0)
3290 return ret;
3291
3292 *alarm = !!(ret & 0x40);
3293
3294 return 0;
3295}
3296#endif /* CONFIG_NET_DSA_HWMON */
3297
f6271e67
VD		 3298static const struct mv88e6xxx_info *
3299mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table,
0209d144 3300 unsigned int num)
b9b37713 3301{
a439c061 3302 int i;
b9b37713 3303
b9b37713 3304 for (i = 0; i < num; ++i)
f6271e67
VD		 3305 if (table[i].prod_num == prod_num)
3306 return &table[i];
b9b37713 3307
b9b37713
VD		 3308 return NULL;
3309}
3310
0209d144
VD		 3311const char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev,
3312 int sw_addr, void **priv,
f6271e67 3313 const struct mv88e6xxx_info *table,
0209d144 3314 unsigned int num)
a77d43f1 3315{
f6271e67 3316 const struct mv88e6xxx_info *info;
a77d43f1 3317 struct mv88e6xxx_priv_state *ps;
a439c061 3318 struct mii_bus *bus;
0209d144 3319 const char *name;
a439c061 3320 int id, prod_num, rev;
a77d43f1 3321
a439c061 3322 bus = dsa_host_dev_to_mii_bus(host_dev);
c156913b
AL		 3323 if (!bus)
3324 return NULL;
3325
a439c061
VD		 3326 id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3327 if (id < 0)
3328 return NULL;
3329
3330 prod_num = (id & 0xfff0) >> 4;
3331 rev = id & 0x000f;
3332
f6271e67
VD		 3333 info = mv88e6xxx_lookup_info(prod_num, table, num);
3334 if (!info)
a439c061
VD		 3335 return NULL;
3336
f6271e67
VD		 3337 name = info->name;
3338
a439c061
VD		 3339 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3340 if (!ps)
3341 return NULL;
3342
3343 ps->bus = bus;
3344 ps->sw_addr = sw_addr;
f6271e67 3345 ps->info = info;
a439c061
VD		 3346
3347 *priv = ps;
3348
3349 dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3350 prod_num, name, rev);
3351
a77d43f1
AL		 3352 return name;
3353}
3354
98e67308
BH		 3355static int __init mv88e6xxx_init(void)
3356{
3357#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3358 register_switch_driver(&mv88e6131_switch_driver);
3359#endif
ca3dfa51
AL		 3360#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3361 register_switch_driver(&mv88e6123_switch_driver);
42f27253 3362#endif
3ad50cca
GR		 3363#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3364 register_switch_driver(&mv88e6352_switch_driver);
3365#endif
42f27253
AL		 3366#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3367 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 3368#endif
3369 return 0;
3370}
3371module_init(mv88e6xxx_init);
3372
3373static void __exit mv88e6xxx_cleanup(void)
3374{
42f27253
AL		 3375#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3376 unregister_switch_driver(&mv88e6171_switch_driver);
3377#endif
4212b543
VD		 3378#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3379 unregister_switch_driver(&mv88e6352_switch_driver);
3380#endif
ca3dfa51
AL		 3381#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3382 unregister_switch_driver(&mv88e6123_switch_driver);
98e67308
BH		 3383#endif
3384#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3385 unregister_switch_driver(&mv88e6131_switch_driver);
3386#endif
3387}
3388module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 3389
3390MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3391MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3392MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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