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net: dsa: mv88e6xxx: implement port_fdb_dump
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
87c8cefb 14#include <linux/debugfs.h>
19b2f97e 15#include <linux/delay.h>
defb05b9 16#include <linux/etherdevice.h>
dea87024 17#include <linux/ethtool.h>
facd95b2 18#include <linux/if_bridge.h>
19b2f97e 19#include <linux/jiffies.h>
91da11f8 20#include <linux/list.h>
2bbba277 21#include <linux/module.h>
91da11f8
LB		 22#include <linux/netdevice.h>
23#include <linux/phy.h>
87c8cefb 24#include <linux/seq_file.h>
c8f0b869 25#include <net/dsa.h>
1f36faf2 26#include <net/switchdev.h>
91da11f8
LB		 27#include "mv88e6xxx.h"
28
16fe24fc
AL		 29/* MDIO bus access can be nested in the case of PHYs connected to the
30 * internal MDIO bus of the switch, which is accessed via MDIO bus of
31 * the Ethernet interface. Avoid lockdep false positives by using
32 * mutex_lock_nested().
33 */
34static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
35{
36 int ret;
37
38 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
39 ret = bus->read(bus, addr, regnum);
40 mutex_unlock(&bus->mdio_lock);
41
42 return ret;
43}
44
45static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
46 u16 val)
47{
48 int ret;
49
50 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
51 ret = bus->write(bus, addr, regnum, val);
52 mutex_unlock(&bus->mdio_lock);
53
54 return ret;
55}
56
3675c8d7 57/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 58 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
59 * will be directly accessible on some {device address,register address}
60 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
61 * will only respond to SMI transactions to that specific address, and
62 * an indirect addressing mechanism needs to be used to access its
63 * registers.
64 */
65static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
66{
67 int ret;
68 int i;
69
70 for (i = 0; i < 16; i++) {
16fe24fc 71 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
91da11f8
LB		 72 if (ret < 0)
73 return ret;
74
cca8b133 75 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 76 return 0;
77 }
78
79 return -ETIMEDOUT;
80}
81
82int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
83{
84 int ret;
85
86 if (sw_addr == 0)
16fe24fc 87 return mv88e6xxx_mdiobus_read(bus, addr, reg);
91da11f8 88
3675c8d7 89 /* Wait for the bus to become free. */
91da11f8
LB		 90 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
91 if (ret < 0)
92 return ret;
93
3675c8d7 94 /* Transmit the read command. */
16fe24fc
AL		 95 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
96 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 97 if (ret < 0)
98 return ret;
99
3675c8d7 100 /* Wait for the read command to complete. */
91da11f8
LB		 101 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
102 if (ret < 0)
103 return ret;
104
3675c8d7 105 /* Read the data. */
16fe24fc 106 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
91da11f8
LB		 107 if (ret < 0)
108 return ret;
109
110 return ret & 0xffff;
111}
112
8d6d09e7
GR		 113/* Must be called with SMI mutex held */
114static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
91da11f8 115{
b184e497 116 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8
LB		 117 int ret;
118
b184e497
GR		 119 if (bus == NULL)
120 return -EINVAL;
121
b184e497 122 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
bb92ea5e
VD		 123 if (ret < 0)
124 return ret;
125
126 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
127 addr, reg, ret);
128
91da11f8
LB		 129 return ret;
130}
131
8d6d09e7
GR		 132int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
133{
134 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
135 int ret;
136
137 mutex_lock(&ps->smi_mutex);
138 ret = _mv88e6xxx_reg_read(ds, addr, reg);
139 mutex_unlock(&ps->smi_mutex);
140
141 return ret;
142}
143
91da11f8
LB		 144int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
145 int reg, u16 val)
146{
147 int ret;
148
149 if (sw_addr == 0)
16fe24fc 150 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
91da11f8 151
3675c8d7 152 /* Wait for the bus to become free. */
91da11f8
LB		 153 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
154 if (ret < 0)
155 return ret;
156
3675c8d7 157 /* Transmit the data to write. */
16fe24fc 158 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 159 if (ret < 0)
160 return ret;
161
3675c8d7 162 /* Transmit the write command. */
16fe24fc
AL		 163 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
164 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 165 if (ret < 0)
166 return ret;
167
3675c8d7 168 /* Wait for the write command to complete. */
91da11f8
LB		 169 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
170 if (ret < 0)
171 return ret;
172
173 return 0;
174}
175
8d6d09e7
GR		 176/* Must be called with SMI mutex held */
177static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
178 u16 val)
91da11f8 179{
b184e497 180 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 181
b184e497
GR		 182 if (bus == NULL)
183 return -EINVAL;
184
bb92ea5e
VD		 185 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
186 addr, reg, val);
187
8d6d09e7
GR		 188 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
189}
190
191int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
192{
193 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
194 int ret;
195
91da11f8 196 mutex_lock(&ps->smi_mutex);
8d6d09e7 197 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
91da11f8
LB		 198 mutex_unlock(&ps->smi_mutex);
199
200 return ret;
201}
202
2e5f0320
LB		 203int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
204{
cca8b133
AL		 205 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
206 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
207 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2e5f0320
LB		 208
209 return 0;
210}
211
91da11f8
LB		 212int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
213{
214 int i;
215 int ret;
216
217 for (i = 0; i < 6; i++) {
218 int j;
219
3675c8d7 220 /* Write the MAC address byte. */
cca8b133
AL		 221 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
222 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
91da11f8 223
3675c8d7 224 /* Wait for the write to complete. */
91da11f8 225 for (j = 0; j < 16; j++) {
cca8b133
AL		 226 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
227 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 228 break;
229 }
230 if (j == 16)
231 return -ETIMEDOUT;
232 }
233
234 return 0;
235}
236
3898c148 237/* Must be called with SMI mutex held */
fd3a0ee4 238static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
91da11f8
LB		 239{
240 if (addr >= 0)
3898c148 241 return _mv88e6xxx_reg_read(ds, addr, regnum);
91da11f8
LB		 242 return 0xffff;
243}
244
3898c148 245/* Must be called with SMI mutex held */
fd3a0ee4
AL		 246static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
247 u16 val)
91da11f8
LB		 248{
249 if (addr >= 0)
3898c148 250 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
91da11f8
LB		 251 return 0;
252}
253
2e5f0320
LB		 254#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
255static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
256{
257 int ret;
19b2f97e 258 unsigned long timeout;
2e5f0320 259
cca8b133
AL		 260 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
261 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
262 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 263
19b2f97e
BG		 264 timeout = jiffies + 1 * HZ;
265 while (time_before(jiffies, timeout)) {
cca8b133 266 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 267 usleep_range(1000, 2000);
cca8b133
AL		 268 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
269 GLOBAL_STATUS_PPU_POLLING)
85686581 270 return 0;
2e5f0320
LB		 271 }
272
273 return -ETIMEDOUT;
274}
275
276static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
277{
278 int ret;
19b2f97e 279 unsigned long timeout;
2e5f0320 280
cca8b133
AL		 281 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
282 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 283
19b2f97e
BG		 284 timeout = jiffies + 1 * HZ;
285 while (time_before(jiffies, timeout)) {
cca8b133 286 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 287 usleep_range(1000, 2000);
cca8b133
AL		 288 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
289 GLOBAL_STATUS_PPU_POLLING)
85686581 290 return 0;
2e5f0320
LB		 291 }
292
293 return -ETIMEDOUT;
294}
295
296static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
297{
298 struct mv88e6xxx_priv_state *ps;
299
300 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
301 if (mutex_trylock(&ps->ppu_mutex)) {
85686581 302 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
2e5f0320 303
85686581
BG		 304 if (mv88e6xxx_ppu_enable(ds) == 0)
305 ps->ppu_disabled = 0;
306 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 307 }
308}
309
310static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
311{
312 struct mv88e6xxx_priv_state *ps = (void *)_ps;
313
314 schedule_work(&ps->ppu_work);
315}
316
317static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
318{
a22adce5 319 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 320 int ret;
321
322 mutex_lock(&ps->ppu_mutex);
323
3675c8d7 324 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 325 * we can access the PHY registers. If it was already
326 * disabled, cancel the timer that is going to re-enable
327 * it.
328 */
329 if (!ps->ppu_disabled) {
85686581
BG		 330 ret = mv88e6xxx_ppu_disable(ds);
331 if (ret < 0) {
332 mutex_unlock(&ps->ppu_mutex);
333 return ret;
334 }
335 ps->ppu_disabled = 1;
2e5f0320 336 } else {
85686581
BG		 337 del_timer(&ps->ppu_timer);
338 ret = 0;
2e5f0320
LB		 339 }
340
341 return ret;
342}
343
344static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
345{
a22adce5 346 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 347
3675c8d7 348 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 349 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
350 mutex_unlock(&ps->ppu_mutex);
351}
352
353void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
354{
a22adce5 355 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 356
357 mutex_init(&ps->ppu_mutex);
358 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
359 init_timer(&ps->ppu_timer);
360 ps->ppu_timer.data = (unsigned long)ps;
361 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
362}
363
364int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
365{
366 int ret;
367
368 ret = mv88e6xxx_ppu_access_get(ds);
369 if (ret >= 0) {
85686581
BG		 370 ret = mv88e6xxx_reg_read(ds, addr, regnum);
371 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 372 }
373
374 return ret;
375}
376
377int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
378 int regnum, u16 val)
379{
380 int ret;
381
382 ret = mv88e6xxx_ppu_access_get(ds);
383 if (ret >= 0) {
85686581
BG		 384 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
385 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 386 }
387
388 return ret;
389}
390#endif
391
54d792f2
AL		 392static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
393{
394 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
395
396 switch (ps->id) {
397 case PORT_SWITCH_ID_6031:
398 case PORT_SWITCH_ID_6061:
399 case PORT_SWITCH_ID_6035:
400 case PORT_SWITCH_ID_6065:
401 return true;
402 }
403 return false;
404}
405
406static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
407{
408 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
409
410 switch (ps->id) {
411 case PORT_SWITCH_ID_6092:
412 case PORT_SWITCH_ID_6095:
413 return true;
414 }
415 return false;
416}
417
418static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
419{
420 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
421
422 switch (ps->id) {
423 case PORT_SWITCH_ID_6046:
424 case PORT_SWITCH_ID_6085:
425 case PORT_SWITCH_ID_6096:
426 case PORT_SWITCH_ID_6097:
427 return true;
428 }
429 return false;
430}
431
432static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
433{
434 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
435
436 switch (ps->id) {
437 case PORT_SWITCH_ID_6123:
438 case PORT_SWITCH_ID_6161:
439 case PORT_SWITCH_ID_6165:
440 return true;
441 }
442 return false;
443}
444
445static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
446{
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
448
449 switch (ps->id) {
450 case PORT_SWITCH_ID_6121:
451 case PORT_SWITCH_ID_6122:
452 case PORT_SWITCH_ID_6152:
453 case PORT_SWITCH_ID_6155:
454 case PORT_SWITCH_ID_6182:
455 case PORT_SWITCH_ID_6185:
456 case PORT_SWITCH_ID_6108:
457 case PORT_SWITCH_ID_6131:
458 return true;
459 }
460 return false;
461}
462
c22995c5 463static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
7c3d0d67
AK		 464{
465 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
466
467 switch (ps->id) {
468 case PORT_SWITCH_ID_6320:
469 case PORT_SWITCH_ID_6321:
470 return true;
471 }
472 return false;
473}
474
54d792f2
AL		 475static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
476{
477 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
478
479 switch (ps->id) {
480 case PORT_SWITCH_ID_6171:
481 case PORT_SWITCH_ID_6175:
482 case PORT_SWITCH_ID_6350:
483 case PORT_SWITCH_ID_6351:
484 return true;
485 }
486 return false;
487}
488
f3a8b6b6
AL		 489static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
490{
491 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
492
493 switch (ps->id) {
f3a8b6b6
AL		 494 case PORT_SWITCH_ID_6172:
495 case PORT_SWITCH_ID_6176:
54d792f2
AL		 496 case PORT_SWITCH_ID_6240:
497 case PORT_SWITCH_ID_6352:
f3a8b6b6
AL		 498 return true;
499 }
500 return false;
501}
502
dea87024
AL		 503/* We expect the switch to perform auto negotiation if there is a real
504 * phy. However, in the case of a fixed link phy, we force the port
505 * settings from the fixed link settings.
506 */
507void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
508 struct phy_device *phydev)
509{
510 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 511 u32 reg;
512 int ret;
dea87024
AL		 513
514 if (!phy_is_pseudo_fixed_link(phydev))
515 return;
516
517 mutex_lock(&ps->smi_mutex);
518
519 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
520 if (ret < 0)
521 goto out;
522
523 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
524 PORT_PCS_CTRL_FORCE_LINK |
525 PORT_PCS_CTRL_DUPLEX_FULL |
526 PORT_PCS_CTRL_FORCE_DUPLEX |
527 PORT_PCS_CTRL_UNFORCED);
528
529 reg |= PORT_PCS_CTRL_FORCE_LINK;
530 if (phydev->link)
531 reg |= PORT_PCS_CTRL_LINK_UP;
532
533 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
534 goto out;
535
536 switch (phydev->speed) {
537 case SPEED_1000:
538 reg |= PORT_PCS_CTRL_1000;
539 break;
540 case SPEED_100:
541 reg |= PORT_PCS_CTRL_100;
542 break;
543 case SPEED_10:
544 reg |= PORT_PCS_CTRL_10;
545 break;
546 default:
547 pr_info("Unknown speed");
548 goto out;
549 }
550
551 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
552 if (phydev->duplex == DUPLEX_FULL)
553 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
554
e7e72ac0
AL		 555 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
556 (port >= ps->num_ports - 2)) {
557 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
558 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
559 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
560 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
561 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
562 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
563 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
564 }
dea87024
AL		 565 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
566
567out:
568 mutex_unlock(&ps->smi_mutex);
569}
570
31888234
AL		 571/* Must be called with SMI mutex held */
572static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
91da11f8
LB		 573{
574 int ret;
575 int i;
576
577 for (i = 0; i < 10; i++) {
31888234 578 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 579 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 580 return 0;
581 }
582
583 return -ETIMEDOUT;
584}
585
31888234
AL		 586/* Must be called with SMI mutex held */
587static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
91da11f8
LB		 588{
589 int ret;
590
7c3d0d67 591 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
f3a8b6b6
AL		 592 port = (port + 1) << 5;
593
3675c8d7 594 /* Snapshot the hardware statistics counters for this port. */
31888234
AL		 595 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
596 GLOBAL_STATS_OP_CAPTURE_PORT |
597 GLOBAL_STATS_OP_HIST_RX_TX | port);
598 if (ret < 0)
599 return ret;
91da11f8 600
3675c8d7 601 /* Wait for the snapshotting to complete. */
31888234 602 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 603 if (ret < 0)
604 return ret;
605
606 return 0;
607}
608
31888234
AL		 609/* Must be called with SMI mutex held */
610static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
91da11f8
LB		 611{
612 u32 _val;
613 int ret;
614
615 *val = 0;
616
31888234
AL		 617 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
618 GLOBAL_STATS_OP_READ_CAPTURED |
619 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 620 if (ret < 0)
621 return;
622
31888234 623 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 624 if (ret < 0)
625 return;
626
31888234 627 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 628 if (ret < 0)
629 return;
630
631 _val = ret << 16;
632
31888234 633 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 634 if (ret < 0)
635 return;
636
637 *val = _val | ret;
638}
639
e413e7e1
AL		 640static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
641 { "in_good_octets", 8, 0x00, },
642 { "in_bad_octets", 4, 0x02, },
643 { "in_unicast", 4, 0x04, },
644 { "in_broadcasts", 4, 0x06, },
645 { "in_multicasts", 4, 0x07, },
646 { "in_pause", 4, 0x16, },
647 { "in_undersize", 4, 0x18, },
648 { "in_fragments", 4, 0x19, },
649 { "in_oversize", 4, 0x1a, },
650 { "in_jabber", 4, 0x1b, },
651 { "in_rx_error", 4, 0x1c, },
652 { "in_fcs_error", 4, 0x1d, },
653 { "out_octets", 8, 0x0e, },
654 { "out_unicast", 4, 0x10, },
655 { "out_broadcasts", 4, 0x13, },
656 { "out_multicasts", 4, 0x12, },
657 { "out_pause", 4, 0x15, },
658 { "excessive", 4, 0x11, },
659 { "collisions", 4, 0x1e, },
660 { "deferred", 4, 0x05, },
661 { "single", 4, 0x14, },
662 { "multiple", 4, 0x17, },
663 { "out_fcs_error", 4, 0x03, },
664 { "late", 4, 0x1f, },
665 { "hist_64bytes", 4, 0x08, },
666 { "hist_65_127bytes", 4, 0x09, },
667 { "hist_128_255bytes", 4, 0x0a, },
668 { "hist_256_511bytes", 4, 0x0b, },
669 { "hist_512_1023bytes", 4, 0x0c, },
670 { "hist_1024_max_bytes", 4, 0x0d, },
671 /* Not all devices have the following counters */
672 { "sw_in_discards", 4, 0x110, },
673 { "sw_in_filtered", 2, 0x112, },
674 { "sw_out_filtered", 2, 0x113, },
675
676};
677
678static bool have_sw_in_discards(struct dsa_switch *ds)
679{
680 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
681
682 switch (ps->id) {
cca8b133
AL		 683 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
684 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
685 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
686 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
687 case PORT_SWITCH_ID_6352:
e413e7e1
AL		 688 return true;
689 default:
690 return false;
691 }
692}
693
694static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
695 int nr_stats,
696 struct mv88e6xxx_hw_stat *stats,
697 int port, uint8_t *data)
91da11f8
LB		 698{
699 int i;
700
701 for (i = 0; i < nr_stats; i++) {
702 memcpy(data + i * ETH_GSTRING_LEN,
703 stats[i].string, ETH_GSTRING_LEN);
704 }
705}
706
80c4627b
AL		 707static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
708 int stat,
709 struct mv88e6xxx_hw_stat *stats,
710 int port)
711{
712 struct mv88e6xxx_hw_stat *s = stats + stat;
713 u32 low;
714 u32 high = 0;
715 int ret;
716 u64 value;
717
718 if (s->reg >= 0x100) {
719 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
720 s->reg - 0x100);
721 if (ret < 0)
722 return UINT64_MAX;
723
724 low = ret;
725 if (s->sizeof_stat == 4) {
726 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
727 s->reg - 0x100 + 1);
728 if (ret < 0)
729 return UINT64_MAX;
730 high = ret;
731 }
732 } else {
733 _mv88e6xxx_stats_read(ds, s->reg, &low);
734 if (s->sizeof_stat == 8)
735 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
736 }
737 value = (((u64)high) << 16) | low;
738 return value;
739}
740
e413e7e1
AL		 741static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
742 int nr_stats,
743 struct mv88e6xxx_hw_stat *stats,
744 int port, uint64_t *data)
91da11f8 745{
a22adce5 746 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
91da11f8
LB		 747 int ret;
748 int i;
749
31888234 750 mutex_lock(&ps->smi_mutex);
91da11f8 751
31888234 752 ret = _mv88e6xxx_stats_snapshot(ds, port);
91da11f8 753 if (ret < 0) {
31888234 754 mutex_unlock(&ps->smi_mutex);
91da11f8
LB		 755 return;
756 }
757
3675c8d7 758 /* Read each of the counters. */
80c4627b
AL		 759 for (i = 0; i < nr_stats; i++)
760 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
91da11f8 761
31888234 762 mutex_unlock(&ps->smi_mutex);
91da11f8 763}
98e67308 764
e413e7e1
AL		 765/* All the statistics in the table */
766void
767mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
768{
769 if (have_sw_in_discards(ds))
770 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
771 mv88e6xxx_hw_stats, port, data);
772 else
773 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
774 mv88e6xxx_hw_stats, port, data);
775}
776
777int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
778{
779 if (have_sw_in_discards(ds))
780 return ARRAY_SIZE(mv88e6xxx_hw_stats);
781 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
782}
783
784void
785mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
786 int port, uint64_t *data)
787{
788 if (have_sw_in_discards(ds))
789 _mv88e6xxx_get_ethtool_stats(
790 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
791 mv88e6xxx_hw_stats, port, data);
792 else
793 _mv88e6xxx_get_ethtool_stats(
794 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
795 mv88e6xxx_hw_stats, port, data);
796}
797
a1ab91f3
GR		 798int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
799{
800 return 32 * sizeof(u16);
801}
802
803void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
804 struct ethtool_regs *regs, void *_p)
805{
806 u16 *p = _p;
807 int i;
808
809 regs->version = 0;
810
811 memset(p, 0xff, 32 * sizeof(u16));
812
813 for (i = 0; i < 32; i++) {
814 int ret;
815
816 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
817 if (ret >= 0)
818 p[i] = ret;
819 }
820}
821
3898c148
AL		 822/* Must be called with SMI lock held */
823static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
824 u16 mask)
f3044683
AL		 825{
826 unsigned long timeout = jiffies + HZ / 10;
827
828 while (time_before(jiffies, timeout)) {
829 int ret;
830
3898c148
AL		 831 ret = _mv88e6xxx_reg_read(ds, reg, offset);
832 if (ret < 0)
833 return ret;
f3044683
AL		 834 if (!(ret & mask))
835 return 0;
836
837 usleep_range(1000, 2000);
838 }
839 return -ETIMEDOUT;
840}
841
3898c148
AL		 842static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
843{
844 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
845 int ret;
846
847 mutex_lock(&ps->smi_mutex);
848 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
849 mutex_unlock(&ps->smi_mutex);
850
851 return ret;
852}
853
854static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
f3044683 855{
3898c148
AL		 856 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
857 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 858}
859
860int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
861{
cca8b133
AL		 862 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
863 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 864}
865
866int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
867{
cca8b133
AL		 868 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
869 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 870}
871
facd95b2
GR		 872/* Must be called with SMI lock held */
873static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
874{
cca8b133
AL		 875 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
876 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 877}
878
56d95e22
AL		 879/* Must be called with SMI lock held */
880static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds)
881{
882 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
883 GLOBAL2_SCRATCH_BUSY);
884}
885
3898c148 886/* Must be called with SMI mutex held */
fd3a0ee4
AL		 887static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
888 int regnum)
f3044683
AL		 889{
890 int ret;
891
3898c148
AL		 892 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
893 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
894 regnum);
895 if (ret < 0)
896 return ret;
f3044683 897
3898c148 898 ret = _mv88e6xxx_phy_wait(ds);
f3044683
AL		 899 if (ret < 0)
900 return ret;
901
3898c148 902 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
f3044683
AL		 903}
904
3898c148 905/* Must be called with SMI mutex held */
fd3a0ee4
AL		 906static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
907 int regnum, u16 val)
f3044683 908{
3898c148
AL		 909 int ret;
910
911 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
912 if (ret < 0)
913 return ret;
f3044683 914
3898c148
AL		 915 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
916 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
917 regnum);
918
919 return _mv88e6xxx_phy_wait(ds);
f3044683
AL		 920}
921
11b3b45d
GR		 922int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
923{
2f40c698 924 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 925 int reg;
926
3898c148 927 mutex_lock(&ps->smi_mutex);
2f40c698
AL		 928
929 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
11b3b45d 930 if (reg < 0)
2f40c698 931 goto out;
11b3b45d
GR		 932
933 e->eee_enabled = !!(reg & 0x0200);
934 e->tx_lpi_enabled = !!(reg & 0x0100);
935
3898c148 936 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
11b3b45d 937 if (reg < 0)
2f40c698 938 goto out;
11b3b45d 939
cca8b133 940 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 941 reg = 0;
11b3b45d 942
2f40c698 943out:
3898c148 944 mutex_unlock(&ps->smi_mutex);
2f40c698 945 return reg;
11b3b45d
GR		 946}
947
948int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
949 struct phy_device *phydev, struct ethtool_eee *e)
950{
2f40c698
AL		 951 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
952 int reg;
11b3b45d
GR		 953 int ret;
954
3898c148 955 mutex_lock(&ps->smi_mutex);
11b3b45d 956
2f40c698
AL		 957 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
958 if (ret < 0)
959 goto out;
960
961 reg = ret & ~0x0300;
962 if (e->eee_enabled)
963 reg |= 0x0200;
964 if (e->tx_lpi_enabled)
965 reg |= 0x0100;
966
967 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
968out:
3898c148 969 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 970
971 return ret;
11b3b45d
GR		 972}
973
70cc99d1 974static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
facd95b2
GR		 975{
976 int ret;
977
cca8b133 978 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 979 if (ret < 0)
980 return ret;
981
982 return _mv88e6xxx_atu_wait(ds);
983}
984
37705b73
VD		 985static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
986 struct mv88e6xxx_atu_entry *entry)
987{
988 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
989
990 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
991 unsigned int mask, shift;
992
993 if (entry->trunk) {
994 data |= GLOBAL_ATU_DATA_TRUNK;
995 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
996 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
997 } else {
998 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
999 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1000 }
1001
1002 data |= (entry->portv_trunkid << shift) & mask;
1003 }
1004
1005 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1006}
1007
7fb5e755
VD		 1008static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1009 struct mv88e6xxx_atu_entry *entry,
1010 bool static_too)
facd95b2 1011{
7fb5e755
VD		 1012 int op;
1013 int err;
facd95b2 1014
7fb5e755
VD		 1015 err = _mv88e6xxx_atu_wait(ds);
1016 if (err)
1017 return err;
facd95b2 1018
7fb5e755
VD		 1019 err = _mv88e6xxx_atu_data_write(ds, entry);
1020 if (err)
1021 return err;
1022
1023 if (entry->fid) {
1024 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1025 entry->fid);
1026 if (err)
1027 return err;
1028
1029 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1030 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1031 } else {
1032 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1033 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1034 }
1035
1036 return _mv88e6xxx_atu_cmd(ds, op);
1037}
1038
1039static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1040{
1041 struct mv88e6xxx_atu_entry entry = {
1042 .fid = fid,
1043 .state = 0, /* EntryState bits must be 0 */
1044 };
70cc99d1 1045
7fb5e755
VD		 1046 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1047}
1048
9f4d55d2
VD		 1049static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1050 int to_port, bool static_too)
1051{
1052 struct mv88e6xxx_atu_entry entry = {
1053 .trunk = false,
1054 .fid = fid,
1055 };
1056
1057 /* EntryState bits must be 0xF */
1058 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1059
1060 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1061 entry.portv_trunkid = (to_port & 0x0f) << 4;
1062 entry.portv_trunkid |= from_port & 0x0f;
1063
1064 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1065}
1066
1067static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1068 bool static_too)
1069{
1070 /* Destination port 0xF means remove the entries */
1071 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1072}
1073
facd95b2
GR		 1074static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1075{
1076 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
c3ffe6d2 1077 int reg, ret = 0;
facd95b2
GR		 1078 u8 oldstate;
1079
1080 mutex_lock(&ps->smi_mutex);
1081
cca8b133 1082 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
538cc282
GR		 1083 if (reg < 0) {
1084 ret = reg;
facd95b2 1085 goto abort;
538cc282 1086 }
facd95b2 1087
cca8b133 1088 oldstate = reg & PORT_CONTROL_STATE_MASK;
facd95b2
GR		 1089 if (oldstate != state) {
1090 /* Flush forwarding database if we're moving a port
1091 * from Learning or Forwarding state to Disabled or
1092 * Blocking or Listening state.
1093 */
cca8b133
AL		 1094 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1095 state <= PORT_CONTROL_STATE_BLOCKING) {
2b8157b1 1096 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
facd95b2
GR		 1097 if (ret)
1098 goto abort;
1099 }
cca8b133
AL		 1100 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1101 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1102 reg);
facd95b2
GR		 1103 }
1104
1105abort:
1106 mutex_unlock(&ps->smi_mutex);
1107 return ret;
1108}
1109
ede8098d
VD		 1110static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port,
1111 u16 output_ports)
facd95b2
GR		 1112{
1113 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
ede8098d
VD		 1114 const u16 mask = (1 << ps->num_ports) - 1;
1115 int reg;
facd95b2 1116
ede8098d
VD		 1117 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1118 if (reg < 0)
1119 return reg;
facd95b2 1120
ede8098d
VD		 1121 reg &= ~mask;
1122 reg |= output_ports & mask;
facd95b2 1123
ede8098d 1124 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1125}
1126
facd95b2
GR		 1127int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1128{
1129 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1130 int stp_state;
1131
1132 switch (state) {
1133 case BR_STATE_DISABLED:
cca8b133 1134 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1135 break;
1136 case BR_STATE_BLOCKING:
1137 case BR_STATE_LISTENING:
cca8b133 1138 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1139 break;
1140 case BR_STATE_LEARNING:
cca8b133 1141 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1142 break;
1143 case BR_STATE_FORWARDING:
1144 default:
cca8b133 1145 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1146 break;
1147 }
1148
1149 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1150
1151 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1152 * so we can not update the port state directly but need to schedule it.
1153 */
1154 ps->port_state[port] = stp_state;
1155 set_bit(port, &ps->port_state_update_mask);
1156 schedule_work(&ps->bridge_work);
1157
1158 return 0;
1159}
1160
b8fee957
VD		 1161int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1162{
1163 int ret;
1164
1165 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1166 if (ret < 0)
1167 return ret;
1168
1169 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1170
1171 return 0;
1172}
1173
0d3b33e6
VD		 1174int mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1175{
1176 return mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1177 pvid & PORT_DEFAULT_VLAN_MASK);
1178}
1179
6b17e864
VD		 1180static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1181{
1182 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1183 GLOBAL_VTU_OP_BUSY);
1184}
1185
1186static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1187{
1188 int ret;
1189
1190 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1191 if (ret < 0)
1192 return ret;
1193
1194 return _mv88e6xxx_vtu_wait(ds);
1195}
1196
1197static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1198{
1199 int ret;
1200
1201 ret = _mv88e6xxx_vtu_wait(ds);
1202 if (ret < 0)
1203 return ret;
1204
1205 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1206}
1207
b8fee957
VD		 1208static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1209 struct mv88e6xxx_vtu_stu_entry *entry,
1210 unsigned int nibble_offset)
1211{
1212 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1213 u16 regs[3];
1214 int i;
1215 int ret;
1216
1217 for (i = 0; i < 3; ++i) {
1218 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1219 GLOBAL_VTU_DATA_0_3 + i);
1220 if (ret < 0)
1221 return ret;
1222
1223 regs[i] = ret;
1224 }
1225
1226 for (i = 0; i < ps->num_ports; ++i) {
1227 unsigned int shift = (i % 4) * 4 + nibble_offset;
1228 u16 reg = regs[i / 4];
1229
1230 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1231 }
1232
1233 return 0;
1234}
1235
7dad08d7
VD		 1236static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1237 struct mv88e6xxx_vtu_stu_entry *entry,
1238 unsigned int nibble_offset)
1239{
1240 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1241 u16 regs[3] = { 0 };
1242 int i;
1243 int ret;
1244
1245 for (i = 0; i < ps->num_ports; ++i) {
1246 unsigned int shift = (i % 4) * 4 + nibble_offset;
1247 u8 data = entry->data[i];
1248
1249 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1250 }
1251
1252 for (i = 0; i < 3; ++i) {
1253 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1254 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1255 if (ret < 0)
1256 return ret;
1257 }
1258
1259 return 0;
1260}
1261
36d04ba1
VD		 1262static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1263{
1264 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1265 vid & GLOBAL_VTU_VID_MASK);
1266}
1267
1268static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
b8fee957
VD		 1269 struct mv88e6xxx_vtu_stu_entry *entry)
1270{
1271 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1272 int ret;
1273
1274 ret = _mv88e6xxx_vtu_wait(ds);
1275 if (ret < 0)
1276 return ret;
1277
b8fee957
VD		 1278 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1279 if (ret < 0)
1280 return ret;
1281
1282 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1283 if (ret < 0)
1284 return ret;
1285
1286 next.vid = ret & GLOBAL_VTU_VID_MASK;
1287 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1288
1289 if (next.valid) {
1290 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1291 if (ret < 0)
1292 return ret;
1293
1294 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1295 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1296 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1297 GLOBAL_VTU_FID);
1298 if (ret < 0)
1299 return ret;
1300
1301 next.fid = ret & GLOBAL_VTU_FID_MASK;
1302
1303 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1304 GLOBAL_VTU_SID);
1305 if (ret < 0)
1306 return ret;
1307
1308 next.sid = ret & GLOBAL_VTU_SID_MASK;
1309 }
1310 }
1311
1312 *entry = next;
1313 return 0;
1314}
1315
7dad08d7
VD		 1316static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1317 struct mv88e6xxx_vtu_stu_entry *entry)
1318{
1319 u16 reg = 0;
1320 int ret;
1321
1322 ret = _mv88e6xxx_vtu_wait(ds);
1323 if (ret < 0)
1324 return ret;
1325
1326 if (!entry->valid)
1327 goto loadpurge;
1328
1329 /* Write port member tags */
1330 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1331 if (ret < 0)
1332 return ret;
1333
1334 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1335 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1336 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1337 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1338 if (ret < 0)
1339 return ret;
1340
1341 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1342 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1343 if (ret < 0)
1344 return ret;
1345 }
1346
1347 reg = GLOBAL_VTU_VID_VALID;
1348loadpurge:
1349 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1350 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1351 if (ret < 0)
1352 return ret;
1353
1354 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1355}
1356
0d3b33e6
VD		 1357static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1358 struct mv88e6xxx_vtu_stu_entry *entry)
1359{
1360 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1361 int ret;
1362
1363 ret = _mv88e6xxx_vtu_wait(ds);
1364 if (ret < 0)
1365 return ret;
1366
1367 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1368 sid & GLOBAL_VTU_SID_MASK);
1369 if (ret < 0)
1370 return ret;
1371
1372 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1373 if (ret < 0)
1374 return ret;
1375
1376 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1377 if (ret < 0)
1378 return ret;
1379
1380 next.sid = ret & GLOBAL_VTU_SID_MASK;
1381
1382 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1383 if (ret < 0)
1384 return ret;
1385
1386 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1387
1388 if (next.valid) {
1389 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1390 if (ret < 0)
1391 return ret;
1392 }
1393
1394 *entry = next;
1395 return 0;
1396}
1397
1398static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1399 struct mv88e6xxx_vtu_stu_entry *entry)
1400{
1401 u16 reg = 0;
1402 int ret;
1403
1404 ret = _mv88e6xxx_vtu_wait(ds);
1405 if (ret < 0)
1406 return ret;
1407
1408 if (!entry->valid)
1409 goto loadpurge;
1410
1411 /* Write port states */
1412 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1413 if (ret < 0)
1414 return ret;
1415
1416 reg = GLOBAL_VTU_VID_VALID;
1417loadpurge:
1418 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1419 if (ret < 0)
1420 return ret;
1421
1422 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1423 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1424 if (ret < 0)
1425 return ret;
1426
1427 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1428}
1429
1430static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1431 struct mv88e6xxx_vtu_stu_entry *entry)
1432{
1433 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1434 struct mv88e6xxx_vtu_stu_entry vlan = {
1435 .valid = true,
1436 .vid = vid,
f02bdffc 1437 .fid = vid, /* We use one FID per VLAN */
0d3b33e6
VD		 1438 };
1439 int i;
1440
1441 /* exclude all ports except the CPU */
1442 for (i = 0; i < ps->num_ports; ++i)
1443 vlan.data[i] = dsa_is_cpu_port(ds, i) ?
1444 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED :
1445 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1446
1447 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1448 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1449 struct mv88e6xxx_vtu_stu_entry vstp;
1450 int err;
1451
1452 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1453 * implemented, only one STU entry is needed to cover all VTU
1454 * entries. Thus, validate the SID 0.
1455 */
1456 vlan.sid = 0;
1457 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1458 if (err)
1459 return err;
1460
1461 if (vstp.sid != vlan.sid || !vstp.valid) {
1462 memset(&vstp, 0, sizeof(vstp));
1463 vstp.valid = true;
1464 vstp.sid = vlan.sid;
1465
1466 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1467 if (err)
1468 return err;
1469 }
1470
7c400018
VD		 1471 /* Clear all MAC addresses from the new database */
1472 err = _mv88e6xxx_atu_flush(ds, vlan.fid, true);
0d3b33e6
VD		 1473 if (err)
1474 return err;
0d3b33e6
VD		 1475 }
1476
1477 *entry = vlan;
1478 return 0;
1479}
1480
1481int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1482 bool untagged)
1483{
1484 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1485 struct mv88e6xxx_vtu_stu_entry vlan;
1486 int err;
1487
1488 mutex_lock(&ps->smi_mutex);
36d04ba1
VD		 1489
1490 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1491 if (err)
1492 goto unlock;
1493
1494 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
0d3b33e6
VD		 1495 if (err)
1496 goto unlock;
1497
1498 if (vlan.vid != vid || !vlan.valid) {
1499 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1500 if (err)
1501 goto unlock;
1502 }
1503
1504 vlan.data[port] = untagged ?
1505 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1506 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1507
1508 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1509unlock:
1510 mutex_unlock(&ps->smi_mutex);
1511
1512 return err;
1513}
1514
7dad08d7
VD		 1515int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1516{
1517 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1518 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1519 int i, err;
1520
1521 mutex_lock(&ps->smi_mutex);
1522
36d04ba1
VD		 1523 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1524 if (err)
1525 goto unlock;
1526
1527 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
7dad08d7
VD		 1528 if (err)
1529 goto unlock;
1530
1531 if (vlan.vid != vid || !vlan.valid ||
1532 vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1533 err = -ENOENT;
1534 goto unlock;
1535 }
1536
1537 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1538
1539 /* keep the VLAN unless all ports are excluded */
f02bdffc 1540 vlan.valid = false;
7dad08d7
VD		 1541 for (i = 0; i < ps->num_ports; ++i) {
1542 if (dsa_is_cpu_port(ds, i))
1543 continue;
1544
1545 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1546 vlan.valid = true;
7dad08d7
VD		 1547 break;
1548 }
1549 }
1550
7dad08d7
VD		 1551 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1552 if (err)
1553 goto unlock;
1554
9f4d55d2 1555 err = _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
7dad08d7
VD		 1556unlock:
1557 mutex_unlock(&ps->smi_mutex);
1558
1559 return err;
1560}
1561
02512b6f
VD		 1562static int _mv88e6xxx_port_vtu_getnext(struct dsa_switch *ds, int port, u16 vid,
1563 struct mv88e6xxx_vtu_stu_entry *entry)
1564{
1565 int err;
1566
1567 do {
1568 if (vid == 4095)
1569 return -ENOENT;
1570
36d04ba1
VD		 1571 err = _mv88e6xxx_vtu_vid_write(ds, vid);
1572 if (err)
1573 return err;
1574
1575 err = _mv88e6xxx_vtu_getnext(ds, entry);
02512b6f
VD		 1576 if (err)
1577 return err;
1578
1579 if (!entry->valid)
1580 return -ENOENT;
1581
1582 vid = entry->vid;
1583 } while (entry->data[port] != GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED &&
1584 entry->data[port] != GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED);
1585
1586 return 0;
1587}
1588
b8fee957
VD		 1589int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
1590 unsigned long *ports, unsigned long *untagged)
1591{
1592 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1593 struct mv88e6xxx_vtu_stu_entry next;
1594 int port;
1595 int err;
1596
1597 if (*vid == 4095)
1598 return -ENOENT;
1599
1600 mutex_lock(&ps->smi_mutex);
36d04ba1
VD		 1601 err = _mv88e6xxx_vtu_vid_write(ds, *vid);
1602 if (err)
1603 goto unlock;
1604
1605 err = _mv88e6xxx_vtu_getnext(ds, &next);
1606unlock:
b8fee957
VD		 1607 mutex_unlock(&ps->smi_mutex);
1608
1609 if (err)
1610 return err;
1611
1612 if (!next.valid)
1613 return -ENOENT;
1614
1615 *vid = next.vid;
1616
1617 for (port = 0; port < ps->num_ports; ++port) {
1618 clear_bit(port, ports);
1619 clear_bit(port, untagged);
1620
1621 if (dsa_is_cpu_port(ds, port))
1622 continue;
1623
1624 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED ||
1625 next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1626 set_bit(port, ports);
1627
1628 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1629 set_bit(port, untagged);
1630 }
1631
1632 return 0;
1633}
1634
c5723ac5
VD		 1635static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1636 const unsigned char *addr)
defb05b9
GR		 1637{
1638 int i, ret;
1639
1640 for (i = 0; i < 3; i++) {
cca8b133
AL		 1641 ret = _mv88e6xxx_reg_write(
1642 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1643 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 1644 if (ret < 0)
1645 return ret;
1646 }
1647
1648 return 0;
1649}
1650
c5723ac5 1651static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
defb05b9
GR		 1652{
1653 int i, ret;
1654
1655 for (i = 0; i < 3; i++) {
cca8b133
AL		 1656 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1657 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 1658 if (ret < 0)
1659 return ret;
1660 addr[i * 2] = ret >> 8;
1661 addr[i * 2 + 1] = ret & 0xff;
1662 }
1663
1664 return 0;
1665}
1666
fd231c82
VD		 1667static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1668 struct mv88e6xxx_atu_entry *entry)
defb05b9 1669{
6630e236
VD		 1670 int ret;
1671
defb05b9
GR		 1672 ret = _mv88e6xxx_atu_wait(ds);
1673 if (ret < 0)
1674 return ret;
1675
fd231c82 1676 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
defb05b9
GR		 1677 if (ret < 0)
1678 return ret;
1679
37705b73 1680 ret = _mv88e6xxx_atu_data_write(ds, entry);
fd231c82 1681 if (ret < 0)
87820510
VD		 1682 return ret;
1683
70cc99d1
VD		 1684 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1685 if (ret < 0)
1686 return ret;
1687
1688 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 1689}
87820510 1690
fd231c82
VD		 1691static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1692 const unsigned char *addr, u16 vid,
1693 u8 state)
1694{
1695 struct mv88e6xxx_atu_entry entry = { 0 };
fd231c82 1696
f02bdffc 1697 entry.fid = vid; /* We use one FID per VLAN */
fd231c82
VD		 1698 entry.state = state;
1699 ether_addr_copy(entry.mac, addr);
1700 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1701 entry.trunk = false;
1702 entry.portv_trunkid = BIT(port);
1703 }
1704
1705 return _mv88e6xxx_atu_load(ds, &entry);
87820510
VD		 1706}
1707
146a3206
VD		 1708int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1709 const struct switchdev_obj_port_fdb *fdb,
1710 struct switchdev_trans *trans)
1711{
f02bdffc
VD		 1712 /* We don't use per-port FDB */
1713 if (fdb->vid == 0)
1714 return -EOPNOTSUPP;
1715
146a3206
VD		 1716 /* We don't need any dynamic resource from the kernel (yet),
1717 * so skip the prepare phase.
1718 */
1719 return 0;
1720}
1721
cdf09697 1722int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1f36faf2
VD		 1723 const struct switchdev_obj_port_fdb *fdb,
1724 struct switchdev_trans *trans)
87820510 1725{
1f36faf2 1726 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 1727 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1728 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 1729 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1730 int ret;
1731
1732 mutex_lock(&ps->smi_mutex);
1f36faf2 1733 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
87820510
VD		 1734 mutex_unlock(&ps->smi_mutex);
1735
1736 return ret;
1737}
1738
cdf09697 1739int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 1740 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 1741{
1742 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1743 int ret;
1744
1745 mutex_lock(&ps->smi_mutex);
8057b3e7 1746 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
cdf09697 1747 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 1748 mutex_unlock(&ps->smi_mutex);
1749
1750 return ret;
1751}
1752
1d194046 1753static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1d194046 1754 struct mv88e6xxx_atu_entry *entry)
6630e236 1755{
1d194046
VD		 1756 struct mv88e6xxx_atu_entry next = { 0 };
1757 int ret;
1758
1759 next.fid = fid;
defb05b9 1760
cdf09697
DM		 1761 ret = _mv88e6xxx_atu_wait(ds);
1762 if (ret < 0)
1763 return ret;
6630e236 1764
70cc99d1
VD		 1765 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1766 if (ret < 0)
1767 return ret;
1768
1769 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 1770 if (ret < 0)
1771 return ret;
6630e236 1772
1d194046
VD		 1773 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1774 if (ret < 0)
1775 return ret;
6630e236 1776
1d194046 1777 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 1778 if (ret < 0)
1779 return ret;
6630e236 1780
1d194046
VD		 1781 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1782 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1783 unsigned int mask, shift;
1784
1785 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1786 next.trunk = true;
1787 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1788 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1789 } else {
1790 next.trunk = false;
1791 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1792 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1793 }
1794
1795 next.portv_trunkid = (ret & mask) >> shift;
1796 }
cdf09697 1797
1d194046 1798 *entry = next;
cdf09697
DM		 1799 return 0;
1800}
1801
f33475bd
VD		 1802int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1803 struct switchdev_obj_port_fdb *fdb,
1804 int (*cb)(struct switchdev_obj *obj))
1805{
1806 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1807 struct mv88e6xxx_vtu_stu_entry vlan = {
1808 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
1809 };
1810 int err;
1811
1812 mutex_lock(&ps->smi_mutex);
1813
1814 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
1815 if (err)
1816 goto unlock;
1817
1818 do {
1819 struct mv88e6xxx_atu_entry addr = {
1820 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
1821 };
1822
1823 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1824 if (err)
1825 goto unlock;
1826
1827 if (!vlan.valid)
1828 break;
1829
1830 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
1831 if (err)
1832 goto unlock;
1833
1834 do {
1835 err = _mv88e6xxx_atu_getnext(ds, vlan.fid, &addr);
1836 if (err)
1837 goto unlock;
1838
1839 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1840 break;
1841
1842 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
1843 bool is_static = addr.state ==
1844 (is_multicast_ether_addr(addr.mac) ?
1845 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1846 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1847
1848 fdb->vid = vlan.vid;
1849 ether_addr_copy(fdb->addr, addr.mac);
1850 fdb->ndm_state = is_static ? NUD_NOARP :
1851 NUD_REACHABLE;
1852
1853 err = cb(&fdb->obj);
1854 if (err)
1855 goto unlock;
1856 }
1857 } while (!is_broadcast_ether_addr(addr.mac));
1858
1859 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1860
1861unlock:
1862 mutex_unlock(&ps->smi_mutex);
1863
1864 return err;
1865}
1866
cdf09697
DM		 1867/* get next entry for port */
1868int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
2a778e1b 1869 unsigned char *addr, u16 *vid, bool *is_static)
cdf09697
DM		 1870{
1871 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1d194046 1872 struct mv88e6xxx_atu_entry next;
f02bdffc 1873 u16 fid = *vid; /* We use one FID per VLAN */
cdf09697 1874 int ret;
6630e236 1875
cdf09697 1876 mutex_lock(&ps->smi_mutex);
1d194046 1877
1d194046
VD		 1878 do {
1879 if (is_broadcast_ether_addr(addr)) {
02512b6f
VD		 1880 struct mv88e6xxx_vtu_stu_entry vtu;
1881
1882 ret = _mv88e6xxx_port_vtu_getnext(ds, port, *vid, &vtu);
1883 if (ret < 0)
1884 goto unlock;
1885
1886 *vid = vtu.vid;
1887 fid = vtu.fid;
1d194046
VD		 1888 }
1889
b0e1a692
VD		 1890 ret = _mv88e6xxx_atu_mac_write(ds, addr);
1891 if (ret < 0)
1892 goto unlock;
1893
1894 ret = _mv88e6xxx_atu_getnext(ds, fid, &next);
1d194046
VD		 1895 if (ret < 0)
1896 goto unlock;
1897
1898 ether_addr_copy(addr, next.mac);
1899
1900 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1901 continue;
1902 } while (next.trunk || (next.portv_trunkid & BIT(port)) == 0);
1903
1904 *is_static = next.state == (is_multicast_ether_addr(addr) ?
1905 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1906 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1907unlock:
defb05b9
GR		 1908 mutex_unlock(&ps->smi_mutex);
1909
1910 return ret;
1911}
1912
facd95b2
GR		 1913static void mv88e6xxx_bridge_work(struct work_struct *work)
1914{
1915 struct mv88e6xxx_priv_state *ps;
1916 struct dsa_switch *ds;
1917 int port;
1918
1919 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1920 ds = ((struct dsa_switch *)ps) - 1;
1921
1922 while (ps->port_state_update_mask) {
1923 port = __ffs(ps->port_state_update_mask);
1924 clear_bit(port, &ps->port_state_update_mask);
1925 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1926 }
1927}
1928
dbde9e66 1929static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 1930{
1931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 1932 int ret;
54d792f2 1933 u16 reg;
d827e88a
GR		 1934
1935 mutex_lock(&ps->smi_mutex);
1936
54d792f2
AL		 1937 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1938 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1939 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
7c3d0d67 1940 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 1941 /* MAC Forcing register: don't force link, speed,
1942 * duplex or flow control state to any particular
1943 * values on physical ports, but force the CPU port
1944 * and all DSA ports to their maximum bandwidth and
1945 * full duplex.
1946 */
1947 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 1948 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 1949 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 1950 reg |= PORT_PCS_CTRL_FORCE_LINK |
1951 PORT_PCS_CTRL_LINK_UP |
1952 PORT_PCS_CTRL_DUPLEX_FULL |
1953 PORT_PCS_CTRL_FORCE_DUPLEX;
1954 if (mv88e6xxx_6065_family(ds))
1955 reg |= PORT_PCS_CTRL_100;
1956 else
1957 reg |= PORT_PCS_CTRL_1000;
1958 } else {
1959 reg |= PORT_PCS_CTRL_UNFORCED;
1960 }
1961
1962 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1963 PORT_PCS_CTRL, reg);
1964 if (ret)
1965 goto abort;
1966 }
1967
1968 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1969 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1970 * tunneling, determine priority by looking at 802.1p and IP
1971 * priority fields (IP prio has precedence), and set STP state
1972 * to Forwarding.
1973 *
1974 * If this is the CPU link, use DSA or EDSA tagging depending
1975 * on which tagging mode was configured.
1976 *
1977 * If this is a link to another switch, use DSA tagging mode.
1978 *
1979 * If this is the upstream port for this switch, enable
1980 * forwarding of unknown unicasts and multicasts.
1981 */
1982 reg = 0;
1983 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1984 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1985 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 1986 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 1987 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1988 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1989 PORT_CONTROL_STATE_FORWARDING;
1990 if (dsa_is_cpu_port(ds, port)) {
1991 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1992 reg |= PORT_CONTROL_DSA_TAG;
1993 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 1994 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1995 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 1996 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1997 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1998 else
1999 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2000 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2001 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2002 }
2003
2004 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2005 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2006 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2007 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2008 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2009 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2010 }
2011 }
6083ce71
AL		 2012 if (dsa_is_dsa_port(ds, port)) {
2013 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2014 reg |= PORT_CONTROL_DSA_TAG;
2015 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2016 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2017 mv88e6xxx_6320_family(ds)) {
54d792f2 2018 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2019 }
2020
54d792f2
AL		 2021 if (port == dsa_upstream_port(ds))
2022 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2023 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2024 }
2025 if (reg) {
2026 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2027 PORT_CONTROL, reg);
2028 if (ret)
2029 goto abort;
2030 }
2031
8efdda4a
VD		 2032 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2033 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2034 * untagged frames on this port, do a destination address lookup on all
2035 * received packets as usual, disable ARP mirroring and don't send a
2036 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2037 */
2038 reg = 0;
2039 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2040 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67 2041 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2042 reg = PORT_CONTROL_2_MAP_DA;
2043
2044 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67 2045 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2046 reg |= PORT_CONTROL_2_JUMBO_10240;
2047
2048 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2049 /* Set the upstream port this port should use */
2050 reg |= dsa_upstream_port(ds);
2051 /* enable forwarding of unknown multicast addresses to
2052 * the upstream port
2053 */
2054 if (port == dsa_upstream_port(ds))
2055 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2056 }
2057
5fe7f680 2058 reg |= PORT_CONTROL_2_8021Q_SECURE;
8efdda4a 2059
54d792f2
AL		 2060 if (reg) {
2061 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2062 PORT_CONTROL_2, reg);
2063 if (ret)
2064 goto abort;
2065 }
2066
2067 /* Port Association Vector: when learning source addresses
2068 * of packets, add the address to the address database using
2069 * a port bitmap that has only the bit for this port set and
2070 * the other bits clear.
2071 */
2072 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
2073 1 << port);
2074 if (ret)
2075 goto abort;
2076
2077 /* Egress rate control 2: disable egress rate control. */
2078 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2079 0x0000);
2080 if (ret)
2081 goto abort;
2082
2083 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2084 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2085 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2086 /* Do not limit the period of time that this port can
2087 * be paused for by the remote end or the period of
2088 * time that this port can pause the remote end.
2089 */
2090 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2091 PORT_PAUSE_CTRL, 0x0000);
2092 if (ret)
2093 goto abort;
2094
2095 /* Port ATU control: disable limiting the number of
2096 * address database entries that this port is allowed
2097 * to use.
2098 */
2099 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2100 PORT_ATU_CONTROL, 0x0000);
2101 /* Priority Override: disable DA, SA and VTU priority
2102 * override.
2103 */
2104 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2105 PORT_PRI_OVERRIDE, 0x0000);
2106 if (ret)
2107 goto abort;
2108
2109 /* Port Ethertype: use the Ethertype DSA Ethertype
2110 * value.
2111 */
2112 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2113 PORT_ETH_TYPE, ETH_P_EDSA);
2114 if (ret)
2115 goto abort;
2116 /* Tag Remap: use an identity 802.1p prio -> switch
2117 * prio mapping.
2118 */
2119 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2120 PORT_TAG_REGMAP_0123, 0x3210);
2121 if (ret)
2122 goto abort;
2123
2124 /* Tag Remap 2: use an identity 802.1p prio -> switch
2125 * prio mapping.
2126 */
2127 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2128 PORT_TAG_REGMAP_4567, 0x7654);
2129 if (ret)
2130 goto abort;
2131 }
2132
2133 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2134 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2135 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2136 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2137 /* Rate Control: disable ingress rate limiting. */
2138 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2139 PORT_RATE_CONTROL, 0x0001);
2140 if (ret)
2141 goto abort;
2142 }
2143
366f0a0f
GR		 2144 /* Port Control 1: disable trunking, disable sending
2145 * learning messages to this port.
d827e88a 2146 */
614f03fc 2147 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2148 if (ret)
2149 goto abort;
2150
f02bdffc 2151 /* Port based VLAN map: do not give each port its own address
5fe7f680 2152 * database, and allow every port to egress frames on all other ports.
d827e88a 2153 */
5fe7f680 2154 reg = BIT(ps->num_ports) - 1; /* all ports */
ede8098d 2155 ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg & ~port);
d827e88a
GR		 2156 if (ret)
2157 goto abort;
2158
2159 /* Default VLAN ID and priority: don't set a default VLAN
2160 * ID, and set the default packet priority to zero.
2161 */
47cf1e65
VD		 2162 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2163 0x0000);
d827e88a
GR		 2164abort:
2165 mutex_unlock(&ps->smi_mutex);
2166 return ret;
2167}
2168
dbde9e66
AL		 2169int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2170{
2171 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2172 int ret;
2173 int i;
2174
2175 for (i = 0; i < ps->num_ports; i++) {
2176 ret = mv88e6xxx_setup_port(ds, i);
2177 if (ret < 0)
2178 return ret;
2179 }
2180 return 0;
2181}
2182
87c8cefb
AL		 2183static int mv88e6xxx_regs_show(struct seq_file *s, void *p)
2184{
2185 struct dsa_switch *ds = s->private;
2186
2187 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2188 int reg, port;
2189
2190 seq_puts(s, " GLOBAL GLOBAL2 ");
2191 for (port = 0 ; port < ps->num_ports; port++)
2192 seq_printf(s, " %2d ", port);
2193 seq_puts(s, "\n");
2194
2195 for (reg = 0; reg < 32; reg++) {
2196 seq_printf(s, "%2x: ", reg);
2197 seq_printf(s, " %4x %4x ",
2198 mv88e6xxx_reg_read(ds, REG_GLOBAL, reg),
2199 mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg));
2200
2201 for (port = 0 ; port < ps->num_ports; port++)
2202 seq_printf(s, "%4x ",
2203 mv88e6xxx_reg_read(ds, REG_PORT(port), reg));
2204 seq_puts(s, "\n");
2205 }
2206
2207 return 0;
2208}
2209
2210static int mv88e6xxx_regs_open(struct inode *inode, struct file *file)
2211{
2212 return single_open(file, mv88e6xxx_regs_show, inode->i_private);
2213}
2214
2215static const struct file_operations mv88e6xxx_regs_fops = {
2216 .open = mv88e6xxx_regs_open,
2217 .read = seq_read,
2218 .llseek = no_llseek,
2219 .release = single_release,
2220 .owner = THIS_MODULE,
2221};
2222
8a0a265d
AL		 2223static void mv88e6xxx_atu_show_header(struct seq_file *s)
2224{
2225 seq_puts(s, "DB T/P Vec State Addr\n");
2226}
2227
2228static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum,
2229 unsigned char *addr, int data)
2230{
2231 bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK);
2232 int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >>
2233 GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT);
2234 int state = data & GLOBAL_ATU_DATA_STATE_MASK;
2235
2236 seq_printf(s, "%03x %5s %10pb %x %pM\n",
2237 dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr);
2238}
2239
2240static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds,
2241 int dbnum)
2242{
2243 unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2244 unsigned char addr[6];
2245 int ret, data, state;
2246
c5723ac5 2247 ret = _mv88e6xxx_atu_mac_write(ds, bcast);
8a0a265d
AL		 2248 if (ret < 0)
2249 return ret;
2250
2251 do {
70cc99d1
VD		 2252 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
2253 dbnum);
8a0a265d
AL		 2254 if (ret < 0)
2255 return ret;
70cc99d1
VD		 2256
2257 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
2258 if (ret < 0)
2259 return ret;
2260
8a0a265d
AL		 2261 data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2262 if (data < 0)
2263 return data;
2264
2265 state = data & GLOBAL_ATU_DATA_STATE_MASK;
2266 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
2267 break;
c5723ac5 2268 ret = _mv88e6xxx_atu_mac_read(ds, addr);
8a0a265d
AL		 2269 if (ret < 0)
2270 return ret;
2271 mv88e6xxx_atu_show_entry(s, dbnum, addr, data);
2272 } while (state != GLOBAL_ATU_DATA_STATE_UNUSED);
2273
2274 return 0;
2275}
2276
2277static int mv88e6xxx_atu_show(struct seq_file *s, void *p)
2278{
2279 struct dsa_switch *ds = s->private;
2280 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2281 int dbnum;
2282
2283 mv88e6xxx_atu_show_header(s);
2284
2285 for (dbnum = 0; dbnum < 255; dbnum++) {
2286 mutex_lock(&ps->smi_mutex);
2287 mv88e6xxx_atu_show_db(s, ds, dbnum);
2288 mutex_unlock(&ps->smi_mutex);
2289 }
2290
2291 return 0;
2292}
2293
2294static int mv88e6xxx_atu_open(struct inode *inode, struct file *file)
2295{
2296 return single_open(file, mv88e6xxx_atu_show, inode->i_private);
2297}
2298
2299static const struct file_operations mv88e6xxx_atu_fops = {
2300 .open = mv88e6xxx_atu_open,
2301 .read = seq_read,
2302 .llseek = no_llseek,
2303 .release = single_release,
2304 .owner = THIS_MODULE,
2305};
2306
532c7a35
AL		 2307static void mv88e6xxx_stats_show_header(struct seq_file *s,
2308 struct mv88e6xxx_priv_state *ps)
2309{
2310 int port;
2311
2312 seq_puts(s, " Statistic ");
2313 for (port = 0 ; port < ps->num_ports; port++)
2314 seq_printf(s, "Port %2d ", port);
2315 seq_puts(s, "\n");
2316}
2317
2318static int mv88e6xxx_stats_show(struct seq_file *s, void *p)
2319{
2320 struct dsa_switch *ds = s->private;
2321 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2322 struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats;
2323 int port, stat, max_stats;
2324 uint64_t value;
2325
2326 if (have_sw_in_discards(ds))
2327 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats);
2328 else
2329 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
2330
2331 mv88e6xxx_stats_show_header(s, ps);
2332
2333 mutex_lock(&ps->smi_mutex);
2334
2335 for (stat = 0; stat < max_stats; stat++) {
2336 seq_printf(s, "%19s: ", stats[stat].string);
2337 for (port = 0 ; port < ps->num_ports; port++) {
2338 _mv88e6xxx_stats_snapshot(ds, port);
2339 value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats,
2340 port);
2341 seq_printf(s, "%8llu ", value);
2342 }
2343 seq_puts(s, "\n");
2344 }
2345 mutex_unlock(&ps->smi_mutex);
2346
2347 return 0;
2348}
2349
2350static int mv88e6xxx_stats_open(struct inode *inode, struct file *file)
2351{
2352 return single_open(file, mv88e6xxx_stats_show, inode->i_private);
2353}
2354
2355static const struct file_operations mv88e6xxx_stats_fops = {
2356 .open = mv88e6xxx_stats_open,
2357 .read = seq_read,
2358 .llseek = no_llseek,
2359 .release = single_release,
2360 .owner = THIS_MODULE,
2361};
2362
d35bd876
AL		 2363static int mv88e6xxx_device_map_show(struct seq_file *s, void *p)
2364{
2365 struct dsa_switch *ds = s->private;
2366 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2367 int target, ret;
2368
2369 seq_puts(s, "Target Port\n");
2370
2371 mutex_lock(&ps->smi_mutex);
2372 for (target = 0; target < 32; target++) {
2373 ret = _mv88e6xxx_reg_write(
2374 ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2375 target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT);
2376 if (ret < 0)
2377 goto out;
2378 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
2379 GLOBAL2_DEVICE_MAPPING);
2380 seq_printf(s, " %2d %2d\n", target,
2381 ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK);
2382 }
2383out:
2384 mutex_unlock(&ps->smi_mutex);
2385
2386 return 0;
2387}
2388
2389static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file)
2390{
2391 return single_open(file, mv88e6xxx_device_map_show, inode->i_private);
2392}
2393
2394static const struct file_operations mv88e6xxx_device_map_fops = {
2395 .open = mv88e6xxx_device_map_open,
2396 .read = seq_read,
2397 .llseek = no_llseek,
2398 .release = single_release,
2399 .owner = THIS_MODULE,
2400};
2401
56d95e22
AL		 2402static int mv88e6xxx_scratch_show(struct seq_file *s, void *p)
2403{
2404 struct dsa_switch *ds = s->private;
2405 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2406 int reg, ret;
2407
2408 seq_puts(s, "Register Value\n");
2409
2410 mutex_lock(&ps->smi_mutex);
2411 for (reg = 0; reg < 0x80; reg++) {
2412 ret = _mv88e6xxx_reg_write(
2413 ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
2414 reg << GLOBAL2_SCRATCH_REGISTER_SHIFT);
2415 if (ret < 0)
2416 goto out;
2417
2418 ret = _mv88e6xxx_scratch_wait(ds);
2419 if (ret < 0)
2420 goto out;
2421
2422 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
2423 GLOBAL2_SCRATCH_MISC);
2424 seq_printf(s, " %2x %2x\n", reg,
2425 ret & GLOBAL2_SCRATCH_VALUE_MASK);
2426 }
2427out:
2428 mutex_unlock(&ps->smi_mutex);
2429
2430 return 0;
2431}
2432
2433static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file)
2434{
2435 return single_open(file, mv88e6xxx_scratch_show, inode->i_private);
2436}
2437
2438static const struct file_operations mv88e6xxx_scratch_fops = {
2439 .open = mv88e6xxx_scratch_open,
2440 .read = seq_read,
2441 .llseek = no_llseek,
2442 .release = single_release,
2443 .owner = THIS_MODULE,
2444};
2445
acdaffcc
GR		 2446int mv88e6xxx_setup_common(struct dsa_switch *ds)
2447{
2448 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87c8cefb 2449 char *name;
acdaffcc
GR		 2450
2451 mutex_init(&ps->smi_mutex);
acdaffcc 2452
cca8b133 2453 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
a8f064c6 2454
facd95b2
GR		 2455 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2456
87c8cefb
AL		 2457 name = kasprintf(GFP_KERNEL, "dsa%d", ds->index);
2458 ps->dbgfs = debugfs_create_dir(name, NULL);
2459 kfree(name);
2460
2461 debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds,
2462 &mv88e6xxx_regs_fops);
2463
8a0a265d
AL		 2464 debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds,
2465 &mv88e6xxx_atu_fops);
2466
532c7a35
AL		 2467 debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds,
2468 &mv88e6xxx_stats_fops);
2469
d35bd876
AL		 2470 debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds,
2471 &mv88e6xxx_device_map_fops);
56d95e22
AL		 2472
2473 debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds,
2474 &mv88e6xxx_scratch_fops);
acdaffcc
GR		 2475 return 0;
2476}
2477
54d792f2
AL		 2478int mv88e6xxx_setup_global(struct dsa_switch *ds)
2479{
2480 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
24751e29 2481 int ret;
54d792f2
AL		 2482 int i;
2483
2484 /* Set the default address aging time to 5 minutes, and
2485 * enable address learn messages to be sent to all message
2486 * ports.
2487 */
2488 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2489 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2490
2491 /* Configure the IP ToS mapping registers. */
2492 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2493 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2494 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2495 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2496 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2497 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2498 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2499 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2500
2501 /* Configure the IEEE 802.1p priority mapping register. */
2502 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2503
2504 /* Send all frames with destination addresses matching
2505 * 01:80:c2:00:00:0x to the CPU port.
2506 */
2507 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2508
2509 /* Ignore removed tag data on doubly tagged packets, disable
2510 * flow control messages, force flow control priority to the
2511 * highest, and send all special multicast frames to the CPU
2512 * port at the highest priority.
2513 */
2514 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2515 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2516 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2517
2518 /* Program the DSA routing table. */
2519 for (i = 0; i < 32; i++) {
2520 int nexthop = 0x1f;
2521
2522 if (ds->pd->rtable &&
2523 i != ds->index && i < ds->dst->pd->nr_chips)
2524 nexthop = ds->pd->rtable[i] & 0x1f;
2525
2526 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2527 GLOBAL2_DEVICE_MAPPING_UPDATE |
2528 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2529 nexthop);
2530 }
2531
2532 /* Clear all trunk masks. */
2533 for (i = 0; i < 8; i++)
2534 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2535 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2536 ((1 << ps->num_ports) - 1));
2537
2538 /* Clear all trunk mappings. */
2539 for (i = 0; i < 16; i++)
2540 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2541 GLOBAL2_TRUNK_MAPPING_UPDATE |
2542 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2543
2544 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2545 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2546 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2547 /* Send all frames with destination addresses matching
2548 * 01:80:c2:00:00:2x to the CPU port.
2549 */
2550 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2551
2552 /* Initialise cross-chip port VLAN table to reset
2553 * defaults.
2554 */
2555 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2556
2557 /* Clear the priority override table. */
2558 for (i = 0; i < 16; i++)
2559 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2560 0x8000 | (i << 8));
2561 }
2562
2563 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2564 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2565 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2566 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2567 /* Disable ingress rate limiting by resetting all
2568 * ingress rate limit registers to their initial
2569 * state.
2570 */
2571 for (i = 0; i < ps->num_ports; i++)
2572 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2573 0x9000 | (i << 8));
2574 }
2575
db687a56
AL		 2576 /* Clear the statistics counters for all ports */
2577 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2578
2579 /* Wait for the flush to complete. */
24751e29
VD		 2580 mutex_lock(&ps->smi_mutex);
2581 ret = _mv88e6xxx_stats_wait(ds);
6b17e864
VD		 2582 if (ret < 0)
2583 goto unlock;
2584
c161d0a5
VD		 2585 /* Clear all ATU entries */
2586 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2587 if (ret < 0)
2588 goto unlock;
2589
6b17e864
VD		 2590 /* Clear all the VTU and STU entries */
2591 ret = _mv88e6xxx_vtu_stu_flush(ds);
2592unlock:
24751e29 2593 mutex_unlock(&ps->smi_mutex);
db687a56 2594
24751e29 2595 return ret;
54d792f2
AL		 2596}
2597
143a8307
AL		 2598int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2599{
2600 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2601 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2602 unsigned long timeout;
2603 int ret;
2604 int i;
2605
2606 /* Set all ports to the disabled state. */
2607 for (i = 0; i < ps->num_ports; i++) {
cca8b133
AL		 2608 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2609 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
143a8307
AL		 2610 }
2611
2612 /* Wait for transmit queues to drain. */
2613 usleep_range(2000, 4000);
2614
2615 /* Reset the switch. Keep the PPU active if requested. The PPU
2616 * needs to be active to support indirect phy register access
2617 * through global registers 0x18 and 0x19.
2618 */
2619 if (ppu_active)
2620 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2621 else
2622 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2623
2624 /* Wait up to one second for reset to complete. */
2625 timeout = jiffies + 1 * HZ;
2626 while (time_before(jiffies, timeout)) {
2627 ret = REG_READ(REG_GLOBAL, 0x00);
2628 if ((ret & is_reset) == is_reset)
2629 break;
2630 usleep_range(1000, 2000);
2631 }
2632 if (time_after(jiffies, timeout))
2633 return -ETIMEDOUT;
2634
2635 return 0;
2636}
2637
49143585
AL		 2638int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2639{
2640 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2641 int ret;
2642
3898c148 2643 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2644 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2645 if (ret < 0)
2646 goto error;
fd3a0ee4 2647 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
49143585 2648error:
fd3a0ee4 2649 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2650 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2651 return ret;
2652}
2653
2654int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2655 int reg, int val)
2656{
2657 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2658 int ret;
2659
3898c148 2660 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2661 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2662 if (ret < 0)
2663 goto error;
2664
fd3a0ee4 2665 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
49143585 2666error:
fd3a0ee4 2667 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2668 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2669 return ret;
2670}
2671
2672static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2673{
2674 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2675
2676 if (port >= 0 && port < ps->num_ports)
2677 return port;
2678 return -EINVAL;
2679}
2680
2681int
2682mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2683{
2684 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2685 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2686 int ret;
2687
2688 if (addr < 0)
2689 return addr;
2690
3898c148 2691 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2692 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
3898c148 2693 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2694 return ret;
2695}
2696
2697int
2698mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2699{
2700 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2701 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2702 int ret;
2703
2704 if (addr < 0)
2705 return addr;
2706
3898c148 2707 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2708 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
3898c148 2709 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2710 return ret;
2711}
2712
2713int
2714mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2715{
2716 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2717 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2718 int ret;
2719
2720 if (addr < 0)
2721 return addr;
2722
3898c148 2723 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2724 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
3898c148 2725 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2726 return ret;
2727}
2728
2729int
2730mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2731 u16 val)
2732{
2733 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2734 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2735 int ret;
2736
2737 if (addr < 0)
2738 return addr;
2739
3898c148 2740 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2741 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
3898c148 2742 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2743 return ret;
2744}
2745
c22995c5
GR		 2746#ifdef CONFIG_NET_DSA_HWMON
2747
2748static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2749{
2750 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2751 int ret;
2752 int val;
2753
2754 *temp = 0;
2755
2756 mutex_lock(&ps->smi_mutex);
2757
2758 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2759 if (ret < 0)
2760 goto error;
2761
2762 /* Enable temperature sensor */
2763 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2764 if (ret < 0)
2765 goto error;
2766
2767 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2768 if (ret < 0)
2769 goto error;
2770
2771 /* Wait for temperature to stabilize */
2772 usleep_range(10000, 12000);
2773
2774 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2775 if (val < 0) {
2776 ret = val;
2777 goto error;
2778 }
2779
2780 /* Disable temperature sensor */
2781 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2782 if (ret < 0)
2783 goto error;
2784
2785 *temp = ((val & 0x1f) - 5) * 5;
2786
2787error:
2788 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2789 mutex_unlock(&ps->smi_mutex);
2790 return ret;
2791}
2792
2793static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2794{
2795 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2796 int ret;
2797
2798 *temp = 0;
2799
2800 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2801 if (ret < 0)
2802 return ret;
2803
2804 *temp = (ret & 0xff) - 25;
2805
2806 return 0;
2807}
2808
2809int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2810{
2811 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2812 return mv88e63xx_get_temp(ds, temp);
2813
2814 return mv88e61xx_get_temp(ds, temp);
2815}
2816
2817int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2818{
2819 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2820 int ret;
2821
2822 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2823 return -EOPNOTSUPP;
2824
2825 *temp = 0;
2826
2827 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2828 if (ret < 0)
2829 return ret;
2830
2831 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2832
2833 return 0;
2834}
2835
2836int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2837{
2838 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2839 int ret;
2840
2841 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2842 return -EOPNOTSUPP;
2843
2844 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2845 if (ret < 0)
2846 return ret;
2847 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2848 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2849 (ret & 0xe0ff) | (temp << 8));
2850}
2851
2852int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2853{
2854 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2855 int ret;
2856
2857 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2858 return -EOPNOTSUPP;
2859
2860 *alarm = false;
2861
2862 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2863 if (ret < 0)
2864 return ret;
2865
2866 *alarm = !!(ret & 0x40);
2867
2868 return 0;
2869}
2870#endif /* CONFIG_NET_DSA_HWMON */
2871
98e67308
BH		 2872static int __init mv88e6xxx_init(void)
2873{
2874#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2875 register_switch_driver(&mv88e6131_switch_driver);
2876#endif
2877#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2878 register_switch_driver(&mv88e6123_61_65_switch_driver);
42f27253 2879#endif
3ad50cca
GR		 2880#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2881 register_switch_driver(&mv88e6352_switch_driver);
2882#endif
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AL		 2883#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2884 register_switch_driver(&mv88e6171_switch_driver);
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BH		 2885#endif
2886 return 0;
2887}
2888module_init(mv88e6xxx_init);
2889
2890static void __exit mv88e6xxx_cleanup(void)
2891{
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AL		 2892#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2893 unregister_switch_driver(&mv88e6171_switch_driver);
2894#endif
4212b543
VD		 2895#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2896 unregister_switch_driver(&mv88e6352_switch_driver);
2897#endif
98e67308
BH		 2898#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2899 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2900#endif
2901#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2902 unregister_switch_driver(&mv88e6131_switch_driver);
2903#endif
2904}
2905module_exit(mv88e6xxx_cleanup);
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BH		 2906
2907MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2908MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2909MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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