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net: dsa: support VLAN filtering switchdev attr
[deliverable/linux.git] / drivers / net / dsa / mv88e6xxx.c
CommitLineData
91da11f8
LB		 1/*
2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
b8fee957
VD		 5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
7 *
91da11f8
LB		 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
19b2f97e 14#include <linux/delay.h>
defb05b9 15#include <linux/etherdevice.h>
dea87024 16#include <linux/ethtool.h>
facd95b2 17#include <linux/if_bridge.h>
19b2f97e 18#include <linux/jiffies.h>
91da11f8 19#include <linux/list.h>
2bbba277 20#include <linux/module.h>
91da11f8 21#include <linux/netdevice.h>
c8c1b39a 22#include <linux/gpio/consumer.h>
91da11f8 23#include <linux/phy.h>
c8f0b869 24#include <net/dsa.h>
1f36faf2 25#include <net/switchdev.h>
91da11f8
LB		 26#include "mv88e6xxx.h"
27
3996a4ff
VD		 28static void assert_smi_lock(struct dsa_switch *ds)
29{
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
31
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
34 dump_stack();
35 }
36}
37
3675c8d7 38/* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
91da11f8
LB		 39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
44 * registers.
45 */
46static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
47{
48 int ret;
49 int i;
50
51 for (i = 0; i < 16; i++) {
6e899e6c 52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
91da11f8
LB		 53 if (ret < 0)
54 return ret;
55
cca8b133 56 if ((ret & SMI_CMD_BUSY) == 0)
91da11f8
LB		 57 return 0;
58 }
59
60 return -ETIMEDOUT;
61}
62
b9b37713
VD		 63static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
64 int reg)
91da11f8
LB		 65{
66 int ret;
67
68 if (sw_addr == 0)
6e899e6c 69 return mdiobus_read_nested(bus, addr, reg);
91da11f8 70
3675c8d7 71 /* Wait for the bus to become free. */
91da11f8
LB		 72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
73 if (ret < 0)
74 return ret;
75
3675c8d7 76 /* Transmit the read command. */
6e899e6c
NA		 77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
91da11f8
LB		 79 if (ret < 0)
80 return ret;
81
3675c8d7 82 /* Wait for the read command to complete. */
91da11f8
LB		 83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
84 if (ret < 0)
85 return ret;
86
3675c8d7 87 /* Read the data. */
6e899e6c 88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
91da11f8
LB		 89 if (ret < 0)
90 return ret;
91
92 return ret & 0xffff;
93}
94
8d6d09e7 95static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
91da11f8 96{
b184e497 97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8
LB		 98 int ret;
99
3996a4ff
VD		 100 assert_smi_lock(ds);
101
b184e497
GR		 102 if (bus == NULL)
103 return -EINVAL;
104
b184e497 105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
bb92ea5e
VD		 106 if (ret < 0)
107 return ret;
108
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
110 addr, reg, ret);
111
91da11f8
LB		 112 return ret;
113}
114
8d6d09e7
GR		 115int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
116{
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
118 int ret;
119
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
123
124 return ret;
125}
126
b9b37713
VD		 127static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
128 int reg, u16 val)
91da11f8
LB		 129{
130 int ret;
131
132 if (sw_addr == 0)
6e899e6c 133 return mdiobus_write_nested(bus, addr, reg, val);
91da11f8 134
3675c8d7 135 /* Wait for the bus to become free. */
91da11f8
LB		 136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
137 if (ret < 0)
138 return ret;
139
3675c8d7 140 /* Transmit the data to write. */
6e899e6c 141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
91da11f8
LB		 142 if (ret < 0)
143 return ret;
144
3675c8d7 145 /* Transmit the write command. */
6e899e6c
NA		 146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
91da11f8
LB		 148 if (ret < 0)
149 return ret;
150
3675c8d7 151 /* Wait for the write command to complete. */
91da11f8
LB		 152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
153 if (ret < 0)
154 return ret;
155
156 return 0;
157}
158
8d6d09e7
GR		 159static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
160 u16 val)
91da11f8 161{
b184e497 162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
91da11f8 163
3996a4ff
VD		 164 assert_smi_lock(ds);
165
b184e497
GR		 166 if (bus == NULL)
167 return -EINVAL;
168
bb92ea5e
VD		 169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
170 addr, reg, val);
171
8d6d09e7
GR		 172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
173}
174
175int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
176{
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
178 int ret;
179
91da11f8 180 mutex_lock(&ps->smi_mutex);
8d6d09e7 181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
91da11f8
LB		 182 mutex_unlock(&ps->smi_mutex);
183
184 return ret;
185}
186
2e5f0320
LB		 187int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
188{
cca8b133
AL		 189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2e5f0320
LB		 192
193 return 0;
194}
195
91da11f8
LB		 196int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
197{
198 int i;
199 int ret;
200
201 for (i = 0; i < 6; i++) {
202 int j;
203
3675c8d7 204 /* Write the MAC address byte. */
cca8b133
AL		 205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
91da11f8 207
3675c8d7 208 /* Wait for the write to complete. */
91da11f8 209 for (j = 0; j < 16; j++) {
cca8b133
AL		 210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
91da11f8
LB		 212 break;
213 }
214 if (j == 16)
215 return -ETIMEDOUT;
216 }
217
218 return 0;
219}
220
fd3a0ee4 221static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
91da11f8
LB		 222{
223 if (addr >= 0)
3898c148 224 return _mv88e6xxx_reg_read(ds, addr, regnum);
91da11f8
LB		 225 return 0xffff;
226}
227
fd3a0ee4
AL		 228static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
229 u16 val)
91da11f8
LB		 230{
231 if (addr >= 0)
3898c148 232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
91da11f8
LB		 233 return 0;
234}
235
2e5f0320
LB		 236#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
238{
239 int ret;
19b2f97e 240 unsigned long timeout;
2e5f0320 241
cca8b133
AL		 242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 245
19b2f97e
BG		 246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
cca8b133 248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 249 usleep_range(1000, 2000);
cca8b133
AL		 250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
85686581 252 return 0;
2e5f0320
LB		 253 }
254
255 return -ETIMEDOUT;
256}
257
258static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
259{
260 int ret;
19b2f97e 261 unsigned long timeout;
2e5f0320 262
cca8b133
AL		 263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
2e5f0320 265
19b2f97e
BG		 266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
cca8b133 268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
19b2f97e 269 usleep_range(1000, 2000);
cca8b133
AL		 270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
85686581 272 return 0;
2e5f0320
LB		 273 }
274
275 return -ETIMEDOUT;
276}
277
278static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
279{
280 struct mv88e6xxx_priv_state *ps;
281
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
85686581 284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
2e5f0320 285
85686581
BG		 286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
2e5f0320
LB		 289 }
290}
291
292static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
293{
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
295
296 schedule_work(&ps->ppu_work);
297}
298
299static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
300{
a22adce5 301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 302 int ret;
303
304 mutex_lock(&ps->ppu_mutex);
305
3675c8d7 306 /* If the PHY polling unit is enabled, disable it so that
2e5f0320
LB		 307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
309 * it.
310 */
311 if (!ps->ppu_disabled) {
85686581
BG		 312 ret = mv88e6xxx_ppu_disable(ds);
313 if (ret < 0) {
314 mutex_unlock(&ps->ppu_mutex);
315 return ret;
316 }
317 ps->ppu_disabled = 1;
2e5f0320 318 } else {
85686581
BG		 319 del_timer(&ps->ppu_timer);
320 ret = 0;
2e5f0320
LB		 321 }
322
323 return ret;
324}
325
326static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
327{
a22adce5 328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320 329
3675c8d7 330 /* Schedule a timer to re-enable the PHY polling unit. */
2e5f0320
LB		 331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
333}
334
335void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
336{
a22adce5 337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2e5f0320
LB		 338
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
344}
345
346int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
347{
348 int ret;
349
350 ret = mv88e6xxx_ppu_access_get(ds);
351 if (ret >= 0) {
85686581
BG		 352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 354 }
355
356 return ret;
357}
358
359int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
360 int regnum, u16 val)
361{
362 int ret;
363
364 ret = mv88e6xxx_ppu_access_get(ds);
365 if (ret >= 0) {
85686581
BG		 366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
2e5f0320
LB		 368 }
369
370 return ret;
371}
372#endif
373
54d792f2
AL		 374static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
375{
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
377
378 switch (ps->id) {
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
383 return true;
384 }
385 return false;
386}
387
388static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
389{
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
391
392 switch (ps->id) {
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
395 return true;
396 }
397 return false;
398}
399
400static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
401{
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
403
404 switch (ps->id) {
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
409 return true;
410 }
411 return false;
412}
413
414static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
415{
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
417
418 switch (ps->id) {
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
422 return true;
423 }
424 return false;
425}
426
427static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
428{
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
430
431 switch (ps->id) {
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
440 return true;
441 }
442 return false;
443}
444
c22995c5 445static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
7c3d0d67
AK		 446{
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
448
449 switch (ps->id) {
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
452 return true;
453 }
454 return false;
455}
456
54d792f2
AL		 457static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
458{
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
460
461 switch (ps->id) {
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
466 return true;
467 }
468 return false;
469}
470
f3a8b6b6
AL		 471static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
472{
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
474
475 switch (ps->id) {
f3a8b6b6
AL		 476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
54d792f2
AL		 478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
f3a8b6b6
AL		 480 return true;
481 }
482 return false;
483}
484
dea87024
AL		 485/* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
488 */
489void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
491{
492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
49052871
AL		 493 u32 reg;
494 int ret;
dea87024
AL		 495
496 if (!phy_is_pseudo_fixed_link(phydev))
497 return;
498
499 mutex_lock(&ps->smi_mutex);
500
501 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
502 if (ret < 0)
503 goto out;
504
505 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
506 PORT_PCS_CTRL_FORCE_LINK |
507 PORT_PCS_CTRL_DUPLEX_FULL |
508 PORT_PCS_CTRL_FORCE_DUPLEX |
509 PORT_PCS_CTRL_UNFORCED);
510
511 reg |= PORT_PCS_CTRL_FORCE_LINK;
512 if (phydev->link)
513 reg |= PORT_PCS_CTRL_LINK_UP;
514
515 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
516 goto out;
517
518 switch (phydev->speed) {
519 case SPEED_1000:
520 reg |= PORT_PCS_CTRL_1000;
521 break;
522 case SPEED_100:
523 reg |= PORT_PCS_CTRL_100;
524 break;
525 case SPEED_10:
526 reg |= PORT_PCS_CTRL_10;
527 break;
528 default:
529 pr_info("Unknown speed");
530 goto out;
531 }
532
533 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
534 if (phydev->duplex == DUPLEX_FULL)
535 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
536
e7e72ac0
AL		 537 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
538 (port >= ps->num_ports - 2)) {
539 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
540 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
542 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
543 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
544 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
545 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
546 }
dea87024
AL		 547 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
548
549out:
550 mutex_unlock(&ps->smi_mutex);
551}
552
31888234 553static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
91da11f8
LB		 554{
555 int ret;
556 int i;
557
558 for (i = 0; i < 10; i++) {
31888234 559 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
cca8b133 560 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
91da11f8
LB		 561 return 0;
562 }
563
564 return -ETIMEDOUT;
565}
566
31888234 567static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
91da11f8
LB		 568{
569 int ret;
570
7c3d0d67 571 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
f3a8b6b6
AL		 572 port = (port + 1) << 5;
573
3675c8d7 574 /* Snapshot the hardware statistics counters for this port. */
31888234
AL		 575 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
576 GLOBAL_STATS_OP_CAPTURE_PORT |
577 GLOBAL_STATS_OP_HIST_RX_TX | port);
578 if (ret < 0)
579 return ret;
91da11f8 580
3675c8d7 581 /* Wait for the snapshotting to complete. */
31888234 582 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 583 if (ret < 0)
584 return ret;
585
586 return 0;
587}
588
31888234 589static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
91da11f8
LB		 590{
591 u32 _val;
592 int ret;
593
594 *val = 0;
595
31888234
AL		 596 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
597 GLOBAL_STATS_OP_READ_CAPTURED |
598 GLOBAL_STATS_OP_HIST_RX_TX | stat);
91da11f8
LB		 599 if (ret < 0)
600 return;
601
31888234 602 ret = _mv88e6xxx_stats_wait(ds);
91da11f8
LB		 603 if (ret < 0)
604 return;
605
31888234 606 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
91da11f8
LB		 607 if (ret < 0)
608 return;
609
610 _val = ret << 16;
611
31888234 612 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
91da11f8
LB		 613 if (ret < 0)
614 return;
615
616 *val = _val | ret;
617}
618
e413e7e1 619static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
f5e2ed02
AL		 620 { "in_good_octets", 8, 0x00, BANK0, },
621 { "in_bad_octets", 4, 0x02, BANK0, },
622 { "in_unicast", 4, 0x04, BANK0, },
623 { "in_broadcasts", 4, 0x06, BANK0, },
624 { "in_multicasts", 4, 0x07, BANK0, },
625 { "in_pause", 4, 0x16, BANK0, },
626 { "in_undersize", 4, 0x18, BANK0, },
627 { "in_fragments", 4, 0x19, BANK0, },
628 { "in_oversize", 4, 0x1a, BANK0, },
629 { "in_jabber", 4, 0x1b, BANK0, },
630 { "in_rx_error", 4, 0x1c, BANK0, },
631 { "in_fcs_error", 4, 0x1d, BANK0, },
632 { "out_octets", 8, 0x0e, BANK0, },
633 { "out_unicast", 4, 0x10, BANK0, },
634 { "out_broadcasts", 4, 0x13, BANK0, },
635 { "out_multicasts", 4, 0x12, BANK0, },
636 { "out_pause", 4, 0x15, BANK0, },
637 { "excessive", 4, 0x11, BANK0, },
638 { "collisions", 4, 0x1e, BANK0, },
639 { "deferred", 4, 0x05, BANK0, },
640 { "single", 4, 0x14, BANK0, },
641 { "multiple", 4, 0x17, BANK0, },
642 { "out_fcs_error", 4, 0x03, BANK0, },
643 { "late", 4, 0x1f, BANK0, },
644 { "hist_64bytes", 4, 0x08, BANK0, },
645 { "hist_65_127bytes", 4, 0x09, BANK0, },
646 { "hist_128_255bytes", 4, 0x0a, BANK0, },
647 { "hist_256_511bytes", 4, 0x0b, BANK0, },
648 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
649 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
650 { "sw_in_discards", 4, 0x10, PORT, },
651 { "sw_in_filtered", 2, 0x12, PORT, },
652 { "sw_out_filtered", 2, 0x13, PORT, },
653 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
e413e7e1
AL		 679};
680
f5e2ed02
AL		 681static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
682 struct mv88e6xxx_hw_stat *stat)
e413e7e1 683{
f5e2ed02
AL		 684 switch (stat->type) {
685 case BANK0:
e413e7e1 686 return true;
f5e2ed02
AL		 687 case BANK1:
688 return mv88e6xxx_6320_family(ds);
689 case PORT:
690 return mv88e6xxx_6095_family(ds) ||
691 mv88e6xxx_6185_family(ds) ||
692 mv88e6xxx_6097_family(ds) ||
693 mv88e6xxx_6165_family(ds) ||
694 mv88e6xxx_6351_family(ds) ||
695 mv88e6xxx_6352_family(ds);
91da11f8 696 }
f5e2ed02 697 return false;
91da11f8
LB		 698}
699
80c4627b 700static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
f5e2ed02 701 struct mv88e6xxx_hw_stat *s,
80c4627b
AL		 702 int port)
703{
80c4627b
AL		 704 u32 low;
705 u32 high = 0;
706 int ret;
707 u64 value;
708
f5e2ed02
AL		 709 switch (s->type) {
710 case PORT:
711 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
80c4627b
AL		 712 if (ret < 0)
713 return UINT64_MAX;
714
715 low = ret;
716 if (s->sizeof_stat == 4) {
717 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
f5e2ed02 718 s->reg + 1);
80c4627b
AL		 719 if (ret < 0)
720 return UINT64_MAX;
721 high = ret;
722 }
f5e2ed02
AL		 723 break;
724 case BANK0:
725 case BANK1:
80c4627b
AL		 726 _mv88e6xxx_stats_read(ds, s->reg, &low);
727 if (s->sizeof_stat == 8)
728 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
729 }
730 value = (((u64)high) << 16) | low;
731 return value;
732}
733
f5e2ed02 734void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
91da11f8 735{
f5e2ed02
AL		 736 struct mv88e6xxx_hw_stat *stat;
737 int i, j;
91da11f8 738
f5e2ed02
AL		 739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
741 if (mv88e6xxx_has_stat(ds, stat)) {
742 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
743 ETH_GSTRING_LEN);
744 j++;
745 }
91da11f8 746 }
e413e7e1
AL		 747}
748
749int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
750{
f5e2ed02
AL		 751 struct mv88e6xxx_hw_stat *stat;
752 int i, j;
753
754 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
755 stat = &mv88e6xxx_hw_stats[i];
756 if (mv88e6xxx_has_stat(ds, stat))
757 j++;
758 }
759 return j;
e413e7e1
AL		 760}
761
762void
763mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
764 int port, uint64_t *data)
765{
f5e2ed02
AL		 766 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
767 struct mv88e6xxx_hw_stat *stat;
768 int ret;
769 int i, j;
770
771 mutex_lock(&ps->smi_mutex);
772
773 ret = _mv88e6xxx_stats_snapshot(ds, port);
774 if (ret < 0) {
775 mutex_unlock(&ps->smi_mutex);
776 return;
777 }
778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
779 stat = &mv88e6xxx_hw_stats[i];
780 if (mv88e6xxx_has_stat(ds, stat)) {
781 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
782 j++;
783 }
784 }
785
786 mutex_unlock(&ps->smi_mutex);
e413e7e1
AL		 787}
788
a1ab91f3
GR		 789int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
790{
791 return 32 * sizeof(u16);
792}
793
794void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
795 struct ethtool_regs *regs, void *_p)
796{
797 u16 *p = _p;
798 int i;
799
800 regs->version = 0;
801
802 memset(p, 0xff, 32 * sizeof(u16));
803
804 for (i = 0; i < 32; i++) {
805 int ret;
806
807 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
808 if (ret >= 0)
809 p[i] = ret;
810 }
811}
812
3898c148
AL		 813static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
814 u16 mask)
f3044683
AL		 815{
816 unsigned long timeout = jiffies + HZ / 10;
817
818 while (time_before(jiffies, timeout)) {
819 int ret;
820
3898c148
AL		 821 ret = _mv88e6xxx_reg_read(ds, reg, offset);
822 if (ret < 0)
823 return ret;
f3044683
AL		 824 if (!(ret & mask))
825 return 0;
826
827 usleep_range(1000, 2000);
828 }
829 return -ETIMEDOUT;
830}
831
3898c148
AL		 832static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
833{
834 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
835 int ret;
836
837 mutex_lock(&ps->smi_mutex);
838 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
839 mutex_unlock(&ps->smi_mutex);
840
841 return ret;
842}
843
844static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
f3044683 845{
3898c148
AL		 846 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
847 GLOBAL2_SMI_OP_BUSY);
f3044683
AL		 848}
849
850int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
851{
cca8b133
AL		 852 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
853 GLOBAL2_EEPROM_OP_LOAD);
f3044683
AL		 854}
855
856int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
857{
cca8b133
AL		 858 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
859 GLOBAL2_EEPROM_OP_BUSY);
f3044683
AL		 860}
861
facd95b2
GR		 862static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
863{
cca8b133
AL		 864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
865 GLOBAL_ATU_OP_BUSY);
facd95b2
GR		 866}
867
fd3a0ee4
AL		 868static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
869 int regnum)
f3044683
AL		 870{
871 int ret;
872
3898c148
AL		 873 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
874 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
875 regnum);
876 if (ret < 0)
877 return ret;
f3044683 878
3898c148 879 ret = _mv88e6xxx_phy_wait(ds);
f3044683
AL		 880 if (ret < 0)
881 return ret;
882
3898c148 883 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
f3044683
AL		 884}
885
fd3a0ee4
AL		 886static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
887 int regnum, u16 val)
f3044683 888{
3898c148
AL		 889 int ret;
890
891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
892 if (ret < 0)
893 return ret;
f3044683 894
3898c148
AL		 895 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
896 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
897 regnum);
898
899 return _mv88e6xxx_phy_wait(ds);
f3044683
AL		 900}
901
11b3b45d
GR		 902int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
903{
2f40c698 904 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
11b3b45d
GR		 905 int reg;
906
3898c148 907 mutex_lock(&ps->smi_mutex);
2f40c698
AL		 908
909 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
11b3b45d 910 if (reg < 0)
2f40c698 911 goto out;
11b3b45d
GR		 912
913 e->eee_enabled = !!(reg & 0x0200);
914 e->tx_lpi_enabled = !!(reg & 0x0100);
915
3898c148 916 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
11b3b45d 917 if (reg < 0)
2f40c698 918 goto out;
11b3b45d 919
cca8b133 920 e->eee_active = !!(reg & PORT_STATUS_EEE);
2f40c698 921 reg = 0;
11b3b45d 922
2f40c698 923out:
3898c148 924 mutex_unlock(&ps->smi_mutex);
2f40c698 925 return reg;
11b3b45d
GR		 926}
927
928int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
929 struct phy_device *phydev, struct ethtool_eee *e)
930{
2f40c698
AL		 931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
932 int reg;
11b3b45d
GR		 933 int ret;
934
3898c148 935 mutex_lock(&ps->smi_mutex);
11b3b45d 936
2f40c698
AL		 937 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
938 if (ret < 0)
939 goto out;
940
941 reg = ret & ~0x0300;
942 if (e->eee_enabled)
943 reg |= 0x0200;
944 if (e->tx_lpi_enabled)
945 reg |= 0x0100;
946
947 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
948out:
3898c148 949 mutex_unlock(&ps->smi_mutex);
2f40c698
AL		 950
951 return ret;
11b3b45d
GR		 952}
953
70cc99d1 954static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
facd95b2
GR		 955{
956 int ret;
957
cca8b133 958 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
facd95b2
GR		 959 if (ret < 0)
960 return ret;
961
962 return _mv88e6xxx_atu_wait(ds);
963}
964
37705b73
VD		 965static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
966 struct mv88e6xxx_atu_entry *entry)
967{
968 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
969
970 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
971 unsigned int mask, shift;
972
973 if (entry->trunk) {
974 data |= GLOBAL_ATU_DATA_TRUNK;
975 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
976 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
977 } else {
978 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
979 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
980 }
981
982 data |= (entry->portv_trunkid << shift) & mask;
983 }
984
985 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
986}
987
7fb5e755
VD		 988static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
989 struct mv88e6xxx_atu_entry *entry,
990 bool static_too)
facd95b2 991{
7fb5e755
VD		 992 int op;
993 int err;
facd95b2 994
7fb5e755
VD		 995 err = _mv88e6xxx_atu_wait(ds);
996 if (err)
997 return err;
facd95b2 998
7fb5e755
VD		 999 err = _mv88e6xxx_atu_data_write(ds, entry);
1000 if (err)
1001 return err;
1002
1003 if (entry->fid) {
1004 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1005 entry->fid);
1006 if (err)
1007 return err;
1008
1009 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1010 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1011 } else {
1012 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1013 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1014 }
1015
1016 return _mv88e6xxx_atu_cmd(ds, op);
1017}
1018
1019static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1020{
1021 struct mv88e6xxx_atu_entry entry = {
1022 .fid = fid,
1023 .state = 0, /* EntryState bits must be 0 */
1024 };
70cc99d1 1025
7fb5e755
VD		 1026 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1027}
1028
9f4d55d2
VD		 1029static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1030 int to_port, bool static_too)
1031{
1032 struct mv88e6xxx_atu_entry entry = {
1033 .trunk = false,
1034 .fid = fid,
1035 };
1036
1037 /* EntryState bits must be 0xF */
1038 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1039
1040 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1041 entry.portv_trunkid = (to_port & 0x0f) << 4;
1042 entry.portv_trunkid |= from_port & 0x0f;
1043
1044 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1045}
1046
1047static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1048 bool static_too)
1049{
1050 /* Destination port 0xF means remove the entries */
1051 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1052}
1053
facd95b2
GR		 1054static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1055{
1056 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
c3ffe6d2 1057 int reg, ret = 0;
facd95b2
GR		 1058 u8 oldstate;
1059
1060 mutex_lock(&ps->smi_mutex);
1061
cca8b133 1062 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
538cc282
GR		 1063 if (reg < 0) {
1064 ret = reg;
facd95b2 1065 goto abort;
538cc282 1066 }
facd95b2 1067
cca8b133 1068 oldstate = reg & PORT_CONTROL_STATE_MASK;
facd95b2
GR		 1069 if (oldstate != state) {
1070 /* Flush forwarding database if we're moving a port
1071 * from Learning or Forwarding state to Disabled or
1072 * Blocking or Listening state.
1073 */
cca8b133
AL		 1074 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1075 state <= PORT_CONTROL_STATE_BLOCKING) {
2b8157b1 1076 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
facd95b2
GR		 1077 if (ret)
1078 goto abort;
1079 }
cca8b133
AL		 1080 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1081 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1082 reg);
facd95b2
GR		 1083 }
1084
1085abort:
1086 mutex_unlock(&ps->smi_mutex);
1087 return ret;
1088}
1089
ede8098d
VD		 1090static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port,
1091 u16 output_ports)
facd95b2
GR		 1092{
1093 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
ede8098d
VD		 1094 const u16 mask = (1 << ps->num_ports) - 1;
1095 int reg;
facd95b2 1096
ede8098d
VD		 1097 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1098 if (reg < 0)
1099 return reg;
facd95b2 1100
ede8098d
VD		 1101 reg &= ~mask;
1102 reg |= output_ports & mask;
facd95b2 1103
ede8098d 1104 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
facd95b2
GR		 1105}
1106
facd95b2
GR		 1107int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1108{
1109 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1110 int stp_state;
1111
1112 switch (state) {
1113 case BR_STATE_DISABLED:
cca8b133 1114 stp_state = PORT_CONTROL_STATE_DISABLED;
facd95b2
GR		 1115 break;
1116 case BR_STATE_BLOCKING:
1117 case BR_STATE_LISTENING:
cca8b133 1118 stp_state = PORT_CONTROL_STATE_BLOCKING;
facd95b2
GR		 1119 break;
1120 case BR_STATE_LEARNING:
cca8b133 1121 stp_state = PORT_CONTROL_STATE_LEARNING;
facd95b2
GR		 1122 break;
1123 case BR_STATE_FORWARDING:
1124 default:
cca8b133 1125 stp_state = PORT_CONTROL_STATE_FORWARDING;
facd95b2
GR		 1126 break;
1127 }
1128
1129 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1130
1131 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1132 * so we can not update the port state directly but need to schedule it.
1133 */
d715fa64 1134 ps->ports[port].state = stp_state;
facd95b2
GR		 1135 set_bit(port, &ps->port_state_update_mask);
1136 schedule_work(&ps->bridge_work);
1137
1138 return 0;
1139}
1140
76e398a6
VD		 1141static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1142{
1143 int ret;
1144
1145 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1146 if (ret < 0)
1147 return ret;
1148
1149 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1150
1151 return 0;
1152}
1153
76e398a6 1154static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
0d3b33e6 1155{
76e398a6 1156 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
0d3b33e6
VD		 1157 pvid & PORT_DEFAULT_VLAN_MASK);
1158}
1159
6b17e864
VD		 1160static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1161{
1162 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1163 GLOBAL_VTU_OP_BUSY);
1164}
1165
1166static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1167{
1168 int ret;
1169
1170 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1171 if (ret < 0)
1172 return ret;
1173
1174 return _mv88e6xxx_vtu_wait(ds);
1175}
1176
1177static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1178{
1179 int ret;
1180
1181 ret = _mv88e6xxx_vtu_wait(ds);
1182 if (ret < 0)
1183 return ret;
1184
1185 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1186}
1187
b8fee957
VD		 1188static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1189 struct mv88e6xxx_vtu_stu_entry *entry,
1190 unsigned int nibble_offset)
1191{
1192 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1193 u16 regs[3];
1194 int i;
1195 int ret;
1196
1197 for (i = 0; i < 3; ++i) {
1198 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1199 GLOBAL_VTU_DATA_0_3 + i);
1200 if (ret < 0)
1201 return ret;
1202
1203 regs[i] = ret;
1204 }
1205
1206 for (i = 0; i < ps->num_ports; ++i) {
1207 unsigned int shift = (i % 4) * 4 + nibble_offset;
1208 u16 reg = regs[i / 4];
1209
1210 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1211 }
1212
1213 return 0;
1214}
1215
7dad08d7
VD		 1216static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1217 struct mv88e6xxx_vtu_stu_entry *entry,
1218 unsigned int nibble_offset)
1219{
1220 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1221 u16 regs[3] = { 0 };
1222 int i;
1223 int ret;
1224
1225 for (i = 0; i < ps->num_ports; ++i) {
1226 unsigned int shift = (i % 4) * 4 + nibble_offset;
1227 u8 data = entry->data[i];
1228
1229 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1230 }
1231
1232 for (i = 0; i < 3; ++i) {
1233 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1234 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1235 if (ret < 0)
1236 return ret;
1237 }
1238
1239 return 0;
1240}
1241
36d04ba1
VD		 1242static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1243{
1244 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1245 vid & GLOBAL_VTU_VID_MASK);
1246}
1247
1248static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
b8fee957
VD		 1249 struct mv88e6xxx_vtu_stu_entry *entry)
1250{
1251 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1252 int ret;
1253
1254 ret = _mv88e6xxx_vtu_wait(ds);
1255 if (ret < 0)
1256 return ret;
1257
b8fee957
VD		 1258 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1259 if (ret < 0)
1260 return ret;
1261
1262 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1263 if (ret < 0)
1264 return ret;
1265
1266 next.vid = ret & GLOBAL_VTU_VID_MASK;
1267 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1268
1269 if (next.valid) {
1270 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1271 if (ret < 0)
1272 return ret;
1273
1274 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1275 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1276 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1277 GLOBAL_VTU_FID);
1278 if (ret < 0)
1279 return ret;
1280
1281 next.fid = ret & GLOBAL_VTU_FID_MASK;
1282
1283 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1284 GLOBAL_VTU_SID);
1285 if (ret < 0)
1286 return ret;
1287
1288 next.sid = ret & GLOBAL_VTU_SID_MASK;
1289 }
1290 }
1291
1292 *entry = next;
1293 return 0;
1294}
1295
ceff5eff
VD		 1296int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1297 struct switchdev_obj_port_vlan *vlan,
1298 int (*cb)(struct switchdev_obj *obj))
1299{
1300 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1301 struct mv88e6xxx_vtu_stu_entry next;
1302 u16 pvid;
1303 int err;
1304
1305 mutex_lock(&ps->smi_mutex);
1306
1307 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1308 if (err)
1309 goto unlock;
1310
1311 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1312 if (err)
1313 goto unlock;
1314
1315 do {
1316 err = _mv88e6xxx_vtu_getnext(ds, &next);
1317 if (err)
1318 break;
1319
1320 if (!next.valid)
1321 break;
1322
1323 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1324 continue;
1325
1326 /* reinit and dump this VLAN obj */
1327 vlan->vid_begin = vlan->vid_end = next.vid;
1328 vlan->flags = 0;
1329
1330 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1331 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1332
1333 if (next.vid == pvid)
1334 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1335
1336 err = cb(&vlan->obj);
1337 if (err)
1338 break;
1339 } while (next.vid < GLOBAL_VTU_VID_MASK);
1340
1341unlock:
1342 mutex_unlock(&ps->smi_mutex);
1343
1344 return err;
1345}
1346
7dad08d7
VD		 1347static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1348 struct mv88e6xxx_vtu_stu_entry *entry)
1349{
1350 u16 reg = 0;
1351 int ret;
1352
1353 ret = _mv88e6xxx_vtu_wait(ds);
1354 if (ret < 0)
1355 return ret;
1356
1357 if (!entry->valid)
1358 goto loadpurge;
1359
1360 /* Write port member tags */
1361 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1362 if (ret < 0)
1363 return ret;
1364
1365 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1366 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1367 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1368 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1369 if (ret < 0)
1370 return ret;
1371
1372 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1373 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1374 if (ret < 0)
1375 return ret;
1376 }
1377
1378 reg = GLOBAL_VTU_VID_VALID;
1379loadpurge:
1380 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1381 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1382 if (ret < 0)
1383 return ret;
1384
1385 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1386}
1387
0d3b33e6
VD		 1388static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1389 struct mv88e6xxx_vtu_stu_entry *entry)
1390{
1391 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1392 int ret;
1393
1394 ret = _mv88e6xxx_vtu_wait(ds);
1395 if (ret < 0)
1396 return ret;
1397
1398 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1399 sid & GLOBAL_VTU_SID_MASK);
1400 if (ret < 0)
1401 return ret;
1402
1403 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1404 if (ret < 0)
1405 return ret;
1406
1407 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1408 if (ret < 0)
1409 return ret;
1410
1411 next.sid = ret & GLOBAL_VTU_SID_MASK;
1412
1413 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1414 if (ret < 0)
1415 return ret;
1416
1417 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1418
1419 if (next.valid) {
1420 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1421 if (ret < 0)
1422 return ret;
1423 }
1424
1425 *entry = next;
1426 return 0;
1427}
1428
1429static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1430 struct mv88e6xxx_vtu_stu_entry *entry)
1431{
1432 u16 reg = 0;
1433 int ret;
1434
1435 ret = _mv88e6xxx_vtu_wait(ds);
1436 if (ret < 0)
1437 return ret;
1438
1439 if (!entry->valid)
1440 goto loadpurge;
1441
1442 /* Write port states */
1443 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1444 if (ret < 0)
1445 return ret;
1446
1447 reg = GLOBAL_VTU_VID_VALID;
1448loadpurge:
1449 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1450 if (ret < 0)
1451 return ret;
1452
1453 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1454 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1455 if (ret < 0)
1456 return ret;
1457
1458 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1459}
1460
1461static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1462 struct mv88e6xxx_vtu_stu_entry *entry)
1463{
1464 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1465 struct mv88e6xxx_vtu_stu_entry vlan = {
1466 .valid = true,
1467 .vid = vid,
f02bdffc 1468 .fid = vid, /* We use one FID per VLAN */
0d3b33e6
VD		 1469 };
1470 int i;
1471
3d131f07 1472 /* exclude all ports except the CPU and DSA ports */
0d3b33e6 1473 for (i = 0; i < ps->num_ports; ++i)
3d131f07
VD		 1474 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1475 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1476 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
0d3b33e6
VD		 1477
1478 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1479 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1480 struct mv88e6xxx_vtu_stu_entry vstp;
1481 int err;
1482
1483 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1484 * implemented, only one STU entry is needed to cover all VTU
1485 * entries. Thus, validate the SID 0.
1486 */
1487 vlan.sid = 0;
1488 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1489 if (err)
1490 return err;
1491
1492 if (vstp.sid != vlan.sid || !vstp.valid) {
1493 memset(&vstp, 0, sizeof(vstp));
1494 vstp.valid = true;
1495 vstp.sid = vlan.sid;
1496
1497 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1498 if (err)
1499 return err;
1500 }
1501
7c400018
VD		 1502 /* Clear all MAC addresses from the new database */
1503 err = _mv88e6xxx_atu_flush(ds, vlan.fid, true);
0d3b33e6
VD		 1504 if (err)
1505 return err;
0d3b33e6
VD		 1506 }
1507
1508 *entry = vlan;
1509 return 0;
1510}
1511
da9c359e
VD		 1512static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1513 u16 vid_begin, u16 vid_end)
1514{
1515 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1516 struct mv88e6xxx_vtu_stu_entry vlan;
1517 int i, err;
1518
1519 if (!vid_begin)
1520 return -EOPNOTSUPP;
1521
1522 mutex_lock(&ps->smi_mutex);
1523
1524 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1525 if (err)
1526 goto unlock;
1527
1528 do {
1529 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1530 if (err)
1531 goto unlock;
1532
1533 if (!vlan.valid)
1534 break;
1535
1536 if (vlan.vid > vid_end)
1537 break;
1538
1539 for (i = 0; i < ps->num_ports; ++i) {
1540 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1541 continue;
1542
1543 if (vlan.data[i] ==
1544 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1545 continue;
1546
1547 if (ps->ports[i].bridge_dev ==
1548 ps->ports[port].bridge_dev)
1549 break; /* same bridge, check next VLAN */
1550
1551 netdev_warn(ds->ports[port],
1552 "hardware VLAN %d already used by %s\n",
1553 vlan.vid,
1554 netdev_name(ps->ports[i].bridge_dev));
1555 err = -EOPNOTSUPP;
1556 goto unlock;
1557 }
1558 } while (vlan.vid < vid_end);
1559
1560unlock:
1561 mutex_unlock(&ps->smi_mutex);
1562
1563 return err;
1564}
1565
76e398a6
VD		 1566int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1567 const struct switchdev_obj_port_vlan *vlan,
1568 struct switchdev_trans *trans)
1569{
da9c359e
VD		 1570 int err;
1571
e79a8bcb
VD		 1572 /* We reserve a few VLANs to isolate unbridged ports */
1573 if (vlan->vid_end >= 4000)
1574 return -EOPNOTSUPP;
1575
da9c359e
VD		 1576 /* If the requested port doesn't belong to the same bridge as the VLAN
1577 * members, do not support it (yet) and fallback to software VLAN.
1578 */
1579 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1580 vlan->vid_end);
1581 if (err)
1582 return err;
1583
76e398a6
VD		 1584 /* We don't need any dynamic resource from the kernel (yet),
1585 * so skip the prepare phase.
1586 */
1587 return 0;
1588}
1589
1590static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1591 bool untagged)
0d3b33e6 1592{
0d3b33e6
VD		 1593 struct mv88e6xxx_vtu_stu_entry vlan;
1594 int err;
1595
36d04ba1
VD		 1596 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1597 if (err)
76e398a6 1598 return err;
36d04ba1
VD		 1599
1600 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
0d3b33e6 1601 if (err)
76e398a6 1602 return err;
0d3b33e6
VD		 1603
1604 if (vlan.vid != vid || !vlan.valid) {
1605 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1606 if (err)
76e398a6 1607 return err;
0d3b33e6
VD		 1608 }
1609
1610 vlan.data[port] = untagged ?
1611 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1612 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1613
76e398a6
VD		 1614 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1615}
1616
1617int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1618 const struct switchdev_obj_port_vlan *vlan,
1619 struct switchdev_trans *trans)
1620{
1621 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1622 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1623 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1624 u16 vid;
1625 int err = 0;
1626
1627 mutex_lock(&ps->smi_mutex);
1628
1629 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1630 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1631 if (err)
1632 goto unlock;
1633 }
1634
1635 /* no PVID with ranges, otherwise it's a bug */
1636 if (pvid)
db0e51af 1637 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
0d3b33e6
VD		 1638unlock:
1639 mutex_unlock(&ps->smi_mutex);
1640
1641 return err;
1642}
1643
76e398a6 1644static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
7dad08d7
VD		 1645{
1646 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1647 struct mv88e6xxx_vtu_stu_entry vlan;
7dad08d7
VD		 1648 int i, err;
1649
36d04ba1
VD		 1650 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1651 if (err)
76e398a6 1652 return err;
36d04ba1
VD		 1653
1654 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
7dad08d7 1655 if (err)
76e398a6 1656 return err;
7dad08d7
VD		 1657
1658 if (vlan.vid != vid || !vlan.valid ||
76e398a6 1659 vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
3c06f08b 1660 return -EOPNOTSUPP;
7dad08d7
VD		 1661
1662 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1663
1664 /* keep the VLAN unless all ports are excluded */
f02bdffc 1665 vlan.valid = false;
7dad08d7 1666 for (i = 0; i < ps->num_ports; ++i) {
3d131f07 1667 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
7dad08d7
VD		 1668 continue;
1669
1670 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
f02bdffc 1671 vlan.valid = true;
7dad08d7
VD		 1672 break;
1673 }
1674 }
1675
7dad08d7 1676 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
76e398a6
VD		 1677 if (err)
1678 return err;
1679
1680 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1681}
1682
1683int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1684 const struct switchdev_obj_port_vlan *vlan)
1685{
1686 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
66d9cd0f 1687 const u16 defpvid = 4000 + ds->index * DSA_MAX_PORTS + port;
76e398a6
VD		 1688 u16 pvid, vid;
1689 int err = 0;
1690
1691 mutex_lock(&ps->smi_mutex);
1692
1693 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
7dad08d7
VD		 1694 if (err)
1695 goto unlock;
1696
76e398a6
VD		 1697 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1698 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1699 if (err)
1700 goto unlock;
1701
1702 if (vid == pvid) {
66d9cd0f
VD		 1703 /* restore reserved VLAN ID */
1704 err = _mv88e6xxx_port_pvid_set(ds, port, defpvid);
76e398a6
VD		 1705 if (err)
1706 goto unlock;
1707 }
1708 }
1709
7dad08d7
VD		 1710unlock:
1711 mutex_unlock(&ps->smi_mutex);
1712
1713 return err;
1714}
1715
c5723ac5
VD		 1716static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1717 const unsigned char *addr)
defb05b9
GR		 1718{
1719 int i, ret;
1720
1721 for (i = 0; i < 3; i++) {
cca8b133
AL		 1722 ret = _mv88e6xxx_reg_write(
1723 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1724 (addr[i * 2] << 8) | addr[i * 2 + 1]);
defb05b9
GR		 1725 if (ret < 0)
1726 return ret;
1727 }
1728
1729 return 0;
1730}
1731
c5723ac5 1732static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
defb05b9
GR		 1733{
1734 int i, ret;
1735
1736 for (i = 0; i < 3; i++) {
cca8b133
AL		 1737 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1738 GLOBAL_ATU_MAC_01 + i);
defb05b9
GR		 1739 if (ret < 0)
1740 return ret;
1741 addr[i * 2] = ret >> 8;
1742 addr[i * 2 + 1] = ret & 0xff;
1743 }
1744
1745 return 0;
1746}
1747
fd231c82
VD		 1748static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1749 struct mv88e6xxx_atu_entry *entry)
defb05b9 1750{
6630e236
VD		 1751 int ret;
1752
defb05b9
GR		 1753 ret = _mv88e6xxx_atu_wait(ds);
1754 if (ret < 0)
1755 return ret;
1756
fd231c82 1757 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
defb05b9
GR		 1758 if (ret < 0)
1759 return ret;
1760
37705b73 1761 ret = _mv88e6xxx_atu_data_write(ds, entry);
fd231c82 1762 if (ret < 0)
87820510
VD		 1763 return ret;
1764
70cc99d1
VD		 1765 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1766 if (ret < 0)
1767 return ret;
1768
1769 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
fd231c82 1770}
87820510 1771
fd231c82
VD		 1772static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1773 const unsigned char *addr, u16 vid,
1774 u8 state)
1775{
1776 struct mv88e6xxx_atu_entry entry = { 0 };
fd231c82 1777
f02bdffc 1778 entry.fid = vid; /* We use one FID per VLAN */
fd231c82
VD		 1779 entry.state = state;
1780 ether_addr_copy(entry.mac, addr);
1781 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1782 entry.trunk = false;
1783 entry.portv_trunkid = BIT(port);
1784 }
1785
1786 return _mv88e6xxx_atu_load(ds, &entry);
87820510
VD		 1787}
1788
146a3206
VD		 1789int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1790 const struct switchdev_obj_port_fdb *fdb,
1791 struct switchdev_trans *trans)
1792{
f02bdffc
VD		 1793 /* We don't use per-port FDB */
1794 if (fdb->vid == 0)
1795 return -EOPNOTSUPP;
1796
146a3206
VD		 1797 /* We don't need any dynamic resource from the kernel (yet),
1798 * so skip the prepare phase.
1799 */
1800 return 0;
1801}
1802
cdf09697 1803int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1f36faf2
VD		 1804 const struct switchdev_obj_port_fdb *fdb,
1805 struct switchdev_trans *trans)
87820510 1806{
1f36faf2 1807 int state = is_multicast_ether_addr(fdb->addr) ?
87820510
VD		 1808 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1809 GLOBAL_ATU_DATA_STATE_UC_STATIC;
cdf09697 1810 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1811 int ret;
1812
1813 mutex_lock(&ps->smi_mutex);
1f36faf2 1814 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
87820510
VD		 1815 mutex_unlock(&ps->smi_mutex);
1816
1817 return ret;
1818}
1819
cdf09697 1820int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
8057b3e7 1821 const struct switchdev_obj_port_fdb *fdb)
87820510
VD		 1822{
1823 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
87820510
VD		 1824 int ret;
1825
1826 mutex_lock(&ps->smi_mutex);
8057b3e7 1827 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
cdf09697 1828 GLOBAL_ATU_DATA_STATE_UNUSED);
87820510
VD		 1829 mutex_unlock(&ps->smi_mutex);
1830
1831 return ret;
1832}
1833
1d194046 1834static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1d194046 1835 struct mv88e6xxx_atu_entry *entry)
6630e236 1836{
1d194046
VD		 1837 struct mv88e6xxx_atu_entry next = { 0 };
1838 int ret;
1839
1840 next.fid = fid;
defb05b9 1841
cdf09697
DM		 1842 ret = _mv88e6xxx_atu_wait(ds);
1843 if (ret < 0)
1844 return ret;
6630e236 1845
70cc99d1
VD		 1846 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1847 if (ret < 0)
1848 return ret;
1849
1850 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1d194046
VD		 1851 if (ret < 0)
1852 return ret;
6630e236 1853
1d194046
VD		 1854 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1855 if (ret < 0)
1856 return ret;
6630e236 1857
1d194046 1858 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
cdf09697
DM		 1859 if (ret < 0)
1860 return ret;
6630e236 1861
1d194046
VD		 1862 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1863 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1864 unsigned int mask, shift;
1865
1866 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1867 next.trunk = true;
1868 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1869 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1870 } else {
1871 next.trunk = false;
1872 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1873 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1874 }
1875
1876 next.portv_trunkid = (ret & mask) >> shift;
1877 }
cdf09697 1878
1d194046 1879 *entry = next;
cdf09697
DM		 1880 return 0;
1881}
1882
f33475bd
VD		 1883int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1884 struct switchdev_obj_port_fdb *fdb,
1885 int (*cb)(struct switchdev_obj *obj))
1886{
1887 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1888 struct mv88e6xxx_vtu_stu_entry vlan = {
1889 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
1890 };
1891 int err;
1892
1893 mutex_lock(&ps->smi_mutex);
1894
1895 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
1896 if (err)
1897 goto unlock;
1898
1899 do {
1900 struct mv88e6xxx_atu_entry addr = {
1901 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
1902 };
1903
1904 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1905 if (err)
1906 goto unlock;
1907
1908 if (!vlan.valid)
1909 break;
1910
1911 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
1912 if (err)
1913 goto unlock;
1914
1915 do {
1916 err = _mv88e6xxx_atu_getnext(ds, vlan.fid, &addr);
1917 if (err)
1918 goto unlock;
1919
1920 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1921 break;
1922
1923 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
1924 bool is_static = addr.state ==
1925 (is_multicast_ether_addr(addr.mac) ?
1926 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1927 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1928
1929 fdb->vid = vlan.vid;
1930 ether_addr_copy(fdb->addr, addr.mac);
1931 fdb->ndm_state = is_static ? NUD_NOARP :
1932 NUD_REACHABLE;
1933
1934 err = cb(&fdb->obj);
1935 if (err)
1936 goto unlock;
1937 }
1938 } while (!is_broadcast_ether_addr(addr.mac));
1939
1940 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1941
1942unlock:
1943 mutex_unlock(&ps->smi_mutex);
1944
1945 return err;
1946}
1947
a6692754
VD		 1948int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1949 struct net_device *bridge)
e79a8bcb 1950{
a6692754
VD		 1951 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1952
1953 ps->ports[port].bridge_dev = bridge;
1954
66d9cd0f 1955 return 0;
e79a8bcb
VD		 1956}
1957
a6692754 1958int mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
66d9cd0f 1959{
a6692754
VD		 1960 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1961
1962 ps->ports[port].bridge_dev = NULL;
1963
66d9cd0f
VD		 1964 return 0;
1965}
1966
1967static int mv88e6xxx_setup_port_default_vlan(struct dsa_switch *ds, int port)
e79a8bcb
VD		 1968{
1969 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1970 const u16 pvid = 4000 + ds->index * DSA_MAX_PORTS + port;
1971 int err;
1972
e79a8bcb
VD		 1973 mutex_lock(&ps->smi_mutex);
1974 err = _mv88e6xxx_port_vlan_add(ds, port, pvid, true);
1975 if (!err)
1976 err = _mv88e6xxx_port_pvid_set(ds, port, pvid);
1977 mutex_unlock(&ps->smi_mutex);
1978 return err;
1979}
1980
facd95b2
GR		 1981static void mv88e6xxx_bridge_work(struct work_struct *work)
1982{
1983 struct mv88e6xxx_priv_state *ps;
1984 struct dsa_switch *ds;
1985 int port;
1986
1987 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1988 ds = ((struct dsa_switch *)ps) - 1;
1989
1990 while (ps->port_state_update_mask) {
1991 port = __ffs(ps->port_state_update_mask);
1992 clear_bit(port, &ps->port_state_update_mask);
d715fa64 1993 mv88e6xxx_set_port_state(ds, port, ps->ports[port].state);
facd95b2
GR		 1994 }
1995}
1996
dbde9e66 1997static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
d827e88a
GR		 1998{
1999 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
f02bdffc 2000 int ret;
54d792f2 2001 u16 reg;
d827e88a
GR		 2002
2003 mutex_lock(&ps->smi_mutex);
2004
54d792f2
AL		 2005 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2006 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2007 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
7c3d0d67 2008 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2009 /* MAC Forcing register: don't force link, speed,
2010 * duplex or flow control state to any particular
2011 * values on physical ports, but force the CPU port
2012 * and all DSA ports to their maximum bandwidth and
2013 * full duplex.
2014 */
2015 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
60045cbf 2016 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
53adc9e8 2017 reg &= ~PORT_PCS_CTRL_UNFORCED;
54d792f2
AL		 2018 reg |= PORT_PCS_CTRL_FORCE_LINK |
2019 PORT_PCS_CTRL_LINK_UP |
2020 PORT_PCS_CTRL_DUPLEX_FULL |
2021 PORT_PCS_CTRL_FORCE_DUPLEX;
2022 if (mv88e6xxx_6065_family(ds))
2023 reg |= PORT_PCS_CTRL_100;
2024 else
2025 reg |= PORT_PCS_CTRL_1000;
2026 } else {
2027 reg |= PORT_PCS_CTRL_UNFORCED;
2028 }
2029
2030 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2031 PORT_PCS_CTRL, reg);
2032 if (ret)
2033 goto abort;
2034 }
2035
2036 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2037 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2038 * tunneling, determine priority by looking at 802.1p and IP
2039 * priority fields (IP prio has precedence), and set STP state
2040 * to Forwarding.
2041 *
2042 * If this is the CPU link, use DSA or EDSA tagging depending
2043 * on which tagging mode was configured.
2044 *
2045 * If this is a link to another switch, use DSA tagging mode.
2046 *
2047 * If this is the upstream port for this switch, enable
2048 * forwarding of unknown unicasts and multicasts.
2049 */
2050 reg = 0;
2051 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2052 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2053 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2054 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2055 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2056 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2057 PORT_CONTROL_STATE_FORWARDING;
2058 if (dsa_is_cpu_port(ds, port)) {
2059 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2060 reg |= PORT_CONTROL_DSA_TAG;
2061 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2062 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2063 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2064 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2065 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2066 else
2067 reg |= PORT_CONTROL_FRAME_MODE_DSA;
c047a1f9
AL		 2068 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2069 PORT_CONTROL_FORWARD_UNKNOWN_MC;
54d792f2
AL		 2070 }
2071
2072 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2073 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2074 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
7c3d0d67 2075 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2076 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2077 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2078 }
2079 }
6083ce71
AL		 2080 if (dsa_is_dsa_port(ds, port)) {
2081 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2082 reg |= PORT_CONTROL_DSA_TAG;
2083 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2084 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2085 mv88e6xxx_6320_family(ds)) {
54d792f2 2086 reg |= PORT_CONTROL_FRAME_MODE_DSA;
6083ce71
AL		 2087 }
2088
54d792f2
AL		 2089 if (port == dsa_upstream_port(ds))
2090 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2091 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2092 }
2093 if (reg) {
2094 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2095 PORT_CONTROL, reg);
2096 if (ret)
2097 goto abort;
2098 }
2099
8efdda4a
VD		 2100 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2101 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2102 * untagged frames on this port, do a destination address lookup on all
2103 * received packets as usual, disable ARP mirroring and don't send a
2104 * copy of all transmitted/received frames on this port to the CPU.
54d792f2
AL		 2105 */
2106 reg = 0;
2107 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2108 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67 2109 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2110 reg = PORT_CONTROL_2_MAP_DA;
2111
2112 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67 2113 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
54d792f2
AL		 2114 reg |= PORT_CONTROL_2_JUMBO_10240;
2115
2116 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2117 /* Set the upstream port this port should use */
2118 reg |= dsa_upstream_port(ds);
2119 /* enable forwarding of unknown multicast addresses to
2120 * the upstream port
2121 */
2122 if (port == dsa_upstream_port(ds))
2123 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2124 }
2125
5fe7f680 2126 reg |= PORT_CONTROL_2_8021Q_SECURE;
8efdda4a 2127
54d792f2
AL		 2128 if (reg) {
2129 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2130 PORT_CONTROL_2, reg);
2131 if (ret)
2132 goto abort;
2133 }
2134
2135 /* Port Association Vector: when learning source addresses
2136 * of packets, add the address to the address database using
2137 * a port bitmap that has only the bit for this port set and
2138 * the other bits clear.
2139 */
4c7ea3c0
AL		 2140 reg = 1 << port;
2141 /* Disable learning for DSA and CPU ports */
2142 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2143 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2144
2145 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
54d792f2
AL		 2146 if (ret)
2147 goto abort;
2148
2149 /* Egress rate control 2: disable egress rate control. */
2150 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2151 0x0000);
2152 if (ret)
2153 goto abort;
2154
2155 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2156 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2157 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2158 /* Do not limit the period of time that this port can
2159 * be paused for by the remote end or the period of
2160 * time that this port can pause the remote end.
2161 */
2162 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2163 PORT_PAUSE_CTRL, 0x0000);
2164 if (ret)
2165 goto abort;
2166
2167 /* Port ATU control: disable limiting the number of
2168 * address database entries that this port is allowed
2169 * to use.
2170 */
2171 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2172 PORT_ATU_CONTROL, 0x0000);
2173 /* Priority Override: disable DA, SA and VTU priority
2174 * override.
2175 */
2176 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2177 PORT_PRI_OVERRIDE, 0x0000);
2178 if (ret)
2179 goto abort;
2180
2181 /* Port Ethertype: use the Ethertype DSA Ethertype
2182 * value.
2183 */
2184 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2185 PORT_ETH_TYPE, ETH_P_EDSA);
2186 if (ret)
2187 goto abort;
2188 /* Tag Remap: use an identity 802.1p prio -> switch
2189 * prio mapping.
2190 */
2191 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2192 PORT_TAG_REGMAP_0123, 0x3210);
2193 if (ret)
2194 goto abort;
2195
2196 /* Tag Remap 2: use an identity 802.1p prio -> switch
2197 * prio mapping.
2198 */
2199 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2200 PORT_TAG_REGMAP_4567, 0x7654);
2201 if (ret)
2202 goto abort;
2203 }
2204
2205 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2206 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2207 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2208 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2209 /* Rate Control: disable ingress rate limiting. */
2210 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2211 PORT_RATE_CONTROL, 0x0001);
2212 if (ret)
2213 goto abort;
2214 }
2215
366f0a0f
GR		 2216 /* Port Control 1: disable trunking, disable sending
2217 * learning messages to this port.
d827e88a 2218 */
614f03fc 2219 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
d827e88a
GR		 2220 if (ret)
2221 goto abort;
2222
f02bdffc 2223 /* Port based VLAN map: do not give each port its own address
5fe7f680 2224 * database, and allow every port to egress frames on all other ports.
d827e88a 2225 */
5fe7f680 2226 reg = BIT(ps->num_ports) - 1; /* all ports */
be1faa92
VD		 2227 reg &= ~BIT(port); /* except itself */
2228 ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg);
d827e88a
GR		 2229 if (ret)
2230 goto abort;
2231
2232 /* Default VLAN ID and priority: don't set a default VLAN
2233 * ID, and set the default packet priority to zero.
2234 */
47cf1e65
VD		 2235 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2236 0x0000);
d827e88a
GR		 2237abort:
2238 mutex_unlock(&ps->smi_mutex);
2239 return ret;
2240}
2241
dbde9e66
AL		 2242int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2243{
2244 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2245 int ret;
2246 int i;
2247
2248 for (i = 0; i < ps->num_ports; i++) {
2249 ret = mv88e6xxx_setup_port(ds, i);
2250 if (ret < 0)
2251 return ret;
e79a8bcb
VD		 2252
2253 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2254 continue;
2255
66d9cd0f 2256 ret = mv88e6xxx_setup_port_default_vlan(ds, i);
e79a8bcb
VD		 2257 if (ret < 0)
2258 return ret;
dbde9e66
AL		 2259 }
2260 return 0;
2261}
2262
acdaffcc
GR		 2263int mv88e6xxx_setup_common(struct dsa_switch *ds)
2264{
2265 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2266
2267 mutex_init(&ps->smi_mutex);
acdaffcc 2268
cca8b133 2269 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
a8f064c6 2270
facd95b2
GR		 2271 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2272
acdaffcc
GR		 2273 return 0;
2274}
2275
54d792f2
AL		 2276int mv88e6xxx_setup_global(struct dsa_switch *ds)
2277{
2278 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
24751e29 2279 int ret;
54d792f2
AL		 2280 int i;
2281
2282 /* Set the default address aging time to 5 minutes, and
2283 * enable address learn messages to be sent to all message
2284 * ports.
2285 */
2286 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2287 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2288
2289 /* Configure the IP ToS mapping registers. */
2290 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2291 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2292 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2293 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2294 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2295 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2296 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2297 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2298
2299 /* Configure the IEEE 802.1p priority mapping register. */
2300 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2301
2302 /* Send all frames with destination addresses matching
2303 * 01:80:c2:00:00:0x to the CPU port.
2304 */
2305 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2306
2307 /* Ignore removed tag data on doubly tagged packets, disable
2308 * flow control messages, force flow control priority to the
2309 * highest, and send all special multicast frames to the CPU
2310 * port at the highest priority.
2311 */
2312 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2313 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2314 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2315
2316 /* Program the DSA routing table. */
2317 for (i = 0; i < 32; i++) {
2318 int nexthop = 0x1f;
2319
2320 if (ds->pd->rtable &&
2321 i != ds->index && i < ds->dst->pd->nr_chips)
2322 nexthop = ds->pd->rtable[i] & 0x1f;
2323
2324 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2325 GLOBAL2_DEVICE_MAPPING_UPDATE |
2326 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2327 nexthop);
2328 }
2329
2330 /* Clear all trunk masks. */
2331 for (i = 0; i < 8; i++)
2332 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2333 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2334 ((1 << ps->num_ports) - 1));
2335
2336 /* Clear all trunk mappings. */
2337 for (i = 0; i < 16; i++)
2338 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2339 GLOBAL2_TRUNK_MAPPING_UPDATE |
2340 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2341
2342 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
7c3d0d67
AK		 2343 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2344 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2345 /* Send all frames with destination addresses matching
2346 * 01:80:c2:00:00:2x to the CPU port.
2347 */
2348 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2349
2350 /* Initialise cross-chip port VLAN table to reset
2351 * defaults.
2352 */
2353 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2354
2355 /* Clear the priority override table. */
2356 for (i = 0; i < 16; i++)
2357 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2358 0x8000 | (i << 8));
2359 }
2360
2361 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2362 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
7c3d0d67
AK		 2363 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2364 mv88e6xxx_6320_family(ds)) {
54d792f2
AL		 2365 /* Disable ingress rate limiting by resetting all
2366 * ingress rate limit registers to their initial
2367 * state.
2368 */
2369 for (i = 0; i < ps->num_ports; i++)
2370 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2371 0x9000 | (i << 8));
2372 }
2373
db687a56
AL		 2374 /* Clear the statistics counters for all ports */
2375 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2376
2377 /* Wait for the flush to complete. */
24751e29
VD		 2378 mutex_lock(&ps->smi_mutex);
2379 ret = _mv88e6xxx_stats_wait(ds);
6b17e864
VD		 2380 if (ret < 0)
2381 goto unlock;
2382
c161d0a5
VD		 2383 /* Clear all ATU entries */
2384 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2385 if (ret < 0)
2386 goto unlock;
2387
6b17e864
VD		 2388 /* Clear all the VTU and STU entries */
2389 ret = _mv88e6xxx_vtu_stu_flush(ds);
2390unlock:
24751e29 2391 mutex_unlock(&ps->smi_mutex);
db687a56 2392
24751e29 2393 return ret;
54d792f2
AL		 2394}
2395
143a8307
AL		 2396int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2397{
2398 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2399 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
c8c1b39a 2400 struct gpio_desc *gpiod = ds->pd->reset;
143a8307
AL		 2401 unsigned long timeout;
2402 int ret;
2403 int i;
2404
2405 /* Set all ports to the disabled state. */
2406 for (i = 0; i < ps->num_ports; i++) {
cca8b133
AL		 2407 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2408 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
143a8307
AL		 2409 }
2410
2411 /* Wait for transmit queues to drain. */
2412 usleep_range(2000, 4000);
2413
c8c1b39a
AL		 2414 /* If there is a gpio connected to the reset pin, toggle it */
2415 if (gpiod) {
2416 gpiod_set_value_cansleep(gpiod, 1);
2417 usleep_range(10000, 20000);
2418 gpiod_set_value_cansleep(gpiod, 0);
2419 usleep_range(10000, 20000);
2420 }
2421
143a8307
AL		 2422 /* Reset the switch. Keep the PPU active if requested. The PPU
2423 * needs to be active to support indirect phy register access
2424 * through global registers 0x18 and 0x19.
2425 */
2426 if (ppu_active)
2427 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2428 else
2429 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2430
2431 /* Wait up to one second for reset to complete. */
2432 timeout = jiffies + 1 * HZ;
2433 while (time_before(jiffies, timeout)) {
2434 ret = REG_READ(REG_GLOBAL, 0x00);
2435 if ((ret & is_reset) == is_reset)
2436 break;
2437 usleep_range(1000, 2000);
2438 }
2439 if (time_after(jiffies, timeout))
2440 return -ETIMEDOUT;
2441
2442 return 0;
2443}
2444
49143585
AL		 2445int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2446{
2447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2448 int ret;
2449
3898c148 2450 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2451 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2452 if (ret < 0)
2453 goto error;
fd3a0ee4 2454 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
49143585 2455error:
fd3a0ee4 2456 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2457 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2458 return ret;
2459}
2460
2461int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2462 int reg, int val)
2463{
2464 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2465 int ret;
2466
3898c148 2467 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2468 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
49143585
AL		 2469 if (ret < 0)
2470 goto error;
2471
fd3a0ee4 2472 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
49143585 2473error:
fd3a0ee4 2474 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
3898c148 2475 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2476 return ret;
2477}
2478
2479static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2480{
2481 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2482
2483 if (port >= 0 && port < ps->num_ports)
2484 return port;
2485 return -EINVAL;
2486}
2487
2488int
2489mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2490{
2491 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2492 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2493 int ret;
2494
2495 if (addr < 0)
2496 return addr;
2497
3898c148 2498 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2499 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
3898c148 2500 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2501 return ret;
2502}
2503
2504int
2505mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2506{
2507 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2508 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2509 int ret;
2510
2511 if (addr < 0)
2512 return addr;
2513
3898c148 2514 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2515 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
3898c148 2516 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2517 return ret;
2518}
2519
2520int
2521mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2522{
2523 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2524 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2525 int ret;
2526
2527 if (addr < 0)
2528 return addr;
2529
3898c148 2530 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2531 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
3898c148 2532 mutex_unlock(&ps->smi_mutex);
fd3a0ee4
AL		 2533 return ret;
2534}
2535
2536int
2537mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2538 u16 val)
2539{
2540 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2541 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2542 int ret;
2543
2544 if (addr < 0)
2545 return addr;
2546
3898c148 2547 mutex_lock(&ps->smi_mutex);
fd3a0ee4 2548 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
3898c148 2549 mutex_unlock(&ps->smi_mutex);
49143585
AL		 2550 return ret;
2551}
2552
c22995c5
GR		 2553#ifdef CONFIG_NET_DSA_HWMON
2554
2555static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2556{
2557 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2558 int ret;
2559 int val;
2560
2561 *temp = 0;
2562
2563 mutex_lock(&ps->smi_mutex);
2564
2565 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2566 if (ret < 0)
2567 goto error;
2568
2569 /* Enable temperature sensor */
2570 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2571 if (ret < 0)
2572 goto error;
2573
2574 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2575 if (ret < 0)
2576 goto error;
2577
2578 /* Wait for temperature to stabilize */
2579 usleep_range(10000, 12000);
2580
2581 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2582 if (val < 0) {
2583 ret = val;
2584 goto error;
2585 }
2586
2587 /* Disable temperature sensor */
2588 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2589 if (ret < 0)
2590 goto error;
2591
2592 *temp = ((val & 0x1f) - 5) * 5;
2593
2594error:
2595 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2596 mutex_unlock(&ps->smi_mutex);
2597 return ret;
2598}
2599
2600static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2601{
2602 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2603 int ret;
2604
2605 *temp = 0;
2606
2607 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2608 if (ret < 0)
2609 return ret;
2610
2611 *temp = (ret & 0xff) - 25;
2612
2613 return 0;
2614}
2615
2616int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2617{
2618 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2619 return mv88e63xx_get_temp(ds, temp);
2620
2621 return mv88e61xx_get_temp(ds, temp);
2622}
2623
2624int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2625{
2626 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2627 int ret;
2628
2629 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2630 return -EOPNOTSUPP;
2631
2632 *temp = 0;
2633
2634 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2635 if (ret < 0)
2636 return ret;
2637
2638 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2639
2640 return 0;
2641}
2642
2643int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2644{
2645 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2646 int ret;
2647
2648 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2649 return -EOPNOTSUPP;
2650
2651 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2652 if (ret < 0)
2653 return ret;
2654 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2655 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2656 (ret & 0xe0ff) | (temp << 8));
2657}
2658
2659int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2660{
2661 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2662 int ret;
2663
2664 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2665 return -EOPNOTSUPP;
2666
2667 *alarm = false;
2668
2669 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2670 if (ret < 0)
2671 return ret;
2672
2673 *alarm = !!(ret & 0x40);
2674
2675 return 0;
2676}
2677#endif /* CONFIG_NET_DSA_HWMON */
2678
b9b37713
VD		 2679char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
2680 const struct mv88e6xxx_switch_id *table,
2681 unsigned int num)
2682{
2683 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2684 int i, ret;
2685
2686 if (!bus)
2687 return NULL;
2688
2689 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
2690 if (ret < 0)
2691 return NULL;
2692
2693 /* Look up the exact switch ID */
2694 for (i = 0; i < num; ++i)
2695 if (table[i].id == ret)
2696 return table[i].name;
2697
2698 /* Look up only the product number */
2699 for (i = 0; i < num; ++i) {
2700 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
2701 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
2702 ret & PORT_SWITCH_ID_REV_MASK,
2703 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
2704 return table[i].name;
2705 }
2706 }
2707
2708 return NULL;
2709}
2710
98e67308
BH		 2711static int __init mv88e6xxx_init(void)
2712{
2713#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2714 register_switch_driver(&mv88e6131_switch_driver);
2715#endif
2716#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2717 register_switch_driver(&mv88e6123_61_65_switch_driver);
42f27253 2718#endif
3ad50cca
GR		 2719#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2720 register_switch_driver(&mv88e6352_switch_driver);
2721#endif
42f27253
AL		 2722#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2723 register_switch_driver(&mv88e6171_switch_driver);
98e67308
BH		 2724#endif
2725 return 0;
2726}
2727module_init(mv88e6xxx_init);
2728
2729static void __exit mv88e6xxx_cleanup(void)
2730{
42f27253
AL		 2731#if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2732 unregister_switch_driver(&mv88e6171_switch_driver);
2733#endif
4212b543
VD		 2734#if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2735 unregister_switch_driver(&mv88e6352_switch_driver);
2736#endif
98e67308
BH		 2737#if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2738 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2739#endif
2740#if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2741 unregister_switch_driver(&mv88e6131_switch_driver);
2742#endif
2743}
2744module_exit(mv88e6xxx_cleanup);
3d825ede
BH		 2745
2746MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2747MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2748MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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