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91da11f8 LB |
1 | /* |
2 | * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support | |
3 | * Copyright (c) 2008 Marvell Semiconductor | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | */ | |
10 | ||
11 | #ifndef __MV88E6XXX_H | |
12 | #define __MV88E6XXX_H | |
13 | ||
194fea7b VD |
14 | #include <linux/if_vlan.h> |
15 | ||
80c4627b AL |
16 | #ifndef UINT64_MAX |
17 | #define UINT64_MAX (u64)(~((u64)0)) | |
18 | #endif | |
19 | ||
cca8b133 AL |
20 | #define SMI_CMD 0x00 |
21 | #define SMI_CMD_BUSY BIT(15) | |
22 | #define SMI_CMD_CLAUSE_22 BIT(12) | |
23 | #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) | |
24 | #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22) | |
25 | #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY) | |
26 | #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY) | |
27 | #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY) | |
28 | #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY) | |
29 | #define SMI_DATA 0x01 | |
b2eb0662 | 30 | |
13a7ebb3 PU |
31 | /* Fiber/SERDES Registers are located at SMI address F, page 1 */ |
32 | #define REG_FIBER_SERDES 0x0f | |
33 | #define PAGE_FIBER_SERDES 0x01 | |
34 | ||
91da11f8 | 35 | #define REG_PORT(p) (0x10 + (p)) |
cca8b133 AL |
36 | #define PORT_STATUS 0x00 |
37 | #define PORT_STATUS_PAUSE_EN BIT(15) | |
38 | #define PORT_STATUS_MY_PAUSE BIT(14) | |
39 | #define PORT_STATUS_HD_FLOW BIT(13) | |
40 | #define PORT_STATUS_PHY_DETECT BIT(12) | |
41 | #define PORT_STATUS_LINK BIT(11) | |
42 | #define PORT_STATUS_DUPLEX BIT(10) | |
43 | #define PORT_STATUS_SPEED_MASK 0x0300 | |
44 | #define PORT_STATUS_SPEED_10 0x0000 | |
45 | #define PORT_STATUS_SPEED_100 0x0100 | |
46 | #define PORT_STATUS_SPEED_1000 0x0200 | |
47 | #define PORT_STATUS_EEE BIT(6) /* 6352 */ | |
48 | #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */ | |
49 | #define PORT_STATUS_MGMII BIT(6) /* 6185 */ | |
50 | #define PORT_STATUS_TX_PAUSED BIT(5) | |
51 | #define PORT_STATUS_FLOW_CTRL BIT(4) | |
13a7ebb3 PU |
52 | #define PORT_STATUS_CMODE_MASK 0x0f |
53 | #define PORT_STATUS_CMODE_100BASE_X 0x8 | |
54 | #define PORT_STATUS_CMODE_1000BASE_X 0x9 | |
55 | #define PORT_STATUS_CMODE_SGMII 0xa | |
cca8b133 | 56 | #define PORT_PCS_CTRL 0x01 |
e7e72ac0 AL |
57 | #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15) |
58 | #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14) | |
54d792f2 AL |
59 | #define PORT_PCS_CTRL_FC BIT(7) |
60 | #define PORT_PCS_CTRL_FORCE_FC BIT(6) | |
61 | #define PORT_PCS_CTRL_LINK_UP BIT(5) | |
62 | #define PORT_PCS_CTRL_FORCE_LINK BIT(4) | |
63 | #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3) | |
64 | #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2) | |
65 | #define PORT_PCS_CTRL_10 0x00 | |
66 | #define PORT_PCS_CTRL_100 0x01 | |
67 | #define PORT_PCS_CTRL_1000 0x02 | |
68 | #define PORT_PCS_CTRL_UNFORCED 0x03 | |
69 | #define PORT_PAUSE_CTRL 0x02 | |
cca8b133 | 70 | #define PORT_SWITCH_ID 0x03 |
b9b37713 VD |
71 | #define PORT_SWITCH_ID_PROD_NUM_MASK 0xfff0 |
72 | #define PORT_SWITCH_ID_REV_MASK 0x000f | |
54d792f2 AL |
73 | #define PORT_SWITCH_ID_6031 0x0310 |
74 | #define PORT_SWITCH_ID_6035 0x0350 | |
75 | #define PORT_SWITCH_ID_6046 0x0480 | |
76 | #define PORT_SWITCH_ID_6061 0x0610 | |
77 | #define PORT_SWITCH_ID_6065 0x0650 | |
cca8b133 | 78 | #define PORT_SWITCH_ID_6085 0x04a0 |
54d792f2 | 79 | #define PORT_SWITCH_ID_6092 0x0970 |
cca8b133 | 80 | #define PORT_SWITCH_ID_6095 0x0950 |
54d792f2 AL |
81 | #define PORT_SWITCH_ID_6096 0x0980 |
82 | #define PORT_SWITCH_ID_6097 0x0990 | |
83 | #define PORT_SWITCH_ID_6108 0x1070 | |
84 | #define PORT_SWITCH_ID_6121 0x1040 | |
85 | #define PORT_SWITCH_ID_6122 0x1050 | |
cca8b133 AL |
86 | #define PORT_SWITCH_ID_6123 0x1210 |
87 | #define PORT_SWITCH_ID_6123_A1 0x1212 | |
88 | #define PORT_SWITCH_ID_6123_A2 0x1213 | |
89 | #define PORT_SWITCH_ID_6131 0x1060 | |
90 | #define PORT_SWITCH_ID_6131_B2 0x1066 | |
91 | #define PORT_SWITCH_ID_6152 0x1a40 | |
92 | #define PORT_SWITCH_ID_6155 0x1a50 | |
93 | #define PORT_SWITCH_ID_6161 0x1610 | |
94 | #define PORT_SWITCH_ID_6161_A1 0x1612 | |
95 | #define PORT_SWITCH_ID_6161_A2 0x1613 | |
96 | #define PORT_SWITCH_ID_6165 0x1650 | |
97 | #define PORT_SWITCH_ID_6165_A1 0x1652 | |
98 | #define PORT_SWITCH_ID_6165_A2 0x1653 | |
99 | #define PORT_SWITCH_ID_6171 0x1710 | |
100 | #define PORT_SWITCH_ID_6172 0x1720 | |
54d792f2 | 101 | #define PORT_SWITCH_ID_6175 0x1750 |
cca8b133 AL |
102 | #define PORT_SWITCH_ID_6176 0x1760 |
103 | #define PORT_SWITCH_ID_6182 0x1a60 | |
104 | #define PORT_SWITCH_ID_6185 0x1a70 | |
54d792f2 | 105 | #define PORT_SWITCH_ID_6240 0x2400 |
7c3d0d67 AK |
106 | #define PORT_SWITCH_ID_6320 0x1150 |
107 | #define PORT_SWITCH_ID_6320_A1 0x1151 | |
108 | #define PORT_SWITCH_ID_6320_A2 0x1152 | |
109 | #define PORT_SWITCH_ID_6321 0x3100 | |
110 | #define PORT_SWITCH_ID_6321_A1 0x3101 | |
111 | #define PORT_SWITCH_ID_6321_A2 0x3102 | |
54d792f2 AL |
112 | #define PORT_SWITCH_ID_6350 0x3710 |
113 | #define PORT_SWITCH_ID_6351 0x3750 | |
cca8b133 AL |
114 | #define PORT_SWITCH_ID_6352 0x3520 |
115 | #define PORT_SWITCH_ID_6352_A0 0x3521 | |
116 | #define PORT_SWITCH_ID_6352_A1 0x3522 | |
117 | #define PORT_CONTROL 0x04 | |
54d792f2 AL |
118 | #define PORT_CONTROL_USE_CORE_TAG BIT(15) |
119 | #define PORT_CONTROL_DROP_ON_LOCK BIT(14) | |
120 | #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12) | |
121 | #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12) | |
122 | #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12) | |
123 | #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12) | |
124 | #define PORT_CONTROL_HEADER BIT(11) | |
125 | #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10) | |
126 | #define PORT_CONTROL_DOUBLE_TAG BIT(9) | |
127 | #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8) | |
128 | #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8) | |
129 | #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8) | |
130 | #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8) | |
131 | #define PORT_CONTROL_DSA_TAG BIT(8) | |
132 | #define PORT_CONTROL_VLAN_TUNNEL BIT(7) | |
133 | #define PORT_CONTROL_TAG_IF_BOTH BIT(6) | |
134 | #define PORT_CONTROL_USE_IP BIT(5) | |
135 | #define PORT_CONTROL_USE_TAG BIT(4) | |
136 | #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3) | |
137 | #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2) | |
cca8b133 AL |
138 | #define PORT_CONTROL_STATE_MASK 0x03 |
139 | #define PORT_CONTROL_STATE_DISABLED 0x00 | |
140 | #define PORT_CONTROL_STATE_BLOCKING 0x01 | |
141 | #define PORT_CONTROL_STATE_LEARNING 0x02 | |
142 | #define PORT_CONTROL_STATE_FORWARDING 0x03 | |
143 | #define PORT_CONTROL_1 0x05 | |
2db9ce1f | 144 | #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0) |
cca8b133 | 145 | #define PORT_BASE_VLAN 0x06 |
2db9ce1f | 146 | #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12) |
cca8b133 | 147 | #define PORT_DEFAULT_VLAN 0x07 |
b8fee957 | 148 | #define PORT_DEFAULT_VLAN_MASK 0xfff |
cca8b133 | 149 | #define PORT_CONTROL_2 0x08 |
54d792f2 AL |
150 | #define PORT_CONTROL_2_IGNORE_FCS BIT(15) |
151 | #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14) | |
152 | #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13) | |
153 | #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12) | |
154 | #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12) | |
155 | #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12) | |
156 | #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12) | |
8efdda4a VD |
157 | #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10) |
158 | #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10) | |
159 | #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10) | |
160 | #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10) | |
161 | #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10) | |
54d792f2 AL |
162 | #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9) |
163 | #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8) | |
164 | #define PORT_CONTROL_2_MAP_DA BIT(7) | |
165 | #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6) | |
166 | #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6) | |
167 | #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5) | |
168 | #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4) | |
cca8b133 AL |
169 | #define PORT_RATE_CONTROL 0x09 |
170 | #define PORT_RATE_CONTROL_2 0x0a | |
171 | #define PORT_ASSOC_VECTOR 0x0b | |
4c7ea3c0 AL |
172 | #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15) |
173 | #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14) | |
174 | #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13) | |
175 | #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12) | |
176 | #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11) | |
54d792f2 AL |
177 | #define PORT_ATU_CONTROL 0x0c |
178 | #define PORT_PRI_OVERRIDE 0x0d | |
179 | #define PORT_ETH_TYPE 0x0f | |
cca8b133 AL |
180 | #define PORT_IN_DISCARD_LO 0x10 |
181 | #define PORT_IN_DISCARD_HI 0x11 | |
182 | #define PORT_IN_FILTERED 0x12 | |
183 | #define PORT_OUT_FILTERED 0x13 | |
54d792f2 AL |
184 | #define PORT_TAG_REGMAP_0123 0x18 |
185 | #define PORT_TAG_REGMAP_4567 0x19 | |
facd95b2 | 186 | |
cca8b133 AL |
187 | #define REG_GLOBAL 0x1b |
188 | #define GLOBAL_STATUS 0x00 | |
189 | #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */ | |
190 | /* Two bits for 6165, 6185 etc */ | |
191 | #define GLOBAL_STATUS_PPU_MASK (0x3 << 14) | |
192 | #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14) | |
193 | #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14) | |
194 | #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14) | |
195 | #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14) | |
196 | #define GLOBAL_MAC_01 0x01 | |
197 | #define GLOBAL_MAC_23 0x02 | |
198 | #define GLOBAL_MAC_45 0x03 | |
a08df0f0 | 199 | #define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */ |
b8fee957 VD |
200 | #define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */ |
201 | #define GLOBAL_VTU_FID_MASK 0xfff | |
202 | #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */ | |
203 | #define GLOBAL_VTU_SID_MASK 0x3f | |
cca8b133 AL |
204 | #define GLOBAL_CONTROL 0x04 |
205 | #define GLOBAL_CONTROL_SW_RESET BIT(15) | |
206 | #define GLOBAL_CONTROL_PPU_ENABLE BIT(14) | |
207 | #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */ | |
208 | #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */ | |
209 | #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */ | |
54d792f2 | 210 | #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */ |
cca8b133 AL |
211 | #define GLOBAL_CONTROL_DEVICE_EN BIT(7) |
212 | #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6) | |
213 | #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5) | |
214 | #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4) | |
215 | #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3) | |
216 | #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2) | |
217 | #define GLOBAL_CONTROL_TCAM_EN BIT(1) | |
218 | #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0) | |
219 | #define GLOBAL_VTU_OP 0x05 | |
6b17e864 VD |
220 | #define GLOBAL_VTU_OP_BUSY BIT(15) |
221 | #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY) | |
7dad08d7 | 222 | #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY) |
b8fee957 | 223 | #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY) |
0d3b33e6 VD |
224 | #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY) |
225 | #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY) | |
cca8b133 | 226 | #define GLOBAL_VTU_VID 0x06 |
b8fee957 VD |
227 | #define GLOBAL_VTU_VID_MASK 0xfff |
228 | #define GLOBAL_VTU_VID_VALID BIT(12) | |
cca8b133 AL |
229 | #define GLOBAL_VTU_DATA_0_3 0x07 |
230 | #define GLOBAL_VTU_DATA_4_7 0x08 | |
231 | #define GLOBAL_VTU_DATA_8_11 0x09 | |
b8fee957 VD |
232 | #define GLOBAL_VTU_STU_DATA_MASK 0x03 |
233 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00 | |
234 | #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01 | |
235 | #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02 | |
236 | #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03 | |
0d3b33e6 VD |
237 | #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00 |
238 | #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01 | |
239 | #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02 | |
240 | #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03 | |
cca8b133 | 241 | #define GLOBAL_ATU_CONTROL 0x0a |
54d792f2 | 242 | #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3) |
cca8b133 AL |
243 | #define GLOBAL_ATU_OP 0x0b |
244 | #define GLOBAL_ATU_OP_BUSY BIT(15) | |
245 | #define GLOBAL_ATU_OP_NOP (0 << 12) | |
7fb5e755 VD |
246 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY) |
247 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY) | |
cca8b133 AL |
248 | #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY) |
249 | #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY) | |
7fb5e755 VD |
250 | #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY) |
251 | #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY) | |
cca8b133 AL |
252 | #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY) |
253 | #define GLOBAL_ATU_DATA 0x0c | |
8a0a265d | 254 | #define GLOBAL_ATU_DATA_TRUNK BIT(15) |
fd231c82 VD |
255 | #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0 |
256 | #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4 | |
8a0a265d AL |
257 | #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 |
258 | #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4 | |
cca8b133 AL |
259 | #define GLOBAL_ATU_DATA_STATE_MASK 0x0f |
260 | #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00 | |
261 | #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d | |
262 | #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e | |
263 | #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f | |
264 | #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05 | |
265 | #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07 | |
266 | #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e | |
267 | #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f | |
268 | #define GLOBAL_ATU_MAC_01 0x0d | |
269 | #define GLOBAL_ATU_MAC_23 0x0e | |
270 | #define GLOBAL_ATU_MAC_45 0x0f | |
271 | #define GLOBAL_IP_PRI_0 0x10 | |
272 | #define GLOBAL_IP_PRI_1 0x11 | |
273 | #define GLOBAL_IP_PRI_2 0x12 | |
274 | #define GLOBAL_IP_PRI_3 0x13 | |
275 | #define GLOBAL_IP_PRI_4 0x14 | |
276 | #define GLOBAL_IP_PRI_5 0x15 | |
277 | #define GLOBAL_IP_PRI_6 0x16 | |
278 | #define GLOBAL_IP_PRI_7 0x17 | |
279 | #define GLOBAL_IEEE_PRI 0x18 | |
280 | #define GLOBAL_CORE_TAG_TYPE 0x19 | |
281 | #define GLOBAL_MONITOR_CONTROL 0x1a | |
15966a2a AL |
282 | #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12 |
283 | #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8 | |
284 | #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4 | |
285 | #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0 | |
286 | #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0) | |
cca8b133 | 287 | #define GLOBAL_CONTROL_2 0x1c |
15966a2a AL |
288 | #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000 |
289 | #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000 | |
290 | ||
cca8b133 AL |
291 | #define GLOBAL_STATS_OP 0x1d |
292 | #define GLOBAL_STATS_OP_BUSY BIT(15) | |
293 | #define GLOBAL_STATS_OP_NOP (0 << 12) | |
294 | #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY) | |
295 | #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY) | |
296 | #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY) | |
297 | #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY) | |
298 | #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY) | |
299 | #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY) | |
300 | #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY) | |
f5e2ed02 | 301 | #define GLOBAL_STATS_OP_BANK_1 BIT(9) |
cca8b133 AL |
302 | #define GLOBAL_STATS_COUNTER_32 0x1e |
303 | #define GLOBAL_STATS_COUNTER_01 0x1f | |
defb05b9 | 304 | |
cca8b133 AL |
305 | #define REG_GLOBAL2 0x1c |
306 | #define GLOBAL2_INT_SOURCE 0x00 | |
307 | #define GLOBAL2_INT_MASK 0x01 | |
308 | #define GLOBAL2_MGMT_EN_2X 0x02 | |
309 | #define GLOBAL2_MGMT_EN_0X 0x03 | |
310 | #define GLOBAL2_FLOW_CONTROL 0x04 | |
311 | #define GLOBAL2_SWITCH_MGMT 0x05 | |
54d792f2 AL |
312 | #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15) |
313 | #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14) | |
314 | #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13) | |
315 | #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7) | |
316 | #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3) | |
cca8b133 | 317 | #define GLOBAL2_DEVICE_MAPPING 0x06 |
54d792f2 AL |
318 | #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15) |
319 | #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8 | |
d35bd876 | 320 | #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f |
cca8b133 | 321 | #define GLOBAL2_TRUNK_MASK 0x07 |
54d792f2 AL |
322 | #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15) |
323 | #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12 | |
cca8b133 | 324 | #define GLOBAL2_TRUNK_MAPPING 0x08 |
54d792f2 AL |
325 | #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15) |
326 | #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11 | |
cca8b133 AL |
327 | #define GLOBAL2_INGRESS_OP 0x09 |
328 | #define GLOBAL2_INGRESS_DATA 0x0a | |
329 | #define GLOBAL2_PVT_ADDR 0x0b | |
330 | #define GLOBAL2_PVT_DATA 0x0c | |
331 | #define GLOBAL2_SWITCH_MAC 0x0d | |
332 | #define GLOBAL2_SWITCH_MAC_BUSY BIT(15) | |
333 | #define GLOBAL2_ATU_STATS 0x0e | |
334 | #define GLOBAL2_PRIO_OVERRIDE 0x0f | |
15966a2a AL |
335 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7) |
336 | #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4 | |
337 | #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3) | |
338 | #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0 | |
cca8b133 | 339 | #define GLOBAL2_EEPROM_OP 0x14 |
966bce38 AL |
340 | #define GLOBAL2_EEPROM_OP_BUSY BIT(15) |
341 | #define GLOBAL2_EEPROM_OP_WRITE ((3 << 12) | GLOBAL2_EEPROM_OP_BUSY) | |
342 | #define GLOBAL2_EEPROM_OP_READ ((4 << 12) | GLOBAL2_EEPROM_OP_BUSY) | |
343 | #define GLOBAL2_EEPROM_OP_LOAD BIT(11) | |
344 | #define GLOBAL2_EEPROM_OP_WRITE_EN BIT(10) | |
345 | #define GLOBAL2_EEPROM_OP_ADDR_MASK 0xff | |
cca8b133 AL |
346 | #define GLOBAL2_EEPROM_DATA 0x15 |
347 | #define GLOBAL2_PTP_AVB_OP 0x16 | |
348 | #define GLOBAL2_PTP_AVB_DATA 0x17 | |
349 | #define GLOBAL2_SMI_OP 0x18 | |
350 | #define GLOBAL2_SMI_OP_BUSY BIT(15) | |
351 | #define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12) | |
352 | #define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \ | |
353 | GLOBAL2_SMI_OP_CLAUSE_22) | |
354 | #define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \ | |
355 | GLOBAL2_SMI_OP_CLAUSE_22) | |
356 | #define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY) | |
357 | #define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY) | |
358 | #define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY) | |
359 | #define GLOBAL2_SMI_DATA 0x19 | |
360 | #define GLOBAL2_SCRATCH_MISC 0x1a | |
56d95e22 AL |
361 | #define GLOBAL2_SCRATCH_BUSY BIT(15) |
362 | #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8 | |
363 | #define GLOBAL2_SCRATCH_VALUE_MASK 0xff | |
cca8b133 AL |
364 | #define GLOBAL2_WDOG_CONTROL 0x1b |
365 | #define GLOBAL2_QOS_WEIGHT 0x1c | |
366 | #define GLOBAL2_MISC 0x1d | |
defb05b9 | 367 | |
3285f9e8 VD |
368 | #define MV88E6XXX_N_FID 4096 |
369 | ||
b9b37713 VD |
370 | struct mv88e6xxx_switch_id { |
371 | u16 id; | |
372 | char *name; | |
373 | }; | |
374 | ||
fd231c82 VD |
375 | struct mv88e6xxx_atu_entry { |
376 | u16 fid; | |
377 | u8 state; | |
378 | bool trunk; | |
379 | u16 portv_trunkid; | |
380 | u8 mac[ETH_ALEN]; | |
381 | }; | |
382 | ||
b8fee957 VD |
383 | struct mv88e6xxx_vtu_stu_entry { |
384 | /* VTU only */ | |
385 | u16 vid; | |
386 | u16 fid; | |
387 | ||
388 | /* VTU and STU */ | |
389 | u8 sid; | |
390 | bool valid; | |
391 | u8 data[DSA_MAX_PORTS]; | |
392 | }; | |
393 | ||
d715fa64 | 394 | struct mv88e6xxx_priv_port { |
a6692754 | 395 | struct net_device *bridge_dev; |
d715fa64 VD |
396 | u8 state; |
397 | }; | |
398 | ||
91da11f8 | 399 | struct mv88e6xxx_priv_state { |
3675c8d7 | 400 | /* When using multi-chip addressing, this mutex protects |
91da11f8 LB |
401 | * access to the indirect access registers. (In single-chip |
402 | * mode, this mutex is effectively useless.) | |
403 | */ | |
404 | struct mutex smi_mutex; | |
405 | ||
2e5f0320 | 406 | #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU |
3675c8d7 | 407 | /* Handles automatic disabling and re-enabling of the PHY |
2e5f0320 LB |
408 | * polling unit. |
409 | */ | |
410 | struct mutex ppu_mutex; | |
411 | int ppu_disabled; | |
412 | struct work_struct ppu_work; | |
413 | struct timer_list ppu_timer; | |
414 | #endif | |
415 | ||
3675c8d7 | 416 | /* This mutex serialises access to the statistics unit. |
91da11f8 LB |
417 | * Hold this mutex over snapshot + dump sequences. |
418 | */ | |
419 | struct mutex stats_mutex; | |
ec80bfcb | 420 | |
3ad50cca GR |
421 | /* This mutex serializes phy access for chips with |
422 | * indirect phy addressing. It is unused for chips | |
423 | * with direct phy access. | |
424 | */ | |
425 | struct mutex phy_mutex; | |
426 | ||
33b43df4 GR |
427 | /* This mutex serializes eeprom access for chips with |
428 | * eeprom support. | |
429 | */ | |
430 | struct mutex eeprom_mutex; | |
431 | ||
ec80bfcb | 432 | int id; /* switch product id */ |
d198893e | 433 | int num_ports; /* number of switch ports */ |
facd95b2 | 434 | |
d715fa64 VD |
435 | struct mv88e6xxx_priv_port ports[DSA_MAX_PORTS]; |
436 | ||
2d9deae4 | 437 | DECLARE_BITMAP(port_state_update_mask, DSA_MAX_PORTS); |
facd95b2 GR |
438 | |
439 | struct work_struct bridge_work; | |
91da11f8 LB |
440 | }; |
441 | ||
f5e2ed02 AL |
442 | enum stat_type { |
443 | BANK0, | |
444 | BANK1, | |
445 | PORT, | |
446 | }; | |
447 | ||
91da11f8 LB |
448 | struct mv88e6xxx_hw_stat { |
449 | char string[ETH_GSTRING_LEN]; | |
450 | int sizeof_stat; | |
451 | int reg; | |
f5e2ed02 | 452 | enum stat_type type; |
91da11f8 LB |
453 | }; |
454 | ||
143a8307 | 455 | int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active); |
b9b37713 VD |
456 | char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr, |
457 | const struct mv88e6xxx_switch_id *table, | |
458 | unsigned int num); | |
dbde9e66 | 459 | int mv88e6xxx_setup_ports(struct dsa_switch *ds); |
acdaffcc | 460 | int mv88e6xxx_setup_common(struct dsa_switch *ds); |
54d792f2 | 461 | int mv88e6xxx_setup_global(struct dsa_switch *ds); |
91da11f8 | 462 | int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg); |
91da11f8 | 463 | int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val); |
2e5f0320 | 464 | int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr); |
91da11f8 | 465 | int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr); |
fd3a0ee4 AL |
466 | int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum); |
467 | int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val); | |
468 | int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum); | |
469 | int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum, | |
470 | u16 val); | |
2e5f0320 LB |
471 | void mv88e6xxx_ppu_state_init(struct dsa_switch *ds); |
472 | int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum); | |
473 | int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr, | |
474 | int regnum, u16 val); | |
e413e7e1 AL |
475 | void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data); |
476 | void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, | |
477 | uint64_t *data); | |
478 | int mv88e6xxx_get_sset_count(struct dsa_switch *ds); | |
479 | int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds); | |
dea87024 AL |
480 | void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, |
481 | struct phy_device *phydev); | |
a1ab91f3 GR |
482 | int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port); |
483 | void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, | |
484 | struct ethtool_regs *regs, void *_p); | |
c22995c5 GR |
485 | int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp); |
486 | int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp); | |
487 | int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp); | |
488 | int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm); | |
f3044683 AL |
489 | int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds); |
490 | int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds); | |
491 | int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum); | |
492 | int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum, | |
493 | u16 val); | |
11b3b45d GR |
494 | int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e); |
495 | int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, | |
496 | struct phy_device *phydev, struct ethtool_eee *e); | |
a6692754 VD |
497 | int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, |
498 | struct net_device *bridge); | |
16bfa702 | 499 | void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port); |
facd95b2 | 500 | int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state); |
214cdb99 VD |
501 | int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, |
502 | bool vlan_filtering); | |
76e398a6 VD |
503 | int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, |
504 | const struct switchdev_obj_port_vlan *vlan, | |
505 | struct switchdev_trans *trans); | |
506 | int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, | |
507 | const struct switchdev_obj_port_vlan *vlan, | |
508 | struct switchdev_trans *trans); | |
509 | int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, | |
510 | const struct switchdev_obj_port_vlan *vlan); | |
ceff5eff VD |
511 | int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, |
512 | struct switchdev_obj_port_vlan *vlan, | |
513 | int (*cb)(struct switchdev_obj *obj)); | |
146a3206 VD |
514 | int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, |
515 | const struct switchdev_obj_port_fdb *fdb, | |
516 | struct switchdev_trans *trans); | |
cdf09697 | 517 | int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, |
1f36faf2 VD |
518 | const struct switchdev_obj_port_fdb *fdb, |
519 | struct switchdev_trans *trans); | |
cdf09697 | 520 | int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, |
8057b3e7 | 521 | const struct switchdev_obj_port_fdb *fdb); |
f33475bd VD |
522 | int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, |
523 | struct switchdev_obj_port_fdb *fdb, | |
524 | int (*cb)(struct switchdev_obj *obj)); | |
49143585 AL |
525 | int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg); |
526 | int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page, | |
527 | int reg, int val); | |
c22995c5 | 528 | |
98e67308 | 529 | extern struct dsa_switch_driver mv88e6131_switch_driver; |
ca3dfa51 | 530 | extern struct dsa_switch_driver mv88e6123_switch_driver; |
3ad50cca | 531 | extern struct dsa_switch_driver mv88e6352_switch_driver; |
42f27253 | 532 | extern struct dsa_switch_driver mv88e6171_switch_driver; |
98e67308 | 533 | |
91da11f8 LB |
534 | #define REG_READ(addr, reg) \ |
535 | ({ \ | |
536 | int __ret; \ | |
537 | \ | |
538 | __ret = mv88e6xxx_reg_read(ds, addr, reg); \ | |
539 | if (__ret < 0) \ | |
540 | return __ret; \ | |
541 | __ret; \ | |
542 | }) | |
543 | ||
544 | #define REG_WRITE(addr, reg, val) \ | |
545 | ({ \ | |
546 | int __ret; \ | |
547 | \ | |
548 | __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \ | |
549 | if (__ret < 0) \ | |
550 | return __ret; \ | |
551 | }) | |
552 | ||
553 | ||
554 | ||
555 | #endif |