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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux...
[deliverable/linux.git] / drivers / net / e100.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
05479938
JB		 5
6 This program is free software; you can redistribute it and/or modify it
0abb6eb1
AK		 7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
05479938 9
0abb6eb1 10 This program is distributed in the hope it will be useful, but WITHOUT
05479938
JB		 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
05479938 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
05479938 18
0abb6eb1
AK		 19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
05479938 21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
0abb6eb1 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
0a0863af 97 * IV. Receive
1da177e4
LT		 98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
7734f6e6
DA		 109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
1da177e4
LT		 116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
0a0863af 123 * scenario where all Rx resources have been indicated and none re-
1da177e4
LT		 124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
ac7c6669
OM		 142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
72001762
AM		 146 * 2009/06/01 - Andreas Mohr <andi at lisas dot de>
147 * - add clean lowlevel I/O emulation for cards with MII-lacking PHYs
1da177e4
LT		 148 */
149
fa05e1ad
JP		 150#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
151
1da177e4
LT		 152#include <linux/module.h>
153#include <linux/moduleparam.h>
154#include <linux/kernel.h>
155#include <linux/types.h>
d43c36dc 156#include <linux/sched.h>
1da177e4
LT		 157#include <linux/slab.h>
158#include <linux/delay.h>
159#include <linux/init.h>
160#include <linux/pci.h>
1e7f0bd8 161#include <linux/dma-mapping.h>
98468efd 162#include <linux/dmapool.h>
1da177e4
LT		 163#include <linux/netdevice.h>
164#include <linux/etherdevice.h>
165#include <linux/mii.h>
166#include <linux/if_vlan.h>
167#include <linux/skbuff.h>
168#include <linux/ethtool.h>
169#include <linux/string.h>
9ac32e1b 170#include <linux/firmware.h>
401da6ae 171#include <linux/rtnetlink.h>
1da177e4
LT		 172#include <asm/unaligned.h>
173
174
175#define DRV_NAME "e100"
4e1dc97d 176#define DRV_EXT "-NAPI"
b55de80e 177#define DRV_VERSION "3.5.24-k2"DRV_EXT
1da177e4 178#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
4e1dc97d 179#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
1da177e4
LT		 180
181#define E100_WATCHDOG_PERIOD (2 * HZ)
182#define E100_NAPI_WEIGHT 16
183
9ac32e1b
JSR		 184#define FIRMWARE_D101M "e100/d101m_ucode.bin"
185#define FIRMWARE_D101S "e100/d101s_ucode.bin"
186#define FIRMWARE_D102E "e100/d102e_ucode.bin"
187
1da177e4
LT		 188MODULE_DESCRIPTION(DRV_DESCRIPTION);
189MODULE_AUTHOR(DRV_COPYRIGHT);
190MODULE_LICENSE("GPL");
191MODULE_VERSION(DRV_VERSION);
9ac32e1b
JSR		 192MODULE_FIRMWARE(FIRMWARE_D101M);
193MODULE_FIRMWARE(FIRMWARE_D101S);
194MODULE_FIRMWARE(FIRMWARE_D102E);
1da177e4
LT		 195
196static int debug = 3;
8fb6f732 197static int eeprom_bad_csum_allow = 0;
27345bb6 198static int use_io = 0;
1da177e4 199module_param(debug, int, 0);
8fb6f732 200module_param(eeprom_bad_csum_allow, int, 0);
27345bb6 201module_param(use_io, int, 0);
1da177e4 202MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
8fb6f732 203MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
27345bb6 204MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
1da177e4
LT		 205
206#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
207 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
208 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
a3aa1884 209static DEFINE_PCI_DEVICE_TABLE(e100_id_table) = {
1da177e4
LT		 210 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
211 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
212 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
213 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
214 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
216 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
217 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
218 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
219 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
222 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
223 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
224 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
225 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
230 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
231 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
232 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
233 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
234 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
239 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
042e2fb7
MC		 240 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
241 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
242 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
b55de80e 245 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
1da177e4
LT		 246 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
247 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
248 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
249 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
250 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
042e2fb7 251 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
1da177e4
LT		 252 { 0, }
253};
254MODULE_DEVICE_TABLE(pci, e100_id_table);
255
256enum mac {
257 mac_82557_D100_A = 0,
258 mac_82557_D100_B = 1,
259 mac_82557_D100_C = 2,
260 mac_82558_D101_A4 = 4,
261 mac_82558_D101_B0 = 5,
262 mac_82559_D101M = 8,
263 mac_82559_D101S = 9,
264 mac_82550_D102 = 12,
265 mac_82550_D102_C = 13,
266 mac_82551_E = 14,
267 mac_82551_F = 15,
268 mac_82551_10 = 16,
269 mac_unknown = 0xFF,
270};
271
272enum phy {
273 phy_100a = 0x000003E0,
274 phy_100c = 0x035002A8,
275 phy_82555_tx = 0x015002A8,
276 phy_nsc_tx = 0x5C002000,
277 phy_82562_et = 0x033002A8,
278 phy_82562_em = 0x032002A8,
279 phy_82562_ek = 0x031002A8,
280 phy_82562_eh = 0x017002A8,
b55de80e 281 phy_82552_v = 0xd061004d,
1da177e4
LT		 282 phy_unknown = 0xFFFFFFFF,
283};
284
285/* CSR (Control/Status Registers) */
286struct csr {
287 struct {
288 u8 status;
289 u8 stat_ack;
290 u8 cmd_lo;
291 u8 cmd_hi;
292 u32 gen_ptr;
293 } scb;
294 u32 port;
295 u16 flash_ctrl;
296 u8 eeprom_ctrl_lo;
297 u8 eeprom_ctrl_hi;
298 u32 mdi_ctrl;
299 u32 rx_dma_count;
300};
301
302enum scb_status {
7734f6e6 303 rus_no_res = 0x08,
1da177e4
LT		 304 rus_ready = 0x10,
305 rus_mask = 0x3C,
306};
307
ca93ca42
JG		 308enum ru_state {
309 RU_SUSPENDED = 0,
310 RU_RUNNING = 1,
311 RU_UNINITIALIZED = -1,
312};
313
1da177e4
LT		 314enum scb_stat_ack {
315 stat_ack_not_ours = 0x00,
316 stat_ack_sw_gen = 0x04,
317 stat_ack_rnr = 0x10,
318 stat_ack_cu_idle = 0x20,
319 stat_ack_frame_rx = 0x40,
320 stat_ack_cu_cmd_done = 0x80,
321 stat_ack_not_present = 0xFF,
322 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
323 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
324};
325
326enum scb_cmd_hi {
327 irq_mask_none = 0x00,
328 irq_mask_all = 0x01,
329 irq_sw_gen = 0x02,
330};
331
332enum scb_cmd_lo {
333 cuc_nop = 0x00,
334 ruc_start = 0x01,
335 ruc_load_base = 0x06,
336 cuc_start = 0x10,
337 cuc_resume = 0x20,
338 cuc_dump_addr = 0x40,
339 cuc_dump_stats = 0x50,
340 cuc_load_base = 0x60,
341 cuc_dump_reset = 0x70,
342};
343
344enum cuc_dump {
345 cuc_dump_complete = 0x0000A005,
346 cuc_dump_reset_complete = 0x0000A007,
347};
05479938 348
1da177e4
LT		 349enum port {
350 software_reset = 0x0000,
351 selftest = 0x0001,
352 selective_reset = 0x0002,
353};
354
355enum eeprom_ctrl_lo {
356 eesk = 0x01,
357 eecs = 0x02,
358 eedi = 0x04,
359 eedo = 0x08,
360};
361
362enum mdi_ctrl {
363 mdi_write = 0x04000000,
364 mdi_read = 0x08000000,
365 mdi_ready = 0x10000000,
366};
367
368enum eeprom_op {
369 op_write = 0x05,
370 op_read = 0x06,
371 op_ewds = 0x10,
372 op_ewen = 0x13,
373};
374
375enum eeprom_offsets {
376 eeprom_cnfg_mdix = 0x03,
72001762 377 eeprom_phy_iface = 0x06,
1da177e4
LT		 378 eeprom_id = 0x0A,
379 eeprom_config_asf = 0x0D,
380 eeprom_smbus_addr = 0x90,
381};
382
383enum eeprom_cnfg_mdix {
384 eeprom_mdix_enabled = 0x0080,
385};
386
72001762
AM		 387enum eeprom_phy_iface {
388 NoSuchPhy = 0,
389 I82553AB,
390 I82553C,
391 I82503,
392 DP83840,
393 S80C240,
394 S80C24,
395 I82555,
396 DP83840A = 10,
397};
398
1da177e4
LT		 399enum eeprom_id {
400 eeprom_id_wol = 0x0020,
401};
402
403enum eeprom_config_asf {
404 eeprom_asf = 0x8000,
405 eeprom_gcl = 0x4000,
406};
407
408enum cb_status {
409 cb_complete = 0x8000,
410 cb_ok = 0x2000,
411};
412
413enum cb_command {
414 cb_nop = 0x0000,
415 cb_iaaddr = 0x0001,
416 cb_config = 0x0002,
417 cb_multi = 0x0003,
418 cb_tx = 0x0004,
419 cb_ucode = 0x0005,
420 cb_dump = 0x0006,
421 cb_tx_sf = 0x0008,
422 cb_cid = 0x1f00,
423 cb_i = 0x2000,
424 cb_s = 0x4000,
425 cb_el = 0x8000,
426};
427
428struct rfd {
aaf918ba
AV		 429 __le16 status;
430 __le16 command;
431 __le32 link;
432 __le32 rbd;
433 __le16 actual_size;
434 __le16 size;
1da177e4
LT		 435};
436
437struct rx {
438 struct rx *next, *prev;
439 struct sk_buff *skb;
440 dma_addr_t dma_addr;
441};
442
443#if defined(__BIG_ENDIAN_BITFIELD)
444#define X(a,b) b,a
445#else
446#define X(a,b) a,b
447#endif
448struct config {
449/*0*/ u8 X(byte_count:6, pad0:2);
450/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
451/*2*/ u8 adaptive_ifs;
452/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
453 term_write_cache_line:1), pad3:4);
454/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
455/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
456/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
457 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
458 rx_discard_overruns:1), rx_save_bad_frames:1);
459/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
460 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
461 tx_dynamic_tbd:1);
462/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
463/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
464 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
465/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
466 loopback:2);
467/*11*/ u8 X(linear_priority:3, pad11:5);
468/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
469/*13*/ u8 ip_addr_lo;
470/*14*/ u8 ip_addr_hi;
471/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
472 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
473 pad15_2:1), crs_or_cdt:1);
474/*16*/ u8 fc_delay_lo;
475/*17*/ u8 fc_delay_hi;
476/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
477 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
478/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
479 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
480 full_duplex_force:1), full_duplex_pin:1);
481/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
482/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
483/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
484 u8 pad_d102[9];
485};
486
487#define E100_MAX_MULTICAST_ADDRS 64
488struct multi {
aaf918ba 489 __le16 count;
1da177e4
LT		 490 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
491};
492
493/* Important: keep total struct u32-aligned */
494#define UCODE_SIZE 134
495struct cb {
aaf918ba
AV		 496 __le16 status;
497 __le16 command;
498 __le32 link;
1da177e4
LT		 499 union {
500 u8 iaaddr[ETH_ALEN];
aaf918ba 501 __le32 ucode[UCODE_SIZE];
1da177e4
LT		 502 struct config config;
503 struct multi multi;
504 struct {
505 u32 tbd_array;
506 u16 tcb_byte_count;
507 u8 threshold;
508 u8 tbd_count;
509 struct {
aaf918ba
AV		 510 __le32 buf_addr;
511 __le16 size;
1da177e4
LT		 512 u16 eol;
513 } tbd;
514 } tcb;
aaf918ba 515 __le32 dump_buffer_addr;
1da177e4
LT		 516 } u;
517 struct cb *next, *prev;
518 dma_addr_t dma_addr;
519 struct sk_buff *skb;
520};
521
522enum loopback {
523 lb_none = 0, lb_mac = 1, lb_phy = 3,
524};
525
526struct stats {
aaf918ba 527 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
1da177e4
LT		 528 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
529 tx_multiple_collisions, tx_total_collisions;
aaf918ba 530 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
1da177e4
LT		 531 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
532 rx_short_frame_errors;
aaf918ba
AV		 533 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
534 __le16 xmt_tco_frames, rcv_tco_frames;
535 __le32 complete;
1da177e4
LT		 536};
537
538struct mem {
539 struct {
540 u32 signature;
541 u32 result;
542 } selftest;
543 struct stats stats;
544 u8 dump_buf[596];
545};
546
547struct param_range {
548 u32 min;
549 u32 max;
550 u32 count;
551};
552
553struct params {
554 struct param_range rfds;
555 struct param_range cbs;
556};
557
558struct nic {
559 /* Begin: frequently used values: keep adjacent for cache effect */
560 u32 msg_enable ____cacheline_aligned;
561 struct net_device *netdev;
562 struct pci_dev *pdev;
72001762 563 u16 (*mdio_ctrl)(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data);
1da177e4
LT		 564
565 struct rx *rxs ____cacheline_aligned;
566 struct rx *rx_to_use;
567 struct rx *rx_to_clean;
568 struct rfd blank_rfd;
ca93ca42 569 enum ru_state ru_running;
1da177e4
LT		 570
571 spinlock_t cb_lock ____cacheline_aligned;
572 spinlock_t cmd_lock;
573 struct csr __iomem *csr;
574 enum scb_cmd_lo cuc_cmd;
575 unsigned int cbs_avail;
bea3348e 576 struct napi_struct napi;
1da177e4
LT		 577 struct cb *cbs;
578 struct cb *cb_to_use;
579 struct cb *cb_to_send;
580 struct cb *cb_to_clean;
aaf918ba 581 __le16 tx_command;
1da177e4
LT		 582 /* End: frequently used values: keep adjacent for cache effect */
583
584 enum {
585 ich = (1 << 0),
586 promiscuous = (1 << 1),
587 multicast_all = (1 << 2),
588 wol_magic = (1 << 3),
589 ich_10h_workaround = (1 << 4),
590 } flags ____cacheline_aligned;
591
592 enum mac mac;
593 enum phy phy;
594 struct params params;
1da177e4 595 struct timer_list watchdog;
1da177e4 596 struct mii_if_info mii;
2acdb1e0 597 struct work_struct tx_timeout_task;
1da177e4
LT		 598 enum loopback loopback;
599
600 struct mem *mem;
601 dma_addr_t dma_addr;
602
98468efd 603 struct pci_pool *cbs_pool;
1da177e4
LT		 604 dma_addr_t cbs_dma_addr;
605 u8 adaptive_ifs;
606 u8 tx_threshold;
607 u32 tx_frames;
608 u32 tx_collisions;
609 u32 tx_deferred;
610 u32 tx_single_collisions;
611 u32 tx_multiple_collisions;
612 u32 tx_fc_pause;
613 u32 tx_tco_frames;
614
615 u32 rx_fc_pause;
616 u32 rx_fc_unsupported;
617 u32 rx_tco_frames;
618 u32 rx_over_length_errors;
619
1da177e4 620 u16 eeprom_wc;
aaf918ba 621 __le16 eeprom[256];
ac7c6669 622 spinlock_t mdio_lock;
7e15b0c9 623 const struct firmware *fw;
1da177e4
LT		 624};
625
626static inline void e100_write_flush(struct nic *nic)
627{
628 /* Flush previous PCI writes through intermediate bridges
629 * by doing a benign read */
27345bb6 630 (void)ioread8(&nic->csr->scb.status);
1da177e4
LT		 631}
632
858119e1 633static void e100_enable_irq(struct nic *nic)
1da177e4
LT		 634{
635 unsigned long flags;
636
637 spin_lock_irqsave(&nic->cmd_lock, flags);
27345bb6 638 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
1da177e4 639 e100_write_flush(nic);
ad8c48ad 640 spin_unlock_irqrestore(&nic->cmd_lock, flags);
1da177e4
LT		 641}
642
858119e1 643static void e100_disable_irq(struct nic *nic)
1da177e4
LT		 644{
645 unsigned long flags;
646
647 spin_lock_irqsave(&nic->cmd_lock, flags);
27345bb6 648 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
1da177e4 649 e100_write_flush(nic);
ad8c48ad 650 spin_unlock_irqrestore(&nic->cmd_lock, flags);
1da177e4
LT		 651}
652
653static void e100_hw_reset(struct nic *nic)
654{
655 /* Put CU and RU into idle with a selective reset to get
656 * device off of PCI bus */
27345bb6 657 iowrite32(selective_reset, &nic->csr->port);
1da177e4
LT		 658 e100_write_flush(nic); udelay(20);
659
660 /* Now fully reset device */
27345bb6 661 iowrite32(software_reset, &nic->csr->port);
1da177e4
LT		 662 e100_write_flush(nic); udelay(20);
663
664 /* Mask off our interrupt line - it's unmasked after reset */
665 e100_disable_irq(nic);
666}
667
668static int e100_self_test(struct nic *nic)
669{
670 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
671
672 /* Passing the self-test is a pretty good indication
673 * that the device can DMA to/from host memory */
674
675 nic->mem->selftest.signature = 0;
676 nic->mem->selftest.result = 0xFFFFFFFF;
677
27345bb6 678 iowrite32(selftest | dma_addr, &nic->csr->port);
1da177e4
LT		 679 e100_write_flush(nic);
680 /* Wait 10 msec for self-test to complete */
681 msleep(10);
682
683 /* Interrupts are enabled after self-test */
684 e100_disable_irq(nic);
685
686 /* Check results of self-test */
f26251eb 687 if (nic->mem->selftest.result != 0) {
fa05e1ad
JP		 688 netif_err(nic, hw, nic->netdev,
689 "Self-test failed: result=0x%08X\n",
690 nic->mem->selftest.result);
1da177e4
LT		 691 return -ETIMEDOUT;
692 }
f26251eb 693 if (nic->mem->selftest.signature == 0) {
fa05e1ad 694 netif_err(nic, hw, nic->netdev, "Self-test failed: timed out\n");
1da177e4
LT		 695 return -ETIMEDOUT;
696 }
697
698 return 0;
699}
700
aaf918ba 701static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
1da177e4
LT		 702{
703 u32 cmd_addr_data[3];
704 u8 ctrl;
705 int i, j;
706
707 /* Three cmds: write/erase enable, write data, write/erase disable */
708 cmd_addr_data[0] = op_ewen << (addr_len - 2);
709 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
aaf918ba 710 le16_to_cpu(data);
1da177e4
LT		 711 cmd_addr_data[2] = op_ewds << (addr_len - 2);
712
713 /* Bit-bang cmds to write word to eeprom */
f26251eb 714 for (j = 0; j < 3; j++) {
1da177e4
LT		 715
716 /* Chip select */
27345bb6 717 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 718 e100_write_flush(nic); udelay(4);
719
f26251eb 720 for (i = 31; i >= 0; i--) {
1da177e4
LT		 721 ctrl = (cmd_addr_data[j] & (1 << i)) ?
722 eecs | eedi : eecs;
27345bb6 723 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 724 e100_write_flush(nic); udelay(4);
725
27345bb6 726 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 727 e100_write_flush(nic); udelay(4);
728 }
729 /* Wait 10 msec for cmd to complete */
730 msleep(10);
731
732 /* Chip deselect */
27345bb6 733 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 734 e100_write_flush(nic); udelay(4);
735 }
736};
737
738/* General technique stolen from the eepro100 driver - very clever */
aaf918ba 739static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
1da177e4
LT		 740{
741 u32 cmd_addr_data;
742 u16 data = 0;
743 u8 ctrl;
744 int i;
745
746 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
747
748 /* Chip select */
27345bb6 749 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 750 e100_write_flush(nic); udelay(4);
751
752 /* Bit-bang to read word from eeprom */
f26251eb 753 for (i = 31; i >= 0; i--) {
1da177e4 754 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
27345bb6 755 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
1da177e4 756 e100_write_flush(nic); udelay(4);
05479938 757
27345bb6 758 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
1da177e4 759 e100_write_flush(nic); udelay(4);
05479938 760
1da177e4
LT		 761 /* Eeprom drives a dummy zero to EEDO after receiving
762 * complete address. Use this to adjust addr_len. */
27345bb6 763 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
f26251eb 764 if (!(ctrl & eedo) && i > 16) {
1da177e4
LT		 765 *addr_len -= (i - 16);
766 i = 17;
767 }
05479938 768
1da177e4
LT		 769 data = (data << 1) | (ctrl & eedo ? 1 : 0);
770 }
771
772 /* Chip deselect */
27345bb6 773 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
1da177e4
LT		 774 e100_write_flush(nic); udelay(4);
775
aaf918ba 776 return cpu_to_le16(data);
1da177e4
LT		 777};
778
779/* Load entire EEPROM image into driver cache and validate checksum */
780static int e100_eeprom_load(struct nic *nic)
781{
782 u16 addr, addr_len = 8, checksum = 0;
783
784 /* Try reading with an 8-bit addr len to discover actual addr len */
785 e100_eeprom_read(nic, &addr_len, 0);
786 nic->eeprom_wc = 1 << addr_len;
787
f26251eb 788 for (addr = 0; addr < nic->eeprom_wc; addr++) {
1da177e4 789 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
f26251eb 790 if (addr < nic->eeprom_wc - 1)
aaf918ba 791 checksum += le16_to_cpu(nic->eeprom[addr]);
1da177e4
LT		 792 }
793
794 /* The checksum, stored in the last word, is calculated such that
795 * the sum of words should be 0xBABA */
aaf918ba 796 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
fa05e1ad 797 netif_err(nic, probe, nic->netdev, "EEPROM corrupted\n");
8fb6f732
DM		 798 if (!eeprom_bad_csum_allow)
799 return -EAGAIN;
1da177e4
LT		 800 }
801
802 return 0;
803}
804
805/* Save (portion of) driver EEPROM cache to device and update checksum */
806static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
807{
808 u16 addr, addr_len = 8, checksum = 0;
809
810 /* Try reading with an 8-bit addr len to discover actual addr len */
811 e100_eeprom_read(nic, &addr_len, 0);
812 nic->eeprom_wc = 1 << addr_len;
813
f26251eb 814 if (start + count >= nic->eeprom_wc)
1da177e4
LT		 815 return -EINVAL;
816
f26251eb 817 for (addr = start; addr < start + count; addr++)
1da177e4
LT		 818 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
819
820 /* The checksum, stored in the last word, is calculated such that
821 * the sum of words should be 0xBABA */
f26251eb 822 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
aaf918ba
AV		 823 checksum += le16_to_cpu(nic->eeprom[addr]);
824 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
1da177e4
LT		 825 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
826 nic->eeprom[nic->eeprom_wc - 1]);
827
828 return 0;
829}
830
962082b6 831#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
e6280f26 832#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
858119e1 833static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
1da177e4
LT		 834{
835 unsigned long flags;
836 unsigned int i;
837 int err = 0;
838
839 spin_lock_irqsave(&nic->cmd_lock, flags);
840
841 /* Previous command is accepted when SCB clears */
f26251eb
BA		 842 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
843 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
1da177e4
LT		 844 break;
845 cpu_relax();
f26251eb 846 if (unlikely(i > E100_WAIT_SCB_FAST))
1da177e4
LT		 847 udelay(5);
848 }
f26251eb 849 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
1da177e4
LT		 850 err = -EAGAIN;
851 goto err_unlock;
852 }
853
f26251eb 854 if (unlikely(cmd != cuc_resume))
27345bb6
JB		 855 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
856 iowrite8(cmd, &nic->csr->scb.cmd_lo);
1da177e4
LT		 857
858err_unlock:
859 spin_unlock_irqrestore(&nic->cmd_lock, flags);
860
861 return err;
862}
863
858119e1 864static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
1da177e4
LT		 865 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
866{
867 struct cb *cb;
868 unsigned long flags;
869 int err = 0;
870
871 spin_lock_irqsave(&nic->cb_lock, flags);
872
f26251eb 873 if (unlikely(!nic->cbs_avail)) {
1da177e4
LT		 874 err = -ENOMEM;
875 goto err_unlock;
876 }
877
878 cb = nic->cb_to_use;
879 nic->cb_to_use = cb->next;
880 nic->cbs_avail--;
881 cb->skb = skb;
882
f26251eb 883 if (unlikely(!nic->cbs_avail))
1da177e4
LT		 884 err = -ENOSPC;
885
886 cb_prepare(nic, cb, skb);
887
888 /* Order is important otherwise we'll be in a race with h/w:
889 * set S-bit in current first, then clear S-bit in previous. */
890 cb->command |= cpu_to_le16(cb_s);
891 wmb();
892 cb->prev->command &= cpu_to_le16(~cb_s);
893
f26251eb
BA		 894 while (nic->cb_to_send != nic->cb_to_use) {
895 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
1da177e4
LT		 896 nic->cb_to_send->dma_addr))) {
897 /* Ok, here's where things get sticky. It's
898 * possible that we can't schedule the command
899 * because the controller is too busy, so
900 * let's just queue the command and try again
901 * when another command is scheduled. */
f26251eb 902 if (err == -ENOSPC) {
962082b6
MC		 903 //request a reset
904 schedule_work(&nic->tx_timeout_task);
905 }
1da177e4
LT		 906 break;
907 } else {
908 nic->cuc_cmd = cuc_resume;
909 nic->cb_to_send = nic->cb_to_send->next;
910 }
911 }
912
913err_unlock:
914 spin_unlock_irqrestore(&nic->cb_lock, flags);
915
916 return err;
917}
918
72001762
AM		 919static int mdio_read(struct net_device *netdev, int addr, int reg)
920{
921 struct nic *nic = netdev_priv(netdev);
922 return nic->mdio_ctrl(nic, addr, mdi_read, reg, 0);
923}
924
925static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
926{
927 struct nic *nic = netdev_priv(netdev);
928
929 nic->mdio_ctrl(nic, addr, mdi_write, reg, data);
930}
931
932/* the standard mdio_ctrl() function for usual MII-compliant hardware */
933static u16 mdio_ctrl_hw(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
1da177e4
LT		 934{
935 u32 data_out = 0;
936 unsigned int i;
ac7c6669 937 unsigned long flags;
1da177e4 938
ac7c6669
OM		 939
940 /*
941 * Stratus87247: we shouldn't be writing the MDI control
942 * register until the Ready bit shows True. Also, since
943 * manipulation of the MDI control registers is a multi-step
944 * procedure it should be done under lock.
945 */
946 spin_lock_irqsave(&nic->mdio_lock, flags);
947 for (i = 100; i; --i) {
27345bb6 948 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
ac7c6669
OM		 949 break;
950 udelay(20);
951 }
952 if (unlikely(!i)) {
fa05e1ad 953 netdev_err(nic->netdev, "e100.mdio_ctrl won't go Ready\n");
ac7c6669
OM		 954 spin_unlock_irqrestore(&nic->mdio_lock, flags);
955 return 0; /* No way to indicate timeout error */
956 }
27345bb6 957 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
1da177e4 958
ac7c6669 959 for (i = 0; i < 100; i++) {
1da177e4 960 udelay(20);
27345bb6 961 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
1da177e4
LT		 962 break;
963 }
ac7c6669 964 spin_unlock_irqrestore(&nic->mdio_lock, flags);
fa05e1ad
JP		 965 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
966 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
967 dir == mdi_read ? "READ" : "WRITE",
968 addr, reg, data, data_out);
1da177e4
LT		 969 return (u16)data_out;
970}
971
72001762
AM		 972/* slightly tweaked mdio_ctrl() function for phy_82552_v specifics */
973static u16 mdio_ctrl_phy_82552_v(struct nic *nic,
974 u32 addr,
975 u32 dir,
976 u32 reg,
977 u16 data)
978{
979 if ((reg == MII_BMCR) && (dir == mdi_write)) {
980 if (data & (BMCR_ANRESTART | BMCR_ANENABLE)) {
981 u16 advert = mdio_read(nic->netdev, nic->mii.phy_id,
982 MII_ADVERTISE);
983
984 /*
985 * Workaround Si issue where sometimes the part will not
986 * autoneg to 100Mbps even when advertised.
987 */
988 if (advert & ADVERTISE_100FULL)
989 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
990 else if (advert & ADVERTISE_100HALF)
991 data |= BMCR_SPEED100;
992 }
993 }
994 return mdio_ctrl_hw(nic, addr, dir, reg, data);
1da177e4
LT		 995}
996
72001762
AM		 997/* Fully software-emulated mdio_ctrl() function for cards without
998 * MII-compliant PHYs.
999 * For now, this is mainly geared towards 80c24 support; in case of further
1000 * requirements for other types (i82503, ...?) either extend this mechanism
1001 * or split it, whichever is cleaner.
1002 */
1003static u16 mdio_ctrl_phy_mii_emulated(struct nic *nic,
1004 u32 addr,
1005 u32 dir,
1006 u32 reg,
1007 u16 data)
1008{
1009 /* might need to allocate a netdev_priv'ed register array eventually
1010 * to be able to record state changes, but for now
1011 * some fully hardcoded register handling ought to be ok I guess. */
1012
1013 if (dir == mdi_read) {
1014 switch (reg) {
1015 case MII_BMCR:
1016 /* Auto-negotiation, right? */
1017 return BMCR_ANENABLE |
1018 BMCR_FULLDPLX;
1019 case MII_BMSR:
1020 return BMSR_LSTATUS /* for mii_link_ok() */ |
1021 BMSR_ANEGCAPABLE |
1022 BMSR_10FULL;
1023 case MII_ADVERTISE:
1024 /* 80c24 is a "combo card" PHY, right? */
1025 return ADVERTISE_10HALF |
1026 ADVERTISE_10FULL;
1027 default:
fa05e1ad
JP		 1028 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1029 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1030 dir == mdi_read ? "READ" : "WRITE",
1031 addr, reg, data);
72001762
AM		 1032 return 0xFFFF;
1033 }
1034 } else {
1035 switch (reg) {
1036 default:
fa05e1ad
JP		 1037 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1038 "%s:addr=%d, reg=%d, data=0x%04X: unimplemented emulation!\n",
1039 dir == mdi_read ? "READ" : "WRITE",
1040 addr, reg, data);
72001762
AM		 1041 return 0xFFFF;
1042 }
b55de80e 1043 }
72001762
AM		 1044}
1045static inline int e100_phy_supports_mii(struct nic *nic)
1046{
1047 /* for now, just check it by comparing whether we
1048 are using MII software emulation.
1049 */
1050 return (nic->mdio_ctrl != mdio_ctrl_phy_mii_emulated);
1da177e4
LT		 1051}
1052
1053static void e100_get_defaults(struct nic *nic)
1054{
2afecc04
JB		 1055 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
1056 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1da177e4 1057
1da177e4 1058 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
44c10138 1059 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
f26251eb 1060 if (nic->mac == mac_unknown)
1da177e4
LT		 1061 nic->mac = mac_82557_D100_A;
1062
1063 nic->params.rfds = rfds;
1064 nic->params.cbs = cbs;
1065
1066 /* Quadwords to DMA into FIFO before starting frame transmit */
1067 nic->tx_threshold = 0xE0;
1068
0a0863af 1069 /* no interrupt for every tx completion, delay = 256us if not 557 */
962082b6
MC		 1070 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
1071 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1da177e4
LT		 1072
1073 /* Template for a freshly allocated RFD */
7734f6e6 1074 nic->blank_rfd.command = 0;
1172899a 1075 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
1da177e4
LT		 1076 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1077
1078 /* MII setup */
1079 nic->mii.phy_id_mask = 0x1F;
1080 nic->mii.reg_num_mask = 0x1F;
1081 nic->mii.dev = nic->netdev;
1082 nic->mii.mdio_read = mdio_read;
1083 nic->mii.mdio_write = mdio_write;
1084}
1085
1086static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1087{
1088 struct config *config = &cb->u.config;
1089 u8 *c = (u8 *)config;
1090
1091 cb->command = cpu_to_le16(cb_config);
1092
1093 memset(config, 0, sizeof(struct config));
1094
1095 config->byte_count = 0x16; /* bytes in this struct */
1096 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1097 config->direct_rx_dma = 0x1; /* reserved */
1098 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1099 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1100 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1101 config->tx_underrun_retry = 0x3; /* # of underrun retries */
72001762
AM		 1102 if (e100_phy_supports_mii(nic))
1103 config->mii_mode = 1; /* 1=MII mode, 0=i82503 mode */
1da177e4
LT		 1104 config->pad10 = 0x6;
1105 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1106 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1107 config->ifs = 0x6; /* x16 = inter frame spacing */
1108 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1109 config->pad15_1 = 0x1;
1110 config->pad15_2 = 0x1;
1111 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1112 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1113 config->tx_padding = 0x1; /* 1=pad short frames */
1114 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1115 config->pad18 = 0x1;
1116 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1117 config->pad20_1 = 0x1F;
1118 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1119 config->pad21_1 = 0x5;
1120
1121 config->adaptive_ifs = nic->adaptive_ifs;
1122 config->loopback = nic->loopback;
1123
f26251eb 1124 if (nic->mii.force_media && nic->mii.full_duplex)
1da177e4
LT		 1125 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1126
f26251eb 1127 if (nic->flags & promiscuous || nic->loopback) {
1da177e4
LT		 1128 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1129 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1130 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1131 }
1132
f26251eb 1133 if (nic->flags & multicast_all)
1da177e4
LT		 1134 config->multicast_all = 0x1; /* 1=accept, 0=no */
1135
6bdacb1a 1136 /* disable WoL when up */
f26251eb 1137 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1da177e4
LT		 1138 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1139
f26251eb 1140 if (nic->mac >= mac_82558_D101_A4) {
1da177e4
LT		 1141 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1142 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1143 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1144 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
44e4925e 1145 if (nic->mac >= mac_82559_D101M) {
1da177e4 1146 config->tno_intr = 0x1; /* TCO stats enable */
44e4925e
DG		 1147 /* Enable TCO in extended config */
1148 if (nic->mac >= mac_82551_10) {
1149 config->byte_count = 0x20; /* extended bytes */
1150 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1151 }
1152 } else {
1da177e4 1153 config->standard_stat_counter = 0x0;
44e4925e 1154 }
1da177e4
LT		 1155 }
1156
fa05e1ad
JP		 1157 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1158 "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1159 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1160 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1161 "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1162 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1163 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1164 "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1165 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1da177e4
LT		 1166}
1167
2afecc04
JB		 1168/*************************************************************************
1169* CPUSaver parameters
1170*
1171* All CPUSaver parameters are 16-bit literals that are part of a
1172* "move immediate value" instruction. By changing the value of
1173* the literal in the instruction before the code is loaded, the
1174* driver can change the algorithm.
1175*
0779bf2d 1176* INTDELAY - This loads the dead-man timer with its initial value.
05479938 1177* When this timer expires the interrupt is asserted, and the
2afecc04
JB		 1178* timer is reset each time a new packet is received. (see
1179* BUNDLEMAX below to set the limit on number of chained packets)
1180* The current default is 0x600 or 1536. Experiments show that
1181* the value should probably stay within the 0x200 - 0x1000.
1182*
05479938 1183* BUNDLEMAX -
2afecc04
JB		 1184* This sets the maximum number of frames that will be bundled. In
1185* some situations, such as the TCP windowing algorithm, it may be
1186* better to limit the growth of the bundle size than let it go as
1187* high as it can, because that could cause too much added latency.
1188* The default is six, because this is the number of packets in the
1189* default TCP window size. A value of 1 would make CPUSaver indicate
1190* an interrupt for every frame received. If you do not want to put
1191* a limit on the bundle size, set this value to xFFFF.
1192*
05479938 1193* BUNDLESMALL -
2afecc04
JB		 1194* This contains a bit-mask describing the minimum size frame that
1195* will be bundled. The default masks the lower 7 bits, which means
1196* that any frame less than 128 bytes in length will not be bundled,
1197* but will instead immediately generate an interrupt. This does
1198* not affect the current bundle in any way. Any frame that is 128
1199* bytes or large will be bundled normally. This feature is meant
1200* to provide immediate indication of ACK frames in a TCP environment.
1201* Customers were seeing poor performance when a machine with CPUSaver
1202* enabled was sending but not receiving. The delay introduced when
1203* the ACKs were received was enough to reduce total throughput, because
1204* the sender would sit idle until the ACK was finally seen.
1205*
1206* The current default is 0xFF80, which masks out the lower 7 bits.
1207* This means that any frame which is x7F (127) bytes or smaller
05479938 1208* will cause an immediate interrupt. Because this value must be a
2afecc04
JB		 1209* bit mask, there are only a few valid values that can be used. To
1210* turn this feature off, the driver can write the value xFFFF to the
1211* lower word of this instruction (in the same way that the other
1212* parameters are used). Likewise, a value of 0xF800 (2047) would
1213* cause an interrupt to be generated for every frame, because all
1214* standard Ethernet frames are <= 2047 bytes in length.
1215*************************************************************************/
1216
05479938 1217/* if you wish to disable the ucode functionality, while maintaining the
2afecc04
JB		 1218 * workarounds it provides, set the following defines to:
1219 * BUNDLESMALL 0
1220 * BUNDLEMAX 1
1221 * INTDELAY 1
1222 */
1223#define BUNDLESMALL 1
1224#define BUNDLEMAX (u16)6
1225#define INTDELAY (u16)1536 /* 0x600 */
1226
9ac32e1b
JSR		 1227/* Initialize firmware */
1228static const struct firmware *e100_request_firmware(struct nic *nic)
1229{
1230 const char *fw_name;
7e15b0c9 1231 const struct firmware *fw = nic->fw;
9ac32e1b 1232 u8 timer, bundle, min_size;
7e15b0c9 1233 int err = 0;
9ac32e1b 1234
2afecc04
JB		 1235 /* do not load u-code for ICH devices */
1236 if (nic->flags & ich)
9ac32e1b 1237 return NULL;
2afecc04 1238
44c10138 1239 /* Search for ucode match against h/w revision */
9ac32e1b
JSR		 1240 if (nic->mac == mac_82559_D101M)
1241 fw_name = FIRMWARE_D101M;
1242 else if (nic->mac == mac_82559_D101S)
1243 fw_name = FIRMWARE_D101S;
1244 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1245 fw_name = FIRMWARE_D102E;
1246 else /* No ucode on other devices */
1247 return NULL;
1248
7e15b0c9
DG		 1249 /* If the firmware has not previously been loaded, request a pointer
1250 * to it. If it was previously loaded, we are reinitializing the
1251 * adapter, possibly in a resume from hibernate, in which case
1252 * request_firmware() cannot be used.
1253 */
1254 if (!fw)
1255 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1256
9ac32e1b 1257 if (err) {
fa05e1ad
JP		 1258 netif_err(nic, probe, nic->netdev,
1259 "Failed to load firmware \"%s\": %d\n",
1260 fw_name, err);
9ac32e1b
JSR		 1261 return ERR_PTR(err);
1262 }
7e15b0c9 1263
9ac32e1b
JSR		 1264 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1265 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1266 if (fw->size != UCODE_SIZE * 4 + 3) {
fa05e1ad
JP		 1267 netif_err(nic, probe, nic->netdev,
1268 "Firmware \"%s\" has wrong size %zu\n",
1269 fw_name, fw->size);
9ac32e1b
JSR		 1270 release_firmware(fw);
1271 return ERR_PTR(-EINVAL);
2afecc04
JB		 1272 }
1273
9ac32e1b
JSR		 1274 /* Read timer, bundle and min_size from end of firmware blob */
1275 timer = fw->data[UCODE_SIZE * 4];
1276 bundle = fw->data[UCODE_SIZE * 4 + 1];
1277 min_size = fw->data[UCODE_SIZE * 4 + 2];
1278
1279 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1280 min_size >= UCODE_SIZE) {
fa05e1ad
JP		 1281 netif_err(nic, probe, nic->netdev,
1282 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1283 fw_name, timer, bundle, min_size);
9ac32e1b
JSR		 1284 release_firmware(fw);
1285 return ERR_PTR(-EINVAL);
1286 }
7e15b0c9
DG		 1287
1288 /* OK, firmware is validated and ready to use. Save a pointer
1289 * to it in the nic */
1290 nic->fw = fw;
9ac32e1b 1291 return fw;
24180333
JB		 1292}
1293
9ac32e1b
JSR		 1294static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1295 struct sk_buff *skb)
24180333 1296{
9ac32e1b
JSR		 1297 const struct firmware *fw = (void *)skb;
1298 u8 timer, bundle, min_size;
1299
1300 /* It's not a real skb; we just abused the fact that e100_exec_cb
1301 will pass it through to here... */
1302 cb->skb = NULL;
1303
1304 /* firmware is stored as little endian already */
1305 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1306
1307 /* Read timer, bundle and min_size from end of firmware blob */
1308 timer = fw->data[UCODE_SIZE * 4];
1309 bundle = fw->data[UCODE_SIZE * 4 + 1];
1310 min_size = fw->data[UCODE_SIZE * 4 + 2];
1311
1312 /* Insert user-tunable settings in cb->u.ucode */
1313 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1314 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1315 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1316 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1317 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1318 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1319
1320 cb->command = cpu_to_le16(cb_ucode | cb_el);
1321}
1322
1323static inline int e100_load_ucode_wait(struct nic *nic)
1324{
1325 const struct firmware *fw;
24180333
JB		 1326 int err = 0, counter = 50;
1327 struct cb *cb = nic->cb_to_clean;
1328
9ac32e1b
JSR		 1329 fw = e100_request_firmware(nic);
1330 /* If it's NULL, then no ucode is required */
1331 if (!fw || IS_ERR(fw))
1332 return PTR_ERR(fw);
1333
1334 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
fa05e1ad
JP		 1335 netif_err(nic, probe, nic->netdev,
1336 "ucode cmd failed with error %d\n", err);
05479938 1337
24180333
JB		 1338 /* must restart cuc */
1339 nic->cuc_cmd = cuc_start;
1340
1341 /* wait for completion */
1342 e100_write_flush(nic);
1343 udelay(10);
1344
1345 /* wait for possibly (ouch) 500ms */
1346 while (!(cb->status & cpu_to_le16(cb_complete))) {
1347 msleep(10);
1348 if (!--counter) break;
1349 }
05479938 1350
3a4fa0a2 1351 /* ack any interrupts, something could have been set */
27345bb6 1352 iowrite8(~0, &nic->csr->scb.stat_ack);
24180333
JB		 1353
1354 /* if the command failed, or is not OK, notify and return */
1355 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
fa05e1ad 1356 netif_err(nic, probe, nic->netdev, "ucode load failed\n");
24180333
JB		 1357 err = -EPERM;
1358 }
05479938 1359
24180333 1360 return err;
1da177e4
LT		 1361}
1362
1363static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1364 struct sk_buff *skb)
1365{
1366 cb->command = cpu_to_le16(cb_iaaddr);
1367 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1368}
1369
1370static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1371{
1372 cb->command = cpu_to_le16(cb_dump);
1373 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1374 offsetof(struct mem, dump_buf));
1375}
1376
72001762
AM		 1377static int e100_phy_check_without_mii(struct nic *nic)
1378{
1379 u8 phy_type;
1380 int without_mii;
1381
1382 phy_type = (nic->eeprom[eeprom_phy_iface] >> 8) & 0x0f;
1383
1384 switch (phy_type) {
1385 case NoSuchPhy: /* Non-MII PHY; UNTESTED! */
1386 case I82503: /* Non-MII PHY; UNTESTED! */
1387 case S80C24: /* Non-MII PHY; tested and working */
1388 /* paragraph from the FreeBSD driver, "FXP_PHY_80C24":
1389 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
1390 * doesn't have a programming interface of any sort. The
1391 * media is sensed automatically based on how the link partner
1392 * is configured. This is, in essence, manual configuration.
1393 */
fa05e1ad
JP		 1394 netif_info(nic, probe, nic->netdev,
1395 "found MII-less i82503 or 80c24 or other PHY\n");
72001762
AM		 1396
1397 nic->mdio_ctrl = mdio_ctrl_phy_mii_emulated;
1398 nic->mii.phy_id = 0; /* is this ok for an MII-less PHY? */
1399
1400 /* these might be needed for certain MII-less cards...
1401 * nic->flags |= ich;
1402 * nic->flags |= ich_10h_workaround; */
1403
1404 without_mii = 1;
1405 break;
1406 default:
1407 without_mii = 0;
1408 break;
1409 }
1410 return without_mii;
1411}
1412
1da177e4
LT		 1413#define NCONFIG_AUTO_SWITCH 0x0080
1414#define MII_NSC_CONG MII_RESV1
1415#define NSC_CONG_ENABLE 0x0100
1416#define NSC_CONG_TXREADY 0x0400
1417#define ADVERTISE_FC_SUPPORTED 0x0400
1418static int e100_phy_init(struct nic *nic)
1419{
1420 struct net_device *netdev = nic->netdev;
1421 u32 addr;
1422 u16 bmcr, stat, id_lo, id_hi, cong;
1423
1424 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
f26251eb 1425 for (addr = 0; addr < 32; addr++) {
1da177e4
LT		 1426 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1427 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1428 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1429 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
f26251eb 1430 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1da177e4
LT		 1431 break;
1432 }
72001762
AM		 1433 if (addr == 32) {
1434 /* uhoh, no PHY detected: check whether we seem to be some
1435 * weird, rare variant which is *known* to not have any MII.
1436 * But do this AFTER MII checking only, since this does
1437 * lookup of EEPROM values which may easily be unreliable. */
1438 if (e100_phy_check_without_mii(nic))
1439 return 0; /* simply return and hope for the best */
1440 else {
1441 /* for unknown cases log a fatal error */
fa05e1ad
JP		 1442 netif_err(nic, hw, nic->netdev,
1443 "Failed to locate any known PHY, aborting\n");
72001762
AM		 1444 return -EAGAIN;
1445 }
1446 } else
fa05e1ad
JP		 1447 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1448 "phy_addr = %d\n", nic->mii.phy_id);
1da177e4 1449
1da177e4
LT		 1450 /* Get phy ID */
1451 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1452 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1453 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
fa05e1ad
JP		 1454 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1455 "phy ID = 0x%08X\n", nic->phy);
1da177e4 1456
8fbd962e
BA		 1457 /* Select the phy and isolate the rest */
1458 for (addr = 0; addr < 32; addr++) {
1459 if (addr != nic->mii.phy_id) {
1460 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1461 } else if (nic->phy != phy_82552_v) {
1462 bmcr = mdio_read(netdev, addr, MII_BMCR);
1463 mdio_write(netdev, addr, MII_BMCR,
1464 bmcr & ~BMCR_ISOLATE);
1465 }
1466 }
1467 /*
1468 * Workaround for 82552:
1469 * Clear the ISOLATE bit on selected phy_id last (mirrored on all
1470 * other phy_id's) using bmcr value from addr discovery loop above.
1471 */
1472 if (nic->phy == phy_82552_v)
1473 mdio_write(netdev, nic->mii.phy_id, MII_BMCR,
1474 bmcr & ~BMCR_ISOLATE);
1475
1da177e4
LT		 1476 /* Handle National tx phys */
1477#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
f26251eb 1478 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1da177e4
LT		 1479 /* Disable congestion control */
1480 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1481 cong |= NSC_CONG_TXREADY;
1482 cong &= ~NSC_CONG_ENABLE;
1483 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1484 }
1485
b55de80e
BA		 1486 if (nic->phy == phy_82552_v) {
1487 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1488
72001762
AM		 1489 /* assign special tweaked mdio_ctrl() function */
1490 nic->mdio_ctrl = mdio_ctrl_phy_82552_v;
1491
b55de80e
BA		 1492 /* Workaround Si not advertising flow-control during autoneg */
1493 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1494 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1495
1496 /* Reset for the above changes to take effect */
1497 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1498 bmcr |= BMCR_RESET;
1499 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1500 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
60ffa478
JK		 1501 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1502 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1503 /* enable/disable MDI/MDI-X auto-switching. */
1504 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1505 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
64895145 1506 }
1da177e4
LT		 1507
1508 return 0;
1509}
1510
1511static int e100_hw_init(struct nic *nic)
1512{
dca97ad2 1513 int err = 0;
1da177e4
LT		 1514
1515 e100_hw_reset(nic);
1516
fa05e1ad 1517 netif_err(nic, hw, nic->netdev, "e100_hw_init\n");
f26251eb 1518 if (!in_interrupt() && (err = e100_self_test(nic)))
1da177e4
LT		 1519 return err;
1520
f26251eb 1521 if ((err = e100_phy_init(nic)))
1da177e4 1522 return err;
f26251eb 1523 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1da177e4 1524 return err;
f26251eb 1525 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1da177e4 1526 return err;
9ac32e1b 1527 if ((err = e100_load_ucode_wait(nic)))
1da177e4 1528 return err;
f26251eb 1529 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1da177e4 1530 return err;
f26251eb 1531 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1da177e4 1532 return err;
f26251eb 1533 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1da177e4
LT		 1534 nic->dma_addr + offsetof(struct mem, stats))))
1535 return err;
f26251eb 1536 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1da177e4
LT		 1537 return err;
1538
1539 e100_disable_irq(nic);
1540
1541 return 0;
1542}
1543
1544static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1545{
1546 struct net_device *netdev = nic->netdev;
22bedad3 1547 struct netdev_hw_addr *ha;
4cd24eaf 1548 u16 i, count = min(netdev_mc_count(netdev), E100_MAX_MULTICAST_ADDRS);
1da177e4
LT		 1549
1550 cb->command = cpu_to_le16(cb_multi);
1551 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
48e2f183 1552 i = 0;
22bedad3 1553 netdev_for_each_mc_addr(ha, netdev) {
48e2f183
JP		 1554 if (i == count)
1555 break;
22bedad3 1556 memcpy(&cb->u.multi.addr[i++ * ETH_ALEN], &ha->addr,
1da177e4 1557 ETH_ALEN);
48e2f183 1558 }
1da177e4
LT		 1559}
1560
1561static void e100_set_multicast_list(struct net_device *netdev)
1562{
1563 struct nic *nic = netdev_priv(netdev);
1564
fa05e1ad
JP		 1565 netif_printk(nic, hw, KERN_DEBUG, nic->netdev,
1566 "mc_count=%d, flags=0x%04X\n",
1567 netdev_mc_count(netdev), netdev->flags);
1da177e4 1568
f26251eb 1569 if (netdev->flags & IFF_PROMISC)
1da177e4
LT		 1570 nic->flags |= promiscuous;
1571 else
1572 nic->flags &= ~promiscuous;
1573
f26251eb 1574 if (netdev->flags & IFF_ALLMULTI ||
4cd24eaf 1575 netdev_mc_count(netdev) > E100_MAX_MULTICAST_ADDRS)
1da177e4
LT		 1576 nic->flags |= multicast_all;
1577 else
1578 nic->flags &= ~multicast_all;
1579
1580 e100_exec_cb(nic, NULL, e100_configure);
1581 e100_exec_cb(nic, NULL, e100_multi);
1582}
1583
1584static void e100_update_stats(struct nic *nic)
1585{
09f75cd7
JG		 1586 struct net_device *dev = nic->netdev;
1587 struct net_device_stats *ns = &dev->stats;
1da177e4 1588 struct stats *s = &nic->mem->stats;
aaf918ba
AV		 1589 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1590 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1da177e4
LT		 1591 &s->complete;
1592
1593 /* Device's stats reporting may take several microseconds to
0a0863af 1594 * complete, so we're always waiting for results of the
1da177e4
LT		 1595 * previous command. */
1596
f26251eb 1597 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1da177e4
LT		 1598 *complete = 0;
1599 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1600 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1601 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1602 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1603 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1604 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1605 ns->collisions += nic->tx_collisions;
1606 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1607 le32_to_cpu(s->tx_lost_crs);
1da177e4
LT		 1608 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1609 nic->rx_over_length_errors;
1610 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1611 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1612 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1613 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
ecf7130b 1614 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1da177e4
LT		 1615 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1616 le32_to_cpu(s->rx_alignment_errors) +
1617 le32_to_cpu(s->rx_short_frame_errors) +
1618 le32_to_cpu(s->rx_cdt_errors);
1619 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1620 nic->tx_single_collisions +=
1621 le32_to_cpu(s->tx_single_collisions);
1622 nic->tx_multiple_collisions +=
1623 le32_to_cpu(s->tx_multiple_collisions);
f26251eb 1624 if (nic->mac >= mac_82558_D101_A4) {
1da177e4
LT		 1625 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1626 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1627 nic->rx_fc_unsupported +=
1628 le32_to_cpu(s->fc_rcv_unsupported);
f26251eb 1629 if (nic->mac >= mac_82559_D101M) {
1da177e4
LT		 1630 nic->tx_tco_frames +=
1631 le16_to_cpu(s->xmt_tco_frames);
1632 nic->rx_tco_frames +=
1633 le16_to_cpu(s->rcv_tco_frames);
1634 }
1635 }
1636 }
1637
05479938 1638
f26251eb 1639 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
fa05e1ad
JP		 1640 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1641 "exec cuc_dump_reset failed\n");
1da177e4
LT		 1642}
1643
1644static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1645{
1646 /* Adjust inter-frame-spacing (IFS) between two transmits if
1647 * we're getting collisions on a half-duplex connection. */
1648
f26251eb 1649 if (duplex == DUPLEX_HALF) {
1da177e4
LT		 1650 u32 prev = nic->adaptive_ifs;
1651 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1652
f26251eb 1653 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1da177e4 1654 (nic->tx_frames > min_frames)) {
f26251eb 1655 if (nic->adaptive_ifs < 60)
1da177e4
LT		 1656 nic->adaptive_ifs += 5;
1657 } else if (nic->tx_frames < min_frames) {
f26251eb 1658 if (nic->adaptive_ifs >= 5)
1da177e4
LT		 1659 nic->adaptive_ifs -= 5;
1660 }
f26251eb 1661 if (nic->adaptive_ifs != prev)
1da177e4
LT		 1662 e100_exec_cb(nic, NULL, e100_configure);
1663 }
1664}
1665
1666static void e100_watchdog(unsigned long data)
1667{
1668 struct nic *nic = (struct nic *)data;
8ae6daca 1669 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
25db0338 1670 u32 speed;
1da177e4 1671
fa05e1ad
JP		 1672 netif_printk(nic, timer, KERN_DEBUG, nic->netdev,
1673 "right now = %ld\n", jiffies);
1da177e4
LT		 1674
1675 /* mii library handles link maintenance tasks */
1676
1677 mii_ethtool_gset(&nic->mii, &cmd);
25db0338 1678 speed = ethtool_cmd_speed(&cmd);
1da177e4 1679
f26251eb 1680 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
fa05e1ad 1681 netdev_info(nic->netdev, "NIC Link is Up %u Mbps %s Duplex\n",
25db0338 1682 speed == SPEED_100 ? 100 : 10,
fa05e1ad 1683 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
f26251eb 1684 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
fa05e1ad 1685 netdev_info(nic->netdev, "NIC Link is Down\n");
1da177e4
LT		 1686 }
1687
1688 mii_check_link(&nic->mii);
1689
1690 /* Software generated interrupt to recover from (rare) Rx
05479938
JB		 1691 * allocation failure.
1692 * Unfortunately have to use a spinlock to not re-enable interrupts
1693 * accidentally, due to hardware that shares a register between the
1694 * interrupt mask bit and the SW Interrupt generation bit */
1da177e4 1695 spin_lock_irq(&nic->cmd_lock);
27345bb6 1696 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1da177e4 1697 e100_write_flush(nic);
ad8c48ad 1698 spin_unlock_irq(&nic->cmd_lock);
1da177e4
LT		 1699
1700 e100_update_stats(nic);
25db0338 1701 e100_adjust_adaptive_ifs(nic, speed, cmd.duplex);
1da177e4 1702
f26251eb 1703 if (nic->mac <= mac_82557_D100_C)
1da177e4
LT		 1704 /* Issue a multicast command to workaround a 557 lock up */
1705 e100_set_multicast_list(nic->netdev);
1706
25db0338 1707 if (nic->flags & ich && speed == SPEED_10 && cmd.duplex == DUPLEX_HALF)
1da177e4
LT		 1708 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1709 nic->flags |= ich_10h_workaround;
1710 else
1711 nic->flags &= ~ich_10h_workaround;
1712
34c6417b
SH		 1713 mod_timer(&nic->watchdog,
1714 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1da177e4
LT		 1715}
1716
858119e1 1717static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1da177e4
LT		 1718 struct sk_buff *skb)
1719{
1720 cb->command = nic->tx_command;
962082b6 1721 /* interrupt every 16 packets regardless of delay */
f26251eb 1722 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
996ec353 1723 cb->command |= cpu_to_le16(cb_i);
1da177e4
LT		 1724 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1725 cb->u.tcb.tcb_byte_count = 0;
1726 cb->u.tcb.threshold = nic->tx_threshold;
1727 cb->u.tcb.tbd_count = 1;
1728 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1729 skb->data, skb->len, PCI_DMA_TODEVICE));
611494dc 1730 /* check for mapping failure? */
1da177e4
LT		 1731 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1732}
1733
3b29a56d
SH		 1734static netdev_tx_t e100_xmit_frame(struct sk_buff *skb,
1735 struct net_device *netdev)
1da177e4
LT		 1736{
1737 struct nic *nic = netdev_priv(netdev);
1738 int err;
1739
f26251eb 1740 if (nic->flags & ich_10h_workaround) {
1da177e4
LT		 1741 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1742 Issue a NOP command followed by a 1us delay before
1743 issuing the Tx command. */
f26251eb 1744 if (e100_exec_cmd(nic, cuc_nop, 0))
fa05e1ad
JP		 1745 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1746 "exec cuc_nop failed\n");
1da177e4
LT		 1747 udelay(1);
1748 }
1749
1750 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1751
f26251eb 1752 switch (err) {
1da177e4
LT		 1753 case -ENOSPC:
1754 /* We queued the skb, but now we're out of space. */
fa05e1ad
JP		 1755 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1756 "No space for CB\n");
1da177e4
LT		 1757 netif_stop_queue(netdev);
1758 break;
1759 case -ENOMEM:
1760 /* This is a hard error - log it. */
fa05e1ad
JP		 1761 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
1762 "Out of Tx resources, returning skb\n");
1da177e4 1763 netif_stop_queue(netdev);
5b548140 1764 return NETDEV_TX_BUSY;
1da177e4
LT		 1765 }
1766
6ed10654 1767 return NETDEV_TX_OK;
1da177e4
LT		 1768}
1769
858119e1 1770static int e100_tx_clean(struct nic *nic)
1da177e4 1771{
09f75cd7 1772 struct net_device *dev = nic->netdev;
1da177e4
LT		 1773 struct cb *cb;
1774 int tx_cleaned = 0;
1775
1776 spin_lock(&nic->cb_lock);
1777
1da177e4 1778 /* Clean CBs marked complete */
f26251eb 1779 for (cb = nic->cb_to_clean;
1da177e4
LT		 1780 cb->status & cpu_to_le16(cb_complete);
1781 cb = nic->cb_to_clean = cb->next) {
2d0bb1c1 1782 rmb(); /* read skb after status */
fa05e1ad
JP		 1783 netif_printk(nic, tx_done, KERN_DEBUG, nic->netdev,
1784 "cb[%d]->status = 0x%04X\n",
1785 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1786 cb->status);
dc45010e 1787
f26251eb 1788 if (likely(cb->skb != NULL)) {
09f75cd7
JG		 1789 dev->stats.tx_packets++;
1790 dev->stats.tx_bytes += cb->skb->len;
1da177e4
LT		 1791
1792 pci_unmap_single(nic->pdev,
1793 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1794 le16_to_cpu(cb->u.tcb.tbd.size),
1795 PCI_DMA_TODEVICE);
1796 dev_kfree_skb_any(cb->skb);
1797 cb->skb = NULL;
1798 tx_cleaned = 1;
1799 }
1800 cb->status = 0;
1801 nic->cbs_avail++;
1802 }
1803
1804 spin_unlock(&nic->cb_lock);
1805
1806 /* Recover from running out of Tx resources in xmit_frame */
f26251eb 1807 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1da177e4
LT		 1808 netif_wake_queue(nic->netdev);
1809
1810 return tx_cleaned;
1811}
1812
1813static void e100_clean_cbs(struct nic *nic)
1814{
f26251eb
BA		 1815 if (nic->cbs) {
1816 while (nic->cbs_avail != nic->params.cbs.count) {
1da177e4 1817 struct cb *cb = nic->cb_to_clean;
f26251eb 1818 if (cb->skb) {
1da177e4
LT		 1819 pci_unmap_single(nic->pdev,
1820 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1821 le16_to_cpu(cb->u.tcb.tbd.size),
1822 PCI_DMA_TODEVICE);
1823 dev_kfree_skb(cb->skb);
1824 }
1825 nic->cb_to_clean = nic->cb_to_clean->next;
1826 nic->cbs_avail++;
1827 }
98468efd 1828 pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
1da177e4
LT		 1829 nic->cbs = NULL;
1830 nic->cbs_avail = 0;
1831 }
1832 nic->cuc_cmd = cuc_start;
1833 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1834 nic->cbs;
1835}
1836
1837static int e100_alloc_cbs(struct nic *nic)
1838{
1839 struct cb *cb;
1840 unsigned int i, count = nic->params.cbs.count;
1841
1842 nic->cuc_cmd = cuc_start;
1843 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1844 nic->cbs_avail = 0;
1845
98468efd
RO		 1846 nic->cbs = pci_pool_alloc(nic->cbs_pool, GFP_KERNEL,
1847 &nic->cbs_dma_addr);
f26251eb 1848 if (!nic->cbs)
1da177e4 1849 return -ENOMEM;
70abc8cb 1850 memset(nic->cbs, 0, count * sizeof(struct cb));
1da177e4 1851
f26251eb 1852 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1da177e4
LT		 1853 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1854 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1855
1856 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1857 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1858 ((i+1) % count) * sizeof(struct cb));
1da177e4
LT		 1859 }
1860
1861 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1862 nic->cbs_avail = count;
1863
1864 return 0;
1865}
1866
ca93ca42 1867static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1da177e4 1868{
f26251eb
BA		 1869 if (!nic->rxs) return;
1870 if (RU_SUSPENDED != nic->ru_running) return;
ca93ca42
JG		 1871
1872 /* handle init time starts */
f26251eb 1873 if (!rx) rx = nic->rxs;
ca93ca42
JG		 1874
1875 /* (Re)start RU if suspended or idle and RFA is non-NULL */
f26251eb 1876 if (rx->skb) {
ca93ca42
JG		 1877 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1878 nic->ru_running = RU_RUNNING;
1879 }
1da177e4
LT		 1880}
1881
1882#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
858119e1 1883static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1da177e4 1884{
89d71a66 1885 if (!(rx->skb = netdev_alloc_skb_ip_align(nic->netdev, RFD_BUF_LEN)))
1da177e4
LT		 1886 return -ENOMEM;
1887
89d71a66 1888 /* Init, and map the RFD. */
27d7ff46 1889 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1da177e4
LT		 1890 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1891 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1892
8d8bb39b 1893 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1f53367d 1894 dev_kfree_skb_any(rx->skb);
097688ef 1895 rx->skb = NULL;
1f53367d
MC		 1896 rx->dma_addr = 0;
1897 return -ENOMEM;
1898 }
1899
1da177e4 1900 /* Link the RFD to end of RFA by linking previous RFD to
7734f6e6
DA		 1901 * this one. We are safe to touch the previous RFD because
1902 * it is protected by the before last buffer's el bit being set */
aaf918ba 1903 if (rx->prev->skb) {
1da177e4 1904 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
6caf52a4 1905 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1923815d 1906 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
773c9c1f 1907 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 1908 }
1909
1910 return 0;
1911}
1912
858119e1 1913static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1da177e4
LT		 1914 unsigned int *work_done, unsigned int work_to_do)
1915{
09f75cd7 1916 struct net_device *dev = nic->netdev;
1da177e4
LT		 1917 struct sk_buff *skb = rx->skb;
1918 struct rfd *rfd = (struct rfd *)skb->data;
1919 u16 rfd_status, actual_size;
1920
f26251eb 1921 if (unlikely(work_done && *work_done >= work_to_do))
1da177e4
LT		 1922 return -EAGAIN;
1923
1924 /* Need to sync before taking a peek at cb_complete bit */
1925 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
773c9c1f 1926 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 1927 rfd_status = le16_to_cpu(rfd->status);
1928
fa05e1ad
JP		 1929 netif_printk(nic, rx_status, KERN_DEBUG, nic->netdev,
1930 "status=0x%04X\n", rfd_status);
2d0bb1c1 1931 rmb(); /* read size after status bit */
1da177e4
LT		 1932
1933 /* If data isn't ready, nothing to indicate */
7734f6e6
DA		 1934 if (unlikely(!(rfd_status & cb_complete))) {
1935 /* If the next buffer has the el bit, but we think the receiver
1936 * is still running, check to see if it really stopped while
1937 * we had interrupts off.
1938 * This allows for a fast restart without re-enabling
1939 * interrupts */
1940 if ((le16_to_cpu(rfd->command) & cb_el) &&
1941 (RU_RUNNING == nic->ru_running))
1942
17393dd6 1943 if (ioread8(&nic->csr->scb.status) & rus_no_res)
7734f6e6 1944 nic->ru_running = RU_SUSPENDED;
303d67c2
KH		 1945 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1946 sizeof(struct rfd),
6ff9c2e7 1947 PCI_DMA_FROMDEVICE);
1f53367d 1948 return -ENODATA;
7734f6e6 1949 }
1da177e4
LT		 1950
1951 /* Get actual data size */
1952 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
f26251eb 1953 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1da177e4
LT		 1954 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1955
1956 /* Get data */
1957 pci_unmap_single(nic->pdev, rx->dma_addr,
773c9c1f 1958 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1da177e4 1959
7734f6e6
DA		 1960 /* If this buffer has the el bit, but we think the receiver
1961 * is still running, check to see if it really stopped while
1962 * we had interrupts off.
1963 * This allows for a fast restart without re-enabling interrupts.
1964 * This can happen when the RU sees the size change but also sees
1965 * the el bit set. */
1966 if ((le16_to_cpu(rfd->command) & cb_el) &&
1967 (RU_RUNNING == nic->ru_running)) {
1968
17393dd6 1969 if (ioread8(&nic->csr->scb.status) & rus_no_res)
ca93ca42 1970 nic->ru_running = RU_SUSPENDED;
7734f6e6 1971 }
ca93ca42 1972
1da177e4
LT		 1973 /* Pull off the RFD and put the actual data (minus eth hdr) */
1974 skb_reserve(skb, sizeof(struct rfd));
1975 skb_put(skb, actual_size);
1976 skb->protocol = eth_type_trans(skb, nic->netdev);
1977
f26251eb 1978 if (unlikely(!(rfd_status & cb_ok))) {
1da177e4 1979 /* Don't indicate if hardware indicates errors */
1da177e4 1980 dev_kfree_skb_any(skb);
f26251eb 1981 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1da177e4
LT		 1982 /* Don't indicate oversized frames */
1983 nic->rx_over_length_errors++;
1da177e4
LT		 1984 dev_kfree_skb_any(skb);
1985 } else {
09f75cd7
JG		 1986 dev->stats.rx_packets++;
1987 dev->stats.rx_bytes += actual_size;
1da177e4 1988 netif_receive_skb(skb);
f26251eb 1989 if (work_done)
1da177e4
LT		 1990 (*work_done)++;
1991 }
1992
1993 rx->skb = NULL;
1994
1995 return 0;
1996}
1997
858119e1 1998static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1da177e4
LT		 1999 unsigned int work_to_do)
2000{
2001 struct rx *rx;
7734f6e6
DA		 2002 int restart_required = 0, err = 0;
2003 struct rx *old_before_last_rx, *new_before_last_rx;
2004 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1da177e4
LT		 2005
2006 /* Indicate newly arrived packets */
f26251eb 2007 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
7734f6e6
DA		 2008 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
2009 /* Hit quota or no more to clean */
2010 if (-EAGAIN == err || -ENODATA == err)
ca93ca42 2011 break;
1da177e4
LT		 2012 }
2013
7734f6e6
DA		 2014
2015 /* On EAGAIN, hit quota so have more work to do, restart once
2016 * cleanup is complete.
2017 * Else, are we already rnr? then pay attention!!! this ensures that
2018 * the state machine progression never allows a start with a
2019 * partially cleaned list, avoiding a race between hardware
2020 * and rx_to_clean when in NAPI mode */
2021 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
2022 restart_required = 1;
2023
2024 old_before_last_rx = nic->rx_to_use->prev->prev;
2025 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
ca93ca42 2026
1da177e4 2027 /* Alloc new skbs to refill list */
f26251eb
BA		 2028 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
2029 if (unlikely(e100_rx_alloc_skb(nic, rx)))
1da177e4
LT		 2030 break; /* Better luck next time (see watchdog) */
2031 }
ca93ca42 2032
7734f6e6
DA		 2033 new_before_last_rx = nic->rx_to_use->prev->prev;
2034 if (new_before_last_rx != old_before_last_rx) {
2035 /* Set the el-bit on the buffer that is before the last buffer.
2036 * This lets us update the next pointer on the last buffer
2037 * without worrying about hardware touching it.
2038 * We set the size to 0 to prevent hardware from touching this
2039 * buffer.
2040 * When the hardware hits the before last buffer with el-bit
2041 * and size of 0, it will RNR interrupt, the RUS will go into
2042 * the No Resources state. It will not complete nor write to
2043 * this buffer. */
2044 new_before_last_rfd =
2045 (struct rfd *)new_before_last_rx->skb->data;
2046 new_before_last_rfd->size = 0;
2047 new_before_last_rfd->command |= cpu_to_le16(cb_el);
2048 pci_dma_sync_single_for_device(nic->pdev,
2049 new_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2050 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2051
2052 /* Now that we have a new stopping point, we can clear the old
2053 * stopping point. We must sync twice to get the proper
2054 * ordering on the hardware side of things. */
2055 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
2056 pci_dma_sync_single_for_device(nic->pdev,
2057 old_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2058 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2059 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
2060 pci_dma_sync_single_for_device(nic->pdev,
2061 old_before_last_rx->dma_addr, sizeof(struct rfd),
773c9c1f 2062 PCI_DMA_BIDIRECTIONAL);
7734f6e6
DA		 2063 }
2064
f26251eb 2065 if (restart_required) {
ca93ca42 2066 // ack the rnr?
915e91d7 2067 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
7734f6e6 2068 e100_start_receiver(nic, nic->rx_to_clean);
f26251eb 2069 if (work_done)
ca93ca42
JG		 2070 (*work_done)++;
2071 }
1da177e4
LT		 2072}
2073
2074static void e100_rx_clean_list(struct nic *nic)
2075{
2076 struct rx *rx;
2077 unsigned int i, count = nic->params.rfds.count;
2078
ca93ca42
JG		 2079 nic->ru_running = RU_UNINITIALIZED;
2080
f26251eb
BA		 2081 if (nic->rxs) {
2082 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
2083 if (rx->skb) {
1da177e4 2084 pci_unmap_single(nic->pdev, rx->dma_addr,
773c9c1f 2085 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 2086 dev_kfree_skb(rx->skb);
2087 }
2088 }
2089 kfree(nic->rxs);
2090 nic->rxs = NULL;
2091 }
2092
2093 nic->rx_to_use = nic->rx_to_clean = NULL;
1da177e4
LT		 2094}
2095
2096static int e100_rx_alloc_list(struct nic *nic)
2097{
2098 struct rx *rx;
2099 unsigned int i, count = nic->params.rfds.count;
7734f6e6 2100 struct rfd *before_last;
1da177e4
LT		 2101
2102 nic->rx_to_use = nic->rx_to_clean = NULL;
ca93ca42 2103 nic->ru_running = RU_UNINITIALIZED;
1da177e4 2104
f26251eb 2105 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
1da177e4 2106 return -ENOMEM;
1da177e4 2107
f26251eb 2108 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
1da177e4
LT		 2109 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
2110 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
f26251eb 2111 if (e100_rx_alloc_skb(nic, rx)) {
1da177e4
LT		 2112 e100_rx_clean_list(nic);
2113 return -ENOMEM;
2114 }
2115 }
7734f6e6
DA		 2116 /* Set the el-bit on the buffer that is before the last buffer.
2117 * This lets us update the next pointer on the last buffer without
2118 * worrying about hardware touching it.
2119 * We set the size to 0 to prevent hardware from touching this buffer.
2120 * When the hardware hits the before last buffer with el-bit and size
2121 * of 0, it will RNR interrupt, the RU will go into the No Resources
2122 * state. It will not complete nor write to this buffer. */
2123 rx = nic->rxs->prev->prev;
2124 before_last = (struct rfd *)rx->skb->data;
2125 before_last->command |= cpu_to_le16(cb_el);
2126 before_last->size = 0;
2127 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
773c9c1f 2128 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1da177e4
LT		 2129
2130 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
ca93ca42 2131 nic->ru_running = RU_SUSPENDED;
1da177e4
LT		 2132
2133 return 0;
2134}
2135
7d12e780 2136static irqreturn_t e100_intr(int irq, void *dev_id)
1da177e4
LT		 2137{
2138 struct net_device *netdev = dev_id;
2139 struct nic *nic = netdev_priv(netdev);
27345bb6 2140 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
1da177e4 2141
fa05e1ad
JP		 2142 netif_printk(nic, intr, KERN_DEBUG, nic->netdev,
2143 "stat_ack = 0x%02X\n", stat_ack);
1da177e4 2144
f26251eb 2145 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
1da177e4
LT		 2146 stat_ack == stat_ack_not_present) /* Hardware is ejected */
2147 return IRQ_NONE;
2148
2149 /* Ack interrupt(s) */
27345bb6 2150 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
1da177e4 2151
ca93ca42 2152 /* We hit Receive No Resource (RNR); restart RU after cleaning */
f26251eb 2153 if (stat_ack & stat_ack_rnr)
ca93ca42
JG		 2154 nic->ru_running = RU_SUSPENDED;
2155
288379f0 2156 if (likely(napi_schedule_prep(&nic->napi))) {
0685c31b 2157 e100_disable_irq(nic);
288379f0 2158 __napi_schedule(&nic->napi);
0685c31b 2159 }
1da177e4
LT		 2160
2161 return IRQ_HANDLED;
2162}
2163
bea3348e 2164static int e100_poll(struct napi_struct *napi, int budget)
1da177e4 2165{
bea3348e 2166 struct nic *nic = container_of(napi, struct nic, napi);
ddfce6bb 2167 unsigned int work_done = 0;
1da177e4 2168
bea3348e 2169 e100_rx_clean(nic, &work_done, budget);
53e52c72 2170 e100_tx_clean(nic);
1da177e4 2171
53e52c72
DM		 2172 /* If budget not fully consumed, exit the polling mode */
2173 if (work_done < budget) {
288379f0 2174 napi_complete(napi);
1da177e4 2175 e100_enable_irq(nic);
1da177e4
LT		 2176 }
2177
bea3348e 2178 return work_done;
1da177e4
LT		 2179}
2180
2181#ifdef CONFIG_NET_POLL_CONTROLLER
2182static void e100_netpoll(struct net_device *netdev)
2183{
2184 struct nic *nic = netdev_priv(netdev);
611494dc 2185
1da177e4 2186 e100_disable_irq(nic);
7d12e780 2187 e100_intr(nic->pdev->irq, netdev);
1da177e4
LT		 2188 e100_tx_clean(nic);
2189 e100_enable_irq(nic);
2190}
2191#endif
2192
1da177e4
LT		 2193static int e100_set_mac_address(struct net_device *netdev, void *p)
2194{
2195 struct nic *nic = netdev_priv(netdev);
2196 struct sockaddr *addr = p;
2197
2198 if (!is_valid_ether_addr(addr->sa_data))
2199 return -EADDRNOTAVAIL;
2200
2201 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2202 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2203
2204 return 0;
2205}
2206
2207static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2208{
f26251eb 2209 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1da177e4
LT		 2210 return -EINVAL;
2211 netdev->mtu = new_mtu;
2212 return 0;
2213}
2214
2215static int e100_asf(struct nic *nic)
2216{
2217 /* ASF can be enabled from eeprom */
807540ba 2218 return (nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
1da177e4
LT		 2219 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2220 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
807540ba 2221 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE);
1da177e4
LT		 2222}
2223
2224static int e100_up(struct nic *nic)
2225{
2226 int err;
2227
f26251eb 2228 if ((err = e100_rx_alloc_list(nic)))
1da177e4 2229 return err;
f26251eb 2230 if ((err = e100_alloc_cbs(nic)))
1da177e4 2231 goto err_rx_clean_list;
f26251eb 2232 if ((err = e100_hw_init(nic)))
1da177e4
LT		 2233 goto err_clean_cbs;
2234 e100_set_multicast_list(nic->netdev);
ca93ca42 2235 e100_start_receiver(nic, NULL);
1da177e4 2236 mod_timer(&nic->watchdog, jiffies);
f26251eb 2237 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
1da177e4
LT		 2238 nic->netdev->name, nic->netdev)))
2239 goto err_no_irq;
1da177e4 2240 netif_wake_queue(nic->netdev);
bea3348e 2241 napi_enable(&nic->napi);
0236ebb7
MC		 2242 /* enable ints _after_ enabling poll, preventing a race between
2243 * disable ints+schedule */
2244 e100_enable_irq(nic);
1da177e4
LT		 2245 return 0;
2246
2247err_no_irq:
2248 del_timer_sync(&nic->watchdog);
2249err_clean_cbs:
2250 e100_clean_cbs(nic);
2251err_rx_clean_list:
2252 e100_rx_clean_list(nic);
2253 return err;
2254}
2255
2256static void e100_down(struct nic *nic)
2257{
0236ebb7 2258 /* wait here for poll to complete */
bea3348e 2259 napi_disable(&nic->napi);
0236ebb7 2260 netif_stop_queue(nic->netdev);
1da177e4
LT		 2261 e100_hw_reset(nic);
2262 free_irq(nic->pdev->irq, nic->netdev);
2263 del_timer_sync(&nic->watchdog);
2264 netif_carrier_off(nic->netdev);
1da177e4
LT		 2265 e100_clean_cbs(nic);
2266 e100_rx_clean_list(nic);
2267}
2268
2269static void e100_tx_timeout(struct net_device *netdev)
2270{
2271 struct nic *nic = netdev_priv(netdev);
2272
05479938 2273 /* Reset outside of interrupt context, to avoid request_irq
2acdb1e0
MC		 2274 * in interrupt context */
2275 schedule_work(&nic->tx_timeout_task);
2276}
2277
c4028958 2278static void e100_tx_timeout_task(struct work_struct *work)
2acdb1e0 2279{
c4028958
DH		 2280 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2281 struct net_device *netdev = nic->netdev;
2acdb1e0 2282
fa05e1ad
JP		 2283 netif_printk(nic, tx_err, KERN_DEBUG, nic->netdev,
2284 "scb.status=0x%02X\n", ioread8(&nic->csr->scb.status));
401da6ae
AC		 2285
2286 rtnl_lock();
2287 if (netif_running(netdev)) {
2288 e100_down(netdev_priv(netdev));
2289 e100_up(netdev_priv(netdev));
2290 }
2291 rtnl_unlock();
1da177e4
LT		 2292}
2293
2294static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2295{
2296 int err;
2297 struct sk_buff *skb;
2298
2299 /* Use driver resources to perform internal MAC or PHY
2300 * loopback test. A single packet is prepared and transmitted
2301 * in loopback mode, and the test passes if the received
2302 * packet compares byte-for-byte to the transmitted packet. */
2303
f26251eb 2304 if ((err = e100_rx_alloc_list(nic)))
1da177e4 2305 return err;
f26251eb 2306 if ((err = e100_alloc_cbs(nic)))
1da177e4
LT		 2307 goto err_clean_rx;
2308
2309 /* ICH PHY loopback is broken so do MAC loopback instead */
f26251eb 2310 if (nic->flags & ich && loopback_mode == lb_phy)
1da177e4
LT		 2311 loopback_mode = lb_mac;
2312
2313 nic->loopback = loopback_mode;
f26251eb 2314 if ((err = e100_hw_init(nic)))
1da177e4
LT		 2315 goto err_loopback_none;
2316
f26251eb 2317 if (loopback_mode == lb_phy)
1da177e4
LT		 2318 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2319 BMCR_LOOPBACK);
2320
ca93ca42 2321 e100_start_receiver(nic, NULL);
1da177e4 2322
f26251eb 2323 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
1da177e4
LT		 2324 err = -ENOMEM;
2325 goto err_loopback_none;
2326 }
2327 skb_put(skb, ETH_DATA_LEN);
2328 memset(skb->data, 0xFF, ETH_DATA_LEN);
2329 e100_xmit_frame(skb, nic->netdev);
2330
2331 msleep(10);
2332
aa49cdd9 2333 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
773c9c1f 2334 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
aa49cdd9 2335
f26251eb 2336 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
1da177e4
LT		 2337 skb->data, ETH_DATA_LEN))
2338 err = -EAGAIN;
2339
2340err_loopback_none:
2341 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2342 nic->loopback = lb_none;
1da177e4 2343 e100_clean_cbs(nic);
aa49cdd9 2344 e100_hw_reset(nic);
1da177e4
LT		 2345err_clean_rx:
2346 e100_rx_clean_list(nic);
2347 return err;
2348}
2349
2350#define MII_LED_CONTROL 0x1B
b55de80e
BA		 2351#define E100_82552_LED_OVERRIDE 0x19
2352#define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2353#define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
1da177e4
LT		 2354
2355static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2356{
2357 struct nic *nic = netdev_priv(netdev);
2358 return mii_ethtool_gset(&nic->mii, cmd);
2359}
2360
2361static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2362{
2363 struct nic *nic = netdev_priv(netdev);
2364 int err;
2365
2366 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2367 err = mii_ethtool_sset(&nic->mii, cmd);
2368 e100_exec_cb(nic, NULL, e100_configure);
2369
2370 return err;
2371}
2372
2373static void e100_get_drvinfo(struct net_device *netdev,
2374 struct ethtool_drvinfo *info)
2375{
2376 struct nic *nic = netdev_priv(netdev);
2377 strcpy(info->driver, DRV_NAME);
2378 strcpy(info->version, DRV_VERSION);
2379 strcpy(info->fw_version, "N/A");
2380 strcpy(info->bus_info, pci_name(nic->pdev));
2381}
2382
abf9b902 2383#define E100_PHY_REGS 0x1C
1da177e4
LT		 2384static int e100_get_regs_len(struct net_device *netdev)
2385{
2386 struct nic *nic = netdev_priv(netdev);
abf9b902 2387 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
1da177e4
LT		 2388}
2389
2390static void e100_get_regs(struct net_device *netdev,
2391 struct ethtool_regs *regs, void *p)
2392{
2393 struct nic *nic = netdev_priv(netdev);
2394 u32 *buff = p;
2395 int i;
2396
44c10138 2397 regs->version = (1 << 24) | nic->pdev->revision;
27345bb6
JB		 2398 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2399 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2400 ioread16(&nic->csr->scb.status);
f26251eb 2401 for (i = E100_PHY_REGS; i >= 0; i--)
1da177e4
LT		 2402 buff[1 + E100_PHY_REGS - i] =
2403 mdio_read(netdev, nic->mii.phy_id, i);
2404 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2405 e100_exec_cb(nic, NULL, e100_dump);
2406 msleep(10);
2407 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2408 sizeof(nic->mem->dump_buf));
2409}
2410
2411static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2412{
2413 struct nic *nic = netdev_priv(netdev);
2414 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2415 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2416}
2417
2418static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2419{
2420 struct nic *nic = netdev_priv(netdev);
2421
bc79fc84
RW		 2422 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2423 !device_can_wakeup(&nic->pdev->dev))
1da177e4
LT		 2424 return -EOPNOTSUPP;
2425
f26251eb 2426 if (wol->wolopts)
1da177e4
LT		 2427 nic->flags |= wol_magic;
2428 else
2429 nic->flags &= ~wol_magic;
2430
bc79fc84
RW		 2431 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2432
1da177e4
LT		 2433 e100_exec_cb(nic, NULL, e100_configure);
2434
2435 return 0;
2436}
2437
2438static u32 e100_get_msglevel(struct net_device *netdev)
2439{
2440 struct nic *nic = netdev_priv(netdev);
2441 return nic->msg_enable;
2442}
2443
2444static void e100_set_msglevel(struct net_device *netdev, u32 value)
2445{
2446 struct nic *nic = netdev_priv(netdev);
2447 nic->msg_enable = value;
2448}
2449
2450static int e100_nway_reset(struct net_device *netdev)
2451{
2452 struct nic *nic = netdev_priv(netdev);
2453 return mii_nway_restart(&nic->mii);
2454}
2455
2456static u32 e100_get_link(struct net_device *netdev)
2457{
2458 struct nic *nic = netdev_priv(netdev);
2459 return mii_link_ok(&nic->mii);
2460}
2461
2462static int e100_get_eeprom_len(struct net_device *netdev)
2463{
2464 struct nic *nic = netdev_priv(netdev);
2465 return nic->eeprom_wc << 1;
2466}
2467
2468#define E100_EEPROM_MAGIC 0x1234
2469static int e100_get_eeprom(struct net_device *netdev,
2470 struct ethtool_eeprom *eeprom, u8 *bytes)
2471{
2472 struct nic *nic = netdev_priv(netdev);
2473
2474 eeprom->magic = E100_EEPROM_MAGIC;
2475 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2476
2477 return 0;
2478}
2479
2480static int e100_set_eeprom(struct net_device *netdev,
2481 struct ethtool_eeprom *eeprom, u8 *bytes)
2482{
2483 struct nic *nic = netdev_priv(netdev);
2484
f26251eb 2485 if (eeprom->magic != E100_EEPROM_MAGIC)
1da177e4
LT		 2486 return -EINVAL;
2487
2488 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2489
2490 return e100_eeprom_save(nic, eeprom->offset >> 1,
2491 (eeprom->len >> 1) + 1);
2492}
2493
2494static void e100_get_ringparam(struct net_device *netdev,
2495 struct ethtool_ringparam *ring)
2496{
2497 struct nic *nic = netdev_priv(netdev);
2498 struct param_range *rfds = &nic->params.rfds;
2499 struct param_range *cbs = &nic->params.cbs;
2500
2501 ring->rx_max_pending = rfds->max;
2502 ring->tx_max_pending = cbs->max;
2503 ring->rx_mini_max_pending = 0;
2504 ring->rx_jumbo_max_pending = 0;
2505 ring->rx_pending = rfds->count;
2506 ring->tx_pending = cbs->count;
2507 ring->rx_mini_pending = 0;
2508 ring->rx_jumbo_pending = 0;
2509}
2510
2511static int e100_set_ringparam(struct net_device *netdev,
2512 struct ethtool_ringparam *ring)
2513{
2514 struct nic *nic = netdev_priv(netdev);
2515 struct param_range *rfds = &nic->params.rfds;
2516 struct param_range *cbs = &nic->params.cbs;
2517
05479938 2518 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1da177e4
LT		 2519 return -EINVAL;
2520
f26251eb 2521 if (netif_running(netdev))
1da177e4
LT		 2522 e100_down(nic);
2523 rfds->count = max(ring->rx_pending, rfds->min);
2524 rfds->count = min(rfds->count, rfds->max);
2525 cbs->count = max(ring->tx_pending, cbs->min);
2526 cbs->count = min(cbs->count, cbs->max);
fa05e1ad
JP		 2527 netif_info(nic, drv, nic->netdev, "Ring Param settings: rx: %d, tx %d\n",
2528 rfds->count, cbs->count);
f26251eb 2529 if (netif_running(netdev))
1da177e4
LT		 2530 e100_up(nic);
2531
2532 return 0;
2533}
2534
2535static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2536 "Link test (on/offline)",
2537 "Eeprom test (on/offline)",
2538 "Self test (offline)",
2539 "Mac loopback (offline)",
2540 "Phy loopback (offline)",
2541};
4c3616cd 2542#define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
1da177e4 2543
1da177e4
LT		 2544static void e100_diag_test(struct net_device *netdev,
2545 struct ethtool_test *test, u64 *data)
2546{
2547 struct ethtool_cmd cmd;
2548 struct nic *nic = netdev_priv(netdev);
2549 int i, err;
2550
2551 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2552 data[0] = !mii_link_ok(&nic->mii);
2553 data[1] = e100_eeprom_load(nic);
f26251eb 2554 if (test->flags & ETH_TEST_FL_OFFLINE) {
1da177e4
LT		 2555
2556 /* save speed, duplex & autoneg settings */
2557 err = mii_ethtool_gset(&nic->mii, &cmd);
2558
f26251eb 2559 if (netif_running(netdev))
1da177e4
LT		 2560 e100_down(nic);
2561 data[2] = e100_self_test(nic);
2562 data[3] = e100_loopback_test(nic, lb_mac);
2563 data[4] = e100_loopback_test(nic, lb_phy);
2564
2565 /* restore speed, duplex & autoneg settings */
2566 err = mii_ethtool_sset(&nic->mii, &cmd);
2567
f26251eb 2568 if (netif_running(netdev))
1da177e4
LT		 2569 e100_up(nic);
2570 }
f26251eb 2571 for (i = 0; i < E100_TEST_LEN; i++)
1da177e4 2572 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
a074fb86
MC		 2573
2574 msleep_interruptible(4 * 1000);
1da177e4
LT		 2575}
2576
a70b86ae
JK		 2577static int e100_set_phys_id(struct net_device *netdev,
2578 enum ethtool_phys_id_state state)
1da177e4
LT		 2579{
2580 struct nic *nic = netdev_priv(netdev);
a70b86ae
JK		 2581 enum led_state {
2582 led_on = 0x01,
2583 led_off = 0x04,
2584 led_on_559 = 0x05,
2585 led_on_557 = 0x07,
2586 };
b55de80e 2587 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
a70b86ae
JK		 2588 MII_LED_CONTROL;
2589 u16 leds = 0;
2590
2591 switch (state) {
2592 case ETHTOOL_ID_ACTIVE:
2593 return 2;
1da177e4 2594
a70b86ae
JK		 2595 case ETHTOOL_ID_ON:
2596 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_ON :
2597 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2598 break;
2599
2600 case ETHTOOL_ID_OFF:
2601 leds = (nic->phy == phy_82552_v) ? E100_82552_LED_OFF : led_off;
2602 break;
2603
2604 case ETHTOOL_ID_INACTIVE:
2605 break;
2606 }
1da177e4 2607
a70b86ae 2608 mdio_write(netdev, nic->mii.phy_id, led_reg, leds);
1da177e4
LT		 2609 return 0;
2610}
2611
2612static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2613 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2614 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2615 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2616 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2617 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2618 "tx_heartbeat_errors", "tx_window_errors",
2619 /* device-specific stats */
2620 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2621 "tx_flow_control_pause", "rx_flow_control_pause",
2622 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2623};
2624#define E100_NET_STATS_LEN 21
4c3616cd 2625#define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
1da177e4 2626
b9f2c044 2627static int e100_get_sset_count(struct net_device *netdev, int sset)
1da177e4 2628{
b9f2c044
JG		 2629 switch (sset) {
2630 case ETH_SS_TEST:
2631 return E100_TEST_LEN;
2632 case ETH_SS_STATS:
2633 return E100_STATS_LEN;
2634 default:
2635 return -EOPNOTSUPP;
2636 }
1da177e4
LT		 2637}
2638
2639static void e100_get_ethtool_stats(struct net_device *netdev,
2640 struct ethtool_stats *stats, u64 *data)
2641{
2642 struct nic *nic = netdev_priv(netdev);
2643 int i;
2644
f26251eb 2645 for (i = 0; i < E100_NET_STATS_LEN; i++)
09f75cd7 2646 data[i] = ((unsigned long *)&netdev->stats)[i];
1da177e4
LT		 2647
2648 data[i++] = nic->tx_deferred;
2649 data[i++] = nic->tx_single_collisions;
2650 data[i++] = nic->tx_multiple_collisions;
2651 data[i++] = nic->tx_fc_pause;
2652 data[i++] = nic->rx_fc_pause;
2653 data[i++] = nic->rx_fc_unsupported;
2654 data[i++] = nic->tx_tco_frames;
2655 data[i++] = nic->rx_tco_frames;
2656}
2657
2658static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2659{
f26251eb 2660 switch (stringset) {
1da177e4
LT		 2661 case ETH_SS_TEST:
2662 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2663 break;
2664 case ETH_SS_STATS:
2665 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2666 break;
2667 }
2668}
2669
7282d491 2670static const struct ethtool_ops e100_ethtool_ops = {
1da177e4
LT		 2671 .get_settings = e100_get_settings,
2672 .set_settings = e100_set_settings,
2673 .get_drvinfo = e100_get_drvinfo,
2674 .get_regs_len = e100_get_regs_len,
2675 .get_regs = e100_get_regs,
2676 .get_wol = e100_get_wol,
2677 .set_wol = e100_set_wol,
2678 .get_msglevel = e100_get_msglevel,
2679 .set_msglevel = e100_set_msglevel,
2680 .nway_reset = e100_nway_reset,
2681 .get_link = e100_get_link,
2682 .get_eeprom_len = e100_get_eeprom_len,
2683 .get_eeprom = e100_get_eeprom,
2684 .set_eeprom = e100_set_eeprom,
2685 .get_ringparam = e100_get_ringparam,
2686 .set_ringparam = e100_set_ringparam,
1da177e4
LT		 2687 .self_test = e100_diag_test,
2688 .get_strings = e100_get_strings,
a70b86ae 2689 .set_phys_id = e100_set_phys_id,
1da177e4 2690 .get_ethtool_stats = e100_get_ethtool_stats,
b9f2c044 2691 .get_sset_count = e100_get_sset_count,
1da177e4
LT		 2692};
2693
2694static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2695{
2696 struct nic *nic = netdev_priv(netdev);
2697
2698 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2699}
2700
2701static int e100_alloc(struct nic *nic)
2702{
2703 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2704 &nic->dma_addr);
2705 return nic->mem ? 0 : -ENOMEM;
2706}
2707
2708static void e100_free(struct nic *nic)
2709{
f26251eb 2710 if (nic->mem) {
1da177e4
LT		 2711 pci_free_consistent(nic->pdev, sizeof(struct mem),
2712 nic->mem, nic->dma_addr);
2713 nic->mem = NULL;
2714 }
2715}
2716
2717static int e100_open(struct net_device *netdev)
2718{
2719 struct nic *nic = netdev_priv(netdev);
2720 int err = 0;
2721
2722 netif_carrier_off(netdev);
f26251eb 2723 if ((err = e100_up(nic)))
fa05e1ad 2724 netif_err(nic, ifup, nic->netdev, "Cannot open interface, aborting\n");
1da177e4
LT		 2725 return err;
2726}
2727
2728static int e100_close(struct net_device *netdev)
2729{
2730 e100_down(netdev_priv(netdev));
2731 return 0;
2732}
2733
acc78426
SH		 2734static const struct net_device_ops e100_netdev_ops = {
2735 .ndo_open = e100_open,
2736 .ndo_stop = e100_close,
00829823 2737 .ndo_start_xmit = e100_xmit_frame,
acc78426
SH		 2738 .ndo_validate_addr = eth_validate_addr,
2739 .ndo_set_multicast_list = e100_set_multicast_list,
2740 .ndo_set_mac_address = e100_set_mac_address,
2741 .ndo_change_mtu = e100_change_mtu,
2742 .ndo_do_ioctl = e100_do_ioctl,
2743 .ndo_tx_timeout = e100_tx_timeout,
2744#ifdef CONFIG_NET_POLL_CONTROLLER
2745 .ndo_poll_controller = e100_netpoll,
2746#endif
2747};
2748
1da177e4
LT		 2749static int __devinit e100_probe(struct pci_dev *pdev,
2750 const struct pci_device_id *ent)
2751{
2752 struct net_device *netdev;
2753 struct nic *nic;
2754 int err;
2755
f26251eb
BA		 2756 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2757 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
fa05e1ad 2758 pr_err("Etherdev alloc failed, aborting\n");
1da177e4
LT		 2759 return -ENOMEM;
2760 }
2761
acc78426 2762 netdev->netdev_ops = &e100_netdev_ops;
1da177e4 2763 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
1da177e4 2764 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
0eb5a34c 2765 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4
LT		 2766
2767 nic = netdev_priv(netdev);
bea3348e 2768 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
1da177e4
LT		 2769 nic->netdev = netdev;
2770 nic->pdev = pdev;
2771 nic->msg_enable = (1 << debug) - 1;
72001762 2772 nic->mdio_ctrl = mdio_ctrl_hw;
1da177e4
LT		 2773 pci_set_drvdata(pdev, netdev);
2774
f26251eb 2775 if ((err = pci_enable_device(pdev))) {
fa05e1ad 2776 netif_err(nic, probe, nic->netdev, "Cannot enable PCI device, aborting\n");
1da177e4
LT		 2777 goto err_out_free_dev;
2778 }
2779
f26251eb 2780 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
fa05e1ad 2781 netif_err(nic, probe, nic->netdev, "Cannot find proper PCI device base address, aborting\n");
1da177e4
LT		 2782 err = -ENODEV;
2783 goto err_out_disable_pdev;
2784 }
2785
f26251eb 2786 if ((err = pci_request_regions(pdev, DRV_NAME))) {
fa05e1ad 2787 netif_err(nic, probe, nic->netdev, "Cannot obtain PCI resources, aborting\n");
1da177e4
LT		 2788 goto err_out_disable_pdev;
2789 }
2790
284901a9 2791 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
fa05e1ad 2792 netif_err(nic, probe, nic->netdev, "No usable DMA configuration, aborting\n");
1da177e4
LT		 2793 goto err_out_free_res;
2794 }
2795
1da177e4
LT		 2796 SET_NETDEV_DEV(netdev, &pdev->dev);
2797
27345bb6 2798 if (use_io)
fa05e1ad 2799 netif_info(nic, probe, nic->netdev, "using i/o access mode\n");
27345bb6
JB		 2800
2801 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
f26251eb 2802 if (!nic->csr) {
fa05e1ad 2803 netif_err(nic, probe, nic->netdev, "Cannot map device registers, aborting\n");
1da177e4
LT		 2804 err = -ENOMEM;
2805 goto err_out_free_res;
2806 }
2807
f26251eb 2808 if (ent->driver_data)
1da177e4
LT		 2809 nic->flags |= ich;
2810 else
2811 nic->flags &= ~ich;
2812
2813 e100_get_defaults(nic);
2814
1f53367d 2815 /* locks must be initialized before calling hw_reset */
1da177e4
LT		 2816 spin_lock_init(&nic->cb_lock);
2817 spin_lock_init(&nic->cmd_lock);
ac7c6669 2818 spin_lock_init(&nic->mdio_lock);
1da177e4
LT		 2819
2820 /* Reset the device before pci_set_master() in case device is in some
2821 * funky state and has an interrupt pending - hint: we don't have the
2822 * interrupt handler registered yet. */
2823 e100_hw_reset(nic);
2824
2825 pci_set_master(pdev);
2826
2827 init_timer(&nic->watchdog);
2828 nic->watchdog.function = e100_watchdog;
2829 nic->watchdog.data = (unsigned long)nic;
1da177e4 2830
c4028958 2831 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2acdb1e0 2832
f26251eb 2833 if ((err = e100_alloc(nic))) {
fa05e1ad 2834 netif_err(nic, probe, nic->netdev, "Cannot alloc driver memory, aborting\n");
1da177e4
LT		 2835 goto err_out_iounmap;
2836 }
2837
f26251eb 2838 if ((err = e100_eeprom_load(nic)))
1da177e4
LT		 2839 goto err_out_free;
2840
f92d8728
MC		 2841 e100_phy_init(nic);
2842
1da177e4 2843 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
a92dd923 2844 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
948cd43f
JB		 2845 if (!is_valid_ether_addr(netdev->perm_addr)) {
2846 if (!eeprom_bad_csum_allow) {
fa05e1ad 2847 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, aborting\n");
948cd43f
JB		 2848 err = -EAGAIN;
2849 goto err_out_free;
2850 } else {
fa05e1ad 2851 netif_err(nic, probe, nic->netdev, "Invalid MAC address from EEPROM, you MUST configure one.\n");
948cd43f 2852 }
1da177e4
LT		 2853 }
2854
2855 /* Wol magic packet can be enabled from eeprom */
f26251eb 2856 if ((nic->mac >= mac_82558_D101_A4) &&
bc79fc84 2857 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
1da177e4 2858 nic->flags |= wol_magic;
bc79fc84
RW		 2859 device_set_wakeup_enable(&pdev->dev, true);
2860 }
1da177e4 2861
6bdacb1a 2862 /* ack any pending wake events, disable PME */
e7272403 2863 pci_pme_active(pdev, false);
1da177e4
LT		 2864
2865 strcpy(netdev->name, "eth%d");
f26251eb 2866 if ((err = register_netdev(netdev))) {
fa05e1ad 2867 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
1da177e4
LT		 2868 goto err_out_free;
2869 }
98468efd
RO		 2870 nic->cbs_pool = pci_pool_create(netdev->name,
2871 nic->pdev,
211a0d94 2872 nic->params.cbs.max * sizeof(struct cb),
98468efd
RO		 2873 sizeof(u32),
2874 0);
fa05e1ad
JP		 2875 netif_info(nic, probe, nic->netdev,
2876 "addr 0x%llx, irq %d, MAC addr %pM\n",
2877 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2878 pdev->irq, netdev->dev_addr);
1da177e4
LT		 2879
2880 return 0;
2881
2882err_out_free:
2883 e100_free(nic);
2884err_out_iounmap:
27345bb6 2885 pci_iounmap(pdev, nic->csr);
1da177e4
LT		 2886err_out_free_res:
2887 pci_release_regions(pdev);
2888err_out_disable_pdev:
2889 pci_disable_device(pdev);
2890err_out_free_dev:
2891 pci_set_drvdata(pdev, NULL);
2892 free_netdev(netdev);
2893 return err;
2894}
2895
2896static void __devexit e100_remove(struct pci_dev *pdev)
2897{
2898 struct net_device *netdev = pci_get_drvdata(pdev);
2899
f26251eb 2900 if (netdev) {
1da177e4
LT		 2901 struct nic *nic = netdev_priv(netdev);
2902 unregister_netdev(netdev);
2903 e100_free(nic);
915e91d7 2904 pci_iounmap(pdev, nic->csr);
98468efd 2905 pci_pool_destroy(nic->cbs_pool);
1da177e4
LT		 2906 free_netdev(netdev);
2907 pci_release_regions(pdev);
2908 pci_disable_device(pdev);
2909 pci_set_drvdata(pdev, NULL);
2910 }
2911}
2912
b55de80e
BA		 2913#define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2914#define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2915#define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
ac7c992c 2916static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
1da177e4
LT		 2917{
2918 struct net_device *netdev = pci_get_drvdata(pdev);
2919 struct nic *nic = netdev_priv(netdev);
2920
824545e7 2921 if (netif_running(netdev))
f902283b 2922 e100_down(nic);
518d8338 2923 netif_device_detach(netdev);
a53a33da 2924
1da177e4 2925 pci_save_state(pdev);
e8e82b76
AK		 2926
2927 if ((nic->flags & wol_magic) | e100_asf(nic)) {
b55de80e
BA		 2928 /* enable reverse auto-negotiation */
2929 if (nic->phy == phy_82552_v) {
2930 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2931 E100_82552_SMARTSPEED);
2932
2933 mdio_write(netdev, nic->mii.phy_id,
2934 E100_82552_SMARTSPEED, smartspeed |
2935 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2936 }
ac7c992c 2937 *enable_wake = true;
e8e82b76 2938 } else {
ac7c992c 2939 *enable_wake = false;
e8e82b76 2940 }
975b366a 2941
8543da66 2942 pci_disable_device(pdev);
ac7c992c 2943}
1da177e4 2944
ac7c992c
TLSC		 2945static int __e100_power_off(struct pci_dev *pdev, bool wake)
2946{
6905b1f1 2947 if (wake)
ac7c992c 2948 return pci_prepare_to_sleep(pdev);
6905b1f1
RW		 2949
2950 pci_wake_from_d3(pdev, false);
2951 pci_set_power_state(pdev, PCI_D3hot);
2952
2953 return 0;
1da177e4
LT		 2954}
2955
f902283b 2956#ifdef CONFIG_PM
ac7c992c
TLSC		 2957static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2958{
2959 bool wake;
2960 __e100_shutdown(pdev, &wake);
2961 return __e100_power_off(pdev, wake);
2962}
2963
1da177e4
LT		 2964static int e100_resume(struct pci_dev *pdev)
2965{
2966 struct net_device *netdev = pci_get_drvdata(pdev);
2967 struct nic *nic = netdev_priv(netdev);
2968
975b366a 2969 pci_set_power_state(pdev, PCI_D0);
1da177e4 2970 pci_restore_state(pdev);
6bdacb1a 2971 /* ack any pending wake events, disable PME */
975b366a 2972 pci_enable_wake(pdev, 0, 0);
1da177e4 2973
4b512d26 2974 /* disable reverse auto-negotiation */
b55de80e
BA		 2975 if (nic->phy == phy_82552_v) {
2976 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2977 E100_82552_SMARTSPEED);
2978
2979 mdio_write(netdev, nic->mii.phy_id,
2980 E100_82552_SMARTSPEED,
2981 smartspeed & ~(E100_82552_REV_ANEG));
2982 }
2983
1da177e4 2984 netif_device_attach(netdev);
975b366a 2985 if (netif_running(netdev))
1da177e4
LT		 2986 e100_up(nic);
2987
2988 return 0;
2989}
975b366a 2990#endif /* CONFIG_PM */
1da177e4 2991
d18c3db5 2992static void e100_shutdown(struct pci_dev *pdev)
6bdacb1a 2993{
ac7c992c
TLSC		 2994 bool wake;
2995 __e100_shutdown(pdev, &wake);
2996 if (system_state == SYSTEM_POWER_OFF)
2997 __e100_power_off(pdev, wake);
6bdacb1a
MC		 2998}
2999
2cc30492
AK		 3000/* ------------------ PCI Error Recovery infrastructure -------------- */
3001/**
3002 * e100_io_error_detected - called when PCI error is detected.
3003 * @pdev: Pointer to PCI device
0a0863af 3004 * @state: The current pci connection state
2cc30492
AK		 3005 */
3006static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
3007{
3008 struct net_device *netdev = pci_get_drvdata(pdev);
bea3348e 3009 struct nic *nic = netdev_priv(netdev);
2cc30492 3010
2cc30492 3011 netif_device_detach(netdev);
ef681ce1
AD		 3012
3013 if (state == pci_channel_io_perm_failure)
3014 return PCI_ERS_RESULT_DISCONNECT;
3015
3016 if (netif_running(netdev))
3017 e100_down(nic);
b1d26f24 3018 pci_disable_device(pdev);
2cc30492
AK		 3019
3020 /* Request a slot reset. */
3021 return PCI_ERS_RESULT_NEED_RESET;
3022}
3023
3024/**
3025 * e100_io_slot_reset - called after the pci bus has been reset.
3026 * @pdev: Pointer to PCI device
3027 *
3028 * Restart the card from scratch.
3029 */
3030static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
3031{
3032 struct net_device *netdev = pci_get_drvdata(pdev);
3033 struct nic *nic = netdev_priv(netdev);
3034
3035 if (pci_enable_device(pdev)) {
fa05e1ad 3036 pr_err("Cannot re-enable PCI device after reset\n");
2cc30492
AK		 3037 return PCI_ERS_RESULT_DISCONNECT;
3038 }
3039 pci_set_master(pdev);
3040
3041 /* Only one device per card can do a reset */
3042 if (0 != PCI_FUNC(pdev->devfn))
3043 return PCI_ERS_RESULT_RECOVERED;
3044 e100_hw_reset(nic);
3045 e100_phy_init(nic);
3046
3047 return PCI_ERS_RESULT_RECOVERED;
3048}
3049
3050/**
3051 * e100_io_resume - resume normal operations
3052 * @pdev: Pointer to PCI device
3053 *
3054 * Resume normal operations after an error recovery
3055 * sequence has been completed.
3056 */
3057static void e100_io_resume(struct pci_dev *pdev)
3058{
3059 struct net_device *netdev = pci_get_drvdata(pdev);
3060 struct nic *nic = netdev_priv(netdev);
3061
3062 /* ack any pending wake events, disable PME */
3063 pci_enable_wake(pdev, 0, 0);
3064
3065 netif_device_attach(netdev);
3066 if (netif_running(netdev)) {
3067 e100_open(netdev);
3068 mod_timer(&nic->watchdog, jiffies);
3069 }
3070}
3071
3072static struct pci_error_handlers e100_err_handler = {
3073 .error_detected = e100_io_error_detected,
3074 .slot_reset = e100_io_slot_reset,
3075 .resume = e100_io_resume,
3076};
6bdacb1a 3077
1da177e4
LT		 3078static struct pci_driver e100_driver = {
3079 .name = DRV_NAME,
3080 .id_table = e100_id_table,
3081 .probe = e100_probe,
3082 .remove = __devexit_p(e100_remove),
e8e82b76 3083#ifdef CONFIG_PM
975b366a 3084 /* Power Management hooks */
1da177e4
LT		 3085 .suspend = e100_suspend,
3086 .resume = e100_resume,
3087#endif
05479938 3088 .shutdown = e100_shutdown,
2cc30492 3089 .err_handler = &e100_err_handler,
1da177e4
LT		 3090};
3091
3092static int __init e100_init_module(void)
3093{
f26251eb 3094 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
fa05e1ad
JP		 3095 pr_info("%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
3096 pr_info("%s\n", DRV_COPYRIGHT);
1da177e4 3097 }
29917620 3098 return pci_register_driver(&e100_driver);
1da177e4
LT		 3099}
3100
3101static void __exit e100_cleanup_module(void)
3102{
3103 pci_unregister_driver(&e100_driver);
3104}
3105
3106module_init(e100_init_module);
3107module_exit(e100_cleanup_module);
Linux kernel - Deliverables
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