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[PATCH] e1000: support ETHTOOL_GPERMADDR
[deliverable/linux.git] / drivers / net / e100.c
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1da177e4
LT		 1/*******************************************************************************
2
3
611494dc 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Recieve
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * Under typical operation, the receive unit (RU) is start once,
110 * and the controller happily fills RFDs as frames arrive. If
111 * replacement RFDs cannot be allocated, or the RU goes non-active,
112 * the RU must be restarted. Frame arrival generates an interrupt,
113 * and Rx indication and re-allocation happen in the same context,
114 * therefore no locking is required. A software-generated interrupt
115 * is generated from the watchdog to recover from a failed allocation
116 * senario where all Rx resources have been indicated and none re-
117 * placed.
118 *
119 * V. Miscellaneous
120 *
121 * VLAN offloading of tagging, stripping and filtering is not
122 * supported, but driver will accommodate the extra 4-byte VLAN tag
123 * for processing by upper layers. Tx/Rx Checksum offloading is not
124 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
125 * not supported (hardware limitation).
126 *
127 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
128 *
129 * Thanks to JC (jchapman@katalix.com) for helping with
130 * testing/troubleshooting the development driver.
131 *
132 * TODO:
133 * o several entry points race with dev->close
134 * o check for tx-no-resources/stop Q races with tx clean/wake Q
135 */
136
137#include <linux/config.h>
138#include <linux/module.h>
139#include <linux/moduleparam.h>
140#include <linux/kernel.h>
141#include <linux/types.h>
142#include <linux/slab.h>
143#include <linux/delay.h>
144#include <linux/init.h>
145#include <linux/pci.h>
1e7f0bd8 146#include <linux/dma-mapping.h>
1da177e4
LT		 147#include <linux/netdevice.h>
148#include <linux/etherdevice.h>
149#include <linux/mii.h>
150#include <linux/if_vlan.h>
151#include <linux/skbuff.h>
152#include <linux/ethtool.h>
153#include <linux/string.h>
154#include <asm/unaligned.h>
155
156
157#define DRV_NAME "e100"
158#define DRV_EXT "-NAPI"
611494dc 159#define DRV_VERSION "3.4.14-k2"DRV_EXT
1da177e4 160#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
042e2fb7 161#define DRV_COPYRIGHT "Copyright(c) 1999-2005 Intel Corporation"
1da177e4
LT		 162#define PFX DRV_NAME ": "
163
164#define E100_WATCHDOG_PERIOD (2 * HZ)
165#define E100_NAPI_WEIGHT 16
166
167MODULE_DESCRIPTION(DRV_DESCRIPTION);
168MODULE_AUTHOR(DRV_COPYRIGHT);
169MODULE_LICENSE("GPL");
170MODULE_VERSION(DRV_VERSION);
171
172static int debug = 3;
173module_param(debug, int, 0);
174MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
175#define DPRINTK(nlevel, klevel, fmt, args...) \
176 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
177 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
178 __FUNCTION__ , ## args))
179
180#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
181 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
182 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
183static struct pci_device_id e100_id_table[] = {
184 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
185 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
186 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
187 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
188 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
189 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
190 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
191 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
192 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
193 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
194 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
195 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
196 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
197 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
198 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
199 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
200 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
201 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
202 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
203 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
204 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
205 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
206 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
207 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
208 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
209 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
210 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
211 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
212 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
213 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
042e2fb7
MC		 214 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
215 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
216 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
217 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
218 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
1da177e4
LT		 219 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
220 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
221 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
222 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
223 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
042e2fb7 224 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
1da177e4
LT		 225 { 0, }
226};
227MODULE_DEVICE_TABLE(pci, e100_id_table);
228
229enum mac {
230 mac_82557_D100_A = 0,
231 mac_82557_D100_B = 1,
232 mac_82557_D100_C = 2,
233 mac_82558_D101_A4 = 4,
234 mac_82558_D101_B0 = 5,
235 mac_82559_D101M = 8,
236 mac_82559_D101S = 9,
237 mac_82550_D102 = 12,
238 mac_82550_D102_C = 13,
239 mac_82551_E = 14,
240 mac_82551_F = 15,
241 mac_82551_10 = 16,
242 mac_unknown = 0xFF,
243};
244
245enum phy {
246 phy_100a = 0x000003E0,
247 phy_100c = 0x035002A8,
248 phy_82555_tx = 0x015002A8,
249 phy_nsc_tx = 0x5C002000,
250 phy_82562_et = 0x033002A8,
251 phy_82562_em = 0x032002A8,
252 phy_82562_ek = 0x031002A8,
253 phy_82562_eh = 0x017002A8,
254 phy_unknown = 0xFFFFFFFF,
255};
256
257/* CSR (Control/Status Registers) */
258struct csr {
259 struct {
260 u8 status;
261 u8 stat_ack;
262 u8 cmd_lo;
263 u8 cmd_hi;
264 u32 gen_ptr;
265 } scb;
266 u32 port;
267 u16 flash_ctrl;
268 u8 eeprom_ctrl_lo;
269 u8 eeprom_ctrl_hi;
270 u32 mdi_ctrl;
271 u32 rx_dma_count;
272};
273
274enum scb_status {
275 rus_ready = 0x10,
276 rus_mask = 0x3C,
277};
278
1f53367d
MC		 279enum ru_state {
280 RU_SUSPENDED = 0,
281 RU_RUNNING = 1,
282 RU_UNINITIALIZED = -1,
283};
284
1da177e4
LT		 285enum scb_stat_ack {
286 stat_ack_not_ours = 0x00,
287 stat_ack_sw_gen = 0x04,
288 stat_ack_rnr = 0x10,
289 stat_ack_cu_idle = 0x20,
290 stat_ack_frame_rx = 0x40,
291 stat_ack_cu_cmd_done = 0x80,
292 stat_ack_not_present = 0xFF,
293 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
294 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
295};
296
297enum scb_cmd_hi {
298 irq_mask_none = 0x00,
299 irq_mask_all = 0x01,
300 irq_sw_gen = 0x02,
301};
302
303enum scb_cmd_lo {
304 cuc_nop = 0x00,
305 ruc_start = 0x01,
306 ruc_load_base = 0x06,
307 cuc_start = 0x10,
308 cuc_resume = 0x20,
309 cuc_dump_addr = 0x40,
310 cuc_dump_stats = 0x50,
311 cuc_load_base = 0x60,
312 cuc_dump_reset = 0x70,
313};
314
315enum cuc_dump {
316 cuc_dump_complete = 0x0000A005,
317 cuc_dump_reset_complete = 0x0000A007,
318};
319
320enum port {
321 software_reset = 0x0000,
322 selftest = 0x0001,
323 selective_reset = 0x0002,
324};
325
326enum eeprom_ctrl_lo {
327 eesk = 0x01,
328 eecs = 0x02,
329 eedi = 0x04,
330 eedo = 0x08,
331};
332
333enum mdi_ctrl {
334 mdi_write = 0x04000000,
335 mdi_read = 0x08000000,
336 mdi_ready = 0x10000000,
337};
338
339enum eeprom_op {
340 op_write = 0x05,
341 op_read = 0x06,
342 op_ewds = 0x10,
343 op_ewen = 0x13,
344};
345
346enum eeprom_offsets {
347 eeprom_cnfg_mdix = 0x03,
348 eeprom_id = 0x0A,
349 eeprom_config_asf = 0x0D,
350 eeprom_smbus_addr = 0x90,
351};
352
353enum eeprom_cnfg_mdix {
354 eeprom_mdix_enabled = 0x0080,
355};
356
357enum eeprom_id {
358 eeprom_id_wol = 0x0020,
359};
360
361enum eeprom_config_asf {
362 eeprom_asf = 0x8000,
363 eeprom_gcl = 0x4000,
364};
365
366enum cb_status {
367 cb_complete = 0x8000,
368 cb_ok = 0x2000,
369};
370
371enum cb_command {
372 cb_nop = 0x0000,
373 cb_iaaddr = 0x0001,
374 cb_config = 0x0002,
375 cb_multi = 0x0003,
376 cb_tx = 0x0004,
377 cb_ucode = 0x0005,
378 cb_dump = 0x0006,
379 cb_tx_sf = 0x0008,
380 cb_cid = 0x1f00,
381 cb_i = 0x2000,
382 cb_s = 0x4000,
383 cb_el = 0x8000,
384};
385
386struct rfd {
387 u16 status;
388 u16 command;
389 u32 link;
390 u32 rbd;
391 u16 actual_size;
392 u16 size;
393};
394
395struct rx {
396 struct rx *next, *prev;
397 struct sk_buff *skb;
398 dma_addr_t dma_addr;
399};
400
401#if defined(__BIG_ENDIAN_BITFIELD)
402#define X(a,b) b,a
403#else
404#define X(a,b) a,b
405#endif
406struct config {
407/*0*/ u8 X(byte_count:6, pad0:2);
408/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
409/*2*/ u8 adaptive_ifs;
410/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
411 term_write_cache_line:1), pad3:4);
412/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
413/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
414/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
415 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
416 rx_discard_overruns:1), rx_save_bad_frames:1);
417/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
418 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
419 tx_dynamic_tbd:1);
420/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
421/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
422 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
423/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
424 loopback:2);
425/*11*/ u8 X(linear_priority:3, pad11:5);
426/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
427/*13*/ u8 ip_addr_lo;
428/*14*/ u8 ip_addr_hi;
429/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
430 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
431 pad15_2:1), crs_or_cdt:1);
432/*16*/ u8 fc_delay_lo;
433/*17*/ u8 fc_delay_hi;
434/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
435 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
436/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
437 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
438 full_duplex_force:1), full_duplex_pin:1);
439/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
440/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
441/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
442 u8 pad_d102[9];
443};
444
445#define E100_MAX_MULTICAST_ADDRS 64
446struct multi {
447 u16 count;
448 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
449};
450
451/* Important: keep total struct u32-aligned */
452#define UCODE_SIZE 134
453struct cb {
454 u16 status;
455 u16 command;
456 u32 link;
457 union {
458 u8 iaaddr[ETH_ALEN];
459 u32 ucode[UCODE_SIZE];
460 struct config config;
461 struct multi multi;
462 struct {
463 u32 tbd_array;
464 u16 tcb_byte_count;
465 u8 threshold;
466 u8 tbd_count;
467 struct {
468 u32 buf_addr;
469 u16 size;
470 u16 eol;
471 } tbd;
472 } tcb;
473 u32 dump_buffer_addr;
474 } u;
475 struct cb *next, *prev;
476 dma_addr_t dma_addr;
477 struct sk_buff *skb;
478};
479
480enum loopback {
481 lb_none = 0, lb_mac = 1, lb_phy = 3,
482};
483
484struct stats {
485 u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
486 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
487 tx_multiple_collisions, tx_total_collisions;
488 u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
489 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
490 rx_short_frame_errors;
491 u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
492 u16 xmt_tco_frames, rcv_tco_frames;
493 u32 complete;
494};
495
496struct mem {
497 struct {
498 u32 signature;
499 u32 result;
500 } selftest;
501 struct stats stats;
502 u8 dump_buf[596];
503};
504
505struct param_range {
506 u32 min;
507 u32 max;
508 u32 count;
509};
510
511struct params {
512 struct param_range rfds;
513 struct param_range cbs;
514};
515
516struct nic {
517 /* Begin: frequently used values: keep adjacent for cache effect */
518 u32 msg_enable ____cacheline_aligned;
519 struct net_device *netdev;
520 struct pci_dev *pdev;
521
522 struct rx *rxs ____cacheline_aligned;
523 struct rx *rx_to_use;
524 struct rx *rx_to_clean;
525 struct rfd blank_rfd;
1f53367d 526 enum ru_state ru_running;
1da177e4
LT		 527
528 spinlock_t cb_lock ____cacheline_aligned;
529 spinlock_t cmd_lock;
530 struct csr __iomem *csr;
531 enum scb_cmd_lo cuc_cmd;
532 unsigned int cbs_avail;
533 struct cb *cbs;
534 struct cb *cb_to_use;
535 struct cb *cb_to_send;
536 struct cb *cb_to_clean;
537 u16 tx_command;
538 /* End: frequently used values: keep adjacent for cache effect */
539
540 enum {
541 ich = (1 << 0),
542 promiscuous = (1 << 1),
543 multicast_all = (1 << 2),
544 wol_magic = (1 << 3),
545 ich_10h_workaround = (1 << 4),
546 } flags ____cacheline_aligned;
547
548 enum mac mac;
549 enum phy phy;
550 struct params params;
551 struct net_device_stats net_stats;
552 struct timer_list watchdog;
553 struct timer_list blink_timer;
554 struct mii_if_info mii;
2acdb1e0 555 struct work_struct tx_timeout_task;
1da177e4
LT		 556 enum loopback loopback;
557
558 struct mem *mem;
559 dma_addr_t dma_addr;
560
561 dma_addr_t cbs_dma_addr;
562 u8 adaptive_ifs;
563 u8 tx_threshold;
564 u32 tx_frames;
565 u32 tx_collisions;
566 u32 tx_deferred;
567 u32 tx_single_collisions;
568 u32 tx_multiple_collisions;
569 u32 tx_fc_pause;
570 u32 tx_tco_frames;
571
572 u32 rx_fc_pause;
573 u32 rx_fc_unsupported;
574 u32 rx_tco_frames;
575 u32 rx_over_length_errors;
576
577 u8 rev_id;
578 u16 leds;
579 u16 eeprom_wc;
580 u16 eeprom[256];
581};
582
583static inline void e100_write_flush(struct nic *nic)
584{
585 /* Flush previous PCI writes through intermediate bridges
586 * by doing a benign read */
587 (void)readb(&nic->csr->scb.status);
588}
589
590static inline void e100_enable_irq(struct nic *nic)
591{
592 unsigned long flags;
593
594 spin_lock_irqsave(&nic->cmd_lock, flags);
595 writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
596 spin_unlock_irqrestore(&nic->cmd_lock, flags);
597 e100_write_flush(nic);
598}
599
600static inline void e100_disable_irq(struct nic *nic)
601{
602 unsigned long flags;
603
604 spin_lock_irqsave(&nic->cmd_lock, flags);
605 writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
606 spin_unlock_irqrestore(&nic->cmd_lock, flags);
607 e100_write_flush(nic);
608}
609
610static void e100_hw_reset(struct nic *nic)
611{
612 /* Put CU and RU into idle with a selective reset to get
613 * device off of PCI bus */
614 writel(selective_reset, &nic->csr->port);
615 e100_write_flush(nic); udelay(20);
616
617 /* Now fully reset device */
618 writel(software_reset, &nic->csr->port);
619 e100_write_flush(nic); udelay(20);
620
621 /* Mask off our interrupt line - it's unmasked after reset */
622 e100_disable_irq(nic);
623}
624
625static int e100_self_test(struct nic *nic)
626{
627 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
628
629 /* Passing the self-test is a pretty good indication
630 * that the device can DMA to/from host memory */
631
632 nic->mem->selftest.signature = 0;
633 nic->mem->selftest.result = 0xFFFFFFFF;
634
635 writel(selftest | dma_addr, &nic->csr->port);
636 e100_write_flush(nic);
637 /* Wait 10 msec for self-test to complete */
638 msleep(10);
639
640 /* Interrupts are enabled after self-test */
641 e100_disable_irq(nic);
642
643 /* Check results of self-test */
644 if(nic->mem->selftest.result != 0) {
645 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
646 nic->mem->selftest.result);
647 return -ETIMEDOUT;
648 }
649 if(nic->mem->selftest.signature == 0) {
650 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
651 return -ETIMEDOUT;
652 }
653
654 return 0;
655}
656
657static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
658{
659 u32 cmd_addr_data[3];
660 u8 ctrl;
661 int i, j;
662
663 /* Three cmds: write/erase enable, write data, write/erase disable */
664 cmd_addr_data[0] = op_ewen << (addr_len - 2);
665 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
666 cpu_to_le16(data);
667 cmd_addr_data[2] = op_ewds << (addr_len - 2);
668
669 /* Bit-bang cmds to write word to eeprom */
670 for(j = 0; j < 3; j++) {
671
672 /* Chip select */
673 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
674 e100_write_flush(nic); udelay(4);
675
676 for(i = 31; i >= 0; i--) {
677 ctrl = (cmd_addr_data[j] & (1 << i)) ?
678 eecs | eedi : eecs;
679 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
680 e100_write_flush(nic); udelay(4);
681
682 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
683 e100_write_flush(nic); udelay(4);
684 }
685 /* Wait 10 msec for cmd to complete */
686 msleep(10);
687
688 /* Chip deselect */
689 writeb(0, &nic->csr->eeprom_ctrl_lo);
690 e100_write_flush(nic); udelay(4);
691 }
692};
693
694/* General technique stolen from the eepro100 driver - very clever */
695static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
696{
697 u32 cmd_addr_data;
698 u16 data = 0;
699 u8 ctrl;
700 int i;
701
702 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
703
704 /* Chip select */
705 writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
706 e100_write_flush(nic); udelay(4);
707
708 /* Bit-bang to read word from eeprom */
709 for(i = 31; i >= 0; i--) {
710 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
711 writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
712 e100_write_flush(nic); udelay(4);
713
714 writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
715 e100_write_flush(nic); udelay(4);
716
717 /* Eeprom drives a dummy zero to EEDO after receiving
718 * complete address. Use this to adjust addr_len. */
719 ctrl = readb(&nic->csr->eeprom_ctrl_lo);
720 if(!(ctrl & eedo) && i > 16) {
721 *addr_len -= (i - 16);
722 i = 17;
723 }
724
725 data = (data << 1) | (ctrl & eedo ? 1 : 0);
726 }
727
728 /* Chip deselect */
729 writeb(0, &nic->csr->eeprom_ctrl_lo);
730 e100_write_flush(nic); udelay(4);
731
732 return le16_to_cpu(data);
733};
734
735/* Load entire EEPROM image into driver cache and validate checksum */
736static int e100_eeprom_load(struct nic *nic)
737{
738 u16 addr, addr_len = 8, checksum = 0;
739
740 /* Try reading with an 8-bit addr len to discover actual addr len */
741 e100_eeprom_read(nic, &addr_len, 0);
742 nic->eeprom_wc = 1 << addr_len;
743
744 for(addr = 0; addr < nic->eeprom_wc; addr++) {
745 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
746 if(addr < nic->eeprom_wc - 1)
747 checksum += cpu_to_le16(nic->eeprom[addr]);
748 }
749
750 /* The checksum, stored in the last word, is calculated such that
751 * the sum of words should be 0xBABA */
752 checksum = le16_to_cpu(0xBABA - checksum);
753 if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
754 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
755 return -EAGAIN;
756 }
757
758 return 0;
759}
760
761/* Save (portion of) driver EEPROM cache to device and update checksum */
762static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
763{
764 u16 addr, addr_len = 8, checksum = 0;
765
766 /* Try reading with an 8-bit addr len to discover actual addr len */
767 e100_eeprom_read(nic, &addr_len, 0);
768 nic->eeprom_wc = 1 << addr_len;
769
770 if(start + count >= nic->eeprom_wc)
771 return -EINVAL;
772
773 for(addr = start; addr < start + count; addr++)
774 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
775
776 /* The checksum, stored in the last word, is calculated such that
777 * the sum of words should be 0xBABA */
778 for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
779 checksum += cpu_to_le16(nic->eeprom[addr]);
780 nic->eeprom[nic->eeprom_wc - 1] = le16_to_cpu(0xBABA - checksum);
781 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
782 nic->eeprom[nic->eeprom_wc - 1]);
783
784 return 0;
785}
786
962082b6 787#define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
e6280f26 788#define E100_WAIT_SCB_FAST 20 /* delay like the old code */
1da177e4
LT		 789static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
790{
791 unsigned long flags;
792 unsigned int i;
793 int err = 0;
794
795 spin_lock_irqsave(&nic->cmd_lock, flags);
796
797 /* Previous command is accepted when SCB clears */
798 for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
799 if(likely(!readb(&nic->csr->scb.cmd_lo)))
800 break;
801 cpu_relax();
e6280f26 802 if(unlikely(i > E100_WAIT_SCB_FAST))
1da177e4
LT		 803 udelay(5);
804 }
805 if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
806 err = -EAGAIN;
807 goto err_unlock;
808 }
809
810 if(unlikely(cmd != cuc_resume))
811 writel(dma_addr, &nic->csr->scb.gen_ptr);
812 writeb(cmd, &nic->csr->scb.cmd_lo);
813
814err_unlock:
815 spin_unlock_irqrestore(&nic->cmd_lock, flags);
816
817 return err;
818}
819
820static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
821 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
822{
823 struct cb *cb;
824 unsigned long flags;
825 int err = 0;
826
827 spin_lock_irqsave(&nic->cb_lock, flags);
828
829 if(unlikely(!nic->cbs_avail)) {
830 err = -ENOMEM;
831 goto err_unlock;
832 }
833
834 cb = nic->cb_to_use;
835 nic->cb_to_use = cb->next;
836 nic->cbs_avail--;
837 cb->skb = skb;
838
839 if(unlikely(!nic->cbs_avail))
840 err = -ENOSPC;
841
842 cb_prepare(nic, cb, skb);
843
844 /* Order is important otherwise we'll be in a race with h/w:
845 * set S-bit in current first, then clear S-bit in previous. */
846 cb->command |= cpu_to_le16(cb_s);
847 wmb();
848 cb->prev->command &= cpu_to_le16(~cb_s);
849
850 while(nic->cb_to_send != nic->cb_to_use) {
851 if(unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
852 nic->cb_to_send->dma_addr))) {
853 /* Ok, here's where things get sticky. It's
854 * possible that we can't schedule the command
855 * because the controller is too busy, so
856 * let's just queue the command and try again
857 * when another command is scheduled. */
962082b6
MC		 858 if(err == -ENOSPC) {
859 //request a reset
860 schedule_work(&nic->tx_timeout_task);
861 }
1da177e4
LT		 862 break;
863 } else {
864 nic->cuc_cmd = cuc_resume;
865 nic->cb_to_send = nic->cb_to_send->next;
866 }
867 }
868
869err_unlock:
870 spin_unlock_irqrestore(&nic->cb_lock, flags);
871
872 return err;
873}
874
875static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
876{
877 u32 data_out = 0;
878 unsigned int i;
879
880 writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
881
882 for(i = 0; i < 100; i++) {
883 udelay(20);
884 if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
885 break;
886 }
887
888 DPRINTK(HW, DEBUG,
889 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
890 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
891 return (u16)data_out;
892}
893
894static int mdio_read(struct net_device *netdev, int addr, int reg)
895{
896 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
897}
898
899static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
900{
901 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
902}
903
904static void e100_get_defaults(struct nic *nic)
905{
685fac63
MC		 906 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
907 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
1da177e4
LT		 908
909 pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
910 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
911 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
912 if(nic->mac == mac_unknown)
913 nic->mac = mac_82557_D100_A;
914
915 nic->params.rfds = rfds;
916 nic->params.cbs = cbs;
917
918 /* Quadwords to DMA into FIFO before starting frame transmit */
919 nic->tx_threshold = 0xE0;
920
962082b6
MC		 921 /* no interrupt for every tx completion, delay = 256us if not 557*/
922 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
923 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
1da177e4
LT		 924
925 /* Template for a freshly allocated RFD */
926 nic->blank_rfd.command = cpu_to_le16(cb_el);
927 nic->blank_rfd.rbd = 0xFFFFFFFF;
928 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
929
930 /* MII setup */
931 nic->mii.phy_id_mask = 0x1F;
932 nic->mii.reg_num_mask = 0x1F;
933 nic->mii.dev = nic->netdev;
934 nic->mii.mdio_read = mdio_read;
935 nic->mii.mdio_write = mdio_write;
936}
937
938static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
939{
940 struct config *config = &cb->u.config;
941 u8 *c = (u8 *)config;
942
943 cb->command = cpu_to_le16(cb_config);
944
945 memset(config, 0, sizeof(struct config));
946
947 config->byte_count = 0x16; /* bytes in this struct */
948 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
949 config->direct_rx_dma = 0x1; /* reserved */
950 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
951 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
952 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
953 config->tx_underrun_retry = 0x3; /* # of underrun retries */
954 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
955 config->pad10 = 0x6;
956 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
957 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
958 config->ifs = 0x6; /* x16 = inter frame spacing */
959 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
960 config->pad15_1 = 0x1;
961 config->pad15_2 = 0x1;
962 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
963 config->fc_delay_hi = 0x40; /* time delay for fc frame */
964 config->tx_padding = 0x1; /* 1=pad short frames */
965 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
966 config->pad18 = 0x1;
967 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
968 config->pad20_1 = 0x1F;
969 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
970 config->pad21_1 = 0x5;
971
972 config->adaptive_ifs = nic->adaptive_ifs;
973 config->loopback = nic->loopback;
974
975 if(nic->mii.force_media && nic->mii.full_duplex)
976 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
977
978 if(nic->flags & promiscuous || nic->loopback) {
979 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
980 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
981 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
982 }
983
984 if(nic->flags & multicast_all)
985 config->multicast_all = 0x1; /* 1=accept, 0=no */
986
6bdacb1a
MC		 987 /* disable WoL when up */
988 if(netif_running(nic->netdev) || !(nic->flags & wol_magic))
1da177e4
LT		 989 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
990
991 if(nic->mac >= mac_82558_D101_A4) {
992 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
993 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
994 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
995 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
996 if(nic->mac >= mac_82559_D101M)
997 config->tno_intr = 0x1; /* TCO stats enable */
998 else
999 config->standard_stat_counter = 0x0;
1000 }
1001
1002 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1003 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1004 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1005 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1006 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1007 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1008}
1009
685fac63
MC		 1010/********************************************************/
1011/* Micro code for 8086:1229 Rev 8 */
1012/********************************************************/
1013
1014/* Parameter values for the D101M B-step */
1015#define D101M_CPUSAVER_TIMER_DWORD 78
1016#define D101M_CPUSAVER_BUNDLE_DWORD 65
1017#define D101M_CPUSAVER_MIN_SIZE_DWORD 126
1018
1019#define D101M_B_RCVBUNDLE_UCODE \
1020{\
10210x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
10220x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
10230x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
10240x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
10250x00380438, 0x00000000, 0x00140000, 0x00380555, \
10260x00308000, 0x00100662, 0x00100561, 0x000E0408, \
10270x00134861, 0x000C0002, 0x00103093, 0x00308000, \
10280x00100624, 0x00100561, 0x000E0408, 0x00100861, \
10290x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
10300x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
10310x00000000, 0x00000000, 0x00000000, 0x00000000, \
10320x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
10330x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
10340x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
10350x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
10360x00041000, 0x00010004, 0x00130826, 0x000C0006, \
10370x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
10380x00000000, 0x00000000, 0x00000000, 0x00000000, \
10390x00000000, 0x00000000, 0x00000000, 0x00000000, \
10400x00080600, 0x00101B10, 0x00050004, 0x00100826, \
10410x00101210, 0x00380C34, 0x00000000, 0x00000000, \
10420x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
10430x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
10440x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
10450x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
10460x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
10470x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
10480x00130826, 0x000C0001, 0x00220559, 0x00101313, \
10490x00380559, 0x00000000, 0x00000000, 0x00000000, \
10500x00000000, 0x00000000, 0x00000000, 0x00000000, \
10510x00000000, 0x00130831, 0x0010090B, 0x00124813, \
10520x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
10530x003806A8, 0x00000000, 0x00000000, 0x00000000, \
1054}
1055
1056/********************************************************/
1057/* Micro code for 8086:1229 Rev 9 */
1058/********************************************************/
1059
1060/* Parameter values for the D101S */
1061#define D101S_CPUSAVER_TIMER_DWORD 78
1062#define D101S_CPUSAVER_BUNDLE_DWORD 67
1063#define D101S_CPUSAVER_MIN_SIZE_DWORD 128
1064
1065#define D101S_RCVBUNDLE_UCODE \
1066{\
10670x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
10680x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
10690x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
10700x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
10710x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
10720x00308000, 0x00100610, 0x00100561, 0x000E0408, \
10730x00134861, 0x000C0002, 0x00103093, 0x00308000, \
10740x00100624, 0x00100561, 0x000E0408, 0x00100861, \
10750x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
10760x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
10770x00000000, 0x00000000, 0x00000000, 0x00000000, \
10780x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
10790x003A047E, 0x00044010, 0x00380819, 0x00000000, \
10800x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
10810x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
10820x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
10830x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
10840x00101313, 0x00380700, 0x00000000, 0x00000000, \
10850x00000000, 0x00000000, 0x00000000, 0x00000000, \
10860x00080600, 0x00101B10, 0x00050004, 0x00100826, \
10870x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
10880x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
10890x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
10900x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
10910x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
10920x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
10930x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
10940x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
10950x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
10960x00000000, 0x00000000, 0x00000000, 0x00000000, \
10970x00000000, 0x00000000, 0x00000000, 0x00130831, \
10980x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
10990x00041000, 0x00010004, 0x00380700 \
1100}
1101
1102/********************************************************/
1103/* Micro code for the 8086:1229 Rev F/10 */
1104/********************************************************/
1105
1106/* Parameter values for the D102 E-step */
1107#define D102_E_CPUSAVER_TIMER_DWORD 42
1108#define D102_E_CPUSAVER_BUNDLE_DWORD 54
1109#define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
1110
1111#define D102_E_RCVBUNDLE_UCODE \
1112{\
11130x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x0EF70E36, 0x1FFF1FFF, \
11140x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
11150x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
11160x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
11170x00000000, 0x00000000, 0x00000000, 0x00000000, \
11180x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
11190x00000000, 0x00000000, 0x00000000, 0x00000000, \
11200x00000000, 0x00000000, 0x00000000, 0x00000000, \
11210x00000000, 0x00000000, 0x00000000, 0x00000000, \
11220x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
11230x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
11240x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
11250x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
11260x00300006, 0x00E014FB, 0x00000000, 0x00000000, \
11270x00000000, 0x00000000, 0x00000000, 0x00000000, \
11280x00000000, 0x00000000, 0x00000000, 0x00000000, \
11290x00000000, 0x00000000, 0x00000000, 0x00000000, \
11300x00906E41, 0x00800E3C, 0x00E00E39, 0x00000000, \
11310x00906EFD, 0x00900EFD, 0x00E00EF8, 0x00000000, \
11320x00000000, 0x00000000, 0x00000000, 0x00000000, \
11330x00000000, 0x00000000, 0x00000000, 0x00000000, \
11340x00000000, 0x00000000, 0x00000000, 0x00000000, \
11350x00000000, 0x00000000, 0x00000000, 0x00000000, \
11360x00000000, 0x00000000, 0x00000000, 0x00000000, \
11370x00000000, 0x00000000, 0x00000000, 0x00000000, \
11380x00000000, 0x00000000, 0x00000000, 0x00000000, \
11390x00000000, 0x00000000, 0x00000000, 0x00000000, \
11400x00000000, 0x00000000, 0x00000000, 0x00000000, \
11410x00000000, 0x00000000, 0x00000000, 0x00000000, \
11420x00000000, 0x00000000, 0x00000000, 0x00000000, \
11430x00000000, 0x00000000, 0x00000000, 0x00000000, \
11440x00000000, 0x00000000, 0x00000000, 0x00000000, \
11450x00000000, 0x00000000, 0x00000000, 0x00000000, \
1146}
1147
1da177e4
LT		 1148static void e100_load_ucode(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1149{
685fac63
MC		 1150/* *INDENT-OFF* */
1151 static struct {
1152 u32 ucode[UCODE_SIZE + 1];
1153 u8 mac;
1154 u8 timer_dword;
1155 u8 bundle_dword;
1156 u8 min_size_dword;
1157 } ucode_opts[] = {
1158 { D101M_B_RCVBUNDLE_UCODE,
1159 mac_82559_D101M,
1160 D101M_CPUSAVER_TIMER_DWORD,
1161 D101M_CPUSAVER_BUNDLE_DWORD,
1162 D101M_CPUSAVER_MIN_SIZE_DWORD },
1163 { D101S_RCVBUNDLE_UCODE,
1164 mac_82559_D101S,
1165 D101S_CPUSAVER_TIMER_DWORD,
1166 D101S_CPUSAVER_BUNDLE_DWORD,
1167 D101S_CPUSAVER_MIN_SIZE_DWORD },
1168 { D102_E_RCVBUNDLE_UCODE,
1169 mac_82551_F,
1170 D102_E_CPUSAVER_TIMER_DWORD,
1171 D102_E_CPUSAVER_BUNDLE_DWORD,
1172 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1173 { D102_E_RCVBUNDLE_UCODE,
1174 mac_82551_10,
1175 D102_E_CPUSAVER_TIMER_DWORD,
1176 D102_E_CPUSAVER_BUNDLE_DWORD,
1177 D102_E_CPUSAVER_MIN_SIZE_DWORD },
1178 { {0}, 0, 0, 0, 0}
1179 }, *opts;
1180/* *INDENT-ON* */
1181
1182#define BUNDLESMALL 1
1183#define BUNDLEMAX 50
1184#define INTDELAY 15000
1185
1186 opts = ucode_opts;
1187
1188 /* do not load u-code for ICH devices */
1189 if (nic->flags & ich)
1190 return;
1191
1192 /* Search for ucode match against h/w rev_id */
1193 while (opts->mac) {
1194 if (nic->mac == opts->mac) {
1195 int i;
1196 u32 *ucode = opts->ucode;
1197
1198 /* Insert user-tunable settings */
1199 ucode[opts->timer_dword] &= 0xFFFF0000;
1200 ucode[opts->timer_dword] |=
1201 (u16) INTDELAY;
1202 ucode[opts->bundle_dword] &= 0xFFFF0000;
1203 ucode[opts->bundle_dword] |= (u16) BUNDLEMAX;
1204 ucode[opts->min_size_dword] &= 0xFFFF0000;
1205 ucode[opts->min_size_dword] |=
1206 (BUNDLESMALL) ? 0xFFFF : 0xFF80;
1207
1208 for(i = 0; i < UCODE_SIZE; i++)
1209 cb->u.ucode[i] = cpu_to_le32(ucode[i]);
1210 cb->command = cpu_to_le16(cb_ucode);
1211 return;
1212 }
1213 opts++;
1214 }
1215
1216 cb->command = cpu_to_le16(cb_nop);
1da177e4
LT		 1217}
1218
1219static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1220 struct sk_buff *skb)
1221{
1222 cb->command = cpu_to_le16(cb_iaaddr);
1223 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1224}
1225
1226static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1227{
1228 cb->command = cpu_to_le16(cb_dump);
1229 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1230 offsetof(struct mem, dump_buf));
1231}
1232
1233#define NCONFIG_AUTO_SWITCH 0x0080
1234#define MII_NSC_CONG MII_RESV1
1235#define NSC_CONG_ENABLE 0x0100
1236#define NSC_CONG_TXREADY 0x0400
1237#define ADVERTISE_FC_SUPPORTED 0x0400
1238static int e100_phy_init(struct nic *nic)
1239{
1240 struct net_device *netdev = nic->netdev;
1241 u32 addr;
1242 u16 bmcr, stat, id_lo, id_hi, cong;
1243
1244 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1245 for(addr = 0; addr < 32; addr++) {
1246 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1247 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1248 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1249 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1250 if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1251 break;
1252 }
1253 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1254 if(addr == 32)
1255 return -EAGAIN;
1256
1257 /* Selected the phy and isolate the rest */
1258 for(addr = 0; addr < 32; addr++) {
1259 if(addr != nic->mii.phy_id) {
1260 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1261 } else {
1262 bmcr = mdio_read(netdev, addr, MII_BMCR);
1263 mdio_write(netdev, addr, MII_BMCR,
1264 bmcr & ~BMCR_ISOLATE);
1265 }
1266 }
1267
1268 /* Get phy ID */
1269 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1270 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1271 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1272 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1273
1274 /* Handle National tx phys */
1275#define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1276 if((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1277 /* Disable congestion control */
1278 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1279 cong |= NSC_CONG_TXREADY;
1280 cong &= ~NSC_CONG_ENABLE;
1281 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1282 }
1283
1284 if((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
64895145
MC		 1285 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000))) {
1286 /* enable/disable MDI/MDI-X auto-switching.
1287 MDI/MDI-X auto-switching is disabled for 82551ER/QM chips */
1288 if((nic->mac == mac_82551_E) || (nic->mac == mac_82551_F) ||
1289 (nic->mac == mac_82551_10) || (nic->mii.force_media) ||
1290 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))
1291 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, 0);
1292 else
1293 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG, NCONFIG_AUTO_SWITCH);
1294 }
1da177e4
LT		 1295
1296 return 0;
1297}
1298
1299static int e100_hw_init(struct nic *nic)
1300{
1301 int err;
1302
1303 e100_hw_reset(nic);
1304
1305 DPRINTK(HW, ERR, "e100_hw_init\n");
1306 if(!in_interrupt() && (err = e100_self_test(nic)))
1307 return err;
1308
1309 if((err = e100_phy_init(nic)))
1310 return err;
1311 if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1312 return err;
1313 if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1314 return err;
1315 if((err = e100_exec_cb(nic, NULL, e100_load_ucode)))
1316 return err;
1317 if((err = e100_exec_cb(nic, NULL, e100_configure)))
1318 return err;
1319 if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1320 return err;
1321 if((err = e100_exec_cmd(nic, cuc_dump_addr,
1322 nic->dma_addr + offsetof(struct mem, stats))))
1323 return err;
1324 if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1325 return err;
1326
1327 e100_disable_irq(nic);
1328
1329 return 0;
1330}
1331
1332static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1333{
1334 struct net_device *netdev = nic->netdev;
1335 struct dev_mc_list *list = netdev->mc_list;
1336 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1337
1338 cb->command = cpu_to_le16(cb_multi);
1339 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1340 for(i = 0; list && i < count; i++, list = list->next)
1341 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1342 ETH_ALEN);
1343}
1344
1345static void e100_set_multicast_list(struct net_device *netdev)
1346{
1347 struct nic *nic = netdev_priv(netdev);
1348
1349 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1350 netdev->mc_count, netdev->flags);
1351
1352 if(netdev->flags & IFF_PROMISC)
1353 nic->flags |= promiscuous;
1354 else
1355 nic->flags &= ~promiscuous;
1356
1357 if(netdev->flags & IFF_ALLMULTI ||
1358 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1359 nic->flags |= multicast_all;
1360 else
1361 nic->flags &= ~multicast_all;
1362
1363 e100_exec_cb(nic, NULL, e100_configure);
1364 e100_exec_cb(nic, NULL, e100_multi);
1365}
1366
1367static void e100_update_stats(struct nic *nic)
1368{
1369 struct net_device_stats *ns = &nic->net_stats;
1370 struct stats *s = &nic->mem->stats;
1371 u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1372 (nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
1373 &s->complete;
1374
1375 /* Device's stats reporting may take several microseconds to
1376 * complete, so where always waiting for results of the
1377 * previous command. */
1378
1379 if(*complete == le32_to_cpu(cuc_dump_reset_complete)) {
1380 *complete = 0;
1381 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1382 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1383 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1384 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1385 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1386 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1387 ns->collisions += nic->tx_collisions;
1388 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1389 le32_to_cpu(s->tx_lost_crs);
1390 ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
1391 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1392 nic->rx_over_length_errors;
1393 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1394 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1395 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1396 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1397 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1398 le32_to_cpu(s->rx_alignment_errors) +
1399 le32_to_cpu(s->rx_short_frame_errors) +
1400 le32_to_cpu(s->rx_cdt_errors);
1401 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1402 nic->tx_single_collisions +=
1403 le32_to_cpu(s->tx_single_collisions);
1404 nic->tx_multiple_collisions +=
1405 le32_to_cpu(s->tx_multiple_collisions);
1406 if(nic->mac >= mac_82558_D101_A4) {
1407 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1408 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1409 nic->rx_fc_unsupported +=
1410 le32_to_cpu(s->fc_rcv_unsupported);
1411 if(nic->mac >= mac_82559_D101M) {
1412 nic->tx_tco_frames +=
1413 le16_to_cpu(s->xmt_tco_frames);
1414 nic->rx_tco_frames +=
1415 le16_to_cpu(s->rcv_tco_frames);
1416 }
1417 }
1418 }
1419
1f53367d
MC		 1420
1421 if(e100_exec_cmd(nic, cuc_dump_reset, 0))
1422 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1da177e4
LT		 1423}
1424
1425static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1426{
1427 /* Adjust inter-frame-spacing (IFS) between two transmits if
1428 * we're getting collisions on a half-duplex connection. */
1429
1430 if(duplex == DUPLEX_HALF) {
1431 u32 prev = nic->adaptive_ifs;
1432 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1433
1434 if((nic->tx_frames / 32 < nic->tx_collisions) &&
1435 (nic->tx_frames > min_frames)) {
1436 if(nic->adaptive_ifs < 60)
1437 nic->adaptive_ifs += 5;
1438 } else if (nic->tx_frames < min_frames) {
1439 if(nic->adaptive_ifs >= 5)
1440 nic->adaptive_ifs -= 5;
1441 }
1442 if(nic->adaptive_ifs != prev)
1443 e100_exec_cb(nic, NULL, e100_configure);
1444 }
1445}
1446
1447static void e100_watchdog(unsigned long data)
1448{
1449 struct nic *nic = (struct nic *)data;
1450 struct ethtool_cmd cmd;
1451
1452 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1453
1454 /* mii library handles link maintenance tasks */
1455
1456 mii_ethtool_gset(&nic->mii, &cmd);
1457
1458 if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1459 DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
1460 cmd.speed == SPEED_100 ? "100" : "10",
1461 cmd.duplex == DUPLEX_FULL ? "full" : "half");
1462 } else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1463 DPRINTK(LINK, INFO, "link down\n");
1464 }
1465
1466 mii_check_link(&nic->mii);
1467
1468 /* Software generated interrupt to recover from (rare) Rx
1469 * allocation failure.
1470 * Unfortunately have to use a spinlock to not re-enable interrupts
1471 * accidentally, due to hardware that shares a register between the
1472 * interrupt mask bit and the SW Interrupt generation bit */
1473 spin_lock_irq(&nic->cmd_lock);
1474 writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1475 spin_unlock_irq(&nic->cmd_lock);
1476 e100_write_flush(nic);
1477
1478 e100_update_stats(nic);
1479 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1480
1481 if(nic->mac <= mac_82557_D100_C)
1482 /* Issue a multicast command to workaround a 557 lock up */
1483 e100_set_multicast_list(nic->netdev);
1484
1485 if(nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1486 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1487 nic->flags |= ich_10h_workaround;
1488 else
1489 nic->flags &= ~ich_10h_workaround;
1490
1491 mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
1492}
1493
1494static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1495 struct sk_buff *skb)
1496{
1497 cb->command = nic->tx_command;
962082b6 1498 /* interrupt every 16 packets regardless of delay */
996ec353
MC		 1499 if((nic->cbs_avail & ~15) == nic->cbs_avail)
1500 cb->command |= cpu_to_le16(cb_i);
1da177e4
LT		 1501 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1502 cb->u.tcb.tcb_byte_count = 0;
1503 cb->u.tcb.threshold = nic->tx_threshold;
1504 cb->u.tcb.tbd_count = 1;
1505 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1506 skb->data, skb->len, PCI_DMA_TODEVICE));
611494dc 1507 /* check for mapping failure? */
1da177e4
LT		 1508 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1509}
1510
1511static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1512{
1513 struct nic *nic = netdev_priv(netdev);
1514 int err;
1515
1516 if(nic->flags & ich_10h_workaround) {
1517 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1518 Issue a NOP command followed by a 1us delay before
1519 issuing the Tx command. */
1f53367d
MC		 1520 if(e100_exec_cmd(nic, cuc_nop, 0))
1521 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1da177e4
LT		 1522 udelay(1);
1523 }
1524
1525 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1526
1527 switch(err) {
1528 case -ENOSPC:
1529 /* We queued the skb, but now we're out of space. */
1530 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1531 netif_stop_queue(netdev);
1532 break;
1533 case -ENOMEM:
1534 /* This is a hard error - log it. */
1535 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1536 netif_stop_queue(netdev);
1537 return 1;
1538 }
1539
1540 netdev->trans_start = jiffies;
1541 return 0;
1542}
1543
1544static inline int e100_tx_clean(struct nic *nic)
1545{
1546 struct cb *cb;
1547 int tx_cleaned = 0;
1548
1549 spin_lock(&nic->cb_lock);
1550
1551 DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
1552 nic->cb_to_clean->status);
1553
1554 /* Clean CBs marked complete */
1555 for(cb = nic->cb_to_clean;
1556 cb->status & cpu_to_le16(cb_complete);
1557 cb = nic->cb_to_clean = cb->next) {
1558 if(likely(cb->skb != NULL)) {
1559 nic->net_stats.tx_packets++;
1560 nic->net_stats.tx_bytes += cb->skb->len;
1561
1562 pci_unmap_single(nic->pdev,
1563 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1564 le16_to_cpu(cb->u.tcb.tbd.size),
1565 PCI_DMA_TODEVICE);
1566 dev_kfree_skb_any(cb->skb);
1567 cb->skb = NULL;
1568 tx_cleaned = 1;
1569 }
1570 cb->status = 0;
1571 nic->cbs_avail++;
1572 }
1573
1574 spin_unlock(&nic->cb_lock);
1575
1576 /* Recover from running out of Tx resources in xmit_frame */
1577 if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1578 netif_wake_queue(nic->netdev);
1579
1580 return tx_cleaned;
1581}
1582
1583static void e100_clean_cbs(struct nic *nic)
1584{
1585 if(nic->cbs) {
1586 while(nic->cbs_avail != nic->params.cbs.count) {
1587 struct cb *cb = nic->cb_to_clean;
1588 if(cb->skb) {
1589 pci_unmap_single(nic->pdev,
1590 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1591 le16_to_cpu(cb->u.tcb.tbd.size),
1592 PCI_DMA_TODEVICE);
1593 dev_kfree_skb(cb->skb);
1594 }
1595 nic->cb_to_clean = nic->cb_to_clean->next;
1596 nic->cbs_avail++;
1597 }
1598 pci_free_consistent(nic->pdev,
1599 sizeof(struct cb) * nic->params.cbs.count,
1600 nic->cbs, nic->cbs_dma_addr);
1601 nic->cbs = NULL;
1602 nic->cbs_avail = 0;
1603 }
1604 nic->cuc_cmd = cuc_start;
1605 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1606 nic->cbs;
1607}
1608
1609static int e100_alloc_cbs(struct nic *nic)
1610{
1611 struct cb *cb;
1612 unsigned int i, count = nic->params.cbs.count;
1613
1614 nic->cuc_cmd = cuc_start;
1615 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1616 nic->cbs_avail = 0;
1617
1618 nic->cbs = pci_alloc_consistent(nic->pdev,
1619 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1620 if(!nic->cbs)
1621 return -ENOMEM;
1622
1623 for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
1624 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1625 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1626
1627 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1628 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1629 ((i+1) % count) * sizeof(struct cb));
1630 cb->skb = NULL;
1631 }
1632
1633 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1634 nic->cbs_avail = count;
1635
1636 return 0;
1637}
1638
1f53367d 1639static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1da177e4 1640{
1f53367d
MC		 1641 if(!nic->rxs) return;
1642 if(RU_SUSPENDED != nic->ru_running) return;
1643
1644 /* handle init time starts */
1645 if(!rx) rx = nic->rxs;
1646
1da177e4 1647 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1f53367d
MC		 1648 if(rx->skb) {
1649 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1650 nic->ru_running = RU_RUNNING;
1da177e4
LT		 1651 }
1652}
1653
1654#define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1655static inline int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1656{
1657 if(!(rx->skb = dev_alloc_skb(RFD_BUF_LEN + NET_IP_ALIGN)))
1658 return -ENOMEM;
1659
1660 /* Align, init, and map the RFD. */
1661 rx->skb->dev = nic->netdev;
1662 skb_reserve(rx->skb, NET_IP_ALIGN);
1663 memcpy(rx->skb->data, &nic->blank_rfd, sizeof(struct rfd));
1664 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1665 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1666
1f53367d
MC		 1667 if(pci_dma_mapping_error(rx->dma_addr)) {
1668 dev_kfree_skb_any(rx->skb);
1669 rx->skb = 0;
1670 rx->dma_addr = 0;
1671 return -ENOMEM;
1672 }
1673
1da177e4
LT		 1674 /* Link the RFD to end of RFA by linking previous RFD to
1675 * this one, and clearing EL bit of previous. */
1676 if(rx->prev->skb) {
1677 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1678 put_unaligned(cpu_to_le32(rx->dma_addr),
1679 (u32 *)&prev_rfd->link);
1680 wmb();
1681 prev_rfd->command &= ~cpu_to_le16(cb_el);
1682 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1683 sizeof(struct rfd), PCI_DMA_TODEVICE);
1684 }
1685
1686 return 0;
1687}
1688
1689static inline int e100_rx_indicate(struct nic *nic, struct rx *rx,
1690 unsigned int *work_done, unsigned int work_to_do)
1691{
1692 struct sk_buff *skb = rx->skb;
1693 struct rfd *rfd = (struct rfd *)skb->data;
1694 u16 rfd_status, actual_size;
1695
1696 if(unlikely(work_done && *work_done >= work_to_do))
1697 return -EAGAIN;
1698
1699 /* Need to sync before taking a peek at cb_complete bit */
1700 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1701 sizeof(struct rfd), PCI_DMA_FROMDEVICE);
1702 rfd_status = le16_to_cpu(rfd->status);
1703
1704 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1705
1706 /* If data isn't ready, nothing to indicate */
1707 if(unlikely(!(rfd_status & cb_complete)))
1f53367d 1708 return -ENODATA;
1da177e4
LT		 1709
1710 /* Get actual data size */
1711 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1712 if(unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1713 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1714
1715 /* Get data */
1716 pci_unmap_single(nic->pdev, rx->dma_addr,
1717 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1718
1f53367d
MC		 1719 /* this allows for a fast restart without re-enabling interrupts */
1720 if(le16_to_cpu(rfd->command) & cb_el)
1721 nic->ru_running = RU_SUSPENDED;
1722
1da177e4
LT		 1723 /* Pull off the RFD and put the actual data (minus eth hdr) */
1724 skb_reserve(skb, sizeof(struct rfd));
1725 skb_put(skb, actual_size);
1726 skb->protocol = eth_type_trans(skb, nic->netdev);
1727
1728 if(unlikely(!(rfd_status & cb_ok))) {
1729 /* Don't indicate if hardware indicates errors */
1730 nic->net_stats.rx_dropped++;
1731 dev_kfree_skb_any(skb);
136df52d 1732 } else if(actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1da177e4
LT		 1733 /* Don't indicate oversized frames */
1734 nic->rx_over_length_errors++;
1735 nic->net_stats.rx_dropped++;
1736 dev_kfree_skb_any(skb);
1737 } else {
1738 nic->net_stats.rx_packets++;
1739 nic->net_stats.rx_bytes += actual_size;
1740 nic->netdev->last_rx = jiffies;
1741 netif_receive_skb(skb);
1742 if(work_done)
1743 (*work_done)++;
1744 }
1745
1746 rx->skb = NULL;
1747
1748 return 0;
1749}
1750
1751static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1752 unsigned int work_to_do)
1753{
1754 struct rx *rx;
1f53367d
MC		 1755 int restart_required = 0;
1756 struct rx *rx_to_start = NULL;
1757
1758 /* are we already rnr? then pay attention!!! this ensures that
1759 * the state machine progression never allows a start with a
1760 * partially cleaned list, avoiding a race between hardware
1761 * and rx_to_clean when in NAPI mode */
1762 if(RU_SUSPENDED == nic->ru_running)
1763 restart_required = 1;
1da177e4
LT		 1764
1765 /* Indicate newly arrived packets */
1766 for(rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1f53367d
MC		 1767 int err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1768 if(-EAGAIN == err) {
1769 /* hit quota so have more work to do, restart once
1770 * cleanup is complete */
1771 restart_required = 0;
1772 break;
1773 } else if(-ENODATA == err)
1da177e4
LT		 1774 break; /* No more to clean */
1775 }
1776
1f53367d
MC		 1777 /* save our starting point as the place we'll restart the receiver */
1778 if(restart_required)
1779 rx_to_start = nic->rx_to_clean;
1780
1da177e4
LT		 1781 /* Alloc new skbs to refill list */
1782 for(rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1783 if(unlikely(e100_rx_alloc_skb(nic, rx)))
1784 break; /* Better luck next time (see watchdog) */
1785 }
1786
1f53367d
MC		 1787 if(restart_required) {
1788 // ack the rnr?
1789 writeb(stat_ack_rnr, &nic->csr->scb.stat_ack);
1790 e100_start_receiver(nic, rx_to_start);
1791 if(work_done)
1792 (*work_done)++;
1793 }
1da177e4
LT		 1794}
1795
1796static void e100_rx_clean_list(struct nic *nic)
1797{
1798 struct rx *rx;
1799 unsigned int i, count = nic->params.rfds.count;
1800
1f53367d
MC		 1801 nic->ru_running = RU_UNINITIALIZED;
1802
1da177e4
LT		 1803 if(nic->rxs) {
1804 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1805 if(rx->skb) {
1806 pci_unmap_single(nic->pdev, rx->dma_addr,
1807 RFD_BUF_LEN, PCI_DMA_FROMDEVICE);
1808 dev_kfree_skb(rx->skb);
1809 }
1810 }
1811 kfree(nic->rxs);
1812 nic->rxs = NULL;
1813 }
1814
1815 nic->rx_to_use = nic->rx_to_clean = NULL;
1da177e4
LT		 1816}
1817
1818static int e100_rx_alloc_list(struct nic *nic)
1819{
1820 struct rx *rx;
1821 unsigned int i, count = nic->params.rfds.count;
1822
1823 nic->rx_to_use = nic->rx_to_clean = NULL;
1f53367d 1824 nic->ru_running = RU_UNINITIALIZED;
1da177e4
LT		 1825
1826 if(!(nic->rxs = kmalloc(sizeof(struct rx) * count, GFP_ATOMIC)))
1827 return -ENOMEM;
1828 memset(nic->rxs, 0, sizeof(struct rx) * count);
1829
1830 for(rx = nic->rxs, i = 0; i < count; rx++, i++) {
1831 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1832 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1833 if(e100_rx_alloc_skb(nic, rx)) {
1834 e100_rx_clean_list(nic);
1835 return -ENOMEM;
1836 }
1837 }
1838
1839 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1f53367d 1840 nic->ru_running = RU_SUSPENDED;
1da177e4
LT		 1841
1842 return 0;
1843}
1844
1845static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
1846{
1847 struct net_device *netdev = dev_id;
1848 struct nic *nic = netdev_priv(netdev);
1849 u8 stat_ack = readb(&nic->csr->scb.stat_ack);
1850
1851 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1852
1853 if(stat_ack == stat_ack_not_ours || /* Not our interrupt */
1854 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1855 return IRQ_NONE;
1856
1857 /* Ack interrupt(s) */
1858 writeb(stat_ack, &nic->csr->scb.stat_ack);
1859
1860 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1861 if(stat_ack & stat_ack_rnr)
1f53367d 1862 nic->ru_running = RU_SUSPENDED;
1da177e4 1863
0685c31b
MC		 1864 if(likely(netif_rx_schedule_prep(netdev))) {
1865 e100_disable_irq(nic);
1866 __netif_rx_schedule(netdev);
1867 }
1da177e4
LT		 1868
1869 return IRQ_HANDLED;
1870}
1871
1872static int e100_poll(struct net_device *netdev, int *budget)
1873{
1874 struct nic *nic = netdev_priv(netdev);
1875 unsigned int work_to_do = min(netdev->quota, *budget);
1876 unsigned int work_done = 0;
1877 int tx_cleaned;
1878
1879 e100_rx_clean(nic, &work_done, work_to_do);
1880 tx_cleaned = e100_tx_clean(nic);
1881
1882 /* If no Rx and Tx cleanup work was done, exit polling mode. */
1883 if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
1884 netif_rx_complete(netdev);
1885 e100_enable_irq(nic);
1886 return 0;
1887 }
1888
1889 *budget -= work_done;
1890 netdev->quota -= work_done;
1891
1892 return 1;
1893}
1894
1895#ifdef CONFIG_NET_POLL_CONTROLLER
1896static void e100_netpoll(struct net_device *netdev)
1897{
1898 struct nic *nic = netdev_priv(netdev);
611494dc 1899
1da177e4
LT		 1900 e100_disable_irq(nic);
1901 e100_intr(nic->pdev->irq, netdev, NULL);
1902 e100_tx_clean(nic);
1903 e100_enable_irq(nic);
1904}
1905#endif
1906
1907static struct net_device_stats *e100_get_stats(struct net_device *netdev)
1908{
1909 struct nic *nic = netdev_priv(netdev);
1910 return &nic->net_stats;
1911}
1912
1913static int e100_set_mac_address(struct net_device *netdev, void *p)
1914{
1915 struct nic *nic = netdev_priv(netdev);
1916 struct sockaddr *addr = p;
1917
1918 if (!is_valid_ether_addr(addr->sa_data))
1919 return -EADDRNOTAVAIL;
1920
1921 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1922 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
1923
1924 return 0;
1925}
1926
1927static int e100_change_mtu(struct net_device *netdev, int new_mtu)
1928{
1929 if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
1930 return -EINVAL;
1931 netdev->mtu = new_mtu;
1932 return 0;
1933}
1934
6bdacb1a 1935#ifdef CONFIG_PM
1da177e4
LT		 1936static int e100_asf(struct nic *nic)
1937{
1938 /* ASF can be enabled from eeprom */
1939 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
1940 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
1941 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
1942 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
1943}
6bdacb1a 1944#endif
1da177e4
LT		 1945
1946static int e100_up(struct nic *nic)
1947{
1948 int err;
1949
1950 if((err = e100_rx_alloc_list(nic)))
1951 return err;
1952 if((err = e100_alloc_cbs(nic)))
1953 goto err_rx_clean_list;
1954 if((err = e100_hw_init(nic)))
1955 goto err_clean_cbs;
1956 e100_set_multicast_list(nic->netdev);
1f53367d 1957 e100_start_receiver(nic, 0);
1da177e4
LT		 1958 mod_timer(&nic->watchdog, jiffies);
1959 if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
1960 nic->netdev->name, nic->netdev)))
1961 goto err_no_irq;
1da177e4 1962 netif_wake_queue(nic->netdev);
0236ebb7
MC		 1963 netif_poll_enable(nic->netdev);
1964 /* enable ints _after_ enabling poll, preventing a race between
1965 * disable ints+schedule */
1966 e100_enable_irq(nic);
1da177e4
LT		 1967 return 0;
1968
1969err_no_irq:
1970 del_timer_sync(&nic->watchdog);
1971err_clean_cbs:
1972 e100_clean_cbs(nic);
1973err_rx_clean_list:
1974 e100_rx_clean_list(nic);
1975 return err;
1976}
1977
1978static void e100_down(struct nic *nic)
1979{
0236ebb7
MC		 1980 /* wait here for poll to complete */
1981 netif_poll_disable(nic->netdev);
1982 netif_stop_queue(nic->netdev);
1da177e4
LT		 1983 e100_hw_reset(nic);
1984 free_irq(nic->pdev->irq, nic->netdev);
1985 del_timer_sync(&nic->watchdog);
1986 netif_carrier_off(nic->netdev);
1da177e4
LT		 1987 e100_clean_cbs(nic);
1988 e100_rx_clean_list(nic);
1989}
1990
1991static void e100_tx_timeout(struct net_device *netdev)
1992{
1993 struct nic *nic = netdev_priv(netdev);
1994
2acdb1e0
MC		 1995 /* Reset outside of interrupt context, to avoid request_irq
1996 * in interrupt context */
1997 schedule_work(&nic->tx_timeout_task);
1998}
1999
2000static void e100_tx_timeout_task(struct net_device *netdev)
2001{
2002 struct nic *nic = netdev_priv(netdev);
2003
1da177e4
LT		 2004 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2005 readb(&nic->csr->scb.status));
2006 e100_down(netdev_priv(netdev));
2007 e100_up(netdev_priv(netdev));
2008}
2009
2010static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2011{
2012 int err;
2013 struct sk_buff *skb;
2014
2015 /* Use driver resources to perform internal MAC or PHY
2016 * loopback test. A single packet is prepared and transmitted
2017 * in loopback mode, and the test passes if the received
2018 * packet compares byte-for-byte to the transmitted packet. */
2019
2020 if((err = e100_rx_alloc_list(nic)))
2021 return err;
2022 if((err = e100_alloc_cbs(nic)))
2023 goto err_clean_rx;
2024
2025 /* ICH PHY loopback is broken so do MAC loopback instead */
2026 if(nic->flags & ich && loopback_mode == lb_phy)
2027 loopback_mode = lb_mac;
2028
2029 nic->loopback = loopback_mode;
2030 if((err = e100_hw_init(nic)))
2031 goto err_loopback_none;
2032
2033 if(loopback_mode == lb_phy)
2034 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2035 BMCR_LOOPBACK);
2036
1f53367d 2037 e100_start_receiver(nic, 0);
1da177e4
LT		 2038
2039 if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
2040 err = -ENOMEM;
2041 goto err_loopback_none;
2042 }
2043 skb_put(skb, ETH_DATA_LEN);
2044 memset(skb->data, 0xFF, ETH_DATA_LEN);
2045 e100_xmit_frame(skb, nic->netdev);
2046
2047 msleep(10);
2048
2049 if(memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2050 skb->data, ETH_DATA_LEN))
2051 err = -EAGAIN;
2052
2053err_loopback_none:
2054 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2055 nic->loopback = lb_none;
2056 e100_hw_init(nic);
2057 e100_clean_cbs(nic);
2058err_clean_rx:
2059 e100_rx_clean_list(nic);
2060 return err;
2061}
2062
2063#define MII_LED_CONTROL 0x1B
2064static void e100_blink_led(unsigned long data)
2065{
2066 struct nic *nic = (struct nic *)data;
2067 enum led_state {
2068 led_on = 0x01,
2069 led_off = 0x04,
2070 led_on_559 = 0x05,
2071 led_on_557 = 0x07,
2072 };
2073
2074 nic->leds = (nic->leds & led_on) ? led_off :
2075 (nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
2076 mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
2077 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2078}
2079
2080static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2081{
2082 struct nic *nic = netdev_priv(netdev);
2083 return mii_ethtool_gset(&nic->mii, cmd);
2084}
2085
2086static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2087{
2088 struct nic *nic = netdev_priv(netdev);
2089 int err;
2090
2091 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2092 err = mii_ethtool_sset(&nic->mii, cmd);
2093 e100_exec_cb(nic, NULL, e100_configure);
2094
2095 return err;
2096}
2097
2098static void e100_get_drvinfo(struct net_device *netdev,
2099 struct ethtool_drvinfo *info)
2100{
2101 struct nic *nic = netdev_priv(netdev);
2102 strcpy(info->driver, DRV_NAME);
2103 strcpy(info->version, DRV_VERSION);
2104 strcpy(info->fw_version, "N/A");
2105 strcpy(info->bus_info, pci_name(nic->pdev));
2106}
2107
2108static int e100_get_regs_len(struct net_device *netdev)
2109{
2110 struct nic *nic = netdev_priv(netdev);
2111#define E100_PHY_REGS 0x1C
2112#define E100_REGS_LEN 1 + E100_PHY_REGS + \
2113 sizeof(nic->mem->dump_buf) / sizeof(u32)
2114 return E100_REGS_LEN * sizeof(u32);
2115}
2116
2117static void e100_get_regs(struct net_device *netdev,
2118 struct ethtool_regs *regs, void *p)
2119{
2120 struct nic *nic = netdev_priv(netdev);
2121 u32 *buff = p;
2122 int i;
2123
2124 regs->version = (1 << 24) | nic->rev_id;
2125 buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
2126 readb(&nic->csr->scb.cmd_lo) << 16 |
2127 readw(&nic->csr->scb.status);
2128 for(i = E100_PHY_REGS; i >= 0; i--)
2129 buff[1 + E100_PHY_REGS - i] =
2130 mdio_read(netdev, nic->mii.phy_id, i);
2131 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2132 e100_exec_cb(nic, NULL, e100_dump);
2133 msleep(10);
2134 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2135 sizeof(nic->mem->dump_buf));
2136}
2137
2138static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2139{
2140 struct nic *nic = netdev_priv(netdev);
2141 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2142 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2143}
2144
2145static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2146{
2147 struct nic *nic = netdev_priv(netdev);
2148
2149 if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2150 return -EOPNOTSUPP;
2151
2152 if(wol->wolopts)
2153 nic->flags |= wol_magic;
2154 else
2155 nic->flags &= ~wol_magic;
2156
1da177e4
LT		 2157 e100_exec_cb(nic, NULL, e100_configure);
2158
2159 return 0;
2160}
2161
2162static u32 e100_get_msglevel(struct net_device *netdev)
2163{
2164 struct nic *nic = netdev_priv(netdev);
2165 return nic->msg_enable;
2166}
2167
2168static void e100_set_msglevel(struct net_device *netdev, u32 value)
2169{
2170 struct nic *nic = netdev_priv(netdev);
2171 nic->msg_enable = value;
2172}
2173
2174static int e100_nway_reset(struct net_device *netdev)
2175{
2176 struct nic *nic = netdev_priv(netdev);
2177 return mii_nway_restart(&nic->mii);
2178}
2179
2180static u32 e100_get_link(struct net_device *netdev)
2181{
2182 struct nic *nic = netdev_priv(netdev);
2183 return mii_link_ok(&nic->mii);
2184}
2185
2186static int e100_get_eeprom_len(struct net_device *netdev)
2187{
2188 struct nic *nic = netdev_priv(netdev);
2189 return nic->eeprom_wc << 1;
2190}
2191
2192#define E100_EEPROM_MAGIC 0x1234
2193static int e100_get_eeprom(struct net_device *netdev,
2194 struct ethtool_eeprom *eeprom, u8 *bytes)
2195{
2196 struct nic *nic = netdev_priv(netdev);
2197
2198 eeprom->magic = E100_EEPROM_MAGIC;
2199 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2200
2201 return 0;
2202}
2203
2204static int e100_set_eeprom(struct net_device *netdev,
2205 struct ethtool_eeprom *eeprom, u8 *bytes)
2206{
2207 struct nic *nic = netdev_priv(netdev);
2208
2209 if(eeprom->magic != E100_EEPROM_MAGIC)
2210 return -EINVAL;
2211
2212 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2213
2214 return e100_eeprom_save(nic, eeprom->offset >> 1,
2215 (eeprom->len >> 1) + 1);
2216}
2217
2218static void e100_get_ringparam(struct net_device *netdev,
2219 struct ethtool_ringparam *ring)
2220{
2221 struct nic *nic = netdev_priv(netdev);
2222 struct param_range *rfds = &nic->params.rfds;
2223 struct param_range *cbs = &nic->params.cbs;
2224
2225 ring->rx_max_pending = rfds->max;
2226 ring->tx_max_pending = cbs->max;
2227 ring->rx_mini_max_pending = 0;
2228 ring->rx_jumbo_max_pending = 0;
2229 ring->rx_pending = rfds->count;
2230 ring->tx_pending = cbs->count;
2231 ring->rx_mini_pending = 0;
2232 ring->rx_jumbo_pending = 0;
2233}
2234
2235static int e100_set_ringparam(struct net_device *netdev,
2236 struct ethtool_ringparam *ring)
2237{
2238 struct nic *nic = netdev_priv(netdev);
2239 struct param_range *rfds = &nic->params.rfds;
2240 struct param_range *cbs = &nic->params.cbs;
2241
2242 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2243 return -EINVAL;
2244
2245 if(netif_running(netdev))
2246 e100_down(nic);
2247 rfds->count = max(ring->rx_pending, rfds->min);
2248 rfds->count = min(rfds->count, rfds->max);
2249 cbs->count = max(ring->tx_pending, cbs->min);
2250 cbs->count = min(cbs->count, cbs->max);
2251 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2252 rfds->count, cbs->count);
2253 if(netif_running(netdev))
2254 e100_up(nic);
2255
2256 return 0;
2257}
2258
2259static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2260 "Link test (on/offline)",
2261 "Eeprom test (on/offline)",
2262 "Self test (offline)",
2263 "Mac loopback (offline)",
2264 "Phy loopback (offline)",
2265};
2266#define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
2267
2268static int e100_diag_test_count(struct net_device *netdev)
2269{
2270 return E100_TEST_LEN;
2271}
2272
2273static void e100_diag_test(struct net_device *netdev,
2274 struct ethtool_test *test, u64 *data)
2275{
2276 struct ethtool_cmd cmd;
2277 struct nic *nic = netdev_priv(netdev);
2278 int i, err;
2279
2280 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2281 data[0] = !mii_link_ok(&nic->mii);
2282 data[1] = e100_eeprom_load(nic);
2283 if(test->flags & ETH_TEST_FL_OFFLINE) {
2284
2285 /* save speed, duplex & autoneg settings */
2286 err = mii_ethtool_gset(&nic->mii, &cmd);
2287
2288 if(netif_running(netdev))
2289 e100_down(nic);
2290 data[2] = e100_self_test(nic);
2291 data[3] = e100_loopback_test(nic, lb_mac);
2292 data[4] = e100_loopback_test(nic, lb_phy);
2293
2294 /* restore speed, duplex & autoneg settings */
2295 err = mii_ethtool_sset(&nic->mii, &cmd);
2296
2297 if(netif_running(netdev))
2298 e100_up(nic);
2299 }
2300 for(i = 0; i < E100_TEST_LEN; i++)
2301 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
a074fb86
MC		 2302
2303 msleep_interruptible(4 * 1000);
1da177e4
LT		 2304}
2305
2306static int e100_phys_id(struct net_device *netdev, u32 data)
2307{
2308 struct nic *nic = netdev_priv(netdev);
2309
2310 if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2311 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2312 mod_timer(&nic->blink_timer, jiffies);
2313 msleep_interruptible(data * 1000);
2314 del_timer_sync(&nic->blink_timer);
2315 mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
2316
2317 return 0;
2318}
2319
2320static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2321 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2322 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2323 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2324 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2325 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2326 "tx_heartbeat_errors", "tx_window_errors",
2327 /* device-specific stats */
2328 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2329 "tx_flow_control_pause", "rx_flow_control_pause",
2330 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2331};
2332#define E100_NET_STATS_LEN 21
2333#define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
2334
2335static int e100_get_stats_count(struct net_device *netdev)
2336{
2337 return E100_STATS_LEN;
2338}
2339
2340static void e100_get_ethtool_stats(struct net_device *netdev,
2341 struct ethtool_stats *stats, u64 *data)
2342{
2343 struct nic *nic = netdev_priv(netdev);
2344 int i;
2345
2346 for(i = 0; i < E100_NET_STATS_LEN; i++)
2347 data[i] = ((unsigned long *)&nic->net_stats)[i];
2348
2349 data[i++] = nic->tx_deferred;
2350 data[i++] = nic->tx_single_collisions;
2351 data[i++] = nic->tx_multiple_collisions;
2352 data[i++] = nic->tx_fc_pause;
2353 data[i++] = nic->rx_fc_pause;
2354 data[i++] = nic->rx_fc_unsupported;
2355 data[i++] = nic->tx_tco_frames;
2356 data[i++] = nic->rx_tco_frames;
2357}
2358
2359static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2360{
2361 switch(stringset) {
2362 case ETH_SS_TEST:
2363 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2364 break;
2365 case ETH_SS_STATS:
2366 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2367 break;
2368 }
2369}
2370
2371static struct ethtool_ops e100_ethtool_ops = {
2372 .get_settings = e100_get_settings,
2373 .set_settings = e100_set_settings,
2374 .get_drvinfo = e100_get_drvinfo,
2375 .get_regs_len = e100_get_regs_len,
2376 .get_regs = e100_get_regs,
2377 .get_wol = e100_get_wol,
2378 .set_wol = e100_set_wol,
2379 .get_msglevel = e100_get_msglevel,
2380 .set_msglevel = e100_set_msglevel,
2381 .nway_reset = e100_nway_reset,
2382 .get_link = e100_get_link,
2383 .get_eeprom_len = e100_get_eeprom_len,
2384 .get_eeprom = e100_get_eeprom,
2385 .set_eeprom = e100_set_eeprom,
2386 .get_ringparam = e100_get_ringparam,
2387 .set_ringparam = e100_set_ringparam,
2388 .self_test_count = e100_diag_test_count,
2389 .self_test = e100_diag_test,
2390 .get_strings = e100_get_strings,
2391 .phys_id = e100_phys_id,
2392 .get_stats_count = e100_get_stats_count,
2393 .get_ethtool_stats = e100_get_ethtool_stats,
2394};
2395
2396static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2397{
2398 struct nic *nic = netdev_priv(netdev);
2399
2400 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2401}
2402
2403static int e100_alloc(struct nic *nic)
2404{
2405 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2406 &nic->dma_addr);
2407 return nic->mem ? 0 : -ENOMEM;
2408}
2409
2410static void e100_free(struct nic *nic)
2411{
2412 if(nic->mem) {
2413 pci_free_consistent(nic->pdev, sizeof(struct mem),
2414 nic->mem, nic->dma_addr);
2415 nic->mem = NULL;
2416 }
2417}
2418
2419static int e100_open(struct net_device *netdev)
2420{
2421 struct nic *nic = netdev_priv(netdev);
2422 int err = 0;
2423
2424 netif_carrier_off(netdev);
2425 if((err = e100_up(nic)))
2426 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2427 return err;
2428}
2429
2430static int e100_close(struct net_device *netdev)
2431{
2432 e100_down(netdev_priv(netdev));
2433 return 0;
2434}
2435
2436static int __devinit e100_probe(struct pci_dev *pdev,
2437 const struct pci_device_id *ent)
2438{
2439 struct net_device *netdev;
2440 struct nic *nic;
2441 int err;
2442
2443 if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2444 if(((1 << debug) - 1) & NETIF_MSG_PROBE)
2445 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2446 return -ENOMEM;
2447 }
2448
2449 netdev->open = e100_open;
2450 netdev->stop = e100_close;
2451 netdev->hard_start_xmit = e100_xmit_frame;
2452 netdev->get_stats = e100_get_stats;
2453 netdev->set_multicast_list = e100_set_multicast_list;
2454 netdev->set_mac_address = e100_set_mac_address;
2455 netdev->change_mtu = e100_change_mtu;
2456 netdev->do_ioctl = e100_do_ioctl;
2457 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2458 netdev->tx_timeout = e100_tx_timeout;
2459 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2460 netdev->poll = e100_poll;
2461 netdev->weight = E100_NAPI_WEIGHT;
2462#ifdef CONFIG_NET_POLL_CONTROLLER
2463 netdev->poll_controller = e100_netpoll;
2464#endif
2465 strcpy(netdev->name, pci_name(pdev));
2466
2467 nic = netdev_priv(netdev);
2468 nic->netdev = netdev;
2469 nic->pdev = pdev;
2470 nic->msg_enable = (1 << debug) - 1;
2471 pci_set_drvdata(pdev, netdev);
2472
2473 if((err = pci_enable_device(pdev))) {
2474 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2475 goto err_out_free_dev;
2476 }
2477
2478 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2479 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2480 "base address, aborting.\n");
2481 err = -ENODEV;
2482 goto err_out_disable_pdev;
2483 }
2484
2485 if((err = pci_request_regions(pdev, DRV_NAME))) {
2486 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2487 goto err_out_disable_pdev;
2488 }
2489
1e7f0bd8 2490 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4
LT		 2491 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2492 goto err_out_free_res;
2493 }
2494
2495 SET_MODULE_OWNER(netdev);
2496 SET_NETDEV_DEV(netdev, &pdev->dev);
2497
2498 nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
2499 if(!nic->csr) {
2500 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2501 err = -ENOMEM;
2502 goto err_out_free_res;
2503 }
2504
2505 if(ent->driver_data)
2506 nic->flags |= ich;
2507 else
2508 nic->flags &= ~ich;
2509
2510 e100_get_defaults(nic);
2511
1f53367d 2512 /* locks must be initialized before calling hw_reset */
1da177e4
LT		 2513 spin_lock_init(&nic->cb_lock);
2514 spin_lock_init(&nic->cmd_lock);
2515
2516 /* Reset the device before pci_set_master() in case device is in some
2517 * funky state and has an interrupt pending - hint: we don't have the
2518 * interrupt handler registered yet. */
2519 e100_hw_reset(nic);
2520
2521 pci_set_master(pdev);
2522
2523 init_timer(&nic->watchdog);
2524 nic->watchdog.function = e100_watchdog;
2525 nic->watchdog.data = (unsigned long)nic;
2526 init_timer(&nic->blink_timer);
2527 nic->blink_timer.function = e100_blink_led;
2528 nic->blink_timer.data = (unsigned long)nic;
2529
2acdb1e0
MC		 2530 INIT_WORK(&nic->tx_timeout_task,
2531 (void (*)(void *))e100_tx_timeout_task, netdev);
2532
1da177e4
LT		 2533 if((err = e100_alloc(nic))) {
2534 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2535 goto err_out_iounmap;
2536 }
2537
1da177e4
LT		 2538 if((err = e100_eeprom_load(nic)))
2539 goto err_out_free;
2540
f92d8728
MC		 2541 e100_phy_init(nic);
2542
1da177e4
LT		 2543 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2544 if(!is_valid_ether_addr(netdev->dev_addr)) {
2545 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2546 "EEPROM, aborting.\n");
2547 err = -EAGAIN;
2548 goto err_out_free;
2549 }
2550
2551 /* Wol magic packet can be enabled from eeprom */
2552 if((nic->mac >= mac_82558_D101_A4) &&
2553 (nic->eeprom[eeprom_id] & eeprom_id_wol))
2554 nic->flags |= wol_magic;
2555
6bdacb1a
MC		 2556 /* ack any pending wake events, disable PME */
2557 pci_enable_wake(pdev, 0, 0);
1da177e4
LT		 2558
2559 strcpy(netdev->name, "eth%d");
2560 if((err = register_netdev(netdev))) {
2561 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2562 goto err_out_free;
2563 }
2564
2565 DPRINTK(PROBE, INFO, "addr 0x%lx, irq %d, "
2566 "MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
2567 pci_resource_start(pdev, 0), pdev->irq,
2568 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
2569 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
2570
2571 return 0;
2572
2573err_out_free:
2574 e100_free(nic);
2575err_out_iounmap:
2576 iounmap(nic->csr);
2577err_out_free_res:
2578 pci_release_regions(pdev);
2579err_out_disable_pdev:
2580 pci_disable_device(pdev);
2581err_out_free_dev:
2582 pci_set_drvdata(pdev, NULL);
2583 free_netdev(netdev);
2584 return err;
2585}
2586
2587static void __devexit e100_remove(struct pci_dev *pdev)
2588{
2589 struct net_device *netdev = pci_get_drvdata(pdev);
2590
2591 if(netdev) {
2592 struct nic *nic = netdev_priv(netdev);
2593 unregister_netdev(netdev);
2594 e100_free(nic);
2595 iounmap(nic->csr);
2596 free_netdev(netdev);
2597 pci_release_regions(pdev);
2598 pci_disable_device(pdev);
2599 pci_set_drvdata(pdev, NULL);
2600 }
2601}
2602
2603#ifdef CONFIG_PM
2604static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2605{
2606 struct net_device *netdev = pci_get_drvdata(pdev);
2607 struct nic *nic = netdev_priv(netdev);
2608
2609 if(netif_running(netdev))
2610 e100_down(nic);
2611 e100_hw_reset(nic);
2612 netif_device_detach(netdev);
2613
2614 pci_save_state(pdev);
2615 pci_enable_wake(pdev, pci_choose_state(pdev, state), nic->flags & (wol_magic | e100_asf(nic)));
2616 pci_disable_device(pdev);
2617 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2618
2619 return 0;
2620}
2621
2622static int e100_resume(struct pci_dev *pdev)
2623{
2624 struct net_device *netdev = pci_get_drvdata(pdev);
2625 struct nic *nic = netdev_priv(netdev);
2626
2627 pci_set_power_state(pdev, PCI_D0);
2628 pci_restore_state(pdev);
6bdacb1a
MC		 2629 /* ack any pending wake events, disable PME */
2630 pci_enable_wake(pdev, 0, 0);
1f53367d
MC		 2631 if(e100_hw_init(nic))
2632 DPRINTK(HW, ERR, "e100_hw_init failed\n");
1da177e4
LT		 2633
2634 netif_device_attach(netdev);
2635 if(netif_running(netdev))
2636 e100_up(nic);
2637
2638 return 0;
2639}
2640#endif
2641
6bdacb1a 2642
d18c3db5 2643static void e100_shutdown(struct pci_dev *pdev)
6bdacb1a 2644{
6bdacb1a
MC		 2645 struct net_device *netdev = pci_get_drvdata(pdev);
2646 struct nic *nic = netdev_priv(netdev);
2647
2648#ifdef CONFIG_PM
2649 pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
2650#else
2651 pci_enable_wake(pdev, 0, nic->flags & (wol_magic));
2652#endif
2653}
2654
2655
1da177e4
LT		 2656static struct pci_driver e100_driver = {
2657 .name = DRV_NAME,
2658 .id_table = e100_id_table,
2659 .probe = e100_probe,
2660 .remove = __devexit_p(e100_remove),
2661#ifdef CONFIG_PM
2662 .suspend = e100_suspend,
2663 .resume = e100_resume,
2664#endif
d18c3db5 2665 .shutdown = e100_shutdown,
1da177e4
LT		 2666};
2667
2668static int __init e100_init_module(void)
2669{
2670 if(((1 << debug) - 1) & NETIF_MSG_DRV) {
2671 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2672 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2673 }
2674 return pci_module_init(&e100_driver);
2675}
2676
2677static void __exit e100_cleanup_module(void)
2678{
2679 pci_unregister_driver(&e100_driver);
2680}
2681
2682module_init(e100_init_module);
2683module_exit(e100_cleanup_module);
Linux kernel - Deliverables
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