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e1000: omit stats for broken counter in 82543
[deliverable/linux.git] / drivers / net / e1000 / e1000_hw.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
8fc897b0 33
1da177e4
LT		 34#include "e1000_hw.h"
35
35574764
NN		 36static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
37static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
38static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data);
39static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
40static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
41static void e1000_release_software_semaphore(struct e1000_hw *hw);
42
43static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
44static int32_t e1000_check_downshift(struct e1000_hw *hw);
45static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity);
46static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
47static void e1000_clear_vfta(struct e1000_hw *hw);
48static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
49static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
50static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
51static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
52static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
53static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
54static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
55static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
56static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
57static int32_t e1000_get_software_flag(struct e1000_hw *hw);
58static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
59static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
60static int32_t e1000_id_led_init(struct e1000_hw *hw);
61static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
62static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
63static void e1000_init_rx_addrs(struct e1000_hw *hw);
09ae3e88 64static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
35574764
NN		 65static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
66static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
67static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
68static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum);
69static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
70static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
71static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
72static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
73static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
74static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
75static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
76static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
77static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
78static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data);
79static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
80static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
81static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data);
82static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data);
83static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
84static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
85static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
86static void e1000_release_software_flag(struct e1000_hw *hw);
87static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
88static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
89static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
90static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
91static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
92static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
1da177e4
LT		 93static int32_t e1000_set_phy_type(struct e1000_hw *hw);
94static void e1000_phy_init_script(struct e1000_hw *hw);
95static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
96static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
97static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
98static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
99static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
100static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
101static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
102static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
103 uint16_t count);
104static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
105static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
106static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
107 uint16_t words, uint16_t *data);
108static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
109 uint16_t offset, uint16_t words,
110 uint16_t *data);
111static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
112static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
113static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
114static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
115 uint16_t count);
116static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
117 uint16_t phy_data);
118static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
119 uint16_t *phy_data);
120static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
121static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
122static void e1000_release_eeprom(struct e1000_hw *hw);
123static void e1000_standby_eeprom(struct e1000_hw *hw);
1da177e4
LT		 124static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
125static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
126static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
2d7edb92
MC		 127static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
128static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
cd94dd0b
AK		 129static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
130 uint16_t duplex);
6418ecc6 131static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
1da177e4
LT		 132
133/* IGP cable length table */
134static const
135uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
136 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
137 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
138 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
139 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
140 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
141 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
142 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
143 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
144
2d7edb92
MC		 145static const
146uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
868d5309
MC		 147 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
148 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
149 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
150 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
151 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
152 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
153 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
154 104, 109, 114, 118, 121, 124};
2d7edb92 155
1da177e4
LT		 156/******************************************************************************
157 * Set the phy type member in the hw struct.
158 *
159 * hw - Struct containing variables accessed by shared code
160 *****************************************************************************/
35574764 161static int32_t
1da177e4
LT		 162e1000_set_phy_type(struct e1000_hw *hw)
163{
164 DEBUGFUNC("e1000_set_phy_type");
165
8fc897b0 166 if (hw->mac_type == e1000_undefined)
2d7edb92
MC		 167 return -E1000_ERR_PHY_TYPE;
168
8fc897b0 169 switch (hw->phy_id) {
1da177e4
LT		 170 case M88E1000_E_PHY_ID:
171 case M88E1000_I_PHY_ID:
172 case M88E1011_I_PHY_ID:
2d7edb92 173 case M88E1111_I_PHY_ID:
1da177e4
LT		 174 hw->phy_type = e1000_phy_m88;
175 break;
176 case IGP01E1000_I_PHY_ID:
8fc897b0
AK		 177 if (hw->mac_type == e1000_82541 ||
178 hw->mac_type == e1000_82541_rev_2 ||
179 hw->mac_type == e1000_82547 ||
180 hw->mac_type == e1000_82547_rev_2) {
1da177e4
LT		 181 hw->phy_type = e1000_phy_igp;
182 break;
183 }
cd94dd0b
AK		 184 case IGP03E1000_E_PHY_ID:
185 hw->phy_type = e1000_phy_igp_3;
186 break;
187 case IFE_E_PHY_ID:
188 case IFE_PLUS_E_PHY_ID:
189 case IFE_C_E_PHY_ID:
190 hw->phy_type = e1000_phy_ife;
191 break;
6418ecc6
JK		 192 case GG82563_E_PHY_ID:
193 if (hw->mac_type == e1000_80003es2lan) {
194 hw->phy_type = e1000_phy_gg82563;
195 break;
196 }
1da177e4
LT		 197 /* Fall Through */
198 default:
199 /* Should never have loaded on this device */
200 hw->phy_type = e1000_phy_undefined;
201 return -E1000_ERR_PHY_TYPE;
202 }
203
204 return E1000_SUCCESS;
205}
206
207/******************************************************************************
208 * IGP phy init script - initializes the GbE PHY
209 *
210 * hw - Struct containing variables accessed by shared code
211 *****************************************************************************/
212static void
213e1000_phy_init_script(struct e1000_hw *hw)
214{
215 uint32_t ret_val;
216 uint16_t phy_saved_data;
217
218 DEBUGFUNC("e1000_phy_init_script");
219
8fc897b0 220 if (hw->phy_init_script) {
f8ec4733 221 msleep(20);
1da177e4
LT		 222
223 /* Save off the current value of register 0x2F5B to be restored at
224 * the end of this routine. */
225 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
226
227 /* Disabled the PHY transmitter */
228 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
229
f8ec4733 230 msleep(20);
1da177e4
LT		 231
232 e1000_write_phy_reg(hw,0x0000,0x0140);
233
f8ec4733 234 msleep(5);
1da177e4 235
8fc897b0 236 switch (hw->mac_type) {
1da177e4
LT		 237 case e1000_82541:
238 case e1000_82547:
239 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
240
241 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
242
243 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
244
245 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
246
247 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
248
249 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
250
251 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
252
253 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
254
255 e1000_write_phy_reg(hw, 0x2010, 0x0008);
256 break;
257
258 case e1000_82541_rev_2:
259 case e1000_82547_rev_2:
260 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
261 break;
262 default:
263 break;
264 }
265
266 e1000_write_phy_reg(hw, 0x0000, 0x3300);
267
f8ec4733 268 msleep(20);
1da177e4
LT		 269
270 /* Now enable the transmitter */
271 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
272
8fc897b0 273 if (hw->mac_type == e1000_82547) {
1da177e4
LT		 274 uint16_t fused, fine, coarse;
275
276 /* Move to analog registers page */
277 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
278
8fc897b0 279 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1da177e4
LT		 280 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
281
282 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
283 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
284
8fc897b0 285 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1da177e4
LT		 286 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
287 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
8fc897b0 288 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1da177e4
LT		 289 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
290
291 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
292 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
293 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
294
295 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
296 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
297 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
298 }
299 }
300 }
301}
302
303/******************************************************************************
304 * Set the mac type member in the hw struct.
305 *
306 * hw - Struct containing variables accessed by shared code
307 *****************************************************************************/
308int32_t
309e1000_set_mac_type(struct e1000_hw *hw)
310{
bd2371eb
JG		 311 DEBUGFUNC("e1000_set_mac_type");
312
313 switch (hw->device_id) {
314 case E1000_DEV_ID_82542:
315 switch (hw->revision_id) {
316 case E1000_82542_2_0_REV_ID:
317 hw->mac_type = e1000_82542_rev2_0;
318 break;
319 case E1000_82542_2_1_REV_ID:
320 hw->mac_type = e1000_82542_rev2_1;
321 break;
322 default:
323 /* Invalid 82542 revision ID */
324 return -E1000_ERR_MAC_TYPE;
325 }
326 break;
327 case E1000_DEV_ID_82543GC_FIBER:
328 case E1000_DEV_ID_82543GC_COPPER:
329 hw->mac_type = e1000_82543;
330 break;
331 case E1000_DEV_ID_82544EI_COPPER:
332 case E1000_DEV_ID_82544EI_FIBER:
333 case E1000_DEV_ID_82544GC_COPPER:
334 case E1000_DEV_ID_82544GC_LOM:
335 hw->mac_type = e1000_82544;
336 break;
337 case E1000_DEV_ID_82540EM:
338 case E1000_DEV_ID_82540EM_LOM:
339 case E1000_DEV_ID_82540EP:
340 case E1000_DEV_ID_82540EP_LOM:
341 case E1000_DEV_ID_82540EP_LP:
342 hw->mac_type = e1000_82540;
343 break;
344 case E1000_DEV_ID_82545EM_COPPER:
345 case E1000_DEV_ID_82545EM_FIBER:
346 hw->mac_type = e1000_82545;
347 break;
348 case E1000_DEV_ID_82545GM_COPPER:
349 case E1000_DEV_ID_82545GM_FIBER:
350 case E1000_DEV_ID_82545GM_SERDES:
351 hw->mac_type = e1000_82545_rev_3;
352 break;
353 case E1000_DEV_ID_82546EB_COPPER:
354 case E1000_DEV_ID_82546EB_FIBER:
355 case E1000_DEV_ID_82546EB_QUAD_COPPER:
356 hw->mac_type = e1000_82546;
357 break;
358 case E1000_DEV_ID_82546GB_COPPER:
359 case E1000_DEV_ID_82546GB_FIBER:
360 case E1000_DEV_ID_82546GB_SERDES:
361 case E1000_DEV_ID_82546GB_PCIE:
362 case E1000_DEV_ID_82546GB_QUAD_COPPER:
363 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
364 hw->mac_type = e1000_82546_rev_3;
365 break;
366 case E1000_DEV_ID_82541EI:
367 case E1000_DEV_ID_82541EI_MOBILE:
368 case E1000_DEV_ID_82541ER_LOM:
369 hw->mac_type = e1000_82541;
370 break;
371 case E1000_DEV_ID_82541ER:
372 case E1000_DEV_ID_82541GI:
373 case E1000_DEV_ID_82541GI_LF:
374 case E1000_DEV_ID_82541GI_MOBILE:
375 hw->mac_type = e1000_82541_rev_2;
376 break;
377 case E1000_DEV_ID_82547EI:
378 case E1000_DEV_ID_82547EI_MOBILE:
379 hw->mac_type = e1000_82547;
380 break;
381 case E1000_DEV_ID_82547GI:
382 hw->mac_type = e1000_82547_rev_2;
383 break;
384 case E1000_DEV_ID_82571EB_COPPER:
385 case E1000_DEV_ID_82571EB_FIBER:
386 case E1000_DEV_ID_82571EB_SERDES:
387 case E1000_DEV_ID_82571EB_QUAD_COPPER:
388 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
389 hw->mac_type = e1000_82571;
390 break;
391 case E1000_DEV_ID_82572EI_COPPER:
392 case E1000_DEV_ID_82572EI_FIBER:
393 case E1000_DEV_ID_82572EI_SERDES:
394 case E1000_DEV_ID_82572EI:
395 hw->mac_type = e1000_82572;
396 break;
397 case E1000_DEV_ID_82573E:
398 case E1000_DEV_ID_82573E_IAMT:
399 case E1000_DEV_ID_82573L:
400 hw->mac_type = e1000_82573;
401 break;
402 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
403 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
404 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
405 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
406 hw->mac_type = e1000_80003es2lan;
407 break;
408 case E1000_DEV_ID_ICH8_IGP_M_AMT:
409 case E1000_DEV_ID_ICH8_IGP_AMT:
410 case E1000_DEV_ID_ICH8_IGP_C:
411 case E1000_DEV_ID_ICH8_IFE:
412 case E1000_DEV_ID_ICH8_IFE_GT:
413 case E1000_DEV_ID_ICH8_IFE_G:
414 case E1000_DEV_ID_ICH8_IGP_M:
415 hw->mac_type = e1000_ich8lan;
416 break;
417 default:
418 /* Should never have loaded on this device */
419 return -E1000_ERR_MAC_TYPE;
420 }
421
422 switch (hw->mac_type) {
423 case e1000_ich8lan:
424 hw->swfwhw_semaphore_present = TRUE;
425 hw->asf_firmware_present = TRUE;
426 break;
427 case e1000_80003es2lan:
428 hw->swfw_sync_present = TRUE;
429 /* fall through */
430 case e1000_82571:
431 case e1000_82572:
432 case e1000_82573:
433 hw->eeprom_semaphore_present = TRUE;
434 /* fall through */
435 case e1000_82541:
436 case e1000_82547:
437 case e1000_82541_rev_2:
438 case e1000_82547_rev_2:
439 hw->asf_firmware_present = TRUE;
440 break;
441 default:
442 break;
443 }
444
167fb284
JG		 445 /* The 82543 chip does not count tx_carrier_errors properly in
446 * FD mode
447 */
448 if (hw->mac_type == e1000_82543)
449 hw->bad_tx_carr_stats_fd = TRUE;
450
bd2371eb 451 return E1000_SUCCESS;
1da177e4
LT		 452}
453
454/*****************************************************************************
455 * Set media type and TBI compatibility.
456 *
457 * hw - Struct containing variables accessed by shared code
458 * **************************************************************************/
459void
460e1000_set_media_type(struct e1000_hw *hw)
461{
462 uint32_t status;
463
464 DEBUGFUNC("e1000_set_media_type");
465
8fc897b0 466 if (hw->mac_type != e1000_82543) {
1da177e4
LT		 467 /* tbi_compatibility is only valid on 82543 */
468 hw->tbi_compatibility_en = FALSE;
469 }
470
471 switch (hw->device_id) {
472 case E1000_DEV_ID_82545GM_SERDES:
473 case E1000_DEV_ID_82546GB_SERDES:
868d5309
MC		 474 case E1000_DEV_ID_82571EB_SERDES:
475 case E1000_DEV_ID_82572EI_SERDES:
6418ecc6 476 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1da177e4
LT		 477 hw->media_type = e1000_media_type_internal_serdes;
478 break;
479 default:
3893d547
MC		 480 switch (hw->mac_type) {
481 case e1000_82542_rev2_0:
482 case e1000_82542_rev2_1:
483 hw->media_type = e1000_media_type_fiber;
484 break;
cd94dd0b 485 case e1000_ich8lan:
3893d547
MC		 486 case e1000_82573:
487 /* The STATUS_TBIMODE bit is reserved or reused for the this
488 * device.
489 */
490 hw->media_type = e1000_media_type_copper;
491 break;
492 default:
1da177e4 493 status = E1000_READ_REG(hw, STATUS);
3893d547 494 if (status & E1000_STATUS_TBIMODE) {
1da177e4
LT		 495 hw->media_type = e1000_media_type_fiber;
496 /* tbi_compatibility not valid on fiber */
497 hw->tbi_compatibility_en = FALSE;
498 } else {
499 hw->media_type = e1000_media_type_copper;
500 }
3893d547 501 break;
1da177e4
LT		 502 }
503 }
504}
505
506/******************************************************************************
507 * Reset the transmit and receive units; mask and clear all interrupts.
508 *
509 * hw - Struct containing variables accessed by shared code
510 *****************************************************************************/
511int32_t
512e1000_reset_hw(struct e1000_hw *hw)
513{
514 uint32_t ctrl;
515 uint32_t ctrl_ext;
516 uint32_t icr;
517 uint32_t manc;
518 uint32_t led_ctrl;
2d7edb92
MC		 519 uint32_t timeout;
520 uint32_t extcnf_ctrl;
521 int32_t ret_val;
1da177e4
LT		 522
523 DEBUGFUNC("e1000_reset_hw");
524
525 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
8fc897b0 526 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 527 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
528 e1000_pci_clear_mwi(hw);
529 }
530
8fc897b0 531 if (hw->bus_type == e1000_bus_type_pci_express) {
2d7edb92
MC		 532 /* Prevent the PCI-E bus from sticking if there is no TLP connection
533 * on the last TLP read/write transaction when MAC is reset.
534 */
8fc897b0 535 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
2d7edb92
MC		 536 DEBUGOUT("PCI-E Master disable polling has failed.\n");
537 }
538 }
539
1da177e4
LT		 540 /* Clear interrupt mask to stop board from generating interrupts */
541 DEBUGOUT("Masking off all interrupts\n");
542 E1000_WRITE_REG(hw, IMC, 0xffffffff);
543
544 /* Disable the Transmit and Receive units. Then delay to allow
545 * any pending transactions to complete before we hit the MAC with
546 * the global reset.
547 */
548 E1000_WRITE_REG(hw, RCTL, 0);
549 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
550 E1000_WRITE_FLUSH(hw);
551
552 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
553 hw->tbi_compatibility_on = FALSE;
554
555 /* Delay to allow any outstanding PCI transactions to complete before
556 * resetting the device
557 */
f8ec4733 558 msleep(10);
1da177e4
LT		 559
560 ctrl = E1000_READ_REG(hw, CTRL);
561
562 /* Must reset the PHY before resetting the MAC */
8fc897b0 563 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2d7edb92 564 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
f8ec4733 565 msleep(5);
1da177e4
LT		 566 }
567
2d7edb92
MC		 568 /* Must acquire the MDIO ownership before MAC reset.
569 * Ownership defaults to firmware after a reset. */
8fc897b0 570 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 571 timeout = 10;
572
573 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
574 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
575
576 do {
577 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
578 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
579
8fc897b0 580 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
2d7edb92
MC		 581 break;
582 else
583 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
584
f8ec4733 585 msleep(2);
2d7edb92 586 timeout--;
8fc897b0 587 } while (timeout);
2d7edb92
MC		 588 }
589
cd94dd0b
AK		 590 /* Workaround for ICH8 bit corruption issue in FIFO memory */
591 if (hw->mac_type == e1000_ich8lan) {
592 /* Set Tx and Rx buffer allocation to 8k apiece. */
593 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
594 /* Set Packet Buffer Size to 16k. */
595 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
596 }
597
1da177e4
LT		 598 /* Issue a global reset to the MAC. This will reset the chip's
599 * transmit, receive, DMA, and link units. It will not effect
600 * the current PCI configuration. The global reset bit is self-
601 * clearing, and should clear within a microsecond.
602 */
603 DEBUGOUT("Issuing a global reset to MAC\n");
604
8fc897b0 605 switch (hw->mac_type) {
1da177e4
LT		 606 case e1000_82544:
607 case e1000_82540:
608 case e1000_82545:
609 case e1000_82546:
610 case e1000_82541:
611 case e1000_82541_rev_2:
612 /* These controllers can't ack the 64-bit write when issuing the
613 * reset, so use IO-mapping as a workaround to issue the reset */
614 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
615 break;
616 case e1000_82545_rev_3:
617 case e1000_82546_rev_3:
618 /* Reset is performed on a shadow of the control register */
619 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
620 break;
cd94dd0b
AK		 621 case e1000_ich8lan:
622 if (!hw->phy_reset_disable &&
623 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
624 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
625 * at the same time to make sure the interface between
626 * MAC and the external PHY is reset.
627 */
628 ctrl |= E1000_CTRL_PHY_RST;
629 }
630
631 e1000_get_software_flag(hw);
632 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
f8ec4733 633 msleep(5);
cd94dd0b 634 break;
1da177e4
LT		 635 default:
636 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
637 break;
638 }
639
640 /* After MAC reset, force reload of EEPROM to restore power-on settings to
641 * device. Later controllers reload the EEPROM automatically, so just wait
642 * for reload to complete.
643 */
8fc897b0 644 switch (hw->mac_type) {
1da177e4
LT		 645 case e1000_82542_rev2_0:
646 case e1000_82542_rev2_1:
647 case e1000_82543:
648 case e1000_82544:
649 /* Wait for reset to complete */
650 udelay(10);
651 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
652 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
653 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
654 E1000_WRITE_FLUSH(hw);
655 /* Wait for EEPROM reload */
f8ec4733 656 msleep(2);
1da177e4
LT		 657 break;
658 case e1000_82541:
659 case e1000_82541_rev_2:
660 case e1000_82547:
661 case e1000_82547_rev_2:
662 /* Wait for EEPROM reload */
f8ec4733 663 msleep(20);
1da177e4 664 break;
2d7edb92 665 case e1000_82573:
fd803241
JK		 666 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
667 udelay(10);
668 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
669 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
670 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
671 E1000_WRITE_FLUSH(hw);
672 }
2d7edb92 673 /* fall through */
2a88c173
JK		 674 default:
675 /* Auto read done will delay 5ms or poll based on mac type */
2d7edb92 676 ret_val = e1000_get_auto_rd_done(hw);
8fc897b0 677 if (ret_val)
2d7edb92
MC		 678 return ret_val;
679 break;
1da177e4
LT		 680 }
681
682 /* Disable HW ARPs on ASF enabled adapters */
8fc897b0 683 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
1da177e4
LT		 684 manc = E1000_READ_REG(hw, MANC);
685 manc &= ~(E1000_MANC_ARP_EN);
686 E1000_WRITE_REG(hw, MANC, manc);
687 }
688
8fc897b0 689 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 690 e1000_phy_init_script(hw);
691
692 /* Configure activity LED after PHY reset */
693 led_ctrl = E1000_READ_REG(hw, LEDCTL);
694 led_ctrl &= IGP_ACTIVITY_LED_MASK;
695 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
696 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
697 }
698
699 /* Clear interrupt mask to stop board from generating interrupts */
700 DEBUGOUT("Masking off all interrupts\n");
701 E1000_WRITE_REG(hw, IMC, 0xffffffff);
702
703 /* Clear any pending interrupt events. */
704 icr = E1000_READ_REG(hw, ICR);
705
706 /* If MWI was previously enabled, reenable it. */
8fc897b0 707 if (hw->mac_type == e1000_82542_rev2_0) {
f8ec4733 708 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 709 e1000_pci_set_mwi(hw);
710 }
711
cd94dd0b
AK		 712 if (hw->mac_type == e1000_ich8lan) {
713 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
714 kab |= E1000_KABGTXD_BGSQLBIAS;
715 E1000_WRITE_REG(hw, KABGTXD, kab);
716 }
717
1da177e4
LT		 718 return E1000_SUCCESS;
719}
720
09ae3e88
JK		 721/******************************************************************************
722 *
723 * Initialize a number of hardware-dependent bits
724 *
725 * hw: Struct containing variables accessed by shared code
726 *
727 * This function contains hardware limitation workarounds for PCI-E adapters
728 *
729 *****************************************************************************/
730static void
731e1000_initialize_hardware_bits(struct e1000_hw *hw)
732{
733 if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
734 /* Settings common to all PCI-express silicon */
735 uint32_t reg_ctrl, reg_ctrl_ext;
736 uint32_t reg_tarc0, reg_tarc1;
737 uint32_t reg_tctl;
738 uint32_t reg_txdctl, reg_txdctl1;
739
740 /* link autonegotiation/sync workarounds */
741 reg_tarc0 = E1000_READ_REG(hw, TARC0);
742 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
743
744 /* Enable not-done TX descriptor counting */
745 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
746 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
747 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
748 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
749 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
750 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
751
752 switch (hw->mac_type) {
753 case e1000_82571:
754 case e1000_82572:
755 /* Clear PHY TX compatible mode bits */
756 reg_tarc1 = E1000_READ_REG(hw, TARC1);
757 reg_tarc1 &= ~((1 << 30)|(1 << 29));
758
759 /* link autonegotiation/sync workarounds */
760 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
761
762 /* TX ring control fixes */
763 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
764
765 /* Multiple read bit is reversed polarity */
766 reg_tctl = E1000_READ_REG(hw, TCTL);
767 if (reg_tctl & E1000_TCTL_MULR)
768 reg_tarc1 &= ~(1 << 28);
769 else
770 reg_tarc1 |= (1 << 28);
771
772 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
773 break;
774 case e1000_82573:
775 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
776 reg_ctrl_ext &= ~(1 << 23);
777 reg_ctrl_ext |= (1 << 22);
778
779 /* TX byte count fix */
780 reg_ctrl = E1000_READ_REG(hw, CTRL);
781 reg_ctrl &= ~(1 << 29);
782
783 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
784 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
785 break;
786 case e1000_80003es2lan:
787 /* improve small packet performace for fiber/serdes */
788 if ((hw->media_type == e1000_media_type_fiber) ||
789 (hw->media_type == e1000_media_type_internal_serdes)) {
790 reg_tarc0 &= ~(1 << 20);
791 }
792
793 /* Multiple read bit is reversed polarity */
794 reg_tctl = E1000_READ_REG(hw, TCTL);
795 reg_tarc1 = E1000_READ_REG(hw, TARC1);
796 if (reg_tctl & E1000_TCTL_MULR)
797 reg_tarc1 &= ~(1 << 28);
798 else
799 reg_tarc1 |= (1 << 28);
800
801 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
802 break;
803 case e1000_ich8lan:
804 /* Reduce concurrent DMA requests to 3 from 4 */
805 if ((hw->revision_id < 3) ||
806 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
807 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
808 reg_tarc0 |= ((1 << 29)|(1 << 28));
809
810 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
811 reg_ctrl_ext |= (1 << 22);
812 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
813
814 /* workaround TX hang with TSO=on */
815 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
816
817 /* Multiple read bit is reversed polarity */
818 reg_tctl = E1000_READ_REG(hw, TCTL);
819 reg_tarc1 = E1000_READ_REG(hw, TARC1);
820 if (reg_tctl & E1000_TCTL_MULR)
821 reg_tarc1 &= ~(1 << 28);
822 else
823 reg_tarc1 |= (1 << 28);
824
825 /* workaround TX hang with TSO=on */
826 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
827
828 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
829 break;
830 default:
831 break;
832 }
833
834 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
835 }
836}
837
1da177e4
LT		 838/******************************************************************************
839 * Performs basic configuration of the adapter.
840 *
841 * hw - Struct containing variables accessed by shared code
842 *
843 * Assumes that the controller has previously been reset and is in a
844 * post-reset uninitialized state. Initializes the receive address registers,
845 * multicast table, and VLAN filter table. Calls routines to setup link
846 * configuration and flow control settings. Clears all on-chip counters. Leaves
847 * the transmit and receive units disabled and uninitialized.
848 *****************************************************************************/
849int32_t
850e1000_init_hw(struct e1000_hw *hw)
851{
852 uint32_t ctrl;
853 uint32_t i;
854 int32_t ret_val;
855 uint16_t pcix_cmd_word;
856 uint16_t pcix_stat_hi_word;
857 uint16_t cmd_mmrbc;
858 uint16_t stat_mmrbc;
2d7edb92 859 uint32_t mta_size;
6418ecc6 860 uint32_t reg_data;
b7ee49db 861 uint32_t ctrl_ext;
2d7edb92 862
1da177e4
LT		 863 DEBUGFUNC("e1000_init_hw");
864
7820d428 865 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
09ae3e88
JK		 866 if ((hw->mac_type == e1000_ich8lan) &&
867 ((hw->revision_id < 3) ||
868 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
869 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
870 reg_data = E1000_READ_REG(hw, STATUS);
871 reg_data &= ~0x80000000;
872 E1000_WRITE_REG(hw, STATUS, reg_data);
7820d428
JK		 873 }
874
1da177e4
LT		 875 /* Initialize Identification LED */
876 ret_val = e1000_id_led_init(hw);
8fc897b0 877 if (ret_val) {
1da177e4
LT		 878 DEBUGOUT("Error Initializing Identification LED\n");
879 return ret_val;
880 }
881
882 /* Set the media type and TBI compatibility */
883 e1000_set_media_type(hw);
884
09ae3e88
JK		 885 /* Must be called after e1000_set_media_type because media_type is used */
886 e1000_initialize_hardware_bits(hw);
887
1da177e4
LT		 888 /* Disabling VLAN filtering. */
889 DEBUGOUT("Initializing the IEEE VLAN\n");
cd94dd0b
AK		 890 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
891 if (hw->mac_type != e1000_ich8lan) {
892 if (hw->mac_type < e1000_82545_rev_3)
893 E1000_WRITE_REG(hw, VET, 0);
894 e1000_clear_vfta(hw);
895 }
1da177e4
LT		 896
897 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
8fc897b0 898 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 899 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
900 e1000_pci_clear_mwi(hw);
901 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
902 E1000_WRITE_FLUSH(hw);
f8ec4733 903 msleep(5);
1da177e4
LT		 904 }
905
906 /* Setup the receive address. This involves initializing all of the Receive
907 * Address Registers (RARs 0 - 15).
908 */
909 e1000_init_rx_addrs(hw);
910
911 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
8fc897b0 912 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 913 E1000_WRITE_REG(hw, RCTL, 0);
914 E1000_WRITE_FLUSH(hw);
f8ec4733
JG		 915 msleep(1);
916 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 917 e1000_pci_set_mwi(hw);
918 }
919
920 /* Zero out the Multicast HASH table */
921 DEBUGOUT("Zeroing the MTA\n");
2d7edb92 922 mta_size = E1000_MC_TBL_SIZE;
cd94dd0b
AK		 923 if (hw->mac_type == e1000_ich8lan)
924 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
8fc897b0 925 for (i = 0; i < mta_size; i++) {
1da177e4 926 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 927 /* use write flush to prevent Memory Write Block (MWB) from
928 * occuring when accessing our register space */
929 E1000_WRITE_FLUSH(hw);
930 }
1da177e4
LT		 931
932 /* Set the PCI priority bit correctly in the CTRL register. This
933 * determines if the adapter gives priority to receives, or if it
2d7edb92
MC		 934 * gives equal priority to transmits and receives. Valid only on
935 * 82542 and 82543 silicon.
1da177e4 936 */
8fc897b0 937 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1da177e4
LT		 938 ctrl = E1000_READ_REG(hw, CTRL);
939 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
940 }
941
8fc897b0 942 switch (hw->mac_type) {
1da177e4
LT		 943 case e1000_82545_rev_3:
944 case e1000_82546_rev_3:
945 break;
946 default:
947 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
8fc897b0 948 if (hw->bus_type == e1000_bus_type_pcix) {
1da177e4
LT		 949 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
950 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
951 &pcix_stat_hi_word);
952 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
953 PCIX_COMMAND_MMRBC_SHIFT;
954 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
955 PCIX_STATUS_HI_MMRBC_SHIFT;
8fc897b0 956 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1da177e4 957 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
8fc897b0 958 if (cmd_mmrbc > stat_mmrbc) {
1da177e4
LT		 959 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
960 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
961 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
962 &pcix_cmd_word);
963 }
964 }
965 break;
966 }
967
cd94dd0b
AK		 968 /* More time needed for PHY to initialize */
969 if (hw->mac_type == e1000_ich8lan)
f8ec4733 970 msleep(15);
cd94dd0b 971
1da177e4
LT		 972 /* Call a subroutine to configure the link and setup flow control. */
973 ret_val = e1000_setup_link(hw);
974
975 /* Set the transmit descriptor write-back policy */
8fc897b0 976 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 977 ctrl = E1000_READ_REG(hw, TXDCTL);
978 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
979 E1000_WRITE_REG(hw, TXDCTL, ctrl);
980 }
981
2d7edb92 982 if (hw->mac_type == e1000_82573) {
76c224bc 983 e1000_enable_tx_pkt_filtering(hw);
2d7edb92
MC		 984 }
985
868d5309
MC		 986 switch (hw->mac_type) {
987 default:
988 break;
6418ecc6
JK		 989 case e1000_80003es2lan:
990 /* Enable retransmit on late collisions */
991 reg_data = E1000_READ_REG(hw, TCTL);
992 reg_data |= E1000_TCTL_RTLC;
993 E1000_WRITE_REG(hw, TCTL, reg_data);
994
995 /* Configure Gigabit Carry Extend Padding */
996 reg_data = E1000_READ_REG(hw, TCTL_EXT);
997 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
998 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
999 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1000
1001 /* Configure Transmit Inter-Packet Gap */
1002 reg_data = E1000_READ_REG(hw, TIPG);
1003 reg_data &= ~E1000_TIPG_IPGT_MASK;
1004 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1005 E1000_WRITE_REG(hw, TIPG, reg_data);
1006
1007 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1008 reg_data &= ~0x00100000;
1009 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1010 /* Fall through */
868d5309 1011 case e1000_82571:
a7990ba6 1012 case e1000_82572:
cd94dd0b 1013 case e1000_ich8lan:
868d5309 1014 ctrl = E1000_READ_REG(hw, TXDCTL1);
6418ecc6 1015 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
868d5309
MC		 1016 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1017 break;
1018 }
1019
1020
868d5309
MC		 1021 if (hw->mac_type == e1000_82573) {
1022 uint32_t gcr = E1000_READ_REG(hw, GCR);
1023 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1024 E1000_WRITE_REG(hw, GCR, gcr);
1025 }
2d7edb92 1026
1da177e4
LT		 1027 /* Clear all of the statistics registers (clear on read). It is
1028 * important that we do this after we have tried to establish link
1029 * because the symbol error count will increment wildly if there
1030 * is no link.
1031 */
1032 e1000_clear_hw_cntrs(hw);
1033
cd94dd0b
AK		 1034 /* ICH8 No-snoop bits are opposite polarity.
1035 * Set to snoop by default after reset. */
1036 if (hw->mac_type == e1000_ich8lan)
1037 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1038
b7ee49db
JK		 1039 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1040 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1041 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1042 /* Relaxed ordering must be disabled to avoid a parity
1043 * error crash in a PCI slot. */
1044 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1045 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1046 }
1047
1da177e4
LT		 1048 return ret_val;
1049}
1050
1051/******************************************************************************
1052 * Adjust SERDES output amplitude based on EEPROM setting.
1053 *
1054 * hw - Struct containing variables accessed by shared code.
1055 *****************************************************************************/
1056static int32_t
1057e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1058{
1059 uint16_t eeprom_data;
1060 int32_t ret_val;
1061
1062 DEBUGFUNC("e1000_adjust_serdes_amplitude");
1063
8fc897b0 1064 if (hw->media_type != e1000_media_type_internal_serdes)
1da177e4
LT		 1065 return E1000_SUCCESS;
1066
8fc897b0 1067 switch (hw->mac_type) {
1da177e4
LT		 1068 case e1000_82545_rev_3:
1069 case e1000_82546_rev_3:
1070 break;
1071 default:
1072 return E1000_SUCCESS;
1073 }
1074
1075 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1076 if (ret_val) {
1077 return ret_val;
1078 }
1079
8fc897b0 1080 if (eeprom_data != EEPROM_RESERVED_WORD) {
1da177e4 1081 /* Adjust SERDES output amplitude only. */
76c224bc 1082 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1da177e4 1083 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
8fc897b0 1084 if (ret_val)
1da177e4
LT		 1085 return ret_val;
1086 }
1087
1088 return E1000_SUCCESS;
1089}
1090
1091/******************************************************************************
1092 * Configures flow control and link settings.
1093 *
1094 * hw - Struct containing variables accessed by shared code
1095 *
1096 * Determines which flow control settings to use. Calls the apropriate media-
1097 * specific link configuration function. Configures the flow control settings.
1098 * Assuming the adapter has a valid link partner, a valid link should be
1099 * established. Assumes the hardware has previously been reset and the
1100 * transmitter and receiver are not enabled.
1101 *****************************************************************************/
1102int32_t
1103e1000_setup_link(struct e1000_hw *hw)
1104{
1105 uint32_t ctrl_ext;
1106 int32_t ret_val;
1107 uint16_t eeprom_data;
1108
1109 DEBUGFUNC("e1000_setup_link");
1110
526f9957
JK		 1111 /* In the case of the phy reset being blocked, we already have a link.
1112 * We do not have to set it up again. */
1113 if (e1000_check_phy_reset_block(hw))
1114 return E1000_SUCCESS;
1115
1da177e4
LT		 1116 /* Read and store word 0x0F of the EEPROM. This word contains bits
1117 * that determine the hardware's default PAUSE (flow control) mode,
1118 * a bit that determines whether the HW defaults to enabling or
1119 * disabling auto-negotiation, and the direction of the
1120 * SW defined pins. If there is no SW over-ride of the flow
1121 * control setting, then the variable hw->fc will
1122 * be initialized based on a value in the EEPROM.
1123 */
11241b10 1124 if (hw->fc == E1000_FC_DEFAULT) {
fd803241 1125 switch (hw->mac_type) {
cd94dd0b 1126 case e1000_ich8lan:
fd803241 1127 case e1000_82573:
11241b10 1128 hw->fc = E1000_FC_FULL;
fd803241
JK		 1129 break;
1130 default:
1131 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1132 1, &eeprom_data);
1133 if (ret_val) {
1134 DEBUGOUT("EEPROM Read Error\n");
1135 return -E1000_ERR_EEPROM;
1136 }
1137 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
11241b10 1138 hw->fc = E1000_FC_NONE;
fd803241
JK		 1139 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1140 EEPROM_WORD0F_ASM_DIR)
11241b10 1141 hw->fc = E1000_FC_TX_PAUSE;
fd803241 1142 else
11241b10 1143 hw->fc = E1000_FC_FULL;
fd803241
JK		 1144 break;
1145 }
1da177e4
LT		 1146 }
1147
1148 /* We want to save off the original Flow Control configuration just
1149 * in case we get disconnected and then reconnected into a different
1150 * hub or switch with different Flow Control capabilities.
1151 */
8fc897b0 1152 if (hw->mac_type == e1000_82542_rev2_0)
11241b10 1153 hw->fc &= (~E1000_FC_TX_PAUSE);
1da177e4 1154
8fc897b0 1155 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
11241b10 1156 hw->fc &= (~E1000_FC_RX_PAUSE);
1da177e4
LT		 1157
1158 hw->original_fc = hw->fc;
1159
1160 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1161
1162 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1163 * polarity value for the SW controlled pins, and setup the
1164 * Extended Device Control reg with that info.
1165 * This is needed because one of the SW controlled pins is used for
1166 * signal detection. So this should be done before e1000_setup_pcs_link()
1167 * or e1000_phy_setup() is called.
1168 */
497fce5e 1169 if (hw->mac_type == e1000_82543) {
8fc897b0
AK		 1170 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1171 1, &eeprom_data);
1172 if (ret_val) {
1173 DEBUGOUT("EEPROM Read Error\n");
1174 return -E1000_ERR_EEPROM;
1175 }
1da177e4
LT		 1176 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1177 SWDPIO__EXT_SHIFT);
1178 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1179 }
1180
1181 /* Call the necessary subroutine to configure the link. */
1182 ret_val = (hw->media_type == e1000_media_type_copper) ?
1183 e1000_setup_copper_link(hw) :
1184 e1000_setup_fiber_serdes_link(hw);
1185
1186 /* Initialize the flow control address, type, and PAUSE timer
1187 * registers to their default values. This is done even if flow
1188 * control is disabled, because it does not hurt anything to
1189 * initialize these registers.
1190 */
1191 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1192
cd94dd0b
AK		 1193 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1194 if (hw->mac_type != e1000_ich8lan) {
1195 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1196 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1197 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1198 }
2d7edb92 1199
1da177e4
LT		 1200 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1201
1202 /* Set the flow control receive threshold registers. Normally,
1203 * these registers will be set to a default threshold that may be
1204 * adjusted later by the driver's runtime code. However, if the
1205 * ability to transmit pause frames in not enabled, then these
1206 * registers will be set to 0.
1207 */
11241b10 1208 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1da177e4
LT		 1209 E1000_WRITE_REG(hw, FCRTL, 0);
1210 E1000_WRITE_REG(hw, FCRTH, 0);
1211 } else {
1212 /* We need to set up the Receive Threshold high and low water marks
1213 * as well as (optionally) enabling the transmission of XON frames.
1214 */
8fc897b0 1215 if (hw->fc_send_xon) {
1da177e4
LT		 1216 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1217 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1218 } else {
1219 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1220 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1221 }
1222 }
1223 return ret_val;
1224}
1225
1226/******************************************************************************
1227 * Sets up link for a fiber based or serdes based adapter
1228 *
1229 * hw - Struct containing variables accessed by shared code
1230 *
1231 * Manipulates Physical Coding Sublayer functions in order to configure
1232 * link. Assumes the hardware has been previously reset and the transmitter
1233 * and receiver are not enabled.
1234 *****************************************************************************/
1235static int32_t
1236e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1237{
1238 uint32_t ctrl;
1239 uint32_t status;
1240 uint32_t txcw = 0;
1241 uint32_t i;
1242 uint32_t signal = 0;
1243 int32_t ret_val;
1244
1245 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1246
868d5309
MC		 1247 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1248 * until explicitly turned off or a power cycle is performed. A read to
1249 * the register does not indicate its status. Therefore, we ensure
1250 * loopback mode is disabled during initialization.
1251 */
1252 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1253 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1254
09ae3e88 1255 /* On adapters with a MAC newer than 82544, SWDP 1 will be
1da177e4
LT		 1256 * set when the optics detect a signal. On older adapters, it will be
1257 * cleared when there is a signal. This applies to fiber media only.
09ae3e88
JK		 1258 * If we're on serdes media, adjust the output amplitude to value
1259 * set in the EEPROM.
1da177e4
LT		 1260 */
1261 ctrl = E1000_READ_REG(hw, CTRL);
8fc897b0 1262 if (hw->media_type == e1000_media_type_fiber)
1da177e4
LT		 1263 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1264
1265 ret_val = e1000_adjust_serdes_amplitude(hw);
8fc897b0 1266 if (ret_val)
1da177e4
LT		 1267 return ret_val;
1268
1269 /* Take the link out of reset */
1270 ctrl &= ~(E1000_CTRL_LRST);
1271
1272 /* Adjust VCO speed to improve BER performance */
1273 ret_val = e1000_set_vco_speed(hw);
8fc897b0 1274 if (ret_val)
1da177e4
LT		 1275 return ret_val;
1276
1277 e1000_config_collision_dist(hw);
1278
1279 /* Check for a software override of the flow control settings, and setup
1280 * the device accordingly. If auto-negotiation is enabled, then software
1281 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1282 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1283 * auto-negotiation is disabled, then software will have to manually
1284 * configure the two flow control enable bits in the CTRL register.
1285 *
1286 * The possible values of the "fc" parameter are:
1287 * 0: Flow control is completely disabled
1288 * 1: Rx flow control is enabled (we can receive pause frames, but
1289 * not send pause frames).
1290 * 2: Tx flow control is enabled (we can send pause frames but we do
1291 * not support receiving pause frames).
1292 * 3: Both Rx and TX flow control (symmetric) are enabled.
1293 */
1294 switch (hw->fc) {
11241b10 1295 case E1000_FC_NONE:
1da177e4
LT		 1296 /* Flow control is completely disabled by a software over-ride. */
1297 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1298 break;
11241b10 1299 case E1000_FC_RX_PAUSE:
1da177e4
LT		 1300 /* RX Flow control is enabled and TX Flow control is disabled by a
1301 * software over-ride. Since there really isn't a way to advertise
1302 * that we are capable of RX Pause ONLY, we will advertise that we
1303 * support both symmetric and asymmetric RX PAUSE. Later, we will
1304 * disable the adapter's ability to send PAUSE frames.
1305 */
1306 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1307 break;
11241b10 1308 case E1000_FC_TX_PAUSE:
1da177e4
LT		 1309 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1310 * software over-ride.
1311 */
1312 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1313 break;
11241b10 1314 case E1000_FC_FULL:
1da177e4
LT		 1315 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1316 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1317 break;
1318 default:
1319 DEBUGOUT("Flow control param set incorrectly\n");
1320 return -E1000_ERR_CONFIG;
1321 break;
1322 }
1323
1324 /* Since auto-negotiation is enabled, take the link out of reset (the link
1325 * will be in reset, because we previously reset the chip). This will
1326 * restart auto-negotiation. If auto-neogtiation is successful then the
1327 * link-up status bit will be set and the flow control enable bits (RFCE
1328 * and TFCE) will be set according to their negotiated value.
1329 */
1330 DEBUGOUT("Auto-negotiation enabled\n");
1331
1332 E1000_WRITE_REG(hw, TXCW, txcw);
1333 E1000_WRITE_REG(hw, CTRL, ctrl);
1334 E1000_WRITE_FLUSH(hw);
1335
1336 hw->txcw = txcw;
f8ec4733 1337 msleep(1);
1da177e4
LT		 1338
1339 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1340 * indication in the Device Status Register. Time-out if a link isn't
1341 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1342 * less than 500 milliseconds even if the other end is doing it in SW).
1343 * For internal serdes, we just assume a signal is present, then poll.
1344 */
8fc897b0 1345 if (hw->media_type == e1000_media_type_internal_serdes ||
1da177e4
LT		 1346 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1347 DEBUGOUT("Looking for Link\n");
8fc897b0 1348 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
f8ec4733 1349 msleep(10);
1da177e4 1350 status = E1000_READ_REG(hw, STATUS);
8fc897b0 1351 if (status & E1000_STATUS_LU) break;
1da177e4 1352 }
8fc897b0 1353 if (i == (LINK_UP_TIMEOUT / 10)) {
1da177e4
LT		 1354 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1355 hw->autoneg_failed = 1;
1356 /* AutoNeg failed to achieve a link, so we'll call
1357 * e1000_check_for_link. This routine will force the link up if
1358 * we detect a signal. This will allow us to communicate with
1359 * non-autonegotiating link partners.
1360 */
1361 ret_val = e1000_check_for_link(hw);
8fc897b0 1362 if (ret_val) {
1da177e4
LT		 1363 DEBUGOUT("Error while checking for link\n");
1364 return ret_val;
1365 }
1366 hw->autoneg_failed = 0;
1367 } else {
1368 hw->autoneg_failed = 0;
1369 DEBUGOUT("Valid Link Found\n");
1370 }
1371 } else {
1372 DEBUGOUT("No Signal Detected\n");
1373 }
1374 return E1000_SUCCESS;
1375}
1376
1377/******************************************************************************
2d7edb92 1378* Make sure we have a valid PHY and change PHY mode before link setup.
1da177e4
LT		 1379*
1380* hw - Struct containing variables accessed by shared code
1381******************************************************************************/
1382static int32_t
2d7edb92 1383e1000_copper_link_preconfig(struct e1000_hw *hw)
1da177e4
LT		 1384{
1385 uint32_t ctrl;
1da177e4 1386 int32_t ret_val;
1da177e4
LT		 1387 uint16_t phy_data;
1388
2d7edb92 1389 DEBUGFUNC("e1000_copper_link_preconfig");
1da177e4
LT		 1390
1391 ctrl = E1000_READ_REG(hw, CTRL);
1392 /* With 82543, we need to force speed and duplex on the MAC equal to what
1393 * the PHY speed and duplex configuration is. In addition, we need to
1394 * perform a hardware reset on the PHY to take it out of reset.
1395 */
8fc897b0 1396 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 1397 ctrl |= E1000_CTRL_SLU;
1398 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1399 E1000_WRITE_REG(hw, CTRL, ctrl);
1400 } else {
1401 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1402 E1000_WRITE_REG(hw, CTRL, ctrl);
2d7edb92 1403 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 1404 if (ret_val)
2d7edb92 1405 return ret_val;
1da177e4
LT		 1406 }
1407
1408 /* Make sure we have a valid PHY */
1409 ret_val = e1000_detect_gig_phy(hw);
8fc897b0 1410 if (ret_val) {
1da177e4
LT		 1411 DEBUGOUT("Error, did not detect valid phy.\n");
1412 return ret_val;
1413 }
1414 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1415
1416 /* Set PHY to class A mode (if necessary) */
1417 ret_val = e1000_set_phy_mode(hw);
8fc897b0 1418 if (ret_val)
1da177e4
LT		 1419 return ret_val;
1420
8fc897b0 1421 if ((hw->mac_type == e1000_82545_rev_3) ||
1da177e4
LT		 1422 (hw->mac_type == e1000_82546_rev_3)) {
1423 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1424 phy_data |= 0x00000008;
1425 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1426 }
1427
8fc897b0
AK		 1428 if (hw->mac_type <= e1000_82543 ||
1429 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1430 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1da177e4
LT		 1431 hw->phy_reset_disable = FALSE;
1432
2d7edb92
MC		 1433 return E1000_SUCCESS;
1434}
1da177e4 1435
1da177e4 1436
2d7edb92
MC		 1437/********************************************************************
1438* Copper link setup for e1000_phy_igp series.
1439*
1440* hw - Struct containing variables accessed by shared code
1441*********************************************************************/
1442static int32_t
1443e1000_copper_link_igp_setup(struct e1000_hw *hw)
1444{
1445 uint32_t led_ctrl;
1446 int32_t ret_val;
1447 uint16_t phy_data;
1da177e4 1448
2d7edb92 1449 DEBUGFUNC("e1000_copper_link_igp_setup");
1da177e4 1450
2d7edb92
MC		 1451 if (hw->phy_reset_disable)
1452 return E1000_SUCCESS;
76c224bc 1453
2d7edb92
MC		 1454 ret_val = e1000_phy_reset(hw);
1455 if (ret_val) {
1456 DEBUGOUT("Error Resetting the PHY\n");
1457 return ret_val;
1458 }
1da177e4 1459
8fc897b0 1460 /* Wait 15ms for MAC to configure PHY from eeprom settings */
f8ec4733 1461 msleep(15);
cd94dd0b 1462 if (hw->mac_type != e1000_ich8lan) {
2d7edb92
MC		 1463 /* Configure activity LED after PHY reset */
1464 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1465 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1466 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1467 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
cd94dd0b 1468 }
1da177e4 1469
c9c1b834
JK		 1470 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1471 if (hw->phy_type == e1000_phy_igp) {
1472 /* disable lplu d3 during driver init */
1473 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1474 if (ret_val) {
1475 DEBUGOUT("Error Disabling LPLU D3\n");
1476 return ret_val;
1477 }
2d7edb92 1478 }
1da177e4 1479
2d7edb92
MC		 1480 /* disable lplu d0 during driver init */
1481 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1482 if (ret_val) {
1483 DEBUGOUT("Error Disabling LPLU D0\n");
1484 return ret_val;
1485 }
1486 /* Configure mdi-mdix settings */
1487 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1488 if (ret_val)
1489 return ret_val;
1da177e4 1490
2d7edb92
MC		 1491 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1492 hw->dsp_config_state = e1000_dsp_config_disabled;
1493 /* Force MDI for earlier revs of the IGP PHY */
1494 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1495 hw->mdix = 1;
1da177e4 1496
2d7edb92
MC		 1497 } else {
1498 hw->dsp_config_state = e1000_dsp_config_enabled;
1499 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1da177e4 1500
2d7edb92
MC		 1501 switch (hw->mdix) {
1502 case 1:
1503 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1504 break;
1505 case 2:
1506 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1507 break;
1508 case 0:
1509 default:
1510 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1511 break;
1512 }
1513 }
1514 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 1515 if (ret_val)
2d7edb92 1516 return ret_val;
1da177e4 1517
2d7edb92 1518 /* set auto-master slave resolution settings */
8fc897b0 1519 if (hw->autoneg) {
2d7edb92 1520 e1000_ms_type phy_ms_setting = hw->master_slave;
1da177e4 1521
8fc897b0 1522 if (hw->ffe_config_state == e1000_ffe_config_active)
2d7edb92 1523 hw->ffe_config_state = e1000_ffe_config_enabled;
1da177e4 1524
8fc897b0 1525 if (hw->dsp_config_state == e1000_dsp_config_activated)
2d7edb92 1526 hw->dsp_config_state = e1000_dsp_config_enabled;
1da177e4 1527
2d7edb92
MC		 1528 /* when autonegotiation advertisment is only 1000Mbps then we
1529 * should disable SmartSpeed and enable Auto MasterSlave
1530 * resolution as hardware default. */
8fc897b0 1531 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2d7edb92 1532 /* Disable SmartSpeed */
8fc897b0
AK		 1533 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1534 &phy_data);
1535 if (ret_val)
1da177e4 1536 return ret_val;
2d7edb92 1537 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8fc897b0
AK		 1538 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1539 phy_data);
1540 if (ret_val)
1da177e4 1541 return ret_val;
2d7edb92
MC		 1542 /* Set auto Master/Slave resolution process */
1543 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1544 if (ret_val)
2d7edb92
MC		 1545 return ret_val;
1546 phy_data &= ~CR_1000T_MS_ENABLE;
1547 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1548 if (ret_val)
2d7edb92
MC		 1549 return ret_val;
1550 }
1da177e4 1551
2d7edb92 1552 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1553 if (ret_val)
2d7edb92 1554 return ret_val;
1da177e4 1555
2d7edb92
MC		 1556 /* load defaults for future use */
1557 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1558 ((phy_data & CR_1000T_MS_VALUE) ?
1559 e1000_ms_force_master :
1560 e1000_ms_force_slave) :
1561 e1000_ms_auto;
1da177e4 1562
2d7edb92
MC		 1563 switch (phy_ms_setting) {
1564 case e1000_ms_force_master:
1565 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1566 break;
1567 case e1000_ms_force_slave:
1568 phy_data |= CR_1000T_MS_ENABLE;
1569 phy_data &= ~(CR_1000T_MS_VALUE);
1570 break;
1571 case e1000_ms_auto:
1572 phy_data &= ~CR_1000T_MS_ENABLE;
1573 default:
1574 break;
1575 }
1576 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1577 if (ret_val)
2d7edb92 1578 return ret_val;
2b02893e 1579 }
1da177e4 1580
2b02893e 1581 return E1000_SUCCESS;
2d7edb92 1582}
1da177e4 1583
6418ecc6
JK		 1584/********************************************************************
1585* Copper link setup for e1000_phy_gg82563 series.
1586*
1587* hw - Struct containing variables accessed by shared code
1588*********************************************************************/
1589static int32_t
1590e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1591{
1592 int32_t ret_val;
1593 uint16_t phy_data;
1594 uint32_t reg_data;
1595
1596 DEBUGFUNC("e1000_copper_link_ggp_setup");
1597
8fc897b0 1598 if (!hw->phy_reset_disable) {
76c224bc 1599
6418ecc6
JK		 1600 /* Enable CRS on TX for half-duplex operation. */
1601 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1602 &phy_data);
8fc897b0 1603 if (ret_val)
6418ecc6
JK		 1604 return ret_val;
1605
1606 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1607 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1608 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1609
1610 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1611 phy_data);
8fc897b0 1612 if (ret_val)
6418ecc6
JK		 1613 return ret_val;
1614
1615 /* Options:
1616 * MDI/MDI-X = 0 (default)
1617 * 0 - Auto for all speeds
1618 * 1 - MDI mode
1619 * 2 - MDI-X mode
1620 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1621 */
1622 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1623 if (ret_val)
6418ecc6
JK		 1624 return ret_val;
1625
1626 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1627
1628 switch (hw->mdix) {
1629 case 1:
1630 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1631 break;
1632 case 2:
1633 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1634 break;
1635 case 0:
1636 default:
1637 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1638 break;
1639 }
1640
1641 /* Options:
1642 * disable_polarity_correction = 0 (default)
1643 * Automatic Correction for Reversed Cable Polarity
1644 * 0 - Disabled
1645 * 1 - Enabled
1646 */
1647 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
8fc897b0 1648 if (hw->disable_polarity_correction == 1)
6418ecc6
JK		 1649 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1650 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1651
8fc897b0 1652 if (ret_val)
6418ecc6
JK		 1653 return ret_val;
1654
1655 /* SW Reset the PHY so all changes take effect */
1656 ret_val = e1000_phy_reset(hw);
1657 if (ret_val) {
1658 DEBUGOUT("Error Resetting the PHY\n");
1659 return ret_val;
1660 }
1661 } /* phy_reset_disable */
1662
1663 if (hw->mac_type == e1000_80003es2lan) {
1664 /* Bypass RX and TX FIFO's */
1665 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1666 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1667 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1668 if (ret_val)
1669 return ret_val;
1670
1671 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1672 if (ret_val)
1673 return ret_val;
1674
1675 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1676 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1677
1678 if (ret_val)
1679 return ret_val;
1680
1681 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1682 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1683 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1684
1685 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1686 &phy_data);
1687 if (ret_val)
1688 return ret_val;
1689
1690 /* Do not init these registers when the HW is in IAMT mode, since the
1691 * firmware will have already initialized them. We only initialize
1692 * them if the HW is not in IAMT mode.
1693 */
1694 if (e1000_check_mng_mode(hw) == FALSE) {
1695 /* Enable Electrical Idle on the PHY */
1696 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1697 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1698 phy_data);
1699 if (ret_val)
1700 return ret_val;
1701
1702 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1703 &phy_data);
1704 if (ret_val)
1705 return ret_val;
1706
cd94dd0b 1707 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
6418ecc6
JK		 1708 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1709 phy_data);
8fc897b0 1710
6418ecc6
JK		 1711 if (ret_val)
1712 return ret_val;
1713 }
1714
1715 /* Workaround: Disable padding in Kumeran interface in the MAC
1716 * and in the PHY to avoid CRC errors.
1717 */
1718 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1719 &phy_data);
1720 if (ret_val)
1721 return ret_val;
1722 phy_data |= GG82563_ICR_DIS_PADDING;
1723 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1724 phy_data);
1725 if (ret_val)
1726 return ret_val;
1727 }
1728
1729 return E1000_SUCCESS;
1730}
1da177e4 1731
2d7edb92
MC		 1732/********************************************************************
1733* Copper link setup for e1000_phy_m88 series.
1734*
1735* hw - Struct containing variables accessed by shared code
1736*********************************************************************/
1737static int32_t
1738e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1739{
1740 int32_t ret_val;
1741 uint16_t phy_data;
1da177e4 1742
2d7edb92 1743 DEBUGFUNC("e1000_copper_link_mgp_setup");
1da177e4 1744
8fc897b0 1745 if (hw->phy_reset_disable)
2d7edb92 1746 return E1000_SUCCESS;
76c224bc 1747
2d7edb92
MC		 1748 /* Enable CRS on TX. This must be set for half-duplex operation. */
1749 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1750 if (ret_val)
2d7edb92 1751 return ret_val;
1da177e4 1752
2d7edb92 1753 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1da177e4 1754
2d7edb92
MC		 1755 /* Options:
1756 * MDI/MDI-X = 0 (default)
1757 * 0 - Auto for all speeds
1758 * 1 - MDI mode
1759 * 2 - MDI-X mode
1760 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1761 */
1762 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1da177e4 1763
2d7edb92
MC		 1764 switch (hw->mdix) {
1765 case 1:
1766 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1767 break;
1768 case 2:
1769 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1770 break;
1771 case 3:
1772 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1773 break;
1774 case 0:
1775 default:
1776 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1777 break;
1778 }
1779
1780 /* Options:
1781 * disable_polarity_correction = 0 (default)
1782 * Automatic Correction for Reversed Cable Polarity
1783 * 0 - Disabled
1784 * 1 - Enabled
1da177e4 1785 */
2d7edb92 1786 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
8fc897b0 1787 if (hw->disable_polarity_correction == 1)
2d7edb92 1788 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
ee04022a
AK		 1789 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1790 if (ret_val)
2d7edb92
MC		 1791 return ret_val;
1792
2d7edb92 1793 if (hw->phy_revision < M88E1011_I_REV_4) {
ee04022a
AK		 1794 /* Force TX_CLK in the Extended PHY Specific Control Register
1795 * to 25MHz clock.
1796 */
1797 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1798 if (ret_val)
1799 return ret_val;
1800
1801 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1802
1803 if ((hw->phy_revision == E1000_REVISION_2) &&
1804 (hw->phy_id == M88E1111_I_PHY_ID)) {
1805 /* Vidalia Phy, set the downshift counter to 5x */
1806 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1807 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1808 ret_val = e1000_write_phy_reg(hw,
1809 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1810 if (ret_val)
1811 return ret_val;
1812 } else {
1813 /* Configure Master and Slave downshift values */
1814 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
2d7edb92 1815 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
ee04022a 1816 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
2d7edb92 1817 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ee04022a
AK		 1818 ret_val = e1000_write_phy_reg(hw,
1819 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1820 if (ret_val)
1821 return ret_val;
1822 }
2d7edb92 1823 }
1da177e4 1824
2d7edb92
MC		 1825 /* SW Reset the PHY so all changes take effect */
1826 ret_val = e1000_phy_reset(hw);
8fc897b0 1827 if (ret_val) {
2d7edb92
MC		 1828 DEBUGOUT("Error Resetting the PHY\n");
1829 return ret_val;
1da177e4
LT		 1830 }
1831
2d7edb92 1832 return E1000_SUCCESS;
1da177e4
LT		 1833}
1834
2d7edb92
MC		 1835/********************************************************************
1836* Setup auto-negotiation and flow control advertisements,
1837* and then perform auto-negotiation.
1da177e4
LT		 1838*
1839* hw - Struct containing variables accessed by shared code
2d7edb92
MC		 1840*********************************************************************/
1841static int32_t
1842e1000_copper_link_autoneg(struct e1000_hw *hw)
1da177e4
LT		 1843{
1844 int32_t ret_val;
2d7edb92 1845 uint16_t phy_data;
1da177e4 1846
2d7edb92 1847 DEBUGFUNC("e1000_copper_link_autoneg");
1da177e4 1848
2d7edb92
MC		 1849 /* Perform some bounds checking on the hw->autoneg_advertised
1850 * parameter. If this variable is zero, then set it to the default.
1851 */
1852 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1853
1854 /* If autoneg_advertised is zero, we assume it was not defaulted
1855 * by the calling code so we set to advertise full capability.
1856 */
8fc897b0 1857 if (hw->autoneg_advertised == 0)
2d7edb92
MC		 1858 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1859
cd94dd0b
AK		 1860 /* IFE phy only supports 10/100 */
1861 if (hw->phy_type == e1000_phy_ife)
1862 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1863
2d7edb92
MC		 1864 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1865 ret_val = e1000_phy_setup_autoneg(hw);
8fc897b0 1866 if (ret_val) {
2d7edb92
MC		 1867 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1868 return ret_val;
1869 }
1870 DEBUGOUT("Restarting Auto-Neg\n");
1871
1872 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1873 * the Auto Neg Restart bit in the PHY control register.
1874 */
1875 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 1876 if (ret_val)
1da177e4
LT		 1877 return ret_val;
1878
2d7edb92
MC		 1879 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1880 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 1881 if (ret_val)
1da177e4
LT		 1882 return ret_val;
1883
2d7edb92
MC		 1884 /* Does the user want to wait for Auto-Neg to complete here, or
1885 * check at a later time (for example, callback routine).
1886 */
8fc897b0 1887 if (hw->wait_autoneg_complete) {
2d7edb92 1888 ret_val = e1000_wait_autoneg(hw);
8fc897b0 1889 if (ret_val) {
2d7edb92
MC		 1890 DEBUGOUT("Error while waiting for autoneg to complete\n");
1891 return ret_val;
1892 }
1893 }
1894
1895 hw->get_link_status = TRUE;
1896
1897 return E1000_SUCCESS;
1898}
1899
2d7edb92
MC		 1900/******************************************************************************
1901* Config the MAC and the PHY after link is up.
1902* 1) Set up the MAC to the current PHY speed/duplex
1903* if we are on 82543. If we
1904* are on newer silicon, we only need to configure
1905* collision distance in the Transmit Control Register.
1906* 2) Set up flow control on the MAC to that established with
1907* the link partner.
76c224bc 1908* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2d7edb92
MC		 1909*
1910* hw - Struct containing variables accessed by shared code
1911******************************************************************************/
1912static int32_t
1913e1000_copper_link_postconfig(struct e1000_hw *hw)
1914{
1915 int32_t ret_val;
1916 DEBUGFUNC("e1000_copper_link_postconfig");
76c224bc 1917
8fc897b0 1918 if (hw->mac_type >= e1000_82544) {
2d7edb92
MC		 1919 e1000_config_collision_dist(hw);
1920 } else {
1921 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 1922 if (ret_val) {
2d7edb92
MC		 1923 DEBUGOUT("Error configuring MAC to PHY settings\n");
1924 return ret_val;
1925 }
1926 }
1927 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 1928 if (ret_val) {
2d7edb92
MC		 1929 DEBUGOUT("Error Configuring Flow Control\n");
1930 return ret_val;
1931 }
1932
1933 /* Config DSP to improve Giga link quality */
8fc897b0 1934 if (hw->phy_type == e1000_phy_igp) {
2d7edb92 1935 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
8fc897b0 1936 if (ret_val) {
2d7edb92
MC		 1937 DEBUGOUT("Error Configuring DSP after link up\n");
1938 return ret_val;
1939 }
1940 }
76c224bc 1941
2d7edb92
MC		 1942 return E1000_SUCCESS;
1943}
1944
1945/******************************************************************************
1946* Detects which PHY is present and setup the speed and duplex
1947*
1948* hw - Struct containing variables accessed by shared code
1949******************************************************************************/
1950static int32_t
1951e1000_setup_copper_link(struct e1000_hw *hw)
1952{
1953 int32_t ret_val;
1954 uint16_t i;
1955 uint16_t phy_data;
6418ecc6 1956 uint16_t reg_data;
2d7edb92
MC		 1957
1958 DEBUGFUNC("e1000_setup_copper_link");
1959
cd94dd0b
AK		 1960 switch (hw->mac_type) {
1961 case e1000_80003es2lan:
1962 case e1000_ich8lan:
1963 /* Set the mac to wait the maximum time between each
1964 * iteration and increase the max iterations when
1965 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1966 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1967 if (ret_val)
1968 return ret_val;
1969 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1970 if (ret_val)
1971 return ret_val;
1972 reg_data |= 0x3F;
1973 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1974 if (ret_val)
1975 return ret_val;
1976 default:
1977 break;
1978 }
1979
2d7edb92
MC		 1980 /* Check if it is a valid PHY and set PHY mode if necessary. */
1981 ret_val = e1000_copper_link_preconfig(hw);
8fc897b0 1982 if (ret_val)
2d7edb92
MC		 1983 return ret_val;
1984
6418ecc6
JK		 1985 switch (hw->mac_type) {
1986 case e1000_80003es2lan:
cd94dd0b
AK		 1987 /* Kumeran registers are written-only */
1988 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
6418ecc6
JK		 1989 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1990 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1991 reg_data);
1992 if (ret_val)
1993 return ret_val;
1994 break;
1995 default:
1996 break;
1997 }
1998
2d7edb92 1999 if (hw->phy_type == e1000_phy_igp ||
cd94dd0b 2000 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92
MC		 2001 hw->phy_type == e1000_phy_igp_2) {
2002 ret_val = e1000_copper_link_igp_setup(hw);
8fc897b0 2003 if (ret_val)
2d7edb92
MC		 2004 return ret_val;
2005 } else if (hw->phy_type == e1000_phy_m88) {
2006 ret_val = e1000_copper_link_mgp_setup(hw);
8fc897b0 2007 if (ret_val)
2d7edb92 2008 return ret_val;
6418ecc6
JK		 2009 } else if (hw->phy_type == e1000_phy_gg82563) {
2010 ret_val = e1000_copper_link_ggp_setup(hw);
8fc897b0 2011 if (ret_val)
6418ecc6 2012 return ret_val;
2d7edb92
MC		 2013 }
2014
8fc897b0 2015 if (hw->autoneg) {
76c224bc
AK		 2016 /* Setup autoneg and flow control advertisement
2017 * and perform autonegotiation */
2d7edb92 2018 ret_val = e1000_copper_link_autoneg(hw);
8fc897b0 2019 if (ret_val)
76c224bc 2020 return ret_val;
2d7edb92
MC		 2021 } else {
2022 /* PHY will be set to 10H, 10F, 100H,or 100F
2023 * depending on value from forced_speed_duplex. */
2024 DEBUGOUT("Forcing speed and duplex\n");
2025 ret_val = e1000_phy_force_speed_duplex(hw);
8fc897b0 2026 if (ret_val) {
2d7edb92
MC		 2027 DEBUGOUT("Error Forcing Speed and Duplex\n");
2028 return ret_val;
2029 }
2030 }
2031
2032 /* Check link status. Wait up to 100 microseconds for link to become
2033 * valid.
2034 */
8fc897b0 2035 for (i = 0; i < 10; i++) {
2d7edb92 2036 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2037 if (ret_val)
2d7edb92
MC		 2038 return ret_val;
2039 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2040 if (ret_val)
2d7edb92
MC		 2041 return ret_val;
2042
8fc897b0 2043 if (phy_data & MII_SR_LINK_STATUS) {
2d7edb92
MC		 2044 /* Config the MAC and PHY after link is up */
2045 ret_val = e1000_copper_link_postconfig(hw);
8fc897b0 2046 if (ret_val)
2d7edb92 2047 return ret_val;
76c224bc 2048
2d7edb92
MC		 2049 DEBUGOUT("Valid link established!!!\n");
2050 return E1000_SUCCESS;
2051 }
2052 udelay(10);
2053 }
2054
2055 DEBUGOUT("Unable to establish link!!!\n");
2056 return E1000_SUCCESS;
2057}
2058
6418ecc6
JK		 2059/******************************************************************************
2060* Configure the MAC-to-PHY interface for 10/100Mbps
2061*
2062* hw - Struct containing variables accessed by shared code
2063******************************************************************************/
2064static int32_t
cd94dd0b 2065e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
6418ecc6
JK		 2066{
2067 int32_t ret_val = E1000_SUCCESS;
2068 uint32_t tipg;
2069 uint16_t reg_data;
2070
2071 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2072
2073 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2074 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2075 reg_data);
2076 if (ret_val)
2077 return ret_val;
2078
2079 /* Configure Transmit Inter-Packet Gap */
2080 tipg = E1000_READ_REG(hw, TIPG);
2081 tipg &= ~E1000_TIPG_IPGT_MASK;
2082 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2083 E1000_WRITE_REG(hw, TIPG, tipg);
2084
cd94dd0b
AK		 2085 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2086
2087 if (ret_val)
2088 return ret_val;
2089
2090 if (duplex == HALF_DUPLEX)
2091 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
2092 else
2093 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2094
2095 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2096
6418ecc6
JK		 2097 return ret_val;
2098}
2099
2100static int32_t
2101e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2102{
2103 int32_t ret_val = E1000_SUCCESS;
2104 uint16_t reg_data;
2105 uint32_t tipg;
2106
2107 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2108
2109 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2110 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2111 reg_data);
2112 if (ret_val)
2113 return ret_val;
2114
2115 /* Configure Transmit Inter-Packet Gap */
2116 tipg = E1000_READ_REG(hw, TIPG);
2117 tipg &= ~E1000_TIPG_IPGT_MASK;
2118 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2119 E1000_WRITE_REG(hw, TIPG, tipg);
2120
cd94dd0b
AK		 2121 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2122
2123 if (ret_val)
2124 return ret_val;
2125
2126 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2127 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2128
6418ecc6
JK		 2129 return ret_val;
2130}
2131
2d7edb92
MC		 2132/******************************************************************************
2133* Configures PHY autoneg and flow control advertisement settings
2134*
2135* hw - Struct containing variables accessed by shared code
2136******************************************************************************/
2137int32_t
2138e1000_phy_setup_autoneg(struct e1000_hw *hw)
2139{
2140 int32_t ret_val;
2141 uint16_t mii_autoneg_adv_reg;
2142 uint16_t mii_1000t_ctrl_reg;
2143
2144 DEBUGFUNC("e1000_phy_setup_autoneg");
2145
2146 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2147 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
8fc897b0 2148 if (ret_val)
2d7edb92
MC		 2149 return ret_val;
2150
cd94dd0b
AK		 2151 if (hw->phy_type != e1000_phy_ife) {
2152 /* Read the MII 1000Base-T Control Register (Address 9). */
2153 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2154 if (ret_val)
2155 return ret_val;
2156 } else
2157 mii_1000t_ctrl_reg=0;
2d7edb92
MC		 2158
2159 /* Need to parse both autoneg_advertised and fc and set up
2160 * the appropriate PHY registers. First we will parse for
1da177e4
LT		 2161 * autoneg_advertised software override. Since we can advertise
2162 * a plethora of combinations, we need to check each bit
2163 * individually.
2164 */
2165
2166 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2167 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2168 * the 1000Base-T Control Register (Address 9).
2169 */
2170 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2171 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2172
2173 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2174
2175 /* Do we want to advertise 10 Mb Half Duplex? */
8fc897b0 2176 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1da177e4
LT		 2177 DEBUGOUT("Advertise 10mb Half duplex\n");
2178 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2179 }
2180
2181 /* Do we want to advertise 10 Mb Full Duplex? */
8fc897b0 2182 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1da177e4
LT		 2183 DEBUGOUT("Advertise 10mb Full duplex\n");
2184 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2185 }
2186
2187 /* Do we want to advertise 100 Mb Half Duplex? */
8fc897b0 2188 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1da177e4
LT		 2189 DEBUGOUT("Advertise 100mb Half duplex\n");
2190 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2191 }
2192
2193 /* Do we want to advertise 100 Mb Full Duplex? */
8fc897b0 2194 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1da177e4
LT		 2195 DEBUGOUT("Advertise 100mb Full duplex\n");
2196 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2197 }
2198
2199 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
8fc897b0 2200 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1da177e4
LT		 2201 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2202 }
2203
2204 /* Do we want to advertise 1000 Mb Full Duplex? */
8fc897b0 2205 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1da177e4
LT		 2206 DEBUGOUT("Advertise 1000mb Full duplex\n");
2207 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
cd94dd0b
AK		 2208 if (hw->phy_type == e1000_phy_ife) {
2209 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2210 }
1da177e4
LT		 2211 }
2212
2213 /* Check for a software override of the flow control settings, and
2214 * setup the PHY advertisement registers accordingly. If
2215 * auto-negotiation is enabled, then software will have to set the
2216 * "PAUSE" bits to the correct value in the Auto-Negotiation
2217 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2218 *
2219 * The possible values of the "fc" parameter are:
2220 * 0: Flow control is completely disabled
2221 * 1: Rx flow control is enabled (we can receive pause frames
2222 * but not send pause frames).
2223 * 2: Tx flow control is enabled (we can send pause frames
2224 * but we do not support receiving pause frames).
2225 * 3: Both Rx and TX flow control (symmetric) are enabled.
2226 * other: No software override. The flow control configuration
2227 * in the EEPROM is used.
2228 */
2229 switch (hw->fc) {
11241b10 2230 case E1000_FC_NONE: /* 0 */
1da177e4
LT		 2231 /* Flow control (RX & TX) is completely disabled by a
2232 * software over-ride.
2233 */
2234 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2235 break;
11241b10 2236 case E1000_FC_RX_PAUSE: /* 1 */
1da177e4
LT		 2237 /* RX Flow control is enabled, and TX Flow control is
2238 * disabled, by a software over-ride.
2239 */
2240 /* Since there really isn't a way to advertise that we are
2241 * capable of RX Pause ONLY, we will advertise that we
2242 * support both symmetric and asymmetric RX PAUSE. Later
2243 * (in e1000_config_fc_after_link_up) we will disable the
2244 *hw's ability to send PAUSE frames.
2245 */
2246 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2247 break;
11241b10 2248 case E1000_FC_TX_PAUSE: /* 2 */
1da177e4
LT		 2249 /* TX Flow control is enabled, and RX Flow control is
2250 * disabled, by a software over-ride.
2251 */
2252 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2253 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2254 break;
11241b10 2255 case E1000_FC_FULL: /* 3 */
1da177e4
LT		 2256 /* Flow control (both RX and TX) is enabled by a software
2257 * over-ride.
2258 */
2259 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2260 break;
2261 default:
2262 DEBUGOUT("Flow control param set incorrectly\n");
2263 return -E1000_ERR_CONFIG;
2264 }
2265
2266 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
8fc897b0 2267 if (ret_val)
1da177e4
LT		 2268 return ret_val;
2269
2270 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2271
cd94dd0b
AK		 2272 if (hw->phy_type != e1000_phy_ife) {
2273 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2274 if (ret_val)
2275 return ret_val;
2276 }
1da177e4
LT		 2277
2278 return E1000_SUCCESS;
2279}
2280
2281/******************************************************************************
2282* Force PHY speed and duplex settings to hw->forced_speed_duplex
2283*
2284* hw - Struct containing variables accessed by shared code
2285******************************************************************************/
2286static int32_t
2287e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2288{
2289 uint32_t ctrl;
2290 int32_t ret_val;
2291 uint16_t mii_ctrl_reg;
2292 uint16_t mii_status_reg;
2293 uint16_t phy_data;
2294 uint16_t i;
2295
2296 DEBUGFUNC("e1000_phy_force_speed_duplex");
2297
2298 /* Turn off Flow control if we are forcing speed and duplex. */
11241b10 2299 hw->fc = E1000_FC_NONE;
1da177e4
LT		 2300
2301 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2302
2303 /* Read the Device Control Register. */
2304 ctrl = E1000_READ_REG(hw, CTRL);
2305
2306 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2307 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2308 ctrl &= ~(DEVICE_SPEED_MASK);
2309
2310 /* Clear the Auto Speed Detect Enable bit. */
2311 ctrl &= ~E1000_CTRL_ASDE;
2312
2313 /* Read the MII Control Register. */
2314 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
8fc897b0 2315 if (ret_val)
1da177e4
LT		 2316 return ret_val;
2317
2318 /* We need to disable autoneg in order to force link and duplex. */
2319
2320 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2321
2322 /* Are we forcing Full or Half Duplex? */
8fc897b0
AK		 2323 if (hw->forced_speed_duplex == e1000_100_full ||
2324 hw->forced_speed_duplex == e1000_10_full) {
1da177e4
LT		 2325 /* We want to force full duplex so we SET the full duplex bits in the
2326 * Device and MII Control Registers.
2327 */
2328 ctrl |= E1000_CTRL_FD;
2329 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2330 DEBUGOUT("Full Duplex\n");
2331 } else {
2332 /* We want to force half duplex so we CLEAR the full duplex bits in
2333 * the Device and MII Control Registers.
2334 */
2335 ctrl &= ~E1000_CTRL_FD;
2336 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2337 DEBUGOUT("Half Duplex\n");
2338 }
2339
2340 /* Are we forcing 100Mbps??? */
8fc897b0 2341 if (hw->forced_speed_duplex == e1000_100_full ||
1da177e4
LT		 2342 hw->forced_speed_duplex == e1000_100_half) {
2343 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2344 ctrl |= E1000_CTRL_SPD_100;
2345 mii_ctrl_reg |= MII_CR_SPEED_100;
2346 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2347 DEBUGOUT("Forcing 100mb ");
2348 } else {
2349 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2350 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2351 mii_ctrl_reg |= MII_CR_SPEED_10;
2352 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2353 DEBUGOUT("Forcing 10mb ");
2354 }
2355
2356 e1000_config_collision_dist(hw);
2357
2358 /* Write the configured values back to the Device Control Reg. */
2359 E1000_WRITE_REG(hw, CTRL, ctrl);
2360
6418ecc6
JK		 2361 if ((hw->phy_type == e1000_phy_m88) ||
2362 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4 2363 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2364 if (ret_val)
1da177e4
LT		 2365 return ret_val;
2366
2367 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2368 * forced whenever speed are duplex are forced.
2369 */
2370 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2371 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2372 if (ret_val)
1da177e4
LT		 2373 return ret_val;
2374
2375 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2376
2377 /* Need to reset the PHY or these changes will be ignored */
2378 mii_ctrl_reg |= MII_CR_RESET;
90fb5135 2379
cd94dd0b
AK		 2380 /* Disable MDI-X support for 10/100 */
2381 } else if (hw->phy_type == e1000_phy_ife) {
2382 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2383 if (ret_val)
2384 return ret_val;
2385
2386 phy_data &= ~IFE_PMC_AUTO_MDIX;
2387 phy_data &= ~IFE_PMC_FORCE_MDIX;
2388
2389 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2390 if (ret_val)
2391 return ret_val;
90fb5135 2392
1da177e4
LT		 2393 } else {
2394 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2395 * forced whenever speed or duplex are forced.
2396 */
2397 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
8fc897b0 2398 if (ret_val)
1da177e4
LT		 2399 return ret_val;
2400
2401 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2402 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2403
2404 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 2405 if (ret_val)
1da177e4
LT		 2406 return ret_val;
2407 }
2408
2409 /* Write back the modified PHY MII control register. */
2410 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
8fc897b0 2411 if (ret_val)
1da177e4
LT		 2412 return ret_val;
2413
2414 udelay(1);
2415
2416 /* The wait_autoneg_complete flag may be a little misleading here.
2417 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2418 * But we do want to delay for a period while forcing only so we
2419 * don't generate false No Link messages. So we will wait here
2420 * only if the user has set wait_autoneg_complete to 1, which is
2421 * the default.
2422 */
8fc897b0 2423 if (hw->wait_autoneg_complete) {
1da177e4
LT		 2424 /* We will wait for autoneg to complete. */
2425 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2426 mii_status_reg = 0;
2427
2428 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 2429 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 2430 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2431 * to be set.
2432 */
2433 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2434 if (ret_val)
1da177e4
LT		 2435 return ret_val;
2436
2437 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2438 if (ret_val)
1da177e4
LT		 2439 return ret_val;
2440
8fc897b0 2441 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 2442 msleep(100);
1da177e4 2443 }
8fc897b0 2444 if ((i == 0) &&
6418ecc6
JK		 2445 ((hw->phy_type == e1000_phy_m88) ||
2446 (hw->phy_type == e1000_phy_gg82563))) {
1da177e4
LT		 2447 /* We didn't get link. Reset the DSP and wait again for link. */
2448 ret_val = e1000_phy_reset_dsp(hw);
8fc897b0 2449 if (ret_val) {
1da177e4
LT		 2450 DEBUGOUT("Error Resetting PHY DSP\n");
2451 return ret_val;
2452 }
2453 }
2454 /* This loop will early-out if the link condition has been met. */
8fc897b0
AK		 2455 for (i = PHY_FORCE_TIME; i > 0; i--) {
2456 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 2457 msleep(100);
1da177e4
LT		 2458 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2459 * to be set.
2460 */
2461 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2462 if (ret_val)
1da177e4
LT		 2463 return ret_val;
2464
2465 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2466 if (ret_val)
1da177e4
LT		 2467 return ret_val;
2468 }
2469 }
2470
2471 if (hw->phy_type == e1000_phy_m88) {
2472 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2473 * Extended PHY Specific Control Register to 25MHz clock. This value
2474 * defaults back to a 2.5MHz clock when the PHY is reset.
2475 */
2476 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2477 if (ret_val)
1da177e4
LT		 2478 return ret_val;
2479
2480 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2481 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
8fc897b0 2482 if (ret_val)
1da177e4
LT		 2483 return ret_val;
2484
2485 /* In addition, because of the s/w reset above, we need to enable CRS on
2486 * TX. This must be set for both full and half duplex operation.
2487 */
2488 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2489 if (ret_val)
1da177e4
LT		 2490 return ret_val;
2491
2492 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2493 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2494 if (ret_val)
1da177e4
LT		 2495 return ret_val;
2496
8fc897b0
AK		 2497 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2498 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2499 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4 2500 ret_val = e1000_polarity_reversal_workaround(hw);
8fc897b0 2501 if (ret_val)
1da177e4
LT		 2502 return ret_val;
2503 }
6418ecc6
JK		 2504 } else if (hw->phy_type == e1000_phy_gg82563) {
2505 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2506 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2507 * we're not in a forced 10/duplex configuration. */
2508 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2509 if (ret_val)
2510 return ret_val;
2511
2512 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2513 if ((hw->forced_speed_duplex == e1000_10_full) ||
2514 (hw->forced_speed_duplex == e1000_10_half))
2515 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2516 else
2517 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2518
2519 /* Also due to the reset, we need to enable CRS on Tx. */
2520 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2521
2522 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2523 if (ret_val)
2524 return ret_val;
1da177e4
LT		 2525 }
2526 return E1000_SUCCESS;
2527}
2528
2529/******************************************************************************
2530* Sets the collision distance in the Transmit Control register
2531*
2532* hw - Struct containing variables accessed by shared code
2533*
2534* Link should have been established previously. Reads the speed and duplex
2535* information from the Device Status register.
2536******************************************************************************/
2537void
2538e1000_config_collision_dist(struct e1000_hw *hw)
2539{
0fadb059 2540 uint32_t tctl, coll_dist;
1da177e4
LT		 2541
2542 DEBUGFUNC("e1000_config_collision_dist");
2543
0fadb059
JK		 2544 if (hw->mac_type < e1000_82543)
2545 coll_dist = E1000_COLLISION_DISTANCE_82542;
2546 else
2547 coll_dist = E1000_COLLISION_DISTANCE;
2548
1da177e4
LT		 2549 tctl = E1000_READ_REG(hw, TCTL);
2550
2551 tctl &= ~E1000_TCTL_COLD;
0fadb059 2552 tctl |= coll_dist << E1000_COLD_SHIFT;
1da177e4
LT		 2553
2554 E1000_WRITE_REG(hw, TCTL, tctl);
2555 E1000_WRITE_FLUSH(hw);
2556}
2557
2558/******************************************************************************
2559* Sets MAC speed and duplex settings to reflect the those in the PHY
2560*
2561* hw - Struct containing variables accessed by shared code
2562* mii_reg - data to write to the MII control register
2563*
2564* The contents of the PHY register containing the needed information need to
2565* be passed in.
2566******************************************************************************/
2567static int32_t
2568e1000_config_mac_to_phy(struct e1000_hw *hw)
2569{
2570 uint32_t ctrl;
2571 int32_t ret_val;
2572 uint16_t phy_data;
2573
2574 DEBUGFUNC("e1000_config_mac_to_phy");
2575
76c224bc 2576 /* 82544 or newer MAC, Auto Speed Detection takes care of
2d7edb92
MC		 2577 * MAC speed/duplex configuration.*/
2578 if (hw->mac_type >= e1000_82544)
2579 return E1000_SUCCESS;
2580
1da177e4
LT		 2581 /* Read the Device Control Register and set the bits to Force Speed
2582 * and Duplex.
2583 */
2584 ctrl = E1000_READ_REG(hw, CTRL);
2585 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2586 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2587
2588 /* Set up duplex in the Device Control and Transmit Control
2589 * registers depending on negotiated values.
2590 */
2d7edb92 2591 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 2592 if (ret_val)
2d7edb92 2593 return ret_val;
1da177e4 2594
8fc897b0 2595 if (phy_data & M88E1000_PSSR_DPLX)
2d7edb92 2596 ctrl |= E1000_CTRL_FD;
76c224bc 2597 else
2d7edb92 2598 ctrl &= ~E1000_CTRL_FD;
1da177e4 2599
2d7edb92 2600 e1000_config_collision_dist(hw);
1da177e4 2601
2d7edb92
MC		 2602 /* Set up speed in the Device Control register depending on
2603 * negotiated values.
2604 */
8fc897b0 2605 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2d7edb92 2606 ctrl |= E1000_CTRL_SPD_1000;
8fc897b0 2607 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2d7edb92 2608 ctrl |= E1000_CTRL_SPD_100;
1da177e4 2609
1da177e4
LT		 2610 /* Write the configured values back to the Device Control Reg. */
2611 E1000_WRITE_REG(hw, CTRL, ctrl);
2612 return E1000_SUCCESS;
2613}
2614
2615/******************************************************************************
2616 * Forces the MAC's flow control settings.
2617 *
2618 * hw - Struct containing variables accessed by shared code
2619 *
2620 * Sets the TFCE and RFCE bits in the device control register to reflect
2621 * the adapter settings. TFCE and RFCE need to be explicitly set by
2622 * software when a Copper PHY is used because autonegotiation is managed
2623 * by the PHY rather than the MAC. Software must also configure these
2624 * bits when link is forced on a fiber connection.
2625 *****************************************************************************/
2626int32_t
2627e1000_force_mac_fc(struct e1000_hw *hw)
2628{
2629 uint32_t ctrl;
2630
2631 DEBUGFUNC("e1000_force_mac_fc");
2632
2633 /* Get the current configuration of the Device Control Register */
2634 ctrl = E1000_READ_REG(hw, CTRL);
2635
2636 /* Because we didn't get link via the internal auto-negotiation
2637 * mechanism (we either forced link or we got link via PHY
2638 * auto-neg), we have to manually enable/disable transmit an
2639 * receive flow control.
2640 *
2641 * The "Case" statement below enables/disable flow control
2642 * according to the "hw->fc" parameter.
2643 *
2644 * The possible values of the "fc" parameter are:
2645 * 0: Flow control is completely disabled
2646 * 1: Rx flow control is enabled (we can receive pause
2647 * frames but not send pause frames).
2648 * 2: Tx flow control is enabled (we can send pause frames
2649 * frames but we do not receive pause frames).
2650 * 3: Both Rx and TX flow control (symmetric) is enabled.
2651 * other: No other values should be possible at this point.
2652 */
2653
2654 switch (hw->fc) {
11241b10 2655 case E1000_FC_NONE:
1da177e4
LT		 2656 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2657 break;
11241b10 2658 case E1000_FC_RX_PAUSE:
1da177e4
LT		 2659 ctrl &= (~E1000_CTRL_TFCE);
2660 ctrl |= E1000_CTRL_RFCE;
2661 break;
11241b10 2662 case E1000_FC_TX_PAUSE:
1da177e4
LT		 2663 ctrl &= (~E1000_CTRL_RFCE);
2664 ctrl |= E1000_CTRL_TFCE;
2665 break;
11241b10 2666 case E1000_FC_FULL:
1da177e4
LT		 2667 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2668 break;
2669 default:
2670 DEBUGOUT("Flow control param set incorrectly\n");
2671 return -E1000_ERR_CONFIG;
2672 }
2673
2674 /* Disable TX Flow Control for 82542 (rev 2.0) */
8fc897b0 2675 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2676 ctrl &= (~E1000_CTRL_TFCE);
2677
2678 E1000_WRITE_REG(hw, CTRL, ctrl);
2679 return E1000_SUCCESS;
2680}
2681
2682/******************************************************************************
2683 * Configures flow control settings after link is established
2684 *
2685 * hw - Struct containing variables accessed by shared code
2686 *
2687 * Should be called immediately after a valid link has been established.
2688 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2689 * and autonegotiation is enabled, the MAC flow control settings will be set
2690 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2691 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2692 *****************************************************************************/
3ad2cc67 2693static int32_t
1da177e4
LT		 2694e1000_config_fc_after_link_up(struct e1000_hw *hw)
2695{
2696 int32_t ret_val;
2697 uint16_t mii_status_reg;
2698 uint16_t mii_nway_adv_reg;
2699 uint16_t mii_nway_lp_ability_reg;
2700 uint16_t speed;
2701 uint16_t duplex;
2702
2703 DEBUGFUNC("e1000_config_fc_after_link_up");
2704
2705 /* Check for the case where we have fiber media and auto-neg failed
2706 * so we had to force link. In this case, we need to force the
2707 * configuration of the MAC to match the "fc" parameter.
2708 */
8fc897b0
AK		 2709 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2710 ((hw->media_type == e1000_media_type_internal_serdes) &&
2711 (hw->autoneg_failed)) ||
2712 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1da177e4 2713 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2714 if (ret_val) {
1da177e4
LT		 2715 DEBUGOUT("Error forcing flow control settings\n");
2716 return ret_val;
2717 }
2718 }
2719
2720 /* Check for the case where we have copper media and auto-neg is
2721 * enabled. In this case, we need to check and see if Auto-Neg
2722 * has completed, and if so, how the PHY and link partner has
2723 * flow control configured.
2724 */
8fc897b0 2725 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1da177e4
LT		 2726 /* Read the MII Status Register and check to see if AutoNeg
2727 * has completed. We read this twice because this reg has
2728 * some "sticky" (latched) bits.
2729 */
2730 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2731 if (ret_val)
1da177e4
LT		 2732 return ret_val;
2733 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2734 if (ret_val)
1da177e4
LT		 2735 return ret_val;
2736
8fc897b0 2737 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 2738 /* The AutoNeg process has completed, so we now need to
2739 * read both the Auto Negotiation Advertisement Register
2740 * (Address 4) and the Auto_Negotiation Base Page Ability
2741 * Register (Address 5) to determine how flow control was
2742 * negotiated.
2743 */
2744 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2745 &mii_nway_adv_reg);
8fc897b0 2746 if (ret_val)
1da177e4
LT		 2747 return ret_val;
2748 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2749 &mii_nway_lp_ability_reg);
8fc897b0 2750 if (ret_val)
1da177e4
LT		 2751 return ret_val;
2752
2753 /* Two bits in the Auto Negotiation Advertisement Register
2754 * (Address 4) and two bits in the Auto Negotiation Base
2755 * Page Ability Register (Address 5) determine flow control
2756 * for both the PHY and the link partner. The following
2757 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2758 * 1999, describes these PAUSE resolution bits and how flow
2759 * control is determined based upon these settings.
2760 * NOTE: DC = Don't Care
2761 *
2762 * LOCAL DEVICE | LINK PARTNER
2763 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2764 *-------|---------|-------|---------|--------------------
11241b10
JK		 2765 * 0 | 0 | DC | DC | E1000_FC_NONE
2766 * 0 | 1 | 0 | DC | E1000_FC_NONE
2767 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2768 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2769 * 1 | 0 | 0 | DC | E1000_FC_NONE
2770 * 1 | DC | 1 | DC | E1000_FC_FULL
2771 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2772 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
1da177e4
LT		 2773 *
2774 */
2775 /* Are both PAUSE bits set to 1? If so, this implies
2776 * Symmetric Flow Control is enabled at both ends. The
2777 * ASM_DIR bits are irrelevant per the spec.
2778 *
2779 * For Symmetric Flow Control:
2780 *
2781 * LOCAL DEVICE | LINK PARTNER
2782 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2783 *-------|---------|-------|---------|--------------------
11241b10 2784 * 1 | DC | 1 | DC | E1000_FC_FULL
1da177e4
LT		 2785 *
2786 */
8fc897b0
AK		 2787 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2788 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1da177e4
LT		 2789 /* Now we need to check if the user selected RX ONLY
2790 * of pause frames. In this case, we had to advertise
2791 * FULL flow control because we could not advertise RX
2792 * ONLY. Hence, we must now check to see if we need to
2793 * turn OFF the TRANSMISSION of PAUSE frames.
2794 */
11241b10
JK		 2795 if (hw->original_fc == E1000_FC_FULL) {
2796 hw->fc = E1000_FC_FULL;
a42a507c 2797 DEBUGOUT("Flow Control = FULL.\n");
1da177e4 2798 } else {
11241b10 2799 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2800 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2801 }
2802 }
2803 /* For receiving PAUSE frames ONLY.
2804 *
2805 * LOCAL DEVICE | LINK PARTNER
2806 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2807 *-------|---------|-------|---------|--------------------
11241b10 2808 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
1da177e4
LT		 2809 *
2810 */
8fc897b0
AK		 2811 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2812 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2813 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2814 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
11241b10 2815 hw->fc = E1000_FC_TX_PAUSE;
a42a507c 2816 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1da177e4
LT		 2817 }
2818 /* For transmitting PAUSE frames ONLY.
2819 *
2820 * LOCAL DEVICE | LINK PARTNER
2821 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2822 *-------|---------|-------|---------|--------------------
11241b10 2823 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
1da177e4
LT		 2824 *
2825 */
8fc897b0
AK		 2826 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2827 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2828 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2829 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
11241b10 2830 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2831 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2832 }
2833 /* Per the IEEE spec, at this point flow control should be
2834 * disabled. However, we want to consider that we could
2835 * be connected to a legacy switch that doesn't advertise
2836 * desired flow control, but can be forced on the link
2837 * partner. So if we advertised no flow control, that is
2838 * what we will resolve to. If we advertised some kind of
2839 * receive capability (Rx Pause Only or Full Flow Control)
2840 * and the link partner advertised none, we will configure
2841 * ourselves to enable Rx Flow Control only. We can do
2842 * this safely for two reasons: If the link partner really
2843 * didn't want flow control enabled, and we enable Rx, no
2844 * harm done since we won't be receiving any PAUSE frames
2845 * anyway. If the intent on the link partner was to have
2846 * flow control enabled, then by us enabling RX only, we
2847 * can at least receive pause frames and process them.
2848 * This is a good idea because in most cases, since we are
2849 * predominantly a server NIC, more times than not we will
2850 * be asked to delay transmission of packets than asking
2851 * our link partner to pause transmission of frames.
2852 */
11241b10
JK		 2853 else if ((hw->original_fc == E1000_FC_NONE ||
2854 hw->original_fc == E1000_FC_TX_PAUSE) ||
8fc897b0 2855 hw->fc_strict_ieee) {
11241b10 2856 hw->fc = E1000_FC_NONE;
a42a507c 2857 DEBUGOUT("Flow Control = NONE.\n");
1da177e4 2858 } else {
11241b10 2859 hw->fc = E1000_FC_RX_PAUSE;
a42a507c 2860 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2861 }
2862
2863 /* Now we need to do one last check... If we auto-
2864 * negotiated to HALF DUPLEX, flow control should not be
2865 * enabled per IEEE 802.3 spec.
2866 */
2867 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 2868 if (ret_val) {
1da177e4
LT		 2869 DEBUGOUT("Error getting link speed and duplex\n");
2870 return ret_val;
2871 }
2872
8fc897b0 2873 if (duplex == HALF_DUPLEX)
11241b10 2874 hw->fc = E1000_FC_NONE;
1da177e4
LT		 2875
2876 /* Now we call a subroutine to actually force the MAC
2877 * controller to use the correct flow control settings.
2878 */
2879 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2880 if (ret_val) {
1da177e4
LT		 2881 DEBUGOUT("Error forcing flow control settings\n");
2882 return ret_val;
2883 }
2884 } else {
a42a507c 2885 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1da177e4
LT		 2886 }
2887 }
2888 return E1000_SUCCESS;
2889}
2890
2891/******************************************************************************
2892 * Checks to see if the link status of the hardware has changed.
2893 *
2894 * hw - Struct containing variables accessed by shared code
2895 *
2896 * Called by any function that needs to check the link status of the adapter.
2897 *****************************************************************************/
2898int32_t
2899e1000_check_for_link(struct e1000_hw *hw)
2900{
2901 uint32_t rxcw = 0;
2902 uint32_t ctrl;
2903 uint32_t status;
2904 uint32_t rctl;
2905 uint32_t icr;
2906 uint32_t signal = 0;
2907 int32_t ret_val;
2908 uint16_t phy_data;
2909
2910 DEBUGFUNC("e1000_check_for_link");
2911
2912 ctrl = E1000_READ_REG(hw, CTRL);
2913 status = E1000_READ_REG(hw, STATUS);
2914
2915 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2916 * set when the optics detect a signal. On older adapters, it will be
2917 * cleared when there is a signal. This applies to fiber media only.
2918 */
8fc897b0
AK		 2919 if ((hw->media_type == e1000_media_type_fiber) ||
2920 (hw->media_type == e1000_media_type_internal_serdes)) {
1da177e4
LT		 2921 rxcw = E1000_READ_REG(hw, RXCW);
2922
8fc897b0 2923 if (hw->media_type == e1000_media_type_fiber) {
1da177e4 2924 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
8fc897b0 2925 if (status & E1000_STATUS_LU)
1da177e4
LT		 2926 hw->get_link_status = FALSE;
2927 }
2928 }
2929
2930 /* If we have a copper PHY then we only want to go out to the PHY
2931 * registers to see if Auto-Neg has completed and/or if our link
2932 * status has changed. The get_link_status flag will be set if we
2933 * receive a Link Status Change interrupt or we have Rx Sequence
2934 * Errors.
2935 */
8fc897b0 2936 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1da177e4
LT		 2937 /* First we want to see if the MII Status Register reports
2938 * link. If so, then we want to get the current speed/duplex
2939 * of the PHY.
2940 * Read the register twice since the link bit is sticky.
2941 */
2942 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2943 if (ret_val)
1da177e4
LT		 2944 return ret_val;
2945 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2946 if (ret_val)
1da177e4
LT		 2947 return ret_val;
2948
8fc897b0 2949 if (phy_data & MII_SR_LINK_STATUS) {
1da177e4
LT		 2950 hw->get_link_status = FALSE;
2951 /* Check if there was DownShift, must be checked immediately after
2952 * link-up */
2953 e1000_check_downshift(hw);
2954
2955 /* If we are on 82544 or 82543 silicon and speed/duplex
2956 * are forced to 10H or 10F, then we will implement the polarity
2957 * reversal workaround. We disable interrupts first, and upon
2958 * returning, place the devices interrupt state to its previous
2959 * value except for the link status change interrupt which will
2960 * happen due to the execution of this workaround.
2961 */
2962
8fc897b0
AK		 2963 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2964 (!hw->autoneg) &&
2965 (hw->forced_speed_duplex == e1000_10_full ||
2966 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4
LT		 2967 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2968 ret_val = e1000_polarity_reversal_workaround(hw);
2969 icr = E1000_READ_REG(hw, ICR);
2970 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2971 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2972 }
2973
2974 } else {
2975 /* No link detected */
2976 e1000_config_dsp_after_link_change(hw, FALSE);
2977 return 0;
2978 }
2979
2980 /* If we are forcing speed/duplex, then we simply return since
2981 * we have already determined whether we have link or not.
2982 */
8fc897b0 2983 if (!hw->autoneg) return -E1000_ERR_CONFIG;
1da177e4
LT		 2984
2985 /* optimize the dsp settings for the igp phy */
2986 e1000_config_dsp_after_link_change(hw, TRUE);
2987
2988 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2989 * have Si on board that is 82544 or newer, Auto
2990 * Speed Detection takes care of MAC speed/duplex
2991 * configuration. So we only need to configure Collision
2992 * Distance in the MAC. Otherwise, we need to force
2993 * speed/duplex on the MAC to the current PHY speed/duplex
2994 * settings.
2995 */
8fc897b0 2996 if (hw->mac_type >= e1000_82544)
1da177e4
LT		 2997 e1000_config_collision_dist(hw);
2998 else {
2999 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 3000 if (ret_val) {
1da177e4
LT		 3001 DEBUGOUT("Error configuring MAC to PHY settings\n");
3002 return ret_val;
3003 }
3004 }
3005
3006 /* Configure Flow Control now that Auto-Neg has completed. First, we
3007 * need to restore the desired flow control settings because we may
3008 * have had to re-autoneg with a different link partner.
3009 */
3010 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 3011 if (ret_val) {
1da177e4
LT		 3012 DEBUGOUT("Error configuring flow control\n");
3013 return ret_val;
3014 }
3015
3016 /* At this point we know that we are on copper and we have
3017 * auto-negotiated link. These are conditions for checking the link
3018 * partner capability register. We use the link speed to determine if
3019 * TBI compatibility needs to be turned on or off. If the link is not
3020 * at gigabit speed, then TBI compatibility is not needed. If we are
3021 * at gigabit speed, we turn on TBI compatibility.
3022 */
8fc897b0 3023 if (hw->tbi_compatibility_en) {
1da177e4 3024 uint16_t speed, duplex;
592600a0
AK		 3025 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3026 if (ret_val) {
3027 DEBUGOUT("Error getting link speed and duplex\n");
3028 return ret_val;
3029 }
3030 if (speed != SPEED_1000) {
1da177e4
LT		 3031 /* If link speed is not set to gigabit speed, we do not need
3032 * to enable TBI compatibility.
3033 */
8fc897b0 3034 if (hw->tbi_compatibility_on) {
1da177e4
LT		 3035 /* If we previously were in the mode, turn it off. */
3036 rctl = E1000_READ_REG(hw, RCTL);
3037 rctl &= ~E1000_RCTL_SBP;
3038 E1000_WRITE_REG(hw, RCTL, rctl);
3039 hw->tbi_compatibility_on = FALSE;
3040 }
3041 } else {
3042 /* If TBI compatibility is was previously off, turn it on. For
3043 * compatibility with a TBI link partner, we will store bad
3044 * packets. Some frames have an additional byte on the end and
3045 * will look like CRC errors to to the hardware.
3046 */
8fc897b0 3047 if (!hw->tbi_compatibility_on) {
1da177e4
LT		 3048 hw->tbi_compatibility_on = TRUE;
3049 rctl = E1000_READ_REG(hw, RCTL);
3050 rctl |= E1000_RCTL_SBP;
3051 E1000_WRITE_REG(hw, RCTL, rctl);
3052 }
3053 }
3054 }
3055 }
3056 /* If we don't have link (auto-negotiation failed or link partner cannot
3057 * auto-negotiate), the cable is plugged in (we have signal), and our
3058 * link partner is not trying to auto-negotiate with us (we are receiving
3059 * idles or data), we need to force link up. We also need to give
3060 * auto-negotiation time to complete, in case the cable was just plugged
3061 * in. The autoneg_failed flag does this.
3062 */
8fc897b0 3063 else if ((((hw->media_type == e1000_media_type_fiber) &&
1da177e4 3064 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
8fc897b0
AK		 3065 (hw->media_type == e1000_media_type_internal_serdes)) &&
3066 (!(status & E1000_STATUS_LU)) &&
3067 (!(rxcw & E1000_RXCW_C))) {
3068 if (hw->autoneg_failed == 0) {
1da177e4
LT		 3069 hw->autoneg_failed = 1;
3070 return 0;
3071 }
a42a507c 3072 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1da177e4
LT		 3073
3074 /* Disable auto-negotiation in the TXCW register */
3075 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3076
3077 /* Force link-up and also force full-duplex. */
3078 ctrl = E1000_READ_REG(hw, CTRL);
3079 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3080 E1000_WRITE_REG(hw, CTRL, ctrl);
3081
3082 /* Configure Flow Control after forcing link up. */
3083 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 3084 if (ret_val) {
1da177e4
LT		 3085 DEBUGOUT("Error configuring flow control\n");
3086 return ret_val;
3087 }
3088 }
3089 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3090 * auto-negotiation in the TXCW register and disable forced link in the
3091 * Device Control register in an attempt to auto-negotiate with our link
3092 * partner.
3093 */
8fc897b0
AK		 3094 else if (((hw->media_type == e1000_media_type_fiber) ||
3095 (hw->media_type == e1000_media_type_internal_serdes)) &&
3096 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
a42a507c 3097 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1da177e4
LT		 3098 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3099 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3100
3101 hw->serdes_link_down = FALSE;
3102 }
3103 /* If we force link for non-auto-negotiation switch, check link status
3104 * based on MAC synchronization for internal serdes media type.
3105 */
8fc897b0
AK		 3106 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3107 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3108 /* SYNCH bit and IV bit are sticky. */
3109 udelay(10);
8fc897b0
AK		 3110 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3111 if (!(rxcw & E1000_RXCW_IV)) {
1da177e4
LT		 3112 hw->serdes_link_down = FALSE;
3113 DEBUGOUT("SERDES: Link is up.\n");
3114 }
3115 } else {
3116 hw->serdes_link_down = TRUE;
3117 DEBUGOUT("SERDES: Link is down.\n");
3118 }
3119 }
8fc897b0
AK		 3120 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3121 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3122 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3123 }
3124 return E1000_SUCCESS;
3125}
3126
3127/******************************************************************************
3128 * Detects the current speed and duplex settings of the hardware.
3129 *
3130 * hw - Struct containing variables accessed by shared code
3131 * speed - Speed of the connection
3132 * duplex - Duplex setting of the connection
3133 *****************************************************************************/
3134int32_t
3135e1000_get_speed_and_duplex(struct e1000_hw *hw,
3136 uint16_t *speed,
3137 uint16_t *duplex)
3138{
3139 uint32_t status;
3140 int32_t ret_val;
3141 uint16_t phy_data;
3142
3143 DEBUGFUNC("e1000_get_speed_and_duplex");
3144
8fc897b0 3145 if (hw->mac_type >= e1000_82543) {
1da177e4 3146 status = E1000_READ_REG(hw, STATUS);
8fc897b0 3147 if (status & E1000_STATUS_SPEED_1000) {
1da177e4
LT		 3148 *speed = SPEED_1000;
3149 DEBUGOUT("1000 Mbs, ");
8fc897b0 3150 } else if (status & E1000_STATUS_SPEED_100) {
1da177e4
LT		 3151 *speed = SPEED_100;
3152 DEBUGOUT("100 Mbs, ");
3153 } else {
3154 *speed = SPEED_10;
3155 DEBUGOUT("10 Mbs, ");
3156 }
3157
8fc897b0 3158 if (status & E1000_STATUS_FD) {
1da177e4 3159 *duplex = FULL_DUPLEX;
a42a507c 3160 DEBUGOUT("Full Duplex\n");
1da177e4
LT		 3161 } else {
3162 *duplex = HALF_DUPLEX;
a42a507c 3163 DEBUGOUT(" Half Duplex\n");
1da177e4
LT		 3164 }
3165 } else {
a42a507c 3166 DEBUGOUT("1000 Mbs, Full Duplex\n");
1da177e4
LT		 3167 *speed = SPEED_1000;
3168 *duplex = FULL_DUPLEX;
3169 }
3170
3171 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3172 * if it is operating at half duplex. Here we set the duplex settings to
3173 * match the duplex in the link partner's capabilities.
3174 */
8fc897b0 3175 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
1da177e4 3176 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
8fc897b0 3177 if (ret_val)
1da177e4
LT		 3178 return ret_val;
3179
8fc897b0 3180 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
1da177e4
LT		 3181 *duplex = HALF_DUPLEX;
3182 else {
3183 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
8fc897b0 3184 if (ret_val)
1da177e4 3185 return ret_val;
8fc897b0 3186 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
1da177e4
LT		 3187 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3188 *duplex = HALF_DUPLEX;
3189 }
3190 }
3191
76c224bc 3192 if ((hw->mac_type == e1000_80003es2lan) &&
6418ecc6
JK		 3193 (hw->media_type == e1000_media_type_copper)) {
3194 if (*speed == SPEED_1000)
3195 ret_val = e1000_configure_kmrn_for_1000(hw);
3196 else
cd94dd0b
AK		 3197 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3198 if (ret_val)
3199 return ret_val;
3200 }
3201
3202 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3203 ret_val = e1000_kumeran_lock_loss_workaround(hw);
6418ecc6
JK		 3204 if (ret_val)
3205 return ret_val;
3206 }
3207
1da177e4
LT		 3208 return E1000_SUCCESS;
3209}
3210
3211/******************************************************************************
3212* Blocks until autoneg completes or times out (~4.5 seconds)
3213*
3214* hw - Struct containing variables accessed by shared code
3215******************************************************************************/
3ad2cc67 3216static int32_t
1da177e4
LT		 3217e1000_wait_autoneg(struct e1000_hw *hw)
3218{
3219 int32_t ret_val;
3220 uint16_t i;
3221 uint16_t phy_data;
3222
3223 DEBUGFUNC("e1000_wait_autoneg");
3224 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3225
3226 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 3227 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
1da177e4
LT		 3228 /* Read the MII Status Register and wait for Auto-Neg
3229 * Complete bit to be set.
3230 */
3231 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3232 if (ret_val)
1da177e4
LT		 3233 return ret_val;
3234 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3235 if (ret_val)
1da177e4 3236 return ret_val;
8fc897b0 3237 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 3238 return E1000_SUCCESS;
3239 }
f8ec4733 3240 msleep(100);
1da177e4
LT		 3241 }
3242 return E1000_SUCCESS;
3243}
3244
3245/******************************************************************************
3246* Raises the Management Data Clock
3247*
3248* hw - Struct containing variables accessed by shared code
3249* ctrl - Device control register's current value
3250******************************************************************************/
3251static void
3252e1000_raise_mdi_clk(struct e1000_hw *hw,
3253 uint32_t *ctrl)
3254{
3255 /* Raise the clock input to the Management Data Clock (by setting the MDC
3256 * bit), and then delay 10 microseconds.
3257 */
3258 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3259 E1000_WRITE_FLUSH(hw);
3260 udelay(10);
3261}
3262
3263/******************************************************************************
3264* Lowers the Management Data Clock
3265*
3266* hw - Struct containing variables accessed by shared code
3267* ctrl - Device control register's current value
3268******************************************************************************/
3269static void
3270e1000_lower_mdi_clk(struct e1000_hw *hw,
3271 uint32_t *ctrl)
3272{
3273 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3274 * bit), and then delay 10 microseconds.
3275 */
3276 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3277 E1000_WRITE_FLUSH(hw);
3278 udelay(10);
3279}
3280
3281/******************************************************************************
3282* Shifts data bits out to the PHY
3283*
3284* hw - Struct containing variables accessed by shared code
3285* data - Data to send out to the PHY
3286* count - Number of bits to shift out
3287*
3288* Bits are shifted out in MSB to LSB order.
3289******************************************************************************/
3290static void
3291e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3292 uint32_t data,
3293 uint16_t count)
3294{
3295 uint32_t ctrl;
3296 uint32_t mask;
3297
3298 /* We need to shift "count" number of bits out to the PHY. So, the value
3299 * in the "data" parameter will be shifted out to the PHY one bit at a
3300 * time. In order to do this, "data" must be broken down into bits.
3301 */
3302 mask = 0x01;
3303 mask <<= (count - 1);
3304
3305 ctrl = E1000_READ_REG(hw, CTRL);
3306
3307 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3308 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3309
8fc897b0 3310 while (mask) {
1da177e4
LT		 3311 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3312 * then raising and lowering the Management Data Clock. A "0" is
3313 * shifted out to the PHY by setting the MDIO bit to "0" and then
3314 * raising and lowering the clock.
3315 */
8fc897b0
AK		 3316 if (data & mask)
3317 ctrl |= E1000_CTRL_MDIO;
3318 else
3319 ctrl &= ~E1000_CTRL_MDIO;
1da177e4
LT		 3320
3321 E1000_WRITE_REG(hw, CTRL, ctrl);
3322 E1000_WRITE_FLUSH(hw);
3323
3324 udelay(10);
3325
3326 e1000_raise_mdi_clk(hw, &ctrl);
3327 e1000_lower_mdi_clk(hw, &ctrl);
3328
3329 mask = mask >> 1;
3330 }
3331}
3332
3333/******************************************************************************
3334* Shifts data bits in from the PHY
3335*
3336* hw - Struct containing variables accessed by shared code
3337*
3338* Bits are shifted in in MSB to LSB order.
3339******************************************************************************/
3340static uint16_t
3341e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3342{
3343 uint32_t ctrl;
3344 uint16_t data = 0;
3345 uint8_t i;
3346
3347 /* In order to read a register from the PHY, we need to shift in a total
3348 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3349 * to avoid contention on the MDIO pin when a read operation is performed.
3350 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3351 * by raising the input to the Management Data Clock (setting the MDC bit),
3352 * and then reading the value of the MDIO bit.
3353 */
3354 ctrl = E1000_READ_REG(hw, CTRL);
3355
3356 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3357 ctrl &= ~E1000_CTRL_MDIO_DIR;
3358 ctrl &= ~E1000_CTRL_MDIO;
3359
3360 E1000_WRITE_REG(hw, CTRL, ctrl);
3361 E1000_WRITE_FLUSH(hw);
3362
3363 /* Raise and Lower the clock before reading in the data. This accounts for
3364 * the turnaround bits. The first clock occurred when we clocked out the
3365 * last bit of the Register Address.
3366 */
3367 e1000_raise_mdi_clk(hw, &ctrl);
3368 e1000_lower_mdi_clk(hw, &ctrl);
3369
8fc897b0 3370 for (data = 0, i = 0; i < 16; i++) {
1da177e4
LT		 3371 data = data << 1;
3372 e1000_raise_mdi_clk(hw, &ctrl);
3373 ctrl = E1000_READ_REG(hw, CTRL);
3374 /* Check to see if we shifted in a "1". */
8fc897b0
AK		 3375 if (ctrl & E1000_CTRL_MDIO)
3376 data |= 1;
1da177e4
LT		 3377 e1000_lower_mdi_clk(hw, &ctrl);
3378 }
3379
3380 e1000_raise_mdi_clk(hw, &ctrl);
3381 e1000_lower_mdi_clk(hw, &ctrl);
3382
3383 return data;
3384}
3385
e4c780b1 3386static int32_t
6418ecc6
JK		 3387e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3388{
3389 uint32_t swfw_sync = 0;
3390 uint32_t swmask = mask;
3391 uint32_t fwmask = mask << 16;
3392 int32_t timeout = 200;
3393
3394 DEBUGFUNC("e1000_swfw_sync_acquire");
3395
cd94dd0b
AK		 3396 if (hw->swfwhw_semaphore_present)
3397 return e1000_get_software_flag(hw);
3398
6418ecc6
JK		 3399 if (!hw->swfw_sync_present)
3400 return e1000_get_hw_eeprom_semaphore(hw);
3401
8fc897b0 3402 while (timeout) {
6418ecc6
JK		 3403 if (e1000_get_hw_eeprom_semaphore(hw))
3404 return -E1000_ERR_SWFW_SYNC;
3405
3406 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3407 if (!(swfw_sync & (fwmask | swmask))) {
3408 break;
3409 }
3410
3411 /* firmware currently using resource (fwmask) */
3412 /* or other software thread currently using resource (swmask) */
3413 e1000_put_hw_eeprom_semaphore(hw);
f8ec4733 3414 mdelay(5);
6418ecc6
JK		 3415 timeout--;
3416 }
3417
3418 if (!timeout) {
3419 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3420 return -E1000_ERR_SWFW_SYNC;
3421 }
3422
3423 swfw_sync |= swmask;
3424 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3425
3426 e1000_put_hw_eeprom_semaphore(hw);
3427 return E1000_SUCCESS;
3428}
3429
e4c780b1 3430static void
6418ecc6
JK		 3431e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3432{
3433 uint32_t swfw_sync;
3434 uint32_t swmask = mask;
3435
3436 DEBUGFUNC("e1000_swfw_sync_release");
3437
cd94dd0b
AK		 3438 if (hw->swfwhw_semaphore_present) {
3439 e1000_release_software_flag(hw);
3440 return;
3441 }
3442
6418ecc6
JK		 3443 if (!hw->swfw_sync_present) {
3444 e1000_put_hw_eeprom_semaphore(hw);
3445 return;
3446 }
3447
3448 /* if (e1000_get_hw_eeprom_semaphore(hw))
3449 * return -E1000_ERR_SWFW_SYNC; */
3450 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3451 /* empty */
3452
3453 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3454 swfw_sync &= ~swmask;
3455 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3456
3457 e1000_put_hw_eeprom_semaphore(hw);
3458}
3459
1da177e4
LT		 3460/*****************************************************************************
3461* Reads the value from a PHY register, if the value is on a specific non zero
3462* page, sets the page first.
3463* hw - Struct containing variables accessed by shared code
3464* reg_addr - address of the PHY register to read
3465******************************************************************************/
3466int32_t
3467e1000_read_phy_reg(struct e1000_hw *hw,
3468 uint32_t reg_addr,
3469 uint16_t *phy_data)
3470{
3471 uint32_t ret_val;
6418ecc6 3472 uint16_t swfw;
1da177e4
LT		 3473
3474 DEBUGFUNC("e1000_read_phy_reg");
3475
6418ecc6
JK		 3476 if ((hw->mac_type == e1000_80003es2lan) &&
3477 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3478 swfw = E1000_SWFW_PHY1_SM;
3479 } else {
3480 swfw = E1000_SWFW_PHY0_SM;
3481 }
3482 if (e1000_swfw_sync_acquire(hw, swfw))
3483 return -E1000_ERR_SWFW_SYNC;
3484
cd94dd0b
AK		 3485 if ((hw->phy_type == e1000_phy_igp ||
3486 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3487 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3488 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3489 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3490 (uint16_t)reg_addr);
8fc897b0 3491 if (ret_val) {
6418ecc6 3492 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3493 return ret_val;
3494 }
6418ecc6
JK		 3495 } else if (hw->phy_type == e1000_phy_gg82563) {
3496 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3497 (hw->mac_type == e1000_80003es2lan)) {
3498 /* Select Configuration Page */
3499 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3500 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3501 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3502 } else {
3503 /* Use Alternative Page Select register to access
3504 * registers 30 and 31
3505 */
3506 ret_val = e1000_write_phy_reg_ex(hw,
3507 GG82563_PHY_PAGE_SELECT_ALT,
3508 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3509 }
3510
3511 if (ret_val) {
3512 e1000_swfw_sync_release(hw, swfw);
3513 return ret_val;
3514 }
3515 }
1da177e4
LT		 3516 }
3517
3518 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3519 phy_data);
3520
6418ecc6 3521 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3522 return ret_val;
3523}
3524
35574764
NN		 3525static int32_t
3526e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
1da177e4
LT		 3527 uint16_t *phy_data)
3528{
3529 uint32_t i;
3530 uint32_t mdic = 0;
3531 const uint32_t phy_addr = 1;
3532
3533 DEBUGFUNC("e1000_read_phy_reg_ex");
3534
8fc897b0 3535 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3536 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3537 return -E1000_ERR_PARAM;
3538 }
3539
8fc897b0 3540 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3541 /* Set up Op-code, Phy Address, and register address in the MDI
3542 * Control register. The MAC will take care of interfacing with the
3543 * PHY to retrieve the desired data.
3544 */
3545 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3546 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3547 (E1000_MDIC_OP_READ));
3548
3549 E1000_WRITE_REG(hw, MDIC, mdic);
3550
3551 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3552 for (i = 0; i < 64; i++) {
1da177e4
LT		 3553 udelay(50);
3554 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3555 if (mdic & E1000_MDIC_READY) break;
1da177e4 3556 }
8fc897b0 3557 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3558 DEBUGOUT("MDI Read did not complete\n");
3559 return -E1000_ERR_PHY;
3560 }
8fc897b0 3561 if (mdic & E1000_MDIC_ERROR) {
1da177e4
LT		 3562 DEBUGOUT("MDI Error\n");
3563 return -E1000_ERR_PHY;
3564 }
3565 *phy_data = (uint16_t) mdic;
3566 } else {
3567 /* We must first send a preamble through the MDIO pin to signal the
3568 * beginning of an MII instruction. This is done by sending 32
3569 * consecutive "1" bits.
3570 */
3571 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3572
3573 /* Now combine the next few fields that are required for a read
3574 * operation. We use this method instead of calling the
3575 * e1000_shift_out_mdi_bits routine five different times. The format of
3576 * a MII read instruction consists of a shift out of 14 bits and is
3577 * defined as follows:
3578 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3579 * followed by a shift in of 18 bits. This first two bits shifted in
3580 * are TurnAround bits used to avoid contention on the MDIO pin when a
3581 * READ operation is performed. These two bits are thrown away
3582 * followed by a shift in of 16 bits which contains the desired data.
3583 */
3584 mdic = ((reg_addr) | (phy_addr << 5) |
3585 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3586
3587 e1000_shift_out_mdi_bits(hw, mdic, 14);
3588
3589 /* Now that we've shifted out the read command to the MII, we need to
3590 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3591 * register address.
3592 */
3593 *phy_data = e1000_shift_in_mdi_bits(hw);
3594 }
3595 return E1000_SUCCESS;
3596}
3597
3598/******************************************************************************
3599* Writes a value to a PHY register
3600*
3601* hw - Struct containing variables accessed by shared code
3602* reg_addr - address of the PHY register to write
3603* data - data to write to the PHY
3604******************************************************************************/
3605int32_t
35574764 3606e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
1da177e4
LT		 3607 uint16_t phy_data)
3608{
3609 uint32_t ret_val;
6418ecc6 3610 uint16_t swfw;
1da177e4
LT		 3611
3612 DEBUGFUNC("e1000_write_phy_reg");
3613
6418ecc6
JK		 3614 if ((hw->mac_type == e1000_80003es2lan) &&
3615 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3616 swfw = E1000_SWFW_PHY1_SM;
3617 } else {
3618 swfw = E1000_SWFW_PHY0_SM;
3619 }
3620 if (e1000_swfw_sync_acquire(hw, swfw))
3621 return -E1000_ERR_SWFW_SYNC;
3622
cd94dd0b
AK		 3623 if ((hw->phy_type == e1000_phy_igp ||
3624 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3625 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3626 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3627 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3628 (uint16_t)reg_addr);
8fc897b0 3629 if (ret_val) {
6418ecc6 3630 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3631 return ret_val;
3632 }
6418ecc6
JK		 3633 } else if (hw->phy_type == e1000_phy_gg82563) {
3634 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3635 (hw->mac_type == e1000_80003es2lan)) {
3636 /* Select Configuration Page */
3637 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3638 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3639 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3640 } else {
3641 /* Use Alternative Page Select register to access
3642 * registers 30 and 31
3643 */
3644 ret_val = e1000_write_phy_reg_ex(hw,
3645 GG82563_PHY_PAGE_SELECT_ALT,
3646 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3647 }
3648
3649 if (ret_val) {
3650 e1000_swfw_sync_release(hw, swfw);
3651 return ret_val;
3652 }
3653 }
1da177e4
LT		 3654 }
3655
3656 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3657 phy_data);
3658
6418ecc6 3659 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3660 return ret_val;
3661}
3662
35574764
NN		 3663static int32_t
3664e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3665 uint16_t phy_data)
1da177e4
LT		 3666{
3667 uint32_t i;
3668 uint32_t mdic = 0;
3669 const uint32_t phy_addr = 1;
3670
3671 DEBUGFUNC("e1000_write_phy_reg_ex");
3672
8fc897b0 3673 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3674 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3675 return -E1000_ERR_PARAM;
3676 }
3677
8fc897b0 3678 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3679 /* Set up Op-code, Phy Address, register address, and data intended
3680 * for the PHY register in the MDI Control register. The MAC will take
3681 * care of interfacing with the PHY to send the desired data.
3682 */
3683 mdic = (((uint32_t) phy_data) |
3684 (reg_addr << E1000_MDIC_REG_SHIFT) |
3685 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3686 (E1000_MDIC_OP_WRITE));
3687
3688 E1000_WRITE_REG(hw, MDIC, mdic);
3689
3690 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3691 for (i = 0; i < 641; i++) {
1da177e4
LT		 3692 udelay(5);
3693 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3694 if (mdic & E1000_MDIC_READY) break;
1da177e4 3695 }
8fc897b0 3696 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3697 DEBUGOUT("MDI Write did not complete\n");
3698 return -E1000_ERR_PHY;
3699 }
3700 } else {
3701 /* We'll need to use the SW defined pins to shift the write command
3702 * out to the PHY. We first send a preamble to the PHY to signal the
3703 * beginning of the MII instruction. This is done by sending 32
3704 * consecutive "1" bits.
3705 */
3706 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3707
3708 /* Now combine the remaining required fields that will indicate a
3709 * write operation. We use this method instead of calling the
3710 * e1000_shift_out_mdi_bits routine for each field in the command. The
3711 * format of a MII write instruction is as follows:
3712 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3713 */
3714 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3715 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3716 mdic <<= 16;
3717 mdic |= (uint32_t) phy_data;
3718
3719 e1000_shift_out_mdi_bits(hw, mdic, 32);
3720 }
3721
3722 return E1000_SUCCESS;
3723}
3724
e4c780b1 3725static int32_t
6418ecc6
JK		 3726e1000_read_kmrn_reg(struct e1000_hw *hw,
3727 uint32_t reg_addr,
3728 uint16_t *data)
3729{
3730 uint32_t reg_val;
3731 uint16_t swfw;
3732 DEBUGFUNC("e1000_read_kmrn_reg");
3733
3734 if ((hw->mac_type == e1000_80003es2lan) &&
3735 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3736 swfw = E1000_SWFW_PHY1_SM;
3737 } else {
3738 swfw = E1000_SWFW_PHY0_SM;
3739 }
3740 if (e1000_swfw_sync_acquire(hw, swfw))
3741 return -E1000_ERR_SWFW_SYNC;
3742
3743 /* Write register address */
3744 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3745 E1000_KUMCTRLSTA_OFFSET) |
3746 E1000_KUMCTRLSTA_REN;
3747 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3748 udelay(2);
3749
3750 /* Read the data returned */
3751 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3752 *data = (uint16_t)reg_val;
3753
3754 e1000_swfw_sync_release(hw, swfw);
3755 return E1000_SUCCESS;
3756}
3757
e4c780b1 3758static int32_t
6418ecc6
JK		 3759e1000_write_kmrn_reg(struct e1000_hw *hw,
3760 uint32_t reg_addr,
3761 uint16_t data)
3762{
3763 uint32_t reg_val;
3764 uint16_t swfw;
3765 DEBUGFUNC("e1000_write_kmrn_reg");
3766
3767 if ((hw->mac_type == e1000_80003es2lan) &&
3768 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3769 swfw = E1000_SWFW_PHY1_SM;
3770 } else {
3771 swfw = E1000_SWFW_PHY0_SM;
3772 }
3773 if (e1000_swfw_sync_acquire(hw, swfw))
3774 return -E1000_ERR_SWFW_SYNC;
3775
3776 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3777 E1000_KUMCTRLSTA_OFFSET) | data;
3778 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3779 udelay(2);
3780
3781 e1000_swfw_sync_release(hw, swfw);
3782 return E1000_SUCCESS;
3783}
2d7edb92 3784
1da177e4
LT		 3785/******************************************************************************
3786* Returns the PHY to the power-on reset state
3787*
3788* hw - Struct containing variables accessed by shared code
3789******************************************************************************/
2d7edb92 3790int32_t
1da177e4
LT		 3791e1000_phy_hw_reset(struct e1000_hw *hw)
3792{
3793 uint32_t ctrl, ctrl_ext;
3794 uint32_t led_ctrl;
2d7edb92 3795 int32_t ret_val;
6418ecc6 3796 uint16_t swfw;
1da177e4
LT		 3797
3798 DEBUGFUNC("e1000_phy_hw_reset");
3799
2d7edb92
MC		 3800 /* In the case of the phy reset being blocked, it's not an error, we
3801 * simply return success without performing the reset. */
3802 ret_val = e1000_check_phy_reset_block(hw);
3803 if (ret_val)
3804 return E1000_SUCCESS;
3805
1da177e4
LT		 3806 DEBUGOUT("Resetting Phy...\n");
3807
8fc897b0 3808 if (hw->mac_type > e1000_82543) {
6418ecc6
JK		 3809 if ((hw->mac_type == e1000_80003es2lan) &&
3810 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3811 swfw = E1000_SWFW_PHY1_SM;
3812 } else {
3813 swfw = E1000_SWFW_PHY0_SM;
3814 }
3815 if (e1000_swfw_sync_acquire(hw, swfw)) {
2a88c173 3816 DEBUGOUT("Unable to acquire swfw sync\n");
6418ecc6
JK		 3817 return -E1000_ERR_SWFW_SYNC;
3818 }
1da177e4
LT		 3819 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3820 * bit. Then, take it out of reset.
76c224bc 3821 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
fd803241 3822 * and deassert. For e1000_82571 hardware and later, we instead delay
0f15a8fa 3823 * for 50us between and 10ms after the deassertion.
1da177e4
LT		 3824 */
3825 ctrl = E1000_READ_REG(hw, CTRL);
3826 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3827 E1000_WRITE_FLUSH(hw);
76c224bc
AK		 3828
3829 if (hw->mac_type < e1000_82571)
f8ec4733 3830 msleep(10);
b55ccb35
JK		 3831 else
3832 udelay(100);
76c224bc 3833
1da177e4
LT		 3834 E1000_WRITE_REG(hw, CTRL, ctrl);
3835 E1000_WRITE_FLUSH(hw);
76c224bc 3836
fd803241 3837 if (hw->mac_type >= e1000_82571)
f8ec4733 3838 mdelay(10);
35574764 3839
6418ecc6 3840 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3841 } else {
3842 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3843 * bit to put the PHY into reset. Then, take it out of reset.
3844 */
3845 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3846 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3847 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3848 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3849 E1000_WRITE_FLUSH(hw);
f8ec4733 3850 msleep(10);
1da177e4
LT		 3851 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3852 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3853 E1000_WRITE_FLUSH(hw);
3854 }
3855 udelay(150);
3856
8fc897b0 3857 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 3858 /* Configure activity LED after PHY reset */
3859 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3860 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3861 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3862 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3863 }
2d7edb92
MC		 3864
3865 /* Wait for FW to finish PHY configuration. */
3866 ret_val = e1000_get_phy_cfg_done(hw);
8fc897b0
AK		 3867 if (ret_val != E1000_SUCCESS)
3868 return ret_val;
6418ecc6 3869 e1000_release_software_semaphore(hw);
2d7edb92 3870
8fc897b0
AK		 3871 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3872 ret_val = e1000_init_lcd_from_nvm(hw);
3873
2d7edb92 3874 return ret_val;
1da177e4
LT		 3875}
3876
3877/******************************************************************************
3878* Resets the PHY
3879*
3880* hw - Struct containing variables accessed by shared code
3881*
0779bf2d 3882* Sets bit 15 of the MII Control register
1da177e4
LT		 3883******************************************************************************/
3884int32_t
3885e1000_phy_reset(struct e1000_hw *hw)
3886{
3887 int32_t ret_val;
3888 uint16_t phy_data;
3889
3890 DEBUGFUNC("e1000_phy_reset");
3891
2d7edb92
MC		 3892 /* In the case of the phy reset being blocked, it's not an error, we
3893 * simply return success without performing the reset. */
3894 ret_val = e1000_check_phy_reset_block(hw);
3895 if (ret_val)
3896 return E1000_SUCCESS;
3897
2a88c173
JK		 3898 switch (hw->phy_type) {
3899 case e1000_phy_igp:
3900 case e1000_phy_igp_2:
3901 case e1000_phy_igp_3:
3902 case e1000_phy_ife:
2d7edb92 3903 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 3904 if (ret_val)
2d7edb92
MC		 3905 return ret_val;
3906 break;
3907 default:
1da177e4 3908 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 3909 if (ret_val)
1da177e4
LT		 3910 return ret_val;
3911
3912 phy_data |= MII_CR_RESET;
3913 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 3914 if (ret_val)
1da177e4
LT		 3915 return ret_val;
3916
3917 udelay(1);
2d7edb92
MC		 3918 break;
3919 }
1da177e4 3920
8fc897b0 3921 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
1da177e4
LT		 3922 e1000_phy_init_script(hw);
3923
3924 return E1000_SUCCESS;
3925}
3926
d37ea5d5
AK		 3927/******************************************************************************
3928* Work-around for 82566 power-down: on D3 entry-
3929* 1) disable gigabit link
3930* 2) write VR power-down enable
3931* 3) read it back
3932* if successful continue, else issue LCD reset and repeat
3933*
3934* hw - struct containing variables accessed by shared code
3935******************************************************************************/
3936void
3937e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3938{
3939 int32_t reg;
3940 uint16_t phy_data;
3941 int32_t retry = 0;
3942
3943 DEBUGFUNC("e1000_phy_powerdown_workaround");
3944
3945 if (hw->phy_type != e1000_phy_igp_3)
3946 return;
3947
3948 do {
3949 /* Disable link */
3950 reg = E1000_READ_REG(hw, PHY_CTRL);
3951 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3952 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3953
070f6ffb 3954 /* Write VR power-down enable - bits 9:8 should be 10b */
d37ea5d5 3955 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
070f6ffb
JK		 3956 phy_data |= (1 << 9);
3957 phy_data &= ~(1 << 8);
3958 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
d37ea5d5
AK		 3959
3960 /* Read it back and test */
3961 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
070f6ffb 3962 if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry)
d37ea5d5
AK		 3963 break;
3964
3965 /* Issue PHY reset and repeat at most one more time */
3966 reg = E1000_READ_REG(hw, CTRL);
3967 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3968 retry++;
3969 } while (retry);
3970
3971 return;
3972
3973}
3974
3975/******************************************************************************
3976* Work-around for 82566 Kumeran PCS lock loss:
3977* On link status change (i.e. PCI reset, speed change) and link is up and
3978* speed is gigabit-
3979* 0) if workaround is optionally disabled do nothing
3980* 1) wait 1ms for Kumeran link to come up
3981* 2) check Kumeran Diagnostic register PCS lock loss bit
3982* 3) if not set the link is locked (all is good), otherwise...
3983* 4) reset the PHY
3984* 5) repeat up to 10 times
3985* Note: this is only called for IGP3 copper when speed is 1gb.
3986*
3987* hw - struct containing variables accessed by shared code
3988******************************************************************************/
e4c780b1 3989static int32_t
d37ea5d5
AK		 3990e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3991{
3992 int32_t ret_val;
3993 int32_t reg;
3994 int32_t cnt;
3995 uint16_t phy_data;
3996
3997 if (hw->kmrn_lock_loss_workaround_disabled)
3998 return E1000_SUCCESS;
3999
8fc897b0
AK		 4000 /* Make sure link is up before proceeding. If not just return.
4001 * Attempting this while link is negotiating fouled up link
d37ea5d5
AK		 4002 * stability */
4003 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4004 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4005
4006 if (phy_data & MII_SR_LINK_STATUS) {
4007 for (cnt = 0; cnt < 10; cnt++) {
4008 /* read once to clear */
4009 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4010 if (ret_val)
4011 return ret_val;
4012 /* and again to get new status */
4013 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4014 if (ret_val)
4015 return ret_val;
4016
4017 /* check for PCS lock */
4018 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4019 return E1000_SUCCESS;
4020
4021 /* Issue PHY reset */
4022 e1000_phy_hw_reset(hw);
f8ec4733 4023 mdelay(5);
d37ea5d5
AK		 4024 }
4025 /* Disable GigE link negotiation */
4026 reg = E1000_READ_REG(hw, PHY_CTRL);
4027 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
4028 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4029
4030 /* unable to acquire PCS lock */
4031 return E1000_ERR_PHY;
4032 }
4033
4034 return E1000_SUCCESS;
4035}
4036
1da177e4
LT		 4037/******************************************************************************
4038* Probes the expected PHY address for known PHY IDs
4039*
4040* hw - Struct containing variables accessed by shared code
4041******************************************************************************/
35574764 4042static int32_t
1da177e4
LT		 4043e1000_detect_gig_phy(struct e1000_hw *hw)
4044{
4045 int32_t phy_init_status, ret_val;
4046 uint16_t phy_id_high, phy_id_low;
4047 boolean_t match = FALSE;
4048
4049 DEBUGFUNC("e1000_detect_gig_phy");
4050
2a88c173
JK		 4051 if (hw->phy_id != 0)
4052 return E1000_SUCCESS;
4053
868d5309
MC		 4054 /* The 82571 firmware may still be configuring the PHY. In this
4055 * case, we cannot access the PHY until the configuration is done. So
4056 * we explicitly set the PHY values. */
cd94dd0b
AK		 4057 if (hw->mac_type == e1000_82571 ||
4058 hw->mac_type == e1000_82572) {
868d5309
MC		 4059 hw->phy_id = IGP01E1000_I_PHY_ID;
4060 hw->phy_type = e1000_phy_igp_2;
4061 return E1000_SUCCESS;
4062 }
4063
6418ecc6
JK		 4064 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4065 * around that forces PHY page 0 to be set or the reads fail. The rest of
4066 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4067 * So for ESB-2 we need to have this set so our reads won't fail. If the
4068 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
4069 * this out as well. */
4070 if (hw->mac_type == e1000_80003es2lan)
4071 hw->phy_type = e1000_phy_gg82563;
4072
1da177e4
LT		 4073 /* Read the PHY ID Registers to identify which PHY is onboard. */
4074 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
cd94dd0b 4075 if (ret_val)
1da177e4
LT		 4076 return ret_val;
4077
4078 hw->phy_id = (uint32_t) (phy_id_high << 16);
4079 udelay(20);
4080 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
8fc897b0 4081 if (ret_val)
1da177e4
LT		 4082 return ret_val;
4083
4084 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4085 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4086
8fc897b0 4087 switch (hw->mac_type) {
1da177e4 4088 case e1000_82543:
8fc897b0 4089 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
1da177e4
LT		 4090 break;
4091 case e1000_82544:
8fc897b0 4092 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
1da177e4
LT		 4093 break;
4094 case e1000_82540:
4095 case e1000_82545:
4096 case e1000_82545_rev_3:
4097 case e1000_82546:
4098 case e1000_82546_rev_3:
8fc897b0 4099 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
1da177e4
LT		 4100 break;
4101 case e1000_82541:
4102 case e1000_82541_rev_2:
4103 case e1000_82547:
4104 case e1000_82547_rev_2:
8fc897b0 4105 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
1da177e4 4106 break;
2d7edb92 4107 case e1000_82573:
8fc897b0 4108 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
2d7edb92 4109 break;
6418ecc6
JK		 4110 case e1000_80003es2lan:
4111 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4112 break;
cd94dd0b
AK		 4113 case e1000_ich8lan:
4114 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4115 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4116 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4117 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4118 break;
1da177e4
LT		 4119 default:
4120 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4121 return -E1000_ERR_CONFIG;
4122 }
4123 phy_init_status = e1000_set_phy_type(hw);
4124
4125 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4126 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4127 return E1000_SUCCESS;
4128 }
4129 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4130 return -E1000_ERR_PHY;
4131}
4132
4133/******************************************************************************
4134* Resets the PHY's DSP
4135*
4136* hw - Struct containing variables accessed by shared code
4137******************************************************************************/
4138static int32_t
4139e1000_phy_reset_dsp(struct e1000_hw *hw)
4140{
4141 int32_t ret_val;
4142 DEBUGFUNC("e1000_phy_reset_dsp");
4143
4144 do {
6418ecc6
JK		 4145 if (hw->phy_type != e1000_phy_gg82563) {
4146 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
8fc897b0 4147 if (ret_val) break;
6418ecc6 4148 }
1da177e4 4149 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
8fc897b0 4150 if (ret_val) break;
1da177e4 4151 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
8fc897b0 4152 if (ret_val) break;
1da177e4 4153 ret_val = E1000_SUCCESS;
8fc897b0 4154 } while (0);
1da177e4
LT		 4155
4156 return ret_val;
4157}
4158
4159/******************************************************************************
4160* Get PHY information from various PHY registers for igp PHY only.
4161*
4162* hw - Struct containing variables accessed by shared code
4163* phy_info - PHY information structure
4164******************************************************************************/
cff93eb3 4165static int32_t
1da177e4
LT		 4166e1000_phy_igp_get_info(struct e1000_hw *hw,
4167 struct e1000_phy_info *phy_info)
4168{
4169 int32_t ret_val;
70c6f30a
JK		 4170 uint16_t phy_data, min_length, max_length, average;
4171 e1000_rev_polarity polarity;
1da177e4
LT		 4172
4173 DEBUGFUNC("e1000_phy_igp_get_info");
4174
4175 /* The downshift status is checked only once, after link is established,
4176 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4177 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4178
4179 /* IGP01E1000 does not need to support it. */
4180 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4181
4182 /* IGP01E1000 always correct polarity reversal */
4183 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4184
4185 /* Check polarity status */
4186 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4187 if (ret_val)
1da177e4
LT		 4188 return ret_val;
4189
4190 phy_info->cable_polarity = polarity;
4191
4192 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
8fc897b0 4193 if (ret_val)
1da177e4
LT		 4194 return ret_val;
4195
70c6f30a
JK		 4196 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4197 IGP01E1000_PSSR_MDIX_SHIFT);
1da177e4 4198
8fc897b0 4199 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 4200 IGP01E1000_PSSR_SPEED_1000MBPS) {
4201 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4202 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4203 if (ret_val)
1da177e4
LT		 4204 return ret_val;
4205
70c6f30a
JK		 4206 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4207 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4208 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4209 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4210 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4211 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1da177e4
LT		 4212
4213 /* Get cable length */
4214 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
8fc897b0 4215 if (ret_val)
1da177e4
LT		 4216 return ret_val;
4217
2d7edb92 4218 /* Translate to old method */
1da177e4
LT		 4219 average = (max_length + min_length) / 2;
4220
8fc897b0 4221 if (average <= e1000_igp_cable_length_50)
1da177e4 4222 phy_info->cable_length = e1000_cable_length_50;
8fc897b0 4223 else if (average <= e1000_igp_cable_length_80)
1da177e4 4224 phy_info->cable_length = e1000_cable_length_50_80;
8fc897b0 4225 else if (average <= e1000_igp_cable_length_110)
1da177e4 4226 phy_info->cable_length = e1000_cable_length_80_110;
8fc897b0 4227 else if (average <= e1000_igp_cable_length_140)
1da177e4
LT		 4228 phy_info->cable_length = e1000_cable_length_110_140;
4229 else
4230 phy_info->cable_length = e1000_cable_length_140;
4231 }
4232
4233 return E1000_SUCCESS;
4234}
4235
d37ea5d5
AK		 4236/******************************************************************************
4237* Get PHY information from various PHY registers for ife PHY only.
4238*
4239* hw - Struct containing variables accessed by shared code
4240* phy_info - PHY information structure
4241******************************************************************************/
e4c780b1 4242static int32_t
d37ea5d5
AK		 4243e1000_phy_ife_get_info(struct e1000_hw *hw,
4244 struct e1000_phy_info *phy_info)
4245{
4246 int32_t ret_val;
70c6f30a
JK		 4247 uint16_t phy_data;
4248 e1000_rev_polarity polarity;
d37ea5d5
AK		 4249
4250 DEBUGFUNC("e1000_phy_ife_get_info");
4251
4252 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4253 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4254
4255 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4256 if (ret_val)
4257 return ret_val;
4258 phy_info->polarity_correction =
70c6f30a
JK		 4259 ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4260 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4261 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
d37ea5d5
AK		 4262
4263 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4264 ret_val = e1000_check_polarity(hw, &polarity);
4265 if (ret_val)
4266 return ret_val;
4267 } else {
4268 /* Polarity is forced. */
70c6f30a
JK		 4269 polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4270 IFE_PSC_FORCE_POLARITY_SHIFT) ?
4271 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
d37ea5d5
AK		 4272 }
4273 phy_info->cable_polarity = polarity;
4274
4275 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4276 if (ret_val)
4277 return ret_val;
4278
70c6f30a
JK		 4279 phy_info->mdix_mode = (e1000_auto_x_mode)
4280 ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4281 IFE_PMC_MDIX_MODE_SHIFT);
d37ea5d5
AK		 4282
4283 return E1000_SUCCESS;
4284}
4285
1da177e4
LT		 4286/******************************************************************************
4287* Get PHY information from various PHY registers fot m88 PHY only.
4288*
4289* hw - Struct containing variables accessed by shared code
4290* phy_info - PHY information structure
4291******************************************************************************/
3ad2cc67 4292static int32_t
1da177e4
LT		 4293e1000_phy_m88_get_info(struct e1000_hw *hw,
4294 struct e1000_phy_info *phy_info)
4295{
4296 int32_t ret_val;
70c6f30a
JK		 4297 uint16_t phy_data;
4298 e1000_rev_polarity polarity;
1da177e4
LT		 4299
4300 DEBUGFUNC("e1000_phy_m88_get_info");
4301
4302 /* The downshift status is checked only once, after link is established,
4303 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4304 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4305
4306 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 4307 if (ret_val)
1da177e4
LT		 4308 return ret_val;
4309
4310 phy_info->extended_10bt_distance =
70c6f30a
JK		 4311 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4312 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4313 e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4314
1da177e4 4315 phy_info->polarity_correction =
70c6f30a
JK		 4316 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4317 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4318 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
1da177e4
LT		 4319
4320 /* Check polarity status */
4321 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4322 if (ret_val)
76c224bc 4323 return ret_val;
1da177e4
LT		 4324 phy_info->cable_polarity = polarity;
4325
4326 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 4327 if (ret_val)
1da177e4
LT		 4328 return ret_val;
4329
70c6f30a
JK		 4330 phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4331 M88E1000_PSSR_MDIX_SHIFT);
1da177e4
LT		 4332
4333 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4334 /* Cable Length Estimation and Local/Remote Receiver Information
4335 * are only valid at 1000 Mbps.
4336 */
6418ecc6 4337 if (hw->phy_type != e1000_phy_gg82563) {
70c6f30a 4338 phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6418ecc6
JK		 4339 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4340 } else {
4341 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4342 &phy_data);
4343 if (ret_val)
4344 return ret_val;
4345
70c6f30a 4346 phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
6418ecc6 4347 }
1da177e4
LT		 4348
4349 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4350 if (ret_val)
1da177e4
LT		 4351 return ret_val;
4352
70c6f30a
JK		 4353 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4354 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4355 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4356 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4357 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4358 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1da177e4 4359
1da177e4
LT		 4360 }
4361
4362 return E1000_SUCCESS;
4363}
4364
4365/******************************************************************************
4366* Get PHY information from various PHY registers
4367*
4368* hw - Struct containing variables accessed by shared code
4369* phy_info - PHY information structure
4370******************************************************************************/
4371int32_t
4372e1000_phy_get_info(struct e1000_hw *hw,
4373 struct e1000_phy_info *phy_info)
4374{
4375 int32_t ret_val;
4376 uint16_t phy_data;
4377
4378 DEBUGFUNC("e1000_phy_get_info");
4379
4380 phy_info->cable_length = e1000_cable_length_undefined;
4381 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4382 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4383 phy_info->downshift = e1000_downshift_undefined;
4384 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4385 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4386 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4387 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4388
8fc897b0 4389 if (hw->media_type != e1000_media_type_copper) {
1da177e4
LT		 4390 DEBUGOUT("PHY info is only valid for copper media\n");
4391 return -E1000_ERR_CONFIG;
4392 }
4393
4394 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4395 if (ret_val)
1da177e4
LT		 4396 return ret_val;
4397
4398 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4399 if (ret_val)
1da177e4
LT		 4400 return ret_val;
4401
8fc897b0 4402 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
1da177e4
LT		 4403 DEBUGOUT("PHY info is only valid if link is up\n");
4404 return -E1000_ERR_CONFIG;
4405 }
4406
cd94dd0b
AK		 4407 if (hw->phy_type == e1000_phy_igp ||
4408 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 4409 hw->phy_type == e1000_phy_igp_2)
1da177e4 4410 return e1000_phy_igp_get_info(hw, phy_info);
cd94dd0b
AK		 4411 else if (hw->phy_type == e1000_phy_ife)
4412 return e1000_phy_ife_get_info(hw, phy_info);
1da177e4
LT		 4413 else
4414 return e1000_phy_m88_get_info(hw, phy_info);
4415}
4416
4417int32_t
4418e1000_validate_mdi_setting(struct e1000_hw *hw)
4419{
4420 DEBUGFUNC("e1000_validate_mdi_settings");
4421
8fc897b0 4422 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
1da177e4
LT		 4423 DEBUGOUT("Invalid MDI setting detected\n");
4424 hw->mdix = 1;
4425 return -E1000_ERR_CONFIG;
4426 }
4427 return E1000_SUCCESS;
4428}
4429
4430
4431/******************************************************************************
4432 * Sets up eeprom variables in the hw struct. Must be called after mac_type
0f15a8fa
JK		 4433 * is configured. Additionally, if this is ICH8, the flash controller GbE
4434 * registers must be mapped, or this will crash.
1da177e4
LT		 4435 *
4436 * hw - Struct containing variables accessed by shared code
4437 *****************************************************************************/
2d7edb92 4438int32_t
1da177e4
LT		 4439e1000_init_eeprom_params(struct e1000_hw *hw)
4440{
4441 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4442 uint32_t eecd = E1000_READ_REG(hw, EECD);
2d7edb92 4443 int32_t ret_val = E1000_SUCCESS;
1da177e4
LT		 4444 uint16_t eeprom_size;
4445
4446 DEBUGFUNC("e1000_init_eeprom_params");
4447
4448 switch (hw->mac_type) {
4449 case e1000_82542_rev2_0:
4450 case e1000_82542_rev2_1:
4451 case e1000_82543:
4452 case e1000_82544:
4453 eeprom->type = e1000_eeprom_microwire;
4454 eeprom->word_size = 64;
4455 eeprom->opcode_bits = 3;
4456 eeprom->address_bits = 6;
4457 eeprom->delay_usec = 50;
2d7edb92
MC		 4458 eeprom->use_eerd = FALSE;
4459 eeprom->use_eewr = FALSE;
1da177e4
LT		 4460 break;
4461 case e1000_82540:
4462 case e1000_82545:
4463 case e1000_82545_rev_3:
4464 case e1000_82546:
4465 case e1000_82546_rev_3:
4466 eeprom->type = e1000_eeprom_microwire;
4467 eeprom->opcode_bits = 3;
4468 eeprom->delay_usec = 50;
8fc897b0 4469 if (eecd & E1000_EECD_SIZE) {
1da177e4
LT		 4470 eeprom->word_size = 256;
4471 eeprom->address_bits = 8;
4472 } else {
4473 eeprom->word_size = 64;
4474 eeprom->address_bits = 6;
4475 }
2d7edb92
MC		 4476 eeprom->use_eerd = FALSE;
4477 eeprom->use_eewr = FALSE;
1da177e4
LT		 4478 break;
4479 case e1000_82541:
4480 case e1000_82541_rev_2:
4481 case e1000_82547:
4482 case e1000_82547_rev_2:
4483 if (eecd & E1000_EECD_TYPE) {
4484 eeprom->type = e1000_eeprom_spi;
4485 eeprom->opcode_bits = 8;
4486 eeprom->delay_usec = 1;
4487 if (eecd & E1000_EECD_ADDR_BITS) {
4488 eeprom->page_size = 32;
4489 eeprom->address_bits = 16;
4490 } else {
4491 eeprom->page_size = 8;
4492 eeprom->address_bits = 8;
4493 }
4494 } else {
4495 eeprom->type = e1000_eeprom_microwire;
4496 eeprom->opcode_bits = 3;
4497 eeprom->delay_usec = 50;
4498 if (eecd & E1000_EECD_ADDR_BITS) {
4499 eeprom->word_size = 256;
4500 eeprom->address_bits = 8;
4501 } else {
4502 eeprom->word_size = 64;
4503 eeprom->address_bits = 6;
4504 }
4505 }
2d7edb92
MC		 4506 eeprom->use_eerd = FALSE;
4507 eeprom->use_eewr = FALSE;
4508 break;
868d5309
MC		 4509 case e1000_82571:
4510 case e1000_82572:
4511 eeprom->type = e1000_eeprom_spi;
4512 eeprom->opcode_bits = 8;
4513 eeprom->delay_usec = 1;
4514 if (eecd & E1000_EECD_ADDR_BITS) {
4515 eeprom->page_size = 32;
4516 eeprom->address_bits = 16;
4517 } else {
4518 eeprom->page_size = 8;
4519 eeprom->address_bits = 8;
4520 }
4521 eeprom->use_eerd = FALSE;
4522 eeprom->use_eewr = FALSE;
4523 break;
2d7edb92
MC		 4524 case e1000_82573:
4525 eeprom->type = e1000_eeprom_spi;
4526 eeprom->opcode_bits = 8;
4527 eeprom->delay_usec = 1;
4528 if (eecd & E1000_EECD_ADDR_BITS) {
4529 eeprom->page_size = 32;
4530 eeprom->address_bits = 16;
4531 } else {
4532 eeprom->page_size = 8;
4533 eeprom->address_bits = 8;
4534 }
4535 eeprom->use_eerd = TRUE;
4536 eeprom->use_eewr = TRUE;
8fc897b0 4537 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
2d7edb92
MC		 4538 eeprom->type = e1000_eeprom_flash;
4539 eeprom->word_size = 2048;
4540
4541 /* Ensure that the Autonomous FLASH update bit is cleared due to
4542 * Flash update issue on parts which use a FLASH for NVM. */
4543 eecd &= ~E1000_EECD_AUPDEN;
4544 E1000_WRITE_REG(hw, EECD, eecd);
4545 }
1da177e4 4546 break;
6418ecc6
JK		 4547 case e1000_80003es2lan:
4548 eeprom->type = e1000_eeprom_spi;
4549 eeprom->opcode_bits = 8;
4550 eeprom->delay_usec = 1;
4551 if (eecd & E1000_EECD_ADDR_BITS) {
4552 eeprom->page_size = 32;
4553 eeprom->address_bits = 16;
4554 } else {
4555 eeprom->page_size = 8;
4556 eeprom->address_bits = 8;
4557 }
4558 eeprom->use_eerd = TRUE;
4559 eeprom->use_eewr = FALSE;
4560 break;
cd94dd0b 4561 case e1000_ich8lan:
35574764 4562 {
cd94dd0b 4563 int32_t i = 0;
2df7d59f 4564 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
cd94dd0b
AK		 4565
4566 eeprom->type = e1000_eeprom_ich8;
4567 eeprom->use_eerd = FALSE;
4568 eeprom->use_eewr = FALSE;
4569 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4570
4571 /* Zero the shadow RAM structure. But don't load it from NVM
4572 * so as to save time for driver init */
4573 if (hw->eeprom_shadow_ram != NULL) {
4574 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4575 hw->eeprom_shadow_ram[i].modified = FALSE;
4576 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4577 }
4578 }
4579
2df7d59f
JK		 4580 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4581 ICH_FLASH_SECTOR_SIZE;
4582
4583 hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4584 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4585
4586 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
cd94dd0b 4587
cd94dd0b
AK		 4588 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4589
4590 break;
35574764 4591 }
1da177e4
LT		 4592 default:
4593 break;
4594 }
4595
4596 if (eeprom->type == e1000_eeprom_spi) {
2d7edb92
MC		 4597 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4598 * 32KB (incremented by powers of 2).
4599 */
8fc897b0 4600 if (hw->mac_type <= e1000_82547_rev_2) {
2d7edb92
MC		 4601 /* Set to default value for initial eeprom read. */
4602 eeprom->word_size = 64;
4603 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
8fc897b0 4604 if (ret_val)
2d7edb92
MC		 4605 return ret_val;
4606 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4607 /* 256B eeprom size was not supported in earlier hardware, so we
4608 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4609 * is never the result used in the shifting logic below. */
8fc897b0 4610 if (eeprom_size)
2d7edb92
MC		 4611 eeprom_size++;
4612 } else {
4613 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4614 E1000_EECD_SIZE_EX_SHIFT);
1da177e4 4615 }
2d7edb92
MC		 4616
4617 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
1da177e4 4618 }
2d7edb92 4619 return ret_val;
1da177e4
LT		 4620}
4621
4622/******************************************************************************
4623 * Raises the EEPROM's clock input.
4624 *
4625 * hw - Struct containing variables accessed by shared code
4626 * eecd - EECD's current value
4627 *****************************************************************************/
4628static void
4629e1000_raise_ee_clk(struct e1000_hw *hw,
4630 uint32_t *eecd)
4631{
4632 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4633 * wait <delay> microseconds.
4634 */
4635 *eecd = *eecd | E1000_EECD_SK;
4636 E1000_WRITE_REG(hw, EECD, *eecd);
4637 E1000_WRITE_FLUSH(hw);
4638 udelay(hw->eeprom.delay_usec);
4639}
4640
4641/******************************************************************************
4642 * Lowers the EEPROM's clock input.
4643 *
4644 * hw - Struct containing variables accessed by shared code
4645 * eecd - EECD's current value
4646 *****************************************************************************/
4647static void
4648e1000_lower_ee_clk(struct e1000_hw *hw,
4649 uint32_t *eecd)
4650{
4651 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4652 * wait 50 microseconds.
4653 */
4654 *eecd = *eecd & ~E1000_EECD_SK;
4655 E1000_WRITE_REG(hw, EECD, *eecd);
4656 E1000_WRITE_FLUSH(hw);
4657 udelay(hw->eeprom.delay_usec);
4658}
4659
4660/******************************************************************************
4661 * Shift data bits out to the EEPROM.
4662 *
4663 * hw - Struct containing variables accessed by shared code
4664 * data - data to send to the EEPROM
4665 * count - number of bits to shift out
4666 *****************************************************************************/
4667static void
4668e1000_shift_out_ee_bits(struct e1000_hw *hw,
4669 uint16_t data,
4670 uint16_t count)
4671{
4672 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4673 uint32_t eecd;
4674 uint32_t mask;
4675
4676 /* We need to shift "count" bits out to the EEPROM. So, value in the
4677 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4678 * In order to do this, "data" must be broken down into bits.
4679 */
4680 mask = 0x01 << (count - 1);
4681 eecd = E1000_READ_REG(hw, EECD);
4682 if (eeprom->type == e1000_eeprom_microwire) {
4683 eecd &= ~E1000_EECD_DO;
4684 } else if (eeprom->type == e1000_eeprom_spi) {
4685 eecd |= E1000_EECD_DO;
4686 }
4687 do {
4688 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4689 * and then raising and then lowering the clock (the SK bit controls
4690 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4691 * by setting "DI" to "0" and then raising and then lowering the clock.
4692 */
4693 eecd &= ~E1000_EECD_DI;
4694
8fc897b0 4695 if (data & mask)
1da177e4
LT		 4696 eecd |= E1000_EECD_DI;
4697
4698 E1000_WRITE_REG(hw, EECD, eecd);
4699 E1000_WRITE_FLUSH(hw);
4700
4701 udelay(eeprom->delay_usec);
4702
4703 e1000_raise_ee_clk(hw, &eecd);
4704 e1000_lower_ee_clk(hw, &eecd);
4705
4706 mask = mask >> 1;
4707
8fc897b0 4708 } while (mask);
1da177e4
LT		 4709
4710 /* We leave the "DI" bit set to "0" when we leave this routine. */
4711 eecd &= ~E1000_EECD_DI;
4712 E1000_WRITE_REG(hw, EECD, eecd);
4713}
4714
4715/******************************************************************************
4716 * Shift data bits in from the EEPROM
4717 *
4718 * hw - Struct containing variables accessed by shared code
4719 *****************************************************************************/
4720static uint16_t
4721e1000_shift_in_ee_bits(struct e1000_hw *hw,
4722 uint16_t count)
4723{
4724 uint32_t eecd;
4725 uint32_t i;
4726 uint16_t data;
4727
4728 /* In order to read a register from the EEPROM, we need to shift 'count'
4729 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4730 * input to the EEPROM (setting the SK bit), and then reading the value of
4731 * the "DO" bit. During this "shifting in" process the "DI" bit should
4732 * always be clear.
4733 */
4734
4735 eecd = E1000_READ_REG(hw, EECD);
4736
4737 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4738 data = 0;
4739
8fc897b0 4740 for (i = 0; i < count; i++) {
1da177e4
LT		 4741 data = data << 1;
4742 e1000_raise_ee_clk(hw, &eecd);
4743
4744 eecd = E1000_READ_REG(hw, EECD);
4745
4746 eecd &= ~(E1000_EECD_DI);
8fc897b0 4747 if (eecd & E1000_EECD_DO)
1da177e4
LT		 4748 data |= 1;
4749
4750 e1000_lower_ee_clk(hw, &eecd);
4751 }
4752
4753 return data;
4754}
4755
4756/******************************************************************************
4757 * Prepares EEPROM for access
4758 *
4759 * hw - Struct containing variables accessed by shared code
4760 *
4761 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4762 * function should be called before issuing a command to the EEPROM.
4763 *****************************************************************************/
4764static int32_t
4765e1000_acquire_eeprom(struct e1000_hw *hw)
4766{
4767 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4768 uint32_t eecd, i=0;
4769
4770 DEBUGFUNC("e1000_acquire_eeprom");
4771
6418ecc6
JK		 4772 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4773 return -E1000_ERR_SWFW_SYNC;
1da177e4
LT		 4774 eecd = E1000_READ_REG(hw, EECD);
4775
2d7edb92 4776 if (hw->mac_type != e1000_82573) {
868d5309 4777 /* Request EEPROM Access */
8fc897b0 4778 if (hw->mac_type > e1000_82544) {
868d5309 4779 eecd |= E1000_EECD_REQ;
1da177e4 4780 E1000_WRITE_REG(hw, EECD, eecd);
868d5309 4781 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 4782 while ((!(eecd & E1000_EECD_GNT)) &&
868d5309
MC		 4783 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4784 i++;
4785 udelay(5);
4786 eecd = E1000_READ_REG(hw, EECD);
4787 }
8fc897b0 4788 if (!(eecd & E1000_EECD_GNT)) {
868d5309
MC		 4789 eecd &= ~E1000_EECD_REQ;
4790 E1000_WRITE_REG(hw, EECD, eecd);
4791 DEBUGOUT("Could not acquire EEPROM grant\n");
6418ecc6 4792 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
868d5309
MC		 4793 return -E1000_ERR_EEPROM;
4794 }
1da177e4
LT		 4795 }
4796 }
4797
4798 /* Setup EEPROM for Read/Write */
4799
4800 if (eeprom->type == e1000_eeprom_microwire) {
4801 /* Clear SK and DI */
4802 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4803 E1000_WRITE_REG(hw, EECD, eecd);
4804
4805 /* Set CS */
4806 eecd |= E1000_EECD_CS;
4807 E1000_WRITE_REG(hw, EECD, eecd);
4808 } else if (eeprom->type == e1000_eeprom_spi) {
4809 /* Clear SK and CS */
4810 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4811 E1000_WRITE_REG(hw, EECD, eecd);
4812 udelay(1);
4813 }
4814
4815 return E1000_SUCCESS;
4816}
4817
4818/******************************************************************************
4819 * Returns EEPROM to a "standby" state
4820 *
4821 * hw - Struct containing variables accessed by shared code
4822 *****************************************************************************/
4823static void
4824e1000_standby_eeprom(struct e1000_hw *hw)
4825{
4826 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4827 uint32_t eecd;
4828
4829 eecd = E1000_READ_REG(hw, EECD);
4830
8fc897b0 4831 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 4832 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4833 E1000_WRITE_REG(hw, EECD, eecd);
4834 E1000_WRITE_FLUSH(hw);
4835 udelay(eeprom->delay_usec);
4836
4837 /* Clock high */
4838 eecd |= E1000_EECD_SK;
4839 E1000_WRITE_REG(hw, EECD, eecd);
4840 E1000_WRITE_FLUSH(hw);
4841 udelay(eeprom->delay_usec);
4842
4843 /* Select EEPROM */
4844 eecd |= E1000_EECD_CS;
4845 E1000_WRITE_REG(hw, EECD, eecd);
4846 E1000_WRITE_FLUSH(hw);
4847 udelay(eeprom->delay_usec);
4848
4849 /* Clock low */
4850 eecd &= ~E1000_EECD_SK;
4851 E1000_WRITE_REG(hw, EECD, eecd);
4852 E1000_WRITE_FLUSH(hw);
4853 udelay(eeprom->delay_usec);
8fc897b0 4854 } else if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 4855 /* Toggle CS to flush commands */
4856 eecd |= E1000_EECD_CS;
4857 E1000_WRITE_REG(hw, EECD, eecd);
4858 E1000_WRITE_FLUSH(hw);
4859 udelay(eeprom->delay_usec);
4860 eecd &= ~E1000_EECD_CS;
4861 E1000_WRITE_REG(hw, EECD, eecd);
4862 E1000_WRITE_FLUSH(hw);
4863 udelay(eeprom->delay_usec);
4864 }
4865}
4866
4867/******************************************************************************
4868 * Terminates a command by inverting the EEPROM's chip select pin
4869 *
4870 * hw - Struct containing variables accessed by shared code
4871 *****************************************************************************/
4872static void
4873e1000_release_eeprom(struct e1000_hw *hw)
4874{
4875 uint32_t eecd;
4876
4877 DEBUGFUNC("e1000_release_eeprom");
4878
4879 eecd = E1000_READ_REG(hw, EECD);
4880
4881 if (hw->eeprom.type == e1000_eeprom_spi) {
4882 eecd |= E1000_EECD_CS; /* Pull CS high */
4883 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4884
4885 E1000_WRITE_REG(hw, EECD, eecd);
4886
4887 udelay(hw->eeprom.delay_usec);
8fc897b0 4888 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
1da177e4
LT		 4889 /* cleanup eeprom */
4890
4891 /* CS on Microwire is active-high */
4892 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4893
4894 E1000_WRITE_REG(hw, EECD, eecd);
4895
4896 /* Rising edge of clock */
4897 eecd |= E1000_EECD_SK;
4898 E1000_WRITE_REG(hw, EECD, eecd);
4899 E1000_WRITE_FLUSH(hw);
4900 udelay(hw->eeprom.delay_usec);
4901
4902 /* Falling edge of clock */
4903 eecd &= ~E1000_EECD_SK;
4904 E1000_WRITE_REG(hw, EECD, eecd);
4905 E1000_WRITE_FLUSH(hw);
4906 udelay(hw->eeprom.delay_usec);
4907 }
4908
4909 /* Stop requesting EEPROM access */
8fc897b0 4910 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 4911 eecd &= ~E1000_EECD_REQ;
4912 E1000_WRITE_REG(hw, EECD, eecd);
4913 }
2d7edb92 4914
6418ecc6 4915 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
1da177e4
LT		 4916}
4917
4918/******************************************************************************
4919 * Reads a 16 bit word from the EEPROM.
4920 *
4921 * hw - Struct containing variables accessed by shared code
4922 *****************************************************************************/
35574764 4923static int32_t
1da177e4
LT		 4924e1000_spi_eeprom_ready(struct e1000_hw *hw)
4925{
4926 uint16_t retry_count = 0;
4927 uint8_t spi_stat_reg;
4928
4929 DEBUGFUNC("e1000_spi_eeprom_ready");
4930
4931 /* Read "Status Register" repeatedly until the LSB is cleared. The
4932 * EEPROM will signal that the command has been completed by clearing
4933 * bit 0 of the internal status register. If it's not cleared within
4934 * 5 milliseconds, then error out.
4935 */
4936 retry_count = 0;
4937 do {
4938 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4939 hw->eeprom.opcode_bits);
4940 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4941 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4942 break;
4943
4944 udelay(5);
4945 retry_count += 5;
4946
4947 e1000_standby_eeprom(hw);
8fc897b0 4948 } while (retry_count < EEPROM_MAX_RETRY_SPI);
1da177e4
LT		 4949
4950 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4951 * only 0-5mSec on 5V devices)
4952 */
8fc897b0 4953 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
1da177e4
LT		 4954 DEBUGOUT("SPI EEPROM Status error\n");
4955 return -E1000_ERR_EEPROM;
4956 }
4957
4958 return E1000_SUCCESS;
4959}
4960
4961/******************************************************************************
4962 * Reads a 16 bit word from the EEPROM.
4963 *
4964 * hw - Struct containing variables accessed by shared code
4965 * offset - offset of word in the EEPROM to read
4966 * data - word read from the EEPROM
4967 * words - number of words to read
4968 *****************************************************************************/
4969int32_t
4970e1000_read_eeprom(struct e1000_hw *hw,
4971 uint16_t offset,
4972 uint16_t words,
4973 uint16_t *data)
4974{
4975 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4976 uint32_t i = 0;
4977
4978 DEBUGFUNC("e1000_read_eeprom");
2d7edb92 4979
2a88c173
JK		 4980 /* If eeprom is not yet detected, do so now */
4981 if (eeprom->word_size == 0)
4982 e1000_init_eeprom_params(hw);
4983
1da177e4
LT		 4984 /* A check for invalid values: offset too large, too many words, and not
4985 * enough words.
4986 */
8fc897b0 4987 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4 4988 (words == 0)) {
2a88c173 4989 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
1da177e4
LT		 4990 return -E1000_ERR_EEPROM;
4991 }
4992
2a88c173
JK		 4993 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
4994 * directly. In this case, we need to acquire the EEPROM so that
4995 * FW or other port software does not interrupt.
4996 */
4d351858 4997 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
8fc897b0 4998 hw->eeprom.use_eerd == FALSE) {
2a88c173
JK		 4999 /* Prepare the EEPROM for bit-bang reading */
5000 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5001 return -E1000_ERR_EEPROM;
2d7edb92
MC		 5002 }
5003
2a88c173
JK		 5004 /* Eerd register EEPROM access requires no eeprom aquire/release */
5005 if (eeprom->use_eerd == TRUE)
5006 return e1000_read_eeprom_eerd(hw, offset, words, data);
1da177e4 5007
2a88c173 5008 /* ICH EEPROM access is done via the ICH flash controller */
cd94dd0b
AK		 5009 if (eeprom->type == e1000_eeprom_ich8)
5010 return e1000_read_eeprom_ich8(hw, offset, words, data);
5011
2a88c173
JK		 5012 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5013 * acquired the EEPROM at this point, so any returns should relase it */
cd94dd0b 5014 if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 5015 uint16_t word_in;
5016 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5017
8fc897b0 5018 if (e1000_spi_eeprom_ready(hw)) {
1da177e4
LT		 5019 e1000_release_eeprom(hw);
5020 return -E1000_ERR_EEPROM;
5021 }
5022
5023 e1000_standby_eeprom(hw);
5024
5025 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 5026 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 5027 read_opcode |= EEPROM_A8_OPCODE_SPI;
5028
5029 /* Send the READ command (opcode + addr) */
5030 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5031 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5032
5033 /* Read the data. The address of the eeprom internally increments with
5034 * each byte (spi) being read, saving on the overhead of eeprom setup
5035 * and tear-down. The address counter will roll over if reading beyond
5036 * the size of the eeprom, thus allowing the entire memory to be read
5037 * starting from any offset. */
5038 for (i = 0; i < words; i++) {
5039 word_in = e1000_shift_in_ee_bits(hw, 16);
5040 data[i] = (word_in >> 8) | (word_in << 8);
5041 }
8fc897b0 5042 } else if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 5043 for (i = 0; i < words; i++) {
5044 /* Send the READ command (opcode + addr) */
5045 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5046 eeprom->opcode_bits);
5047 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5048 eeprom->address_bits);
5049
5050 /* Read the data. For microwire, each word requires the overhead
5051 * of eeprom setup and tear-down. */
5052 data[i] = e1000_shift_in_ee_bits(hw, 16);
5053 e1000_standby_eeprom(hw);
5054 }
5055 }
5056
5057 /* End this read operation */
5058 e1000_release_eeprom(hw);
5059
5060 return E1000_SUCCESS;
5061}
5062
5063/******************************************************************************
2d7edb92 5064 * Reads a 16 bit word from the EEPROM using the EERD register.
1da177e4
LT		 5065 *
5066 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 5067 * offset - offset of word in the EEPROM to read
5068 * data - word read from the EEPROM
5069 * words - number of words to read
1da177e4 5070 *****************************************************************************/
3ad2cc67 5071static int32_t
2d7edb92
MC		 5072e1000_read_eeprom_eerd(struct e1000_hw *hw,
5073 uint16_t offset,
5074 uint16_t words,
5075 uint16_t *data)
1da177e4 5076{
2d7edb92
MC		 5077 uint32_t i, eerd = 0;
5078 int32_t error = 0;
1da177e4 5079
2d7edb92
MC		 5080 for (i = 0; i < words; i++) {
5081 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5082 E1000_EEPROM_RW_REG_START;
1da177e4 5083
2d7edb92
MC		 5084 E1000_WRITE_REG(hw, EERD, eerd);
5085 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
76c224bc 5086
8fc897b0 5087 if (error) {
2d7edb92 5088 break;
1da177e4 5089 }
2d7edb92 5090 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
76c224bc 5091
1da177e4 5092 }
76c224bc 5093
2d7edb92 5094 return error;
1da177e4
LT		 5095}
5096
5097/******************************************************************************
2d7edb92 5098 * Writes a 16 bit word from the EEPROM using the EEWR register.
1da177e4
LT		 5099 *
5100 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 5101 * offset - offset of word in the EEPROM to read
5102 * data - word read from the EEPROM
5103 * words - number of words to read
1da177e4 5104 *****************************************************************************/
3ad2cc67 5105static int32_t
2d7edb92
MC		 5106e1000_write_eeprom_eewr(struct e1000_hw *hw,
5107 uint16_t offset,
5108 uint16_t words,
5109 uint16_t *data)
1da177e4 5110{
2d7edb92
MC		 5111 uint32_t register_value = 0;
5112 uint32_t i = 0;
5113 int32_t error = 0;
1da177e4 5114
6418ecc6
JK		 5115 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5116 return -E1000_ERR_SWFW_SYNC;
5117
2d7edb92 5118 for (i = 0; i < words; i++) {
76c224bc
AK		 5119 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5120 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
2d7edb92 5121 E1000_EEPROM_RW_REG_START;
1da177e4 5122
2d7edb92 5123 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
8fc897b0 5124 if (error) {
2d7edb92 5125 break;
76c224bc 5126 }
2d7edb92
MC		 5127
5128 E1000_WRITE_REG(hw, EEWR, register_value);
76c224bc 5129
2d7edb92 5130 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
76c224bc 5131
8fc897b0 5132 if (error) {
2d7edb92 5133 break;
76c224bc 5134 }
2d7edb92 5135 }
76c224bc 5136
6418ecc6 5137 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
2d7edb92
MC		 5138 return error;
5139}
5140
5141/******************************************************************************
5142 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5143 *
5144 * hw - Struct containing variables accessed by shared code
5145 *****************************************************************************/
3ad2cc67 5146static int32_t
2d7edb92
MC		 5147e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5148{
5149 uint32_t attempts = 100000;
5150 uint32_t i, reg = 0;
5151 int32_t done = E1000_ERR_EEPROM;
5152
8fc897b0
AK		 5153 for (i = 0; i < attempts; i++) {
5154 if (eerd == E1000_EEPROM_POLL_READ)
2d7edb92 5155 reg = E1000_READ_REG(hw, EERD);
76c224bc 5156 else
2d7edb92
MC		 5157 reg = E1000_READ_REG(hw, EEWR);
5158
8fc897b0 5159 if (reg & E1000_EEPROM_RW_REG_DONE) {
2d7edb92
MC		 5160 done = E1000_SUCCESS;
5161 break;
5162 }
5163 udelay(5);
5164 }
5165
5166 return done;
5167}
5168
5169/***************************************************************************
5170* Description: Determines if the onboard NVM is FLASH or EEPROM.
5171*
5172* hw - Struct containing variables accessed by shared code
5173****************************************************************************/
3ad2cc67 5174static boolean_t
2d7edb92
MC		 5175e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5176{
5177 uint32_t eecd = 0;
5178
6418ecc6
JK		 5179 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5180
cd94dd0b
AK		 5181 if (hw->mac_type == e1000_ich8lan)
5182 return FALSE;
5183
5184 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 5185 eecd = E1000_READ_REG(hw, EECD);
5186
5187 /* Isolate bits 15 & 16 */
5188 eecd = ((eecd >> 15) & 0x03);
5189
5190 /* If both bits are set, device is Flash type */
8fc897b0 5191 if (eecd == 0x03) {
2d7edb92
MC		 5192 return FALSE;
5193 }
5194 }
5195 return TRUE;
5196}
5197
5198/******************************************************************************
5199 * Verifies that the EEPROM has a valid checksum
5200 *
5201 * hw - Struct containing variables accessed by shared code
5202 *
5203 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5204 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5205 * valid.
5206 *****************************************************************************/
5207int32_t
5208e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5209{
5210 uint16_t checksum = 0;
5211 uint16_t i, eeprom_data;
5212
5213 DEBUGFUNC("e1000_validate_eeprom_checksum");
5214
5215 if ((hw->mac_type == e1000_82573) &&
5216 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5217 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5218 * 10h-12h. Checksum may need to be fixed. */
5219 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5220 if ((eeprom_data & 0x10) == 0) {
5221 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5222 * has already been fixed. If the checksum is still wrong and this
5223 * bit is a 1, we need to return bad checksum. Otherwise, we need
5224 * to set this bit to a 1 and update the checksum. */
5225 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5226 if ((eeprom_data & 0x8000) == 0) {
5227 eeprom_data |= 0x8000;
5228 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5229 e1000_update_eeprom_checksum(hw);
5230 }
5231 }
5232 }
5233
cd94dd0b
AK		 5234 if (hw->mac_type == e1000_ich8lan) {
5235 /* Drivers must allocate the shadow ram structure for the
5236 * EEPROM checksum to be updated. Otherwise, this bit as well
5237 * as the checksum must both be set correctly for this
5238 * validation to pass.
5239 */
5240 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5241 if ((eeprom_data & 0x40) == 0) {
5242 eeprom_data |= 0x40;
5243 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5244 e1000_update_eeprom_checksum(hw);
5245 }
5246 }
5247
5248 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5249 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5250 DEBUGOUT("EEPROM Read Error\n");
5251 return -E1000_ERR_EEPROM;
5252 }
5253 checksum += eeprom_data;
5254 }
5255
8fc897b0 5256 if (checksum == (uint16_t) EEPROM_SUM)
2d7edb92
MC		 5257 return E1000_SUCCESS;
5258 else {
5259 DEBUGOUT("EEPROM Checksum Invalid\n");
5260 return -E1000_ERR_EEPROM;
5261 }
5262}
5263
5264/******************************************************************************
5265 * Calculates the EEPROM checksum and writes it to the EEPROM
5266 *
5267 * hw - Struct containing variables accessed by shared code
5268 *
5269 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5270 * Writes the difference to word offset 63 of the EEPROM.
5271 *****************************************************************************/
5272int32_t
5273e1000_update_eeprom_checksum(struct e1000_hw *hw)
5274{
cd94dd0b 5275 uint32_t ctrl_ext;
2d7edb92
MC		 5276 uint16_t checksum = 0;
5277 uint16_t i, eeprom_data;
5278
5279 DEBUGFUNC("e1000_update_eeprom_checksum");
5280
8fc897b0
AK		 5281 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5282 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5283 DEBUGOUT("EEPROM Read Error\n");
5284 return -E1000_ERR_EEPROM;
5285 }
5286 checksum += eeprom_data;
5287 }
5288 checksum = (uint16_t) EEPROM_SUM - checksum;
8fc897b0 5289 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
1da177e4
LT		 5290 DEBUGOUT("EEPROM Write Error\n");
5291 return -E1000_ERR_EEPROM;
2d7edb92
MC		 5292 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5293 e1000_commit_shadow_ram(hw);
cd94dd0b
AK		 5294 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5295 e1000_commit_shadow_ram(hw);
5296 /* Reload the EEPROM, or else modifications will not appear
5297 * until after next adapter reset. */
5298 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5299 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5300 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
f8ec4733 5301 msleep(10);
1da177e4
LT		 5302 }
5303 return E1000_SUCCESS;
5304}
5305
5306/******************************************************************************
5307 * Parent function for writing words to the different EEPROM types.
5308 *
5309 * hw - Struct containing variables accessed by shared code
5310 * offset - offset within the EEPROM to be written to
5311 * words - number of words to write
5312 * data - 16 bit word to be written to the EEPROM
5313 *
5314 * If e1000_update_eeprom_checksum is not called after this function, the
5315 * EEPROM will most likely contain an invalid checksum.
5316 *****************************************************************************/
5317int32_t
5318e1000_write_eeprom(struct e1000_hw *hw,
5319 uint16_t offset,
5320 uint16_t words,
5321 uint16_t *data)
5322{
5323 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5324 int32_t status = 0;
5325
5326 DEBUGFUNC("e1000_write_eeprom");
5327
2a88c173
JK		 5328 /* If eeprom is not yet detected, do so now */
5329 if (eeprom->word_size == 0)
5330 e1000_init_eeprom_params(hw);
5331
1da177e4
LT		 5332 /* A check for invalid values: offset too large, too many words, and not
5333 * enough words.
5334 */
8fc897b0 5335 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4
LT		 5336 (words == 0)) {
5337 DEBUGOUT("\"words\" parameter out of bounds\n");
5338 return -E1000_ERR_EEPROM;
5339 }
5340
868d5309 5341 /* 82573 writes only through eewr */
8fc897b0 5342 if (eeprom->use_eewr == TRUE)
2d7edb92
MC		 5343 return e1000_write_eeprom_eewr(hw, offset, words, data);
5344
cd94dd0b
AK		 5345 if (eeprom->type == e1000_eeprom_ich8)
5346 return e1000_write_eeprom_ich8(hw, offset, words, data);
5347
1da177e4
LT		 5348 /* Prepare the EEPROM for writing */
5349 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5350 return -E1000_ERR_EEPROM;
5351
8fc897b0 5352 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 5353 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5354 } else {
5355 status = e1000_write_eeprom_spi(hw, offset, words, data);
f8ec4733 5356 msleep(10);
1da177e4
LT		 5357 }
5358
5359 /* Done with writing */
5360 e1000_release_eeprom(hw);
5361
5362 return status;
5363}
5364
5365/******************************************************************************
5366 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5367 *
5368 * hw - Struct containing variables accessed by shared code
5369 * offset - offset within the EEPROM to be written to
5370 * words - number of words to write
5371 * data - pointer to array of 8 bit words to be written to the EEPROM
5372 *
5373 *****************************************************************************/
35574764 5374static int32_t
1da177e4
LT		 5375e1000_write_eeprom_spi(struct e1000_hw *hw,
5376 uint16_t offset,
5377 uint16_t words,
5378 uint16_t *data)
5379{
5380 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5381 uint16_t widx = 0;
5382
5383 DEBUGFUNC("e1000_write_eeprom_spi");
5384
5385 while (widx < words) {
5386 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5387
8fc897b0 5388 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
1da177e4
LT		 5389
5390 e1000_standby_eeprom(hw);
5391
5392 /* Send the WRITE ENABLE command (8 bit opcode ) */
5393 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5394 eeprom->opcode_bits);
5395
5396 e1000_standby_eeprom(hw);
5397
5398 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 5399 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 5400 write_opcode |= EEPROM_A8_OPCODE_SPI;
5401
5402 /* Send the Write command (8-bit opcode + addr) */
5403 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5404
5405 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5406 eeprom->address_bits);
5407
5408 /* Send the data */
5409
5410 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5411 while (widx < words) {
5412 uint16_t word_out = data[widx];
5413 word_out = (word_out >> 8) | (word_out << 8);
5414 e1000_shift_out_ee_bits(hw, word_out, 16);
5415 widx++;
5416
5417 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5418 * operation, while the smaller eeproms are capable of an 8-byte
5419 * PAGE WRITE operation. Break the inner loop to pass new address
5420 */
8fc897b0 5421 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
1da177e4
LT		 5422 e1000_standby_eeprom(hw);
5423 break;
5424 }
5425 }
5426 }
5427
5428 return E1000_SUCCESS;
5429}
5430
5431/******************************************************************************
5432 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5433 *
5434 * hw - Struct containing variables accessed by shared code
5435 * offset - offset within the EEPROM to be written to
5436 * words - number of words to write
5437 * data - pointer to array of 16 bit words to be written to the EEPROM
5438 *
5439 *****************************************************************************/
35574764 5440static int32_t
1da177e4
LT		 5441e1000_write_eeprom_microwire(struct e1000_hw *hw,
5442 uint16_t offset,
5443 uint16_t words,
5444 uint16_t *data)
5445{
5446 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5447 uint32_t eecd;
5448 uint16_t words_written = 0;
5449 uint16_t i = 0;
5450
5451 DEBUGFUNC("e1000_write_eeprom_microwire");
5452
5453 /* Send the write enable command to the EEPROM (3-bit opcode plus
5454 * 6/8-bit dummy address beginning with 11). It's less work to include
5455 * the 11 of the dummy address as part of the opcode than it is to shift
5456 * it over the correct number of bits for the address. This puts the
5457 * EEPROM into write/erase mode.
5458 */
5459 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5460 (uint16_t)(eeprom->opcode_bits + 2));
5461
5462 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5463
5464 /* Prepare the EEPROM */
5465 e1000_standby_eeprom(hw);
5466
5467 while (words_written < words) {
5468 /* Send the Write command (3-bit opcode + addr) */
5469 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5470 eeprom->opcode_bits);
5471
5472 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5473 eeprom->address_bits);
5474
5475 /* Send the data */
5476 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5477
5478 /* Toggle the CS line. This in effect tells the EEPROM to execute
5479 * the previous command.
5480 */
5481 e1000_standby_eeprom(hw);
5482
5483 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5484 * signal that the command has been completed by raising the DO signal.
5485 * If DO does not go high in 10 milliseconds, then error out.
5486 */
8fc897b0 5487 for (i = 0; i < 200; i++) {
1da177e4 5488 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 5489 if (eecd & E1000_EECD_DO) break;
1da177e4
LT		 5490 udelay(50);
5491 }
8fc897b0 5492 if (i == 200) {
1da177e4
LT		 5493 DEBUGOUT("EEPROM Write did not complete\n");
5494 return -E1000_ERR_EEPROM;
5495 }
5496
5497 /* Recover from write */
5498 e1000_standby_eeprom(hw);
5499
5500 words_written++;
5501 }
5502
5503 /* Send the write disable command to the EEPROM (3-bit opcode plus
5504 * 6/8-bit dummy address beginning with 10). It's less work to include
5505 * the 10 of the dummy address as part of the opcode than it is to shift
5506 * it over the correct number of bits for the address. This takes the
5507 * EEPROM out of write/erase mode.
5508 */
5509 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5510 (uint16_t)(eeprom->opcode_bits + 2));
5511
5512 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5513
5514 return E1000_SUCCESS;
5515}
5516
2d7edb92
MC		 5517/******************************************************************************
5518 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5519 * in the eeprom cache and the non modified values in the currently active bank
5520 * to the new bank.
5521 *
5522 * hw - Struct containing variables accessed by shared code
5523 * offset - offset of word in the EEPROM to read
5524 * data - word read from the EEPROM
5525 * words - number of words to read
5526 *****************************************************************************/
3ad2cc67 5527static int32_t
2d7edb92
MC		 5528e1000_commit_shadow_ram(struct e1000_hw *hw)
5529{
5530 uint32_t attempts = 100000;
5531 uint32_t eecd = 0;
5532 uint32_t flop = 0;
5533 uint32_t i = 0;
5534 int32_t error = E1000_SUCCESS;
cd94dd0b
AK		 5535 uint32_t old_bank_offset = 0;
5536 uint32_t new_bank_offset = 0;
cd94dd0b
AK		 5537 uint8_t low_byte = 0;
5538 uint8_t high_byte = 0;
cd94dd0b 5539 boolean_t sector_write_failed = FALSE;
2d7edb92
MC		 5540
5541 if (hw->mac_type == e1000_82573) {
cd94dd0b
AK		 5542 /* The flop register will be used to determine if flash type is STM */
5543 flop = E1000_READ_REG(hw, FLOP);
2d7edb92
MC		 5544 for (i=0; i < attempts; i++) {
5545 eecd = E1000_READ_REG(hw, EECD);
5546 if ((eecd & E1000_EECD_FLUPD) == 0) {
5547 break;
5548 }
5549 udelay(5);
5550 }
5551
5552 if (i == attempts) {
5553 return -E1000_ERR_EEPROM;
5554 }
5555
96838a40 5556 /* If STM opcode located in bits 15:8 of flop, reset firmware */
2d7edb92
MC		 5557 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5558 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5559 }
5560
5561 /* Perform the flash update */
5562 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5563
96838a40 5564 for (i=0; i < attempts; i++) {
2d7edb92
MC		 5565 eecd = E1000_READ_REG(hw, EECD);
5566 if ((eecd & E1000_EECD_FLUPD) == 0) {
5567 break;
5568 }
5569 udelay(5);
5570 }
5571
5572 if (i == attempts) {
5573 return -E1000_ERR_EEPROM;
5574 }
5575 }
5576
cd94dd0b
AK		 5577 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5578 /* We're writing to the opposite bank so if we're on bank 1,
5579 * write to bank 0 etc. We also need to erase the segment that
5580 * is going to be written */
5581 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5582 new_bank_offset = hw->flash_bank_size * 2;
5583 old_bank_offset = 0;
5584 e1000_erase_ich8_4k_segment(hw, 1);
5585 } else {
5586 old_bank_offset = hw->flash_bank_size * 2;
5587 new_bank_offset = 0;
5588 e1000_erase_ich8_4k_segment(hw, 0);
5589 }
5590
2a88c173
JK		 5591 sector_write_failed = FALSE;
5592 /* Loop for every byte in the shadow RAM,
5593 * which is in units of words. */
5594 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5595 /* Determine whether to write the value stored
5596 * in the other NVM bank or a modified value stored
5597 * in the shadow RAM */
5598 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5599 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5600 udelay(100);
5601 error = e1000_verify_write_ich8_byte(hw,
5602 (i << 1) + new_bank_offset, low_byte);
5603
5604 if (error != E1000_SUCCESS)
5605 sector_write_failed = TRUE;
5606 else {
cd94dd0b
AK		 5607 high_byte =
5608 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
cd94dd0b 5609 udelay(100);
2a88c173
JK		 5610 }
5611 } else {
5612 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5613 &low_byte);
5614 udelay(100);
5615 error = e1000_verify_write_ich8_byte(hw,
5616 (i << 1) + new_bank_offset, low_byte);
5617
5618 if (error != E1000_SUCCESS)
5619 sector_write_failed = TRUE;
5620 else {
cd94dd0b
AK		 5621 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5622 &high_byte);
2a88c173 5623 udelay(100);
cd94dd0b 5624 }
2a88c173 5625 }
cd94dd0b 5626
2a88c173
JK		 5627 /* If the write of the low byte was successful, go ahread and
5628 * write the high byte while checking to make sure that if it
5629 * is the signature byte, then it is handled properly */
5630 if (sector_write_failed == FALSE) {
cd94dd0b
AK		 5631 /* If the word is 0x13, then make sure the signature bits
5632 * (15:14) are 11b until the commit has completed.
5633 * This will allow us to write 10b which indicates the
5634 * signature is valid. We want to do this after the write
5635 * has completed so that we don't mark the segment valid
5636 * while the write is still in progress */
2df7d59f
JK		 5637 if (i == E1000_ICH_NVM_SIG_WORD)
5638 high_byte = E1000_ICH_NVM_SIG_MASK | high_byte;
cd94dd0b
AK		 5639
5640 error = e1000_verify_write_ich8_byte(hw,
2a88c173 5641 (i << 1) + new_bank_offset + 1, high_byte);
cd94dd0b
AK		 5642 if (error != E1000_SUCCESS)
5643 sector_write_failed = TRUE;
5644
2a88c173
JK		 5645 } else {
5646 /* If the write failed then break from the loop and
5647 * return an error */
5648 break;
cd94dd0b 5649 }
2a88c173 5650 }
cd94dd0b 5651
2a88c173
JK		 5652 /* Don't bother writing the segment valid bits if sector
5653 * programming failed. */
5654 if (sector_write_failed == FALSE) {
5655 /* Finally validate the new segment by setting bit 15:14
5656 * to 10b in word 0x13 , this can be done without an
5657 * erase as well since these bits are 11 to start with
5658 * and we need to change bit 14 to 0b */
5659 e1000_read_ich8_byte(hw,
2df7d59f 5660 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
2a88c173
JK		 5661 &high_byte);
5662 high_byte &= 0xBF;
5663 error = e1000_verify_write_ich8_byte(hw,
2df7d59f 5664 E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
2a88c173
JK		 5665 /* And invalidate the previously valid segment by setting
5666 * its signature word (0x13) high_byte to 0b. This can be
5667 * done without an erase because flash erase sets all bits
5668 * to 1's. We can write 1's to 0's without an erase */
5669 if (error == E1000_SUCCESS) {
cd94dd0b 5670 error = e1000_verify_write_ich8_byte(hw,
2df7d59f 5671 E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
2a88c173 5672 }
cd94dd0b 5673
2a88c173
JK		 5674 /* Clear the now not used entry in the cache */
5675 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5676 hw->eeprom_shadow_ram[i].modified = FALSE;
5677 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
cd94dd0b 5678 }
2a88c173 5679 }
cd94dd0b
AK		 5680 }
5681
2d7edb92
MC		 5682 return error;
5683}
5684
1da177e4
LT		 5685/******************************************************************************
5686 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5687 * second function of dual function devices
5688 *
5689 * hw - Struct containing variables accessed by shared code
5690 *****************************************************************************/
5691int32_t
5692e1000_read_mac_addr(struct e1000_hw * hw)
5693{
5694 uint16_t offset;
5695 uint16_t eeprom_data, i;
5696
5697 DEBUGFUNC("e1000_read_mac_addr");
5698
8fc897b0 5699 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1da177e4 5700 offset = i >> 1;
8fc897b0 5701 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1da177e4
LT		 5702 DEBUGOUT("EEPROM Read Error\n");
5703 return -E1000_ERR_EEPROM;
5704 }
5705 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5706 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5707 }
96838a40 5708
868d5309
MC		 5709 switch (hw->mac_type) {
5710 default:
5711 break;
5712 case e1000_82546:
5713 case e1000_82546_rev_3:
5714 case e1000_82571:
6418ecc6 5715 case e1000_80003es2lan:
8fc897b0 5716 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1da177e4 5717 hw->perm_mac_addr[5] ^= 0x01;
868d5309
MC		 5718 break;
5719 }
1da177e4 5720
8fc897b0 5721 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
1da177e4
LT		 5722 hw->mac_addr[i] = hw->perm_mac_addr[i];
5723 return E1000_SUCCESS;
5724}
5725
5726/******************************************************************************
5727 * Initializes receive address filters.
5728 *
5729 * hw - Struct containing variables accessed by shared code
5730 *
5731 * Places the MAC address in receive address register 0 and clears the rest
5732 * of the receive addresss registers. Clears the multicast table. Assumes
5733 * the receiver is in reset when the routine is called.
5734 *****************************************************************************/
3ad2cc67 5735static void
1da177e4
LT		 5736e1000_init_rx_addrs(struct e1000_hw *hw)
5737{
5738 uint32_t i;
2d7edb92 5739 uint32_t rar_num;
1da177e4
LT		 5740
5741 DEBUGFUNC("e1000_init_rx_addrs");
5742
5743 /* Setup the receive address. */
5744 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5745
5746 e1000_rar_set(hw, hw->mac_addr, 0);
5747
2d7edb92 5748 rar_num = E1000_RAR_ENTRIES;
868d5309
MC		 5749
5750 /* Reserve a spot for the Locally Administered Address to work around
5751 * an 82571 issue in which a reset on one port will reload the MAC on
5752 * the other port. */
5753 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5754 rar_num -= 1;
cd94dd0b
AK		 5755 if (hw->mac_type == e1000_ich8lan)
5756 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5757
1da177e4
LT		 5758 /* Zero out the other 15 receive addresses. */
5759 DEBUGOUT("Clearing RAR[1-15]\n");
8fc897b0 5760 for (i = 1; i < rar_num; i++) {
1da177e4 5761 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4ca213a6 5762 E1000_WRITE_FLUSH(hw);
1da177e4 5763 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4ca213a6 5764 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5765 }
5766}
5767
1da177e4
LT		 5768/******************************************************************************
5769 * Hashes an address to determine its location in the multicast table
5770 *
5771 * hw - Struct containing variables accessed by shared code
5772 * mc_addr - the multicast address to hash
5773 *****************************************************************************/
5774uint32_t
5775e1000_hash_mc_addr(struct e1000_hw *hw,
5776 uint8_t *mc_addr)
5777{
5778 uint32_t hash_value = 0;
5779
5780 /* The portion of the address that is used for the hash table is
5781 * determined by the mc_filter_type setting.
5782 */
5783 switch (hw->mc_filter_type) {
5784 /* [0] [1] [2] [3] [4] [5]
5785 * 01 AA 00 12 34 56
5786 * LSB MSB
5787 */
5788 case 0:
cd94dd0b
AK		 5789 if (hw->mac_type == e1000_ich8lan) {
5790 /* [47:38] i.e. 0x158 for above example address */
5791 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5792 } else {
5793 /* [47:36] i.e. 0x563 for above example address */
5794 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5795 }
1da177e4
LT		 5796 break;
5797 case 1:
cd94dd0b
AK		 5798 if (hw->mac_type == e1000_ich8lan) {
5799 /* [46:37] i.e. 0x2B1 for above example address */
5800 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5801 } else {
5802 /* [46:35] i.e. 0xAC6 for above example address */
5803 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5804 }
1da177e4
LT		 5805 break;
5806 case 2:
cd94dd0b
AK		 5807 if (hw->mac_type == e1000_ich8lan) {
5808 /*[45:36] i.e. 0x163 for above example address */
5809 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5810 } else {
5811 /* [45:34] i.e. 0x5D8 for above example address */
5812 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5813 }
1da177e4
LT		 5814 break;
5815 case 3:
cd94dd0b
AK		 5816 if (hw->mac_type == e1000_ich8lan) {
5817 /* [43:34] i.e. 0x18D for above example address */
5818 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5819 } else {
5820 /* [43:32] i.e. 0x634 for above example address */
5821 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5822 }
1da177e4
LT		 5823 break;
5824 }
5825
5826 hash_value &= 0xFFF;
cd94dd0b
AK		 5827 if (hw->mac_type == e1000_ich8lan)
5828 hash_value &= 0x3FF;
2d7edb92 5829
1da177e4
LT		 5830 return hash_value;
5831}
5832
5833/******************************************************************************
5834 * Sets the bit in the multicast table corresponding to the hash value.
5835 *
5836 * hw - Struct containing variables accessed by shared code
5837 * hash_value - Multicast address hash value
5838 *****************************************************************************/
5839void
5840e1000_mta_set(struct e1000_hw *hw,
5841 uint32_t hash_value)
5842{
5843 uint32_t hash_bit, hash_reg;
5844 uint32_t mta;
5845 uint32_t temp;
5846
5847 /* The MTA is a register array of 128 32-bit registers.
5848 * It is treated like an array of 4096 bits. We want to set
5849 * bit BitArray[hash_value]. So we figure out what register
5850 * the bit is in, read it, OR in the new bit, then write
5851 * back the new value. The register is determined by the
5852 * upper 7 bits of the hash value and the bit within that
5853 * register are determined by the lower 5 bits of the value.
5854 */
5855 hash_reg = (hash_value >> 5) & 0x7F;
cd94dd0b
AK		 5856 if (hw->mac_type == e1000_ich8lan)
5857 hash_reg &= 0x1F;
90fb5135 5858
1da177e4
LT		 5859 hash_bit = hash_value & 0x1F;
5860
5861 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5862
5863 mta |= (1 << hash_bit);
5864
5865 /* If we are on an 82544 and we are trying to write an odd offset
5866 * in the MTA, save off the previous entry before writing and
5867 * restore the old value after writing.
5868 */
8fc897b0 5869 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
1da177e4
LT		 5870 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5871 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5872 E1000_WRITE_FLUSH(hw);
1da177e4 5873 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4ca213a6 5874 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5875 } else {
5876 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5877 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5878 }
5879}
5880
5881/******************************************************************************
5882 * Puts an ethernet address into a receive address register.
5883 *
5884 * hw - Struct containing variables accessed by shared code
5885 * addr - Address to put into receive address register
5886 * index - Receive address register to write
5887 *****************************************************************************/
5888void
5889e1000_rar_set(struct e1000_hw *hw,
5890 uint8_t *addr,
5891 uint32_t index)
5892{
5893 uint32_t rar_low, rar_high;
5894
5895 /* HW expects these in little endian so we reverse the byte order
5896 * from network order (big endian) to little endian
5897 */
5898 rar_low = ((uint32_t) addr[0] |
5899 ((uint32_t) addr[1] << 8) |
5900 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
8df06e50 5901 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
1da177e4 5902
8df06e50
JK		 5903 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5904 * unit hang.
5905 *
5906 * Description:
5907 * If there are any Rx frames queued up or otherwise present in the HW
5908 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5909 * hang. To work around this issue, we have to disable receives and
5910 * flush out all Rx frames before we enable RSS. To do so, we modify we
5911 * redirect all Rx traffic to manageability and then reset the HW.
5912 * This flushes away Rx frames, and (since the redirections to
5913 * manageability persists across resets) keeps new ones from coming in
5914 * while we work. Then, we clear the Address Valid AV bit for all MAC
5915 * addresses and undo the re-direction to manageability.
5916 * Now, frames are coming in again, but the MAC won't accept them, so
5917 * far so good. We now proceed to initialize RSS (if necessary) and
5918 * configure the Rx unit. Last, we re-enable the AV bits and continue
5919 * on our merry way.
5920 */
5921 switch (hw->mac_type) {
5922 case e1000_82571:
5923 case e1000_82572:
6418ecc6 5924 case e1000_80003es2lan:
8df06e50
JK		 5925 if (hw->leave_av_bit_off == TRUE)
5926 break;
5927 default:
5928 /* Indicate to hardware the Address is Valid. */
5929 rar_high |= E1000_RAH_AV;
5930 break;
5931 }
1da177e4
LT		 5932
5933 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4ca213a6 5934 E1000_WRITE_FLUSH(hw);
1da177e4 5935 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4ca213a6 5936 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5937}
5938
5939/******************************************************************************
5940 * Writes a value to the specified offset in the VLAN filter table.
5941 *
5942 * hw - Struct containing variables accessed by shared code
5943 * offset - Offset in VLAN filer table to write
5944 * value - Value to write into VLAN filter table
5945 *****************************************************************************/
5946void
5947e1000_write_vfta(struct e1000_hw *hw,
5948 uint32_t offset,
5949 uint32_t value)
5950{
5951 uint32_t temp;
5952
cd94dd0b
AK		 5953 if (hw->mac_type == e1000_ich8lan)
5954 return;
5955
5956 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
1da177e4
LT		 5957 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5958 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5959 E1000_WRITE_FLUSH(hw);
1da177e4 5960 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4ca213a6 5961 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5962 } else {
5963 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5964 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5965 }
5966}
5967
5968/******************************************************************************
5969 * Clears the VLAN filer table
5970 *
5971 * hw - Struct containing variables accessed by shared code
5972 *****************************************************************************/
3ad2cc67 5973static void
1da177e4
LT		 5974e1000_clear_vfta(struct e1000_hw *hw)
5975{
5976 uint32_t offset;
2d7edb92
MC		 5977 uint32_t vfta_value = 0;
5978 uint32_t vfta_offset = 0;
5979 uint32_t vfta_bit_in_reg = 0;
5980
cd94dd0b
AK		 5981 if (hw->mac_type == e1000_ich8lan)
5982 return;
5983
2d7edb92
MC		 5984 if (hw->mac_type == e1000_82573) {
5985 if (hw->mng_cookie.vlan_id != 0) {
5986 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5987 * ID. The following operations determine which 32b entry
5988 * (i.e. offset) into the array we want to set the VLAN ID
5989 * (i.e. bit) of the manageability unit. */
5990 vfta_offset = (hw->mng_cookie.vlan_id >>
5991 E1000_VFTA_ENTRY_SHIFT) &
5992 E1000_VFTA_ENTRY_MASK;
5993 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5994 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5995 }
5996 }
5997 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5998 /* If the offset we want to clear is the same offset of the
5999 * manageability VLAN ID, then clear all bits except that of the
6000 * manageability unit */
6001 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
6002 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4ca213a6 6003 E1000_WRITE_FLUSH(hw);
2d7edb92 6004 }
1da177e4
LT		 6005}
6006
3ad2cc67 6007static int32_t
1da177e4
LT		 6008e1000_id_led_init(struct e1000_hw * hw)
6009{
6010 uint32_t ledctl;
6011 const uint32_t ledctl_mask = 0x000000FF;
6012 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6013 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6014 uint16_t eeprom_data, i, temp;
6015 const uint16_t led_mask = 0x0F;
6016
6017 DEBUGFUNC("e1000_id_led_init");
6018
8fc897b0 6019 if (hw->mac_type < e1000_82540) {
1da177e4
LT		 6020 /* Nothing to do */
6021 return E1000_SUCCESS;
6022 }
6023
6024 ledctl = E1000_READ_REG(hw, LEDCTL);
6025 hw->ledctl_default = ledctl;
6026 hw->ledctl_mode1 = hw->ledctl_default;
6027 hw->ledctl_mode2 = hw->ledctl_default;
6028
8fc897b0 6029 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
1da177e4
LT		 6030 DEBUGOUT("EEPROM Read Error\n");
6031 return -E1000_ERR_EEPROM;
6032 }
cd94dd0b
AK		 6033
6034 if ((hw->mac_type == e1000_82573) &&
6035 (eeprom_data == ID_LED_RESERVED_82573))
6036 eeprom_data = ID_LED_DEFAULT_82573;
6037 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6038 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6039 if (hw->mac_type == e1000_ich8lan)
6040 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6041 else
6042 eeprom_data = ID_LED_DEFAULT;
6043 }
90fb5135 6044
cd94dd0b 6045 for (i = 0; i < 4; i++) {
1da177e4 6046 temp = (eeprom_data >> (i << 2)) & led_mask;
8fc897b0 6047 switch (temp) {
1da177e4
LT		 6048 case ID_LED_ON1_DEF2:
6049 case ID_LED_ON1_ON2:
6050 case ID_LED_ON1_OFF2:
6051 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6052 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6053 break;
6054 case ID_LED_OFF1_DEF2:
6055 case ID_LED_OFF1_ON2:
6056 case ID_LED_OFF1_OFF2:
6057 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6058 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6059 break;
6060 default:
6061 /* Do nothing */
6062 break;
6063 }
8fc897b0 6064 switch (temp) {
1da177e4
LT		 6065 case ID_LED_DEF1_ON2:
6066 case ID_LED_ON1_ON2:
6067 case ID_LED_OFF1_ON2:
6068 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6069 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6070 break;
6071 case ID_LED_DEF1_OFF2:
6072 case ID_LED_ON1_OFF2:
6073 case ID_LED_OFF1_OFF2:
6074 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6075 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6076 break;
6077 default:
6078 /* Do nothing */
6079 break;
6080 }
6081 }
6082 return E1000_SUCCESS;
6083}
6084
6085/******************************************************************************
6086 * Prepares SW controlable LED for use and saves the current state of the LED.
6087 *
6088 * hw - Struct containing variables accessed by shared code
6089 *****************************************************************************/
6090int32_t
6091e1000_setup_led(struct e1000_hw *hw)
6092{
6093 uint32_t ledctl;
6094 int32_t ret_val = E1000_SUCCESS;
6095
6096 DEBUGFUNC("e1000_setup_led");
6097
8fc897b0 6098 switch (hw->mac_type) {
1da177e4
LT		 6099 case e1000_82542_rev2_0:
6100 case e1000_82542_rev2_1:
6101 case e1000_82543:
6102 case e1000_82544:
6103 /* No setup necessary */
6104 break;
6105 case e1000_82541:
6106 case e1000_82547:
6107 case e1000_82541_rev_2:
6108 case e1000_82547_rev_2:
6109 /* Turn off PHY Smart Power Down (if enabled) */
6110 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6111 &hw->phy_spd_default);
8fc897b0 6112 if (ret_val)
1da177e4
LT		 6113 return ret_val;
6114 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6115 (uint16_t)(hw->phy_spd_default &
6116 ~IGP01E1000_GMII_SPD));
8fc897b0 6117 if (ret_val)
1da177e4
LT		 6118 return ret_val;
6119 /* Fall Through */
6120 default:
8fc897b0 6121 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6122 ledctl = E1000_READ_REG(hw, LEDCTL);
6123 /* Save current LEDCTL settings */
6124 hw->ledctl_default = ledctl;
6125 /* Turn off LED0 */
6126 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6127 E1000_LEDCTL_LED0_BLINK |
6128 E1000_LEDCTL_LED0_MODE_MASK);
6129 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6130 E1000_LEDCTL_LED0_MODE_SHIFT);
6131 E1000_WRITE_REG(hw, LEDCTL, ledctl);
8fc897b0 6132 } else if (hw->media_type == e1000_media_type_copper)
1da177e4
LT		 6133 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6134 break;
6135 }
6136
6137 return E1000_SUCCESS;
6138}
6139
8fc897b0 6140
f1b3a853
AK		 6141/******************************************************************************
6142 * Used on 82571 and later Si that has LED blink bits.
6143 * Callers must use their own timer and should have already called
6144 * e1000_id_led_init()
6145 * Call e1000_cleanup led() to stop blinking
6146 *
6147 * hw - Struct containing variables accessed by shared code
6148 *****************************************************************************/
6149int32_t
6150e1000_blink_led_start(struct e1000_hw *hw)
6151{
6152 int16_t i;
6153 uint32_t ledctl_blink = 0;
6154
6155 DEBUGFUNC("e1000_id_led_blink_on");
6156
6157 if (hw->mac_type < e1000_82571) {
6158 /* Nothing to do */
6159 return E1000_SUCCESS;
6160 }
6161 if (hw->media_type == e1000_media_type_fiber) {
6162 /* always blink LED0 for PCI-E fiber */
6163 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6164 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6165 } else {
6166 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6167 ledctl_blink = hw->ledctl_mode2;
6168 for (i=0; i < 4; i++)
6169 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6170 E1000_LEDCTL_MODE_LED_ON)
6171 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6172 }
6173
6174 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6175
6176 return E1000_SUCCESS;
6177}
6178
1da177e4
LT		 6179/******************************************************************************
6180 * Restores the saved state of the SW controlable LED.
6181 *
6182 * hw - Struct containing variables accessed by shared code
6183 *****************************************************************************/
6184int32_t
6185e1000_cleanup_led(struct e1000_hw *hw)
6186{
6187 int32_t ret_val = E1000_SUCCESS;
6188
6189 DEBUGFUNC("e1000_cleanup_led");
6190
8fc897b0 6191 switch (hw->mac_type) {
1da177e4
LT		 6192 case e1000_82542_rev2_0:
6193 case e1000_82542_rev2_1:
6194 case e1000_82543:
6195 case e1000_82544:
6196 /* No cleanup necessary */
6197 break;
6198 case e1000_82541:
6199 case e1000_82547:
6200 case e1000_82541_rev_2:
6201 case e1000_82547_rev_2:
6202 /* Turn on PHY Smart Power Down (if previously enabled) */
6203 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6204 hw->phy_spd_default);
8fc897b0 6205 if (ret_val)
1da177e4
LT		 6206 return ret_val;
6207 /* Fall Through */
6208 default:
cd94dd0b
AK		 6209 if (hw->phy_type == e1000_phy_ife) {
6210 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6211 break;
6212 }
1da177e4
LT		 6213 /* Restore LEDCTL settings */
6214 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6215 break;
6216 }
6217
6218 return E1000_SUCCESS;
6219}
6220
6221/******************************************************************************
6222 * Turns on the software controllable LED
6223 *
6224 * hw - Struct containing variables accessed by shared code
6225 *****************************************************************************/
6226int32_t
6227e1000_led_on(struct e1000_hw *hw)
6228{
6229 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6230
6231 DEBUGFUNC("e1000_led_on");
6232
8fc897b0 6233 switch (hw->mac_type) {
1da177e4
LT		 6234 case e1000_82542_rev2_0:
6235 case e1000_82542_rev2_1:
6236 case e1000_82543:
6237 /* Set SW Defineable Pin 0 to turn on the LED */
6238 ctrl |= E1000_CTRL_SWDPIN0;
6239 ctrl |= E1000_CTRL_SWDPIO0;
6240 break;
6241 case e1000_82544:
8fc897b0 6242 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6243 /* Set SW Defineable Pin 0 to turn on the LED */
6244 ctrl |= E1000_CTRL_SWDPIN0;
6245 ctrl |= E1000_CTRL_SWDPIO0;
6246 } else {
6247 /* Clear SW Defineable Pin 0 to turn on the LED */
6248 ctrl &= ~E1000_CTRL_SWDPIN0;
6249 ctrl |= E1000_CTRL_SWDPIO0;
6250 }
6251 break;
6252 default:
8fc897b0 6253 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6254 /* Clear SW Defineable Pin 0 to turn on the LED */
6255 ctrl &= ~E1000_CTRL_SWDPIN0;
6256 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6257 } else if (hw->phy_type == e1000_phy_ife) {
6258 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6259 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6260 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6261 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6262 return E1000_SUCCESS;
6263 }
6264 break;
6265 }
6266
6267 E1000_WRITE_REG(hw, CTRL, ctrl);
6268
6269 return E1000_SUCCESS;
6270}
6271
6272/******************************************************************************
6273 * Turns off the software controllable LED
6274 *
6275 * hw - Struct containing variables accessed by shared code
6276 *****************************************************************************/
6277int32_t
6278e1000_led_off(struct e1000_hw *hw)
6279{
6280 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6281
6282 DEBUGFUNC("e1000_led_off");
6283
8fc897b0 6284 switch (hw->mac_type) {
1da177e4
LT		 6285 case e1000_82542_rev2_0:
6286 case e1000_82542_rev2_1:
6287 case e1000_82543:
6288 /* Clear SW Defineable Pin 0 to turn off the LED */
6289 ctrl &= ~E1000_CTRL_SWDPIN0;
6290 ctrl |= E1000_CTRL_SWDPIO0;
6291 break;
6292 case e1000_82544:
8fc897b0 6293 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6294 /* Clear SW Defineable Pin 0 to turn off the LED */
6295 ctrl &= ~E1000_CTRL_SWDPIN0;
6296 ctrl |= E1000_CTRL_SWDPIO0;
6297 } else {
6298 /* Set SW Defineable Pin 0 to turn off the LED */
6299 ctrl |= E1000_CTRL_SWDPIN0;
6300 ctrl |= E1000_CTRL_SWDPIO0;
6301 }
6302 break;
6303 default:
8fc897b0 6304 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6305 /* Set SW Defineable Pin 0 to turn off the LED */
6306 ctrl |= E1000_CTRL_SWDPIN0;
6307 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6308 } else if (hw->phy_type == e1000_phy_ife) {
6309 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6310 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6311 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6312 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6313 return E1000_SUCCESS;
6314 }
6315 break;
6316 }
6317
6318 E1000_WRITE_REG(hw, CTRL, ctrl);
6319
6320 return E1000_SUCCESS;
6321}
6322
6323/******************************************************************************
6324 * Clears all hardware statistics counters.
6325 *
6326 * hw - Struct containing variables accessed by shared code
6327 *****************************************************************************/
35574764 6328static void
1da177e4
LT		 6329e1000_clear_hw_cntrs(struct e1000_hw *hw)
6330{
6331 volatile uint32_t temp;
6332
6333 temp = E1000_READ_REG(hw, CRCERRS);
6334 temp = E1000_READ_REG(hw, SYMERRS);
6335 temp = E1000_READ_REG(hw, MPC);
6336 temp = E1000_READ_REG(hw, SCC);
6337 temp = E1000_READ_REG(hw, ECOL);
6338 temp = E1000_READ_REG(hw, MCC);
6339 temp = E1000_READ_REG(hw, LATECOL);
6340 temp = E1000_READ_REG(hw, COLC);
6341 temp = E1000_READ_REG(hw, DC);
6342 temp = E1000_READ_REG(hw, SEC);
6343 temp = E1000_READ_REG(hw, RLEC);
6344 temp = E1000_READ_REG(hw, XONRXC);
6345 temp = E1000_READ_REG(hw, XONTXC);
6346 temp = E1000_READ_REG(hw, XOFFRXC);
6347 temp = E1000_READ_REG(hw, XOFFTXC);
6348 temp = E1000_READ_REG(hw, FCRUC);
cd94dd0b
AK		 6349
6350 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6351 temp = E1000_READ_REG(hw, PRC64);
6352 temp = E1000_READ_REG(hw, PRC127);
6353 temp = E1000_READ_REG(hw, PRC255);
6354 temp = E1000_READ_REG(hw, PRC511);
6355 temp = E1000_READ_REG(hw, PRC1023);
6356 temp = E1000_READ_REG(hw, PRC1522);
cd94dd0b
AK		 6357 }
6358
1da177e4
LT		 6359 temp = E1000_READ_REG(hw, GPRC);
6360 temp = E1000_READ_REG(hw, BPRC);
6361 temp = E1000_READ_REG(hw, MPRC);
6362 temp = E1000_READ_REG(hw, GPTC);
6363 temp = E1000_READ_REG(hw, GORCL);
6364 temp = E1000_READ_REG(hw, GORCH);
6365 temp = E1000_READ_REG(hw, GOTCL);
6366 temp = E1000_READ_REG(hw, GOTCH);
6367 temp = E1000_READ_REG(hw, RNBC);
6368 temp = E1000_READ_REG(hw, RUC);
6369 temp = E1000_READ_REG(hw, RFC);
6370 temp = E1000_READ_REG(hw, ROC);
6371 temp = E1000_READ_REG(hw, RJC);
6372 temp = E1000_READ_REG(hw, TORL);
6373 temp = E1000_READ_REG(hw, TORH);
6374 temp = E1000_READ_REG(hw, TOTL);
6375 temp = E1000_READ_REG(hw, TOTH);
6376 temp = E1000_READ_REG(hw, TPR);
6377 temp = E1000_READ_REG(hw, TPT);
cd94dd0b
AK		 6378
6379 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6380 temp = E1000_READ_REG(hw, PTC64);
6381 temp = E1000_READ_REG(hw, PTC127);
6382 temp = E1000_READ_REG(hw, PTC255);
6383 temp = E1000_READ_REG(hw, PTC511);
6384 temp = E1000_READ_REG(hw, PTC1023);
6385 temp = E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 6386 }
6387
1da177e4
LT		 6388 temp = E1000_READ_REG(hw, MPTC);
6389 temp = E1000_READ_REG(hw, BPTC);
6390
8fc897b0 6391 if (hw->mac_type < e1000_82543) return;
1da177e4
LT		 6392
6393 temp = E1000_READ_REG(hw, ALGNERRC);
6394 temp = E1000_READ_REG(hw, RXERRC);
6395 temp = E1000_READ_REG(hw, TNCRS);
6396 temp = E1000_READ_REG(hw, CEXTERR);
6397 temp = E1000_READ_REG(hw, TSCTC);
6398 temp = E1000_READ_REG(hw, TSCTFC);
6399
8fc897b0 6400 if (hw->mac_type <= e1000_82544) return;
1da177e4
LT		 6401
6402 temp = E1000_READ_REG(hw, MGTPRC);
6403 temp = E1000_READ_REG(hw, MGTPDC);
6404 temp = E1000_READ_REG(hw, MGTPTC);
2d7edb92 6405
8fc897b0 6406 if (hw->mac_type <= e1000_82547_rev_2) return;
2d7edb92
MC		 6407
6408 temp = E1000_READ_REG(hw, IAC);
6409 temp = E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 6410
6411 if (hw->mac_type == e1000_ich8lan) return;
6412
2d7edb92
MC		 6413 temp = E1000_READ_REG(hw, ICRXPTC);
6414 temp = E1000_READ_REG(hw, ICRXATC);
6415 temp = E1000_READ_REG(hw, ICTXPTC);
6416 temp = E1000_READ_REG(hw, ICTXATC);
6417 temp = E1000_READ_REG(hw, ICTXQEC);
6418 temp = E1000_READ_REG(hw, ICTXQMTC);
6419 temp = E1000_READ_REG(hw, ICRXDMTC);
1da177e4
LT		 6420}
6421
6422/******************************************************************************
6423 * Resets Adaptive IFS to its default state.
6424 *
6425 * hw - Struct containing variables accessed by shared code
6426 *
6427 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6428 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6429 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6430 * before calling this function.
6431 *****************************************************************************/
6432void
6433e1000_reset_adaptive(struct e1000_hw *hw)
6434{
6435 DEBUGFUNC("e1000_reset_adaptive");
6436
8fc897b0
AK		 6437 if (hw->adaptive_ifs) {
6438 if (!hw->ifs_params_forced) {
1da177e4
LT		 6439 hw->current_ifs_val = 0;
6440 hw->ifs_min_val = IFS_MIN;
6441 hw->ifs_max_val = IFS_MAX;
6442 hw->ifs_step_size = IFS_STEP;
6443 hw->ifs_ratio = IFS_RATIO;
6444 }
6445 hw->in_ifs_mode = FALSE;
6446 E1000_WRITE_REG(hw, AIT, 0);
6447 } else {
6448 DEBUGOUT("Not in Adaptive IFS mode!\n");
6449 }
6450}
6451
6452/******************************************************************************
6453 * Called during the callback/watchdog routine to update IFS value based on
6454 * the ratio of transmits to collisions.
6455 *
6456 * hw - Struct containing variables accessed by shared code
6457 * tx_packets - Number of transmits since last callback
6458 * total_collisions - Number of collisions since last callback
6459 *****************************************************************************/
6460void
6461e1000_update_adaptive(struct e1000_hw *hw)
6462{
6463 DEBUGFUNC("e1000_update_adaptive");
6464
8fc897b0
AK		 6465 if (hw->adaptive_ifs) {
6466 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6467 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
1da177e4 6468 hw->in_ifs_mode = TRUE;
8fc897b0
AK		 6469 if (hw->current_ifs_val < hw->ifs_max_val) {
6470 if (hw->current_ifs_val == 0)
1da177e4
LT		 6471 hw->current_ifs_val = hw->ifs_min_val;
6472 else
6473 hw->current_ifs_val += hw->ifs_step_size;
6474 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6475 }
6476 }
6477 } else {
8fc897b0 6478 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
1da177e4
LT		 6479 hw->current_ifs_val = 0;
6480 hw->in_ifs_mode = FALSE;
6481 E1000_WRITE_REG(hw, AIT, 0);
6482 }
6483 }
6484 } else {
6485 DEBUGOUT("Not in Adaptive IFS mode!\n");
6486 }
6487}
6488
6489/******************************************************************************
6490 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6491 *
6492 * hw - Struct containing variables accessed by shared code
6493 * frame_len - The length of the frame in question
6494 * mac_addr - The Ethernet destination address of the frame in question
6495 *****************************************************************************/
6496void
6497e1000_tbi_adjust_stats(struct e1000_hw *hw,
6498 struct e1000_hw_stats *stats,
6499 uint32_t frame_len,
6500 uint8_t *mac_addr)
6501{
6502 uint64_t carry_bit;
6503
6504 /* First adjust the frame length. */
6505 frame_len--;
6506 /* We need to adjust the statistics counters, since the hardware
6507 * counters overcount this packet as a CRC error and undercount
6508 * the packet as a good packet
6509 */
6510 /* This packet should not be counted as a CRC error. */
6511 stats->crcerrs--;
6512 /* This packet does count as a Good Packet Received. */
6513 stats->gprc++;
6514
6515 /* Adjust the Good Octets received counters */
6516 carry_bit = 0x80000000 & stats->gorcl;
6517 stats->gorcl += frame_len;
6518 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6519 * Received Count) was one before the addition,
6520 * AND it is zero after, then we lost the carry out,
6521 * need to add one to Gorch (Good Octets Received Count High).
6522 * This could be simplified if all environments supported
6523 * 64-bit integers.
6524 */
8fc897b0 6525 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
1da177e4
LT		 6526 stats->gorch++;
6527 /* Is this a broadcast or multicast? Check broadcast first,
6528 * since the test for a multicast frame will test positive on
6529 * a broadcast frame.
6530 */
8fc897b0 6531 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
1da177e4
LT		 6532 /* Broadcast packet */
6533 stats->bprc++;
8fc897b0 6534 else if (*mac_addr & 0x01)
1da177e4
LT		 6535 /* Multicast packet */
6536 stats->mprc++;
6537
8fc897b0 6538 if (frame_len == hw->max_frame_size) {
1da177e4
LT		 6539 /* In this case, the hardware has overcounted the number of
6540 * oversize frames.
6541 */
8fc897b0 6542 if (stats->roc > 0)
1da177e4
LT		 6543 stats->roc--;
6544 }
6545
6546 /* Adjust the bin counters when the extra byte put the frame in the
6547 * wrong bin. Remember that the frame_len was adjusted above.
6548 */
8fc897b0 6549 if (frame_len == 64) {
1da177e4
LT		 6550 stats->prc64++;
6551 stats->prc127--;
8fc897b0 6552 } else if (frame_len == 127) {
1da177e4
LT		 6553 stats->prc127++;
6554 stats->prc255--;
8fc897b0 6555 } else if (frame_len == 255) {
1da177e4
LT		 6556 stats->prc255++;
6557 stats->prc511--;
8fc897b0 6558 } else if (frame_len == 511) {
1da177e4
LT		 6559 stats->prc511++;
6560 stats->prc1023--;
8fc897b0 6561 } else if (frame_len == 1023) {
1da177e4
LT		 6562 stats->prc1023++;
6563 stats->prc1522--;
8fc897b0 6564 } else if (frame_len == 1522) {
1da177e4
LT		 6565 stats->prc1522++;
6566 }
6567}
6568
6569/******************************************************************************
6570 * Gets the current PCI bus type, speed, and width of the hardware
6571 *
6572 * hw - Struct containing variables accessed by shared code
6573 *****************************************************************************/
6574void
6575e1000_get_bus_info(struct e1000_hw *hw)
6576{
caeccb68
JK		 6577 int32_t ret_val;
6578 uint16_t pci_ex_link_status;
1da177e4
LT		 6579 uint32_t status;
6580
6581 switch (hw->mac_type) {
6582 case e1000_82542_rev2_0:
6583 case e1000_82542_rev2_1:
6584 hw->bus_type = e1000_bus_type_unknown;
6585 hw->bus_speed = e1000_bus_speed_unknown;
6586 hw->bus_width = e1000_bus_width_unknown;
6587 break;
caeccb68 6588 case e1000_82571:
868d5309 6589 case e1000_82572:
2d7edb92 6590 case e1000_82573:
caeccb68 6591 case e1000_80003es2lan:
fd803241
JK		 6592 hw->bus_type = e1000_bus_type_pci_express;
6593 hw->bus_speed = e1000_bus_speed_2500;
caeccb68
JK		 6594 ret_val = e1000_read_pcie_cap_reg(hw,
6595 PCI_EX_LINK_STATUS,
6596 &pci_ex_link_status);
6597 if (ret_val)
6598 hw->bus_width = e1000_bus_width_unknown;
6599 else
6600 hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6601 PCI_EX_LINK_WIDTH_SHIFT;
fd803241 6602 break;
cd94dd0b 6603 case e1000_ich8lan:
2d7edb92
MC		 6604 hw->bus_type = e1000_bus_type_pci_express;
6605 hw->bus_speed = e1000_bus_speed_2500;
caeccb68 6606 hw->bus_width = e1000_bus_width_pciex_1;
2d7edb92 6607 break;
1da177e4
LT		 6608 default:
6609 status = E1000_READ_REG(hw, STATUS);
6610 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6611 e1000_bus_type_pcix : e1000_bus_type_pci;
6612
8fc897b0 6613 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
1da177e4
LT		 6614 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6615 e1000_bus_speed_66 : e1000_bus_speed_120;
8fc897b0 6616 } else if (hw->bus_type == e1000_bus_type_pci) {
1da177e4
LT		 6617 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6618 e1000_bus_speed_66 : e1000_bus_speed_33;
6619 } else {
6620 switch (status & E1000_STATUS_PCIX_SPEED) {
6621 case E1000_STATUS_PCIX_SPEED_66:
6622 hw->bus_speed = e1000_bus_speed_66;
6623 break;
6624 case E1000_STATUS_PCIX_SPEED_100:
6625 hw->bus_speed = e1000_bus_speed_100;
6626 break;
6627 case E1000_STATUS_PCIX_SPEED_133:
6628 hw->bus_speed = e1000_bus_speed_133;
6629 break;
6630 default:
6631 hw->bus_speed = e1000_bus_speed_reserved;
6632 break;
6633 }
6634 }
6635 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6636 e1000_bus_width_64 : e1000_bus_width_32;
6637 break;
6638 }
6639}
1da177e4
LT		 6640
6641/******************************************************************************
6642 * Writes a value to one of the devices registers using port I/O (as opposed to
6643 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6644 *
6645 * hw - Struct containing variables accessed by shared code
6646 * offset - offset to write to
6647 * value - value to write
6648 *****************************************************************************/
3ad2cc67 6649static void
1da177e4
LT		 6650e1000_write_reg_io(struct e1000_hw *hw,
6651 uint32_t offset,
6652 uint32_t value)
6653{
6654 unsigned long io_addr = hw->io_base;
6655 unsigned long io_data = hw->io_base + 4;
6656
6657 e1000_io_write(hw, io_addr, offset);
6658 e1000_io_write(hw, io_data, value);
6659}
6660
1da177e4
LT		 6661/******************************************************************************
6662 * Estimates the cable length.
6663 *
6664 * hw - Struct containing variables accessed by shared code
6665 * min_length - The estimated minimum length
6666 * max_length - The estimated maximum length
6667 *
6668 * returns: - E1000_ERR_XXX
6669 * E1000_SUCCESS
6670 *
6671 * This function always returns a ranged length (minimum & maximum).
6672 * So for M88 phy's, this function interprets the one value returned from the
6673 * register to the minimum and maximum range.
6674 * For IGP phy's, the function calculates the range by the AGC registers.
6675 *****************************************************************************/
3ad2cc67 6676static int32_t
1da177e4
LT		 6677e1000_get_cable_length(struct e1000_hw *hw,
6678 uint16_t *min_length,
6679 uint16_t *max_length)
6680{
6681 int32_t ret_val;
6682 uint16_t agc_value = 0;
1da177e4
LT		 6683 uint16_t i, phy_data;
6684 uint16_t cable_length;
6685
6686 DEBUGFUNC("e1000_get_cable_length");
6687
6688 *min_length = *max_length = 0;
6689
6690 /* Use old method for Phy older than IGP */
8fc897b0 6691 if (hw->phy_type == e1000_phy_m88) {
2d7edb92 6692
1da177e4
LT		 6693 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6694 &phy_data);
8fc897b0 6695 if (ret_val)
1da177e4
LT		 6696 return ret_val;
6697 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6698 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6699
6700 /* Convert the enum value to ranged values */
6701 switch (cable_length) {
6702 case e1000_cable_length_50:
6703 *min_length = 0;
6704 *max_length = e1000_igp_cable_length_50;
6705 break;
6706 case e1000_cable_length_50_80:
6707 *min_length = e1000_igp_cable_length_50;
6708 *max_length = e1000_igp_cable_length_80;
6709 break;
6710 case e1000_cable_length_80_110:
6711 *min_length = e1000_igp_cable_length_80;
6712 *max_length = e1000_igp_cable_length_110;
6713 break;
6714 case e1000_cable_length_110_140:
6715 *min_length = e1000_igp_cable_length_110;
6716 *max_length = e1000_igp_cable_length_140;
6717 break;
6718 case e1000_cable_length_140:
6719 *min_length = e1000_igp_cable_length_140;
6720 *max_length = e1000_igp_cable_length_170;
6721 break;
6722 default:
6723 return -E1000_ERR_PHY;
6724 break;
6725 }
6418ecc6
JK		 6726 } else if (hw->phy_type == e1000_phy_gg82563) {
6727 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6728 &phy_data);
6729 if (ret_val)
6730 return ret_val;
6731 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6732
6733 switch (cable_length) {
6734 case e1000_gg_cable_length_60:
6735 *min_length = 0;
6736 *max_length = e1000_igp_cable_length_60;
6737 break;
6738 case e1000_gg_cable_length_60_115:
6739 *min_length = e1000_igp_cable_length_60;
6740 *max_length = e1000_igp_cable_length_115;
6741 break;
6742 case e1000_gg_cable_length_115_150:
6743 *min_length = e1000_igp_cable_length_115;
6744 *max_length = e1000_igp_cable_length_150;
6745 break;
6746 case e1000_gg_cable_length_150:
6747 *min_length = e1000_igp_cable_length_150;
6748 *max_length = e1000_igp_cable_length_180;
6749 break;
6750 default:
6751 return -E1000_ERR_PHY;
6752 break;
6753 }
8fc897b0 6754 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
cd94dd0b
AK		 6755 uint16_t cur_agc_value;
6756 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
1da177e4
LT		 6757 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6758 {IGP01E1000_PHY_AGC_A,
6759 IGP01E1000_PHY_AGC_B,
6760 IGP01E1000_PHY_AGC_C,
6761 IGP01E1000_PHY_AGC_D};
6762 /* Read the AGC registers for all channels */
8fc897b0 6763 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 6764
6765 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
8fc897b0 6766 if (ret_val)
1da177e4
LT		 6767 return ret_val;
6768
cd94dd0b 6769 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
1da177e4 6770
cd94dd0b
AK		 6771 /* Value bound check. */
6772 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6773 (cur_agc_value == 0))
1da177e4
LT		 6774 return -E1000_ERR_PHY;
6775
cd94dd0b 6776 agc_value += cur_agc_value;
1da177e4
LT		 6777
6778 /* Update minimal AGC value. */
cd94dd0b
AK		 6779 if (min_agc_value > cur_agc_value)
6780 min_agc_value = cur_agc_value;
1da177e4
LT		 6781 }
6782
6783 /* Remove the minimal AGC result for length < 50m */
cd94dd0b
AK		 6784 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6785 agc_value -= min_agc_value;
1da177e4
LT		 6786
6787 /* Get the average length of the remaining 3 channels */
6788 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6789 } else {
6790 /* Get the average length of all the 4 channels. */
6791 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6792 }
6793
6794 /* Set the range of the calculated length. */
6795 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6796 IGP01E1000_AGC_RANGE) > 0) ?
6797 (e1000_igp_cable_length_table[agc_value] -
6798 IGP01E1000_AGC_RANGE) : 0;
6799 *max_length = e1000_igp_cable_length_table[agc_value] +
6800 IGP01E1000_AGC_RANGE;
cd94dd0b
AK		 6801 } else if (hw->phy_type == e1000_phy_igp_2 ||
6802 hw->phy_type == e1000_phy_igp_3) {
6803 uint16_t cur_agc_index, max_agc_index = 0;
6804 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
868d5309
MC		 6805 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6806 {IGP02E1000_PHY_AGC_A,
6807 IGP02E1000_PHY_AGC_B,
6808 IGP02E1000_PHY_AGC_C,
6809 IGP02E1000_PHY_AGC_D};
6810 /* Read the AGC registers for all channels */
6811 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6812 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6813 if (ret_val)
6814 return ret_val;
6815
8fc897b0 6816 /* Getting bits 15:9, which represent the combination of course and
868d5309
MC		 6817 * fine gain values. The result is a number that can be put into
6818 * the lookup table to obtain the approximate cable length. */
cd94dd0b
AK		 6819 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6820 IGP02E1000_AGC_LENGTH_MASK;
868d5309 6821
cd94dd0b
AK		 6822 /* Array index bound check. */
6823 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6824 (cur_agc_index == 0))
6825 return -E1000_ERR_PHY;
868d5309 6826
cd94dd0b
AK		 6827 /* Remove min & max AGC values from calculation. */
6828 if (e1000_igp_2_cable_length_table[min_agc_index] >
6829 e1000_igp_2_cable_length_table[cur_agc_index])
6830 min_agc_index = cur_agc_index;
6831 if (e1000_igp_2_cable_length_table[max_agc_index] <
6832 e1000_igp_2_cable_length_table[cur_agc_index])
6833 max_agc_index = cur_agc_index;
6834
6835 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
868d5309
MC		 6836 }
6837
cd94dd0b
AK		 6838 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6839 e1000_igp_2_cable_length_table[max_agc_index]);
868d5309
MC		 6840 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6841
6842 /* Calculate cable length with the error range of +/- 10 meters. */
6843 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6844 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6845 *max_length = agc_value + IGP02E1000_AGC_RANGE;
1da177e4
LT		 6846 }
6847
6848 return E1000_SUCCESS;
6849}
6850
6851/******************************************************************************
6852 * Check the cable polarity
6853 *
6854 * hw - Struct containing variables accessed by shared code
6855 * polarity - output parameter : 0 - Polarity is not reversed
6856 * 1 - Polarity is reversed.
6857 *
6858 * returns: - E1000_ERR_XXX
6859 * E1000_SUCCESS
6860 *
6861 * For phy's older then IGP, this function simply reads the polarity bit in the
6862 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6863 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6864 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6865 * IGP01E1000_PHY_PCS_INIT_REG.
6866 *****************************************************************************/
3ad2cc67 6867static int32_t
1da177e4 6868e1000_check_polarity(struct e1000_hw *hw,
70c6f30a 6869 e1000_rev_polarity *polarity)
1da177e4
LT		 6870{
6871 int32_t ret_val;
6872 uint16_t phy_data;
6873
6874 DEBUGFUNC("e1000_check_polarity");
6875
6418ecc6
JK		 6876 if ((hw->phy_type == e1000_phy_m88) ||
6877 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6878 /* return the Polarity bit in the Status register. */
6879 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6880 &phy_data);
8fc897b0 6881 if (ret_val)
1da177e4 6882 return ret_val;
70c6f30a
JK		 6883 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
6884 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
6885 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
6886
cd94dd0b
AK		 6887 } else if (hw->phy_type == e1000_phy_igp ||
6888 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6889 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6890 /* Read the Status register to check the speed */
6891 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6892 &phy_data);
8fc897b0 6893 if (ret_val)
1da177e4
LT		 6894 return ret_val;
6895
6896 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6897 * find the polarity status */
8fc897b0 6898 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 6899 IGP01E1000_PSSR_SPEED_1000MBPS) {
6900
6901 /* Read the GIG initialization PCS register (0x00B4) */
6902 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6903 &phy_data);
8fc897b0 6904 if (ret_val)
1da177e4
LT		 6905 return ret_val;
6906
6907 /* Check the polarity bits */
70c6f30a
JK		 6908 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
6909 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4
LT		 6910 } else {
6911 /* For 10 Mbps, read the polarity bit in the status register. (for
6912 * 100 Mbps this bit is always 0) */
70c6f30a
JK		 6913 *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
6914 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4 6915 }
cd94dd0b
AK		 6916 } else if (hw->phy_type == e1000_phy_ife) {
6917 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6918 &phy_data);
6919 if (ret_val)
6920 return ret_val;
70c6f30a
JK		 6921 *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
6922 IFE_PESC_POLARITY_REVERSED_SHIFT) ?
6923 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
1da177e4
LT		 6924 }
6925 return E1000_SUCCESS;
6926}
6927
6928/******************************************************************************
6929 * Check if Downshift occured
6930 *
6931 * hw - Struct containing variables accessed by shared code
6932 * downshift - output parameter : 0 - No Downshift ocured.
6933 * 1 - Downshift ocured.
6934 *
6935 * returns: - E1000_ERR_XXX
76c224bc 6936 * E1000_SUCCESS
1da177e4
LT		 6937 *
6938 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6939 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6940 * Link Health register. In IGP this bit is latched high, so the driver must
6941 * read it immediately after link is established.
6942 *****************************************************************************/
3ad2cc67 6943static int32_t
1da177e4
LT		 6944e1000_check_downshift(struct e1000_hw *hw)
6945{
6946 int32_t ret_val;
6947 uint16_t phy_data;
6948
6949 DEBUGFUNC("e1000_check_downshift");
6950
cd94dd0b
AK		 6951 if (hw->phy_type == e1000_phy_igp ||
6952 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6953 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6954 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6955 &phy_data);
8fc897b0 6956 if (ret_val)
1da177e4
LT		 6957 return ret_val;
6958
6959 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6418ecc6
JK		 6960 } else if ((hw->phy_type == e1000_phy_m88) ||
6961 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6962 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6963 &phy_data);
8fc897b0 6964 if (ret_val)
1da177e4
LT		 6965 return ret_val;
6966
6967 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6968 M88E1000_PSSR_DOWNSHIFT_SHIFT;
cd94dd0b
AK		 6969 } else if (hw->phy_type == e1000_phy_ife) {
6970 /* e1000_phy_ife supports 10/100 speed only */
6971 hw->speed_downgraded = FALSE;
1da177e4 6972 }
2d7edb92 6973
1da177e4
LT		 6974 return E1000_SUCCESS;
6975}
6976
6977/*****************************************************************************
6978 *
6979 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6980 * gigabit link is achieved to improve link quality.
6981 *
6982 * hw: Struct containing variables accessed by shared code
6983 *
6984 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6985 * E1000_SUCCESS at any other case.
6986 *
6987 ****************************************************************************/
6988
3ad2cc67 6989static int32_t
1da177e4
LT		 6990e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6991 boolean_t link_up)
6992{
6993 int32_t ret_val;
6994 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6995 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6996 {IGP01E1000_PHY_AGC_PARAM_A,
6997 IGP01E1000_PHY_AGC_PARAM_B,
6998 IGP01E1000_PHY_AGC_PARAM_C,
6999 IGP01E1000_PHY_AGC_PARAM_D};
7000 uint16_t min_length, max_length;
7001
7002 DEBUGFUNC("e1000_config_dsp_after_link_change");
7003
8fc897b0 7004 if (hw->phy_type != e1000_phy_igp)
1da177e4
LT		 7005 return E1000_SUCCESS;
7006
8fc897b0 7007 if (link_up) {
1da177e4 7008 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 7009 if (ret_val) {
1da177e4
LT		 7010 DEBUGOUT("Error getting link speed and duplex\n");
7011 return ret_val;
7012 }
7013
8fc897b0 7014 if (speed == SPEED_1000) {
1da177e4 7015
cd94dd0b
AK		 7016 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7017 if (ret_val)
7018 return ret_val;
1da177e4 7019
8fc897b0 7020 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
1da177e4
LT		 7021 min_length >= e1000_igp_cable_length_50) {
7022
8fc897b0 7023 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 7024 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7025 &phy_data);
8fc897b0 7026 if (ret_val)
1da177e4
LT		 7027 return ret_val;
7028
7029 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7030
7031 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7032 phy_data);
8fc897b0 7033 if (ret_val)
1da177e4
LT		 7034 return ret_val;
7035 }
7036 hw->dsp_config_state = e1000_dsp_config_activated;
7037 }
7038
8fc897b0 7039 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
1da177e4
LT		 7040 (min_length < e1000_igp_cable_length_50)) {
7041
7042 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7043 uint32_t idle_errs = 0;
7044
7045 /* clear previous idle error counts */
7046 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7047 &phy_data);
8fc897b0 7048 if (ret_val)
1da177e4
LT		 7049 return ret_val;
7050
8fc897b0 7051 for (i = 0; i < ffe_idle_err_timeout; i++) {
1da177e4
LT		 7052 udelay(1000);
7053 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7054 &phy_data);
8fc897b0 7055 if (ret_val)
1da177e4
LT		 7056 return ret_val;
7057
7058 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
8fc897b0 7059 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
1da177e4
LT		 7060 hw->ffe_config_state = e1000_ffe_config_active;
7061
7062 ret_val = e1000_write_phy_reg(hw,
7063 IGP01E1000_PHY_DSP_FFE,
7064 IGP01E1000_PHY_DSP_FFE_CM_CP);
8fc897b0 7065 if (ret_val)
1da177e4
LT		 7066 return ret_val;
7067 break;
7068 }
7069
8fc897b0 7070 if (idle_errs)
1da177e4
LT		 7071 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7072 }
7073 }
7074 }
7075 } else {
8fc897b0 7076 if (hw->dsp_config_state == e1000_dsp_config_activated) {
1da177e4
LT		 7077 /* Save off the current value of register 0x2F5B to be restored at
7078 * the end of the routines. */
7079 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7080
8fc897b0 7081 if (ret_val)
1da177e4
LT		 7082 return ret_val;
7083
7084 /* Disable the PHY transmitter */
7085 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7086
8fc897b0 7087 if (ret_val)
1da177e4
LT		 7088 return ret_val;
7089
f8ec4733 7090 mdelay(20);
1da177e4
LT		 7091
7092 ret_val = e1000_write_phy_reg(hw, 0x0000,
7093 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7094 if (ret_val)
1da177e4 7095 return ret_val;
8fc897b0 7096 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4 7097 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
8fc897b0 7098 if (ret_val)
1da177e4
LT		 7099 return ret_val;
7100
7101 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7102 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7103
7104 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
8fc897b0 7105 if (ret_val)
1da177e4
LT		 7106 return ret_val;
7107 }
7108
7109 ret_val = e1000_write_phy_reg(hw, 0x0000,
7110 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7111 if (ret_val)
1da177e4
LT		 7112 return ret_val;
7113
f8ec4733 7114 mdelay(20);
1da177e4
LT		 7115
7116 /* Now enable the transmitter */
7117 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7118
8fc897b0 7119 if (ret_val)
1da177e4
LT		 7120 return ret_val;
7121
7122 hw->dsp_config_state = e1000_dsp_config_enabled;
7123 }
7124
8fc897b0 7125 if (hw->ffe_config_state == e1000_ffe_config_active) {
1da177e4
LT		 7126 /* Save off the current value of register 0x2F5B to be restored at
7127 * the end of the routines. */
7128 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7129
8fc897b0 7130 if (ret_val)
1da177e4
LT		 7131 return ret_val;
7132
7133 /* Disable the PHY transmitter */
7134 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7135
8fc897b0 7136 if (ret_val)
1da177e4
LT		 7137 return ret_val;
7138
f8ec4733 7139 mdelay(20);
1da177e4
LT		 7140
7141 ret_val = e1000_write_phy_reg(hw, 0x0000,
7142 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7143 if (ret_val)
1da177e4
LT		 7144 return ret_val;
7145 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7146 IGP01E1000_PHY_DSP_FFE_DEFAULT);
8fc897b0 7147 if (ret_val)
1da177e4
LT		 7148 return ret_val;
7149
7150 ret_val = e1000_write_phy_reg(hw, 0x0000,
7151 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7152 if (ret_val)
1da177e4
LT		 7153 return ret_val;
7154
f8ec4733 7155 mdelay(20);
1da177e4
LT		 7156
7157 /* Now enable the transmitter */
7158 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7159
8fc897b0 7160 if (ret_val)
1da177e4
LT		 7161 return ret_val;
7162
7163 hw->ffe_config_state = e1000_ffe_config_enabled;
7164 }
7165 }
7166 return E1000_SUCCESS;
7167}
7168
7169/*****************************************************************************
7170 * Set PHY to class A mode
7171 * Assumes the following operations will follow to enable the new class mode.
7172 * 1. Do a PHY soft reset
7173 * 2. Restart auto-negotiation or force link.
7174 *
7175 * hw - Struct containing variables accessed by shared code
7176 ****************************************************************************/
7177static int32_t
7178e1000_set_phy_mode(struct e1000_hw *hw)
7179{
7180 int32_t ret_val;
7181 uint16_t eeprom_data;
7182
7183 DEBUGFUNC("e1000_set_phy_mode");
7184
8fc897b0
AK		 7185 if ((hw->mac_type == e1000_82545_rev_3) &&
7186 (hw->media_type == e1000_media_type_copper)) {
1da177e4 7187 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
8fc897b0 7188 if (ret_val) {
1da177e4
LT		 7189 return ret_val;
7190 }
7191
8fc897b0
AK		 7192 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7193 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1da177e4 7194 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
8fc897b0 7195 if (ret_val)
1da177e4
LT		 7196 return ret_val;
7197 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
8fc897b0 7198 if (ret_val)
1da177e4
LT		 7199 return ret_val;
7200
7201 hw->phy_reset_disable = FALSE;
7202 }
7203 }
7204
7205 return E1000_SUCCESS;
7206}
7207
7208/*****************************************************************************
7209 *
7210 * This function sets the lplu state according to the active flag. When
7211 * activating lplu this function also disables smart speed and vise versa.
7212 * lplu will not be activated unless the device autonegotiation advertisment
7213 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7214 * hw: Struct containing variables accessed by shared code
7215 * active - true to enable lplu false to disable lplu.
7216 *
7217 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7218 * E1000_SUCCESS at any other case.
7219 *
7220 ****************************************************************************/
7221
3ad2cc67 7222static int32_t
1da177e4
LT		 7223e1000_set_d3_lplu_state(struct e1000_hw *hw,
7224 boolean_t active)
7225{
cd94dd0b 7226 uint32_t phy_ctrl = 0;
1da177e4
LT		 7227 int32_t ret_val;
7228 uint16_t phy_data;
7229 DEBUGFUNC("e1000_set_d3_lplu_state");
7230
cd94dd0b
AK		 7231 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7232 && hw->phy_type != e1000_phy_igp_3)
1da177e4
LT		 7233 return E1000_SUCCESS;
7234
7235 /* During driver activity LPLU should not be used or it will attain link
7236 * from the lowest speeds starting from 10Mbps. The capability is used for
7237 * Dx transitions and states */
cd94dd0b 7238 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
2d7edb92 7239 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
cd94dd0b 7240 if (ret_val)
2d7edb92 7241 return ret_val;
cd94dd0b
AK		 7242 } else if (hw->mac_type == e1000_ich8lan) {
7243 /* MAC writes into PHY register based on the state transition
7244 * and start auto-negotiation. SW driver can overwrite the settings
7245 * in CSR PHY power control E1000_PHY_CTRL register. */
7246 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2d7edb92
MC		 7247 } else {
7248 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7249 if (ret_val)
1da177e4 7250 return ret_val;
2d7edb92
MC		 7251 }
7252
8fc897b0
AK		 7253 if (!active) {
7254 if (hw->mac_type == e1000_82541_rev_2 ||
7255 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7256 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7257 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7258 if (ret_val)
2d7edb92
MC		 7259 return ret_val;
7260 } else {
cd94dd0b
AK		 7261 if (hw->mac_type == e1000_ich8lan) {
7262 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7263 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7264 } else {
2d7edb92
MC		 7265 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7266 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7267 phy_data);
7268 if (ret_val)
7269 return ret_val;
cd94dd0b 7270 }
2d7edb92 7271 }
1da177e4
LT		 7272
7273 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7274 * Dx states where the power conservation is most important. During
7275 * driver activity we should enable SmartSpeed, so performance is
7276 * maintained. */
7277 if (hw->smart_speed == e1000_smart_speed_on) {
7278 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7279 &phy_data);
8fc897b0 7280 if (ret_val)
1da177e4
LT		 7281 return ret_val;
7282
7283 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7284 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7285 phy_data);
8fc897b0 7286 if (ret_val)
1da177e4
LT		 7287 return ret_val;
7288 } else if (hw->smart_speed == e1000_smart_speed_off) {
7289 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7290 &phy_data);
35574764 7291 if (ret_val)
1da177e4
LT		 7292 return ret_val;
7293
7294 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7295 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7296 phy_data);
8fc897b0 7297 if (ret_val)
1da177e4
LT		 7298 return ret_val;
7299 }
7300
8fc897b0
AK		 7301 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7302 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7303 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
1da177e4 7304
8fc897b0 7305 if (hw->mac_type == e1000_82541_rev_2 ||
cd94dd0b 7306 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7307 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7308 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7309 if (ret_val)
2d7edb92
MC		 7310 return ret_val;
7311 } else {
cd94dd0b
AK		 7312 if (hw->mac_type == e1000_ich8lan) {
7313 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7314 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7315 } else {
2d7edb92
MC		 7316 phy_data |= IGP02E1000_PM_D3_LPLU;
7317 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7318 phy_data);
7319 if (ret_val)
7320 return ret_val;
cd94dd0b 7321 }
2d7edb92
MC		 7322 }
7323
7324 /* When LPLU is enabled we should disable SmartSpeed */
7325 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7326 if (ret_val)
2d7edb92
MC		 7327 return ret_val;
7328
7329 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7330 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7331 if (ret_val)
2d7edb92
MC		 7332 return ret_val;
7333
7334 }
7335 return E1000_SUCCESS;
7336}
7337
7338/*****************************************************************************
7339 *
7340 * This function sets the lplu d0 state according to the active flag. When
7341 * activating lplu this function also disables smart speed and vise versa.
7342 * lplu will not be activated unless the device autonegotiation advertisment
7343 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7344 * hw: Struct containing variables accessed by shared code
7345 * active - true to enable lplu false to disable lplu.
7346 *
7347 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7348 * E1000_SUCCESS at any other case.
7349 *
7350 ****************************************************************************/
7351
3ad2cc67 7352static int32_t
2d7edb92
MC		 7353e1000_set_d0_lplu_state(struct e1000_hw *hw,
7354 boolean_t active)
7355{
cd94dd0b 7356 uint32_t phy_ctrl = 0;
2d7edb92
MC		 7357 int32_t ret_val;
7358 uint16_t phy_data;
7359 DEBUGFUNC("e1000_set_d0_lplu_state");
7360
8fc897b0 7361 if (hw->mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 7362 return E1000_SUCCESS;
7363
cd94dd0b
AK		 7364 if (hw->mac_type == e1000_ich8lan) {
7365 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7366 } else {
2d7edb92 7367 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7368 if (ret_val)
1da177e4 7369 return ret_val;
cd94dd0b 7370 }
1da177e4 7371
2d7edb92 7372 if (!active) {
cd94dd0b
AK		 7373 if (hw->mac_type == e1000_ich8lan) {
7374 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7375 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7376 } else {
2d7edb92
MC		 7377 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7378 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7379 if (ret_val)
7380 return ret_val;
cd94dd0b 7381 }
2d7edb92
MC		 7382
7383 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7384 * Dx states where the power conservation is most important. During
7385 * driver activity we should enable SmartSpeed, so performance is
7386 * maintained. */
7387 if (hw->smart_speed == e1000_smart_speed_on) {
7388 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7389 &phy_data);
8fc897b0 7390 if (ret_val)
2d7edb92
MC		 7391 return ret_val;
7392
7393 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7394 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7395 phy_data);
8fc897b0 7396 if (ret_val)
2d7edb92
MC		 7397 return ret_val;
7398 } else if (hw->smart_speed == e1000_smart_speed_off) {
7399 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7400 &phy_data);
35574764 7401 if (ret_val)
2d7edb92
MC		 7402 return ret_val;
7403
7404 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7405 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7406 phy_data);
8fc897b0 7407 if (ret_val)
2d7edb92
MC		 7408 return ret_val;
7409 }
7410
7411
7412 } else {
76c224bc 7413
cd94dd0b
AK		 7414 if (hw->mac_type == e1000_ich8lan) {
7415 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7416 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7417 } else {
76c224bc 7418 phy_data |= IGP02E1000_PM_D0_LPLU;
2d7edb92
MC		 7419 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7420 if (ret_val)
7421 return ret_val;
cd94dd0b 7422 }
2d7edb92 7423
1da177e4
LT		 7424 /* When LPLU is enabled we should disable SmartSpeed */
7425 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7426 if (ret_val)
1da177e4
LT		 7427 return ret_val;
7428
7429 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7430 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7431 if (ret_val)
1da177e4
LT		 7432 return ret_val;
7433
7434 }
7435 return E1000_SUCCESS;
7436}
7437
7438/******************************************************************************
7439 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7440 *
7441 * hw - Struct containing variables accessed by shared code
7442 *****************************************************************************/
7443static int32_t
7444e1000_set_vco_speed(struct e1000_hw *hw)
7445{
7446 int32_t ret_val;
7447 uint16_t default_page = 0;
7448 uint16_t phy_data;
7449
7450 DEBUGFUNC("e1000_set_vco_speed");
7451
8fc897b0 7452 switch (hw->mac_type) {
1da177e4
LT		 7453 case e1000_82545_rev_3:
7454 case e1000_82546_rev_3:
7455 break;
7456 default:
7457 return E1000_SUCCESS;
7458 }
7459
7460 /* Set PHY register 30, page 5, bit 8 to 0 */
7461
7462 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
8fc897b0 7463 if (ret_val)
1da177e4
LT		 7464 return ret_val;
7465
7466 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
8fc897b0 7467 if (ret_val)
1da177e4
LT		 7468 return ret_val;
7469
7470 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7471 if (ret_val)
1da177e4
LT		 7472 return ret_val;
7473
7474 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7475 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7476 if (ret_val)
1da177e4
LT		 7477 return ret_val;
7478
7479 /* Set PHY register 30, page 4, bit 11 to 1 */
7480
7481 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
8fc897b0 7482 if (ret_val)
1da177e4
LT		 7483 return ret_val;
7484
7485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7486 if (ret_val)
1da177e4
LT		 7487 return ret_val;
7488
7489 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7490 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7491 if (ret_val)
1da177e4
LT		 7492 return ret_val;
7493
7494 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
8fc897b0 7495 if (ret_val)
1da177e4
LT		 7496 return ret_val;
7497
7498 return E1000_SUCCESS;
7499}
7500
1da177e4 7501
2d7edb92
MC		 7502/*****************************************************************************
7503 * This function reads the cookie from ARC ram.
7504 *
7505 * returns: - E1000_SUCCESS .
7506 ****************************************************************************/
35574764 7507static int32_t
2d7edb92
MC		 7508e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7509{
7510 uint8_t i;
76c224bc 7511 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
2d7edb92 7512 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
1da177e4 7513
2d7edb92
MC		 7514 length = (length >> 2);
7515 offset = (offset >> 2);
1da177e4 7516
2d7edb92
MC		 7517 for (i = 0; i < length; i++) {
7518 *((uint32_t *) buffer + i) =
7519 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7520 }
7521 return E1000_SUCCESS;
7522}
7523
7524
7525/*****************************************************************************
7526 * This function checks whether the HOST IF is enabled for command operaton
7527 * and also checks whether the previous command is completed.
7528 * It busy waits in case of previous command is not completed.
7529 *
76c224bc 7530 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
2d7edb92
MC		 7531 * timeout
7532 * - E1000_SUCCESS for success.
7533 ****************************************************************************/
3ad2cc67 7534static int32_t
2d7edb92
MC		 7535e1000_mng_enable_host_if(struct e1000_hw * hw)
7536{
7537 uint32_t hicr;
7538 uint8_t i;
7539
7540 /* Check that the host interface is enabled. */
7541 hicr = E1000_READ_REG(hw, HICR);
7542 if ((hicr & E1000_HICR_EN) == 0) {
7543 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7544 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7545 }
7546 /* check the previous command is completed */
7547 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7548 hicr = E1000_READ_REG(hw, HICR);
7549 if (!(hicr & E1000_HICR_C))
7550 break;
f8ec4733 7551 mdelay(1);
2d7edb92
MC		 7552 }
7553
76c224bc 7554 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2d7edb92
MC		 7555 DEBUGOUT("Previous command timeout failed .\n");
7556 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7557 }
7558 return E1000_SUCCESS;
7559}
7560
7561/*****************************************************************************
7562 * This function writes the buffer content at the offset given on the host if.
7563 * It also does alignment considerations to do the writes in most efficient way.
7564 * Also fills up the sum of the buffer in *buffer parameter.
7565 *
7566 * returns - E1000_SUCCESS for success.
7567 ****************************************************************************/
3ad2cc67 7568static int32_t
2d7edb92
MC		 7569e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7570 uint16_t length, uint16_t offset, uint8_t *sum)
7571{
7572 uint8_t *tmp;
7573 uint8_t *bufptr = buffer;
8fc897b0 7574 uint32_t data = 0;
2d7edb92
MC		 7575 uint16_t remaining, i, j, prev_bytes;
7576
7577 /* sum = only sum of the data and it is not checksum */
7578
7579 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7580 return -E1000_ERR_PARAM;
7581 }
7582
7583 tmp = (uint8_t *)&data;
7584 prev_bytes = offset & 0x3;
7585 offset &= 0xFFFC;
7586 offset >>= 2;
7587
7588 if (prev_bytes) {
7589 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7590 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7591 *(tmp + j) = *bufptr++;
7592 *sum += *(tmp + j);
7593 }
7594 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7595 length -= j - prev_bytes;
7596 offset++;
7597 }
7598
7599 remaining = length & 0x3;
7600 length -= remaining;
7601
7602 /* Calculate length in DWORDs */
7603 length >>= 2;
7604
7605 /* The device driver writes the relevant command block into the
7606 * ram area. */
7607 for (i = 0; i < length; i++) {
7608 for (j = 0; j < sizeof(uint32_t); j++) {
7609 *(tmp + j) = *bufptr++;
7610 *sum += *(tmp + j);
7611 }
7612
7613 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7614 }
7615 if (remaining) {
7616 for (j = 0; j < sizeof(uint32_t); j++) {
7617 if (j < remaining)
7618 *(tmp + j) = *bufptr++;
7619 else
7620 *(tmp + j) = 0;
7621
7622 *sum += *(tmp + j);
7623 }
7624 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7625 }
7626
7627 return E1000_SUCCESS;
7628}
7629
7630
7631/*****************************************************************************
7632 * This function writes the command header after does the checksum calculation.
7633 *
7634 * returns - E1000_SUCCESS for success.
7635 ****************************************************************************/
3ad2cc67 7636static int32_t
2d7edb92
MC		 7637e1000_mng_write_cmd_header(struct e1000_hw * hw,
7638 struct e1000_host_mng_command_header * hdr)
7639{
7640 uint16_t i;
7641 uint8_t sum;
7642 uint8_t *buffer;
7643
7644 /* Write the whole command header structure which includes sum of
7645 * the buffer */
7646
7647 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7648
7649 sum = hdr->checksum;
7650 hdr->checksum = 0;
7651
7652 buffer = (uint8_t *) hdr;
7653 i = length;
8fc897b0 7654 while (i--)
2d7edb92
MC		 7655 sum += buffer[i];
7656
7657 hdr->checksum = 0 - sum;
7658
7659 length >>= 2;
7660 /* The device driver writes the relevant command block into the ram area. */
4ca213a6 7661 for (i = 0; i < length; i++) {
2d7edb92 7662 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
4ca213a6
AK		 7663 E1000_WRITE_FLUSH(hw);
7664 }
2d7edb92
MC		 7665
7666 return E1000_SUCCESS;
7667}
7668
7669
7670/*****************************************************************************
7671 * This function indicates to ARC that a new command is pending which completes
7672 * one write operation by the driver.
7673 *
7674 * returns - E1000_SUCCESS for success.
7675 ****************************************************************************/
3ad2cc67 7676static int32_t
8fc897b0 7677e1000_mng_write_commit(struct e1000_hw * hw)
2d7edb92
MC		 7678{
7679 uint32_t hicr;
7680
7681 hicr = E1000_READ_REG(hw, HICR);
7682 /* Setting this bit tells the ARC that a new command is pending. */
7683 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7684
7685 return E1000_SUCCESS;
7686}
7687
7688
7689/*****************************************************************************
7690 * This function checks the mode of the firmware.
7691 *
7692 * returns - TRUE when the mode is IAMT or FALSE.
7693 ****************************************************************************/
7694boolean_t
cd94dd0b 7695e1000_check_mng_mode(struct e1000_hw *hw)
2d7edb92
MC		 7696{
7697 uint32_t fwsm;
7698
7699 fwsm = E1000_READ_REG(hw, FWSM);
7700
cd94dd0b
AK		 7701 if (hw->mac_type == e1000_ich8lan) {
7702 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7703 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7704 return TRUE;
7705 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7706 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2d7edb92
MC		 7707 return TRUE;
7708
7709 return FALSE;
7710}
7711
7712
7713/*****************************************************************************
7714 * This function writes the dhcp info .
7715 ****************************************************************************/
7716int32_t
7717e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
35574764 7718 uint16_t length)
2d7edb92
MC		 7719{
7720 int32_t ret_val;
7721 struct e1000_host_mng_command_header hdr;
7722
7723 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7724 hdr.command_length = length;
7725 hdr.reserved1 = 0;
7726 hdr.reserved2 = 0;
7727 hdr.checksum = 0;
7728
7729 ret_val = e1000_mng_enable_host_if(hw);
7730 if (ret_val == E1000_SUCCESS) {
7731 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7732 &(hdr.checksum));
7733 if (ret_val == E1000_SUCCESS) {
7734 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7735 if (ret_val == E1000_SUCCESS)
7736 ret_val = e1000_mng_write_commit(hw);
7737 }
7738 }
7739 return ret_val;
7740}
7741
7742
7743/*****************************************************************************
7744 * This function calculates the checksum.
7745 *
7746 * returns - checksum of buffer contents.
7747 ****************************************************************************/
35574764 7748static uint8_t
2d7edb92
MC		 7749e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7750{
7751 uint8_t sum = 0;
7752 uint32_t i;
7753
7754 if (!buffer)
7755 return 0;
7756
7757 for (i=0; i < length; i++)
7758 sum += buffer[i];
7759
7760 return (uint8_t) (0 - sum);
7761}
7762
7763/*****************************************************************************
7764 * This function checks whether tx pkt filtering needs to be enabled or not.
7765 *
7766 * returns - TRUE for packet filtering or FALSE.
7767 ****************************************************************************/
7768boolean_t
7769e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7770{
7771 /* called in init as well as watchdog timer functions */
7772
7773 int32_t ret_val, checksum;
7774 boolean_t tx_filter = FALSE;
7775 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7776 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7777
7778 if (e1000_check_mng_mode(hw)) {
7779 ret_val = e1000_mng_enable_host_if(hw);
7780 if (ret_val == E1000_SUCCESS) {
7781 ret_val = e1000_host_if_read_cookie(hw, buffer);
7782 if (ret_val == E1000_SUCCESS) {
7783 checksum = hdr->checksum;
7784 hdr->checksum = 0;
7785 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7786 checksum == e1000_calculate_mng_checksum((char *)buffer,
7787 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7788 if (hdr->status &
7789 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7790 tx_filter = TRUE;
7791 } else
7792 tx_filter = TRUE;
7793 } else
7794 tx_filter = TRUE;
7795 }
7796 }
7797
7798 hw->tx_pkt_filtering = tx_filter;
7799 return tx_filter;
7800}
7801
7802/******************************************************************************
7803 * Verifies the hardware needs to allow ARPs to be processed by the host
7804 *
7805 * hw - Struct containing variables accessed by shared code
7806 *
7807 * returns: - TRUE/FALSE
7808 *
7809 *****************************************************************************/
7810uint32_t
7811e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7812{
7813 uint32_t manc;
7814 uint32_t fwsm, factps;
7815
7816 if (hw->asf_firmware_present) {
7817 manc = E1000_READ_REG(hw, MANC);
7818
7819 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7820 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7821 return FALSE;
7822 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7823 fwsm = E1000_READ_REG(hw, FWSM);
7824 factps = E1000_READ_REG(hw, FACTPS);
7825
7826 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7827 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7828 (factps & E1000_FACTPS_MNGCG))
7829 return TRUE;
7830 } else
7831 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7832 return TRUE;
7833 }
7834 return FALSE;
7835}
7836
7837static int32_t
7838e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7839{
7840 int32_t ret_val;
7841 uint16_t mii_status_reg;
7842 uint16_t i;
7843
7844 /* Polarity reversal workaround for forced 10F/10H links. */
7845
7846 /* Disable the transmitter on the PHY */
7847
7848 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7849 if (ret_val)
1da177e4
LT		 7850 return ret_val;
7851 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
8fc897b0 7852 if (ret_val)
1da177e4
LT		 7853 return ret_val;
7854
7855 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7856 if (ret_val)
1da177e4
LT		 7857 return ret_val;
7858
7859 /* This loop will early-out if the NO link condition has been met. */
8fc897b0 7860 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7861 /* Read the MII Status Register and wait for Link Status bit
7862 * to be clear.
7863 */
7864
7865 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7866 if (ret_val)
1da177e4
LT		 7867 return ret_val;
7868
7869 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7870 if (ret_val)
1da177e4
LT		 7871 return ret_val;
7872
8fc897b0 7873 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
f8ec4733 7874 mdelay(100);
1da177e4
LT		 7875 }
7876
7877 /* Recommended delay time after link has been lost */
f8ec4733 7878 mdelay(1000);
1da177e4
LT		 7879
7880 /* Now we will re-enable th transmitter on the PHY */
7881
7882 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7883 if (ret_val)
1da177e4 7884 return ret_val;
f8ec4733 7885 mdelay(50);
1da177e4 7886 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8fc897b0 7887 if (ret_val)
1da177e4 7888 return ret_val;
f8ec4733 7889 mdelay(50);
1da177e4 7890 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8fc897b0 7891 if (ret_val)
1da177e4 7892 return ret_val;
f8ec4733 7893 mdelay(50);
1da177e4 7894 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8fc897b0 7895 if (ret_val)
1da177e4
LT		 7896 return ret_val;
7897
7898 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7899 if (ret_val)
1da177e4
LT		 7900 return ret_val;
7901
7902 /* This loop will early-out if the link condition has been met. */
8fc897b0 7903 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7904 /* Read the MII Status Register and wait for Link Status bit
7905 * to be set.
7906 */
7907
7908 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7909 if (ret_val)
1da177e4
LT		 7910 return ret_val;
7911
7912 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7913 if (ret_val)
1da177e4
LT		 7914 return ret_val;
7915
8fc897b0 7916 if (mii_status_reg & MII_SR_LINK_STATUS) break;
f8ec4733 7917 mdelay(100);
1da177e4
LT		 7918 }
7919 return E1000_SUCCESS;
7920}
7921
2d7edb92
MC		 7922/***************************************************************************
7923 *
7924 * Disables PCI-Express master access.
7925 *
7926 * hw: Struct containing variables accessed by shared code
7927 *
7928 * returns: - none.
7929 *
7930 ***************************************************************************/
3ad2cc67 7931static void
2d7edb92
MC		 7932e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7933{
7934 uint32_t ctrl;
7935
7936 DEBUGFUNC("e1000_set_pci_express_master_disable");
7937
7938 if (hw->bus_type != e1000_bus_type_pci_express)
7939 return;
7940
7941 ctrl = E1000_READ_REG(hw, CTRL);
7942 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7943 E1000_WRITE_REG(hw, CTRL, ctrl);
7944}
7945
2d7edb92
MC		 7946/*******************************************************************************
7947 *
7948 * Disables PCI-Express master access and verifies there are no pending requests
7949 *
7950 * hw: Struct containing variables accessed by shared code
7951 *
7952 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7953 * caused the master requests to be disabled.
7954 * E1000_SUCCESS master requests disabled.
7955 *
7956 ******************************************************************************/
7957int32_t
7958e1000_disable_pciex_master(struct e1000_hw *hw)
7959{
7960 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7961
7962 DEBUGFUNC("e1000_disable_pciex_master");
7963
7964 if (hw->bus_type != e1000_bus_type_pci_express)
7965 return E1000_SUCCESS;
7966
7967 e1000_set_pci_express_master_disable(hw);
7968
8fc897b0
AK		 7969 while (timeout) {
7970 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
2d7edb92
MC		 7971 break;
7972 else
7973 udelay(100);
7974 timeout--;
7975 }
7976
8fc897b0 7977 if (!timeout) {
2d7edb92
MC		 7978 DEBUGOUT("Master requests are pending.\n");
7979 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7980 }
7981
7982 return E1000_SUCCESS;
7983}
7984
7985/*******************************************************************************
7986 *
7987 * Check for EEPROM Auto Read bit done.
7988 *
7989 * hw: Struct containing variables accessed by shared code
7990 *
7991 * returns: - E1000_ERR_RESET if fail to reset MAC
7992 * E1000_SUCCESS at any other case.
7993 *
7994 ******************************************************************************/
3ad2cc67 7995static int32_t
2d7edb92
MC		 7996e1000_get_auto_rd_done(struct e1000_hw *hw)
7997{
7998 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7999
8000 DEBUGFUNC("e1000_get_auto_rd_done");
8001
8002 switch (hw->mac_type) {
8003 default:
f8ec4733 8004 msleep(5);
2d7edb92 8005 break;
868d5309
MC		 8006 case e1000_82571:
8007 case e1000_82572:
2d7edb92 8008 case e1000_82573:
6418ecc6 8009 case e1000_80003es2lan:
cd94dd0b
AK		 8010 case e1000_ich8lan:
8011 while (timeout) {
8012 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8013 break;
f8ec4733 8014 else msleep(1);
2d7edb92
MC		 8015 timeout--;
8016 }
8017
8fc897b0 8018 if (!timeout) {
2d7edb92
MC		 8019 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8020 return -E1000_ERR_RESET;
8021 }
8022 break;
8023 }
8024
fd803241
JK		 8025 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8026 * Need to wait for PHY configuration completion before accessing NVM
8027 * and PHY. */
8028 if (hw->mac_type == e1000_82573)
f8ec4733 8029 msleep(25);
fd803241 8030
2d7edb92
MC		 8031 return E1000_SUCCESS;
8032}
8033
8034/***************************************************************************
8035 * Checks if the PHY configuration is done
8036 *
8037 * hw: Struct containing variables accessed by shared code
8038 *
8039 * returns: - E1000_ERR_RESET if fail to reset MAC
8040 * E1000_SUCCESS at any other case.
8041 *
8042 ***************************************************************************/
3ad2cc67 8043static int32_t
2d7edb92
MC		 8044e1000_get_phy_cfg_done(struct e1000_hw *hw)
8045{
868d5309
MC		 8046 int32_t timeout = PHY_CFG_TIMEOUT;
8047 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8048
2d7edb92
MC		 8049 DEBUGFUNC("e1000_get_phy_cfg_done");
8050
868d5309
MC		 8051 switch (hw->mac_type) {
8052 default:
f8ec4733 8053 mdelay(10);
868d5309 8054 break;
6418ecc6
JK		 8055 case e1000_80003es2lan:
8056 /* Separate *_CFG_DONE_* bit for each port */
8057 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8058 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8059 /* Fall Through */
868d5309
MC		 8060 case e1000_82571:
8061 case e1000_82572:
8062 while (timeout) {
8063 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8064 break;
8065 else
f8ec4733 8066 msleep(1);
868d5309
MC		 8067 timeout--;
8068 }
868d5309
MC		 8069 if (!timeout) {
8070 DEBUGOUT("MNG configuration cycle has not completed.\n");
8071 return -E1000_ERR_RESET;
8072 }
8073 break;
8074 }
2d7edb92
MC		 8075
8076 return E1000_SUCCESS;
8077}
8078
8079/***************************************************************************
8080 *
8081 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8082 * adapter or Eeprom access.
8083 *
8084 * hw: Struct containing variables accessed by shared code
8085 *
8086 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8087 * E1000_SUCCESS at any other case.
8088 *
8089 ***************************************************************************/
3ad2cc67 8090static int32_t
2d7edb92
MC		 8091e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8092{
8093 int32_t timeout;
8094 uint32_t swsm;
8095
8096 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8097
8fc897b0 8098 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8099 return E1000_SUCCESS;
8100
6418ecc6
JK		 8101 if (hw->mac_type == e1000_80003es2lan) {
8102 /* Get the SW semaphore. */
8103 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8104 return -E1000_ERR_EEPROM;
8105 }
2d7edb92
MC		 8106
8107 /* Get the FW semaphore. */
8108 timeout = hw->eeprom.word_size + 1;
8fc897b0 8109 while (timeout) {
2d7edb92
MC		 8110 swsm = E1000_READ_REG(hw, SWSM);
8111 swsm |= E1000_SWSM_SWESMBI;
8112 E1000_WRITE_REG(hw, SWSM, swsm);
8113 /* if we managed to set the bit we got the semaphore. */
8114 swsm = E1000_READ_REG(hw, SWSM);
8fc897b0 8115 if (swsm & E1000_SWSM_SWESMBI)
2d7edb92
MC		 8116 break;
8117
8118 udelay(50);
8119 timeout--;
8120 }
8121
8fc897b0 8122 if (!timeout) {
2d7edb92
MC		 8123 /* Release semaphores */
8124 e1000_put_hw_eeprom_semaphore(hw);
8125 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8126 return -E1000_ERR_EEPROM;
8127 }
8128
8129 return E1000_SUCCESS;
8130}
8131
8132/***************************************************************************
8133 * This function clears HW semaphore bits.
8134 *
8135 * hw: Struct containing variables accessed by shared code
8136 *
8137 * returns: - None.
8138 *
8139 ***************************************************************************/
3ad2cc67 8140static void
2d7edb92
MC		 8141e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8142{
8143 uint32_t swsm;
8144
8145 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8146
8fc897b0 8147 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8148 return;
8149
8150 swsm = E1000_READ_REG(hw, SWSM);
6418ecc6
JK		 8151 if (hw->mac_type == e1000_80003es2lan) {
8152 /* Release both semaphores. */
8153 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8154 } else
868d5309 8155 swsm &= ~(E1000_SWSM_SWESMBI);
2d7edb92
MC		 8156 E1000_WRITE_REG(hw, SWSM, swsm);
8157}
8158
6418ecc6
JK		 8159/***************************************************************************
8160 *
8161 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8162 *
8163 * hw: Struct containing variables accessed by shared code
8164 *
8165 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8166 * E1000_SUCCESS at any other case.
8167 *
8168 ***************************************************************************/
e4c780b1 8169static int32_t
6418ecc6
JK		 8170e1000_get_software_semaphore(struct e1000_hw *hw)
8171{
8172 int32_t timeout = hw->eeprom.word_size + 1;
8173 uint32_t swsm;
8174
8175 DEBUGFUNC("e1000_get_software_semaphore");
8176
35574764 8177 if (hw->mac_type != e1000_80003es2lan) {
6418ecc6 8178 return E1000_SUCCESS;
35574764 8179 }
6418ecc6 8180
8fc897b0 8181 while (timeout) {
6418ecc6
JK		 8182 swsm = E1000_READ_REG(hw, SWSM);
8183 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8fc897b0 8184 if (!(swsm & E1000_SWSM_SMBI))
6418ecc6 8185 break;
f8ec4733 8186 mdelay(1);
6418ecc6
JK		 8187 timeout--;
8188 }
8189
8fc897b0 8190 if (!timeout) {
6418ecc6
JK		 8191 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8192 return -E1000_ERR_RESET;
8193 }
8194
8195 return E1000_SUCCESS;
8196}
8197
8198/***************************************************************************
8199 *
8200 * Release semaphore bit (SMBI).
8201 *
8202 * hw: Struct containing variables accessed by shared code
8203 *
8204 ***************************************************************************/
e4c780b1 8205static void
6418ecc6
JK		 8206e1000_release_software_semaphore(struct e1000_hw *hw)
8207{
8208 uint32_t swsm;
8209
8210 DEBUGFUNC("e1000_release_software_semaphore");
8211
35574764 8212 if (hw->mac_type != e1000_80003es2lan) {
6418ecc6 8213 return;
35574764 8214 }
6418ecc6
JK		 8215
8216 swsm = E1000_READ_REG(hw, SWSM);
8217 /* Release the SW semaphores.*/
8218 swsm &= ~E1000_SWSM_SMBI;
8219 E1000_WRITE_REG(hw, SWSM, swsm);
8220}
8221
2d7edb92
MC		 8222/******************************************************************************
8223 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8224 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8225 * the caller to figure out how to deal with it.
8226 *
8227 * hw - Struct containing variables accessed by shared code
8228 *
8229 * returns: - E1000_BLK_PHY_RESET
8230 * E1000_SUCCESS
8231 *
8232 *****************************************************************************/
8233int32_t
8234e1000_check_phy_reset_block(struct e1000_hw *hw)
8235{
8236 uint32_t manc = 0;
cd94dd0b
AK		 8237 uint32_t fwsm = 0;
8238
8239 if (hw->mac_type == e1000_ich8lan) {
8240 fwsm = E1000_READ_REG(hw, FWSM);
8241 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8242 : E1000_BLK_PHY_RESET;
8243 }
96838a40
JB		 8244
8245 if (hw->mac_type > e1000_82547_rev_2)
2d7edb92
MC		 8246 manc = E1000_READ_REG(hw, MANC);
8247 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
35574764 8248 E1000_BLK_PHY_RESET : E1000_SUCCESS;
2d7edb92
MC		 8249}
8250
3ad2cc67 8251static uint8_t
2d7edb92
MC		 8252e1000_arc_subsystem_valid(struct e1000_hw *hw)
8253{
8254 uint32_t fwsm;
8255
8256 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8257 * may not be provided a DMA clock when no manageability features are
8258 * enabled. We do not want to perform any reads/writes to these registers
8259 * if this is the case. We read FWSM to determine the manageability mode.
8260 */
8261 switch (hw->mac_type) {
868d5309
MC		 8262 case e1000_82571:
8263 case e1000_82572:
2d7edb92 8264 case e1000_82573:
6418ecc6 8265 case e1000_80003es2lan:
2d7edb92 8266 fwsm = E1000_READ_REG(hw, FWSM);
8fc897b0 8267 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
2d7edb92
MC		 8268 return TRUE;
8269 break;
cd94dd0b
AK		 8270 case e1000_ich8lan:
8271 return TRUE;
2d7edb92
MC		 8272 default:
8273 break;
8274 }
8275 return FALSE;
8276}
8277
8278
d37ea5d5
AK		 8279/******************************************************************************
8280 * Configure PCI-Ex no-snoop
8281 *
8282 * hw - Struct containing variables accessed by shared code.
8283 * no_snoop - Bitmap of no-snoop events.
8284 *
8285 * returns: E1000_SUCCESS
8286 *
8287 *****************************************************************************/
e4c780b1 8288static int32_t
d37ea5d5
AK		 8289e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8290{
8291 uint32_t gcr_reg = 0;
8292
8293 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8294
8295 if (hw->bus_type == e1000_bus_type_unknown)
8296 e1000_get_bus_info(hw);
8297
8298 if (hw->bus_type != e1000_bus_type_pci_express)
8299 return E1000_SUCCESS;
8300
8301 if (no_snoop) {
8302 gcr_reg = E1000_READ_REG(hw, GCR);
8303 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8304 gcr_reg |= no_snoop;
8305 E1000_WRITE_REG(hw, GCR, gcr_reg);
8306 }
8307 if (hw->mac_type == e1000_ich8lan) {
8308 uint32_t ctrl_ext;
8309
8310 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8311
8312 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8313 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8314 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8315 }
8316
8317 return E1000_SUCCESS;
8318}
8319
8320/***************************************************************************
8321 *
8322 * Get software semaphore FLAG bit (SWFLAG).
8323 * SWFLAG is used to synchronize the access to all shared resource between
8324 * SW, FW and HW.
8325 *
8326 * hw: Struct containing variables accessed by shared code
8327 *
8328 ***************************************************************************/
e4c780b1 8329static int32_t
d37ea5d5
AK		 8330e1000_get_software_flag(struct e1000_hw *hw)
8331{
8332 int32_t timeout = PHY_CFG_TIMEOUT;
8333 uint32_t extcnf_ctrl;
8334
8335 DEBUGFUNC("e1000_get_software_flag");
8336
8337 if (hw->mac_type == e1000_ich8lan) {
8338 while (timeout) {
8339 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8340 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8341 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8342
8343 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8344 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8345 break;
f8ec4733 8346 mdelay(1);
d37ea5d5
AK		 8347 timeout--;
8348 }
8349
8350 if (!timeout) {
8351 DEBUGOUT("FW or HW locks the resource too long.\n");
8352 return -E1000_ERR_CONFIG;
8353 }
8354 }
8355
8356 return E1000_SUCCESS;
8357}
8358
8359/***************************************************************************
8360 *
8361 * Release software semaphore FLAG bit (SWFLAG).
8362 * SWFLAG is used to synchronize the access to all shared resource between
8363 * SW, FW and HW.
8364 *
8365 * hw: Struct containing variables accessed by shared code
8366 *
8367 ***************************************************************************/
e4c780b1 8368static void
d37ea5d5
AK		 8369e1000_release_software_flag(struct e1000_hw *hw)
8370{
8371 uint32_t extcnf_ctrl;
8372
8373 DEBUGFUNC("e1000_release_software_flag");
8374
8375 if (hw->mac_type == e1000_ich8lan) {
8376 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8377 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8378 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8379 }
8380
8381 return;
8382}
8383
d37ea5d5
AK		 8384/******************************************************************************
8385 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8386 * register.
8387 *
8388 * hw - Struct containing variables accessed by shared code
8389 * offset - offset of word in the EEPROM to read
8390 * data - word read from the EEPROM
8391 * words - number of words to read
8392 *****************************************************************************/
e4c780b1 8393static int32_t
d37ea5d5
AK		 8394e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8395 uint16_t *data)
8396{
8397 int32_t error = E1000_SUCCESS;
8398 uint32_t flash_bank = 0;
8399 uint32_t act_offset = 0;
8400 uint32_t bank_offset = 0;
8401 uint16_t word = 0;
8402 uint16_t i = 0;
8403
8404 /* We need to know which is the valid flash bank. In the event
8405 * that we didn't allocate eeprom_shadow_ram, we may not be
8406 * managing flash_bank. So it cannot be trusted and needs
8407 * to be updated with each read.
8408 */
8409 /* Value of bit 22 corresponds to the flash bank we're on. */
8410 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8411
8412 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8413 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8414
8415 error = e1000_get_software_flag(hw);
8416 if (error != E1000_SUCCESS)
8417 return error;
8418
8419 for (i = 0; i < words; i++) {
8420 if (hw->eeprom_shadow_ram != NULL &&
8421 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8422 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8423 } else {
8424 /* The NVM part needs a byte offset, hence * 2 */
8425 act_offset = bank_offset + ((offset + i) * 2);
8426 error = e1000_read_ich8_word(hw, act_offset, &word);
8427 if (error != E1000_SUCCESS)
8428 break;
8429 data[i] = word;
8430 }
8431 }
8432
8433 e1000_release_software_flag(hw);
8434
8435 return error;
8436}
8437
8438/******************************************************************************
8439 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8440 * register. Actually, writes are written to the shadow ram cache in the hw
8441 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8442 * the NVM, which occurs when the NVM checksum is updated.
8443 *
8444 * hw - Struct containing variables accessed by shared code
8445 * offset - offset of word in the EEPROM to write
8446 * words - number of words to write
8447 * data - words to write to the EEPROM
8448 *****************************************************************************/
e4c780b1 8449static int32_t
d37ea5d5
AK		 8450e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8451 uint16_t *data)
8452{
8453 uint32_t i = 0;
8454 int32_t error = E1000_SUCCESS;
8455
8456 error = e1000_get_software_flag(hw);
8457 if (error != E1000_SUCCESS)
8458 return error;
8459
8460 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8461 * allocated. Subsequent reads to the modified words are read from
8462 * this cached structure as well. Writes will only go into this
8463 * cached structure unless it's followed by a call to
8464 * e1000_update_eeprom_checksum() where it will commit the changes
8465 * and clear the "modified" field.
8466 */
8467 if (hw->eeprom_shadow_ram != NULL) {
8468 for (i = 0; i < words; i++) {
8469 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8470 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8471 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8472 } else {
8473 error = -E1000_ERR_EEPROM;
8474 break;
8475 }
8476 }
8477 } else {
8478 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8479 * as they don't perform any NVM writes. An attempt in doing so
8480 * will result in this error.
8481 */
8482 error = -E1000_ERR_EEPROM;
8483 }
8484
8485 e1000_release_software_flag(hw);
8486
8487 return error;
8488}
8489
8490/******************************************************************************
8491 * This function does initial flash setup so that a new read/write/erase cycle
8492 * can be started.
8493 *
8494 * hw - The pointer to the hw structure
8495 ****************************************************************************/
e4c780b1 8496static int32_t
d37ea5d5
AK		 8497e1000_ich8_cycle_init(struct e1000_hw *hw)
8498{
8499 union ich8_hws_flash_status hsfsts;
8500 int32_t error = E1000_ERR_EEPROM;
8501 int32_t i = 0;
8502
8503 DEBUGFUNC("e1000_ich8_cycle_init");
8504
2df7d59f 8505 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8506
8507 /* May be check the Flash Des Valid bit in Hw status */
8508 if (hsfsts.hsf_status.fldesvalid == 0) {
8509 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8510 return error;
8511 }
8512
8513 /* Clear FCERR in Hw status by writing 1 */
8514 /* Clear DAEL in Hw status by writing a 1 */
8515 hsfsts.hsf_status.flcerr = 1;
8516 hsfsts.hsf_status.dael = 1;
8517
2df7d59f 8518 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
d37ea5d5
AK		 8519
8520 /* Either we should have a hardware SPI cycle in progress bit to check
8521 * against, in order to start a new cycle or FDONE bit should be changed
8522 * in the hardware so that it is 1 after harware reset, which can then be
8523 * used as an indication whether a cycle is in progress or has been
8524 * completed .. we should also have some software semaphore mechanism to
8525 * guard FDONE or the cycle in progress bit so that two threads access to
8526 * those bits can be sequentiallized or a way so that 2 threads dont
8527 * start the cycle at the same time */
8528
8529 if (hsfsts.hsf_status.flcinprog == 0) {
8530 /* There is no cycle running at present, so we can start a cycle */
8531 /* Begin by setting Flash Cycle Done. */
8532 hsfsts.hsf_status.flcdone = 1;
2df7d59f 8533 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
d37ea5d5
AK		 8534 error = E1000_SUCCESS;
8535 } else {
8536 /* otherwise poll for sometime so the current cycle has a chance
8537 * to end before giving up. */
2df7d59f
JK		 8538 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8539 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8540 if (hsfsts.hsf_status.flcinprog == 0) {
8541 error = E1000_SUCCESS;
8542 break;
8543 }
8544 udelay(1);
8545 }
8546 if (error == E1000_SUCCESS) {
8547 /* Successful in waiting for previous cycle to timeout,
8548 * now set the Flash Cycle Done. */
8549 hsfsts.hsf_status.flcdone = 1;
2df7d59f 8550 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
d37ea5d5
AK		 8551 } else {
8552 DEBUGOUT("Flash controller busy, cannot get access");
8553 }
8554 }
8555 return error;
8556}
8557
8558/******************************************************************************
8559 * This function starts a flash cycle and waits for its completion
8560 *
8561 * hw - The pointer to the hw structure
8562 ****************************************************************************/
e4c780b1 8563static int32_t
d37ea5d5
AK		 8564e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8565{
8566 union ich8_hws_flash_ctrl hsflctl;
8567 union ich8_hws_flash_status hsfsts;
8568 int32_t error = E1000_ERR_EEPROM;
8569 uint32_t i = 0;
8570
8571 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2df7d59f 8572 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
d37ea5d5 8573 hsflctl.hsf_ctrl.flcgo = 1;
2df7d59f 8574 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
d37ea5d5
AK		 8575
8576 /* wait till FDONE bit is set to 1 */
8577 do {
2df7d59f 8578 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8579 if (hsfsts.hsf_status.flcdone == 1)
8580 break;
8581 udelay(1);
8582 i++;
8583 } while (i < timeout);
8584 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8585 error = E1000_SUCCESS;
8586 }
8587 return error;
8588}
8589
8590/******************************************************************************
8591 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8592 *
8593 * hw - The pointer to the hw structure
8594 * index - The index of the byte or word to read.
8595 * size - Size of data to read, 1=byte 2=word
8596 * data - Pointer to the word to store the value read.
8597 *****************************************************************************/
e4c780b1 8598static int32_t
d37ea5d5
AK		 8599e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8600 uint32_t size, uint16_t* data)
8601{
8602 union ich8_hws_flash_status hsfsts;
8603 union ich8_hws_flash_ctrl hsflctl;
8604 uint32_t flash_linear_address;
8605 uint32_t flash_data = 0;
8606 int32_t error = -E1000_ERR_EEPROM;
8607 int32_t count = 0;
8608
8609 DEBUGFUNC("e1000_read_ich8_data");
8610
8611 if (size < 1 || size > 2 || data == 0x0 ||
2df7d59f 8612 index > ICH_FLASH_LINEAR_ADDR_MASK)
d37ea5d5
AK		 8613 return error;
8614
2df7d59f 8615 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
d37ea5d5
AK		 8616 hw->flash_base_addr;
8617
8618 do {
8619 udelay(1);
8620 /* Steps */
8621 error = e1000_ich8_cycle_init(hw);
8622 if (error != E1000_SUCCESS)
8623 break;
8624
2df7d59f 8625 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
d37ea5d5
AK		 8626 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8627 hsflctl.hsf_ctrl.fldbcount = size - 1;
2df7d59f
JK		 8628 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8629 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
d37ea5d5
AK		 8630
8631 /* Write the last 24 bits of index into Flash Linear address field in
8632 * Flash Address */
8633 /* TODO: TBD maybe check the index against the size of flash */
8634
2df7d59f 8635 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
d37ea5d5 8636
2df7d59f 8637 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
d37ea5d5
AK		 8638
8639 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8640 * sequence a few more times, else read in (shift in) the Flash Data0,
8641 * the order is least significant byte first msb to lsb */
8642 if (error == E1000_SUCCESS) {
2df7d59f 8643 flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
d37ea5d5
AK		 8644 if (size == 1) {
8645 *data = (uint8_t)(flash_data & 0x000000FF);
8646 } else if (size == 2) {
8647 *data = (uint16_t)(flash_data & 0x0000FFFF);
8648 }
8649 break;
8650 } else {
8651 /* If we've gotten here, then things are probably completely hosed,
8652 * but if the error condition is detected, it won't hurt to give
2df7d59f 8653 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
d37ea5d5 8654 */
2df7d59f 8655 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8656 if (hsfsts.hsf_status.flcerr == 1) {
8657 /* Repeat for some time before giving up. */
8658 continue;
8659 } else if (hsfsts.hsf_status.flcdone == 0) {
8660 DEBUGOUT("Timeout error - flash cycle did not complete.");
8661 break;
8662 }
8663 }
2df7d59f 8664 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
d37ea5d5
AK		 8665
8666 return error;
8667}
8668
8669/******************************************************************************
8670 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8671 *
8672 * hw - The pointer to the hw structure
8673 * index - The index of the byte/word to read.
8674 * size - Size of data to read, 1=byte 2=word
8675 * data - The byte(s) to write to the NVM.
8676 *****************************************************************************/
e4c780b1 8677static int32_t
d37ea5d5
AK		 8678e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8679 uint16_t data)
8680{
8681 union ich8_hws_flash_status hsfsts;
8682 union ich8_hws_flash_ctrl hsflctl;
8683 uint32_t flash_linear_address;
8684 uint32_t flash_data = 0;
8685 int32_t error = -E1000_ERR_EEPROM;
8686 int32_t count = 0;
8687
8688 DEBUGFUNC("e1000_write_ich8_data");
8689
8690 if (size < 1 || size > 2 || data > size * 0xff ||
2df7d59f 8691 index > ICH_FLASH_LINEAR_ADDR_MASK)
d37ea5d5
AK		 8692 return error;
8693
2df7d59f 8694 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
d37ea5d5
AK		 8695 hw->flash_base_addr;
8696
8697 do {
8698 udelay(1);
8699 /* Steps */
8700 error = e1000_ich8_cycle_init(hw);
8701 if (error != E1000_SUCCESS)
8702 break;
8703
2df7d59f 8704 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
d37ea5d5
AK		 8705 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8706 hsflctl.hsf_ctrl.fldbcount = size -1;
2df7d59f
JK		 8707 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8708 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
d37ea5d5
AK		 8709
8710 /* Write the last 24 bits of index into Flash Linear address field in
8711 * Flash Address */
2df7d59f 8712 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
d37ea5d5
AK		 8713
8714 if (size == 1)
8715 flash_data = (uint32_t)data & 0x00FF;
8716 else
8717 flash_data = (uint32_t)data;
8718
2df7d59f 8719 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
d37ea5d5
AK		 8720
8721 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8722 * sequence a few more times else done */
2df7d59f 8723 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
d37ea5d5
AK		 8724 if (error == E1000_SUCCESS) {
8725 break;
8726 } else {
8727 /* If we're here, then things are most likely completely hosed,
8728 * but if the error condition is detected, it won't hurt to give
2df7d59f 8729 * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
d37ea5d5 8730 */
2df7d59f 8731 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8732 if (hsfsts.hsf_status.flcerr == 1) {
8733 /* Repeat for some time before giving up. */
8734 continue;
8735 } else if (hsfsts.hsf_status.flcdone == 0) {
8736 DEBUGOUT("Timeout error - flash cycle did not complete.");
8737 break;
8738 }
8739 }
2df7d59f 8740 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
d37ea5d5
AK		 8741
8742 return error;
8743}
8744
8745/******************************************************************************
8746 * Reads a single byte from the NVM using the ICH8 flash access registers.
8747 *
8748 * hw - pointer to e1000_hw structure
8749 * index - The index of the byte to read.
8750 * data - Pointer to a byte to store the value read.
8751 *****************************************************************************/
e4c780b1 8752static int32_t
d37ea5d5
AK		 8753e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8754{
8755 int32_t status = E1000_SUCCESS;
8756 uint16_t word = 0;
8757
8758 status = e1000_read_ich8_data(hw, index, 1, &word);
8759 if (status == E1000_SUCCESS) {
8760 *data = (uint8_t)word;
8761 }
8762
8763 return status;
8764}
8765
8766/******************************************************************************
8767 * Writes a single byte to the NVM using the ICH8 flash access registers.
8768 * Performs verification by reading back the value and then going through
8769 * a retry algorithm before giving up.
8770 *
8771 * hw - pointer to e1000_hw structure
8772 * index - The index of the byte to write.
8773 * byte - The byte to write to the NVM.
8774 *****************************************************************************/
e4c780b1 8775static int32_t
d37ea5d5
AK		 8776e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8777{
8778 int32_t error = E1000_SUCCESS;
2a88c173 8779 int32_t program_retries = 0;
d37ea5d5 8780
2a88c173 8781 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
d37ea5d5 8782
2a88c173
JK		 8783 error = e1000_write_ich8_byte(hw, index, byte);
8784
8785 if (error != E1000_SUCCESS) {
8786 for (program_retries = 0; program_retries < 100; program_retries++) {
8787 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8788 error = e1000_write_ich8_byte(hw, index, byte);
8789 udelay(100);
8790 if (error == E1000_SUCCESS)
8791 break;
8792 }
d37ea5d5 8793 }
2a88c173 8794
d37ea5d5
AK		 8795 if (program_retries == 100)
8796 error = E1000_ERR_EEPROM;
8797
8798 return error;
8799}
8800
8801/******************************************************************************
8802 * Writes a single byte to the NVM using the ICH8 flash access registers.
8803 *
8804 * hw - pointer to e1000_hw structure
8805 * index - The index of the byte to read.
8806 * data - The byte to write to the NVM.
8807 *****************************************************************************/
e4c780b1 8808static int32_t
d37ea5d5
AK		 8809e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8810{
8811 int32_t status = E1000_SUCCESS;
8812 uint16_t word = (uint16_t)data;
8813
8814 status = e1000_write_ich8_data(hw, index, 1, word);
8815
8816 return status;
8817}
8818
8819/******************************************************************************
8820 * Reads a word from the NVM using the ICH8 flash access registers.
8821 *
8822 * hw - pointer to e1000_hw structure
8823 * index - The starting byte index of the word to read.
8824 * data - Pointer to a word to store the value read.
8825 *****************************************************************************/
e4c780b1 8826static int32_t
d37ea5d5
AK		 8827e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8828{
8829 int32_t status = E1000_SUCCESS;
8830 status = e1000_read_ich8_data(hw, index, 2, data);
8831 return status;
8832}
8833
8834/******************************************************************************
2a88c173
JK		 8835 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8836 * based.
d37ea5d5
AK		 8837 *
8838 * hw - pointer to e1000_hw structure
2a88c173 8839 * bank - 0 for first bank, 1 for second bank
d37ea5d5 8840 *
2a88c173
JK		 8841 * Note that this function may actually erase as much as 8 or 64 KBytes. The
8842 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
8843 * bank size may be 4, 8 or 64 KBytes
d37ea5d5 8844 *****************************************************************************/
2a88c173
JK		 8845int32_t
8846e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
d37ea5d5
AK		 8847{
8848 union ich8_hws_flash_status hsfsts;
8849 union ich8_hws_flash_ctrl hsflctl;
8850 uint32_t flash_linear_address;
8851 int32_t count = 0;
8852 int32_t error = E1000_ERR_EEPROM;
2a88c173
JK		 8853 int32_t iteration;
8854 int32_t sub_sector_size = 0;
8855 int32_t bank_size;
d37ea5d5
AK		 8856 int32_t j = 0;
8857 int32_t error_flag = 0;
8858
2df7d59f 8859 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8860
8861 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8862 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8863 * consecutive sectors. The start index for the nth Hw sector can be
2a88c173 8864 * calculated as bank * 4096 + n * 256
d37ea5d5
AK		 8865 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8866 * The start index for the nth Hw sector can be calculated
2a88c173
JK		 8867 * as bank * 4096
8868 * 10: The HW sector is 8K bytes
8869 * 11: The Hw sector size is 64K bytes */
d37ea5d5
AK		 8870 if (hsfsts.hsf_status.berasesz == 0x0) {
8871 /* Hw sector size 256 */
2df7d59f
JK		 8872 sub_sector_size = ICH_FLASH_SEG_SIZE_256;
8873 bank_size = ICH_FLASH_SECTOR_SIZE;
8874 iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
d37ea5d5 8875 } else if (hsfsts.hsf_status.berasesz == 0x1) {
2df7d59f 8876 bank_size = ICH_FLASH_SEG_SIZE_4K;
d37ea5d5
AK		 8877 iteration = 1;
8878 } else if (hsfsts.hsf_status.berasesz == 0x3) {
2df7d59f 8879 bank_size = ICH_FLASH_SEG_SIZE_64K;
d37ea5d5
AK		 8880 iteration = 1;
8881 } else {
8882 return error;
8883 }
8884
8885 for (j = 0; j < iteration ; j++) {
8886 do {
8887 count++;
8888 /* Steps */
8889 error = e1000_ich8_cycle_init(hw);
8890 if (error != E1000_SUCCESS) {
8891 error_flag = 1;
8892 break;
8893 }
8894
8895 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8896 * Control */
2df7d59f
JK		 8897 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8898 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
8899 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
d37ea5d5
AK		 8900
8901 /* Write the last 24 bits of an index within the block into Flash
8902 * Linear address field in Flash Address. This probably needs to
2a88c173
JK		 8903 * be calculated here based off the on-chip erase sector size and
8904 * the software bank size (4, 8 or 64 KBytes) */
8905 flash_linear_address = bank * bank_size + j * sub_sector_size;
d37ea5d5 8906 flash_linear_address += hw->flash_base_addr;
2df7d59f 8907 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
d37ea5d5 8908
2df7d59f 8909 E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
d37ea5d5 8910
2df7d59f 8911 error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
d37ea5d5
AK		 8912 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8913 * sequence a few more times else Done */
8914 if (error == E1000_SUCCESS) {
8915 break;
8916 } else {
2df7d59f 8917 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
d37ea5d5
AK		 8918 if (hsfsts.hsf_status.flcerr == 1) {
8919 /* repeat for some time before giving up */
8920 continue;
8921 } else if (hsfsts.hsf_status.flcdone == 0) {
8922 error_flag = 1;
8923 break;
8924 }
8925 }
2df7d59f 8926 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
d37ea5d5
AK		 8927 if (error_flag == 1)
8928 break;
8929 }
8930 if (error_flag != 1)
8931 error = E1000_SUCCESS;
8932 return error;
8933}
8934
e4c780b1 8935static int32_t
d37ea5d5
AK		 8936e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
8937 uint32_t cnf_base_addr, uint32_t cnf_size)
8938{
8939 uint32_t ret_val = E1000_SUCCESS;
8940 uint16_t word_addr, reg_data, reg_addr;
8941 uint16_t i;
8942
8943 /* cnf_base_addr is in DWORD */
8944 word_addr = (uint16_t)(cnf_base_addr << 1);
8945
8946 /* cnf_size is returned in size of dwords */
8947 for (i = 0; i < cnf_size; i++) {
8948 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
8949 if (ret_val)
8950 return ret_val;
8951
8952 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
8953 if (ret_val)
8954 return ret_val;
8955
8956 ret_val = e1000_get_software_flag(hw);
8957 if (ret_val != E1000_SUCCESS)
8958 return ret_val;
8959
8960 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
8961
8962 e1000_release_software_flag(hw);
8963 }
8964
8965 return ret_val;
8966}
8967
8968
2a88c173
JK		 8969/******************************************************************************
8970 * This function initializes the PHY from the NVM on ICH8 platforms. This
8971 * is needed due to an issue where the NVM configuration is not properly
8972 * autoloaded after power transitions. Therefore, after each PHY reset, we
8973 * will load the configuration data out of the NVM manually.
8974 *
8975 * hw: Struct containing variables accessed by shared code
8976 *****************************************************************************/
e4c780b1 8977static int32_t
d37ea5d5
AK		 8978e1000_init_lcd_from_nvm(struct e1000_hw *hw)
8979{
8980 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
8981
8982 if (hw->phy_type != e1000_phy_igp_3)
8983 return E1000_SUCCESS;
8984
8985 /* Check if SW needs configure the PHY */
8986 reg_data = E1000_READ_REG(hw, FEXTNVM);
8987 if (!(reg_data & FEXTNVM_SW_CONFIG))
8988 return E1000_SUCCESS;
8989
8990 /* Wait for basic configuration completes before proceeding*/
8991 loop = 0;
8992 do {
8993 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
8994 udelay(100);
8995 loop++;
8996 } while ((!reg_data) && (loop < 50));
8997
8998 /* Clear the Init Done bit for the next init event */
8999 reg_data = E1000_READ_REG(hw, STATUS);
9000 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9001 E1000_WRITE_REG(hw, STATUS, reg_data);
9002
9003 /* Make sure HW does not configure LCD from PHY extended configuration
9004 before SW configuration */
9005 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9006 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9007 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9008 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9009 cnf_size >>= 16;
9010 if (cnf_size) {
9011 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9012 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9013 /* cnf_base_addr is in DWORD */
9014 cnf_base_addr >>= 16;
9015
9016 /* Configure LCD from extended configuration region. */
9017 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9018 cnf_size);
9019 if (ret_val)
9020 return ret_val;
9021 }
9022 }
9023
9024 return E1000_SUCCESS;
9025}
9026
Linux kernel - Deliverables
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