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Merge 2.6.38-rc5 into staging-next
[deliverable/linux.git] / drivers / net / e1000 / e1000_hw.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
120a5d0d 27 */
1da177e4
LT		 28
29/* e1000_hw.c
30 * Shared functions for accessing and configuring the MAC
31 */
32
675ad473 33#include "e1000.h"
1da177e4 34
406874a7 35static s32 e1000_check_downshift(struct e1000_hw *hw);
64798845
JP		 36static s32 e1000_check_polarity(struct e1000_hw *hw,
37 e1000_rev_polarity *polarity);
35574764
NN		 38static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
39static void e1000_clear_vfta(struct e1000_hw *hw);
406874a7 40static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
64798845 41 bool link_up);
406874a7
JP		 42static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
43static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
406874a7 44static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
64798845
JP		 45static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
46 u16 *max_length);
406874a7 47static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
406874a7 48static s32 e1000_id_led_init(struct e1000_hw *hw);
35574764 49static void e1000_init_rx_addrs(struct e1000_hw *hw);
64798845
JP		 50static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
51 struct e1000_phy_info *phy_info);
64798845
JP		 52static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
53 struct e1000_phy_info *phy_info);
406874a7 54static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
406874a7
JP		 55static s32 e1000_wait_autoneg(struct e1000_hw *hw);
56static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value);
57static s32 e1000_set_phy_type(struct e1000_hw *hw);
1da177e4 58static void e1000_phy_init_script(struct e1000_hw *hw);
406874a7
JP		 59static s32 e1000_setup_copper_link(struct e1000_hw *hw);
60static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
61static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
62static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
63static s32 e1000_config_mac_to_phy(struct e1000_hw *hw);
64static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
65static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
120a5d0d 66static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count);
406874a7
JP		 67static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw);
68static s32 e1000_phy_reset_dsp(struct e1000_hw *hw);
69static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset,
120a5d0d 70 u16 words, u16 *data);
64798845
JP		 71static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
72 u16 words, u16 *data);
406874a7
JP		 73static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw);
74static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd);
75static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd);
64798845 76static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count);
406874a7 77static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
64798845 78 u16 phy_data);
120a5d0d 79static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
64798845 80 u16 *phy_data);
406874a7
JP		 81static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count);
82static s32 e1000_acquire_eeprom(struct e1000_hw *hw);
1da177e4
LT		 83static void e1000_release_eeprom(struct e1000_hw *hw);
84static void e1000_standby_eeprom(struct e1000_hw *hw);
406874a7
JP		 85static s32 e1000_set_vco_speed(struct e1000_hw *hw);
86static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw);
87static s32 e1000_set_phy_mode(struct e1000_hw *hw);
120a5d0d
JB		 88static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
89 u16 *data);
90static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
91 u16 *data);
1da177e4
LT		 92
93/* IGP cable length table */
94static const
120a5d0d
JB		 95u16 e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = {
96 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
97 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
98 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
99 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
100 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
101 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100,
102 100,
103 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
104 110, 110,
105 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120,
106 120, 120
107};
1da177e4 108
78566fec
CL		 109static DEFINE_SPINLOCK(e1000_eeprom_lock);
110
120a5d0d
JB		 111/**
112 * e1000_set_phy_type - Set the phy type member in the hw struct.
113 * @hw: Struct containing variables accessed by shared code
114 */
64798845 115static s32 e1000_set_phy_type(struct e1000_hw *hw)
1da177e4 116{
675ad473 117 e_dbg("e1000_set_phy_type");
1da177e4 118
120a5d0d
JB		 119 if (hw->mac_type == e1000_undefined)
120 return -E1000_ERR_PHY_TYPE;
1da177e4 121
120a5d0d
JB		 122 switch (hw->phy_id) {
123 case M88E1000_E_PHY_ID:
124 case M88E1000_I_PHY_ID:
125 case M88E1011_I_PHY_ID:
126 case M88E1111_I_PHY_ID:
cf8e09b0 127 case M88E1118_E_PHY_ID:
120a5d0d
JB		 128 hw->phy_type = e1000_phy_m88;
129 break;
130 case IGP01E1000_I_PHY_ID:
131 if (hw->mac_type == e1000_82541 ||
132 hw->mac_type == e1000_82541_rev_2 ||
133 hw->mac_type == e1000_82547 ||
5377a416 134 hw->mac_type == e1000_82547_rev_2)
120a5d0d 135 hw->phy_type = e1000_phy_igp;
5377a416
DB		 136 break;
137 case RTL8211B_PHY_ID:
138 hw->phy_type = e1000_phy_8211;
139 break;
140 case RTL8201N_PHY_ID:
141 hw->phy_type = e1000_phy_8201;
142 break;
120a5d0d
JB		 143 default:
144 /* Should never have loaded on this device */
145 hw->phy_type = e1000_phy_undefined;
146 return -E1000_ERR_PHY_TYPE;
147 }
1da177e4 148
120a5d0d
JB		 149 return E1000_SUCCESS;
150}
1da177e4 151
120a5d0d
JB		 152/**
153 * e1000_phy_init_script - IGP phy init script - initializes the GbE PHY
154 * @hw: Struct containing variables accessed by shared code
155 */
156static void e1000_phy_init_script(struct e1000_hw *hw)
157{
158 u32 ret_val;
159 u16 phy_saved_data;
160
675ad473 161 e_dbg("e1000_phy_init_script");
120a5d0d
JB		 162
163 if (hw->phy_init_script) {
164 msleep(20);
165
166 /* Save off the current value of register 0x2F5B to be restored at
167 * the end of this routine. */
168 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
169
170 /* Disabled the PHY transmitter */
171 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
172 msleep(20);
173
174 e1000_write_phy_reg(hw, 0x0000, 0x0140);
175 msleep(5);
176
177 switch (hw->mac_type) {
178 case e1000_82541:
179 case e1000_82547:
180 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
181 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
182 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
183 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
184 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
185 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
186 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
187 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
188 e1000_write_phy_reg(hw, 0x2010, 0x0008);
189 break;
1da177e4 190
120a5d0d
JB		 191 case e1000_82541_rev_2:
192 case e1000_82547_rev_2:
193 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
194 break;
195 default:
196 break;
197 }
1da177e4 198
120a5d0d
JB		 199 e1000_write_phy_reg(hw, 0x0000, 0x3300);
200 msleep(20);
201
202 /* Now enable the transmitter */
203 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
204
205 if (hw->mac_type == e1000_82547) {
206 u16 fused, fine, coarse;
207
208 /* Move to analog registers page */
209 e1000_read_phy_reg(hw,
210 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
211 &fused);
212
213 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
214 e1000_read_phy_reg(hw,
215 IGP01E1000_ANALOG_FUSE_STATUS,
216 &fused);
217
218 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
219 coarse =
220 fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
221
222 if (coarse >
223 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
224 coarse -=
225 IGP01E1000_ANALOG_FUSE_COARSE_10;
226 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
227 } else if (coarse ==
228 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
229 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
230
231 fused =
232 (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
233 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
234 (coarse &
235 IGP01E1000_ANALOG_FUSE_COARSE_MASK);
236
237 e1000_write_phy_reg(hw,
238 IGP01E1000_ANALOG_FUSE_CONTROL,
239 fused);
240 e1000_write_phy_reg(hw,
241 IGP01E1000_ANALOG_FUSE_BYPASS,
242 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
243 }
244 }
245 }
1da177e4
LT		 246}
247
120a5d0d
JB		 248/**
249 * e1000_set_mac_type - Set the mac type member in the hw struct.
250 * @hw: Struct containing variables accessed by shared code
251 */
64798845 252s32 e1000_set_mac_type(struct e1000_hw *hw)
1da177e4 253{
675ad473 254 e_dbg("e1000_set_mac_type");
bd2371eb
JG		 255
256 switch (hw->device_id) {
257 case E1000_DEV_ID_82542:
258 switch (hw->revision_id) {
259 case E1000_82542_2_0_REV_ID:
260 hw->mac_type = e1000_82542_rev2_0;
261 break;
262 case E1000_82542_2_1_REV_ID:
263 hw->mac_type = e1000_82542_rev2_1;
264 break;
265 default:
266 /* Invalid 82542 revision ID */
267 return -E1000_ERR_MAC_TYPE;
268 }
269 break;
270 case E1000_DEV_ID_82543GC_FIBER:
271 case E1000_DEV_ID_82543GC_COPPER:
272 hw->mac_type = e1000_82543;
273 break;
274 case E1000_DEV_ID_82544EI_COPPER:
275 case E1000_DEV_ID_82544EI_FIBER:
276 case E1000_DEV_ID_82544GC_COPPER:
277 case E1000_DEV_ID_82544GC_LOM:
278 hw->mac_type = e1000_82544;
279 break;
280 case E1000_DEV_ID_82540EM:
281 case E1000_DEV_ID_82540EM_LOM:
282 case E1000_DEV_ID_82540EP:
283 case E1000_DEV_ID_82540EP_LOM:
284 case E1000_DEV_ID_82540EP_LP:
285 hw->mac_type = e1000_82540;
286 break;
287 case E1000_DEV_ID_82545EM_COPPER:
288 case E1000_DEV_ID_82545EM_FIBER:
289 hw->mac_type = e1000_82545;
290 break;
291 case E1000_DEV_ID_82545GM_COPPER:
292 case E1000_DEV_ID_82545GM_FIBER:
293 case E1000_DEV_ID_82545GM_SERDES:
294 hw->mac_type = e1000_82545_rev_3;
295 break;
296 case E1000_DEV_ID_82546EB_COPPER:
297 case E1000_DEV_ID_82546EB_FIBER:
298 case E1000_DEV_ID_82546EB_QUAD_COPPER:
299 hw->mac_type = e1000_82546;
300 break;
301 case E1000_DEV_ID_82546GB_COPPER:
302 case E1000_DEV_ID_82546GB_FIBER:
303 case E1000_DEV_ID_82546GB_SERDES:
304 case E1000_DEV_ID_82546GB_PCIE:
305 case E1000_DEV_ID_82546GB_QUAD_COPPER:
306 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
307 hw->mac_type = e1000_82546_rev_3;
308 break;
309 case E1000_DEV_ID_82541EI:
310 case E1000_DEV_ID_82541EI_MOBILE:
311 case E1000_DEV_ID_82541ER_LOM:
312 hw->mac_type = e1000_82541;
313 break;
314 case E1000_DEV_ID_82541ER:
315 case E1000_DEV_ID_82541GI:
316 case E1000_DEV_ID_82541GI_LF:
317 case E1000_DEV_ID_82541GI_MOBILE:
318 hw->mac_type = e1000_82541_rev_2;
319 break;
320 case E1000_DEV_ID_82547EI:
321 case E1000_DEV_ID_82547EI_MOBILE:
322 hw->mac_type = e1000_82547;
323 break;
324 case E1000_DEV_ID_82547GI:
325 hw->mac_type = e1000_82547_rev_2;
326 break;
5377a416
DB		 327 case E1000_DEV_ID_INTEL_CE4100_GBE:
328 hw->mac_type = e1000_ce4100;
329 break;
bd2371eb
JG		 330 default:
331 /* Should never have loaded on this device */
332 return -E1000_ERR_MAC_TYPE;
333 }
334
335 switch (hw->mac_type) {
bd2371eb
JG		 336 case e1000_82541:
337 case e1000_82547:
338 case e1000_82541_rev_2:
339 case e1000_82547_rev_2:
c3033b01 340 hw->asf_firmware_present = true;
bd2371eb
JG		 341 break;
342 default:
343 break;
344 }
345
167fb284
JG		 346 /* The 82543 chip does not count tx_carrier_errors properly in
347 * FD mode
348 */
349 if (hw->mac_type == e1000_82543)
c3033b01 350 hw->bad_tx_carr_stats_fd = true;
167fb284 351
15e376b4 352 if (hw->mac_type > e1000_82544)
c3033b01 353 hw->has_smbus = true;
bb8e3311 354
bd2371eb 355 return E1000_SUCCESS;
1da177e4
LT		 356}
357
120a5d0d
JB		 358/**
359 * e1000_set_media_type - Set media type and TBI compatibility.
360 * @hw: Struct containing variables accessed by shared code
361 */
64798845 362void e1000_set_media_type(struct e1000_hw *hw)
1da177e4 363{
120a5d0d
JB		 364 u32 status;
365
675ad473 366 e_dbg("e1000_set_media_type");
120a5d0d
JB		 367
368 if (hw->mac_type != e1000_82543) {
369 /* tbi_compatibility is only valid on 82543 */
370 hw->tbi_compatibility_en = false;
371 }
372
373 switch (hw->device_id) {
374 case E1000_DEV_ID_82545GM_SERDES:
375 case E1000_DEV_ID_82546GB_SERDES:
376 hw->media_type = e1000_media_type_internal_serdes;
377 break;
378 default:
379 switch (hw->mac_type) {
380 case e1000_82542_rev2_0:
381 case e1000_82542_rev2_1:
382 hw->media_type = e1000_media_type_fiber;
383 break;
5377a416
DB		 384 case e1000_ce4100:
385 hw->media_type = e1000_media_type_copper;
386 break;
120a5d0d
JB		 387 default:
388 status = er32(STATUS);
389 if (status & E1000_STATUS_TBIMODE) {
390 hw->media_type = e1000_media_type_fiber;
391 /* tbi_compatibility not valid on fiber */
392 hw->tbi_compatibility_en = false;
393 } else {
394 hw->media_type = e1000_media_type_copper;
395 }
396 break;
397 }
398 }
1da177e4
LT		 399}
400
120a5d0d
JB		 401/**
402 * e1000_reset_hw: reset the hardware completely
403 * @hw: Struct containing variables accessed by shared code
1da177e4 404 *
120a5d0d
JB		 405 * Reset the transmit and receive units; mask and clear all interrupts.
406 */
64798845 407s32 e1000_reset_hw(struct e1000_hw *hw)
1da177e4 408{
120a5d0d
JB		 409 u32 ctrl;
410 u32 ctrl_ext;
411 u32 icr;
412 u32 manc;
413 u32 led_ctrl;
414 s32 ret_val;
415
675ad473 416 e_dbg("e1000_reset_hw");
120a5d0d
JB		 417
418 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
419 if (hw->mac_type == e1000_82542_rev2_0) {
675ad473 420 e_dbg("Disabling MWI on 82542 rev 2.0\n");
120a5d0d
JB		 421 e1000_pci_clear_mwi(hw);
422 }
423
424 /* Clear interrupt mask to stop board from generating interrupts */
675ad473 425 e_dbg("Masking off all interrupts\n");
120a5d0d
JB		 426 ew32(IMC, 0xffffffff);
427
428 /* Disable the Transmit and Receive units. Then delay to allow
429 * any pending transactions to complete before we hit the MAC with
430 * the global reset.
431 */
432 ew32(RCTL, 0);
433 ew32(TCTL, E1000_TCTL_PSP);
434 E1000_WRITE_FLUSH();
435
436 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
437 hw->tbi_compatibility_on = false;
438
439 /* Delay to allow any outstanding PCI transactions to complete before
440 * resetting the device
441 */
442 msleep(10);
443
444 ctrl = er32(CTRL);
445
446 /* Must reset the PHY before resetting the MAC */
447 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
448 ew32(CTRL, (ctrl | E1000_CTRL_PHY_RST));
449 msleep(5);
450 }
451
452 /* Issue a global reset to the MAC. This will reset the chip's
453 * transmit, receive, DMA, and link units. It will not effect
454 * the current PCI configuration. The global reset bit is self-
455 * clearing, and should clear within a microsecond.
456 */
675ad473 457 e_dbg("Issuing a global reset to MAC\n");
120a5d0d
JB		 458
459 switch (hw->mac_type) {
460 case e1000_82544:
461 case e1000_82540:
462 case e1000_82545:
463 case e1000_82546:
464 case e1000_82541:
465 case e1000_82541_rev_2:
466 /* These controllers can't ack the 64-bit write when issuing the
467 * reset, so use IO-mapping as a workaround to issue the reset */
468 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
469 break;
470 case e1000_82545_rev_3:
471 case e1000_82546_rev_3:
472 /* Reset is performed on a shadow of the control register */
473 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
474 break;
5377a416 475 case e1000_ce4100:
120a5d0d
JB		 476 default:
477 ew32(CTRL, (ctrl | E1000_CTRL_RST));
478 break;
479 }
480
481 /* After MAC reset, force reload of EEPROM to restore power-on settings to
482 * device. Later controllers reload the EEPROM automatically, so just wait
483 * for reload to complete.
484 */
485 switch (hw->mac_type) {
486 case e1000_82542_rev2_0:
487 case e1000_82542_rev2_1:
488 case e1000_82543:
489 case e1000_82544:
490 /* Wait for reset to complete */
491 udelay(10);
492 ctrl_ext = er32(CTRL_EXT);
493 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
494 ew32(CTRL_EXT, ctrl_ext);
495 E1000_WRITE_FLUSH();
496 /* Wait for EEPROM reload */
497 msleep(2);
498 break;
499 case e1000_82541:
500 case e1000_82541_rev_2:
501 case e1000_82547:
502 case e1000_82547_rev_2:
503 /* Wait for EEPROM reload */
504 msleep(20);
505 break;
506 default:
507 /* Auto read done will delay 5ms or poll based on mac type */
508 ret_val = e1000_get_auto_rd_done(hw);
509 if (ret_val)
510 return ret_val;
511 break;
512 }
513
514 /* Disable HW ARPs on ASF enabled adapters */
515 if (hw->mac_type >= e1000_82540) {
516 manc = er32(MANC);
517 manc &= ~(E1000_MANC_ARP_EN);
518 ew32(MANC, manc);
519 }
520
521 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
522 e1000_phy_init_script(hw);
523
524 /* Configure activity LED after PHY reset */
525 led_ctrl = er32(LEDCTL);
526 led_ctrl &= IGP_ACTIVITY_LED_MASK;
527 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
528 ew32(LEDCTL, led_ctrl);
529 }
530
531 /* Clear interrupt mask to stop board from generating interrupts */
675ad473 532 e_dbg("Masking off all interrupts\n");
120a5d0d
JB		 533 ew32(IMC, 0xffffffff);
534
535 /* Clear any pending interrupt events. */
536 icr = er32(ICR);
537
538 /* If MWI was previously enabled, reenable it. */
539 if (hw->mac_type == e1000_82542_rev2_0) {
540 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
541 e1000_pci_set_mwi(hw);
542 }
543
544 return E1000_SUCCESS;
1da177e4
LT		 545}
546
120a5d0d
JB		 547/**
548 * e1000_init_hw: Performs basic configuration of the adapter.
549 * @hw: Struct containing variables accessed by shared code
1da177e4
LT		 550 *
551 * Assumes that the controller has previously been reset and is in a
552 * post-reset uninitialized state. Initializes the receive address registers,
553 * multicast table, and VLAN filter table. Calls routines to setup link
554 * configuration and flow control settings. Clears all on-chip counters. Leaves
555 * the transmit and receive units disabled and uninitialized.
120a5d0d 556 */
64798845 557s32 e1000_init_hw(struct e1000_hw *hw)
1da177e4 558{
120a5d0d
JB		 559 u32 ctrl;
560 u32 i;
561 s32 ret_val;
562 u32 mta_size;
563 u32 ctrl_ext;
564
675ad473 565 e_dbg("e1000_init_hw");
120a5d0d
JB		 566
567 /* Initialize Identification LED */
568 ret_val = e1000_id_led_init(hw);
569 if (ret_val) {
675ad473 570 e_dbg("Error Initializing Identification LED\n");
120a5d0d
JB		 571 return ret_val;
572 }
573
574 /* Set the media type and TBI compatibility */
575 e1000_set_media_type(hw);
576
577 /* Disabling VLAN filtering. */
675ad473 578 e_dbg("Initializing the IEEE VLAN\n");
120a5d0d
JB		 579 if (hw->mac_type < e1000_82545_rev_3)
580 ew32(VET, 0);
581 e1000_clear_vfta(hw);
582
583 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
584 if (hw->mac_type == e1000_82542_rev2_0) {
675ad473 585 e_dbg("Disabling MWI on 82542 rev 2.0\n");
120a5d0d
JB		 586 e1000_pci_clear_mwi(hw);
587 ew32(RCTL, E1000_RCTL_RST);
588 E1000_WRITE_FLUSH();
589 msleep(5);
590 }
591
592 /* Setup the receive address. This involves initializing all of the Receive
593 * Address Registers (RARs 0 - 15).
594 */
595 e1000_init_rx_addrs(hw);
596
597 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
598 if (hw->mac_type == e1000_82542_rev2_0) {
599 ew32(RCTL, 0);
600 E1000_WRITE_FLUSH();
601 msleep(1);
602 if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
603 e1000_pci_set_mwi(hw);
604 }
605
606 /* Zero out the Multicast HASH table */
675ad473 607 e_dbg("Zeroing the MTA\n");
120a5d0d
JB		 608 mta_size = E1000_MC_TBL_SIZE;
609 for (i = 0; i < mta_size; i++) {
610 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
611 /* use write flush to prevent Memory Write Block (MWB) from
612 * occurring when accessing our register space */
613 E1000_WRITE_FLUSH();
614 }
615
616 /* Set the PCI priority bit correctly in the CTRL register. This
617 * determines if the adapter gives priority to receives, or if it
618 * gives equal priority to transmits and receives. Valid only on
619 * 82542 and 82543 silicon.
620 */
621 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
622 ctrl = er32(CTRL);
623 ew32(CTRL, ctrl | E1000_CTRL_PRIOR);
624 }
625
626 switch (hw->mac_type) {
627 case e1000_82545_rev_3:
628 case e1000_82546_rev_3:
629 break;
630 default:
631 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
632 if (hw->bus_type == e1000_bus_type_pcix
633 && e1000_pcix_get_mmrbc(hw) > 2048)
634 e1000_pcix_set_mmrbc(hw, 2048);
635 break;
636 }
637
638 /* Call a subroutine to configure the link and setup flow control. */
639 ret_val = e1000_setup_link(hw);
640
641 /* Set the transmit descriptor write-back policy */
642 if (hw->mac_type > e1000_82544) {
643 ctrl = er32(TXDCTL);
644 ctrl =
645 (ctrl & ~E1000_TXDCTL_WTHRESH) |
646 E1000_TXDCTL_FULL_TX_DESC_WB;
647 ew32(TXDCTL, ctrl);
648 }
649
650 /* Clear all of the statistics registers (clear on read). It is
651 * important that we do this after we have tried to establish link
652 * because the symbol error count will increment wildly if there
653 * is no link.
654 */
655 e1000_clear_hw_cntrs(hw);
656
657 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
658 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
659 ctrl_ext = er32(CTRL_EXT);
660 /* Relaxed ordering must be disabled to avoid a parity
661 * error crash in a PCI slot. */
662 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
663 ew32(CTRL_EXT, ctrl_ext);
664 }
665
666 return ret_val;
1da177e4
LT		 667}
668
120a5d0d
JB		 669/**
670 * e1000_adjust_serdes_amplitude - Adjust SERDES output amplitude based on EEPROM setting.
671 * @hw: Struct containing variables accessed by shared code.
672 */
64798845 673static s32 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1da177e4 674{
120a5d0d
JB		 675 u16 eeprom_data;
676 s32 ret_val;
677
675ad473 678 e_dbg("e1000_adjust_serdes_amplitude");
120a5d0d
JB		 679
680 if (hw->media_type != e1000_media_type_internal_serdes)
681 return E1000_SUCCESS;
682
683 switch (hw->mac_type) {
684 case e1000_82545_rev_3:
685 case e1000_82546_rev_3:
686 break;
687 default:
688 return E1000_SUCCESS;
689 }
690
691 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
692 &eeprom_data);
693 if (ret_val) {
694 return ret_val;
695 }
696
697 if (eeprom_data != EEPROM_RESERVED_WORD) {
698 /* Adjust SERDES output amplitude only. */
699 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
700 ret_val =
701 e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
702 if (ret_val)
703 return ret_val;
704 }
705
706 return E1000_SUCCESS;
1da177e4
LT		 707}
708
120a5d0d
JB		 709/**
710 * e1000_setup_link - Configures flow control and link settings.
711 * @hw: Struct containing variables accessed by shared code
1da177e4 712 *
120a5d0d 713 * Determines which flow control settings to use. Calls the appropriate media-
1da177e4
LT		 714 * specific link configuration function. Configures the flow control settings.
715 * Assuming the adapter has a valid link partner, a valid link should be
716 * established. Assumes the hardware has previously been reset and the
717 * transmitter and receiver are not enabled.
120a5d0d 718 */
64798845 719s32 e1000_setup_link(struct e1000_hw *hw)
1da177e4 720{
120a5d0d
JB		 721 u32 ctrl_ext;
722 s32 ret_val;
723 u16 eeprom_data;
724
675ad473 725 e_dbg("e1000_setup_link");
120a5d0d
JB		 726
727 /* Read and store word 0x0F of the EEPROM. This word contains bits
728 * that determine the hardware's default PAUSE (flow control) mode,
729 * a bit that determines whether the HW defaults to enabling or
730 * disabling auto-negotiation, and the direction of the
731 * SW defined pins. If there is no SW over-ride of the flow
732 * control setting, then the variable hw->fc will
733 * be initialized based on a value in the EEPROM.
734 */
735 if (hw->fc == E1000_FC_DEFAULT) {
736 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
737 1, &eeprom_data);
738 if (ret_val) {
675ad473 739 e_dbg("EEPROM Read Error\n");
120a5d0d
JB		 740 return -E1000_ERR_EEPROM;
741 }
742 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
743 hw->fc = E1000_FC_NONE;
744 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
745 EEPROM_WORD0F_ASM_DIR)
746 hw->fc = E1000_FC_TX_PAUSE;
747 else
748 hw->fc = E1000_FC_FULL;
749 }
1da177e4 750
120a5d0d
JB		 751 /* We want to save off the original Flow Control configuration just
752 * in case we get disconnected and then reconnected into a different
753 * hub or switch with different Flow Control capabilities.
754 */
755 if (hw->mac_type == e1000_82542_rev2_0)
756 hw->fc &= (~E1000_FC_TX_PAUSE);
1da177e4 757
120a5d0d
JB		 758 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
759 hw->fc &= (~E1000_FC_RX_PAUSE);
1da177e4 760
120a5d0d 761 hw->original_fc = hw->fc;
1da177e4 762
675ad473 763 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc);
1da177e4 764
120a5d0d
JB		 765 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
766 * polarity value for the SW controlled pins, and setup the
767 * Extended Device Control reg with that info.
768 * This is needed because one of the SW controlled pins is used for
769 * signal detection. So this should be done before e1000_setup_pcs_link()
770 * or e1000_phy_setup() is called.
771 */
772 if (hw->mac_type == e1000_82543) {
773 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
774 1, &eeprom_data);
775 if (ret_val) {
675ad473 776 e_dbg("EEPROM Read Error\n");
120a5d0d
JB		 777 return -E1000_ERR_EEPROM;
778 }
779 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
780 SWDPIO__EXT_SHIFT);
781 ew32(CTRL_EXT, ctrl_ext);
782 }
1da177e4 783
120a5d0d
JB		 784 /* Call the necessary subroutine to configure the link. */
785 ret_val = (hw->media_type == e1000_media_type_copper) ?
786 e1000_setup_copper_link(hw) : e1000_setup_fiber_serdes_link(hw);
2d7edb92 787
120a5d0d
JB		 788 /* Initialize the flow control address, type, and PAUSE timer
789 * registers to their default values. This is done even if flow
790 * control is disabled, because it does not hurt anything to
791 * initialize these registers.
792 */
675ad473 793 e_dbg("Initializing the Flow Control address, type and timer regs\n");
2d7edb92 794
120a5d0d
JB		 795 ew32(FCT, FLOW_CONTROL_TYPE);
796 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH);
797 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW);
2d7edb92 798
120a5d0d 799 ew32(FCTTV, hw->fc_pause_time);
1da177e4 800
120a5d0d
JB		 801 /* Set the flow control receive threshold registers. Normally,
802 * these registers will be set to a default threshold that may be
803 * adjusted later by the driver's runtime code. However, if the
804 * ability to transmit pause frames in not enabled, then these
805 * registers will be set to 0.
806 */
807 if (!(hw->fc & E1000_FC_TX_PAUSE)) {
808 ew32(FCRTL, 0);
809 ew32(FCRTH, 0);
810 } else {
811 /* We need to set up the Receive Threshold high and low water marks
812 * as well as (optionally) enabling the transmission of XON frames.
813 */
814 if (hw->fc_send_xon) {
815 ew32(FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
816 ew32(FCRTH, hw->fc_high_water);
817 } else {
818 ew32(FCRTL, hw->fc_low_water);
819 ew32(FCRTH, hw->fc_high_water);
820 }
821 }
822 return ret_val;
1da177e4
LT		 823}
824
120a5d0d
JB		 825/**
826 * e1000_setup_fiber_serdes_link - prepare fiber or serdes link
827 * @hw: Struct containing variables accessed by shared code
828 *
829 * Manipulates Physical Coding Sublayer functions in order to configure
830 * link. Assumes the hardware has been previously reset and the transmitter
831 * and receiver are not enabled.
832 */
833static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1da177e4 834{
120a5d0d
JB		 835 u32 ctrl;
836 u32 status;
837 u32 txcw = 0;
838 u32 i;
839 u32 signal = 0;
840 s32 ret_val;
841
675ad473 842 e_dbg("e1000_setup_fiber_serdes_link");
120a5d0d
JB		 843
844 /* On adapters with a MAC newer than 82544, SWDP 1 will be
845 * set when the optics detect a signal. On older adapters, it will be
846 * cleared when there is a signal. This applies to fiber media only.
847 * If we're on serdes media, adjust the output amplitude to value
848 * set in the EEPROM.
849 */
850 ctrl = er32(CTRL);
851 if (hw->media_type == e1000_media_type_fiber)
852 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
853
854 ret_val = e1000_adjust_serdes_amplitude(hw);
855 if (ret_val)
856 return ret_val;
857
858 /* Take the link out of reset */
859 ctrl &= ~(E1000_CTRL_LRST);
860
861 /* Adjust VCO speed to improve BER performance */
862 ret_val = e1000_set_vco_speed(hw);
863 if (ret_val)
864 return ret_val;
865
866 e1000_config_collision_dist(hw);
867
868 /* Check for a software override of the flow control settings, and setup
869 * the device accordingly. If auto-negotiation is enabled, then software
870 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
871 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
872 * auto-negotiation is disabled, then software will have to manually
873 * configure the two flow control enable bits in the CTRL register.
874 *
875 * The possible values of the "fc" parameter are:
876 * 0: Flow control is completely disabled
877 * 1: Rx flow control is enabled (we can receive pause frames, but
878 * not send pause frames).
879 * 2: Tx flow control is enabled (we can send pause frames but we do
880 * not support receiving pause frames).
881 * 3: Both Rx and TX flow control (symmetric) are enabled.
882 */
883 switch (hw->fc) {
884 case E1000_FC_NONE:
885 /* Flow control is completely disabled by a software over-ride. */
886 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
887 break;
888 case E1000_FC_RX_PAUSE:
889 /* RX Flow control is enabled and TX Flow control is disabled by a
890 * software over-ride. Since there really isn't a way to advertise
891 * that we are capable of RX Pause ONLY, we will advertise that we
892 * support both symmetric and asymmetric RX PAUSE. Later, we will
893 * disable the adapter's ability to send PAUSE frames.
894 */
895 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
896 break;
897 case E1000_FC_TX_PAUSE:
898 /* TX Flow control is enabled, and RX Flow control is disabled, by a
899 * software over-ride.
900 */
901 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
902 break;
903 case E1000_FC_FULL:
904 /* Flow control (both RX and TX) is enabled by a software over-ride. */
905 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
906 break;
907 default:
675ad473 908 e_dbg("Flow control param set incorrectly\n");
120a5d0d
JB		 909 return -E1000_ERR_CONFIG;
910 break;
911 }
1da177e4 912
120a5d0d
JB		 913 /* Since auto-negotiation is enabled, take the link out of reset (the link
914 * will be in reset, because we previously reset the chip). This will
915 * restart auto-negotiation. If auto-negotiation is successful then the
916 * link-up status bit will be set and the flow control enable bits (RFCE
917 * and TFCE) will be set according to their negotiated value.
918 */
675ad473 919 e_dbg("Auto-negotiation enabled\n");
0fadb059 920
120a5d0d
JB		 921 ew32(TXCW, txcw);
922 ew32(CTRL, ctrl);
923 E1000_WRITE_FLUSH();
1da177e4 924
120a5d0d
JB		 925 hw->txcw = txcw;
926 msleep(1);
1da177e4 927
120a5d0d
JB		 928 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
929 * indication in the Device Status Register. Time-out if a link isn't
930 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
931 * less than 500 milliseconds even if the other end is doing it in SW).
932 * For internal serdes, we just assume a signal is present, then poll.
933 */
934 if (hw->media_type == e1000_media_type_internal_serdes ||
935 (er32(CTRL) & E1000_CTRL_SWDPIN1) == signal) {
675ad473 936 e_dbg("Looking for Link\n");
120a5d0d
JB		 937 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
938 msleep(10);
939 status = er32(STATUS);
940 if (status & E1000_STATUS_LU)
941 break;
942 }
943 if (i == (LINK_UP_TIMEOUT / 10)) {
675ad473 944 e_dbg("Never got a valid link from auto-neg!!!\n");
120a5d0d
JB		 945 hw->autoneg_failed = 1;
946 /* AutoNeg failed to achieve a link, so we'll call
947 * e1000_check_for_link. This routine will force the link up if
948 * we detect a signal. This will allow us to communicate with
949 * non-autonegotiating link partners.
950 */
951 ret_val = e1000_check_for_link(hw);
952 if (ret_val) {
675ad473 953 e_dbg("Error while checking for link\n");
120a5d0d
JB		 954 return ret_val;
955 }
956 hw->autoneg_failed = 0;
957 } else {
958 hw->autoneg_failed = 0;
675ad473 959 e_dbg("Valid Link Found\n");
120a5d0d
JB		 960 }
961 } else {
675ad473 962 e_dbg("No Signal Detected\n");
120a5d0d
JB		 963 }
964 return E1000_SUCCESS;
1da177e4
LT		 965}
966
5377a416
DB		 967/**
968 * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
969 * @hw: Struct containing variables accessed by shared code
970 *
971 * Commits changes to PHY configuration by calling e1000_phy_reset().
972 */
973static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
974{
975 s32 ret_val;
976
977 /* SW reset the PHY so all changes take effect */
978 ret_val = e1000_phy_reset(hw);
979 if (ret_val) {
980 e_dbg("Error Resetting the PHY\n");
981 return ret_val;
982 }
983
984 return E1000_SUCCESS;
985}
986
987static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
988{
989 s32 ret_val;
990 u32 ctrl_aux;
991
992 switch (hw->phy_type) {
993 case e1000_phy_8211:
994 ret_val = e1000_copper_link_rtl_setup(hw);
995 if (ret_val) {
996 e_dbg("e1000_copper_link_rtl_setup failed!\n");
997 return ret_val;
998 }
999 break;
1000 case e1000_phy_8201:
1001 /* Set RMII mode */
1002 ctrl_aux = er32(CTL_AUX);
1003 ctrl_aux |= E1000_CTL_AUX_RMII;
1004 ew32(CTL_AUX, ctrl_aux);
1005 E1000_WRITE_FLUSH();
1006
1007 /* Disable the J/K bits required for receive */
1008 ctrl_aux = er32(CTL_AUX);
1009 ctrl_aux |= 0x4;
1010 ctrl_aux &= ~0x2;
1011 ew32(CTL_AUX, ctrl_aux);
1012 E1000_WRITE_FLUSH();
1013 ret_val = e1000_copper_link_rtl_setup(hw);
1014
1015 if (ret_val) {
1016 e_dbg("e1000_copper_link_rtl_setup failed!\n");
1017 return ret_val;
1018 }
1019 break;
1020 default:
1021 e_dbg("Error Resetting the PHY\n");
1022 return E1000_ERR_PHY_TYPE;
1023 }
1024
1025 return E1000_SUCCESS;
1026}
1027
120a5d0d
JB		 1028/**
1029 * e1000_copper_link_preconfig - early configuration for copper
1030 * @hw: Struct containing variables accessed by shared code
1031 *
1032 * Make sure we have a valid PHY and change PHY mode before link setup.
1033 */
1034static s32 e1000_copper_link_preconfig(struct e1000_hw *hw)
1da177e4 1035{
120a5d0d
JB		 1036 u32 ctrl;
1037 s32 ret_val;
1038 u16 phy_data;
1039
675ad473 1040 e_dbg("e1000_copper_link_preconfig");
120a5d0d
JB		 1041
1042 ctrl = er32(CTRL);
1043 /* With 82543, we need to force speed and duplex on the MAC equal to what
1044 * the PHY speed and duplex configuration is. In addition, we need to
1045 * perform a hardware reset on the PHY to take it out of reset.
1046 */
1047 if (hw->mac_type > e1000_82543) {
1048 ctrl |= E1000_CTRL_SLU;
1049 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1050 ew32(CTRL, ctrl);
1051 } else {
1052 ctrl |=
1053 (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1054 ew32(CTRL, ctrl);
1055 ret_val = e1000_phy_hw_reset(hw);
1056 if (ret_val)
1057 return ret_val;
1058 }
1059
1060 /* Make sure we have a valid PHY */
1061 ret_val = e1000_detect_gig_phy(hw);
1062 if (ret_val) {
675ad473 1063 e_dbg("Error, did not detect valid phy.\n");
120a5d0d
JB		 1064 return ret_val;
1065 }
675ad473 1066 e_dbg("Phy ID = %x\n", hw->phy_id);
120a5d0d
JB		 1067
1068 /* Set PHY to class A mode (if necessary) */
1069 ret_val = e1000_set_phy_mode(hw);
1070 if (ret_val)
1071 return ret_val;
1072
1073 if ((hw->mac_type == e1000_82545_rev_3) ||
1074 (hw->mac_type == e1000_82546_rev_3)) {
1075 ret_val =
1076 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1077 phy_data |= 0x00000008;
1078 ret_val =
1079 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1080 }
1081
1082 if (hw->mac_type <= e1000_82543 ||
1083 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1084 hw->mac_type == e1000_82541_rev_2
1085 || hw->mac_type == e1000_82547_rev_2)
1086 hw->phy_reset_disable = false;
1087
1088 return E1000_SUCCESS;
1da177e4
LT		 1089}
1090
120a5d0d
JB		 1091/**
1092 * e1000_copper_link_igp_setup - Copper link setup for e1000_phy_igp series.
1093 * @hw: Struct containing variables accessed by shared code
1094 */
1095static s32 e1000_copper_link_igp_setup(struct e1000_hw *hw)
1096{
1097 u32 led_ctrl;
1098 s32 ret_val;
1099 u16 phy_data;
1100
675ad473 1101 e_dbg("e1000_copper_link_igp_setup");
120a5d0d
JB		 1102
1103 if (hw->phy_reset_disable)
1104 return E1000_SUCCESS;
1105
1106 ret_val = e1000_phy_reset(hw);
1107 if (ret_val) {
675ad473 1108 e_dbg("Error Resetting the PHY\n");
120a5d0d
JB		 1109 return ret_val;
1110 }
1111
1112 /* Wait 15ms for MAC to configure PHY from eeprom settings */
1113 msleep(15);
1114 /* Configure activity LED after PHY reset */
1115 led_ctrl = er32(LEDCTL);
1116 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1117 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1118 ew32(LEDCTL, led_ctrl);
1119
1120 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1121 if (hw->phy_type == e1000_phy_igp) {
1122 /* disable lplu d3 during driver init */
1123 ret_val = e1000_set_d3_lplu_state(hw, false);
1124 if (ret_val) {
675ad473 1125 e_dbg("Error Disabling LPLU D3\n");
120a5d0d
JB		 1126 return ret_val;
1127 }
1128 }
1129
1130 /* Configure mdi-mdix settings */
1131 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1132 if (ret_val)
1133 return ret_val;
1134
1135 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1136 hw->dsp_config_state = e1000_dsp_config_disabled;
1137 /* Force MDI for earlier revs of the IGP PHY */
1138 phy_data &=
1139 ~(IGP01E1000_PSCR_AUTO_MDIX |
1140 IGP01E1000_PSCR_FORCE_MDI_MDIX);
1141 hw->mdix = 1;
1142
1143 } else {
1144 hw->dsp_config_state = e1000_dsp_config_enabled;
1145 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1146
1147 switch (hw->mdix) {
1148 case 1:
1149 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1150 break;
1151 case 2:
1152 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1153 break;
1154 case 0:
1155 default:
1156 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1157 break;
1158 }
1159 }
1160 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1161 if (ret_val)
1162 return ret_val;
1163
1164 /* set auto-master slave resolution settings */
1165 if (hw->autoneg) {
1166 e1000_ms_type phy_ms_setting = hw->master_slave;
1167
1168 if (hw->ffe_config_state == e1000_ffe_config_active)
1169 hw->ffe_config_state = e1000_ffe_config_enabled;
1170
1171 if (hw->dsp_config_state == e1000_dsp_config_activated)
1172 hw->dsp_config_state = e1000_dsp_config_enabled;
1173
1174 /* when autonegotiation advertisement is only 1000Mbps then we
1175 * should disable SmartSpeed and enable Auto MasterSlave
1176 * resolution as hardware default. */
1177 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1178 /* Disable SmartSpeed */
1179 ret_val =
1180 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1181 &phy_data);
1182 if (ret_val)
1183 return ret_val;
1184 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1185 ret_val =
1186 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1187 phy_data);
1188 if (ret_val)
1189 return ret_val;
1190 /* Set auto Master/Slave resolution process */
1191 ret_val =
1192 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1193 if (ret_val)
1194 return ret_val;
1195 phy_data &= ~CR_1000T_MS_ENABLE;
1196 ret_val =
1197 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1198 if (ret_val)
1199 return ret_val;
1200 }
1201
1202 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1203 if (ret_val)
1204 return ret_val;
1205
1206 /* load defaults for future use */
1207 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1208 ((phy_data & CR_1000T_MS_VALUE) ?
1209 e1000_ms_force_master :
1210 e1000_ms_force_slave) : e1000_ms_auto;
1211
1212 switch (phy_ms_setting) {
1213 case e1000_ms_force_master:
1214 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1215 break;
1216 case e1000_ms_force_slave:
1217 phy_data |= CR_1000T_MS_ENABLE;
1218 phy_data &= ~(CR_1000T_MS_VALUE);
1219 break;
1220 case e1000_ms_auto:
1221 phy_data &= ~CR_1000T_MS_ENABLE;
1222 default:
1223 break;
1224 }
1225 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1226 if (ret_val)
1227 return ret_val;
1228 }
1229
1230 return E1000_SUCCESS;
1231}
1232
1233/**
1234 * e1000_copper_link_mgp_setup - Copper link setup for e1000_phy_m88 series.
1235 * @hw: Struct containing variables accessed by shared code
1236 */
1237static s32 e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1238{
1239 s32 ret_val;
1240 u16 phy_data;
1241
675ad473 1242 e_dbg("e1000_copper_link_mgp_setup");
120a5d0d
JB		 1243
1244 if (hw->phy_reset_disable)
1245 return E1000_SUCCESS;
1246
1247 /* Enable CRS on TX. This must be set for half-duplex operation. */
1248 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1249 if (ret_val)
1250 return ret_val;
1251
1252 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1253
1254 /* Options:
1255 * MDI/MDI-X = 0 (default)
1256 * 0 - Auto for all speeds
1257 * 1 - MDI mode
1258 * 2 - MDI-X mode
1259 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1260 */
1261 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1262
1263 switch (hw->mdix) {
1264 case 1:
1265 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1266 break;
1267 case 2:
1268 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1269 break;
1270 case 3:
1271 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1272 break;
1273 case 0:
1274 default:
1275 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1276 break;
1277 }
1278
1279 /* Options:
1280 * disable_polarity_correction = 0 (default)
1281 * Automatic Correction for Reversed Cable Polarity
1282 * 0 - Disabled
1283 * 1 - Enabled
1284 */
1285 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1286 if (hw->disable_polarity_correction == 1)
1287 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
1288 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1289 if (ret_val)
1290 return ret_val;
1291
1292 if (hw->phy_revision < M88E1011_I_REV_4) {
1293 /* Force TX_CLK in the Extended PHY Specific Control Register
1294 * to 25MHz clock.
1295 */
1296 ret_val =
1297 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1298 &phy_data);
1299 if (ret_val)
1300 return ret_val;
1301
1302 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1303
1304 if ((hw->phy_revision == E1000_REVISION_2) &&
1305 (hw->phy_id == M88E1111_I_PHY_ID)) {
1306 /* Vidalia Phy, set the downshift counter to 5x */
1307 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1308 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1309 ret_val = e1000_write_phy_reg(hw,
1310 M88E1000_EXT_PHY_SPEC_CTRL,
1311 phy_data);
1312 if (ret_val)
1313 return ret_val;
1314 } else {
1315 /* Configure Master and Slave downshift values */
1316 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1317 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1318 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1319 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1320 ret_val = e1000_write_phy_reg(hw,
1321 M88E1000_EXT_PHY_SPEC_CTRL,
1322 phy_data);
1323 if (ret_val)
1324 return ret_val;
1325 }
1326 }
1327
1328 /* SW Reset the PHY so all changes take effect */
1329 ret_val = e1000_phy_reset(hw);
1330 if (ret_val) {
675ad473 1331 e_dbg("Error Resetting the PHY\n");
120a5d0d
JB		 1332 return ret_val;
1333 }
1334
1335 return E1000_SUCCESS;
1336}
1337
1338/**
1339 * e1000_copper_link_autoneg - setup auto-neg
1340 * @hw: Struct containing variables accessed by shared code
1da177e4 1341 *
120a5d0d
JB		 1342 * Setup auto-negotiation and flow control advertisements,
1343 * and then perform auto-negotiation.
1344 */
1345static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1346{
1347 s32 ret_val;
1348 u16 phy_data;
1349
675ad473 1350 e_dbg("e1000_copper_link_autoneg");
120a5d0d
JB		 1351
1352 /* Perform some bounds checking on the hw->autoneg_advertised
1353 * parameter. If this variable is zero, then set it to the default.
1354 */
1355 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1356
1357 /* If autoneg_advertised is zero, we assume it was not defaulted
1358 * by the calling code so we set to advertise full capability.
1359 */
1360 if (hw->autoneg_advertised == 0)
1361 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1362
5377a416
DB		 1363 /* IFE/RTL8201N PHY only supports 10/100 */
1364 if (hw->phy_type == e1000_phy_8201)
1365 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1366
675ad473 1367 e_dbg("Reconfiguring auto-neg advertisement params\n");
120a5d0d
JB		 1368 ret_val = e1000_phy_setup_autoneg(hw);
1369 if (ret_val) {
675ad473 1370 e_dbg("Error Setting up Auto-Negotiation\n");
120a5d0d
JB		 1371 return ret_val;
1372 }
675ad473 1373 e_dbg("Restarting Auto-Neg\n");
120a5d0d
JB		 1374
1375 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1376 * the Auto Neg Restart bit in the PHY control register.
1377 */
1378 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1379 if (ret_val)
1380 return ret_val;
1381
1382 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1383 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1384 if (ret_val)
1385 return ret_val;
1386
1387 /* Does the user want to wait for Auto-Neg to complete here, or
1388 * check at a later time (for example, callback routine).
1389 */
1390 if (hw->wait_autoneg_complete) {
1391 ret_val = e1000_wait_autoneg(hw);
1392 if (ret_val) {
675ad473 1393 e_dbg
120a5d0d
JB		 1394 ("Error while waiting for autoneg to complete\n");
1395 return ret_val;
1396 }
1397 }
1398
1399 hw->get_link_status = true;
1400
1401 return E1000_SUCCESS;
1402}
1403
1404/**
1405 * e1000_copper_link_postconfig - post link setup
1406 * @hw: Struct containing variables accessed by shared code
1da177e4 1407 *
120a5d0d
JB		 1408 * Config the MAC and the PHY after link is up.
1409 * 1) Set up the MAC to the current PHY speed/duplex
1410 * if we are on 82543. If we
1411 * are on newer silicon, we only need to configure
1412 * collision distance in the Transmit Control Register.
1413 * 2) Set up flow control on the MAC to that established with
1414 * the link partner.
1415 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1416 */
1417static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
1418{
1419 s32 ret_val;
675ad473 1420 e_dbg("e1000_copper_link_postconfig");
120a5d0d 1421
5377a416 1422 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
120a5d0d
JB		 1423 e1000_config_collision_dist(hw);
1424 } else {
1425 ret_val = e1000_config_mac_to_phy(hw);
1426 if (ret_val) {
675ad473 1427 e_dbg("Error configuring MAC to PHY settings\n");
120a5d0d
JB		 1428 return ret_val;
1429 }
1430 }
1431 ret_val = e1000_config_fc_after_link_up(hw);
1432 if (ret_val) {
675ad473 1433 e_dbg("Error Configuring Flow Control\n");
120a5d0d
JB		 1434 return ret_val;
1435 }
1436
1437 /* Config DSP to improve Giga link quality */
1438 if (hw->phy_type == e1000_phy_igp) {
1439 ret_val = e1000_config_dsp_after_link_change(hw, true);
1440 if (ret_val) {
675ad473 1441 e_dbg("Error Configuring DSP after link up\n");
120a5d0d
JB		 1442 return ret_val;
1443 }
1444 }
1445
1446 return E1000_SUCCESS;
1447}
1448
1449/**
1450 * e1000_setup_copper_link - phy/speed/duplex setting
1451 * @hw: Struct containing variables accessed by shared code
1452 *
1453 * Detects which PHY is present and sets up the speed and duplex
1454 */
1455static s32 e1000_setup_copper_link(struct e1000_hw *hw)
1456{
1457 s32 ret_val;
1458 u16 i;
1459 u16 phy_data;
1460
675ad473 1461 e_dbg("e1000_setup_copper_link");
120a5d0d
JB		 1462
1463 /* Check if it is a valid PHY and set PHY mode if necessary. */
1464 ret_val = e1000_copper_link_preconfig(hw);
1465 if (ret_val)
1466 return ret_val;
1467
1468 if (hw->phy_type == e1000_phy_igp) {
1469 ret_val = e1000_copper_link_igp_setup(hw);
1470 if (ret_val)
1471 return ret_val;
1472 } else if (hw->phy_type == e1000_phy_m88) {
1473 ret_val = e1000_copper_link_mgp_setup(hw);
1474 if (ret_val)
1475 return ret_val;
5377a416
DB		 1476 } else {
1477 ret_val = gbe_dhg_phy_setup(hw);
1478 if (ret_val) {
1479 e_dbg("gbe_dhg_phy_setup failed!\n");
1480 return ret_val;
1481 }
120a5d0d
JB		 1482 }
1483
1484 if (hw->autoneg) {
1485 /* Setup autoneg and flow control advertisement
1486 * and perform autonegotiation */
1487 ret_val = e1000_copper_link_autoneg(hw);
1488 if (ret_val)
1489 return ret_val;
1490 } else {
1491 /* PHY will be set to 10H, 10F, 100H,or 100F
1492 * depending on value from forced_speed_duplex. */
675ad473 1493 e_dbg("Forcing speed and duplex\n");
120a5d0d
JB		 1494 ret_val = e1000_phy_force_speed_duplex(hw);
1495 if (ret_val) {
675ad473 1496 e_dbg("Error Forcing Speed and Duplex\n");
120a5d0d
JB		 1497 return ret_val;
1498 }
1499 }
1500
1501 /* Check link status. Wait up to 100 microseconds for link to become
1502 * valid.
1503 */
1504 for (i = 0; i < 10; i++) {
1505 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1506 if (ret_val)
1507 return ret_val;
1508 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
1509 if (ret_val)
1510 return ret_val;
1511
1512 if (phy_data & MII_SR_LINK_STATUS) {
1513 /* Config the MAC and PHY after link is up */
1514 ret_val = e1000_copper_link_postconfig(hw);
1515 if (ret_val)
1516 return ret_val;
1517
675ad473 1518 e_dbg("Valid link established!!!\n");
120a5d0d
JB		 1519 return E1000_SUCCESS;
1520 }
1521 udelay(10);
1522 }
1523
675ad473 1524 e_dbg("Unable to establish link!!!\n");
120a5d0d
JB		 1525 return E1000_SUCCESS;
1526}
1527
1528/**
1529 * e1000_phy_setup_autoneg - phy settings
1530 * @hw: Struct containing variables accessed by shared code
1531 *
1532 * Configures PHY autoneg and flow control advertisement settings
1533 */
1534s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1535{
1536 s32 ret_val;
1537 u16 mii_autoneg_adv_reg;
1538 u16 mii_1000t_ctrl_reg;
1539
675ad473 1540 e_dbg("e1000_phy_setup_autoneg");
120a5d0d
JB		 1541
1542 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1543 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1544 if (ret_val)
1545 return ret_val;
1546
1547 /* Read the MII 1000Base-T Control Register (Address 9). */
5377a416 1548 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
120a5d0d
JB		 1549 if (ret_val)
1550 return ret_val;
5377a416
DB		 1551 else if (hw->phy_type == e1000_phy_8201)
1552 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
120a5d0d
JB		 1553
1554 /* Need to parse both autoneg_advertised and fc and set up
1555 * the appropriate PHY registers. First we will parse for
1556 * autoneg_advertised software override. Since we can advertise
1557 * a plethora of combinations, we need to check each bit
1558 * individually.
1559 */
1560
1561 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1562 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1563 * the 1000Base-T Control Register (Address 9).
1564 */
1565 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1566 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1567
675ad473 1568 e_dbg("autoneg_advertised %x\n", hw->autoneg_advertised);
120a5d0d
JB		 1569
1570 /* Do we want to advertise 10 Mb Half Duplex? */
1571 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
675ad473 1572 e_dbg("Advertise 10mb Half duplex\n");
120a5d0d
JB		 1573 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1574 }
1575
1576 /* Do we want to advertise 10 Mb Full Duplex? */
1577 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
675ad473 1578 e_dbg("Advertise 10mb Full duplex\n");
120a5d0d
JB		 1579 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1580 }
1581
1582 /* Do we want to advertise 100 Mb Half Duplex? */
1583 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
675ad473 1584 e_dbg("Advertise 100mb Half duplex\n");
120a5d0d
JB		 1585 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1586 }
1587
1588 /* Do we want to advertise 100 Mb Full Duplex? */
1589 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
675ad473 1590 e_dbg("Advertise 100mb Full duplex\n");
120a5d0d
JB		 1591 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1592 }
1593
1594 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1595 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
675ad473 1596 e_dbg
120a5d0d
JB		 1597 ("Advertise 1000mb Half duplex requested, request denied!\n");
1598 }
1599
1600 /* Do we want to advertise 1000 Mb Full Duplex? */
1601 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
675ad473 1602 e_dbg("Advertise 1000mb Full duplex\n");
120a5d0d
JB		 1603 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1604 }
1605
1606 /* Check for a software override of the flow control settings, and
1607 * setup the PHY advertisement registers accordingly. If
1608 * auto-negotiation is enabled, then software will have to set the
1609 * "PAUSE" bits to the correct value in the Auto-Negotiation
1610 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1611 *
1612 * The possible values of the "fc" parameter are:
1613 * 0: Flow control is completely disabled
1614 * 1: Rx flow control is enabled (we can receive pause frames
1615 * but not send pause frames).
1616 * 2: Tx flow control is enabled (we can send pause frames
1617 * but we do not support receiving pause frames).
1618 * 3: Both Rx and TX flow control (symmetric) are enabled.
1619 * other: No software override. The flow control configuration
1620 * in the EEPROM is used.
1621 */
1622 switch (hw->fc) {
1623 case E1000_FC_NONE: /* 0 */
1624 /* Flow control (RX & TX) is completely disabled by a
1625 * software over-ride.
1626 */
1627 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1628 break;
1629 case E1000_FC_RX_PAUSE: /* 1 */
1630 /* RX Flow control is enabled, and TX Flow control is
1631 * disabled, by a software over-ride.
1632 */
1633 /* Since there really isn't a way to advertise that we are
1634 * capable of RX Pause ONLY, we will advertise that we
1635 * support both symmetric and asymmetric RX PAUSE. Later
1636 * (in e1000_config_fc_after_link_up) we will disable the
1637 *hw's ability to send PAUSE frames.
1638 */
1639 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1640 break;
1641 case E1000_FC_TX_PAUSE: /* 2 */
1642 /* TX Flow control is enabled, and RX Flow control is
1643 * disabled, by a software over-ride.
1644 */
1645 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1646 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1647 break;
1648 case E1000_FC_FULL: /* 3 */
1649 /* Flow control (both RX and TX) is enabled by a software
1650 * over-ride.
1651 */
1652 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1653 break;
1654 default:
675ad473 1655 e_dbg("Flow control param set incorrectly\n");
120a5d0d
JB		 1656 return -E1000_ERR_CONFIG;
1657 }
1658
1659 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1660 if (ret_val)
1661 return ret_val;
1662
675ad473 1663 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
120a5d0d 1664
5377a416
DB		 1665 if (hw->phy_type == e1000_phy_8201) {
1666 mii_1000t_ctrl_reg = 0;
1667 } else {
1668 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1669 mii_1000t_ctrl_reg);
1670 if (ret_val)
1671 return ret_val;
1672 }
120a5d0d
JB		 1673
1674 return E1000_SUCCESS;
1675}
1676
1677/**
1678 * e1000_phy_force_speed_duplex - force link settings
1679 * @hw: Struct containing variables accessed by shared code
1680 *
1681 * Force PHY speed and duplex settings to hw->forced_speed_duplex
1682 */
1683static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1684{
1685 u32 ctrl;
1686 s32 ret_val;
1687 u16 mii_ctrl_reg;
1688 u16 mii_status_reg;
1689 u16 phy_data;
1690 u16 i;
1691
675ad473 1692 e_dbg("e1000_phy_force_speed_duplex");
120a5d0d
JB		 1693
1694 /* Turn off Flow control if we are forcing speed and duplex. */
1695 hw->fc = E1000_FC_NONE;
1696
675ad473 1697 e_dbg("hw->fc = %d\n", hw->fc);
120a5d0d
JB		 1698
1699 /* Read the Device Control Register. */
1700 ctrl = er32(CTRL);
1701
1702 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
1703 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1704 ctrl &= ~(DEVICE_SPEED_MASK);
1705
1706 /* Clear the Auto Speed Detect Enable bit. */
1707 ctrl &= ~E1000_CTRL_ASDE;
1708
1709 /* Read the MII Control Register. */
1710 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
1711 if (ret_val)
1712 return ret_val;
1713
1714 /* We need to disable autoneg in order to force link and duplex. */
1715
1716 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
1717
1718 /* Are we forcing Full or Half Duplex? */
1719 if (hw->forced_speed_duplex == e1000_100_full ||
1720 hw->forced_speed_duplex == e1000_10_full) {
1721 /* We want to force full duplex so we SET the full duplex bits in the
1722 * Device and MII Control Registers.
1723 */
1724 ctrl |= E1000_CTRL_FD;
1725 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
675ad473 1726 e_dbg("Full Duplex\n");
120a5d0d
JB		 1727 } else {
1728 /* We want to force half duplex so we CLEAR the full duplex bits in
1729 * the Device and MII Control Registers.
1730 */
1731 ctrl &= ~E1000_CTRL_FD;
1732 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
675ad473 1733 e_dbg("Half Duplex\n");
120a5d0d
JB		 1734 }
1735
1736 /* Are we forcing 100Mbps??? */
1737 if (hw->forced_speed_duplex == e1000_100_full ||
1738 hw->forced_speed_duplex == e1000_100_half) {
1739 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
1740 ctrl |= E1000_CTRL_SPD_100;
1741 mii_ctrl_reg |= MII_CR_SPEED_100;
1742 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
675ad473 1743 e_dbg("Forcing 100mb ");
120a5d0d
JB		 1744 } else {
1745 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
1746 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1747 mii_ctrl_reg |= MII_CR_SPEED_10;
1748 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
675ad473 1749 e_dbg("Forcing 10mb ");
120a5d0d
JB		 1750 }
1751
1752 e1000_config_collision_dist(hw);
1753
1754 /* Write the configured values back to the Device Control Reg. */
1755 ew32(CTRL, ctrl);
1756
1757 if (hw->phy_type == e1000_phy_m88) {
1758 ret_val =
1759 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1760 if (ret_val)
1761 return ret_val;
1762
1763 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1764 * forced whenever speed are duplex are forced.
1765 */
1766 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1767 ret_val =
1768 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1769 if (ret_val)
1770 return ret_val;
1771
675ad473 1772 e_dbg("M88E1000 PSCR: %x\n", phy_data);
120a5d0d
JB		 1773
1774 /* Need to reset the PHY or these changes will be ignored */
1775 mii_ctrl_reg |= MII_CR_RESET;
1776
1777 /* Disable MDI-X support for 10/100 */
1778 } else {
1779 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1780 * forced whenever speed or duplex are forced.
1781 */
1782 ret_val =
1783 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1784 if (ret_val)
1785 return ret_val;
1786
1787 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1788 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1789
1790 ret_val =
1791 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1792 if (ret_val)
1793 return ret_val;
1794 }
1795
1796 /* Write back the modified PHY MII control register. */
1797 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
1798 if (ret_val)
1799 return ret_val;
1800
1801 udelay(1);
1802
1803 /* The wait_autoneg_complete flag may be a little misleading here.
1804 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
1805 * But we do want to delay for a period while forcing only so we
1806 * don't generate false No Link messages. So we will wait here
1807 * only if the user has set wait_autoneg_complete to 1, which is
1808 * the default.
1809 */
1810 if (hw->wait_autoneg_complete) {
1811 /* We will wait for autoneg to complete. */
675ad473 1812 e_dbg("Waiting for forced speed/duplex link.\n");
120a5d0d
JB		 1813 mii_status_reg = 0;
1814
1815 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
1816 for (i = PHY_FORCE_TIME; i > 0; i--) {
1817 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1818 * to be set.
1819 */
1820 ret_val =
1821 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1822 if (ret_val)
1823 return ret_val;
1824
1825 ret_val =
1826 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1827 if (ret_val)
1828 return ret_val;
1829
1830 if (mii_status_reg & MII_SR_LINK_STATUS)
1831 break;
1832 msleep(100);
1833 }
1834 if ((i == 0) && (hw->phy_type == e1000_phy_m88)) {
1835 /* We didn't get link. Reset the DSP and wait again for link. */
1836 ret_val = e1000_phy_reset_dsp(hw);
1837 if (ret_val) {
675ad473 1838 e_dbg("Error Resetting PHY DSP\n");
120a5d0d
JB		 1839 return ret_val;
1840 }
1841 }
1842 /* This loop will early-out if the link condition has been met. */
1843 for (i = PHY_FORCE_TIME; i > 0; i--) {
1844 if (mii_status_reg & MII_SR_LINK_STATUS)
1845 break;
1846 msleep(100);
1847 /* Read the MII Status Register and wait for Auto-Neg Complete bit
1848 * to be set.
1849 */
1850 ret_val =
1851 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1852 if (ret_val)
1853 return ret_val;
1854
1855 ret_val =
1856 e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1857 if (ret_val)
1858 return ret_val;
1859 }
1860 }
1861
1862 if (hw->phy_type == e1000_phy_m88) {
1863 /* Because we reset the PHY above, we need to re-force TX_CLK in the
1864 * Extended PHY Specific Control Register to 25MHz clock. This value
1865 * defaults back to a 2.5MHz clock when the PHY is reset.
1866 */
1867 ret_val =
1868 e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1869 &phy_data);
1870 if (ret_val)
1871 return ret_val;
1872
1873 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1874 ret_val =
1875 e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1876 phy_data);
1877 if (ret_val)
1878 return ret_val;
1879
1880 /* In addition, because of the s/w reset above, we need to enable CRS on
1881 * TX. This must be set for both full and half duplex operation.
1882 */
1883 ret_val =
1884 e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1885 if (ret_val)
1886 return ret_val;
1887
1888 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1889 ret_val =
1890 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1891 if (ret_val)
1892 return ret_val;
1893
1894 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543)
1895 && (!hw->autoneg)
1896 && (hw->forced_speed_duplex == e1000_10_full
1897 || hw->forced_speed_duplex == e1000_10_half)) {
1898 ret_val = e1000_polarity_reversal_workaround(hw);
1899 if (ret_val)
1900 return ret_val;
1901 }
1902 }
1903 return E1000_SUCCESS;
1904}
1905
1906/**
1907 * e1000_config_collision_dist - set collision distance register
1908 * @hw: Struct containing variables accessed by shared code
1909 *
1910 * Sets the collision distance in the Transmit Control register.
1911 * Link should have been established previously. Reads the speed and duplex
1912 * information from the Device Status register.
1913 */
1914void e1000_config_collision_dist(struct e1000_hw *hw)
1915{
1916 u32 tctl, coll_dist;
1917
675ad473 1918 e_dbg("e1000_config_collision_dist");
120a5d0d
JB		 1919
1920 if (hw->mac_type < e1000_82543)
1921 coll_dist = E1000_COLLISION_DISTANCE_82542;
1922 else
1923 coll_dist = E1000_COLLISION_DISTANCE;
1924
1925 tctl = er32(TCTL);
1926
1927 tctl &= ~E1000_TCTL_COLD;
1928 tctl |= coll_dist << E1000_COLD_SHIFT;
1929
1930 ew32(TCTL, tctl);
1931 E1000_WRITE_FLUSH();
1932}
1933
1934/**
1935 * e1000_config_mac_to_phy - sync phy and mac settings
1936 * @hw: Struct containing variables accessed by shared code
1937 * @mii_reg: data to write to the MII control register
1938 *
1939 * Sets MAC speed and duplex settings to reflect the those in the PHY
1940 * The contents of the PHY register containing the needed information need to
1941 * be passed in.
1942 */
1943static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
1944{
1945 u32 ctrl;
1946 s32 ret_val;
1947 u16 phy_data;
1948
675ad473 1949 e_dbg("e1000_config_mac_to_phy");
120a5d0d
JB		 1950
1951 /* 82544 or newer MAC, Auto Speed Detection takes care of
1952 * MAC speed/duplex configuration.*/
5377a416 1953 if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
120a5d0d
JB		 1954 return E1000_SUCCESS;
1955
1956 /* Read the Device Control Register and set the bits to Force Speed
1957 * and Duplex.
1958 */
1959 ctrl = er32(CTRL);
1960 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1961 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1962
5377a416
DB		 1963 switch (hw->phy_type) {
1964 case e1000_phy_8201:
1965 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1966 if (ret_val)
1967 return ret_val;
120a5d0d 1968
5377a416
DB		 1969 if (phy_data & RTL_PHY_CTRL_FD)
1970 ctrl |= E1000_CTRL_FD;
1971 else
1972 ctrl &= ~E1000_CTRL_FD;
120a5d0d 1973
5377a416
DB		 1974 if (phy_data & RTL_PHY_CTRL_SPD_100)
1975 ctrl |= E1000_CTRL_SPD_100;
1976 else
1977 ctrl |= E1000_CTRL_SPD_10;
120a5d0d 1978
5377a416
DB		 1979 e1000_config_collision_dist(hw);
1980 break;
1981 default:
1982 /* Set up duplex in the Device Control and Transmit Control
1983 * registers depending on negotiated values.
1984 */
1985 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1986 &phy_data);
1987 if (ret_val)
1988 return ret_val;
1989
1990 if (phy_data & M88E1000_PSSR_DPLX)
1991 ctrl |= E1000_CTRL_FD;
1992 else
1993 ctrl &= ~E1000_CTRL_FD;
1994
1995 e1000_config_collision_dist(hw);
1996
1997 /* Set up speed in the Device Control register depending on
1998 * negotiated values.
1999 */
2000 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2001 ctrl |= E1000_CTRL_SPD_1000;
2002 else if ((phy_data & M88E1000_PSSR_SPEED) ==
2003 M88E1000_PSSR_100MBS)
2004 ctrl |= E1000_CTRL_SPD_100;
2005 }
120a5d0d
JB		 2006
2007 /* Write the configured values back to the Device Control Reg. */
2008 ew32(CTRL, ctrl);
2009 return E1000_SUCCESS;
2010}
2011
2012/**
2013 * e1000_force_mac_fc - force flow control settings
2014 * @hw: Struct containing variables accessed by shared code
2015 *
2016 * Forces the MAC's flow control settings.
1da177e4
LT		 2017 * Sets the TFCE and RFCE bits in the device control register to reflect
2018 * the adapter settings. TFCE and RFCE need to be explicitly set by
2019 * software when a Copper PHY is used because autonegotiation is managed
2020 * by the PHY rather than the MAC. Software must also configure these
2021 * bits when link is forced on a fiber connection.
120a5d0d 2022 */
64798845 2023s32 e1000_force_mac_fc(struct e1000_hw *hw)
1da177e4 2024{
120a5d0d
JB		 2025 u32 ctrl;
2026
675ad473 2027 e_dbg("e1000_force_mac_fc");
120a5d0d
JB		 2028
2029 /* Get the current configuration of the Device Control Register */
2030 ctrl = er32(CTRL);
2031
2032 /* Because we didn't get link via the internal auto-negotiation
2033 * mechanism (we either forced link or we got link via PHY
2034 * auto-neg), we have to manually enable/disable transmit an
2035 * receive flow control.
2036 *
2037 * The "Case" statement below enables/disable flow control
2038 * according to the "hw->fc" parameter.
2039 *
2040 * The possible values of the "fc" parameter are:
2041 * 0: Flow control is completely disabled
2042 * 1: Rx flow control is enabled (we can receive pause
2043 * frames but not send pause frames).
2044 * 2: Tx flow control is enabled (we can send pause frames
2045 * frames but we do not receive pause frames).
2046 * 3: Both Rx and TX flow control (symmetric) is enabled.
2047 * other: No other values should be possible at this point.
2048 */
2049
2050 switch (hw->fc) {
2051 case E1000_FC_NONE:
2052 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2053 break;
2054 case E1000_FC_RX_PAUSE:
2055 ctrl &= (~E1000_CTRL_TFCE);
2056 ctrl |= E1000_CTRL_RFCE;
2057 break;
2058 case E1000_FC_TX_PAUSE:
2059 ctrl &= (~E1000_CTRL_RFCE);
2060 ctrl |= E1000_CTRL_TFCE;
2061 break;
2062 case E1000_FC_FULL:
2063 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2064 break;
2065 default:
675ad473 2066 e_dbg("Flow control param set incorrectly\n");
120a5d0d
JB		 2067 return -E1000_ERR_CONFIG;
2068 }
2069
2070 /* Disable TX Flow Control for 82542 (rev 2.0) */
2071 if (hw->mac_type == e1000_82542_rev2_0)
2072 ctrl &= (~E1000_CTRL_TFCE);
2073
2074 ew32(CTRL, ctrl);
2075 return E1000_SUCCESS;
1da177e4
LT		 2076}
2077
120a5d0d
JB		 2078/**
2079 * e1000_config_fc_after_link_up - configure flow control after autoneg
2080 * @hw: Struct containing variables accessed by shared code
1da177e4 2081 *
120a5d0d 2082 * Configures flow control settings after link is established
1da177e4
LT		 2083 * Should be called immediately after a valid link has been established.
2084 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2085 * and autonegotiation is enabled, the MAC flow control settings will be set
2086 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
120a5d0d
JB		 2087 * and RFCE bits will be automatically set to the negotiated flow control mode.
2088 */
64798845 2089static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1da177e4 2090{
120a5d0d
JB		 2091 s32 ret_val;
2092 u16 mii_status_reg;
2093 u16 mii_nway_adv_reg;
2094 u16 mii_nway_lp_ability_reg;
2095 u16 speed;
2096 u16 duplex;
2097
675ad473 2098 e_dbg("e1000_config_fc_after_link_up");
120a5d0d
JB		 2099
2100 /* Check for the case where we have fiber media and auto-neg failed
2101 * so we had to force link. In this case, we need to force the
2102 * configuration of the MAC to match the "fc" parameter.
2103 */
2104 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
2105 || ((hw->media_type == e1000_media_type_internal_serdes)
2106 && (hw->autoneg_failed))
2107 || ((hw->media_type == e1000_media_type_copper)
2108 && (!hw->autoneg))) {
2109 ret_val = e1000_force_mac_fc(hw);
2110 if (ret_val) {
675ad473 2111 e_dbg("Error forcing flow control settings\n");
120a5d0d
JB		 2112 return ret_val;
2113 }
2114 }
2115
2116 /* Check for the case where we have copper media and auto-neg is
2117 * enabled. In this case, we need to check and see if Auto-Neg
2118 * has completed, and if so, how the PHY and link partner has
2119 * flow control configured.
2120 */
2121 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2122 /* Read the MII Status Register and check to see if AutoNeg
2123 * has completed. We read this twice because this reg has
2124 * some "sticky" (latched) bits.
2125 */
2126 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2127 if (ret_val)
2128 return ret_val;
2129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2130 if (ret_val)
2131 return ret_val;
2132
2133 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2134 /* The AutoNeg process has completed, so we now need to
2135 * read both the Auto Negotiation Advertisement Register
2136 * (Address 4) and the Auto_Negotiation Base Page Ability
2137 * Register (Address 5) to determine how flow control was
2138 * negotiated.
2139 */
2140 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2141 &mii_nway_adv_reg);
2142 if (ret_val)
2143 return ret_val;
2144 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2145 &mii_nway_lp_ability_reg);
2146 if (ret_val)
2147 return ret_val;
2148
2149 /* Two bits in the Auto Negotiation Advertisement Register
2150 * (Address 4) and two bits in the Auto Negotiation Base
2151 * Page Ability Register (Address 5) determine flow control
2152 * for both the PHY and the link partner. The following
2153 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2154 * 1999, describes these PAUSE resolution bits and how flow
2155 * control is determined based upon these settings.
2156 * NOTE: DC = Don't Care
2157 *
2158 * LOCAL DEVICE | LINK PARTNER
2159 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2160 *-------|---------|-------|---------|--------------------
2161 * 0 | 0 | DC | DC | E1000_FC_NONE
2162 * 0 | 1 | 0 | DC | E1000_FC_NONE
2163 * 0 | 1 | 1 | 0 | E1000_FC_NONE
2164 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2165 * 1 | 0 | 0 | DC | E1000_FC_NONE
2166 * 1 | DC | 1 | DC | E1000_FC_FULL
2167 * 1 | 1 | 0 | 0 | E1000_FC_NONE
2168 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2169 *
2170 */
2171 /* Are both PAUSE bits set to 1? If so, this implies
2172 * Symmetric Flow Control is enabled at both ends. The
2173 * ASM_DIR bits are irrelevant per the spec.
2174 *
2175 * For Symmetric Flow Control:
2176 *
2177 * LOCAL DEVICE | LINK PARTNER
2178 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2179 *-------|---------|-------|---------|--------------------
2180 * 1 | DC | 1 | DC | E1000_FC_FULL
2181 *
2182 */
2183 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2184 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2185 /* Now we need to check if the user selected RX ONLY
2186 * of pause frames. In this case, we had to advertise
2187 * FULL flow control because we could not advertise RX
2188 * ONLY. Hence, we must now check to see if we need to
2189 * turn OFF the TRANSMISSION of PAUSE frames.
2190 */
2191 if (hw->original_fc == E1000_FC_FULL) {
2192 hw->fc = E1000_FC_FULL;
675ad473 2193 e_dbg("Flow Control = FULL.\n");
120a5d0d
JB		 2194 } else {
2195 hw->fc = E1000_FC_RX_PAUSE;
675ad473 2196 e_dbg
120a5d0d
JB		 2197 ("Flow Control = RX PAUSE frames only.\n");
2198 }
2199 }
2200 /* For receiving PAUSE frames ONLY.
2201 *
2202 * LOCAL DEVICE | LINK PARTNER
2203 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2204 *-------|---------|-------|---------|--------------------
2205 * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE
2206 *
2207 */
2208 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2209 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2210 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2211 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2212 {
2213 hw->fc = E1000_FC_TX_PAUSE;
675ad473 2214 e_dbg
120a5d0d
JB		 2215 ("Flow Control = TX PAUSE frames only.\n");
2216 }
2217 /* For transmitting PAUSE frames ONLY.
2218 *
2219 * LOCAL DEVICE | LINK PARTNER
2220 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2221 *-------|---------|-------|---------|--------------------
2222 * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE
2223 *
2224 */
2225 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2226 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2227 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2228 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
2229 {
2230 hw->fc = E1000_FC_RX_PAUSE;
675ad473 2231 e_dbg
120a5d0d
JB		 2232 ("Flow Control = RX PAUSE frames only.\n");
2233 }
2234 /* Per the IEEE spec, at this point flow control should be
2235 * disabled. However, we want to consider that we could
2236 * be connected to a legacy switch that doesn't advertise
2237 * desired flow control, but can be forced on the link
2238 * partner. So if we advertised no flow control, that is
2239 * what we will resolve to. If we advertised some kind of
2240 * receive capability (Rx Pause Only or Full Flow Control)
2241 * and the link partner advertised none, we will configure
2242 * ourselves to enable Rx Flow Control only. We can do
2243 * this safely for two reasons: If the link partner really
2244 * didn't want flow control enabled, and we enable Rx, no
2245 * harm done since we won't be receiving any PAUSE frames
2246 * anyway. If the intent on the link partner was to have
2247 * flow control enabled, then by us enabling RX only, we
2248 * can at least receive pause frames and process them.
2249 * This is a good idea because in most cases, since we are
2250 * predominantly a server NIC, more times than not we will
2251 * be asked to delay transmission of packets than asking
2252 * our link partner to pause transmission of frames.
2253 */
2254 else if ((hw->original_fc == E1000_FC_NONE ||
2255 hw->original_fc == E1000_FC_TX_PAUSE) ||
2256 hw->fc_strict_ieee) {
2257 hw->fc = E1000_FC_NONE;
675ad473 2258 e_dbg("Flow Control = NONE.\n");
120a5d0d
JB		 2259 } else {
2260 hw->fc = E1000_FC_RX_PAUSE;
675ad473 2261 e_dbg
120a5d0d
JB		 2262 ("Flow Control = RX PAUSE frames only.\n");
2263 }
2264
2265 /* Now we need to do one last check... If we auto-
2266 * negotiated to HALF DUPLEX, flow control should not be
2267 * enabled per IEEE 802.3 spec.
2268 */
2269 ret_val =
2270 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2271 if (ret_val) {
675ad473 2272 e_dbg
120a5d0d
JB		 2273 ("Error getting link speed and duplex\n");
2274 return ret_val;
2275 }
2276
2277 if (duplex == HALF_DUPLEX)
2278 hw->fc = E1000_FC_NONE;
2279
2280 /* Now we call a subroutine to actually force the MAC
2281 * controller to use the correct flow control settings.
2282 */
2283 ret_val = e1000_force_mac_fc(hw);
2284 if (ret_val) {
675ad473 2285 e_dbg
120a5d0d
JB		 2286 ("Error forcing flow control settings\n");
2287 return ret_val;
2288 }
2289 } else {
675ad473 2290 e_dbg
120a5d0d
JB		 2291 ("Copper PHY and Auto Neg has not completed.\n");
2292 }
2293 }
2294 return E1000_SUCCESS;
1da177e4
LT		 2295}
2296
be0f0719 2297/**
120a5d0d
JB		 2298 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
2299 * @hw: pointer to the HW structure
be0f0719 2300 *
120a5d0d
JB		 2301 * Checks for link up on the hardware. If link is not up and we have
2302 * a signal, then we need to force link up.
2303 */
11b7f7b3 2304static s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
be0f0719
JB		 2305{
2306 u32 rxcw;
2307 u32 ctrl;
2308 u32 status;
2309 s32 ret_val = E1000_SUCCESS;
2310
675ad473 2311 e_dbg("e1000_check_for_serdes_link_generic");
be0f0719
JB		 2312
2313 ctrl = er32(CTRL);
2314 status = er32(STATUS);
2315 rxcw = er32(RXCW);
2316
2317 /*
2318 * If we don't have link (auto-negotiation failed or link partner
2319 * cannot auto-negotiate), and our link partner is not trying to
2320 * auto-negotiate with us (we are receiving idles or data),
2321 * we need to force link up. We also need to give auto-negotiation
2322 * time to complete.
2323 */
2324 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
2325 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
2326 if (hw->autoneg_failed == 0) {
2327 hw->autoneg_failed = 1;
2328 goto out;
2329 }
675ad473 2330 e_dbg("NOT RXing /C/, disable AutoNeg and force link.\n");
be0f0719
JB		 2331
2332 /* Disable auto-negotiation in the TXCW register */
2333 ew32(TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2334
2335 /* Force link-up and also force full-duplex. */
2336 ctrl = er32(CTRL);
2337 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2338 ew32(CTRL, ctrl);
2339
2340 /* Configure Flow Control after forcing link up. */
2341 ret_val = e1000_config_fc_after_link_up(hw);
2342 if (ret_val) {
675ad473 2343 e_dbg("Error configuring flow control\n");
be0f0719
JB		 2344 goto out;
2345 }
2346 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
2347 /*
2348 * If we are forcing link and we are receiving /C/ ordered
2349 * sets, re-enable auto-negotiation in the TXCW register
2350 * and disable forced link in the Device Control register
2351 * in an attempt to auto-negotiate with our link partner.
2352 */
675ad473 2353 e_dbg("RXing /C/, enable AutoNeg and stop forcing link.\n");
be0f0719
JB		 2354 ew32(TXCW, hw->txcw);
2355 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
2356
2357 hw->serdes_has_link = true;
2358 } else if (!(E1000_TXCW_ANE & er32(TXCW))) {
2359 /*
2360 * If we force link for non-auto-negotiation switch, check
2361 * link status based on MAC synchronization for internal
2362 * serdes media type.
2363 */
2364 /* SYNCH bit and IV bit are sticky. */
2365 udelay(10);
2366 rxcw = er32(RXCW);
2367 if (rxcw & E1000_RXCW_SYNCH) {
2368 if (!(rxcw & E1000_RXCW_IV)) {
2369 hw->serdes_has_link = true;
675ad473 2370 e_dbg("SERDES: Link up - forced.\n");
be0f0719
JB		 2371 }
2372 } else {
2373 hw->serdes_has_link = false;
675ad473 2374 e_dbg("SERDES: Link down - force failed.\n");
be0f0719
JB		 2375 }
2376 }
2377
2378 if (E1000_TXCW_ANE & er32(TXCW)) {
2379 status = er32(STATUS);
2380 if (status & E1000_STATUS_LU) {
2381 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
2382 udelay(10);
2383 rxcw = er32(RXCW);
2384 if (rxcw & E1000_RXCW_SYNCH) {
2385 if (!(rxcw & E1000_RXCW_IV)) {
2386 hw->serdes_has_link = true;
675ad473 2387 e_dbg("SERDES: Link up - autoneg "
120a5d0d 2388 "completed successfully.\n");
be0f0719
JB		 2389 } else {
2390 hw->serdes_has_link = false;
675ad473 2391 e_dbg("SERDES: Link down - invalid"
120a5d0d
JB		 2392 "codewords detected in autoneg.\n");
2393 }
2394 } else {
2395 hw->serdes_has_link = false;
675ad473 2396 e_dbg("SERDES: Link down - no sync.\n");
120a5d0d
JB		 2397 }
2398 } else {
2399 hw->serdes_has_link = false;
675ad473 2400 e_dbg("SERDES: Link down - autoneg failed\n");
120a5d0d
JB		 2401 }
2402 }
2403
2404 out:
2405 return ret_val;
2406}
2407
2408/**
2409 * e1000_check_for_link
2410 * @hw: Struct containing variables accessed by shared code
2411 *
2412 * Checks to see if the link status of the hardware has changed.
2413 * Called by any function that needs to check the link status of the adapter.
2414 */
2415s32 e1000_check_for_link(struct e1000_hw *hw)
2416{
2417 u32 rxcw = 0;
2418 u32 ctrl;
2419 u32 status;
2420 u32 rctl;
2421 u32 icr;
2422 u32 signal = 0;
2423 s32 ret_val;
2424 u16 phy_data;
2425
675ad473 2426 e_dbg("e1000_check_for_link");
120a5d0d
JB		 2427
2428 ctrl = er32(CTRL);
2429 status = er32(STATUS);
2430
2431 /* On adapters with a MAC newer than 82544, SW Definable pin 1 will be
2432 * set when the optics detect a signal. On older adapters, it will be
2433 * cleared when there is a signal. This applies to fiber media only.
2434 */
2435 if ((hw->media_type == e1000_media_type_fiber) ||
2436 (hw->media_type == e1000_media_type_internal_serdes)) {
2437 rxcw = er32(RXCW);
2438
2439 if (hw->media_type == e1000_media_type_fiber) {
2440 signal =
2441 (hw->mac_type >
2442 e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2443 if (status & E1000_STATUS_LU)
2444 hw->get_link_status = false;
2445 }
2446 }
2447
2448 /* If we have a copper PHY then we only want to go out to the PHY
2449 * registers to see if Auto-Neg has completed and/or if our link
2450 * status has changed. The get_link_status flag will be set if we
2451 * receive a Link Status Change interrupt or we have Rx Sequence
2452 * Errors.
2453 */
2454 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2455 /* First we want to see if the MII Status Register reports
2456 * link. If so, then we want to get the current speed/duplex
2457 * of the PHY.
2458 * Read the register twice since the link bit is sticky.
2459 */
2460 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2461 if (ret_val)
2462 return ret_val;
2463 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2464 if (ret_val)
2465 return ret_val;
2466
2467 if (phy_data & MII_SR_LINK_STATUS) {
2468 hw->get_link_status = false;
2469 /* Check if there was DownShift, must be checked immediately after
2470 * link-up */
2471 e1000_check_downshift(hw);
2472
2473 /* If we are on 82544 or 82543 silicon and speed/duplex
2474 * are forced to 10H or 10F, then we will implement the polarity
2475 * reversal workaround. We disable interrupts first, and upon
2476 * returning, place the devices interrupt state to its previous
2477 * value except for the link status change interrupt which will
2478 * happen due to the execution of this workaround.
2479 */
2480
2481 if ((hw->mac_type == e1000_82544
2482 || hw->mac_type == e1000_82543) && (!hw->autoneg)
2483 && (hw->forced_speed_duplex == e1000_10_full
2484 || hw->forced_speed_duplex == e1000_10_half)) {
2485 ew32(IMC, 0xffffffff);
2486 ret_val =
2487 e1000_polarity_reversal_workaround(hw);
2488 icr = er32(ICR);
2489 ew32(ICS, (icr & ~E1000_ICS_LSC));
2490 ew32(IMS, IMS_ENABLE_MASK);
2491 }
2492
2493 } else {
2494 /* No link detected */
2495 e1000_config_dsp_after_link_change(hw, false);
2496 return 0;
2497 }
2498
2499 /* If we are forcing speed/duplex, then we simply return since
2500 * we have already determined whether we have link or not.
2501 */
2502 if (!hw->autoneg)
2503 return -E1000_ERR_CONFIG;
2504
2505 /* optimize the dsp settings for the igp phy */
2506 e1000_config_dsp_after_link_change(hw, true);
2507
2508 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2509 * have Si on board that is 82544 or newer, Auto
2510 * Speed Detection takes care of MAC speed/duplex
2511 * configuration. So we only need to configure Collision
2512 * Distance in the MAC. Otherwise, we need to force
2513 * speed/duplex on the MAC to the current PHY speed/duplex
2514 * settings.
2515 */
5377a416
DB		 2516 if ((hw->mac_type >= e1000_82544) &&
2517 (hw->mac_type != e1000_ce4100))
120a5d0d
JB		 2518 e1000_config_collision_dist(hw);
2519 else {
2520 ret_val = e1000_config_mac_to_phy(hw);
2521 if (ret_val) {
675ad473 2522 e_dbg
120a5d0d
JB		 2523 ("Error configuring MAC to PHY settings\n");
2524 return ret_val;
2525 }
2526 }
2527
2528 /* Configure Flow Control now that Auto-Neg has completed. First, we
2529 * need to restore the desired flow control settings because we may
2530 * have had to re-autoneg with a different link partner.
2531 */
2532 ret_val = e1000_config_fc_after_link_up(hw);
2533 if (ret_val) {
675ad473 2534 e_dbg("Error configuring flow control\n");
120a5d0d
JB		 2535 return ret_val;
2536 }
2537
2538 /* At this point we know that we are on copper and we have
2539 * auto-negotiated link. These are conditions for checking the link
2540 * partner capability register. We use the link speed to determine if
2541 * TBI compatibility needs to be turned on or off. If the link is not
2542 * at gigabit speed, then TBI compatibility is not needed. If we are
2543 * at gigabit speed, we turn on TBI compatibility.
2544 */
2545 if (hw->tbi_compatibility_en) {
2546 u16 speed, duplex;
2547 ret_val =
2548 e1000_get_speed_and_duplex(hw, &speed, &duplex);
2549 if (ret_val) {
675ad473 2550 e_dbg
120a5d0d
JB		 2551 ("Error getting link speed and duplex\n");
2552 return ret_val;
2553 }
2554 if (speed != SPEED_1000) {
2555 /* If link speed is not set to gigabit speed, we do not need
2556 * to enable TBI compatibility.
2557 */
2558 if (hw->tbi_compatibility_on) {
2559 /* If we previously were in the mode, turn it off. */
2560 rctl = er32(RCTL);
2561 rctl &= ~E1000_RCTL_SBP;
2562 ew32(RCTL, rctl);
2563 hw->tbi_compatibility_on = false;
be0f0719
JB		 2564 }
2565 } else {
120a5d0d
JB		 2566 /* If TBI compatibility is was previously off, turn it on. For
2567 * compatibility with a TBI link partner, we will store bad
2568 * packets. Some frames have an additional byte on the end and
2569 * will look like CRC errors to to the hardware.
2570 */
2571 if (!hw->tbi_compatibility_on) {
2572 hw->tbi_compatibility_on = true;
2573 rctl = er32(RCTL);
2574 rctl |= E1000_RCTL_SBP;
2575 ew32(RCTL, rctl);
2576 }
be0f0719 2577 }
be0f0719
JB		 2578 }
2579 }
2580
120a5d0d
JB		 2581 if ((hw->media_type == e1000_media_type_fiber) ||
2582 (hw->media_type == e1000_media_type_internal_serdes))
2583 e1000_check_for_serdes_link_generic(hw);
2584
2585 return E1000_SUCCESS;
1da177e4
LT		 2586}
2587
120a5d0d
JB		 2588/**
2589 * e1000_get_speed_and_duplex
2590 * @hw: Struct containing variables accessed by shared code
2591 * @speed: Speed of the connection
2592 * @duplex: Duplex setting of the connection
2593
1da177e4 2594 * Detects the current speed and duplex settings of the hardware.
120a5d0d 2595 */
64798845 2596s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed, u16 *duplex)
1da177e4 2597{
120a5d0d
JB		 2598 u32 status;
2599 s32 ret_val;
2600 u16 phy_data;
2601
675ad473 2602 e_dbg("e1000_get_speed_and_duplex");
120a5d0d
JB		 2603
2604 if (hw->mac_type >= e1000_82543) {
2605 status = er32(STATUS);
2606 if (status & E1000_STATUS_SPEED_1000) {
2607 *speed = SPEED_1000;
675ad473 2608 e_dbg("1000 Mbs, ");
120a5d0d
JB		 2609 } else if (status & E1000_STATUS_SPEED_100) {
2610 *speed = SPEED_100;
675ad473 2611 e_dbg("100 Mbs, ");
120a5d0d
JB		 2612 } else {
2613 *speed = SPEED_10;
675ad473 2614 e_dbg("10 Mbs, ");
120a5d0d
JB		 2615 }
2616
2617 if (status & E1000_STATUS_FD) {
2618 *duplex = FULL_DUPLEX;
675ad473 2619 e_dbg("Full Duplex\n");
120a5d0d
JB		 2620 } else {
2621 *duplex = HALF_DUPLEX;
675ad473 2622 e_dbg(" Half Duplex\n");
120a5d0d
JB		 2623 }
2624 } else {
675ad473 2625 e_dbg("1000 Mbs, Full Duplex\n");
120a5d0d
JB		 2626 *speed = SPEED_1000;
2627 *duplex = FULL_DUPLEX;
2628 }
2629
2630 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
2631 * if it is operating at half duplex. Here we set the duplex settings to
2632 * match the duplex in the link partner's capabilities.
2633 */
2634 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
2635 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
2636 if (ret_val)
2637 return ret_val;
2638
2639 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
2640 *duplex = HALF_DUPLEX;
2641 else {
2642 ret_val =
2643 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
2644 if (ret_val)
2645 return ret_val;
2646 if ((*speed == SPEED_100
2647 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
2648 || (*speed == SPEED_10
2649 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
2650 *duplex = HALF_DUPLEX;
2651 }
2652 }
2653
2654 return E1000_SUCCESS;
1da177e4
LT		 2655}
2656
120a5d0d
JB		 2657/**
2658 * e1000_wait_autoneg
2659 * @hw: Struct containing variables accessed by shared code
2660 *
2661 * Blocks until autoneg completes or times out (~4.5 seconds)
2662 */
64798845 2663static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1da177e4 2664{
120a5d0d
JB		 2665 s32 ret_val;
2666 u16 i;
2667 u16 phy_data;
2668
675ad473
ET		 2669 e_dbg("e1000_wait_autoneg");
2670 e_dbg("Waiting for Auto-Neg to complete.\n");
120a5d0d
JB		 2671
2672 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2673 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2674 /* Read the MII Status Register and wait for Auto-Neg
2675 * Complete bit to be set.
2676 */
2677 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2678 if (ret_val)
2679 return ret_val;
2680 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2681 if (ret_val)
2682 return ret_val;
2683 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
2684 return E1000_SUCCESS;
2685 }
2686 msleep(100);
2687 }
2688 return E1000_SUCCESS;
1da177e4
LT		 2689}
2690
120a5d0d
JB		 2691/**
2692 * e1000_raise_mdi_clk - Raises the Management Data Clock
2693 * @hw: Struct containing variables accessed by shared code
2694 * @ctrl: Device control register's current value
2695 */
64798845 2696static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
1da177e4 2697{
120a5d0d
JB		 2698 /* Raise the clock input to the Management Data Clock (by setting the MDC
2699 * bit), and then delay 10 microseconds.
2700 */
2701 ew32(CTRL, (*ctrl | E1000_CTRL_MDC));
2702 E1000_WRITE_FLUSH();
2703 udelay(10);
1da177e4
LT		 2704}
2705
120a5d0d
JB		 2706/**
2707 * e1000_lower_mdi_clk - Lowers the Management Data Clock
2708 * @hw: Struct containing variables accessed by shared code
2709 * @ctrl: Device control register's current value
2710 */
64798845 2711static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl)
1da177e4 2712{
120a5d0d
JB		 2713 /* Lower the clock input to the Management Data Clock (by clearing the MDC
2714 * bit), and then delay 10 microseconds.
2715 */
2716 ew32(CTRL, (*ctrl & ~E1000_CTRL_MDC));
2717 E1000_WRITE_FLUSH();
2718 udelay(10);
1da177e4
LT		 2719}
2720
120a5d0d
JB		 2721/**
2722 * e1000_shift_out_mdi_bits - Shifts data bits out to the PHY
2723 * @hw: Struct containing variables accessed by shared code
2724 * @data: Data to send out to the PHY
2725 * @count: Number of bits to shift out
2726 *
2727 * Bits are shifted out in MSB to LSB order.
2728 */
64798845 2729static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, u32 data, u16 count)
1da177e4 2730{
120a5d0d
JB		 2731 u32 ctrl;
2732 u32 mask;
2733
2734 /* We need to shift "count" number of bits out to the PHY. So, the value
2735 * in the "data" parameter will be shifted out to the PHY one bit at a
2736 * time. In order to do this, "data" must be broken down into bits.
2737 */
2738 mask = 0x01;
2739 mask <<= (count - 1);
2740
2741 ctrl = er32(CTRL);
2742
2743 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2744 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2745
2746 while (mask) {
2747 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2748 * then raising and lowering the Management Data Clock. A "0" is
2749 * shifted out to the PHY by setting the MDIO bit to "0" and then
2750 * raising and lowering the clock.
2751 */
2752 if (data & mask)
2753 ctrl |= E1000_CTRL_MDIO;
2754 else
2755 ctrl &= ~E1000_CTRL_MDIO;
2756
2757 ew32(CTRL, ctrl);
2758 E1000_WRITE_FLUSH();
2759
2760 udelay(10);
2761
2762 e1000_raise_mdi_clk(hw, &ctrl);
2763 e1000_lower_mdi_clk(hw, &ctrl);
2764
2765 mask = mask >> 1;
2766 }
1da177e4
LT		 2767}
2768
120a5d0d
JB		 2769/**
2770 * e1000_shift_in_mdi_bits - Shifts data bits in from the PHY
2771 * @hw: Struct containing variables accessed by shared code
2772 *
2773 * Bits are shifted in in MSB to LSB order.
2774 */
64798845 2775static u16 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
1da177e4 2776{
120a5d0d
JB		 2777 u32 ctrl;
2778 u16 data = 0;
2779 u8 i;
2780
2781 /* In order to read a register from the PHY, we need to shift in a total
2782 * of 18 bits from the PHY. The first two bit (turnaround) times are used
2783 * to avoid contention on the MDIO pin when a read operation is performed.
2784 * These two bits are ignored by us and thrown away. Bits are "shifted in"
2785 * by raising the input to the Management Data Clock (setting the MDC bit),
2786 * and then reading the value of the MDIO bit.
2787 */
2788 ctrl = er32(CTRL);
2789
2790 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2791 ctrl &= ~E1000_CTRL_MDIO_DIR;
2792 ctrl &= ~E1000_CTRL_MDIO;
2793
2794 ew32(CTRL, ctrl);
2795 E1000_WRITE_FLUSH();
2796
2797 /* Raise and Lower the clock before reading in the data. This accounts for
2798 * the turnaround bits. The first clock occurred when we clocked out the
2799 * last bit of the Register Address.
2800 */
2801 e1000_raise_mdi_clk(hw, &ctrl);
2802 e1000_lower_mdi_clk(hw, &ctrl);
2803
2804 for (data = 0, i = 0; i < 16; i++) {
2805 data = data << 1;
2806 e1000_raise_mdi_clk(hw, &ctrl);
2807 ctrl = er32(CTRL);
2808 /* Check to see if we shifted in a "1". */
2809 if (ctrl & E1000_CTRL_MDIO)
2810 data |= 1;
2811 e1000_lower_mdi_clk(hw, &ctrl);
2812 }
2813
2814 e1000_raise_mdi_clk(hw, &ctrl);
2815 e1000_lower_mdi_clk(hw, &ctrl);
2816
2817 return data;
1da177e4
LT		 2818}
2819
120a5d0d
JB		 2820
2821/**
2822 * e1000_read_phy_reg - read a phy register
2823 * @hw: Struct containing variables accessed by shared code
2824 * @reg_addr: address of the PHY register to read
2825 *
2826 * Reads the value from a PHY register, if the value is on a specific non zero
2827 * page, sets the page first.
2828 */
64798845 2829s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 *phy_data)
1da177e4 2830{
120a5d0d 2831 u32 ret_val;
1da177e4 2832
675ad473 2833 e_dbg("e1000_read_phy_reg");
1da177e4 2834
120a5d0d
JB		 2835 if ((hw->phy_type == e1000_phy_igp) &&
2836 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2837 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2838 (u16) reg_addr);
2839 if (ret_val)
2840 return ret_val;
2841 }
2842
2843 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2844 phy_data);
1da177e4 2845
120a5d0d 2846 return ret_val;
1da177e4
LT		 2847}
2848
64798845
JP		 2849static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2850 u16 *phy_data)
1da177e4 2851{
120a5d0d
JB		 2852 u32 i;
2853 u32 mdic = 0;
5377a416 2854 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
120a5d0d 2855
675ad473 2856 e_dbg("e1000_read_phy_reg_ex");
120a5d0d
JB		 2857
2858 if (reg_addr > MAX_PHY_REG_ADDRESS) {
675ad473 2859 e_dbg("PHY Address %d is out of range\n", reg_addr);
120a5d0d
JB		 2860 return -E1000_ERR_PARAM;
2861 }
2862
2863 if (hw->mac_type > e1000_82543) {
2864 /* Set up Op-code, Phy Address, and register address in the MDI
2865 * Control register. The MAC will take care of interfacing with the
2866 * PHY to retrieve the desired data.
2867 */
5377a416
DB		 2868 if (hw->mac_type == e1000_ce4100) {
2869 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2870 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2871 (INTEL_CE_GBE_MDIC_OP_READ) |
2872 (INTEL_CE_GBE_MDIC_GO));
120a5d0d 2873
5377a416 2874 writel(mdic, E1000_MDIO_CMD);
120a5d0d 2875
5377a416
DB		 2876 /* Poll the ready bit to see if the MDI read
2877 * completed
2878 */
2879 for (i = 0; i < 64; i++) {
2880 udelay(50);
2881 mdic = readl(E1000_MDIO_CMD);
2882 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
2883 break;
2884 }
2885
2886 if (mdic & INTEL_CE_GBE_MDIC_GO) {
2887 e_dbg("MDI Read did not complete\n");
2888 return -E1000_ERR_PHY;
2889 }
2890
2891 mdic = readl(E1000_MDIO_STS);
2892 if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
2893 e_dbg("MDI Read Error\n");
2894 return -E1000_ERR_PHY;
2895 }
2896 *phy_data = (u16) mdic;
2897 } else {
2898 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2899 (phy_addr << E1000_MDIC_PHY_SHIFT) |
2900 (E1000_MDIC_OP_READ));
2901
2902 ew32(MDIC, mdic);
2903
2904 /* Poll the ready bit to see if the MDI read
2905 * completed
2906 */
2907 for (i = 0; i < 64; i++) {
2908 udelay(50);
2909 mdic = er32(MDIC);
2910 if (mdic & E1000_MDIC_READY)
2911 break;
2912 }
2913 if (!(mdic & E1000_MDIC_READY)) {
2914 e_dbg("MDI Read did not complete\n");
2915 return -E1000_ERR_PHY;
2916 }
2917 if (mdic & E1000_MDIC_ERROR) {
2918 e_dbg("MDI Error\n");
2919 return -E1000_ERR_PHY;
2920 }
2921 *phy_data = (u16) mdic;
120a5d0d 2922 }
120a5d0d
JB		 2923 } else {
2924 /* We must first send a preamble through the MDIO pin to signal the
2925 * beginning of an MII instruction. This is done by sending 32
2926 * consecutive "1" bits.
2927 */
2928 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2929
2930 /* Now combine the next few fields that are required for a read
2931 * operation. We use this method instead of calling the
2932 * e1000_shift_out_mdi_bits routine five different times. The format of
2933 * a MII read instruction consists of a shift out of 14 bits and is
2934 * defined as follows:
2935 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2936 * followed by a shift in of 18 bits. This first two bits shifted in
2937 * are TurnAround bits used to avoid contention on the MDIO pin when a
2938 * READ operation is performed. These two bits are thrown away
2939 * followed by a shift in of 16 bits which contains the desired data.
2940 */
2941 mdic = ((reg_addr) | (phy_addr << 5) |
2942 (PHY_OP_READ << 10) | (PHY_SOF << 12));
2943
2944 e1000_shift_out_mdi_bits(hw, mdic, 14);
2945
2946 /* Now that we've shifted out the read command to the MII, we need to
2947 * "shift in" the 16-bit value (18 total bits) of the requested PHY
2948 * register address.
2949 */
2950 *phy_data = e1000_shift_in_mdi_bits(hw);
2951 }
2952 return E1000_SUCCESS;
1da177e4
LT		 2953}
2954
120a5d0d
JB		 2955/**
2956 * e1000_write_phy_reg - write a phy register
2957 *
2958 * @hw: Struct containing variables accessed by shared code
2959 * @reg_addr: address of the PHY register to write
2960 * @data: data to write to the PHY
2961
2962 * Writes a value to a PHY register
2963 */
64798845 2964s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 phy_data)
1da177e4 2965{
120a5d0d 2966 u32 ret_val;
1da177e4 2967
675ad473 2968 e_dbg("e1000_write_phy_reg");
1da177e4 2969
120a5d0d
JB		 2970 if ((hw->phy_type == e1000_phy_igp) &&
2971 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2972 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2973 (u16) reg_addr);
2974 if (ret_val)
2975 return ret_val;
2976 }
1da177e4 2977
120a5d0d
JB		 2978 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
2979 phy_data);
1da177e4 2980
120a5d0d 2981 return ret_val;
1da177e4
LT		 2982}
2983
64798845
JP		 2984static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
2985 u16 phy_data)
1da177e4 2986{
120a5d0d
JB		 2987 u32 i;
2988 u32 mdic = 0;
5377a416 2989 const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
120a5d0d 2990
675ad473 2991 e_dbg("e1000_write_phy_reg_ex");
120a5d0d
JB		 2992
2993 if (reg_addr > MAX_PHY_REG_ADDRESS) {
675ad473 2994 e_dbg("PHY Address %d is out of range\n", reg_addr);
120a5d0d
JB		 2995 return -E1000_ERR_PARAM;
2996 }
2997
2998 if (hw->mac_type > e1000_82543) {
5377a416
DB		 2999 /* Set up Op-code, Phy Address, register address, and data
3000 * intended for the PHY register in the MDI Control register.
3001 * The MAC will take care of interfacing with the PHY to send
3002 * the desired data.
120a5d0d 3003 */
5377a416
DB		 3004 if (hw->mac_type == e1000_ce4100) {
3005 mdic = (((u32) phy_data) |
3006 (reg_addr << E1000_MDIC_REG_SHIFT) |
3007 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3008 (INTEL_CE_GBE_MDIC_OP_WRITE) |
3009 (INTEL_CE_GBE_MDIC_GO));
120a5d0d 3010
5377a416 3011 writel(mdic, E1000_MDIO_CMD);
120a5d0d 3012
5377a416
DB		 3013 /* Poll the ready bit to see if the MDI read
3014 * completed
3015 */
3016 for (i = 0; i < 640; i++) {
3017 udelay(5);
3018 mdic = readl(E1000_MDIO_CMD);
3019 if (!(mdic & INTEL_CE_GBE_MDIC_GO))
3020 break;
3021 }
3022 if (mdic & INTEL_CE_GBE_MDIC_GO) {
3023 e_dbg("MDI Write did not complete\n");
3024 return -E1000_ERR_PHY;
3025 }
3026 } else {
3027 mdic = (((u32) phy_data) |
3028 (reg_addr << E1000_MDIC_REG_SHIFT) |
3029 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3030 (E1000_MDIC_OP_WRITE));
3031
3032 ew32(MDIC, mdic);
3033
3034 /* Poll the ready bit to see if the MDI read
3035 * completed
3036 */
3037 for (i = 0; i < 641; i++) {
3038 udelay(5);
3039 mdic = er32(MDIC);
3040 if (mdic & E1000_MDIC_READY)
3041 break;
3042 }
3043 if (!(mdic & E1000_MDIC_READY)) {
3044 e_dbg("MDI Write did not complete\n");
3045 return -E1000_ERR_PHY;
3046 }
120a5d0d
JB		 3047 }
3048 } else {
3049 /* We'll need to use the SW defined pins to shift the write command
3050 * out to the PHY. We first send a preamble to the PHY to signal the
3051 * beginning of the MII instruction. This is done by sending 32
3052 * consecutive "1" bits.
3053 */
3054 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3055
3056 /* Now combine the remaining required fields that will indicate a
3057 * write operation. We use this method instead of calling the
3058 * e1000_shift_out_mdi_bits routine for each field in the command. The
3059 * format of a MII write instruction is as follows:
3060 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3061 */
3062 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3063 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3064 mdic <<= 16;
3065 mdic |= (u32) phy_data;
3066
3067 e1000_shift_out_mdi_bits(hw, mdic, 32);
3068 }
3069
3070 return E1000_SUCCESS;
1da177e4
LT		 3071}
3072
120a5d0d
JB		 3073/**
3074 * e1000_phy_hw_reset - reset the phy, hardware style
3075 * @hw: Struct containing variables accessed by shared code
3076 *
3077 * Returns the PHY to the power-on reset state
3078 */
64798845 3079s32 e1000_phy_hw_reset(struct e1000_hw *hw)
1da177e4 3080{
120a5d0d
JB		 3081 u32 ctrl, ctrl_ext;
3082 u32 led_ctrl;
3083 s32 ret_val;
3084
675ad473 3085 e_dbg("e1000_phy_hw_reset");
120a5d0d 3086
675ad473 3087 e_dbg("Resetting Phy...\n");
120a5d0d
JB		 3088
3089 if (hw->mac_type > e1000_82543) {
3090 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3091 * bit. Then, take it out of reset.
3092 * For e1000 hardware, we delay for 10ms between the assert
3093 * and deassert.
3094 */
3095 ctrl = er32(CTRL);
3096 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
3097 E1000_WRITE_FLUSH();
3098
3099 msleep(10);
3100
3101 ew32(CTRL, ctrl);
3102 E1000_WRITE_FLUSH();
3103
3104 } else {
3105 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3106 * bit to put the PHY into reset. Then, take it out of reset.
3107 */
3108 ctrl_ext = er32(CTRL_EXT);
3109 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3110 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3111 ew32(CTRL_EXT, ctrl_ext);
3112 E1000_WRITE_FLUSH();
3113 msleep(10);
3114 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3115 ew32(CTRL_EXT, ctrl_ext);
3116 E1000_WRITE_FLUSH();
3117 }
3118 udelay(150);
3119
3120 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
3121 /* Configure activity LED after PHY reset */
3122 led_ctrl = er32(LEDCTL);
3123 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3124 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3125 ew32(LEDCTL, led_ctrl);
3126 }
3127
3128 /* Wait for FW to finish PHY configuration. */
3129 ret_val = e1000_get_phy_cfg_done(hw);
3130 if (ret_val != E1000_SUCCESS)
3131 return ret_val;
3132
3133 return ret_val;
1da177e4
LT		 3134}
3135
120a5d0d
JB		 3136/**
3137 * e1000_phy_reset - reset the phy to commit settings
3138 * @hw: Struct containing variables accessed by shared code
3139 *
3140 * Resets the PHY
3141 * Sets bit 15 of the MII Control register
3142 */
64798845 3143s32 e1000_phy_reset(struct e1000_hw *hw)
1da177e4 3144{
120a5d0d
JB		 3145 s32 ret_val;
3146 u16 phy_data;
3147
675ad473 3148 e_dbg("e1000_phy_reset");
120a5d0d
JB		 3149
3150 switch (hw->phy_type) {
3151 case e1000_phy_igp:
3152 ret_val = e1000_phy_hw_reset(hw);
3153 if (ret_val)
3154 return ret_val;
3155 break;
3156 default:
3157 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3158 if (ret_val)
3159 return ret_val;
3160
3161 phy_data |= MII_CR_RESET;
3162 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3163 if (ret_val)
3164 return ret_val;
3165
3166 udelay(1);
3167 break;
3168 }
3169
3170 if (hw->phy_type == e1000_phy_igp)
3171 e1000_phy_init_script(hw);
3172
3173 return E1000_SUCCESS;
1da177e4
LT		 3174}
3175
120a5d0d
JB		 3176/**
3177 * e1000_detect_gig_phy - check the phy type
3178 * @hw: Struct containing variables accessed by shared code
3179 *
3180 * Probes the expected PHY address for known PHY IDs
3181 */
64798845 3182static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
1da177e4 3183{
120a5d0d
JB		 3184 s32 phy_init_status, ret_val;
3185 u16 phy_id_high, phy_id_low;
3186 bool match = false;
3187
675ad473 3188 e_dbg("e1000_detect_gig_phy");
120a5d0d
JB		 3189
3190 if (hw->phy_id != 0)
3191 return E1000_SUCCESS;
3192
3193 /* Read the PHY ID Registers to identify which PHY is onboard. */
3194 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
3195 if (ret_val)
3196 return ret_val;
3197
3198 hw->phy_id = (u32) (phy_id_high << 16);
3199 udelay(20);
3200 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
3201 if (ret_val)
3202 return ret_val;
3203
3204 hw->phy_id |= (u32) (phy_id_low & PHY_REVISION_MASK);
3205 hw->phy_revision = (u32) phy_id_low & ~PHY_REVISION_MASK;
3206
3207 switch (hw->mac_type) {
3208 case e1000_82543:
3209 if (hw->phy_id == M88E1000_E_PHY_ID)
3210 match = true;
3211 break;
3212 case e1000_82544:
3213 if (hw->phy_id == M88E1000_I_PHY_ID)
3214 match = true;
3215 break;
3216 case e1000_82540:
3217 case e1000_82545:
3218 case e1000_82545_rev_3:
3219 case e1000_82546:
3220 case e1000_82546_rev_3:
3221 if (hw->phy_id == M88E1011_I_PHY_ID)
3222 match = true;
3223 break;
5377a416
DB		 3224 case e1000_ce4100:
3225 if ((hw->phy_id == RTL8211B_PHY_ID) ||
cf8e09b0
FF		 3226 (hw->phy_id == RTL8201N_PHY_ID) ||
3227 (hw->phy_id == M88E1118_E_PHY_ID))
5377a416
DB		 3228 match = true;
3229 break;
120a5d0d
JB		 3230 case e1000_82541:
3231 case e1000_82541_rev_2:
3232 case e1000_82547:
3233 case e1000_82547_rev_2:
3234 if (hw->phy_id == IGP01E1000_I_PHY_ID)
3235 match = true;
3236 break;
3237 default:
675ad473 3238 e_dbg("Invalid MAC type %d\n", hw->mac_type);
120a5d0d
JB		 3239 return -E1000_ERR_CONFIG;
3240 }
3241 phy_init_status = e1000_set_phy_type(hw);
3242
3243 if ((match) && (phy_init_status == E1000_SUCCESS)) {
675ad473 3244 e_dbg("PHY ID 0x%X detected\n", hw->phy_id);
120a5d0d
JB		 3245 return E1000_SUCCESS;
3246 }
675ad473 3247 e_dbg("Invalid PHY ID 0x%X\n", hw->phy_id);
120a5d0d 3248 return -E1000_ERR_PHY;
1da177e4
LT		 3249}
3250
120a5d0d
JB		 3251/**
3252 * e1000_phy_reset_dsp - reset DSP
3253 * @hw: Struct containing variables accessed by shared code
3254 *
3255 * Resets the PHY's DSP
3256 */
64798845 3257static s32 e1000_phy_reset_dsp(struct e1000_hw *hw)
1da177e4 3258{
120a5d0d 3259 s32 ret_val;
675ad473 3260 e_dbg("e1000_phy_reset_dsp");
120a5d0d
JB		 3261
3262 do {
3263 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
3264 if (ret_val)
3265 break;
3266 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
3267 if (ret_val)
3268 break;
3269 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
3270 if (ret_val)
3271 break;
3272 ret_val = E1000_SUCCESS;
3273 } while (0);
3274
3275 return ret_val;
1da177e4
LT		 3276}
3277
120a5d0d
JB		 3278/**
3279 * e1000_phy_igp_get_info - get igp specific registers
3280 * @hw: Struct containing variables accessed by shared code
3281 * @phy_info: PHY information structure
3282 *
3283 * Get PHY information from various PHY registers for igp PHY only.
3284 */
64798845
JP		 3285static s32 e1000_phy_igp_get_info(struct e1000_hw *hw,
3286 struct e1000_phy_info *phy_info)
1da177e4 3287{
120a5d0d
JB		 3288 s32 ret_val;
3289 u16 phy_data, min_length, max_length, average;
3290 e1000_rev_polarity polarity;
3291
675ad473 3292 e_dbg("e1000_phy_igp_get_info");
120a5d0d
JB		 3293
3294 /* The downshift status is checked only once, after link is established,
3295 * and it stored in the hw->speed_downgraded parameter. */
3296 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3297
3298 /* IGP01E1000 does not need to support it. */
3299 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
3300
3301 /* IGP01E1000 always correct polarity reversal */
3302 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
3303
3304 /* Check polarity status */
3305 ret_val = e1000_check_polarity(hw, &polarity);
3306 if (ret_val)
3307 return ret_val;
3308
3309 phy_info->cable_polarity = polarity;
3310
3311 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
3312 if (ret_val)
3313 return ret_val;
3314
3315 phy_info->mdix_mode =
3316 (e1000_auto_x_mode) ((phy_data & IGP01E1000_PSSR_MDIX) >>
3317 IGP01E1000_PSSR_MDIX_SHIFT);
3318
3319 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
3320 IGP01E1000_PSSR_SPEED_1000MBPS) {
3321 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
3322 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3323 if (ret_val)
3324 return ret_val;
3325
3326 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3327 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3328 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3329 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3330 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3331 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3332
3333 /* Get cable length */
3334 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
3335 if (ret_val)
3336 return ret_val;
3337
3338 /* Translate to old method */
3339 average = (max_length + min_length) / 2;
3340
3341 if (average <= e1000_igp_cable_length_50)
3342 phy_info->cable_length = e1000_cable_length_50;
3343 else if (average <= e1000_igp_cable_length_80)
3344 phy_info->cable_length = e1000_cable_length_50_80;
3345 else if (average <= e1000_igp_cable_length_110)
3346 phy_info->cable_length = e1000_cable_length_80_110;
3347 else if (average <= e1000_igp_cable_length_140)
3348 phy_info->cable_length = e1000_cable_length_110_140;
3349 else
3350 phy_info->cable_length = e1000_cable_length_140;
3351 }
1da177e4 3352
120a5d0d
JB		 3353 return E1000_SUCCESS;
3354}
d37ea5d5 3355
120a5d0d
JB		 3356/**
3357 * e1000_phy_m88_get_info - get m88 specific registers
3358 * @hw: Struct containing variables accessed by shared code
3359 * @phy_info: PHY information structure
3360 *
3361 * Get PHY information from various PHY registers for m88 PHY only.
3362 */
64798845
JP		 3363static s32 e1000_phy_m88_get_info(struct e1000_hw *hw,
3364 struct e1000_phy_info *phy_info)
1da177e4 3365{
120a5d0d
JB		 3366 s32 ret_val;
3367 u16 phy_data;
3368 e1000_rev_polarity polarity;
3369
675ad473 3370 e_dbg("e1000_phy_m88_get_info");
120a5d0d
JB		 3371
3372 /* The downshift status is checked only once, after link is established,
3373 * and it stored in the hw->speed_downgraded parameter. */
3374 phy_info->downshift = (e1000_downshift) hw->speed_downgraded;
3375
3376 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3377 if (ret_val)
3378 return ret_val;
3379
3380 phy_info->extended_10bt_distance =
3381 ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
3382 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
3383 e1000_10bt_ext_dist_enable_lower :
3384 e1000_10bt_ext_dist_enable_normal;
3385
3386 phy_info->polarity_correction =
3387 ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
3388 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
3389 e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
3390
3391 /* Check polarity status */
3392 ret_val = e1000_check_polarity(hw, &polarity);
3393 if (ret_val)
3394 return ret_val;
3395 phy_info->cable_polarity = polarity;
3396
3397 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
3398 if (ret_val)
3399 return ret_val;
3400
3401 phy_info->mdix_mode =
3402 (e1000_auto_x_mode) ((phy_data & M88E1000_PSSR_MDIX) >>
3403 M88E1000_PSSR_MDIX_SHIFT);
3404
3405 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
3406 /* Cable Length Estimation and Local/Remote Receiver Information
3407 * are only valid at 1000 Mbps.
3408 */
3409 phy_info->cable_length =
3410 (e1000_cable_length) ((phy_data &
3411 M88E1000_PSSR_CABLE_LENGTH) >>
3412 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
3413
3414 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
3415 if (ret_val)
3416 return ret_val;
3417
3418 phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
3419 SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
3420 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3421 phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
3422 SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
3423 e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3424
3425 }
3426
3427 return E1000_SUCCESS;
1da177e4
LT		 3428}
3429
120a5d0d
JB		 3430/**
3431 * e1000_phy_get_info - request phy info
3432 * @hw: Struct containing variables accessed by shared code
3433 * @phy_info: PHY information structure
3434 *
3435 * Get PHY information from various PHY registers
3436 */
64798845 3437s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
1da177e4 3438{
120a5d0d
JB		 3439 s32 ret_val;
3440 u16 phy_data;
3441
675ad473 3442 e_dbg("e1000_phy_get_info");
120a5d0d
JB		 3443
3444 phy_info->cable_length = e1000_cable_length_undefined;
3445 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
3446 phy_info->cable_polarity = e1000_rev_polarity_undefined;
3447 phy_info->downshift = e1000_downshift_undefined;
3448 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
3449 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
3450 phy_info->local_rx = e1000_1000t_rx_status_undefined;
3451 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
3452
3453 if (hw->media_type != e1000_media_type_copper) {
675ad473 3454 e_dbg("PHY info is only valid for copper media\n");
120a5d0d
JB		 3455 return -E1000_ERR_CONFIG;
3456 }
3457
3458 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3459 if (ret_val)
3460 return ret_val;
3461
3462 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3463 if (ret_val)
3464 return ret_val;
3465
3466 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
675ad473 3467 e_dbg("PHY info is only valid if link is up\n");
120a5d0d
JB		 3468 return -E1000_ERR_CONFIG;
3469 }
3470
3471 if (hw->phy_type == e1000_phy_igp)
3472 return e1000_phy_igp_get_info(hw, phy_info);
5377a416
DB		 3473 else if ((hw->phy_type == e1000_phy_8211) ||
3474 (hw->phy_type == e1000_phy_8201))
3475 return E1000_SUCCESS;
120a5d0d
JB		 3476 else
3477 return e1000_phy_m88_get_info(hw, phy_info);
1da177e4
LT		 3478}
3479
64798845 3480s32 e1000_validate_mdi_setting(struct e1000_hw *hw)
1da177e4 3481{
675ad473 3482 e_dbg("e1000_validate_mdi_settings");
1da177e4 3483
120a5d0d 3484 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
675ad473 3485 e_dbg("Invalid MDI setting detected\n");
120a5d0d
JB		 3486 hw->mdix = 1;
3487 return -E1000_ERR_CONFIG;
3488 }
3489 return E1000_SUCCESS;
3490}
1da177e4 3491
120a5d0d
JB		 3492/**
3493 * e1000_init_eeprom_params - initialize sw eeprom vars
3494 * @hw: Struct containing variables accessed by shared code
3495 *
1da177e4 3496 * Sets up eeprom variables in the hw struct. Must be called after mac_type
1532ecea 3497 * is configured.
120a5d0d 3498 */
64798845 3499s32 e1000_init_eeprom_params(struct e1000_hw *hw)
1da177e4 3500{
120a5d0d
JB		 3501 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3502 u32 eecd = er32(EECD);
3503 s32 ret_val = E1000_SUCCESS;
3504 u16 eeprom_size;
3505
675ad473 3506 e_dbg("e1000_init_eeprom_params");
120a5d0d
JB		 3507
3508 switch (hw->mac_type) {
3509 case e1000_82542_rev2_0:
3510 case e1000_82542_rev2_1:
3511 case e1000_82543:
3512 case e1000_82544:
3513 eeprom->type = e1000_eeprom_microwire;
3514 eeprom->word_size = 64;
3515 eeprom->opcode_bits = 3;
3516 eeprom->address_bits = 6;
3517 eeprom->delay_usec = 50;
120a5d0d
JB		 3518 break;
3519 case e1000_82540:
3520 case e1000_82545:
3521 case e1000_82545_rev_3:
3522 case e1000_82546:
3523 case e1000_82546_rev_3:
3524 eeprom->type = e1000_eeprom_microwire;
3525 eeprom->opcode_bits = 3;
3526 eeprom->delay_usec = 50;
3527 if (eecd & E1000_EECD_SIZE) {
3528 eeprom->word_size = 256;
3529 eeprom->address_bits = 8;
3530 } else {
3531 eeprom->word_size = 64;
3532 eeprom->address_bits = 6;
3533 }
120a5d0d
JB		 3534 break;
3535 case e1000_82541:
3536 case e1000_82541_rev_2:
3537 case e1000_82547:
3538 case e1000_82547_rev_2:
3539 if (eecd & E1000_EECD_TYPE) {
3540 eeprom->type = e1000_eeprom_spi;
3541 eeprom->opcode_bits = 8;
3542 eeprom->delay_usec = 1;
3543 if (eecd & E1000_EECD_ADDR_BITS) {
3544 eeprom->page_size = 32;
3545 eeprom->address_bits = 16;
3546 } else {
3547 eeprom->page_size = 8;
3548 eeprom->address_bits = 8;
3549 }
3550 } else {
3551 eeprom->type = e1000_eeprom_microwire;
3552 eeprom->opcode_bits = 3;
3553 eeprom->delay_usec = 50;
3554 if (eecd & E1000_EECD_ADDR_BITS) {
3555 eeprom->word_size = 256;
3556 eeprom->address_bits = 8;
3557 } else {
3558 eeprom->word_size = 64;
3559 eeprom->address_bits = 6;
3560 }
3561 }
120a5d0d
JB		 3562 break;
3563 default:
3564 break;
3565 }
3566
3567 if (eeprom->type == e1000_eeprom_spi) {
3568 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
3569 * 32KB (incremented by powers of 2).
3570 */
3571 /* Set to default value for initial eeprom read. */
3572 eeprom->word_size = 64;
3573 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
3574 if (ret_val)
3575 return ret_val;
3576 eeprom_size =
3577 (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
3578 /* 256B eeprom size was not supported in earlier hardware, so we
3579 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
3580 * is never the result used in the shifting logic below. */
3581 if (eeprom_size)
3582 eeprom_size++;
3583
3584 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
3585 }
3586 return ret_val;
1da177e4
LT		 3587}
3588
120a5d0d
JB		 3589/**
3590 * e1000_raise_ee_clk - Raises the EEPROM's clock input.
3591 * @hw: Struct containing variables accessed by shared code
3592 * @eecd: EECD's current value
3593 */
64798845 3594static void e1000_raise_ee_clk(struct e1000_hw *hw, u32 *eecd)
1da177e4 3595{
120a5d0d
JB		 3596 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
3597 * wait <delay> microseconds.
3598 */
3599 *eecd = *eecd | E1000_EECD_SK;
3600 ew32(EECD, *eecd);
3601 E1000_WRITE_FLUSH();
3602 udelay(hw->eeprom.delay_usec);
1da177e4
LT		 3603}
3604
120a5d0d
JB		 3605/**
3606 * e1000_lower_ee_clk - Lowers the EEPROM's clock input.
3607 * @hw: Struct containing variables accessed by shared code
3608 * @eecd: EECD's current value
3609 */
64798845 3610static void e1000_lower_ee_clk(struct e1000_hw *hw, u32 *eecd)
1da177e4 3611{
120a5d0d
JB		 3612 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
3613 * wait 50 microseconds.
3614 */
3615 *eecd = *eecd & ~E1000_EECD_SK;
3616 ew32(EECD, *eecd);
3617 E1000_WRITE_FLUSH();
3618 udelay(hw->eeprom.delay_usec);
1da177e4
LT		 3619}
3620
120a5d0d
JB		 3621/**
3622 * e1000_shift_out_ee_bits - Shift data bits out to the EEPROM.
3623 * @hw: Struct containing variables accessed by shared code
3624 * @data: data to send to the EEPROM
3625 * @count: number of bits to shift out
3626 */
64798845 3627static void e1000_shift_out_ee_bits(struct e1000_hw *hw, u16 data, u16 count)
1da177e4 3628{
120a5d0d
JB		 3629 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3630 u32 eecd;
3631 u32 mask;
3632
3633 /* We need to shift "count" bits out to the EEPROM. So, value in the
3634 * "data" parameter will be shifted out to the EEPROM one bit at a time.
3635 * In order to do this, "data" must be broken down into bits.
3636 */
3637 mask = 0x01 << (count - 1);
3638 eecd = er32(EECD);
3639 if (eeprom->type == e1000_eeprom_microwire) {
3640 eecd &= ~E1000_EECD_DO;
3641 } else if (eeprom->type == e1000_eeprom_spi) {
3642 eecd |= E1000_EECD_DO;
3643 }
3644 do {
3645 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
3646 * and then raising and then lowering the clock (the SK bit controls
3647 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
3648 * by setting "DI" to "0" and then raising and then lowering the clock.
3649 */
3650 eecd &= ~E1000_EECD_DI;
3651
3652 if (data & mask)
3653 eecd |= E1000_EECD_DI;
3654
3655 ew32(EECD, eecd);
3656 E1000_WRITE_FLUSH();
3657
3658 udelay(eeprom->delay_usec);
3659
3660 e1000_raise_ee_clk(hw, &eecd);
3661 e1000_lower_ee_clk(hw, &eecd);
3662
3663 mask = mask >> 1;
3664
3665 } while (mask);
3666
3667 /* We leave the "DI" bit set to "0" when we leave this routine. */
3668 eecd &= ~E1000_EECD_DI;
3669 ew32(EECD, eecd);
1da177e4
LT		 3670}
3671
120a5d0d
JB		 3672/**
3673 * e1000_shift_in_ee_bits - Shift data bits in from the EEPROM
3674 * @hw: Struct containing variables accessed by shared code
3675 * @count: number of bits to shift in
3676 */
64798845 3677static u16 e1000_shift_in_ee_bits(struct e1000_hw *hw, u16 count)
1da177e4 3678{
120a5d0d
JB		 3679 u32 eecd;
3680 u32 i;
3681 u16 data;
3682
3683 /* In order to read a register from the EEPROM, we need to shift 'count'
3684 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
3685 * input to the EEPROM (setting the SK bit), and then reading the value of
3686 * the "DO" bit. During this "shifting in" process the "DI" bit should
3687 * always be clear.
3688 */
1da177e4 3689
120a5d0d 3690 eecd = er32(EECD);
1da177e4 3691
120a5d0d
JB		 3692 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
3693 data = 0;
1da177e4 3694
120a5d0d
JB		 3695 for (i = 0; i < count; i++) {
3696 data = data << 1;
3697 e1000_raise_ee_clk(hw, &eecd);
1da177e4 3698
120a5d0d 3699 eecd = er32(EECD);
1da177e4 3700
120a5d0d
JB		 3701 eecd &= ~(E1000_EECD_DI);
3702 if (eecd & E1000_EECD_DO)
3703 data |= 1;
1da177e4 3704
120a5d0d
JB		 3705 e1000_lower_ee_clk(hw, &eecd);
3706 }
1da177e4 3707
120a5d0d 3708 return data;
1da177e4
LT		 3709}
3710
120a5d0d
JB		 3711/**
3712 * e1000_acquire_eeprom - Prepares EEPROM for access
3713 * @hw: Struct containing variables accessed by shared code
1da177e4
LT		 3714 *
3715 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
3716 * function should be called before issuing a command to the EEPROM.
120a5d0d 3717 */
64798845 3718static s32 e1000_acquire_eeprom(struct e1000_hw *hw)
1da177e4 3719{
120a5d0d
JB		 3720 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3721 u32 eecd, i = 0;
3722
675ad473 3723 e_dbg("e1000_acquire_eeprom");
120a5d0d
JB		 3724
3725 eecd = er32(EECD);
3726
3727 /* Request EEPROM Access */
3728 if (hw->mac_type > e1000_82544) {
3729 eecd |= E1000_EECD_REQ;
3730 ew32(EECD, eecd);
3731 eecd = er32(EECD);
3732 while ((!(eecd & E1000_EECD_GNT)) &&
3733 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
3734 i++;
3735 udelay(5);
3736 eecd = er32(EECD);
3737 }
3738 if (!(eecd & E1000_EECD_GNT)) {
3739 eecd &= ~E1000_EECD_REQ;
3740 ew32(EECD, eecd);
675ad473 3741 e_dbg("Could not acquire EEPROM grant\n");
120a5d0d
JB		 3742 return -E1000_ERR_EEPROM;
3743 }
3744 }
3745
3746 /* Setup EEPROM for Read/Write */
3747
3748 if (eeprom->type == e1000_eeprom_microwire) {
3749 /* Clear SK and DI */
3750 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
3751 ew32(EECD, eecd);
3752
3753 /* Set CS */
3754 eecd |= E1000_EECD_CS;
3755 ew32(EECD, eecd);
3756 } else if (eeprom->type == e1000_eeprom_spi) {
3757 /* Clear SK and CS */
3758 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3759 ew32(EECD, eecd);
3760 udelay(1);
3761 }
3762
3763 return E1000_SUCCESS;
1da177e4
LT		 3764}
3765
120a5d0d
JB		 3766/**
3767 * e1000_standby_eeprom - Returns EEPROM to a "standby" state
3768 * @hw: Struct containing variables accessed by shared code
3769 */
64798845 3770static void e1000_standby_eeprom(struct e1000_hw *hw)
1da177e4 3771{
120a5d0d
JB		 3772 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3773 u32 eecd;
3774
3775 eecd = er32(EECD);
3776
3777 if (eeprom->type == e1000_eeprom_microwire) {
3778 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
3779 ew32(EECD, eecd);
3780 E1000_WRITE_FLUSH();
3781 udelay(eeprom->delay_usec);
3782
3783 /* Clock high */
3784 eecd |= E1000_EECD_SK;
3785 ew32(EECD, eecd);
3786 E1000_WRITE_FLUSH();
3787 udelay(eeprom->delay_usec);
3788
3789 /* Select EEPROM */
3790 eecd |= E1000_EECD_CS;
3791 ew32(EECD, eecd);
3792 E1000_WRITE_FLUSH();
3793 udelay(eeprom->delay_usec);
3794
3795 /* Clock low */
3796 eecd &= ~E1000_EECD_SK;
3797 ew32(EECD, eecd);
3798 E1000_WRITE_FLUSH();
3799 udelay(eeprom->delay_usec);
3800 } else if (eeprom->type == e1000_eeprom_spi) {
3801 /* Toggle CS to flush commands */
3802 eecd |= E1000_EECD_CS;
3803 ew32(EECD, eecd);
3804 E1000_WRITE_FLUSH();
3805 udelay(eeprom->delay_usec);
3806 eecd &= ~E1000_EECD_CS;
3807 ew32(EECD, eecd);
3808 E1000_WRITE_FLUSH();
3809 udelay(eeprom->delay_usec);
3810 }
1da177e4
LT		 3811}
3812
120a5d0d
JB		 3813/**
3814 * e1000_release_eeprom - drop chip select
3815 * @hw: Struct containing variables accessed by shared code
1da177e4 3816 *
120a5d0d
JB		 3817 * Terminates a command by inverting the EEPROM's chip select pin
3818 */
64798845 3819static void e1000_release_eeprom(struct e1000_hw *hw)
1da177e4 3820{
120a5d0d 3821 u32 eecd;
1da177e4 3822
675ad473 3823 e_dbg("e1000_release_eeprom");
1da177e4 3824
120a5d0d 3825 eecd = er32(EECD);
1da177e4 3826
120a5d0d
JB		 3827 if (hw->eeprom.type == e1000_eeprom_spi) {
3828 eecd |= E1000_EECD_CS; /* Pull CS high */
3829 eecd &= ~E1000_EECD_SK; /* Lower SCK */
1da177e4 3830
120a5d0d 3831 ew32(EECD, eecd);
1da177e4 3832
120a5d0d
JB		 3833 udelay(hw->eeprom.delay_usec);
3834 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
3835 /* cleanup eeprom */
1da177e4 3836
120a5d0d
JB		 3837 /* CS on Microwire is active-high */
3838 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
1da177e4 3839
120a5d0d 3840 ew32(EECD, eecd);
1da177e4 3841
120a5d0d
JB		 3842 /* Rising edge of clock */
3843 eecd |= E1000_EECD_SK;
3844 ew32(EECD, eecd);
3845 E1000_WRITE_FLUSH();
3846 udelay(hw->eeprom.delay_usec);
1da177e4 3847
120a5d0d
JB		 3848 /* Falling edge of clock */
3849 eecd &= ~E1000_EECD_SK;
3850 ew32(EECD, eecd);
3851 E1000_WRITE_FLUSH();
3852 udelay(hw->eeprom.delay_usec);
3853 }
1da177e4 3854
120a5d0d
JB		 3855 /* Stop requesting EEPROM access */
3856 if (hw->mac_type > e1000_82544) {
3857 eecd &= ~E1000_EECD_REQ;
3858 ew32(EECD, eecd);
3859 }
1da177e4
LT		 3860}
3861
120a5d0d
JB		 3862/**
3863 * e1000_spi_eeprom_ready - Reads a 16 bit word from the EEPROM.
3864 * @hw: Struct containing variables accessed by shared code
3865 */
64798845 3866static s32 e1000_spi_eeprom_ready(struct e1000_hw *hw)
1da177e4 3867{
120a5d0d
JB		 3868 u16 retry_count = 0;
3869 u8 spi_stat_reg;
3870
675ad473 3871 e_dbg("e1000_spi_eeprom_ready");
120a5d0d
JB		 3872
3873 /* Read "Status Register" repeatedly until the LSB is cleared. The
3874 * EEPROM will signal that the command has been completed by clearing
3875 * bit 0 of the internal status register. If it's not cleared within
3876 * 5 milliseconds, then error out.
3877 */
3878 retry_count = 0;
3879 do {
3880 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3881 hw->eeprom.opcode_bits);
3882 spi_stat_reg = (u8) e1000_shift_in_ee_bits(hw, 8);
3883 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3884 break;
3885
3886 udelay(5);
3887 retry_count += 5;
3888
3889 e1000_standby_eeprom(hw);
3890 } while (retry_count < EEPROM_MAX_RETRY_SPI);
3891
3892 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3893 * only 0-5mSec on 5V devices)
3894 */
3895 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
675ad473 3896 e_dbg("SPI EEPROM Status error\n");
120a5d0d
JB		 3897 return -E1000_ERR_EEPROM;
3898 }
3899
3900 return E1000_SUCCESS;
1da177e4
LT		 3901}
3902
120a5d0d
JB		 3903/**
3904 * e1000_read_eeprom - Reads a 16 bit word from the EEPROM.
3905 * @hw: Struct containing variables accessed by shared code
3906 * @offset: offset of word in the EEPROM to read
3907 * @data: word read from the EEPROM
3908 * @words: number of words to read
3909 */
64798845 3910s32 e1000_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
78566fec 3911{
120a5d0d
JB		 3912 s32 ret;
3913 spin_lock(&e1000_eeprom_lock);
3914 ret = e1000_do_read_eeprom(hw, offset, words, data);
3915 spin_unlock(&e1000_eeprom_lock);
3916 return ret;
78566fec
CL		 3917}
3918
120a5d0d
JB		 3919static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
3920 u16 *data)
1da177e4 3921{
120a5d0d
JB		 3922 struct e1000_eeprom_info *eeprom = &hw->eeprom;
3923 u32 i = 0;
3924
675ad473 3925 e_dbg("e1000_read_eeprom");
120a5d0d 3926
5377a416
DB		 3927 if (hw->mac_type == e1000_ce4100) {
3928 GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
3929 data);
3930 return E1000_SUCCESS;
3931 }
3932
120a5d0d
JB		 3933 /* If eeprom is not yet detected, do so now */
3934 if (eeprom->word_size == 0)
3935 e1000_init_eeprom_params(hw);
3936
3937 /* A check for invalid values: offset too large, too many words, and not
3938 * enough words.
3939 */
3940 if ((offset >= eeprom->word_size)
3941 || (words > eeprom->word_size - offset) || (words == 0)) {
675ad473
ET		 3942 e_dbg("\"words\" parameter out of bounds. Words = %d,"
3943 "size = %d\n", offset, eeprom->word_size);
120a5d0d
JB		 3944 return -E1000_ERR_EEPROM;
3945 }
3946
3947 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
3948 * directly. In this case, we need to acquire the EEPROM so that
3949 * FW or other port software does not interrupt.
3950 */
8f601b2d
JB		 3951 /* Prepare the EEPROM for bit-bang reading */
3952 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3953 return -E1000_ERR_EEPROM;
120a5d0d
JB		 3954
3955 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
3956 * acquired the EEPROM at this point, so any returns should release it */
3957 if (eeprom->type == e1000_eeprom_spi) {
3958 u16 word_in;
3959 u8 read_opcode = EEPROM_READ_OPCODE_SPI;
3960
3961 if (e1000_spi_eeprom_ready(hw)) {
3962 e1000_release_eeprom(hw);
3963 return -E1000_ERR_EEPROM;
3964 }
3965
3966 e1000_standby_eeprom(hw);
3967
3968 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3969 if ((eeprom->address_bits == 8) && (offset >= 128))
3970 read_opcode |= EEPROM_A8_OPCODE_SPI;
3971
3972 /* Send the READ command (opcode + addr) */
3973 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3974 e1000_shift_out_ee_bits(hw, (u16) (offset * 2),
3975 eeprom->address_bits);
3976
3977 /* Read the data. The address of the eeprom internally increments with
3978 * each byte (spi) being read, saving on the overhead of eeprom setup
3979 * and tear-down. The address counter will roll over if reading beyond
3980 * the size of the eeprom, thus allowing the entire memory to be read
3981 * starting from any offset. */
3982 for (i = 0; i < words; i++) {
3983 word_in = e1000_shift_in_ee_bits(hw, 16);
3984 data[i] = (word_in >> 8) | (word_in << 8);
3985 }
3986 } else if (eeprom->type == e1000_eeprom_microwire) {
3987 for (i = 0; i < words; i++) {
3988 /* Send the READ command (opcode + addr) */
3989 e1000_shift_out_ee_bits(hw,
3990 EEPROM_READ_OPCODE_MICROWIRE,
3991 eeprom->opcode_bits);
3992 e1000_shift_out_ee_bits(hw, (u16) (offset + i),
3993 eeprom->address_bits);
3994
3995 /* Read the data. For microwire, each word requires the overhead
3996 * of eeprom setup and tear-down. */
3997 data[i] = e1000_shift_in_ee_bits(hw, 16);
3998 e1000_standby_eeprom(hw);
3999 }
4000 }
4001
4002 /* End this read operation */
4003 e1000_release_eeprom(hw);
4004
4005 return E1000_SUCCESS;
1da177e4
LT		 4006}
4007
120a5d0d
JB		 4008/**
4009 * e1000_validate_eeprom_checksum - Verifies that the EEPROM has a valid checksum
4010 * @hw: Struct containing variables accessed by shared code
2d7edb92
MC		 4011 *
4012 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
4013 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
4014 * valid.
120a5d0d 4015 */
64798845 4016s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
2d7edb92 4017{
120a5d0d
JB		 4018 u16 checksum = 0;
4019 u16 i, eeprom_data;
4020
675ad473 4021 e_dbg("e1000_validate_eeprom_checksum");
120a5d0d
JB		 4022
4023 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
4024 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
675ad473 4025 e_dbg("EEPROM Read Error\n");
120a5d0d
JB		 4026 return -E1000_ERR_EEPROM;
4027 }
4028 checksum += eeprom_data;
4029 }
4030
4031 if (checksum == (u16) EEPROM_SUM)
4032 return E1000_SUCCESS;
4033 else {
675ad473 4034 e_dbg("EEPROM Checksum Invalid\n");
120a5d0d
JB		 4035 return -E1000_ERR_EEPROM;
4036 }
2d7edb92
MC		 4037}
4038
120a5d0d
JB		 4039/**
4040 * e1000_update_eeprom_checksum - Calculates/writes the EEPROM checksum
4041 * @hw: Struct containing variables accessed by shared code
2d7edb92
MC		 4042 *
4043 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
4044 * Writes the difference to word offset 63 of the EEPROM.
120a5d0d 4045 */
64798845 4046s32 e1000_update_eeprom_checksum(struct e1000_hw *hw)
2d7edb92 4047{
120a5d0d
JB		 4048 u16 checksum = 0;
4049 u16 i, eeprom_data;
4050
675ad473 4051 e_dbg("e1000_update_eeprom_checksum");
120a5d0d
JB		 4052
4053 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
4054 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
675ad473 4055 e_dbg("EEPROM Read Error\n");
120a5d0d
JB		 4056 return -E1000_ERR_EEPROM;
4057 }
4058 checksum += eeprom_data;
4059 }
4060 checksum = (u16) EEPROM_SUM - checksum;
4061 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
675ad473 4062 e_dbg("EEPROM Write Error\n");
120a5d0d
JB		 4063 return -E1000_ERR_EEPROM;
4064 }
4065 return E1000_SUCCESS;
1da177e4
LT		 4066}
4067
120a5d0d
JB		 4068/**
4069 * e1000_write_eeprom - write words to the different EEPROM types.
4070 * @hw: Struct containing variables accessed by shared code
4071 * @offset: offset within the EEPROM to be written to
4072 * @words: number of words to write
4073 * @data: 16 bit word to be written to the EEPROM
1da177e4
LT		 4074 *
4075 * If e1000_update_eeprom_checksum is not called after this function, the
4076 * EEPROM will most likely contain an invalid checksum.
120a5d0d 4077 */
64798845 4078s32 e1000_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
78566fec 4079{
120a5d0d
JB		 4080 s32 ret;
4081 spin_lock(&e1000_eeprom_lock);
4082 ret = e1000_do_write_eeprom(hw, offset, words, data);
4083 spin_unlock(&e1000_eeprom_lock);
4084 return ret;
78566fec
CL		 4085}
4086
120a5d0d
JB		 4087static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
4088 u16 *data)
1da177e4 4089{
120a5d0d
JB		 4090 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4091 s32 status = 0;
4092
675ad473 4093 e_dbg("e1000_write_eeprom");
120a5d0d 4094
5377a416
DB		 4095 if (hw->mac_type == e1000_ce4100) {
4096 GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
4097 data);
4098 return E1000_SUCCESS;
4099 }
4100
120a5d0d
JB		 4101 /* If eeprom is not yet detected, do so now */
4102 if (eeprom->word_size == 0)
4103 e1000_init_eeprom_params(hw);
4104
4105 /* A check for invalid values: offset too large, too many words, and not
4106 * enough words.
4107 */
4108 if ((offset >= eeprom->word_size)
4109 || (words > eeprom->word_size - offset) || (words == 0)) {
675ad473 4110 e_dbg("\"words\" parameter out of bounds\n");
120a5d0d
JB		 4111 return -E1000_ERR_EEPROM;
4112 }
4113
120a5d0d
JB		 4114 /* Prepare the EEPROM for writing */
4115 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4116 return -E1000_ERR_EEPROM;
4117
4118 if (eeprom->type == e1000_eeprom_microwire) {
4119 status = e1000_write_eeprom_microwire(hw, offset, words, data);
4120 } else {
4121 status = e1000_write_eeprom_spi(hw, offset, words, data);
4122 msleep(10);
4123 }
4124
4125 /* Done with writing */
4126 e1000_release_eeprom(hw);
4127
4128 return status;
1da177e4
LT		 4129}
4130
120a5d0d
JB		 4131/**
4132 * e1000_write_eeprom_spi - Writes a 16 bit word to a given offset in an SPI EEPROM.
4133 * @hw: Struct containing variables accessed by shared code
4134 * @offset: offset within the EEPROM to be written to
4135 * @words: number of words to write
4136 * @data: pointer to array of 8 bit words to be written to the EEPROM
4137 */
64798845
JP		 4138static s32 e1000_write_eeprom_spi(struct e1000_hw *hw, u16 offset, u16 words,
4139 u16 *data)
1da177e4 4140{
120a5d0d
JB		 4141 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4142 u16 widx = 0;
1da177e4 4143
675ad473 4144 e_dbg("e1000_write_eeprom_spi");
1da177e4 4145
120a5d0d
JB		 4146 while (widx < words) {
4147 u8 write_opcode = EEPROM_WRITE_OPCODE_SPI;
1da177e4 4148
120a5d0d
JB		 4149 if (e1000_spi_eeprom_ready(hw))
4150 return -E1000_ERR_EEPROM;
1da177e4 4151
120a5d0d 4152 e1000_standby_eeprom(hw);
1da177e4 4153
120a5d0d
JB		 4154 /* Send the WRITE ENABLE command (8 bit opcode ) */
4155 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
4156 eeprom->opcode_bits);
1da177e4 4157
120a5d0d 4158 e1000_standby_eeprom(hw);
1da177e4 4159
120a5d0d
JB		 4160 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
4161 if ((eeprom->address_bits == 8) && (offset >= 128))
4162 write_opcode |= EEPROM_A8_OPCODE_SPI;
1da177e4 4163
120a5d0d
JB		 4164 /* Send the Write command (8-bit opcode + addr) */
4165 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
1da177e4 4166
120a5d0d
JB		 4167 e1000_shift_out_ee_bits(hw, (u16) ((offset + widx) * 2),
4168 eeprom->address_bits);
1da177e4 4169
120a5d0d 4170 /* Send the data */
1da177e4 4171
120a5d0d
JB		 4172 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
4173 while (widx < words) {
4174 u16 word_out = data[widx];
4175 word_out = (word_out >> 8) | (word_out << 8);
4176 e1000_shift_out_ee_bits(hw, word_out, 16);
4177 widx++;
1da177e4 4178
120a5d0d
JB		 4179 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
4180 * operation, while the smaller eeproms are capable of an 8-byte
4181 * PAGE WRITE operation. Break the inner loop to pass new address
4182 */
4183 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
4184 e1000_standby_eeprom(hw);
4185 break;
4186 }
4187 }
4188 }
1da177e4 4189
120a5d0d 4190 return E1000_SUCCESS;
1da177e4
LT		 4191}
4192
120a5d0d
JB		 4193/**
4194 * e1000_write_eeprom_microwire - Writes a 16 bit word to a given offset in a Microwire EEPROM.
4195 * @hw: Struct containing variables accessed by shared code
4196 * @offset: offset within the EEPROM to be written to
4197 * @words: number of words to write
4198 * @data: pointer to array of 8 bit words to be written to the EEPROM
4199 */
64798845
JP		 4200static s32 e1000_write_eeprom_microwire(struct e1000_hw *hw, u16 offset,
4201 u16 words, u16 *data)
1da177e4 4202{
120a5d0d
JB		 4203 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4204 u32 eecd;
4205 u16 words_written = 0;
4206 u16 i = 0;
4207
675ad473 4208 e_dbg("e1000_write_eeprom_microwire");
120a5d0d
JB		 4209
4210 /* Send the write enable command to the EEPROM (3-bit opcode plus
4211 * 6/8-bit dummy address beginning with 11). It's less work to include
4212 * the 11 of the dummy address as part of the opcode than it is to shift
4213 * it over the correct number of bits for the address. This puts the
4214 * EEPROM into write/erase mode.
4215 */
4216 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
4217 (u16) (eeprom->opcode_bits + 2));
4218
4219 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4220
4221 /* Prepare the EEPROM */
4222 e1000_standby_eeprom(hw);
4223
4224 while (words_written < words) {
4225 /* Send the Write command (3-bit opcode + addr) */
4226 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
4227 eeprom->opcode_bits);
4228
4229 e1000_shift_out_ee_bits(hw, (u16) (offset + words_written),
4230 eeprom->address_bits);
4231
4232 /* Send the data */
4233 e1000_shift_out_ee_bits(hw, data[words_written], 16);
4234
4235 /* Toggle the CS line. This in effect tells the EEPROM to execute
4236 * the previous command.
4237 */
4238 e1000_standby_eeprom(hw);
4239
4240 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
4241 * signal that the command has been completed by raising the DO signal.
4242 * If DO does not go high in 10 milliseconds, then error out.
4243 */
4244 for (i = 0; i < 200; i++) {
4245 eecd = er32(EECD);
4246 if (eecd & E1000_EECD_DO)
4247 break;
4248 udelay(50);
4249 }
4250 if (i == 200) {
675ad473 4251 e_dbg("EEPROM Write did not complete\n");
120a5d0d
JB		 4252 return -E1000_ERR_EEPROM;
4253 }
4254
4255 /* Recover from write */
4256 e1000_standby_eeprom(hw);
4257
4258 words_written++;
4259 }
4260
4261 /* Send the write disable command to the EEPROM (3-bit opcode plus
4262 * 6/8-bit dummy address beginning with 10). It's less work to include
4263 * the 10 of the dummy address as part of the opcode than it is to shift
4264 * it over the correct number of bits for the address. This takes the
4265 * EEPROM out of write/erase mode.
4266 */
4267 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
4268 (u16) (eeprom->opcode_bits + 2));
4269
4270 e1000_shift_out_ee_bits(hw, 0, (u16) (eeprom->address_bits - 2));
4271
4272 return E1000_SUCCESS;
1da177e4
LT		 4273}
4274
120a5d0d
JB		 4275/**
4276 * e1000_read_mac_addr - read the adapters MAC from eeprom
4277 * @hw: Struct containing variables accessed by shared code
4278 *
1da177e4
LT		 4279 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
4280 * second function of dual function devices
120a5d0d 4281 */
64798845 4282s32 e1000_read_mac_addr(struct e1000_hw *hw)
1da177e4 4283{
120a5d0d
JB		 4284 u16 offset;
4285 u16 eeprom_data, i;
4286
675ad473 4287 e_dbg("e1000_read_mac_addr");
120a5d0d
JB		 4288
4289 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
4290 offset = i >> 1;
4291 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
675ad473 4292 e_dbg("EEPROM Read Error\n");
120a5d0d
JB		 4293 return -E1000_ERR_EEPROM;
4294 }
4295 hw->perm_mac_addr[i] = (u8) (eeprom_data & 0x00FF);
4296 hw->perm_mac_addr[i + 1] = (u8) (eeprom_data >> 8);
4297 }
4298
4299 switch (hw->mac_type) {
4300 default:
4301 break;
4302 case e1000_82546:
4303 case e1000_82546_rev_3:
4304 if (er32(STATUS) & E1000_STATUS_FUNC_1)
4305 hw->perm_mac_addr[5] ^= 0x01;
4306 break;
4307 }
4308
4309 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
4310 hw->mac_addr[i] = hw->perm_mac_addr[i];
4311 return E1000_SUCCESS;
1da177e4
LT		 4312}
4313
120a5d0d
JB		 4314/**
4315 * e1000_init_rx_addrs - Initializes receive address filters.
4316 * @hw: Struct containing variables accessed by shared code
1da177e4
LT		 4317 *
4318 * Places the MAC address in receive address register 0 and clears the rest
120a5d0d 4319 * of the receive address registers. Clears the multicast table. Assumes
1da177e4 4320 * the receiver is in reset when the routine is called.
120a5d0d 4321 */
64798845 4322static void e1000_init_rx_addrs(struct e1000_hw *hw)
1da177e4 4323{
120a5d0d
JB		 4324 u32 i;
4325 u32 rar_num;
1da177e4 4326
675ad473 4327 e_dbg("e1000_init_rx_addrs");
1da177e4 4328
120a5d0d 4329 /* Setup the receive address. */
675ad473 4330 e_dbg("Programming MAC Address into RAR[0]\n");
1da177e4 4331
120a5d0d 4332 e1000_rar_set(hw, hw->mac_addr, 0);
1da177e4 4333
120a5d0d 4334 rar_num = E1000_RAR_ENTRIES;
868d5309 4335
120a5d0d 4336 /* Zero out the other 15 receive addresses. */
675ad473 4337 e_dbg("Clearing RAR[1-15]\n");
120a5d0d
JB		 4338 for (i = 1; i < rar_num; i++) {
4339 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4340 E1000_WRITE_FLUSH();
4341 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4342 E1000_WRITE_FLUSH();
4343 }
1da177e4
LT		 4344}
4345
120a5d0d
JB		 4346/**
4347 * e1000_hash_mc_addr - Hashes an address to determine its location in the multicast table
4348 * @hw: Struct containing variables accessed by shared code
4349 * @mc_addr: the multicast address to hash
4350 */
64798845 4351u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
1da177e4 4352{
120a5d0d
JB		 4353 u32 hash_value = 0;
4354
4355 /* The portion of the address that is used for the hash table is
4356 * determined by the mc_filter_type setting.
4357 */
4358 switch (hw->mc_filter_type) {
4359 /* [0] [1] [2] [3] [4] [5]
4360 * 01 AA 00 12 34 56
4361 * LSB MSB
4362 */
4363 case 0:
4364 /* [47:36] i.e. 0x563 for above example address */
4365 hash_value = ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
4366 break;
4367 case 1:
4368 /* [46:35] i.e. 0xAC6 for above example address */
4369 hash_value = ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
4370 break;
4371 case 2:
4372 /* [45:34] i.e. 0x5D8 for above example address */
4373 hash_value = ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
4374 break;
4375 case 3:
4376 /* [43:32] i.e. 0x634 for above example address */
4377 hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
4378 break;
4379 }
4380
4381 hash_value &= 0xFFF;
4382 return hash_value;
1da177e4
LT		 4383}
4384
120a5d0d
JB		 4385/**
4386 * e1000_rar_set - Puts an ethernet address into a receive address register.
4387 * @hw: Struct containing variables accessed by shared code
4388 * @addr: Address to put into receive address register
4389 * @index: Receive address register to write
4390 */
64798845 4391void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
1da177e4 4392{
120a5d0d
JB		 4393 u32 rar_low, rar_high;
4394
4395 /* HW expects these in little endian so we reverse the byte order
4396 * from network order (big endian) to little endian
4397 */
4398 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
4399 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
4400 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
4401
4402 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
4403 * unit hang.
4404 *
4405 * Description:
4406 * If there are any Rx frames queued up or otherwise present in the HW
4407 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
4408 * hang. To work around this issue, we have to disable receives and
4409 * flush out all Rx frames before we enable RSS. To do so, we modify we
4410 * redirect all Rx traffic to manageability and then reset the HW.
4411 * This flushes away Rx frames, and (since the redirections to
4412 * manageability persists across resets) keeps new ones from coming in
4413 * while we work. Then, we clear the Address Valid AV bit for all MAC
4414 * addresses and undo the re-direction to manageability.
4415 * Now, frames are coming in again, but the MAC won't accept them, so
4416 * far so good. We now proceed to initialize RSS (if necessary) and
4417 * configure the Rx unit. Last, we re-enable the AV bits and continue
4418 * on our merry way.
4419 */
4420 switch (hw->mac_type) {
4421 default:
4422 /* Indicate to hardware the Address is Valid. */
4423 rar_high |= E1000_RAH_AV;
4424 break;
4425 }
4426
4427 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4428 E1000_WRITE_FLUSH();
4429 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4430 E1000_WRITE_FLUSH();
1da177e4
LT		 4431}
4432
120a5d0d
JB		 4433/**
4434 * e1000_write_vfta - Writes a value to the specified offset in the VLAN filter table.
4435 * @hw: Struct containing variables accessed by shared code
4436 * @offset: Offset in VLAN filer table to write
4437 * @value: Value to write into VLAN filter table
4438 */
64798845 4439void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
1da177e4 4440{
120a5d0d
JB		 4441 u32 temp;
4442
4443 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
4444 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
4445 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4446 E1000_WRITE_FLUSH();
4447 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4448 E1000_WRITE_FLUSH();
4449 } else {
4450 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4451 E1000_WRITE_FLUSH();
4452 }
1da177e4
LT		 4453}
4454
120a5d0d
JB		 4455/**
4456 * e1000_clear_vfta - Clears the VLAN filer table
4457 * @hw: Struct containing variables accessed by shared code
4458 */
64798845 4459static void e1000_clear_vfta(struct e1000_hw *hw)
1da177e4 4460{
120a5d0d
JB		 4461 u32 offset;
4462 u32 vfta_value = 0;
4463 u32 vfta_offset = 0;
4464 u32 vfta_bit_in_reg = 0;
4465
4466 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
4467 /* If the offset we want to clear is the same offset of the
4468 * manageability VLAN ID, then clear all bits except that of the
4469 * manageability unit */
4470 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
4471 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4472 E1000_WRITE_FLUSH();
4473 }
1da177e4
LT		 4474}
4475
64798845 4476static s32 e1000_id_led_init(struct e1000_hw *hw)
1da177e4 4477{
120a5d0d
JB		 4478 u32 ledctl;
4479 const u32 ledctl_mask = 0x000000FF;
4480 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
4481 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
4482 u16 eeprom_data, i, temp;
4483 const u16 led_mask = 0x0F;
4484
675ad473 4485 e_dbg("e1000_id_led_init");
120a5d0d
JB		 4486
4487 if (hw->mac_type < e1000_82540) {
4488 /* Nothing to do */
4489 return E1000_SUCCESS;
4490 }
4491
4492 ledctl = er32(LEDCTL);
4493 hw->ledctl_default = ledctl;
4494 hw->ledctl_mode1 = hw->ledctl_default;
4495 hw->ledctl_mode2 = hw->ledctl_default;
4496
4497 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
675ad473 4498 e_dbg("EEPROM Read Error\n");
120a5d0d
JB		 4499 return -E1000_ERR_EEPROM;
4500 }
4501
4502 if ((eeprom_data == ID_LED_RESERVED_0000) ||
4503 (eeprom_data == ID_LED_RESERVED_FFFF)) {
4504 eeprom_data = ID_LED_DEFAULT;
4505 }
4506
4507 for (i = 0; i < 4; i++) {
4508 temp = (eeprom_data >> (i << 2)) & led_mask;
4509 switch (temp) {
4510 case ID_LED_ON1_DEF2:
4511 case ID_LED_ON1_ON2:
4512 case ID_LED_ON1_OFF2:
4513 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4514 hw->ledctl_mode1 |= ledctl_on << (i << 3);
4515 break;
4516 case ID_LED_OFF1_DEF2:
4517 case ID_LED_OFF1_ON2:
4518 case ID_LED_OFF1_OFF2:
4519 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
4520 hw->ledctl_mode1 |= ledctl_off << (i << 3);
4521 break;
4522 default:
4523 /* Do nothing */
4524 break;
4525 }
4526 switch (temp) {
4527 case ID_LED_DEF1_ON2:
4528 case ID_LED_ON1_ON2:
4529 case ID_LED_OFF1_ON2:
4530 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4531 hw->ledctl_mode2 |= ledctl_on << (i << 3);
4532 break;
4533 case ID_LED_DEF1_OFF2:
4534 case ID_LED_ON1_OFF2:
4535 case ID_LED_OFF1_OFF2:
4536 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
4537 hw->ledctl_mode2 |= ledctl_off << (i << 3);
4538 break;
4539 default:
4540 /* Do nothing */
4541 break;
4542 }
4543 }
4544 return E1000_SUCCESS;
1da177e4
LT		 4545}
4546
120a5d0d
JB		 4547/**
4548 * e1000_setup_led
4549 * @hw: Struct containing variables accessed by shared code
1da177e4 4550 *
120a5d0d
JB		 4551 * Prepares SW controlable LED for use and saves the current state of the LED.
4552 */
64798845 4553s32 e1000_setup_led(struct e1000_hw *hw)
1da177e4 4554{
120a5d0d
JB		 4555 u32 ledctl;
4556 s32 ret_val = E1000_SUCCESS;
4557
675ad473 4558 e_dbg("e1000_setup_led");
120a5d0d
JB		 4559
4560 switch (hw->mac_type) {
4561 case e1000_82542_rev2_0:
4562 case e1000_82542_rev2_1:
4563 case e1000_82543:
4564 case e1000_82544:
4565 /* No setup necessary */
4566 break;
4567 case e1000_82541:
4568 case e1000_82547:
4569 case e1000_82541_rev_2:
4570 case e1000_82547_rev_2:
4571 /* Turn off PHY Smart Power Down (if enabled) */
4572 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
4573 &hw->phy_spd_default);
4574 if (ret_val)
4575 return ret_val;
4576 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4577 (u16) (hw->phy_spd_default &
4578 ~IGP01E1000_GMII_SPD));
4579 if (ret_val)
4580 return ret_val;
4581 /* Fall Through */
4582 default:
4583 if (hw->media_type == e1000_media_type_fiber) {
4584 ledctl = er32(LEDCTL);
4585 /* Save current LEDCTL settings */
4586 hw->ledctl_default = ledctl;
4587 /* Turn off LED0 */
4588 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
4589 E1000_LEDCTL_LED0_BLINK |
4590 E1000_LEDCTL_LED0_MODE_MASK);
4591 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
4592 E1000_LEDCTL_LED0_MODE_SHIFT);
4593 ew32(LEDCTL, ledctl);
4594 } else if (hw->media_type == e1000_media_type_copper)
4595 ew32(LEDCTL, hw->ledctl_mode1);
4596 break;
4597 }
4598
4599 return E1000_SUCCESS;
1da177e4
LT		 4600}
4601
120a5d0d
JB		 4602/**
4603 * e1000_cleanup_led - Restores the saved state of the SW controlable LED.
4604 * @hw: Struct containing variables accessed by shared code
4605 */
64798845 4606s32 e1000_cleanup_led(struct e1000_hw *hw)
1da177e4 4607{
120a5d0d
JB		 4608 s32 ret_val = E1000_SUCCESS;
4609
675ad473 4610 e_dbg("e1000_cleanup_led");
120a5d0d
JB		 4611
4612 switch (hw->mac_type) {
4613 case e1000_82542_rev2_0:
4614 case e1000_82542_rev2_1:
4615 case e1000_82543:
4616 case e1000_82544:
4617 /* No cleanup necessary */
4618 break;
4619 case e1000_82541:
4620 case e1000_82547:
4621 case e1000_82541_rev_2:
4622 case e1000_82547_rev_2:
4623 /* Turn on PHY Smart Power Down (if previously enabled) */
4624 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
4625 hw->phy_spd_default);
4626 if (ret_val)
4627 return ret_val;
4628 /* Fall Through */
4629 default:
4630 /* Restore LEDCTL settings */
4631 ew32(LEDCTL, hw->ledctl_default);
4632 break;
4633 }
4634
4635 return E1000_SUCCESS;
1da177e4
LT		 4636}
4637
120a5d0d
JB		 4638/**
4639 * e1000_led_on - Turns on the software controllable LED
4640 * @hw: Struct containing variables accessed by shared code
4641 */
64798845 4642s32 e1000_led_on(struct e1000_hw *hw)
1da177e4 4643{
120a5d0d
JB		 4644 u32 ctrl = er32(CTRL);
4645
675ad473 4646 e_dbg("e1000_led_on");
120a5d0d
JB		 4647
4648 switch (hw->mac_type) {
4649 case e1000_82542_rev2_0:
4650 case e1000_82542_rev2_1:
4651 case e1000_82543:
4652 /* Set SW Defineable Pin 0 to turn on the LED */
4653 ctrl |= E1000_CTRL_SWDPIN0;
4654 ctrl |= E1000_CTRL_SWDPIO0;
4655 break;
4656 case e1000_82544:
4657 if (hw->media_type == e1000_media_type_fiber) {
4658 /* Set SW Defineable Pin 0 to turn on the LED */
4659 ctrl |= E1000_CTRL_SWDPIN0;
4660 ctrl |= E1000_CTRL_SWDPIO0;
4661 } else {
4662 /* Clear SW Defineable Pin 0 to turn on the LED */
4663 ctrl &= ~E1000_CTRL_SWDPIN0;
4664 ctrl |= E1000_CTRL_SWDPIO0;
4665 }
4666 break;
4667 default:
4668 if (hw->media_type == e1000_media_type_fiber) {
4669 /* Clear SW Defineable Pin 0 to turn on the LED */
4670 ctrl &= ~E1000_CTRL_SWDPIN0;
4671 ctrl |= E1000_CTRL_SWDPIO0;
4672 } else if (hw->media_type == e1000_media_type_copper) {
4673 ew32(LEDCTL, hw->ledctl_mode2);
4674 return E1000_SUCCESS;
4675 }
4676 break;
4677 }
4678
4679 ew32(CTRL, ctrl);
4680
4681 return E1000_SUCCESS;
1da177e4
LT		 4682}
4683
120a5d0d
JB		 4684/**
4685 * e1000_led_off - Turns off the software controllable LED
4686 * @hw: Struct containing variables accessed by shared code
4687 */
64798845 4688s32 e1000_led_off(struct e1000_hw *hw)
1da177e4 4689{
120a5d0d
JB		 4690 u32 ctrl = er32(CTRL);
4691
675ad473 4692 e_dbg("e1000_led_off");
120a5d0d
JB		 4693
4694 switch (hw->mac_type) {
4695 case e1000_82542_rev2_0:
4696 case e1000_82542_rev2_1:
4697 case e1000_82543:
4698 /* Clear SW Defineable Pin 0 to turn off the LED */
4699 ctrl &= ~E1000_CTRL_SWDPIN0;
4700 ctrl |= E1000_CTRL_SWDPIO0;
4701 break;
4702 case e1000_82544:
4703 if (hw->media_type == e1000_media_type_fiber) {
4704 /* Clear SW Defineable Pin 0 to turn off the LED */
4705 ctrl &= ~E1000_CTRL_SWDPIN0;
4706 ctrl |= E1000_CTRL_SWDPIO0;
4707 } else {
4708 /* Set SW Defineable Pin 0 to turn off the LED */
4709 ctrl |= E1000_CTRL_SWDPIN0;
4710 ctrl |= E1000_CTRL_SWDPIO0;
4711 }
4712 break;
4713 default:
4714 if (hw->media_type == e1000_media_type_fiber) {
4715 /* Set SW Defineable Pin 0 to turn off the LED */
4716 ctrl |= E1000_CTRL_SWDPIN0;
4717 ctrl |= E1000_CTRL_SWDPIO0;
4718 } else if (hw->media_type == e1000_media_type_copper) {
4719 ew32(LEDCTL, hw->ledctl_mode1);
4720 return E1000_SUCCESS;
4721 }
4722 break;
4723 }
4724
4725 ew32(CTRL, ctrl);
4726
4727 return E1000_SUCCESS;
1da177e4
LT		 4728}
4729
120a5d0d
JB		 4730/**
4731 * e1000_clear_hw_cntrs - Clears all hardware statistics counters.
4732 * @hw: Struct containing variables accessed by shared code
4733 */
64798845 4734static void e1000_clear_hw_cntrs(struct e1000_hw *hw)
1da177e4 4735{
120a5d0d
JB		 4736 volatile u32 temp;
4737
4738 temp = er32(CRCERRS);
4739 temp = er32(SYMERRS);
4740 temp = er32(MPC);
4741 temp = er32(SCC);
4742 temp = er32(ECOL);
4743 temp = er32(MCC);
4744 temp = er32(LATECOL);
4745 temp = er32(COLC);
4746 temp = er32(DC);
4747 temp = er32(SEC);
4748 temp = er32(RLEC);
4749 temp = er32(XONRXC);
4750 temp = er32(XONTXC);
4751 temp = er32(XOFFRXC);
4752 temp = er32(XOFFTXC);
4753 temp = er32(FCRUC);
4754
4755 temp = er32(PRC64);
4756 temp = er32(PRC127);
4757 temp = er32(PRC255);
4758 temp = er32(PRC511);
4759 temp = er32(PRC1023);
4760 temp = er32(PRC1522);
4761
4762 temp = er32(GPRC);
4763 temp = er32(BPRC);
4764 temp = er32(MPRC);
4765 temp = er32(GPTC);
4766 temp = er32(GORCL);
4767 temp = er32(GORCH);
4768 temp = er32(GOTCL);
4769 temp = er32(GOTCH);
4770 temp = er32(RNBC);
4771 temp = er32(RUC);
4772 temp = er32(RFC);
4773 temp = er32(ROC);
4774 temp = er32(RJC);
4775 temp = er32(TORL);
4776 temp = er32(TORH);
4777 temp = er32(TOTL);
4778 temp = er32(TOTH);
4779 temp = er32(TPR);
4780 temp = er32(TPT);
4781
4782 temp = er32(PTC64);
4783 temp = er32(PTC127);
4784 temp = er32(PTC255);
4785 temp = er32(PTC511);
4786 temp = er32(PTC1023);
4787 temp = er32(PTC1522);
4788
4789 temp = er32(MPTC);
4790 temp = er32(BPTC);
4791
4792 if (hw->mac_type < e1000_82543)
4793 return;
4794
4795 temp = er32(ALGNERRC);
4796 temp = er32(RXERRC);
4797 temp = er32(TNCRS);
4798 temp = er32(CEXTERR);
4799 temp = er32(TSCTC);
4800 temp = er32(TSCTFC);
4801
4802 if (hw->mac_type <= e1000_82544)
4803 return;
4804
4805 temp = er32(MGTPRC);
4806 temp = er32(MGTPDC);
4807 temp = er32(MGTPTC);
1da177e4
LT		 4808}
4809
120a5d0d
JB		 4810/**
4811 * e1000_reset_adaptive - Resets Adaptive IFS to its default state.
4812 * @hw: Struct containing variables accessed by shared code
1da177e4
LT		 4813 *
4814 * Call this after e1000_init_hw. You may override the IFS defaults by setting
c3033b01 4815 * hw->ifs_params_forced to true. However, you must initialize hw->
1da177e4
LT		 4816 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
4817 * before calling this function.
120a5d0d 4818 */
64798845 4819void e1000_reset_adaptive(struct e1000_hw *hw)
1da177e4 4820{
675ad473 4821 e_dbg("e1000_reset_adaptive");
120a5d0d
JB		 4822
4823 if (hw->adaptive_ifs) {
4824 if (!hw->ifs_params_forced) {
4825 hw->current_ifs_val = 0;
4826 hw->ifs_min_val = IFS_MIN;
4827 hw->ifs_max_val = IFS_MAX;
4828 hw->ifs_step_size = IFS_STEP;
4829 hw->ifs_ratio = IFS_RATIO;
4830 }
4831 hw->in_ifs_mode = false;
4832 ew32(AIT, 0);
4833 } else {
675ad473 4834 e_dbg("Not in Adaptive IFS mode!\n");
120a5d0d 4835 }
1da177e4
LT		 4836}
4837
120a5d0d
JB		 4838/**
4839 * e1000_update_adaptive - update adaptive IFS
4840 * @hw: Struct containing variables accessed by shared code
4841 * @tx_packets: Number of transmits since last callback
4842 * @total_collisions: Number of collisions since last callback
4843 *
1da177e4
LT		 4844 * Called during the callback/watchdog routine to update IFS value based on
4845 * the ratio of transmits to collisions.
120a5d0d 4846 */
64798845 4847void e1000_update_adaptive(struct e1000_hw *hw)
1da177e4 4848{
675ad473 4849 e_dbg("e1000_update_adaptive");
120a5d0d
JB		 4850
4851 if (hw->adaptive_ifs) {
4852 if ((hw->collision_delta *hw->ifs_ratio) > hw->tx_packet_delta) {
4853 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
4854 hw->in_ifs_mode = true;
4855 if (hw->current_ifs_val < hw->ifs_max_val) {
4856 if (hw->current_ifs_val == 0)
4857 hw->current_ifs_val =
4858 hw->ifs_min_val;
4859 else
4860 hw->current_ifs_val +=
4861 hw->ifs_step_size;
4862 ew32(AIT, hw->current_ifs_val);
4863 }
4864 }
4865 } else {
4866 if (hw->in_ifs_mode
4867 && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
4868 hw->current_ifs_val = 0;
4869 hw->in_ifs_mode = false;
4870 ew32(AIT, 0);
4871 }
4872 }
4873 } else {
675ad473 4874 e_dbg("Not in Adaptive IFS mode!\n");
120a5d0d 4875 }
1da177e4
LT		 4876}
4877
120a5d0d
JB		 4878/**
4879 * e1000_tbi_adjust_stats
4880 * @hw: Struct containing variables accessed by shared code
4881 * @frame_len: The length of the frame in question
4882 * @mac_addr: The Ethernet destination address of the frame in question
1da177e4 4883 *
120a5d0d
JB		 4884 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
4885 */
64798845
JP		 4886void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
4887 u32 frame_len, u8 *mac_addr)
1da177e4 4888{
120a5d0d
JB		 4889 u64 carry_bit;
4890
4891 /* First adjust the frame length. */
4892 frame_len--;
4893 /* We need to adjust the statistics counters, since the hardware
4894 * counters overcount this packet as a CRC error and undercount
4895 * the packet as a good packet
4896 */
4897 /* This packet should not be counted as a CRC error. */
4898 stats->crcerrs--;
4899 /* This packet does count as a Good Packet Received. */
4900 stats->gprc++;
4901
4902 /* Adjust the Good Octets received counters */
4903 carry_bit = 0x80000000 & stats->gorcl;
4904 stats->gorcl += frame_len;
4905 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
4906 * Received Count) was one before the addition,
4907 * AND it is zero after, then we lost the carry out,
4908 * need to add one to Gorch (Good Octets Received Count High).
4909 * This could be simplified if all environments supported
4910 * 64-bit integers.
4911 */
4912 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
4913 stats->gorch++;
4914 /* Is this a broadcast or multicast? Check broadcast first,
4915 * since the test for a multicast frame will test positive on
4916 * a broadcast frame.
4917 */
4918 if ((mac_addr[0] == (u8) 0xff) && (mac_addr[1] == (u8) 0xff))
4919 /* Broadcast packet */
4920 stats->bprc++;
4921 else if (*mac_addr & 0x01)
4922 /* Multicast packet */
4923 stats->mprc++;
4924
4925 if (frame_len == hw->max_frame_size) {
4926 /* In this case, the hardware has overcounted the number of
4927 * oversize frames.
4928 */
4929 if (stats->roc > 0)
4930 stats->roc--;
4931 }
4932
4933 /* Adjust the bin counters when the extra byte put the frame in the
4934 * wrong bin. Remember that the frame_len was adjusted above.
4935 */
4936 if (frame_len == 64) {
4937 stats->prc64++;
4938 stats->prc127--;
4939 } else if (frame_len == 127) {
4940 stats->prc127++;
4941 stats->prc255--;
4942 } else if (frame_len == 255) {
4943 stats->prc255++;
4944 stats->prc511--;
4945 } else if (frame_len == 511) {
4946 stats->prc511++;
4947 stats->prc1023--;
4948 } else if (frame_len == 1023) {
4949 stats->prc1023++;
4950 stats->prc1522--;
4951 } else if (frame_len == 1522) {
4952 stats->prc1522++;
4953 }
1da177e4
LT		 4954}
4955
120a5d0d
JB		 4956/**
4957 * e1000_get_bus_info
4958 * @hw: Struct containing variables accessed by shared code
1da177e4 4959 *
120a5d0d
JB		 4960 * Gets the current PCI bus type, speed, and width of the hardware
4961 */
64798845 4962void e1000_get_bus_info(struct e1000_hw *hw)
1da177e4 4963{
120a5d0d
JB		 4964 u32 status;
4965
4966 switch (hw->mac_type) {
4967 case e1000_82542_rev2_0:
4968 case e1000_82542_rev2_1:
4969 hw->bus_type = e1000_bus_type_pci;
4970 hw->bus_speed = e1000_bus_speed_unknown;
4971 hw->bus_width = e1000_bus_width_unknown;
4972 break;
4973 default:
4974 status = er32(STATUS);
4975 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
4976 e1000_bus_type_pcix : e1000_bus_type_pci;
4977
4978 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
4979 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
4980 e1000_bus_speed_66 : e1000_bus_speed_120;
4981 } else if (hw->bus_type == e1000_bus_type_pci) {
4982 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
4983 e1000_bus_speed_66 : e1000_bus_speed_33;
4984 } else {
4985 switch (status & E1000_STATUS_PCIX_SPEED) {
4986 case E1000_STATUS_PCIX_SPEED_66:
4987 hw->bus_speed = e1000_bus_speed_66;
4988 break;
4989 case E1000_STATUS_PCIX_SPEED_100:
4990 hw->bus_speed = e1000_bus_speed_100;
4991 break;
4992 case E1000_STATUS_PCIX_SPEED_133:
4993 hw->bus_speed = e1000_bus_speed_133;
4994 break;
4995 default:
4996 hw->bus_speed = e1000_bus_speed_reserved;
4997 break;
4998 }
4999 }
5000 hw->bus_width = (status & E1000_STATUS_BUS64) ?
5001 e1000_bus_width_64 : e1000_bus_width_32;
5002 break;
5003 }
1da177e4 5004}
1da177e4 5005
120a5d0d
JB		 5006/**
5007 * e1000_write_reg_io
5008 * @hw: Struct containing variables accessed by shared code
5009 * @offset: offset to write to
5010 * @value: value to write
5011 *
1da177e4
LT		 5012 * Writes a value to one of the devices registers using port I/O (as opposed to
5013 * memory mapped I/O). Only 82544 and newer devices support port I/O.
120a5d0d 5014 */
64798845 5015static void e1000_write_reg_io(struct e1000_hw *hw, u32 offset, u32 value)
1da177e4 5016{
120a5d0d
JB		 5017 unsigned long io_addr = hw->io_base;
5018 unsigned long io_data = hw->io_base + 4;
1da177e4 5019
120a5d0d
JB		 5020 e1000_io_write(hw, io_addr, offset);
5021 e1000_io_write(hw, io_data, value);
1da177e4
LT		 5022}
5023
120a5d0d
JB		 5024/**
5025 * e1000_get_cable_length - Estimates the cable length.
5026 * @hw: Struct containing variables accessed by shared code
5027 * @min_length: The estimated minimum length
5028 * @max_length: The estimated maximum length
1da177e4
LT		 5029 *
5030 * returns: - E1000_ERR_XXX
5031 * E1000_SUCCESS
5032 *
5033 * This function always returns a ranged length (minimum & maximum).
5034 * So for M88 phy's, this function interprets the one value returned from the
5035 * register to the minimum and maximum range.
5036 * For IGP phy's, the function calculates the range by the AGC registers.
120a5d0d 5037 */
64798845
JP		 5038static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
5039 u16 *max_length)
1da177e4 5040{
120a5d0d
JB		 5041 s32 ret_val;
5042 u16 agc_value = 0;
5043 u16 i, phy_data;
5044 u16 cable_length;
5045
675ad473 5046 e_dbg("e1000_get_cable_length");
120a5d0d
JB		 5047
5048 *min_length = *max_length = 0;
5049
5050 /* Use old method for Phy older than IGP */
5051 if (hw->phy_type == e1000_phy_m88) {
5052
5053 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5054 &phy_data);
5055 if (ret_val)
5056 return ret_val;
5057 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
5058 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
5059
5060 /* Convert the enum value to ranged values */
5061 switch (cable_length) {
5062 case e1000_cable_length_50:
5063 *min_length = 0;
5064 *max_length = e1000_igp_cable_length_50;
5065 break;
5066 case e1000_cable_length_50_80:
5067 *min_length = e1000_igp_cable_length_50;
5068 *max_length = e1000_igp_cable_length_80;
5069 break;
5070 case e1000_cable_length_80_110:
5071 *min_length = e1000_igp_cable_length_80;
5072 *max_length = e1000_igp_cable_length_110;
5073 break;
5074 case e1000_cable_length_110_140:
5075 *min_length = e1000_igp_cable_length_110;
5076 *max_length = e1000_igp_cable_length_140;
5077 break;
5078 case e1000_cable_length_140:
5079 *min_length = e1000_igp_cable_length_140;
5080 *max_length = e1000_igp_cable_length_170;
5081 break;
5082 default:
5083 return -E1000_ERR_PHY;
5084 break;
5085 }
5086 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
5087 u16 cur_agc_value;
5088 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
66744500
JK		 5089 static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5090 IGP01E1000_PHY_AGC_A,
5091 IGP01E1000_PHY_AGC_B,
5092 IGP01E1000_PHY_AGC_C,
5093 IGP01E1000_PHY_AGC_D
120a5d0d
JB		 5094 };
5095 /* Read the AGC registers for all channels */
5096 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5097
5098 ret_val =
5099 e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
5100 if (ret_val)
5101 return ret_val;
5102
5103 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
5104
5105 /* Value bound check. */
5106 if ((cur_agc_value >=
5107 IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1)
5108 || (cur_agc_value == 0))
5109 return -E1000_ERR_PHY;
5110
5111 agc_value += cur_agc_value;
5112
5113 /* Update minimal AGC value. */
5114 if (min_agc_value > cur_agc_value)
5115 min_agc_value = cur_agc_value;
5116 }
5117
5118 /* Remove the minimal AGC result for length < 50m */
5119 if (agc_value <
5120 IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
5121 agc_value -= min_agc_value;
5122
5123 /* Get the average length of the remaining 3 channels */
5124 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
5125 } else {
5126 /* Get the average length of all the 4 channels. */
5127 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
5128 }
5129
5130 /* Set the range of the calculated length. */
5131 *min_length = ((e1000_igp_cable_length_table[agc_value] -
5132 IGP01E1000_AGC_RANGE) > 0) ?
5133 (e1000_igp_cable_length_table[agc_value] -
5134 IGP01E1000_AGC_RANGE) : 0;
5135 *max_length = e1000_igp_cable_length_table[agc_value] +
5136 IGP01E1000_AGC_RANGE;
5137 }
5138
5139 return E1000_SUCCESS;
1da177e4
LT		 5140}
5141
120a5d0d
JB		 5142/**
5143 * e1000_check_polarity - Check the cable polarity
5144 * @hw: Struct containing variables accessed by shared code
5145 * @polarity: output parameter : 0 - Polarity is not reversed
1da177e4
LT		 5146 * 1 - Polarity is reversed.
5147 *
5148 * returns: - E1000_ERR_XXX
5149 * E1000_SUCCESS
5150 *
025dfdaf 5151 * For phy's older than IGP, this function simply reads the polarity bit in the
1da177e4
LT		 5152 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
5153 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
5154 * return 0. If the link speed is 1000 Mbps the polarity status is in the
5155 * IGP01E1000_PHY_PCS_INIT_REG.
120a5d0d 5156 */
64798845
JP		 5157static s32 e1000_check_polarity(struct e1000_hw *hw,
5158 e1000_rev_polarity *polarity)
1da177e4 5159{
120a5d0d
JB		 5160 s32 ret_val;
5161 u16 phy_data;
5162
675ad473 5163 e_dbg("e1000_check_polarity");
120a5d0d
JB		 5164
5165 if (hw->phy_type == e1000_phy_m88) {
5166 /* return the Polarity bit in the Status register. */
5167 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5168 &phy_data);
5169 if (ret_val)
5170 return ret_val;
5171 *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
5172 M88E1000_PSSR_REV_POLARITY_SHIFT) ?
5173 e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
5174
5175 } else if (hw->phy_type == e1000_phy_igp) {
5176 /* Read the Status register to check the speed */
5177 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
5178 &phy_data);
5179 if (ret_val)
5180 return ret_val;
5181
5182 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
5183 * find the polarity status */
5184 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
5185 IGP01E1000_PSSR_SPEED_1000MBPS) {
5186
5187 /* Read the GIG initialization PCS register (0x00B4) */
5188 ret_val =
5189 e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
5190 &phy_data);
5191 if (ret_val)
5192 return ret_val;
5193
5194 /* Check the polarity bits */
5195 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
5196 e1000_rev_polarity_reversed :
5197 e1000_rev_polarity_normal;
5198 } else {
5199 /* For 10 Mbps, read the polarity bit in the status register. (for
5200 * 100 Mbps this bit is always 0) */
5201 *polarity =
5202 (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
5203 e1000_rev_polarity_reversed :
5204 e1000_rev_polarity_normal;
5205 }
5206 }
5207 return E1000_SUCCESS;
1da177e4
LT		 5208}
5209
120a5d0d
JB		 5210/**
5211 * e1000_check_downshift - Check if Downshift occurred
5212 * @hw: Struct containing variables accessed by shared code
5213 * @downshift: output parameter : 0 - No Downshift occurred.
5214 * 1 - Downshift occurred.
1da177e4
LT		 5215 *
5216 * returns: - E1000_ERR_XXX
76c224bc 5217 * E1000_SUCCESS
1da177e4 5218 *
025dfdaf 5219 * For phy's older than IGP, this function reads the Downshift bit in the Phy
1da177e4
LT		 5220 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
5221 * Link Health register. In IGP this bit is latched high, so the driver must
5222 * read it immediately after link is established.
120a5d0d 5223 */
64798845 5224static s32 e1000_check_downshift(struct e1000_hw *hw)
1da177e4 5225{
120a5d0d
JB		 5226 s32 ret_val;
5227 u16 phy_data;
5228
675ad473 5229 e_dbg("e1000_check_downshift");
120a5d0d
JB		 5230
5231 if (hw->phy_type == e1000_phy_igp) {
5232 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
5233 &phy_data);
5234 if (ret_val)
5235 return ret_val;
5236
5237 hw->speed_downgraded =
5238 (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
5239 } else if (hw->phy_type == e1000_phy_m88) {
5240 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
5241 &phy_data);
5242 if (ret_val)
5243 return ret_val;
5244
5245 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
5246 M88E1000_PSSR_DOWNSHIFT_SHIFT;
5247 }
2d7edb92 5248
120a5d0d 5249 return E1000_SUCCESS;
1da177e4
LT		 5250}
5251
120a5d0d
JB		 5252/**
5253 * e1000_config_dsp_after_link_change
5254 * @hw: Struct containing variables accessed by shared code
5255 * @link_up: was link up at the time this was called
1da177e4
LT		 5256 *
5257 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5258 * E1000_SUCCESS at any other case.
5259 *
120a5d0d
JB		 5260 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
5261 * gigabit link is achieved to improve link quality.
5262 */
1da177e4 5263
64798845 5264static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
1da177e4 5265{
120a5d0d
JB		 5266 s32 ret_val;
5267 u16 phy_data, phy_saved_data, speed, duplex, i;
66744500
JK		 5268 static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
5269 IGP01E1000_PHY_AGC_PARAM_A,
5270 IGP01E1000_PHY_AGC_PARAM_B,
5271 IGP01E1000_PHY_AGC_PARAM_C,
5272 IGP01E1000_PHY_AGC_PARAM_D
120a5d0d
JB		 5273 };
5274 u16 min_length, max_length;
5275
675ad473 5276 e_dbg("e1000_config_dsp_after_link_change");
120a5d0d
JB		 5277
5278 if (hw->phy_type != e1000_phy_igp)
5279 return E1000_SUCCESS;
5280
5281 if (link_up) {
5282 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
5283 if (ret_val) {
675ad473 5284 e_dbg("Error getting link speed and duplex\n");
120a5d0d
JB		 5285 return ret_val;
5286 }
5287
5288 if (speed == SPEED_1000) {
5289
5290 ret_val =
5291 e1000_get_cable_length(hw, &min_length,
5292 &max_length);
5293 if (ret_val)
5294 return ret_val;
5295
5296 if ((hw->dsp_config_state == e1000_dsp_config_enabled)
5297 && min_length >= e1000_igp_cable_length_50) {
5298
5299 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5300 ret_val =
5301 e1000_read_phy_reg(hw,
5302 dsp_reg_array[i],
5303 &phy_data);
5304 if (ret_val)
5305 return ret_val;
5306
5307 phy_data &=
5308 ~IGP01E1000_PHY_EDAC_MU_INDEX;
5309
5310 ret_val =
5311 e1000_write_phy_reg(hw,
5312 dsp_reg_array
5313 [i], phy_data);
5314 if (ret_val)
5315 return ret_val;
5316 }
5317 hw->dsp_config_state =
5318 e1000_dsp_config_activated;
5319 }
5320
5321 if ((hw->ffe_config_state == e1000_ffe_config_enabled)
5322 && (min_length < e1000_igp_cable_length_50)) {
5323
5324 u16 ffe_idle_err_timeout =
5325 FFE_IDLE_ERR_COUNT_TIMEOUT_20;
5326 u32 idle_errs = 0;
5327
5328 /* clear previous idle error counts */
5329 ret_val =
5330 e1000_read_phy_reg(hw, PHY_1000T_STATUS,
5331 &phy_data);
5332 if (ret_val)
5333 return ret_val;
5334
5335 for (i = 0; i < ffe_idle_err_timeout; i++) {
5336 udelay(1000);
5337 ret_val =
5338 e1000_read_phy_reg(hw,
5339 PHY_1000T_STATUS,
5340 &phy_data);
5341 if (ret_val)
5342 return ret_val;
5343
5344 idle_errs +=
5345 (phy_data &
5346 SR_1000T_IDLE_ERROR_CNT);
5347 if (idle_errs >
5348 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT)
5349 {
5350 hw->ffe_config_state =
5351 e1000_ffe_config_active;
5352
5353 ret_val =
5354 e1000_write_phy_reg(hw,
5355 IGP01E1000_PHY_DSP_FFE,
5356 IGP01E1000_PHY_DSP_FFE_CM_CP);
5357 if (ret_val)
5358 return ret_val;
5359 break;
5360 }
5361
5362 if (idle_errs)
5363 ffe_idle_err_timeout =
5364 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
5365 }
5366 }
5367 }
5368 } else {
5369 if (hw->dsp_config_state == e1000_dsp_config_activated) {
5370 /* Save off the current value of register 0x2F5B to be restored at
5371 * the end of the routines. */
5372 ret_val =
5373 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5374
5375 if (ret_val)
5376 return ret_val;
5377
5378 /* Disable the PHY transmitter */
5379 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5380
5381 if (ret_val)
5382 return ret_val;
5383
5384 mdelay(20);
5385
5386 ret_val = e1000_write_phy_reg(hw, 0x0000,
5387 IGP01E1000_IEEE_FORCE_GIGA);
5388 if (ret_val)
5389 return ret_val;
5390 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
5391 ret_val =
5392 e1000_read_phy_reg(hw, dsp_reg_array[i],
5393 &phy_data);
5394 if (ret_val)
5395 return ret_val;
5396
5397 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
5398 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
5399
5400 ret_val =
5401 e1000_write_phy_reg(hw, dsp_reg_array[i],
5402 phy_data);
5403 if (ret_val)
5404 return ret_val;
5405 }
5406
5407 ret_val = e1000_write_phy_reg(hw, 0x0000,
5408 IGP01E1000_IEEE_RESTART_AUTONEG);
5409 if (ret_val)
5410 return ret_val;
5411
5412 mdelay(20);
5413
5414 /* Now enable the transmitter */
5415 ret_val =
5416 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5417
5418 if (ret_val)
5419 return ret_val;
5420
5421 hw->dsp_config_state = e1000_dsp_config_enabled;
5422 }
5423
5424 if (hw->ffe_config_state == e1000_ffe_config_active) {
5425 /* Save off the current value of register 0x2F5B to be restored at
5426 * the end of the routines. */
5427 ret_val =
5428 e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
5429
5430 if (ret_val)
5431 return ret_val;
5432
5433 /* Disable the PHY transmitter */
5434 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
5435
5436 if (ret_val)
5437 return ret_val;
5438
5439 mdelay(20);
5440
5441 ret_val = e1000_write_phy_reg(hw, 0x0000,
5442 IGP01E1000_IEEE_FORCE_GIGA);
5443 if (ret_val)
5444 return ret_val;
5445 ret_val =
5446 e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
5447 IGP01E1000_PHY_DSP_FFE_DEFAULT);
5448 if (ret_val)
5449 return ret_val;
5450
5451 ret_val = e1000_write_phy_reg(hw, 0x0000,
5452 IGP01E1000_IEEE_RESTART_AUTONEG);
5453 if (ret_val)
5454 return ret_val;
5455
5456 mdelay(20);
5457
5458 /* Now enable the transmitter */
5459 ret_val =
5460 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
5461
5462 if (ret_val)
5463 return ret_val;
5464
5465 hw->ffe_config_state = e1000_ffe_config_enabled;
5466 }
5467 }
5468 return E1000_SUCCESS;
1da177e4
LT		 5469}
5470
120a5d0d
JB		 5471/**
5472 * e1000_set_phy_mode - Set PHY to class A mode
5473 * @hw: Struct containing variables accessed by shared code
5474 *
1da177e4
LT		 5475 * Assumes the following operations will follow to enable the new class mode.
5476 * 1. Do a PHY soft reset
5477 * 2. Restart auto-negotiation or force link.
120a5d0d 5478 */
64798845 5479static s32 e1000_set_phy_mode(struct e1000_hw *hw)
1da177e4 5480{
120a5d0d
JB		 5481 s32 ret_val;
5482 u16 eeprom_data;
5483
675ad473 5484 e_dbg("e1000_set_phy_mode");
120a5d0d
JB		 5485
5486 if ((hw->mac_type == e1000_82545_rev_3) &&
5487 (hw->media_type == e1000_media_type_copper)) {
5488 ret_val =
5489 e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1,
5490 &eeprom_data);
5491 if (ret_val) {
5492 return ret_val;
5493 }
5494
5495 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
5496 (eeprom_data & EEPROM_PHY_CLASS_A)) {
5497 ret_val =
5498 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT,
5499 0x000B);
5500 if (ret_val)
5501 return ret_val;
5502 ret_val =
5503 e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL,
5504 0x8104);
5505 if (ret_val)
5506 return ret_val;
5507
5508 hw->phy_reset_disable = false;
5509 }
5510 }
5511
5512 return E1000_SUCCESS;
1da177e4
LT		 5513}
5514
120a5d0d
JB		 5515/**
5516 * e1000_set_d3_lplu_state - set d3 link power state
5517 * @hw: Struct containing variables accessed by shared code
5518 * @active: true to enable lplu false to disable lplu.
1da177e4
LT		 5519 *
5520 * This function sets the lplu state according to the active flag. When
5521 * activating lplu this function also disables smart speed and vise versa.
120a5d0d 5522 * lplu will not be activated unless the device autonegotiation advertisement
1da177e4 5523 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
1da177e4
LT		 5524 *
5525 * returns: - E1000_ERR_PHY if fail to read/write the PHY
5526 * E1000_SUCCESS at any other case.
120a5d0d 5527 */
64798845 5528static s32 e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1da177e4 5529{
120a5d0d
JB		 5530 s32 ret_val;
5531 u16 phy_data;
675ad473 5532 e_dbg("e1000_set_d3_lplu_state");
120a5d0d
JB		 5533
5534 if (hw->phy_type != e1000_phy_igp)
5535 return E1000_SUCCESS;
5536
5537 /* During driver activity LPLU should not be used or it will attain link
5538 * from the lowest speeds starting from 10Mbps. The capability is used for
5539 * Dx transitions and states */
5540 if (hw->mac_type == e1000_82541_rev_2
5541 || hw->mac_type == e1000_82547_rev_2) {
5542 ret_val =
5543 e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
5544 if (ret_val)
5545 return ret_val;
5546 }
5547
5548 if (!active) {
5549 if (hw->mac_type == e1000_82541_rev_2 ||
5550 hw->mac_type == e1000_82547_rev_2) {
5551 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
5552 ret_val =
5553 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5554 phy_data);
5555 if (ret_val)
5556 return ret_val;
5557 }
5558
5559 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
5560 * Dx states where the power conservation is most important. During
5561 * driver activity we should enable SmartSpeed, so performance is
5562 * maintained. */
5563 if (hw->smart_speed == e1000_smart_speed_on) {
5564 ret_val =
5565 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5566 &phy_data);
5567 if (ret_val)
5568 return ret_val;
5569
5570 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
5571 ret_val =
5572 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5573 phy_data);
5574 if (ret_val)
5575 return ret_val;
5576 } else if (hw->smart_speed == e1000_smart_speed_off) {
5577 ret_val =
5578 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5579 &phy_data);
5580 if (ret_val)
5581 return ret_val;
5582
5583 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5584 ret_val =
5585 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5586 phy_data);
5587 if (ret_val)
5588 return ret_val;
5589 }
5590 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
5591 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL)
5592 || (hw->autoneg_advertised ==
5593 AUTONEG_ADVERTISE_10_100_ALL)) {
5594
5595 if (hw->mac_type == e1000_82541_rev_2 ||
5596 hw->mac_type == e1000_82547_rev_2) {
5597 phy_data |= IGP01E1000_GMII_FLEX_SPD;
5598 ret_val =
5599 e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
5600 phy_data);
5601 if (ret_val)
5602 return ret_val;
5603 }
5604
5605 /* When LPLU is enabled we should disable SmartSpeed */
5606 ret_val =
5607 e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5608 &phy_data);
5609 if (ret_val)
5610 return ret_val;
5611
5612 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
5613 ret_val =
5614 e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
5615 phy_data);
5616 if (ret_val)
5617 return ret_val;
5618
5619 }
5620 return E1000_SUCCESS;
2d7edb92
MC		 5621}
5622
120a5d0d
JB		 5623/**
5624 * e1000_set_vco_speed
5625 * @hw: Struct containing variables accessed by shared code
2d7edb92 5626 *
120a5d0d
JB		 5627 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
5628 */
1532ecea 5629static s32 e1000_set_vco_speed(struct e1000_hw *hw)
2d7edb92 5630{
120a5d0d
JB		 5631 s32 ret_val;
5632 u16 default_page = 0;
5633 u16 phy_data;
2d7edb92 5634
675ad473 5635 e_dbg("e1000_set_vco_speed");
2d7edb92 5636
120a5d0d
JB		 5637 switch (hw->mac_type) {
5638 case e1000_82545_rev_3:
5639 case e1000_82546_rev_3:
5640 break;
5641 default:
5642 return E1000_SUCCESS;
5643 }
1da177e4 5644
120a5d0d 5645 /* Set PHY register 30, page 5, bit 8 to 0 */
1da177e4 5646
120a5d0d
JB		 5647 ret_val =
5648 e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
5649 if (ret_val)
5650 return ret_val;
1da177e4 5651
120a5d0d
JB		 5652 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
5653 if (ret_val)
5654 return ret_val;
1da177e4 5655
120a5d0d
JB		 5656 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5657 if (ret_val)
5658 return ret_val;
1da177e4 5659
120a5d0d
JB		 5660 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
5661 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5662 if (ret_val)
5663 return ret_val;
1da177e4 5664
120a5d0d 5665 /* Set PHY register 30, page 4, bit 11 to 1 */
1da177e4 5666
120a5d0d
JB		 5667 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
5668 if (ret_val)
5669 return ret_val;
1da177e4 5670
120a5d0d
JB		 5671 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
5672 if (ret_val)
5673 return ret_val;
1da177e4 5674
120a5d0d
JB		 5675 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
5676 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
5677 if (ret_val)
5678 return ret_val;
1da177e4 5679
120a5d0d
JB		 5680 ret_val =
5681 e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
5682 if (ret_val)
5683 return ret_val;
1da177e4 5684
120a5d0d 5685 return E1000_SUCCESS;
1da177e4
LT		 5686}
5687
1da177e4 5688
120a5d0d
JB		 5689/**
5690 * e1000_enable_mng_pass_thru - check for bmc pass through
5691 * @hw: Struct containing variables accessed by shared code
2d7edb92 5692 *
120a5d0d 5693 * Verifies the hardware needs to allow ARPs to be processed by the host
c3033b01 5694 * returns: - true/false
120a5d0d 5695 */
64798845 5696u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw)
2d7edb92 5697{
120a5d0d
JB		 5698 u32 manc;
5699
5700 if (hw->asf_firmware_present) {
5701 manc = er32(MANC);
5702
5703 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
5704 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
5705 return false;
5706 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
5707 return true;
5708 }
5709 return false;
2d7edb92
MC		 5710}
5711
64798845 5712static s32 e1000_polarity_reversal_workaround(struct e1000_hw *hw)
2d7edb92 5713{
120a5d0d
JB		 5714 s32 ret_val;
5715 u16 mii_status_reg;
5716 u16 i;
5717
5718 /* Polarity reversal workaround for forced 10F/10H links. */
5719
5720 /* Disable the transmitter on the PHY */
5721
5722 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5723 if (ret_val)
5724 return ret_val;
5725 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
5726 if (ret_val)
5727 return ret_val;
5728
5729 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5730 if (ret_val)
5731 return ret_val;
5732
5733 /* This loop will early-out if the NO link condition has been met. */
5734 for (i = PHY_FORCE_TIME; i > 0; i--) {
5735 /* Read the MII Status Register and wait for Link Status bit
5736 * to be clear.
5737 */
5738
5739 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5740 if (ret_val)
5741 return ret_val;
5742
5743 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5744 if (ret_val)
5745 return ret_val;
5746
5747 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
5748 break;
5749 mdelay(100);
5750 }
5751
5752 /* Recommended delay time after link has been lost */
5753 mdelay(1000);
5754
5755 /* Now we will re-enable th transmitter on the PHY */
5756
5757 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
5758 if (ret_val)
5759 return ret_val;
5760 mdelay(50);
5761 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
5762 if (ret_val)
5763 return ret_val;
5764 mdelay(50);
5765 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
5766 if (ret_val)
5767 return ret_val;
5768 mdelay(50);
5769 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
5770 if (ret_val)
5771 return ret_val;
5772
5773 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
5774 if (ret_val)
5775 return ret_val;
5776
5777 /* This loop will early-out if the link condition has been met. */
5778 for (i = PHY_FORCE_TIME; i > 0; i--) {
5779 /* Read the MII Status Register and wait for Link Status bit
5780 * to be set.
5781 */
5782
5783 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5784 if (ret_val)
5785 return ret_val;
5786
5787 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
5788 if (ret_val)
5789 return ret_val;
5790
5791 if (mii_status_reg & MII_SR_LINK_STATUS)
5792 break;
5793 mdelay(100);
5794 }
5795 return E1000_SUCCESS;
1da177e4
LT		 5796}
5797
120a5d0d
JB		 5798/**
5799 * e1000_get_auto_rd_done
5800 * @hw: Struct containing variables accessed by shared code
2d7edb92 5801 *
1532ecea 5802 * Check for EEPROM Auto Read bit done.
1532ecea
JB		 5803 * returns: - E1000_ERR_RESET if fail to reset MAC
5804 * E1000_SUCCESS at any other case.
120a5d0d 5805 */
1532ecea 5806static s32 e1000_get_auto_rd_done(struct e1000_hw *hw)
2d7edb92 5807{
675ad473 5808 e_dbg("e1000_get_auto_rd_done");
120a5d0d
JB		 5809 msleep(5);
5810 return E1000_SUCCESS;
1532ecea 5811}
2d7edb92 5812
120a5d0d
JB		 5813/**
5814 * e1000_get_phy_cfg_done
5815 * @hw: Struct containing variables accessed by shared code
1532ecea 5816 *
120a5d0d 5817 * Checks if the PHY configuration is done
1532ecea
JB		 5818 * returns: - E1000_ERR_RESET if fail to reset MAC
5819 * E1000_SUCCESS at any other case.
120a5d0d 5820 */
1532ecea
JB		 5821static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
5822{
675ad473 5823 e_dbg("e1000_get_phy_cfg_done");
120a5d0d
JB		 5824 mdelay(10);
5825 return E1000_SUCCESS;
2d7edb92 5826}
Linux kernel - Deliverables
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