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[PATCH] make drivers/net/e1000/e1000_hw.c:e1000_phy_igp_get_info() static
[deliverable/linux.git] / drivers / net / e1000 / e1000_hw.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
3d41e30a 4 Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
3d41e30a 25 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 26 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27
28*******************************************************************************/
29
30/* e1000_hw.c
31 * Shared functions for accessing and configuring the MAC
32 */
33
8fc897b0 34
1da177e4
LT		 35#include "e1000_hw.h"
36
37static int32_t e1000_set_phy_type(struct e1000_hw *hw);
38static void e1000_phy_init_script(struct e1000_hw *hw);
39static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
40static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
41static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
42static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
43static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
44static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
45static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl);
46static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
47 uint16_t count);
48static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
49static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
50static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
51 uint16_t words, uint16_t *data);
52static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
53 uint16_t offset, uint16_t words,
54 uint16_t *data);
55static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
56static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
57static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd);
58static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
59 uint16_t count);
60static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
61 uint16_t phy_data);
62static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
63 uint16_t *phy_data);
64static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
65static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
66static void e1000_release_eeprom(struct e1000_hw *hw);
67static void e1000_standby_eeprom(struct e1000_hw *hw);
1da177e4
LT		 68static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
69static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
70static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
2d7edb92
MC		 71static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer);
72static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
3ad2cc67
AB		 73static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
74static int32_t e1000_check_downshift(struct e1000_hw *hw);
75static int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
76static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
77static void e1000_clear_vfta(struct e1000_hw *hw);
78static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
79static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw,
80 boolean_t link_up);
81static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
82static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
83static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
84static int32_t e1000_get_cable_length(struct e1000_hw *hw,
85 uint16_t *min_length,
86 uint16_t *max_length);
87static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
88static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
89static int32_t e1000_id_led_init(struct e1000_hw * hw);
90static void e1000_init_rx_addrs(struct e1000_hw *hw);
91static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
92static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
93static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
94static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset,
95 uint16_t words, uint16_t *data);
96static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
97static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
98static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
99
100static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset,
101 uint32_t value);
102
103#define E1000_WRITE_REG_IO(a, reg, val) \
104 e1000_write_reg_io((a), E1000_##reg, val)
cd94dd0b
AK		 105static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
106 uint16_t duplex);
6418ecc6 107static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
1da177e4 108
e4c780b1
AB		 109static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw,
110 uint32_t segment);
111static int32_t e1000_get_software_flag(struct e1000_hw *hw);
112static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
113static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
114static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
115static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
116 uint16_t words, uint16_t *data);
117static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index,
118 uint8_t* data);
119static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index,
120 uint16_t *data);
121static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
122 uint16_t *data);
123static void e1000_release_software_flag(struct e1000_hw *hw);
124static void e1000_release_software_semaphore(struct e1000_hw *hw);
125static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw,
126 uint32_t no_snoop);
127static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw,
128 uint32_t index, uint8_t byte);
129static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset,
130 uint16_t words, uint16_t *data);
131static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index,
132 uint8_t data);
133static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr,
134 uint16_t data);
135
1da177e4
LT		 136/* IGP cable length table */
137static const
138uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
139 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
140 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
141 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
142 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
143 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
144 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
145 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
146 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
147
2d7edb92
MC		 148static const
149uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
868d5309
MC		 150 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
151 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
152 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
153 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
154 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
155 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
156 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
157 104, 109, 114, 118, 121, 124};
2d7edb92 158
1da177e4
LT		 159
160/******************************************************************************
161 * Set the phy type member in the hw struct.
162 *
163 * hw - Struct containing variables accessed by shared code
164 *****************************************************************************/
165int32_t
166e1000_set_phy_type(struct e1000_hw *hw)
167{
168 DEBUGFUNC("e1000_set_phy_type");
169
8fc897b0 170 if (hw->mac_type == e1000_undefined)
2d7edb92
MC		 171 return -E1000_ERR_PHY_TYPE;
172
8fc897b0 173 switch (hw->phy_id) {
1da177e4
LT		 174 case M88E1000_E_PHY_ID:
175 case M88E1000_I_PHY_ID:
176 case M88E1011_I_PHY_ID:
2d7edb92 177 case M88E1111_I_PHY_ID:
1da177e4
LT		 178 hw->phy_type = e1000_phy_m88;
179 break;
180 case IGP01E1000_I_PHY_ID:
8fc897b0
AK		 181 if (hw->mac_type == e1000_82541 ||
182 hw->mac_type == e1000_82541_rev_2 ||
183 hw->mac_type == e1000_82547 ||
184 hw->mac_type == e1000_82547_rev_2) {
1da177e4
LT		 185 hw->phy_type = e1000_phy_igp;
186 break;
187 }
cd94dd0b
AK		 188 case IGP03E1000_E_PHY_ID:
189 hw->phy_type = e1000_phy_igp_3;
190 break;
191 case IFE_E_PHY_ID:
192 case IFE_PLUS_E_PHY_ID:
193 case IFE_C_E_PHY_ID:
194 hw->phy_type = e1000_phy_ife;
195 break;
6418ecc6
JK		 196 case GG82563_E_PHY_ID:
197 if (hw->mac_type == e1000_80003es2lan) {
198 hw->phy_type = e1000_phy_gg82563;
199 break;
200 }
1da177e4
LT		 201 /* Fall Through */
202 default:
203 /* Should never have loaded on this device */
204 hw->phy_type = e1000_phy_undefined;
205 return -E1000_ERR_PHY_TYPE;
206 }
207
208 return E1000_SUCCESS;
209}
210
8fc897b0 211
1da177e4
LT		 212/******************************************************************************
213 * IGP phy init script - initializes the GbE PHY
214 *
215 * hw - Struct containing variables accessed by shared code
216 *****************************************************************************/
217static void
218e1000_phy_init_script(struct e1000_hw *hw)
219{
220 uint32_t ret_val;
221 uint16_t phy_saved_data;
222
223 DEBUGFUNC("e1000_phy_init_script");
224
8fc897b0 225 if (hw->phy_init_script) {
1da177e4
LT		 226 msec_delay(20);
227
228 /* Save off the current value of register 0x2F5B to be restored at
229 * the end of this routine. */
230 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
231
232 /* Disabled the PHY transmitter */
233 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
234
235 msec_delay(20);
236
237 e1000_write_phy_reg(hw,0x0000,0x0140);
238
239 msec_delay(5);
240
8fc897b0 241 switch (hw->mac_type) {
1da177e4
LT		 242 case e1000_82541:
243 case e1000_82547:
244 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
245
246 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
247
248 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
249
250 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
251
252 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
253
254 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
255
256 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
257
258 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
259
260 e1000_write_phy_reg(hw, 0x2010, 0x0008);
261 break;
262
263 case e1000_82541_rev_2:
264 case e1000_82547_rev_2:
265 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
266 break;
267 default:
268 break;
269 }
270
271 e1000_write_phy_reg(hw, 0x0000, 0x3300);
272
273 msec_delay(20);
274
275 /* Now enable the transmitter */
276 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
277
8fc897b0 278 if (hw->mac_type == e1000_82547) {
1da177e4
LT		 279 uint16_t fused, fine, coarse;
280
281 /* Move to analog registers page */
282 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
283
8fc897b0 284 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1da177e4
LT		 285 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
286
287 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
288 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
289
8fc897b0 290 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1da177e4
LT		 291 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
292 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
8fc897b0 293 } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1da177e4
LT		 294 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
295
296 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
297 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
298 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
299
300 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
301 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
302 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
303 }
304 }
305 }
306}
307
308/******************************************************************************
309 * Set the mac type member in the hw struct.
310 *
311 * hw - Struct containing variables accessed by shared code
312 *****************************************************************************/
313int32_t
314e1000_set_mac_type(struct e1000_hw *hw)
315{
316 DEBUGFUNC("e1000_set_mac_type");
317
318 switch (hw->device_id) {
319 case E1000_DEV_ID_82542:
320 switch (hw->revision_id) {
321 case E1000_82542_2_0_REV_ID:
322 hw->mac_type = e1000_82542_rev2_0;
323 break;
324 case E1000_82542_2_1_REV_ID:
325 hw->mac_type = e1000_82542_rev2_1;
326 break;
327 default:
328 /* Invalid 82542 revision ID */
329 return -E1000_ERR_MAC_TYPE;
330 }
331 break;
332 case E1000_DEV_ID_82543GC_FIBER:
333 case E1000_DEV_ID_82543GC_COPPER:
334 hw->mac_type = e1000_82543;
335 break;
336 case E1000_DEV_ID_82544EI_COPPER:
337 case E1000_DEV_ID_82544EI_FIBER:
338 case E1000_DEV_ID_82544GC_COPPER:
339 case E1000_DEV_ID_82544GC_LOM:
340 hw->mac_type = e1000_82544;
341 break;
342 case E1000_DEV_ID_82540EM:
343 case E1000_DEV_ID_82540EM_LOM:
344 case E1000_DEV_ID_82540EP:
345 case E1000_DEV_ID_82540EP_LOM:
346 case E1000_DEV_ID_82540EP_LP:
347 hw->mac_type = e1000_82540;
348 break;
349 case E1000_DEV_ID_82545EM_COPPER:
350 case E1000_DEV_ID_82545EM_FIBER:
351 hw->mac_type = e1000_82545;
352 break;
353 case E1000_DEV_ID_82545GM_COPPER:
354 case E1000_DEV_ID_82545GM_FIBER:
355 case E1000_DEV_ID_82545GM_SERDES:
356 hw->mac_type = e1000_82545_rev_3;
357 break;
358 case E1000_DEV_ID_82546EB_COPPER:
359 case E1000_DEV_ID_82546EB_FIBER:
360 case E1000_DEV_ID_82546EB_QUAD_COPPER:
361 hw->mac_type = e1000_82546;
362 break;
363 case E1000_DEV_ID_82546GB_COPPER:
364 case E1000_DEV_ID_82546GB_FIBER:
365 case E1000_DEV_ID_82546GB_SERDES:
366 case E1000_DEV_ID_82546GB_PCIE:
b7ee49db
JK		 367 case E1000_DEV_ID_82546GB_QUAD_COPPER:
368 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1da177e4
LT		 369 hw->mac_type = e1000_82546_rev_3;
370 break;
371 case E1000_DEV_ID_82541EI:
372 case E1000_DEV_ID_82541EI_MOBILE:
cd94dd0b 373 case E1000_DEV_ID_82541ER_LOM:
1da177e4
LT		 374 hw->mac_type = e1000_82541;
375 break;
376 case E1000_DEV_ID_82541ER:
377 case E1000_DEV_ID_82541GI:
378 case E1000_DEV_ID_82541GI_LF:
379 case E1000_DEV_ID_82541GI_MOBILE:
380 hw->mac_type = e1000_82541_rev_2;
381 break;
382 case E1000_DEV_ID_82547EI:
cd94dd0b 383 case E1000_DEV_ID_82547EI_MOBILE:
1da177e4
LT		 384 hw->mac_type = e1000_82547;
385 break;
386 case E1000_DEV_ID_82547GI:
387 hw->mac_type = e1000_82547_rev_2;
388 break;
868d5309
MC		 389 case E1000_DEV_ID_82571EB_COPPER:
390 case E1000_DEV_ID_82571EB_FIBER:
391 case E1000_DEV_ID_82571EB_SERDES:
5881cde8 392 case E1000_DEV_ID_82571EB_QUAD_COPPER:
868d5309
MC		 393 hw->mac_type = e1000_82571;
394 break;
395 case E1000_DEV_ID_82572EI_COPPER:
396 case E1000_DEV_ID_82572EI_FIBER:
397 case E1000_DEV_ID_82572EI_SERDES:
cd94dd0b 398 case E1000_DEV_ID_82572EI:
868d5309
MC		 399 hw->mac_type = e1000_82572;
400 break;
2d7edb92
MC		 401 case E1000_DEV_ID_82573E:
402 case E1000_DEV_ID_82573E_IAMT:
868d5309 403 case E1000_DEV_ID_82573L:
2d7edb92
MC		 404 hw->mac_type = e1000_82573;
405 break;
cd94dd0b
AK		 406 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
407 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
6418ecc6
JK		 408 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
409 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
410 hw->mac_type = e1000_80003es2lan;
411 break;
cd94dd0b
AK		 412 case E1000_DEV_ID_ICH8_IGP_M_AMT:
413 case E1000_DEV_ID_ICH8_IGP_AMT:
414 case E1000_DEV_ID_ICH8_IGP_C:
415 case E1000_DEV_ID_ICH8_IFE:
416 case E1000_DEV_ID_ICH8_IGP_M:
417 hw->mac_type = e1000_ich8lan;
418 break;
1da177e4
LT		 419 default:
420 /* Should never have loaded on this device */
421 return -E1000_ERR_MAC_TYPE;
422 }
423
8fc897b0 424 switch (hw->mac_type) {
cd94dd0b
AK		 425 case e1000_ich8lan:
426 hw->swfwhw_semaphore_present = TRUE;
427 hw->asf_firmware_present = TRUE;
428 break;
6418ecc6
JK		 429 case e1000_80003es2lan:
430 hw->swfw_sync_present = TRUE;
431 /* fall through */
868d5309
MC		 432 case e1000_82571:
433 case e1000_82572:
2d7edb92
MC		 434 case e1000_82573:
435 hw->eeprom_semaphore_present = TRUE;
436 /* fall through */
1da177e4
LT		 437 case e1000_82541:
438 case e1000_82547:
439 case e1000_82541_rev_2:
440 case e1000_82547_rev_2:
441 hw->asf_firmware_present = TRUE;
442 break;
443 default:
444 break;
445 }
446
447 return E1000_SUCCESS;
448}
449
450/*****************************************************************************
451 * Set media type and TBI compatibility.
452 *
453 * hw - Struct containing variables accessed by shared code
454 * **************************************************************************/
455void
456e1000_set_media_type(struct e1000_hw *hw)
457{
458 uint32_t status;
459
460 DEBUGFUNC("e1000_set_media_type");
461
8fc897b0 462 if (hw->mac_type != e1000_82543) {
1da177e4
LT		 463 /* tbi_compatibility is only valid on 82543 */
464 hw->tbi_compatibility_en = FALSE;
465 }
466
467 switch (hw->device_id) {
468 case E1000_DEV_ID_82545GM_SERDES:
469 case E1000_DEV_ID_82546GB_SERDES:
868d5309
MC		 470 case E1000_DEV_ID_82571EB_SERDES:
471 case E1000_DEV_ID_82572EI_SERDES:
6418ecc6 472 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1da177e4
LT		 473 hw->media_type = e1000_media_type_internal_serdes;
474 break;
475 default:
3893d547
MC		 476 switch (hw->mac_type) {
477 case e1000_82542_rev2_0:
478 case e1000_82542_rev2_1:
479 hw->media_type = e1000_media_type_fiber;
480 break;
cd94dd0b 481 case e1000_ich8lan:
3893d547
MC		 482 case e1000_82573:
483 /* The STATUS_TBIMODE bit is reserved or reused for the this
484 * device.
485 */
486 hw->media_type = e1000_media_type_copper;
487 break;
488 default:
1da177e4 489 status = E1000_READ_REG(hw, STATUS);
3893d547 490 if (status & E1000_STATUS_TBIMODE) {
1da177e4
LT		 491 hw->media_type = e1000_media_type_fiber;
492 /* tbi_compatibility not valid on fiber */
493 hw->tbi_compatibility_en = FALSE;
494 } else {
495 hw->media_type = e1000_media_type_copper;
496 }
3893d547 497 break;
1da177e4
LT		 498 }
499 }
500}
501
502/******************************************************************************
503 * Reset the transmit and receive units; mask and clear all interrupts.
504 *
505 * hw - Struct containing variables accessed by shared code
506 *****************************************************************************/
507int32_t
508e1000_reset_hw(struct e1000_hw *hw)
509{
510 uint32_t ctrl;
511 uint32_t ctrl_ext;
512 uint32_t icr;
513 uint32_t manc;
514 uint32_t led_ctrl;
2d7edb92
MC		 515 uint32_t timeout;
516 uint32_t extcnf_ctrl;
517 int32_t ret_val;
1da177e4
LT		 518
519 DEBUGFUNC("e1000_reset_hw");
520
521 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
8fc897b0 522 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 523 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
524 e1000_pci_clear_mwi(hw);
525 }
526
8fc897b0 527 if (hw->bus_type == e1000_bus_type_pci_express) {
2d7edb92
MC		 528 /* Prevent the PCI-E bus from sticking if there is no TLP connection
529 * on the last TLP read/write transaction when MAC is reset.
530 */
8fc897b0 531 if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
2d7edb92
MC		 532 DEBUGOUT("PCI-E Master disable polling has failed.\n");
533 }
534 }
535
1da177e4
LT		 536 /* Clear interrupt mask to stop board from generating interrupts */
537 DEBUGOUT("Masking off all interrupts\n");
538 E1000_WRITE_REG(hw, IMC, 0xffffffff);
539
540 /* Disable the Transmit and Receive units. Then delay to allow
541 * any pending transactions to complete before we hit the MAC with
542 * the global reset.
543 */
544 E1000_WRITE_REG(hw, RCTL, 0);
545 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
546 E1000_WRITE_FLUSH(hw);
547
548 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
549 hw->tbi_compatibility_on = FALSE;
550
551 /* Delay to allow any outstanding PCI transactions to complete before
552 * resetting the device
553 */
554 msec_delay(10);
555
556 ctrl = E1000_READ_REG(hw, CTRL);
557
558 /* Must reset the PHY before resetting the MAC */
8fc897b0 559 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2d7edb92 560 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1da177e4
LT		 561 msec_delay(5);
562 }
563
2d7edb92
MC		 564 /* Must acquire the MDIO ownership before MAC reset.
565 * Ownership defaults to firmware after a reset. */
8fc897b0 566 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 567 timeout = 10;
568
569 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
570 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
571
572 do {
573 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
574 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
575
8fc897b0 576 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
2d7edb92
MC		 577 break;
578 else
579 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
580
581 msec_delay(2);
582 timeout--;
8fc897b0 583 } while (timeout);
2d7edb92
MC		 584 }
585
cd94dd0b
AK		 586 /* Workaround for ICH8 bit corruption issue in FIFO memory */
587 if (hw->mac_type == e1000_ich8lan) {
588 /* Set Tx and Rx buffer allocation to 8k apiece. */
589 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
590 /* Set Packet Buffer Size to 16k. */
591 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
592 }
593
1da177e4
LT		 594 /* Issue a global reset to the MAC. This will reset the chip's
595 * transmit, receive, DMA, and link units. It will not effect
596 * the current PCI configuration. The global reset bit is self-
597 * clearing, and should clear within a microsecond.
598 */
599 DEBUGOUT("Issuing a global reset to MAC\n");
600
8fc897b0 601 switch (hw->mac_type) {
1da177e4
LT		 602 case e1000_82544:
603 case e1000_82540:
604 case e1000_82545:
605 case e1000_82546:
606 case e1000_82541:
607 case e1000_82541_rev_2:
608 /* These controllers can't ack the 64-bit write when issuing the
609 * reset, so use IO-mapping as a workaround to issue the reset */
610 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
611 break;
612 case e1000_82545_rev_3:
613 case e1000_82546_rev_3:
614 /* Reset is performed on a shadow of the control register */
615 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
616 break;
cd94dd0b
AK		 617 case e1000_ich8lan:
618 if (!hw->phy_reset_disable &&
619 e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
620 /* e1000_ich8lan PHY HW reset requires MAC CORE reset
621 * at the same time to make sure the interface between
622 * MAC and the external PHY is reset.
623 */
624 ctrl |= E1000_CTRL_PHY_RST;
625 }
626
627 e1000_get_software_flag(hw);
628 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
629 msec_delay(5);
630 break;
1da177e4
LT		 631 default:
632 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
633 break;
634 }
635
636 /* After MAC reset, force reload of EEPROM to restore power-on settings to
637 * device. Later controllers reload the EEPROM automatically, so just wait
638 * for reload to complete.
639 */
8fc897b0 640 switch (hw->mac_type) {
1da177e4
LT		 641 case e1000_82542_rev2_0:
642 case e1000_82542_rev2_1:
643 case e1000_82543:
644 case e1000_82544:
645 /* Wait for reset to complete */
646 udelay(10);
647 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
648 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
649 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
650 E1000_WRITE_FLUSH(hw);
651 /* Wait for EEPROM reload */
652 msec_delay(2);
653 break;
654 case e1000_82541:
655 case e1000_82541_rev_2:
656 case e1000_82547:
657 case e1000_82547_rev_2:
658 /* Wait for EEPROM reload */
659 msec_delay(20);
660 break;
2d7edb92 661 case e1000_82573:
fd803241
JK		 662 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
663 udelay(10);
664 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
665 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
666 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
667 E1000_WRITE_FLUSH(hw);
668 }
2d7edb92 669 /* fall through */
868d5309
MC		 670 case e1000_82571:
671 case e1000_82572:
cd94dd0b 672 case e1000_ich8lan:
6418ecc6 673 case e1000_80003es2lan:
2d7edb92 674 ret_val = e1000_get_auto_rd_done(hw);
8fc897b0 675 if (ret_val)
2d7edb92
MC		 676 /* We don't want to continue accessing MAC registers. */
677 return ret_val;
678 break;
1da177e4
LT		 679 default:
680 /* Wait for EEPROM reload (it happens automatically) */
681 msec_delay(5);
682 break;
683 }
684
685 /* Disable HW ARPs on ASF enabled adapters */
8fc897b0 686 if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
1da177e4
LT		 687 manc = E1000_READ_REG(hw, MANC);
688 manc &= ~(E1000_MANC_ARP_EN);
689 E1000_WRITE_REG(hw, MANC, manc);
690 }
691
8fc897b0 692 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 693 e1000_phy_init_script(hw);
694
695 /* Configure activity LED after PHY reset */
696 led_ctrl = E1000_READ_REG(hw, LEDCTL);
697 led_ctrl &= IGP_ACTIVITY_LED_MASK;
698 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
699 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
700 }
701
702 /* Clear interrupt mask to stop board from generating interrupts */
703 DEBUGOUT("Masking off all interrupts\n");
704 E1000_WRITE_REG(hw, IMC, 0xffffffff);
705
706 /* Clear any pending interrupt events. */
707 icr = E1000_READ_REG(hw, ICR);
708
709 /* If MWI was previously enabled, reenable it. */
8fc897b0
AK		 710 if (hw->mac_type == e1000_82542_rev2_0) {
711 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1da177e4
LT		 712 e1000_pci_set_mwi(hw);
713 }
714
cd94dd0b
AK		 715 if (hw->mac_type == e1000_ich8lan) {
716 uint32_t kab = E1000_READ_REG(hw, KABGTXD);
717 kab |= E1000_KABGTXD_BGSQLBIAS;
718 E1000_WRITE_REG(hw, KABGTXD, kab);
719 }
720
1da177e4
LT		 721 return E1000_SUCCESS;
722}
723
724/******************************************************************************
725 * Performs basic configuration of the adapter.
726 *
727 * hw - Struct containing variables accessed by shared code
728 *
729 * Assumes that the controller has previously been reset and is in a
730 * post-reset uninitialized state. Initializes the receive address registers,
731 * multicast table, and VLAN filter table. Calls routines to setup link
732 * configuration and flow control settings. Clears all on-chip counters. Leaves
733 * the transmit and receive units disabled and uninitialized.
734 *****************************************************************************/
735int32_t
736e1000_init_hw(struct e1000_hw *hw)
737{
738 uint32_t ctrl;
739 uint32_t i;
740 int32_t ret_val;
741 uint16_t pcix_cmd_word;
742 uint16_t pcix_stat_hi_word;
743 uint16_t cmd_mmrbc;
744 uint16_t stat_mmrbc;
2d7edb92 745 uint32_t mta_size;
6418ecc6 746 uint32_t reg_data;
b7ee49db 747 uint32_t ctrl_ext;
2d7edb92 748
1da177e4
LT		 749 DEBUGFUNC("e1000_init_hw");
750
7820d428
JK		 751 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
752 if (hw->mac_type == e1000_ich8lan) {
753 reg_data = E1000_READ_REG(hw, TARC0);
754 reg_data |= 0x30000000;
755 E1000_WRITE_REG(hw, TARC0, reg_data);
756
757 reg_data = E1000_READ_REG(hw, STATUS);
758 reg_data &= ~0x80000000;
759 E1000_WRITE_REG(hw, STATUS, reg_data);
760 }
761
1da177e4
LT		 762 /* Initialize Identification LED */
763 ret_val = e1000_id_led_init(hw);
8fc897b0 764 if (ret_val) {
1da177e4
LT		 765 DEBUGOUT("Error Initializing Identification LED\n");
766 return ret_val;
767 }
768
769 /* Set the media type and TBI compatibility */
770 e1000_set_media_type(hw);
771
772 /* Disabling VLAN filtering. */
773 DEBUGOUT("Initializing the IEEE VLAN\n");
cd94dd0b
AK		 774 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
775 if (hw->mac_type != e1000_ich8lan) {
776 if (hw->mac_type < e1000_82545_rev_3)
777 E1000_WRITE_REG(hw, VET, 0);
778 e1000_clear_vfta(hw);
779 }
1da177e4
LT		 780
781 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
8fc897b0 782 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 783 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
784 e1000_pci_clear_mwi(hw);
785 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
786 E1000_WRITE_FLUSH(hw);
787 msec_delay(5);
788 }
789
790 /* Setup the receive address. This involves initializing all of the Receive
791 * Address Registers (RARs 0 - 15).
792 */
793 e1000_init_rx_addrs(hw);
794
795 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
8fc897b0 796 if (hw->mac_type == e1000_82542_rev2_0) {
1da177e4
LT		 797 E1000_WRITE_REG(hw, RCTL, 0);
798 E1000_WRITE_FLUSH(hw);
799 msec_delay(1);
8fc897b0 800 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1da177e4
LT		 801 e1000_pci_set_mwi(hw);
802 }
803
804 /* Zero out the Multicast HASH table */
805 DEBUGOUT("Zeroing the MTA\n");
2d7edb92 806 mta_size = E1000_MC_TBL_SIZE;
cd94dd0b
AK		 807 if (hw->mac_type == e1000_ich8lan)
808 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
8fc897b0 809 for (i = 0; i < mta_size; i++) {
1da177e4 810 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 811 /* use write flush to prevent Memory Write Block (MWB) from
812 * occuring when accessing our register space */
813 E1000_WRITE_FLUSH(hw);
814 }
1da177e4
LT		 815
816 /* Set the PCI priority bit correctly in the CTRL register. This
817 * determines if the adapter gives priority to receives, or if it
2d7edb92
MC		 818 * gives equal priority to transmits and receives. Valid only on
819 * 82542 and 82543 silicon.
1da177e4 820 */
8fc897b0 821 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
1da177e4
LT		 822 ctrl = E1000_READ_REG(hw, CTRL);
823 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
824 }
825
8fc897b0 826 switch (hw->mac_type) {
1da177e4
LT		 827 case e1000_82545_rev_3:
828 case e1000_82546_rev_3:
829 break;
830 default:
831 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
8fc897b0 832 if (hw->bus_type == e1000_bus_type_pcix) {
1da177e4
LT		 833 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
834 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
835 &pcix_stat_hi_word);
836 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
837 PCIX_COMMAND_MMRBC_SHIFT;
838 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
839 PCIX_STATUS_HI_MMRBC_SHIFT;
8fc897b0 840 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1da177e4 841 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
8fc897b0 842 if (cmd_mmrbc > stat_mmrbc) {
1da177e4
LT		 843 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
844 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
845 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
846 &pcix_cmd_word);
847 }
848 }
849 break;
850 }
851
cd94dd0b
AK		 852 /* More time needed for PHY to initialize */
853 if (hw->mac_type == e1000_ich8lan)
854 msec_delay(15);
855
1da177e4
LT		 856 /* Call a subroutine to configure the link and setup flow control. */
857 ret_val = e1000_setup_link(hw);
858
859 /* Set the transmit descriptor write-back policy */
8fc897b0 860 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 861 ctrl = E1000_READ_REG(hw, TXDCTL);
862 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
2d7edb92
MC		 863 switch (hw->mac_type) {
864 default:
865 break;
868d5309
MC		 866 case e1000_82571:
867 case e1000_82572:
2d7edb92 868 case e1000_82573:
cd94dd0b 869 case e1000_ich8lan:
6418ecc6 870 case e1000_80003es2lan:
2d7edb92
MC		 871 ctrl |= E1000_TXDCTL_COUNT_DESC;
872 break;
873 }
1da177e4
LT		 874 E1000_WRITE_REG(hw, TXDCTL, ctrl);
875 }
876
2d7edb92 877 if (hw->mac_type == e1000_82573) {
76c224bc 878 e1000_enable_tx_pkt_filtering(hw);
2d7edb92
MC		 879 }
880
868d5309
MC		 881 switch (hw->mac_type) {
882 default:
883 break;
6418ecc6
JK		 884 case e1000_80003es2lan:
885 /* Enable retransmit on late collisions */
886 reg_data = E1000_READ_REG(hw, TCTL);
887 reg_data |= E1000_TCTL_RTLC;
888 E1000_WRITE_REG(hw, TCTL, reg_data);
889
890 /* Configure Gigabit Carry Extend Padding */
891 reg_data = E1000_READ_REG(hw, TCTL_EXT);
892 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
893 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
894 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
895
896 /* Configure Transmit Inter-Packet Gap */
897 reg_data = E1000_READ_REG(hw, TIPG);
898 reg_data &= ~E1000_TIPG_IPGT_MASK;
899 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
900 E1000_WRITE_REG(hw, TIPG, reg_data);
901
902 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
903 reg_data &= ~0x00100000;
904 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
905 /* Fall through */
868d5309 906 case e1000_82571:
a7990ba6 907 case e1000_82572:
cd94dd0b 908 case e1000_ich8lan:
868d5309 909 ctrl = E1000_READ_REG(hw, TXDCTL1);
6418ecc6 910 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
8fc897b0 911 if (hw->mac_type >= e1000_82571)
6418ecc6 912 ctrl |= E1000_TXDCTL_COUNT_DESC;
868d5309
MC		 913 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
914 break;
915 }
916
917
868d5309
MC		 918 if (hw->mac_type == e1000_82573) {
919 uint32_t gcr = E1000_READ_REG(hw, GCR);
920 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
921 E1000_WRITE_REG(hw, GCR, gcr);
922 }
2d7edb92 923
1da177e4
LT		 924 /* Clear all of the statistics registers (clear on read). It is
925 * important that we do this after we have tried to establish link
926 * because the symbol error count will increment wildly if there
927 * is no link.
928 */
929 e1000_clear_hw_cntrs(hw);
930
cd94dd0b
AK		 931 /* ICH8 No-snoop bits are opposite polarity.
932 * Set to snoop by default after reset. */
933 if (hw->mac_type == e1000_ich8lan)
934 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
935
b7ee49db
JK		 936 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
937 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
938 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
939 /* Relaxed ordering must be disabled to avoid a parity
940 * error crash in a PCI slot. */
941 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
942 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
943 }
944
1da177e4
LT		 945 return ret_val;
946}
947
948/******************************************************************************
949 * Adjust SERDES output amplitude based on EEPROM setting.
950 *
951 * hw - Struct containing variables accessed by shared code.
952 *****************************************************************************/
953static int32_t
954e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
955{
956 uint16_t eeprom_data;
957 int32_t ret_val;
958
959 DEBUGFUNC("e1000_adjust_serdes_amplitude");
960
8fc897b0 961 if (hw->media_type != e1000_media_type_internal_serdes)
1da177e4
LT		 962 return E1000_SUCCESS;
963
8fc897b0 964 switch (hw->mac_type) {
1da177e4
LT		 965 case e1000_82545_rev_3:
966 case e1000_82546_rev_3:
967 break;
968 default:
969 return E1000_SUCCESS;
970 }
971
972 ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
973 if (ret_val) {
974 return ret_val;
975 }
976
8fc897b0 977 if (eeprom_data != EEPROM_RESERVED_WORD) {
1da177e4 978 /* Adjust SERDES output amplitude only. */
76c224bc 979 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1da177e4 980 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
8fc897b0 981 if (ret_val)
1da177e4
LT		 982 return ret_val;
983 }
984
985 return E1000_SUCCESS;
986}
987
988/******************************************************************************
989 * Configures flow control and link settings.
990 *
991 * hw - Struct containing variables accessed by shared code
992 *
993 * Determines which flow control settings to use. Calls the apropriate media-
994 * specific link configuration function. Configures the flow control settings.
995 * Assuming the adapter has a valid link partner, a valid link should be
996 * established. Assumes the hardware has previously been reset and the
997 * transmitter and receiver are not enabled.
998 *****************************************************************************/
999int32_t
1000e1000_setup_link(struct e1000_hw *hw)
1001{
1002 uint32_t ctrl_ext;
1003 int32_t ret_val;
1004 uint16_t eeprom_data;
1005
1006 DEBUGFUNC("e1000_setup_link");
1007
526f9957
JK		 1008 /* In the case of the phy reset being blocked, we already have a link.
1009 * We do not have to set it up again. */
1010 if (e1000_check_phy_reset_block(hw))
1011 return E1000_SUCCESS;
1012
1da177e4
LT		 1013 /* Read and store word 0x0F of the EEPROM. This word contains bits
1014 * that determine the hardware's default PAUSE (flow control) mode,
1015 * a bit that determines whether the HW defaults to enabling or
1016 * disabling auto-negotiation, and the direction of the
1017 * SW defined pins. If there is no SW over-ride of the flow
1018 * control setting, then the variable hw->fc will
1019 * be initialized based on a value in the EEPROM.
1020 */
fd803241
JK		 1021 if (hw->fc == e1000_fc_default) {
1022 switch (hw->mac_type) {
cd94dd0b 1023 case e1000_ich8lan:
fd803241 1024 case e1000_82573:
1da177e4 1025 hw->fc = e1000_fc_full;
fd803241
JK		 1026 break;
1027 default:
1028 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1029 1, &eeprom_data);
1030 if (ret_val) {
1031 DEBUGOUT("EEPROM Read Error\n");
1032 return -E1000_ERR_EEPROM;
1033 }
1034 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1035 hw->fc = e1000_fc_none;
1036 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1037 EEPROM_WORD0F_ASM_DIR)
1038 hw->fc = e1000_fc_tx_pause;
1039 else
1040 hw->fc = e1000_fc_full;
1041 break;
1042 }
1da177e4
LT		 1043 }
1044
1045 /* We want to save off the original Flow Control configuration just
1046 * in case we get disconnected and then reconnected into a different
1047 * hub or switch with different Flow Control capabilities.
1048 */
8fc897b0 1049 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 1050 hw->fc &= (~e1000_fc_tx_pause);
1051
8fc897b0 1052 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1da177e4
LT		 1053 hw->fc &= (~e1000_fc_rx_pause);
1054
1055 hw->original_fc = hw->fc;
1056
1057 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1058
1059 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1060 * polarity value for the SW controlled pins, and setup the
1061 * Extended Device Control reg with that info.
1062 * This is needed because one of the SW controlled pins is used for
1063 * signal detection. So this should be done before e1000_setup_pcs_link()
1064 * or e1000_phy_setup() is called.
1065 */
497fce5e 1066 if (hw->mac_type == e1000_82543) {
8fc897b0
AK		 1067 ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1068 1, &eeprom_data);
1069 if (ret_val) {
1070 DEBUGOUT("EEPROM Read Error\n");
1071 return -E1000_ERR_EEPROM;
1072 }
1da177e4
LT		 1073 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1074 SWDPIO__EXT_SHIFT);
1075 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1076 }
1077
1078 /* Call the necessary subroutine to configure the link. */
1079 ret_val = (hw->media_type == e1000_media_type_copper) ?
1080 e1000_setup_copper_link(hw) :
1081 e1000_setup_fiber_serdes_link(hw);
1082
1083 /* Initialize the flow control address, type, and PAUSE timer
1084 * registers to their default values. This is done even if flow
1085 * control is disabled, because it does not hurt anything to
1086 * initialize these registers.
1087 */
1088 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1089
cd94dd0b
AK		 1090 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1091 if (hw->mac_type != e1000_ich8lan) {
1092 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1093 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1094 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1095 }
2d7edb92 1096
1da177e4
LT		 1097 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1098
1099 /* Set the flow control receive threshold registers. Normally,
1100 * these registers will be set to a default threshold that may be
1101 * adjusted later by the driver's runtime code. However, if the
1102 * ability to transmit pause frames in not enabled, then these
1103 * registers will be set to 0.
1104 */
8fc897b0 1105 if (!(hw->fc & e1000_fc_tx_pause)) {
1da177e4
LT		 1106 E1000_WRITE_REG(hw, FCRTL, 0);
1107 E1000_WRITE_REG(hw, FCRTH, 0);
1108 } else {
1109 /* We need to set up the Receive Threshold high and low water marks
1110 * as well as (optionally) enabling the transmission of XON frames.
1111 */
8fc897b0 1112 if (hw->fc_send_xon) {
1da177e4
LT		 1113 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1114 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1115 } else {
1116 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1117 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1118 }
1119 }
1120 return ret_val;
1121}
1122
1123/******************************************************************************
1124 * Sets up link for a fiber based or serdes based adapter
1125 *
1126 * hw - Struct containing variables accessed by shared code
1127 *
1128 * Manipulates Physical Coding Sublayer functions in order to configure
1129 * link. Assumes the hardware has been previously reset and the transmitter
1130 * and receiver are not enabled.
1131 *****************************************************************************/
1132static int32_t
1133e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1134{
1135 uint32_t ctrl;
1136 uint32_t status;
1137 uint32_t txcw = 0;
1138 uint32_t i;
1139 uint32_t signal = 0;
1140 int32_t ret_val;
1141
1142 DEBUGFUNC("e1000_setup_fiber_serdes_link");
1143
868d5309
MC		 1144 /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1145 * until explicitly turned off or a power cycle is performed. A read to
1146 * the register does not indicate its status. Therefore, we ensure
1147 * loopback mode is disabled during initialization.
1148 */
1149 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572)
1150 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1151
1da177e4
LT		 1152 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
1153 * set when the optics detect a signal. On older adapters, it will be
1154 * cleared when there is a signal. This applies to fiber media only.
1155 * If we're on serdes media, adjust the output amplitude to value set in
1156 * the EEPROM.
1157 */
1158 ctrl = E1000_READ_REG(hw, CTRL);
8fc897b0 1159 if (hw->media_type == e1000_media_type_fiber)
1da177e4
LT		 1160 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1161
1162 ret_val = e1000_adjust_serdes_amplitude(hw);
8fc897b0 1163 if (ret_val)
1da177e4
LT		 1164 return ret_val;
1165
1166 /* Take the link out of reset */
1167 ctrl &= ~(E1000_CTRL_LRST);
1168
1169 /* Adjust VCO speed to improve BER performance */
1170 ret_val = e1000_set_vco_speed(hw);
8fc897b0 1171 if (ret_val)
1da177e4
LT		 1172 return ret_val;
1173
1174 e1000_config_collision_dist(hw);
1175
1176 /* Check for a software override of the flow control settings, and setup
1177 * the device accordingly. If auto-negotiation is enabled, then software
1178 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1179 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
1180 * auto-negotiation is disabled, then software will have to manually
1181 * configure the two flow control enable bits in the CTRL register.
1182 *
1183 * The possible values of the "fc" parameter are:
1184 * 0: Flow control is completely disabled
1185 * 1: Rx flow control is enabled (we can receive pause frames, but
1186 * not send pause frames).
1187 * 2: Tx flow control is enabled (we can send pause frames but we do
1188 * not support receiving pause frames).
1189 * 3: Both Rx and TX flow control (symmetric) are enabled.
1190 */
1191 switch (hw->fc) {
1192 case e1000_fc_none:
1193 /* Flow control is completely disabled by a software over-ride. */
1194 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1195 break;
1196 case e1000_fc_rx_pause:
1197 /* RX Flow control is enabled and TX Flow control is disabled by a
1198 * software over-ride. Since there really isn't a way to advertise
1199 * that we are capable of RX Pause ONLY, we will advertise that we
1200 * support both symmetric and asymmetric RX PAUSE. Later, we will
1201 * disable the adapter's ability to send PAUSE frames.
1202 */
1203 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1204 break;
1205 case e1000_fc_tx_pause:
1206 /* TX Flow control is enabled, and RX Flow control is disabled, by a
1207 * software over-ride.
1208 */
1209 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1210 break;
1211 case e1000_fc_full:
1212 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1213 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1214 break;
1215 default:
1216 DEBUGOUT("Flow control param set incorrectly\n");
1217 return -E1000_ERR_CONFIG;
1218 break;
1219 }
1220
1221 /* Since auto-negotiation is enabled, take the link out of reset (the link
1222 * will be in reset, because we previously reset the chip). This will
1223 * restart auto-negotiation. If auto-neogtiation is successful then the
1224 * link-up status bit will be set and the flow control enable bits (RFCE
1225 * and TFCE) will be set according to their negotiated value.
1226 */
1227 DEBUGOUT("Auto-negotiation enabled\n");
1228
1229 E1000_WRITE_REG(hw, TXCW, txcw);
1230 E1000_WRITE_REG(hw, CTRL, ctrl);
1231 E1000_WRITE_FLUSH(hw);
1232
1233 hw->txcw = txcw;
1234 msec_delay(1);
1235
1236 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1237 * indication in the Device Status Register. Time-out if a link isn't
1238 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
1239 * less than 500 milliseconds even if the other end is doing it in SW).
1240 * For internal serdes, we just assume a signal is present, then poll.
1241 */
8fc897b0 1242 if (hw->media_type == e1000_media_type_internal_serdes ||
1da177e4
LT		 1243 (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1244 DEBUGOUT("Looking for Link\n");
8fc897b0 1245 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1da177e4
LT		 1246 msec_delay(10);
1247 status = E1000_READ_REG(hw, STATUS);
8fc897b0 1248 if (status & E1000_STATUS_LU) break;
1da177e4 1249 }
8fc897b0 1250 if (i == (LINK_UP_TIMEOUT / 10)) {
1da177e4
LT		 1251 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1252 hw->autoneg_failed = 1;
1253 /* AutoNeg failed to achieve a link, so we'll call
1254 * e1000_check_for_link. This routine will force the link up if
1255 * we detect a signal. This will allow us to communicate with
1256 * non-autonegotiating link partners.
1257 */
1258 ret_val = e1000_check_for_link(hw);
8fc897b0 1259 if (ret_val) {
1da177e4
LT		 1260 DEBUGOUT("Error while checking for link\n");
1261 return ret_val;
1262 }
1263 hw->autoneg_failed = 0;
1264 } else {
1265 hw->autoneg_failed = 0;
1266 DEBUGOUT("Valid Link Found\n");
1267 }
1268 } else {
1269 DEBUGOUT("No Signal Detected\n");
1270 }
1271 return E1000_SUCCESS;
1272}
1273
1274/******************************************************************************
2d7edb92 1275* Make sure we have a valid PHY and change PHY mode before link setup.
1da177e4
LT		 1276*
1277* hw - Struct containing variables accessed by shared code
1278******************************************************************************/
1279static int32_t
2d7edb92 1280e1000_copper_link_preconfig(struct e1000_hw *hw)
1da177e4
LT		 1281{
1282 uint32_t ctrl;
1da177e4 1283 int32_t ret_val;
1da177e4
LT		 1284 uint16_t phy_data;
1285
2d7edb92 1286 DEBUGFUNC("e1000_copper_link_preconfig");
1da177e4
LT		 1287
1288 ctrl = E1000_READ_REG(hw, CTRL);
1289 /* With 82543, we need to force speed and duplex on the MAC equal to what
1290 * the PHY speed and duplex configuration is. In addition, we need to
1291 * perform a hardware reset on the PHY to take it out of reset.
1292 */
8fc897b0 1293 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 1294 ctrl |= E1000_CTRL_SLU;
1295 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1296 E1000_WRITE_REG(hw, CTRL, ctrl);
1297 } else {
1298 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1299 E1000_WRITE_REG(hw, CTRL, ctrl);
2d7edb92 1300 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 1301 if (ret_val)
2d7edb92 1302 return ret_val;
1da177e4
LT		 1303 }
1304
1305 /* Make sure we have a valid PHY */
1306 ret_val = e1000_detect_gig_phy(hw);
8fc897b0 1307 if (ret_val) {
1da177e4
LT		 1308 DEBUGOUT("Error, did not detect valid phy.\n");
1309 return ret_val;
1310 }
1311 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1312
1313 /* Set PHY to class A mode (if necessary) */
1314 ret_val = e1000_set_phy_mode(hw);
8fc897b0 1315 if (ret_val)
1da177e4
LT		 1316 return ret_val;
1317
8fc897b0 1318 if ((hw->mac_type == e1000_82545_rev_3) ||
1da177e4
LT		 1319 (hw->mac_type == e1000_82546_rev_3)) {
1320 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1321 phy_data |= 0x00000008;
1322 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1323 }
1324
8fc897b0
AK		 1325 if (hw->mac_type <= e1000_82543 ||
1326 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1327 hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1da177e4
LT		 1328 hw->phy_reset_disable = FALSE;
1329
2d7edb92
MC		 1330 return E1000_SUCCESS;
1331}
1da177e4 1332
1da177e4 1333
2d7edb92
MC		 1334/********************************************************************
1335* Copper link setup for e1000_phy_igp series.
1336*
1337* hw - Struct containing variables accessed by shared code
1338*********************************************************************/
1339static int32_t
1340e1000_copper_link_igp_setup(struct e1000_hw *hw)
1341{
1342 uint32_t led_ctrl;
1343 int32_t ret_val;
1344 uint16_t phy_data;
1da177e4 1345
2d7edb92 1346 DEBUGFUNC("e1000_copper_link_igp_setup");
1da177e4 1347
2d7edb92
MC		 1348 if (hw->phy_reset_disable)
1349 return E1000_SUCCESS;
76c224bc 1350
2d7edb92
MC		 1351 ret_val = e1000_phy_reset(hw);
1352 if (ret_val) {
1353 DEBUGOUT("Error Resetting the PHY\n");
1354 return ret_val;
1355 }
1da177e4 1356
8fc897b0 1357 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2d7edb92 1358 msec_delay(15);
cd94dd0b 1359 if (hw->mac_type != e1000_ich8lan) {
2d7edb92
MC		 1360 /* Configure activity LED after PHY reset */
1361 led_ctrl = E1000_READ_REG(hw, LEDCTL);
1362 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1363 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1364 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
cd94dd0b 1365 }
1da177e4 1366
c9c1b834
JK		 1367 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1368 if (hw->phy_type == e1000_phy_igp) {
1369 /* disable lplu d3 during driver init */
1370 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1371 if (ret_val) {
1372 DEBUGOUT("Error Disabling LPLU D3\n");
1373 return ret_val;
1374 }
2d7edb92 1375 }
1da177e4 1376
2d7edb92
MC		 1377 /* disable lplu d0 during driver init */
1378 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1379 if (ret_val) {
1380 DEBUGOUT("Error Disabling LPLU D0\n");
1381 return ret_val;
1382 }
1383 /* Configure mdi-mdix settings */
1384 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1385 if (ret_val)
1386 return ret_val;
1da177e4 1387
2d7edb92
MC		 1388 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1389 hw->dsp_config_state = e1000_dsp_config_disabled;
1390 /* Force MDI for earlier revs of the IGP PHY */
1391 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
1392 hw->mdix = 1;
1da177e4 1393
2d7edb92
MC		 1394 } else {
1395 hw->dsp_config_state = e1000_dsp_config_enabled;
1396 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1da177e4 1397
2d7edb92
MC		 1398 switch (hw->mdix) {
1399 case 1:
1400 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1401 break;
1402 case 2:
1403 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1404 break;
1405 case 0:
1406 default:
1407 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1408 break;
1409 }
1410 }
1411 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 1412 if (ret_val)
2d7edb92 1413 return ret_val;
1da177e4 1414
2d7edb92 1415 /* set auto-master slave resolution settings */
8fc897b0 1416 if (hw->autoneg) {
2d7edb92 1417 e1000_ms_type phy_ms_setting = hw->master_slave;
1da177e4 1418
8fc897b0 1419 if (hw->ffe_config_state == e1000_ffe_config_active)
2d7edb92 1420 hw->ffe_config_state = e1000_ffe_config_enabled;
1da177e4 1421
8fc897b0 1422 if (hw->dsp_config_state == e1000_dsp_config_activated)
2d7edb92 1423 hw->dsp_config_state = e1000_dsp_config_enabled;
1da177e4 1424
2d7edb92
MC		 1425 /* when autonegotiation advertisment is only 1000Mbps then we
1426 * should disable SmartSpeed and enable Auto MasterSlave
1427 * resolution as hardware default. */
8fc897b0 1428 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2d7edb92 1429 /* Disable SmartSpeed */
8fc897b0
AK		 1430 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1431 &phy_data);
1432 if (ret_val)
1da177e4 1433 return ret_val;
2d7edb92 1434 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
8fc897b0
AK		 1435 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1436 phy_data);
1437 if (ret_val)
1da177e4 1438 return ret_val;
2d7edb92
MC		 1439 /* Set auto Master/Slave resolution process */
1440 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1441 if (ret_val)
2d7edb92
MC		 1442 return ret_val;
1443 phy_data &= ~CR_1000T_MS_ENABLE;
1444 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1445 if (ret_val)
2d7edb92
MC		 1446 return ret_val;
1447 }
1da177e4 1448
2d7edb92 1449 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
8fc897b0 1450 if (ret_val)
2d7edb92 1451 return ret_val;
1da177e4 1452
2d7edb92
MC		 1453 /* load defaults for future use */
1454 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1455 ((phy_data & CR_1000T_MS_VALUE) ?
1456 e1000_ms_force_master :
1457 e1000_ms_force_slave) :
1458 e1000_ms_auto;
1da177e4 1459
2d7edb92
MC		 1460 switch (phy_ms_setting) {
1461 case e1000_ms_force_master:
1462 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1463 break;
1464 case e1000_ms_force_slave:
1465 phy_data |= CR_1000T_MS_ENABLE;
1466 phy_data &= ~(CR_1000T_MS_VALUE);
1467 break;
1468 case e1000_ms_auto:
1469 phy_data &= ~CR_1000T_MS_ENABLE;
1470 default:
1471 break;
1472 }
1473 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
8fc897b0 1474 if (ret_val)
2d7edb92 1475 return ret_val;
2b02893e 1476 }
1da177e4 1477
2b02893e 1478 return E1000_SUCCESS;
2d7edb92 1479}
1da177e4 1480
6418ecc6
JK		 1481/********************************************************************
1482* Copper link setup for e1000_phy_gg82563 series.
1483*
1484* hw - Struct containing variables accessed by shared code
1485*********************************************************************/
1486static int32_t
1487e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1488{
1489 int32_t ret_val;
1490 uint16_t phy_data;
1491 uint32_t reg_data;
1492
1493 DEBUGFUNC("e1000_copper_link_ggp_setup");
1494
8fc897b0 1495 if (!hw->phy_reset_disable) {
76c224bc 1496
6418ecc6
JK		 1497 /* Enable CRS on TX for half-duplex operation. */
1498 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1499 &phy_data);
8fc897b0 1500 if (ret_val)
6418ecc6
JK		 1501 return ret_val;
1502
1503 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1504 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1505 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1506
1507 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1508 phy_data);
8fc897b0 1509 if (ret_val)
6418ecc6
JK		 1510 return ret_val;
1511
1512 /* Options:
1513 * MDI/MDI-X = 0 (default)
1514 * 0 - Auto for all speeds
1515 * 1 - MDI mode
1516 * 2 - MDI-X mode
1517 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1518 */
1519 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1520 if (ret_val)
6418ecc6
JK		 1521 return ret_val;
1522
1523 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1524
1525 switch (hw->mdix) {
1526 case 1:
1527 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
1528 break;
1529 case 2:
1530 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1531 break;
1532 case 0:
1533 default:
1534 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1535 break;
1536 }
1537
1538 /* Options:
1539 * disable_polarity_correction = 0 (default)
1540 * Automatic Correction for Reversed Cable Polarity
1541 * 0 - Disabled
1542 * 1 - Enabled
1543 */
1544 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
8fc897b0 1545 if (hw->disable_polarity_correction == 1)
6418ecc6
JK		 1546 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1547 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1548
8fc897b0 1549 if (ret_val)
6418ecc6
JK		 1550 return ret_val;
1551
1552 /* SW Reset the PHY so all changes take effect */
1553 ret_val = e1000_phy_reset(hw);
1554 if (ret_val) {
1555 DEBUGOUT("Error Resetting the PHY\n");
1556 return ret_val;
1557 }
1558 } /* phy_reset_disable */
1559
1560 if (hw->mac_type == e1000_80003es2lan) {
1561 /* Bypass RX and TX FIFO's */
1562 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1563 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
1564 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1565 if (ret_val)
1566 return ret_val;
1567
1568 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1569 if (ret_val)
1570 return ret_val;
1571
1572 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1573 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1574
1575 if (ret_val)
1576 return ret_val;
1577
1578 reg_data = E1000_READ_REG(hw, CTRL_EXT);
1579 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1580 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1581
1582 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1583 &phy_data);
1584 if (ret_val)
1585 return ret_val;
1586
1587 /* Do not init these registers when the HW is in IAMT mode, since the
1588 * firmware will have already initialized them. We only initialize
1589 * them if the HW is not in IAMT mode.
1590 */
1591 if (e1000_check_mng_mode(hw) == FALSE) {
1592 /* Enable Electrical Idle on the PHY */
1593 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1594 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1595 phy_data);
1596 if (ret_val)
1597 return ret_val;
1598
1599 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1600 &phy_data);
1601 if (ret_val)
1602 return ret_val;
1603
cd94dd0b 1604 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
6418ecc6
JK		 1605 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1606 phy_data);
8fc897b0 1607
6418ecc6
JK		 1608 if (ret_val)
1609 return ret_val;
1610 }
1611
1612 /* Workaround: Disable padding in Kumeran interface in the MAC
1613 * and in the PHY to avoid CRC errors.
1614 */
1615 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1616 &phy_data);
1617 if (ret_val)
1618 return ret_val;
1619 phy_data |= GG82563_ICR_DIS_PADDING;
1620 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1621 phy_data);
1622 if (ret_val)
1623 return ret_val;
1624 }
1625
1626 return E1000_SUCCESS;
1627}
1da177e4 1628
2d7edb92
MC		 1629/********************************************************************
1630* Copper link setup for e1000_phy_m88 series.
1631*
1632* hw - Struct containing variables accessed by shared code
1633*********************************************************************/
1634static int32_t
1635e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1636{
1637 int32_t ret_val;
1638 uint16_t phy_data;
1da177e4 1639
2d7edb92 1640 DEBUGFUNC("e1000_copper_link_mgp_setup");
1da177e4 1641
8fc897b0 1642 if (hw->phy_reset_disable)
2d7edb92 1643 return E1000_SUCCESS;
76c224bc 1644
2d7edb92
MC		 1645 /* Enable CRS on TX. This must be set for half-duplex operation. */
1646 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 1647 if (ret_val)
2d7edb92 1648 return ret_val;
1da177e4 1649
2d7edb92 1650 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1da177e4 1651
2d7edb92
MC		 1652 /* Options:
1653 * MDI/MDI-X = 0 (default)
1654 * 0 - Auto for all speeds
1655 * 1 - MDI mode
1656 * 2 - MDI-X mode
1657 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1658 */
1659 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1da177e4 1660
2d7edb92
MC		 1661 switch (hw->mdix) {
1662 case 1:
1663 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1664 break;
1665 case 2:
1666 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1667 break;
1668 case 3:
1669 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1670 break;
1671 case 0:
1672 default:
1673 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1674 break;
1675 }
1676
1677 /* Options:
1678 * disable_polarity_correction = 0 (default)
1679 * Automatic Correction for Reversed Cable Polarity
1680 * 0 - Disabled
1681 * 1 - Enabled
1da177e4 1682 */
2d7edb92 1683 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
8fc897b0 1684 if (hw->disable_polarity_correction == 1)
2d7edb92 1685 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
ee04022a
AK		 1686 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1687 if (ret_val)
2d7edb92
MC		 1688 return ret_val;
1689
2d7edb92 1690 if (hw->phy_revision < M88E1011_I_REV_4) {
ee04022a
AK		 1691 /* Force TX_CLK in the Extended PHY Specific Control Register
1692 * to 25MHz clock.
1693 */
1694 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1695 if (ret_val)
1696 return ret_val;
1697
1698 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1699
1700 if ((hw->phy_revision == E1000_REVISION_2) &&
1701 (hw->phy_id == M88E1111_I_PHY_ID)) {
1702 /* Vidalia Phy, set the downshift counter to 5x */
1703 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1704 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1705 ret_val = e1000_write_phy_reg(hw,
1706 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1707 if (ret_val)
1708 return ret_val;
1709 } else {
1710 /* Configure Master and Slave downshift values */
1711 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
2d7edb92 1712 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
ee04022a 1713 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
2d7edb92 1714 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
ee04022a
AK		 1715 ret_val = e1000_write_phy_reg(hw,
1716 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1717 if (ret_val)
1718 return ret_val;
1719 }
2d7edb92 1720 }
1da177e4 1721
2d7edb92
MC		 1722 /* SW Reset the PHY so all changes take effect */
1723 ret_val = e1000_phy_reset(hw);
8fc897b0 1724 if (ret_val) {
2d7edb92
MC		 1725 DEBUGOUT("Error Resetting the PHY\n");
1726 return ret_val;
1da177e4
LT		 1727 }
1728
2d7edb92 1729 return E1000_SUCCESS;
1da177e4
LT		 1730}
1731
2d7edb92
MC		 1732/********************************************************************
1733* Setup auto-negotiation and flow control advertisements,
1734* and then perform auto-negotiation.
1da177e4
LT		 1735*
1736* hw - Struct containing variables accessed by shared code
2d7edb92
MC		 1737*********************************************************************/
1738static int32_t
1739e1000_copper_link_autoneg(struct e1000_hw *hw)
1da177e4
LT		 1740{
1741 int32_t ret_val;
2d7edb92 1742 uint16_t phy_data;
1da177e4 1743
2d7edb92 1744 DEBUGFUNC("e1000_copper_link_autoneg");
1da177e4 1745
2d7edb92
MC		 1746 /* Perform some bounds checking on the hw->autoneg_advertised
1747 * parameter. If this variable is zero, then set it to the default.
1748 */
1749 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1750
1751 /* If autoneg_advertised is zero, we assume it was not defaulted
1752 * by the calling code so we set to advertise full capability.
1753 */
8fc897b0 1754 if (hw->autoneg_advertised == 0)
2d7edb92
MC		 1755 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1756
cd94dd0b
AK		 1757 /* IFE phy only supports 10/100 */
1758 if (hw->phy_type == e1000_phy_ife)
1759 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1760
2d7edb92
MC		 1761 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1762 ret_val = e1000_phy_setup_autoneg(hw);
8fc897b0 1763 if (ret_val) {
2d7edb92
MC		 1764 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1765 return ret_val;
1766 }
1767 DEBUGOUT("Restarting Auto-Neg\n");
1768
1769 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1770 * the Auto Neg Restart bit in the PHY control register.
1771 */
1772 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 1773 if (ret_val)
1da177e4
LT		 1774 return ret_val;
1775
2d7edb92
MC		 1776 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1777 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 1778 if (ret_val)
1da177e4
LT		 1779 return ret_val;
1780
2d7edb92
MC		 1781 /* Does the user want to wait for Auto-Neg to complete here, or
1782 * check at a later time (for example, callback routine).
1783 */
8fc897b0 1784 if (hw->wait_autoneg_complete) {
2d7edb92 1785 ret_val = e1000_wait_autoneg(hw);
8fc897b0 1786 if (ret_val) {
2d7edb92
MC		 1787 DEBUGOUT("Error while waiting for autoneg to complete\n");
1788 return ret_val;
1789 }
1790 }
1791
1792 hw->get_link_status = TRUE;
1793
1794 return E1000_SUCCESS;
1795}
1796
2d7edb92
MC		 1797/******************************************************************************
1798* Config the MAC and the PHY after link is up.
1799* 1) Set up the MAC to the current PHY speed/duplex
1800* if we are on 82543. If we
1801* are on newer silicon, we only need to configure
1802* collision distance in the Transmit Control Register.
1803* 2) Set up flow control on the MAC to that established with
1804* the link partner.
76c224bc 1805* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2d7edb92
MC		 1806*
1807* hw - Struct containing variables accessed by shared code
1808******************************************************************************/
1809static int32_t
1810e1000_copper_link_postconfig(struct e1000_hw *hw)
1811{
1812 int32_t ret_val;
1813 DEBUGFUNC("e1000_copper_link_postconfig");
76c224bc 1814
8fc897b0 1815 if (hw->mac_type >= e1000_82544) {
2d7edb92
MC		 1816 e1000_config_collision_dist(hw);
1817 } else {
1818 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 1819 if (ret_val) {
2d7edb92
MC		 1820 DEBUGOUT("Error configuring MAC to PHY settings\n");
1821 return ret_val;
1822 }
1823 }
1824 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 1825 if (ret_val) {
2d7edb92
MC		 1826 DEBUGOUT("Error Configuring Flow Control\n");
1827 return ret_val;
1828 }
1829
1830 /* Config DSP to improve Giga link quality */
8fc897b0 1831 if (hw->phy_type == e1000_phy_igp) {
2d7edb92 1832 ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
8fc897b0 1833 if (ret_val) {
2d7edb92
MC		 1834 DEBUGOUT("Error Configuring DSP after link up\n");
1835 return ret_val;
1836 }
1837 }
76c224bc 1838
2d7edb92
MC		 1839 return E1000_SUCCESS;
1840}
1841
1842/******************************************************************************
1843* Detects which PHY is present and setup the speed and duplex
1844*
1845* hw - Struct containing variables accessed by shared code
1846******************************************************************************/
1847static int32_t
1848e1000_setup_copper_link(struct e1000_hw *hw)
1849{
1850 int32_t ret_val;
1851 uint16_t i;
1852 uint16_t phy_data;
6418ecc6 1853 uint16_t reg_data;
2d7edb92
MC		 1854
1855 DEBUGFUNC("e1000_setup_copper_link");
1856
cd94dd0b
AK		 1857 switch (hw->mac_type) {
1858 case e1000_80003es2lan:
1859 case e1000_ich8lan:
1860 /* Set the mac to wait the maximum time between each
1861 * iteration and increase the max iterations when
1862 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1863 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1864 if (ret_val)
1865 return ret_val;
1866 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1867 if (ret_val)
1868 return ret_val;
1869 reg_data |= 0x3F;
1870 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1871 if (ret_val)
1872 return ret_val;
1873 default:
1874 break;
1875 }
1876
2d7edb92
MC		 1877 /* Check if it is a valid PHY and set PHY mode if necessary. */
1878 ret_val = e1000_copper_link_preconfig(hw);
8fc897b0 1879 if (ret_val)
2d7edb92
MC		 1880 return ret_val;
1881
6418ecc6
JK		 1882 switch (hw->mac_type) {
1883 case e1000_80003es2lan:
cd94dd0b
AK		 1884 /* Kumeran registers are written-only */
1885 reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
6418ecc6
JK		 1886 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
1887 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
1888 reg_data);
1889 if (ret_val)
1890 return ret_val;
1891 break;
1892 default:
1893 break;
1894 }
1895
2d7edb92 1896 if (hw->phy_type == e1000_phy_igp ||
cd94dd0b 1897 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92
MC		 1898 hw->phy_type == e1000_phy_igp_2) {
1899 ret_val = e1000_copper_link_igp_setup(hw);
8fc897b0 1900 if (ret_val)
2d7edb92
MC		 1901 return ret_val;
1902 } else if (hw->phy_type == e1000_phy_m88) {
1903 ret_val = e1000_copper_link_mgp_setup(hw);
8fc897b0 1904 if (ret_val)
2d7edb92 1905 return ret_val;
6418ecc6
JK		 1906 } else if (hw->phy_type == e1000_phy_gg82563) {
1907 ret_val = e1000_copper_link_ggp_setup(hw);
8fc897b0 1908 if (ret_val)
6418ecc6 1909 return ret_val;
2d7edb92
MC		 1910 }
1911
8fc897b0 1912 if (hw->autoneg) {
76c224bc
AK		 1913 /* Setup autoneg and flow control advertisement
1914 * and perform autonegotiation */
2d7edb92 1915 ret_val = e1000_copper_link_autoneg(hw);
8fc897b0 1916 if (ret_val)
76c224bc 1917 return ret_val;
2d7edb92
MC		 1918 } else {
1919 /* PHY will be set to 10H, 10F, 100H,or 100F
1920 * depending on value from forced_speed_duplex. */
1921 DEBUGOUT("Forcing speed and duplex\n");
1922 ret_val = e1000_phy_force_speed_duplex(hw);
8fc897b0 1923 if (ret_val) {
2d7edb92
MC		 1924 DEBUGOUT("Error Forcing Speed and Duplex\n");
1925 return ret_val;
1926 }
1927 }
1928
1929 /* Check link status. Wait up to 100 microseconds for link to become
1930 * valid.
1931 */
8fc897b0 1932 for (i = 0; i < 10; i++) {
2d7edb92 1933 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 1934 if (ret_val)
2d7edb92
MC		 1935 return ret_val;
1936 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 1937 if (ret_val)
2d7edb92
MC		 1938 return ret_val;
1939
8fc897b0 1940 if (phy_data & MII_SR_LINK_STATUS) {
2d7edb92
MC		 1941 /* Config the MAC and PHY after link is up */
1942 ret_val = e1000_copper_link_postconfig(hw);
8fc897b0 1943 if (ret_val)
2d7edb92 1944 return ret_val;
76c224bc 1945
2d7edb92
MC		 1946 DEBUGOUT("Valid link established!!!\n");
1947 return E1000_SUCCESS;
1948 }
1949 udelay(10);
1950 }
1951
1952 DEBUGOUT("Unable to establish link!!!\n");
1953 return E1000_SUCCESS;
1954}
1955
6418ecc6
JK		 1956/******************************************************************************
1957* Configure the MAC-to-PHY interface for 10/100Mbps
1958*
1959* hw - Struct containing variables accessed by shared code
1960******************************************************************************/
1961static int32_t
cd94dd0b 1962e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
6418ecc6
JK		 1963{
1964 int32_t ret_val = E1000_SUCCESS;
1965 uint32_t tipg;
1966 uint16_t reg_data;
1967
1968 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1969
1970 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
1971 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
1972 reg_data);
1973 if (ret_val)
1974 return ret_val;
1975
1976 /* Configure Transmit Inter-Packet Gap */
1977 tipg = E1000_READ_REG(hw, TIPG);
1978 tipg &= ~E1000_TIPG_IPGT_MASK;
1979 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
1980 E1000_WRITE_REG(hw, TIPG, tipg);
1981
cd94dd0b
AK		 1982 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1983
1984 if (ret_val)
1985 return ret_val;
1986
1987 if (duplex == HALF_DUPLEX)
1988 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1989 else
1990 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1991
1992 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1993
6418ecc6
JK		 1994 return ret_val;
1995}
1996
1997static int32_t
1998e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
1999{
2000 int32_t ret_val = E1000_SUCCESS;
2001 uint16_t reg_data;
2002 uint32_t tipg;
2003
2004 DEBUGFUNC("e1000_configure_kmrn_for_1000");
2005
2006 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2007 ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2008 reg_data);
2009 if (ret_val)
2010 return ret_val;
2011
2012 /* Configure Transmit Inter-Packet Gap */
2013 tipg = E1000_READ_REG(hw, TIPG);
2014 tipg &= ~E1000_TIPG_IPGT_MASK;
2015 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2016 E1000_WRITE_REG(hw, TIPG, tipg);
2017
cd94dd0b
AK		 2018 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2019
2020 if (ret_val)
2021 return ret_val;
2022
2023 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2024 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2025
6418ecc6
JK		 2026 return ret_val;
2027}
2028
2d7edb92
MC		 2029/******************************************************************************
2030* Configures PHY autoneg and flow control advertisement settings
2031*
2032* hw - Struct containing variables accessed by shared code
2033******************************************************************************/
2034int32_t
2035e1000_phy_setup_autoneg(struct e1000_hw *hw)
2036{
2037 int32_t ret_val;
2038 uint16_t mii_autoneg_adv_reg;
2039 uint16_t mii_1000t_ctrl_reg;
2040
2041 DEBUGFUNC("e1000_phy_setup_autoneg");
2042
2043 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2044 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
8fc897b0 2045 if (ret_val)
2d7edb92
MC		 2046 return ret_val;
2047
cd94dd0b
AK		 2048 if (hw->phy_type != e1000_phy_ife) {
2049 /* Read the MII 1000Base-T Control Register (Address 9). */
2050 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2051 if (ret_val)
2052 return ret_val;
2053 } else
2054 mii_1000t_ctrl_reg=0;
2d7edb92
MC		 2055
2056 /* Need to parse both autoneg_advertised and fc and set up
2057 * the appropriate PHY registers. First we will parse for
1da177e4
LT		 2058 * autoneg_advertised software override. Since we can advertise
2059 * a plethora of combinations, we need to check each bit
2060 * individually.
2061 */
2062
2063 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2064 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2065 * the 1000Base-T Control Register (Address 9).
2066 */
2067 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2068 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2069
2070 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2071
2072 /* Do we want to advertise 10 Mb Half Duplex? */
8fc897b0 2073 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
1da177e4
LT		 2074 DEBUGOUT("Advertise 10mb Half duplex\n");
2075 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
2076 }
2077
2078 /* Do we want to advertise 10 Mb Full Duplex? */
8fc897b0 2079 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
1da177e4
LT		 2080 DEBUGOUT("Advertise 10mb Full duplex\n");
2081 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
2082 }
2083
2084 /* Do we want to advertise 100 Mb Half Duplex? */
8fc897b0 2085 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
1da177e4
LT		 2086 DEBUGOUT("Advertise 100mb Half duplex\n");
2087 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
2088 }
2089
2090 /* Do we want to advertise 100 Mb Full Duplex? */
8fc897b0 2091 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
1da177e4
LT		 2092 DEBUGOUT("Advertise 100mb Full duplex\n");
2093 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
2094 }
2095
2096 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
8fc897b0 2097 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1da177e4
LT		 2098 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2099 }
2100
2101 /* Do we want to advertise 1000 Mb Full Duplex? */
8fc897b0 2102 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1da177e4
LT		 2103 DEBUGOUT("Advertise 1000mb Full duplex\n");
2104 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
cd94dd0b
AK		 2105 if (hw->phy_type == e1000_phy_ife) {
2106 DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2107 }
1da177e4
LT		 2108 }
2109
2110 /* Check for a software override of the flow control settings, and
2111 * setup the PHY advertisement registers accordingly. If
2112 * auto-negotiation is enabled, then software will have to set the
2113 * "PAUSE" bits to the correct value in the Auto-Negotiation
2114 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2115 *
2116 * The possible values of the "fc" parameter are:
2117 * 0: Flow control is completely disabled
2118 * 1: Rx flow control is enabled (we can receive pause frames
2119 * but not send pause frames).
2120 * 2: Tx flow control is enabled (we can send pause frames
2121 * but we do not support receiving pause frames).
2122 * 3: Both Rx and TX flow control (symmetric) are enabled.
2123 * other: No software override. The flow control configuration
2124 * in the EEPROM is used.
2125 */
2126 switch (hw->fc) {
2127 case e1000_fc_none: /* 0 */
2128 /* Flow control (RX & TX) is completely disabled by a
2129 * software over-ride.
2130 */
2131 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2132 break;
2133 case e1000_fc_rx_pause: /* 1 */
2134 /* RX Flow control is enabled, and TX Flow control is
2135 * disabled, by a software over-ride.
2136 */
2137 /* Since there really isn't a way to advertise that we are
2138 * capable of RX Pause ONLY, we will advertise that we
2139 * support both symmetric and asymmetric RX PAUSE. Later
2140 * (in e1000_config_fc_after_link_up) we will disable the
2141 *hw's ability to send PAUSE frames.
2142 */
2143 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2144 break;
2145 case e1000_fc_tx_pause: /* 2 */
2146 /* TX Flow control is enabled, and RX Flow control is
2147 * disabled, by a software over-ride.
2148 */
2149 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2150 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2151 break;
2152 case e1000_fc_full: /* 3 */
2153 /* Flow control (both RX and TX) is enabled by a software
2154 * over-ride.
2155 */
2156 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2157 break;
2158 default:
2159 DEBUGOUT("Flow control param set incorrectly\n");
2160 return -E1000_ERR_CONFIG;
2161 }
2162
2163 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
8fc897b0 2164 if (ret_val)
1da177e4
LT		 2165 return ret_val;
2166
2167 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2168
cd94dd0b
AK		 2169 if (hw->phy_type != e1000_phy_ife) {
2170 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2171 if (ret_val)
2172 return ret_val;
2173 }
1da177e4
LT		 2174
2175 return E1000_SUCCESS;
2176}
2177
2178/******************************************************************************
2179* Force PHY speed and duplex settings to hw->forced_speed_duplex
2180*
2181* hw - Struct containing variables accessed by shared code
2182******************************************************************************/
2183static int32_t
2184e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2185{
2186 uint32_t ctrl;
2187 int32_t ret_val;
2188 uint16_t mii_ctrl_reg;
2189 uint16_t mii_status_reg;
2190 uint16_t phy_data;
2191 uint16_t i;
2192
2193 DEBUGFUNC("e1000_phy_force_speed_duplex");
2194
2195 /* Turn off Flow control if we are forcing speed and duplex. */
2196 hw->fc = e1000_fc_none;
2197
2198 DEBUGOUT1("hw->fc = %d\n", hw->fc);
2199
2200 /* Read the Device Control Register. */
2201 ctrl = E1000_READ_REG(hw, CTRL);
2202
2203 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2204 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2205 ctrl &= ~(DEVICE_SPEED_MASK);
2206
2207 /* Clear the Auto Speed Detect Enable bit. */
2208 ctrl &= ~E1000_CTRL_ASDE;
2209
2210 /* Read the MII Control Register. */
2211 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
8fc897b0 2212 if (ret_val)
1da177e4
LT		 2213 return ret_val;
2214
2215 /* We need to disable autoneg in order to force link and duplex. */
2216
2217 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2218
2219 /* Are we forcing Full or Half Duplex? */
8fc897b0
AK		 2220 if (hw->forced_speed_duplex == e1000_100_full ||
2221 hw->forced_speed_duplex == e1000_10_full) {
1da177e4
LT		 2222 /* We want to force full duplex so we SET the full duplex bits in the
2223 * Device and MII Control Registers.
2224 */
2225 ctrl |= E1000_CTRL_FD;
2226 mii_ctrl_reg |= MII_CR_FULL_DUPLEX;
2227 DEBUGOUT("Full Duplex\n");
2228 } else {
2229 /* We want to force half duplex so we CLEAR the full duplex bits in
2230 * the Device and MII Control Registers.
2231 */
2232 ctrl &= ~E1000_CTRL_FD;
2233 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2234 DEBUGOUT("Half Duplex\n");
2235 }
2236
2237 /* Are we forcing 100Mbps??? */
8fc897b0 2238 if (hw->forced_speed_duplex == e1000_100_full ||
1da177e4
LT		 2239 hw->forced_speed_duplex == e1000_100_half) {
2240 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2241 ctrl |= E1000_CTRL_SPD_100;
2242 mii_ctrl_reg |= MII_CR_SPEED_100;
2243 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
2244 DEBUGOUT("Forcing 100mb ");
2245 } else {
2246 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2247 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2248 mii_ctrl_reg |= MII_CR_SPEED_10;
2249 mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2250 DEBUGOUT("Forcing 10mb ");
2251 }
2252
2253 e1000_config_collision_dist(hw);
2254
2255 /* Write the configured values back to the Device Control Reg. */
2256 E1000_WRITE_REG(hw, CTRL, ctrl);
2257
6418ecc6
JK		 2258 if ((hw->phy_type == e1000_phy_m88) ||
2259 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4 2260 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2261 if (ret_val)
1da177e4
LT		 2262 return ret_val;
2263
2264 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2265 * forced whenever speed are duplex are forced.
2266 */
2267 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2268 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2269 if (ret_val)
1da177e4
LT		 2270 return ret_val;
2271
2272 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2273
2274 /* Need to reset the PHY or these changes will be ignored */
2275 mii_ctrl_reg |= MII_CR_RESET;
cd94dd0b
AK		 2276 /* Disable MDI-X support for 10/100 */
2277 } else if (hw->phy_type == e1000_phy_ife) {
2278 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2279 if (ret_val)
2280 return ret_val;
2281
2282 phy_data &= ~IFE_PMC_AUTO_MDIX;
2283 phy_data &= ~IFE_PMC_FORCE_MDIX;
2284
2285 ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2286 if (ret_val)
2287 return ret_val;
1da177e4
LT		 2288 } else {
2289 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2290 * forced whenever speed or duplex are forced.
2291 */
2292 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
8fc897b0 2293 if (ret_val)
1da177e4
LT		 2294 return ret_val;
2295
2296 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2297 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2298
2299 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
8fc897b0 2300 if (ret_val)
1da177e4
LT		 2301 return ret_val;
2302 }
2303
2304 /* Write back the modified PHY MII control register. */
2305 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
8fc897b0 2306 if (ret_val)
1da177e4
LT		 2307 return ret_val;
2308
2309 udelay(1);
2310
2311 /* The wait_autoneg_complete flag may be a little misleading here.
2312 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
2313 * But we do want to delay for a period while forcing only so we
2314 * don't generate false No Link messages. So we will wait here
2315 * only if the user has set wait_autoneg_complete to 1, which is
2316 * the default.
2317 */
8fc897b0 2318 if (hw->wait_autoneg_complete) {
1da177e4
LT		 2319 /* We will wait for autoneg to complete. */
2320 DEBUGOUT("Waiting for forced speed/duplex link.\n");
2321 mii_status_reg = 0;
2322
2323 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 2324 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 2325 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2326 * to be set.
2327 */
2328 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2329 if (ret_val)
1da177e4
LT		 2330 return ret_val;
2331
2332 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2333 if (ret_val)
1da177e4
LT		 2334 return ret_val;
2335
8fc897b0 2336 if (mii_status_reg & MII_SR_LINK_STATUS) break;
1da177e4
LT		 2337 msec_delay(100);
2338 }
8fc897b0 2339 if ((i == 0) &&
6418ecc6
JK		 2340 ((hw->phy_type == e1000_phy_m88) ||
2341 (hw->phy_type == e1000_phy_gg82563))) {
1da177e4
LT		 2342 /* We didn't get link. Reset the DSP and wait again for link. */
2343 ret_val = e1000_phy_reset_dsp(hw);
8fc897b0 2344 if (ret_val) {
1da177e4
LT		 2345 DEBUGOUT("Error Resetting PHY DSP\n");
2346 return ret_val;
2347 }
2348 }
2349 /* This loop will early-out if the link condition has been met. */
8fc897b0
AK		 2350 for (i = PHY_FORCE_TIME; i > 0; i--) {
2351 if (mii_status_reg & MII_SR_LINK_STATUS) break;
1da177e4
LT		 2352 msec_delay(100);
2353 /* Read the MII Status Register and wait for Auto-Neg Complete bit
2354 * to be set.
2355 */
2356 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2357 if (ret_val)
1da177e4
LT		 2358 return ret_val;
2359
2360 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2361 if (ret_val)
1da177e4
LT		 2362 return ret_val;
2363 }
2364 }
2365
2366 if (hw->phy_type == e1000_phy_m88) {
2367 /* Because we reset the PHY above, we need to re-force TX_CLK in the
2368 * Extended PHY Specific Control Register to 25MHz clock. This value
2369 * defaults back to a 2.5MHz clock when the PHY is reset.
2370 */
2371 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2372 if (ret_val)
1da177e4
LT		 2373 return ret_val;
2374
2375 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2376 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
8fc897b0 2377 if (ret_val)
1da177e4
LT		 2378 return ret_val;
2379
2380 /* In addition, because of the s/w reset above, we need to enable CRS on
2381 * TX. This must be set for both full and half duplex operation.
2382 */
2383 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 2384 if (ret_val)
1da177e4
LT		 2385 return ret_val;
2386
2387 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2388 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
8fc897b0 2389 if (ret_val)
1da177e4
LT		 2390 return ret_val;
2391
8fc897b0
AK		 2392 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2393 (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full ||
2394 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4 2395 ret_val = e1000_polarity_reversal_workaround(hw);
8fc897b0 2396 if (ret_val)
1da177e4
LT		 2397 return ret_val;
2398 }
6418ecc6
JK		 2399 } else if (hw->phy_type == e1000_phy_gg82563) {
2400 /* The TX_CLK of the Extended PHY Specific Control Register defaults
2401 * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2402 * we're not in a forced 10/duplex configuration. */
2403 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2404 if (ret_val)
2405 return ret_val;
2406
2407 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2408 if ((hw->forced_speed_duplex == e1000_10_full) ||
2409 (hw->forced_speed_duplex == e1000_10_half))
2410 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2411 else
2412 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2413
2414 /* Also due to the reset, we need to enable CRS on Tx. */
2415 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2416
2417 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2418 if (ret_val)
2419 return ret_val;
1da177e4
LT		 2420 }
2421 return E1000_SUCCESS;
2422}
2423
2424/******************************************************************************
2425* Sets the collision distance in the Transmit Control register
2426*
2427* hw - Struct containing variables accessed by shared code
2428*
2429* Link should have been established previously. Reads the speed and duplex
2430* information from the Device Status register.
2431******************************************************************************/
2432void
2433e1000_config_collision_dist(struct e1000_hw *hw)
2434{
0fadb059 2435 uint32_t tctl, coll_dist;
1da177e4
LT		 2436
2437 DEBUGFUNC("e1000_config_collision_dist");
2438
0fadb059
JK		 2439 if (hw->mac_type < e1000_82543)
2440 coll_dist = E1000_COLLISION_DISTANCE_82542;
2441 else
2442 coll_dist = E1000_COLLISION_DISTANCE;
2443
1da177e4
LT		 2444 tctl = E1000_READ_REG(hw, TCTL);
2445
2446 tctl &= ~E1000_TCTL_COLD;
0fadb059 2447 tctl |= coll_dist << E1000_COLD_SHIFT;
1da177e4
LT		 2448
2449 E1000_WRITE_REG(hw, TCTL, tctl);
2450 E1000_WRITE_FLUSH(hw);
2451}
2452
2453/******************************************************************************
2454* Sets MAC speed and duplex settings to reflect the those in the PHY
2455*
2456* hw - Struct containing variables accessed by shared code
2457* mii_reg - data to write to the MII control register
2458*
2459* The contents of the PHY register containing the needed information need to
2460* be passed in.
2461******************************************************************************/
2462static int32_t
2463e1000_config_mac_to_phy(struct e1000_hw *hw)
2464{
2465 uint32_t ctrl;
2466 int32_t ret_val;
2467 uint16_t phy_data;
2468
2469 DEBUGFUNC("e1000_config_mac_to_phy");
2470
76c224bc 2471 /* 82544 or newer MAC, Auto Speed Detection takes care of
2d7edb92
MC		 2472 * MAC speed/duplex configuration.*/
2473 if (hw->mac_type >= e1000_82544)
2474 return E1000_SUCCESS;
2475
1da177e4
LT		 2476 /* Read the Device Control Register and set the bits to Force Speed
2477 * and Duplex.
2478 */
2479 ctrl = E1000_READ_REG(hw, CTRL);
2480 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2481 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2482
2483 /* Set up duplex in the Device Control and Transmit Control
2484 * registers depending on negotiated values.
2485 */
2d7edb92 2486 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 2487 if (ret_val)
2d7edb92 2488 return ret_val;
1da177e4 2489
8fc897b0 2490 if (phy_data & M88E1000_PSSR_DPLX)
2d7edb92 2491 ctrl |= E1000_CTRL_FD;
76c224bc 2492 else
2d7edb92 2493 ctrl &= ~E1000_CTRL_FD;
1da177e4 2494
2d7edb92 2495 e1000_config_collision_dist(hw);
1da177e4 2496
2d7edb92
MC		 2497 /* Set up speed in the Device Control register depending on
2498 * negotiated values.
2499 */
8fc897b0 2500 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2d7edb92 2501 ctrl |= E1000_CTRL_SPD_1000;
8fc897b0 2502 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2d7edb92 2503 ctrl |= E1000_CTRL_SPD_100;
1da177e4 2504
1da177e4
LT		 2505 /* Write the configured values back to the Device Control Reg. */
2506 E1000_WRITE_REG(hw, CTRL, ctrl);
2507 return E1000_SUCCESS;
2508}
2509
2510/******************************************************************************
2511 * Forces the MAC's flow control settings.
2512 *
2513 * hw - Struct containing variables accessed by shared code
2514 *
2515 * Sets the TFCE and RFCE bits in the device control register to reflect
2516 * the adapter settings. TFCE and RFCE need to be explicitly set by
2517 * software when a Copper PHY is used because autonegotiation is managed
2518 * by the PHY rather than the MAC. Software must also configure these
2519 * bits when link is forced on a fiber connection.
2520 *****************************************************************************/
2521int32_t
2522e1000_force_mac_fc(struct e1000_hw *hw)
2523{
2524 uint32_t ctrl;
2525
2526 DEBUGFUNC("e1000_force_mac_fc");
2527
2528 /* Get the current configuration of the Device Control Register */
2529 ctrl = E1000_READ_REG(hw, CTRL);
2530
2531 /* Because we didn't get link via the internal auto-negotiation
2532 * mechanism (we either forced link or we got link via PHY
2533 * auto-neg), we have to manually enable/disable transmit an
2534 * receive flow control.
2535 *
2536 * The "Case" statement below enables/disable flow control
2537 * according to the "hw->fc" parameter.
2538 *
2539 * The possible values of the "fc" parameter are:
2540 * 0: Flow control is completely disabled
2541 * 1: Rx flow control is enabled (we can receive pause
2542 * frames but not send pause frames).
2543 * 2: Tx flow control is enabled (we can send pause frames
2544 * frames but we do not receive pause frames).
2545 * 3: Both Rx and TX flow control (symmetric) is enabled.
2546 * other: No other values should be possible at this point.
2547 */
2548
2549 switch (hw->fc) {
2550 case e1000_fc_none:
2551 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2552 break;
2553 case e1000_fc_rx_pause:
2554 ctrl &= (~E1000_CTRL_TFCE);
2555 ctrl |= E1000_CTRL_RFCE;
2556 break;
2557 case e1000_fc_tx_pause:
2558 ctrl &= (~E1000_CTRL_RFCE);
2559 ctrl |= E1000_CTRL_TFCE;
2560 break;
2561 case e1000_fc_full:
2562 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2563 break;
2564 default:
2565 DEBUGOUT("Flow control param set incorrectly\n");
2566 return -E1000_ERR_CONFIG;
2567 }
2568
2569 /* Disable TX Flow Control for 82542 (rev 2.0) */
8fc897b0 2570 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2571 ctrl &= (~E1000_CTRL_TFCE);
2572
2573 E1000_WRITE_REG(hw, CTRL, ctrl);
2574 return E1000_SUCCESS;
2575}
2576
2577/******************************************************************************
2578 * Configures flow control settings after link is established
2579 *
2580 * hw - Struct containing variables accessed by shared code
2581 *
2582 * Should be called immediately after a valid link has been established.
2583 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2584 * and autonegotiation is enabled, the MAC flow control settings will be set
2585 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2586 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2587 *****************************************************************************/
3ad2cc67 2588static int32_t
1da177e4
LT		 2589e1000_config_fc_after_link_up(struct e1000_hw *hw)
2590{
2591 int32_t ret_val;
2592 uint16_t mii_status_reg;
2593 uint16_t mii_nway_adv_reg;
2594 uint16_t mii_nway_lp_ability_reg;
2595 uint16_t speed;
2596 uint16_t duplex;
2597
2598 DEBUGFUNC("e1000_config_fc_after_link_up");
2599
2600 /* Check for the case where we have fiber media and auto-neg failed
2601 * so we had to force link. In this case, we need to force the
2602 * configuration of the MAC to match the "fc" parameter.
2603 */
8fc897b0
AK		 2604 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2605 ((hw->media_type == e1000_media_type_internal_serdes) &&
2606 (hw->autoneg_failed)) ||
2607 ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
1da177e4 2608 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2609 if (ret_val) {
1da177e4
LT		 2610 DEBUGOUT("Error forcing flow control settings\n");
2611 return ret_val;
2612 }
2613 }
2614
2615 /* Check for the case where we have copper media and auto-neg is
2616 * enabled. In this case, we need to check and see if Auto-Neg
2617 * has completed, and if so, how the PHY and link partner has
2618 * flow control configured.
2619 */
8fc897b0 2620 if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
1da177e4
LT		 2621 /* Read the MII Status Register and check to see if AutoNeg
2622 * has completed. We read this twice because this reg has
2623 * some "sticky" (latched) bits.
2624 */
2625 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2626 if (ret_val)
1da177e4
LT		 2627 return ret_val;
2628 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 2629 if (ret_val)
1da177e4
LT		 2630 return ret_val;
2631
8fc897b0 2632 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 2633 /* The AutoNeg process has completed, so we now need to
2634 * read both the Auto Negotiation Advertisement Register
2635 * (Address 4) and the Auto_Negotiation Base Page Ability
2636 * Register (Address 5) to determine how flow control was
2637 * negotiated.
2638 */
2639 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2640 &mii_nway_adv_reg);
8fc897b0 2641 if (ret_val)
1da177e4
LT		 2642 return ret_val;
2643 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2644 &mii_nway_lp_ability_reg);
8fc897b0 2645 if (ret_val)
1da177e4
LT		 2646 return ret_val;
2647
2648 /* Two bits in the Auto Negotiation Advertisement Register
2649 * (Address 4) and two bits in the Auto Negotiation Base
2650 * Page Ability Register (Address 5) determine flow control
2651 * for both the PHY and the link partner. The following
2652 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2653 * 1999, describes these PAUSE resolution bits and how flow
2654 * control is determined based upon these settings.
2655 * NOTE: DC = Don't Care
2656 *
2657 * LOCAL DEVICE | LINK PARTNER
2658 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2659 *-------|---------|-------|---------|--------------------
2660 * 0 | 0 | DC | DC | e1000_fc_none
2661 * 0 | 1 | 0 | DC | e1000_fc_none
2662 * 0 | 1 | 1 | 0 | e1000_fc_none
2663 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2664 * 1 | 0 | 0 | DC | e1000_fc_none
2665 * 1 | DC | 1 | DC | e1000_fc_full
2666 * 1 | 1 | 0 | 0 | e1000_fc_none
2667 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2668 *
2669 */
2670 /* Are both PAUSE bits set to 1? If so, this implies
2671 * Symmetric Flow Control is enabled at both ends. The
2672 * ASM_DIR bits are irrelevant per the spec.
2673 *
2674 * For Symmetric Flow Control:
2675 *
2676 * LOCAL DEVICE | LINK PARTNER
2677 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2678 *-------|---------|-------|---------|--------------------
2679 * 1 | DC | 1 | DC | e1000_fc_full
2680 *
2681 */
8fc897b0
AK		 2682 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2683 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1da177e4
LT		 2684 /* Now we need to check if the user selected RX ONLY
2685 * of pause frames. In this case, we had to advertise
2686 * FULL flow control because we could not advertise RX
2687 * ONLY. Hence, we must now check to see if we need to
2688 * turn OFF the TRANSMISSION of PAUSE frames.
2689 */
8fc897b0 2690 if (hw->original_fc == e1000_fc_full) {
1da177e4 2691 hw->fc = e1000_fc_full;
a42a507c 2692 DEBUGOUT("Flow Control = FULL.\n");
1da177e4
LT		 2693 } else {
2694 hw->fc = e1000_fc_rx_pause;
a42a507c 2695 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2696 }
2697 }
2698 /* For receiving PAUSE frames ONLY.
2699 *
2700 * LOCAL DEVICE | LINK PARTNER
2701 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2702 *-------|---------|-------|---------|--------------------
2703 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
2704 *
2705 */
8fc897b0
AK		 2706 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2707 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2708 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2709 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1da177e4 2710 hw->fc = e1000_fc_tx_pause;
a42a507c 2711 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
1da177e4
LT		 2712 }
2713 /* For transmitting PAUSE frames ONLY.
2714 *
2715 * LOCAL DEVICE | LINK PARTNER
2716 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2717 *-------|---------|-------|---------|--------------------
2718 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
2719 *
2720 */
8fc897b0
AK		 2721 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2722 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2723 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2724 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1da177e4 2725 hw->fc = e1000_fc_rx_pause;
a42a507c 2726 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2727 }
2728 /* Per the IEEE spec, at this point flow control should be
2729 * disabled. However, we want to consider that we could
2730 * be connected to a legacy switch that doesn't advertise
2731 * desired flow control, but can be forced on the link
2732 * partner. So if we advertised no flow control, that is
2733 * what we will resolve to. If we advertised some kind of
2734 * receive capability (Rx Pause Only or Full Flow Control)
2735 * and the link partner advertised none, we will configure
2736 * ourselves to enable Rx Flow Control only. We can do
2737 * this safely for two reasons: If the link partner really
2738 * didn't want flow control enabled, and we enable Rx, no
2739 * harm done since we won't be receiving any PAUSE frames
2740 * anyway. If the intent on the link partner was to have
2741 * flow control enabled, then by us enabling RX only, we
2742 * can at least receive pause frames and process them.
2743 * This is a good idea because in most cases, since we are
2744 * predominantly a server NIC, more times than not we will
2745 * be asked to delay transmission of packets than asking
2746 * our link partner to pause transmission of frames.
2747 */
8fc897b0
AK		 2748 else if ((hw->original_fc == e1000_fc_none ||
2749 hw->original_fc == e1000_fc_tx_pause) ||
2750 hw->fc_strict_ieee) {
1da177e4 2751 hw->fc = e1000_fc_none;
a42a507c 2752 DEBUGOUT("Flow Control = NONE.\n");
1da177e4
LT		 2753 } else {
2754 hw->fc = e1000_fc_rx_pause;
a42a507c 2755 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
1da177e4
LT		 2756 }
2757
2758 /* Now we need to do one last check... If we auto-
2759 * negotiated to HALF DUPLEX, flow control should not be
2760 * enabled per IEEE 802.3 spec.
2761 */
2762 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 2763 if (ret_val) {
1da177e4
LT		 2764 DEBUGOUT("Error getting link speed and duplex\n");
2765 return ret_val;
2766 }
2767
8fc897b0 2768 if (duplex == HALF_DUPLEX)
1da177e4
LT		 2769 hw->fc = e1000_fc_none;
2770
2771 /* Now we call a subroutine to actually force the MAC
2772 * controller to use the correct flow control settings.
2773 */
2774 ret_val = e1000_force_mac_fc(hw);
8fc897b0 2775 if (ret_val) {
1da177e4
LT		 2776 DEBUGOUT("Error forcing flow control settings\n");
2777 return ret_val;
2778 }
2779 } else {
a42a507c 2780 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1da177e4
LT		 2781 }
2782 }
2783 return E1000_SUCCESS;
2784}
2785
2786/******************************************************************************
2787 * Checks to see if the link status of the hardware has changed.
2788 *
2789 * hw - Struct containing variables accessed by shared code
2790 *
2791 * Called by any function that needs to check the link status of the adapter.
2792 *****************************************************************************/
2793int32_t
2794e1000_check_for_link(struct e1000_hw *hw)
2795{
2796 uint32_t rxcw = 0;
2797 uint32_t ctrl;
2798 uint32_t status;
2799 uint32_t rctl;
2800 uint32_t icr;
2801 uint32_t signal = 0;
2802 int32_t ret_val;
2803 uint16_t phy_data;
2804
2805 DEBUGFUNC("e1000_check_for_link");
2806
2807 ctrl = E1000_READ_REG(hw, CTRL);
2808 status = E1000_READ_REG(hw, STATUS);
2809
2810 /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2811 * set when the optics detect a signal. On older adapters, it will be
2812 * cleared when there is a signal. This applies to fiber media only.
2813 */
8fc897b0
AK		 2814 if ((hw->media_type == e1000_media_type_fiber) ||
2815 (hw->media_type == e1000_media_type_internal_serdes)) {
1da177e4
LT		 2816 rxcw = E1000_READ_REG(hw, RXCW);
2817
8fc897b0 2818 if (hw->media_type == e1000_media_type_fiber) {
1da177e4 2819 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
8fc897b0 2820 if (status & E1000_STATUS_LU)
1da177e4
LT		 2821 hw->get_link_status = FALSE;
2822 }
2823 }
2824
2825 /* If we have a copper PHY then we only want to go out to the PHY
2826 * registers to see if Auto-Neg has completed and/or if our link
2827 * status has changed. The get_link_status flag will be set if we
2828 * receive a Link Status Change interrupt or we have Rx Sequence
2829 * Errors.
2830 */
8fc897b0 2831 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1da177e4
LT		 2832 /* First we want to see if the MII Status Register reports
2833 * link. If so, then we want to get the current speed/duplex
2834 * of the PHY.
2835 * Read the register twice since the link bit is sticky.
2836 */
2837 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2838 if (ret_val)
1da177e4
LT		 2839 return ret_val;
2840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 2841 if (ret_val)
1da177e4
LT		 2842 return ret_val;
2843
8fc897b0 2844 if (phy_data & MII_SR_LINK_STATUS) {
1da177e4
LT		 2845 hw->get_link_status = FALSE;
2846 /* Check if there was DownShift, must be checked immediately after
2847 * link-up */
2848 e1000_check_downshift(hw);
2849
2850 /* If we are on 82544 or 82543 silicon and speed/duplex
2851 * are forced to 10H or 10F, then we will implement the polarity
2852 * reversal workaround. We disable interrupts first, and upon
2853 * returning, place the devices interrupt state to its previous
2854 * value except for the link status change interrupt which will
2855 * happen due to the execution of this workaround.
2856 */
2857
8fc897b0
AK		 2858 if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) &&
2859 (!hw->autoneg) &&
2860 (hw->forced_speed_duplex == e1000_10_full ||
2861 hw->forced_speed_duplex == e1000_10_half)) {
1da177e4
LT		 2862 E1000_WRITE_REG(hw, IMC, 0xffffffff);
2863 ret_val = e1000_polarity_reversal_workaround(hw);
2864 icr = E1000_READ_REG(hw, ICR);
2865 E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
2866 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
2867 }
2868
2869 } else {
2870 /* No link detected */
2871 e1000_config_dsp_after_link_change(hw, FALSE);
2872 return 0;
2873 }
2874
2875 /* If we are forcing speed/duplex, then we simply return since
2876 * we have already determined whether we have link or not.
2877 */
8fc897b0 2878 if (!hw->autoneg) return -E1000_ERR_CONFIG;
1da177e4
LT		 2879
2880 /* optimize the dsp settings for the igp phy */
2881 e1000_config_dsp_after_link_change(hw, TRUE);
2882
2883 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
2884 * have Si on board that is 82544 or newer, Auto
2885 * Speed Detection takes care of MAC speed/duplex
2886 * configuration. So we only need to configure Collision
2887 * Distance in the MAC. Otherwise, we need to force
2888 * speed/duplex on the MAC to the current PHY speed/duplex
2889 * settings.
2890 */
8fc897b0 2891 if (hw->mac_type >= e1000_82544)
1da177e4
LT		 2892 e1000_config_collision_dist(hw);
2893 else {
2894 ret_val = e1000_config_mac_to_phy(hw);
8fc897b0 2895 if (ret_val) {
1da177e4
LT		 2896 DEBUGOUT("Error configuring MAC to PHY settings\n");
2897 return ret_val;
2898 }
2899 }
2900
2901 /* Configure Flow Control now that Auto-Neg has completed. First, we
2902 * need to restore the desired flow control settings because we may
2903 * have had to re-autoneg with a different link partner.
2904 */
2905 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 2906 if (ret_val) {
1da177e4
LT		 2907 DEBUGOUT("Error configuring flow control\n");
2908 return ret_val;
2909 }
2910
2911 /* At this point we know that we are on copper and we have
2912 * auto-negotiated link. These are conditions for checking the link
2913 * partner capability register. We use the link speed to determine if
2914 * TBI compatibility needs to be turned on or off. If the link is not
2915 * at gigabit speed, then TBI compatibility is not needed. If we are
2916 * at gigabit speed, we turn on TBI compatibility.
2917 */
8fc897b0 2918 if (hw->tbi_compatibility_en) {
1da177e4 2919 uint16_t speed, duplex;
592600a0
AK		 2920 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2921 if (ret_val) {
2922 DEBUGOUT("Error getting link speed and duplex\n");
2923 return ret_val;
2924 }
2925 if (speed != SPEED_1000) {
1da177e4
LT		 2926 /* If link speed is not set to gigabit speed, we do not need
2927 * to enable TBI compatibility.
2928 */
8fc897b0 2929 if (hw->tbi_compatibility_on) {
1da177e4
LT		 2930 /* If we previously were in the mode, turn it off. */
2931 rctl = E1000_READ_REG(hw, RCTL);
2932 rctl &= ~E1000_RCTL_SBP;
2933 E1000_WRITE_REG(hw, RCTL, rctl);
2934 hw->tbi_compatibility_on = FALSE;
2935 }
2936 } else {
2937 /* If TBI compatibility is was previously off, turn it on. For
2938 * compatibility with a TBI link partner, we will store bad
2939 * packets. Some frames have an additional byte on the end and
2940 * will look like CRC errors to to the hardware.
2941 */
8fc897b0 2942 if (!hw->tbi_compatibility_on) {
1da177e4
LT		 2943 hw->tbi_compatibility_on = TRUE;
2944 rctl = E1000_READ_REG(hw, RCTL);
2945 rctl |= E1000_RCTL_SBP;
2946 E1000_WRITE_REG(hw, RCTL, rctl);
2947 }
2948 }
2949 }
2950 }
2951 /* If we don't have link (auto-negotiation failed or link partner cannot
2952 * auto-negotiate), the cable is plugged in (we have signal), and our
2953 * link partner is not trying to auto-negotiate with us (we are receiving
2954 * idles or data), we need to force link up. We also need to give
2955 * auto-negotiation time to complete, in case the cable was just plugged
2956 * in. The autoneg_failed flag does this.
2957 */
8fc897b0 2958 else if ((((hw->media_type == e1000_media_type_fiber) &&
1da177e4 2959 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
8fc897b0
AK		 2960 (hw->media_type == e1000_media_type_internal_serdes)) &&
2961 (!(status & E1000_STATUS_LU)) &&
2962 (!(rxcw & E1000_RXCW_C))) {
2963 if (hw->autoneg_failed == 0) {
1da177e4
LT		 2964 hw->autoneg_failed = 1;
2965 return 0;
2966 }
a42a507c 2967 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1da177e4
LT		 2968
2969 /* Disable auto-negotiation in the TXCW register */
2970 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2971
2972 /* Force link-up and also force full-duplex. */
2973 ctrl = E1000_READ_REG(hw, CTRL);
2974 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2975 E1000_WRITE_REG(hw, CTRL, ctrl);
2976
2977 /* Configure Flow Control after forcing link up. */
2978 ret_val = e1000_config_fc_after_link_up(hw);
8fc897b0 2979 if (ret_val) {
1da177e4
LT		 2980 DEBUGOUT("Error configuring flow control\n");
2981 return ret_val;
2982 }
2983 }
2984 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2985 * auto-negotiation in the TXCW register and disable forced link in the
2986 * Device Control register in an attempt to auto-negotiate with our link
2987 * partner.
2988 */
8fc897b0
AK		 2989 else if (((hw->media_type == e1000_media_type_fiber) ||
2990 (hw->media_type == e1000_media_type_internal_serdes)) &&
2991 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
a42a507c 2992 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1da177e4
LT		 2993 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2994 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2995
2996 hw->serdes_link_down = FALSE;
2997 }
2998 /* If we force link for non-auto-negotiation switch, check link status
2999 * based on MAC synchronization for internal serdes media type.
3000 */
8fc897b0
AK		 3001 else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3002 !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3003 /* SYNCH bit and IV bit are sticky. */
3004 udelay(10);
8fc897b0
AK		 3005 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3006 if (!(rxcw & E1000_RXCW_IV)) {
1da177e4
LT		 3007 hw->serdes_link_down = FALSE;
3008 DEBUGOUT("SERDES: Link is up.\n");
3009 }
3010 } else {
3011 hw->serdes_link_down = TRUE;
3012 DEBUGOUT("SERDES: Link is down.\n");
3013 }
3014 }
8fc897b0
AK		 3015 if ((hw->media_type == e1000_media_type_internal_serdes) &&
3016 (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
1da177e4
LT		 3017 hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3018 }
3019 return E1000_SUCCESS;
3020}
3021
3022/******************************************************************************
3023 * Detects the current speed and duplex settings of the hardware.
3024 *
3025 * hw - Struct containing variables accessed by shared code
3026 * speed - Speed of the connection
3027 * duplex - Duplex setting of the connection
3028 *****************************************************************************/
3029int32_t
3030e1000_get_speed_and_duplex(struct e1000_hw *hw,
3031 uint16_t *speed,
3032 uint16_t *duplex)
3033{
3034 uint32_t status;
3035 int32_t ret_val;
3036 uint16_t phy_data;
3037
3038 DEBUGFUNC("e1000_get_speed_and_duplex");
3039
8fc897b0 3040 if (hw->mac_type >= e1000_82543) {
1da177e4 3041 status = E1000_READ_REG(hw, STATUS);
8fc897b0 3042 if (status & E1000_STATUS_SPEED_1000) {
1da177e4
LT		 3043 *speed = SPEED_1000;
3044 DEBUGOUT("1000 Mbs, ");
8fc897b0 3045 } else if (status & E1000_STATUS_SPEED_100) {
1da177e4
LT		 3046 *speed = SPEED_100;
3047 DEBUGOUT("100 Mbs, ");
3048 } else {
3049 *speed = SPEED_10;
3050 DEBUGOUT("10 Mbs, ");
3051 }
3052
8fc897b0 3053 if (status & E1000_STATUS_FD) {
1da177e4 3054 *duplex = FULL_DUPLEX;
a42a507c 3055 DEBUGOUT("Full Duplex\n");
1da177e4
LT		 3056 } else {
3057 *duplex = HALF_DUPLEX;
a42a507c 3058 DEBUGOUT(" Half Duplex\n");
1da177e4
LT		 3059 }
3060 } else {
a42a507c 3061 DEBUGOUT("1000 Mbs, Full Duplex\n");
1da177e4
LT		 3062 *speed = SPEED_1000;
3063 *duplex = FULL_DUPLEX;
3064 }
3065
3066 /* IGP01 PHY may advertise full duplex operation after speed downgrade even
3067 * if it is operating at half duplex. Here we set the duplex settings to
3068 * match the duplex in the link partner's capabilities.
3069 */
8fc897b0 3070 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
1da177e4 3071 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
8fc897b0 3072 if (ret_val)
1da177e4
LT		 3073 return ret_val;
3074
8fc897b0 3075 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
1da177e4
LT		 3076 *duplex = HALF_DUPLEX;
3077 else {
3078 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
8fc897b0 3079 if (ret_val)
1da177e4 3080 return ret_val;
8fc897b0 3081 if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
1da177e4
LT		 3082 (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3083 *duplex = HALF_DUPLEX;
3084 }
3085 }
3086
76c224bc 3087 if ((hw->mac_type == e1000_80003es2lan) &&
6418ecc6
JK		 3088 (hw->media_type == e1000_media_type_copper)) {
3089 if (*speed == SPEED_1000)
3090 ret_val = e1000_configure_kmrn_for_1000(hw);
3091 else
cd94dd0b
AK		 3092 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3093 if (ret_val)
3094 return ret_val;
3095 }
3096
3097 if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3098 ret_val = e1000_kumeran_lock_loss_workaround(hw);
6418ecc6
JK		 3099 if (ret_val)
3100 return ret_val;
3101 }
3102
1da177e4
LT		 3103 return E1000_SUCCESS;
3104}
3105
3106/******************************************************************************
3107* Blocks until autoneg completes or times out (~4.5 seconds)
3108*
3109* hw - Struct containing variables accessed by shared code
3110******************************************************************************/
3ad2cc67 3111static int32_t
1da177e4
LT		 3112e1000_wait_autoneg(struct e1000_hw *hw)
3113{
3114 int32_t ret_val;
3115 uint16_t i;
3116 uint16_t phy_data;
3117
3118 DEBUGFUNC("e1000_wait_autoneg");
3119 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3120
3121 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
8fc897b0 3122 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
1da177e4
LT		 3123 /* Read the MII Status Register and wait for Auto-Neg
3124 * Complete bit to be set.
3125 */
3126 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3127 if (ret_val)
1da177e4
LT		 3128 return ret_val;
3129 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 3130 if (ret_val)
1da177e4 3131 return ret_val;
8fc897b0 3132 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
1da177e4
LT		 3133 return E1000_SUCCESS;
3134 }
3135 msec_delay(100);
3136 }
3137 return E1000_SUCCESS;
3138}
3139
3140/******************************************************************************
3141* Raises the Management Data Clock
3142*
3143* hw - Struct containing variables accessed by shared code
3144* ctrl - Device control register's current value
3145******************************************************************************/
3146static void
3147e1000_raise_mdi_clk(struct e1000_hw *hw,
3148 uint32_t *ctrl)
3149{
3150 /* Raise the clock input to the Management Data Clock (by setting the MDC
3151 * bit), and then delay 10 microseconds.
3152 */
3153 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3154 E1000_WRITE_FLUSH(hw);
3155 udelay(10);
3156}
3157
3158/******************************************************************************
3159* Lowers the Management Data Clock
3160*
3161* hw - Struct containing variables accessed by shared code
3162* ctrl - Device control register's current value
3163******************************************************************************/
3164static void
3165e1000_lower_mdi_clk(struct e1000_hw *hw,
3166 uint32_t *ctrl)
3167{
3168 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3169 * bit), and then delay 10 microseconds.
3170 */
3171 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3172 E1000_WRITE_FLUSH(hw);
3173 udelay(10);
3174}
3175
3176/******************************************************************************
3177* Shifts data bits out to the PHY
3178*
3179* hw - Struct containing variables accessed by shared code
3180* data - Data to send out to the PHY
3181* count - Number of bits to shift out
3182*
3183* Bits are shifted out in MSB to LSB order.
3184******************************************************************************/
3185static void
3186e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3187 uint32_t data,
3188 uint16_t count)
3189{
3190 uint32_t ctrl;
3191 uint32_t mask;
3192
3193 /* We need to shift "count" number of bits out to the PHY. So, the value
3194 * in the "data" parameter will be shifted out to the PHY one bit at a
3195 * time. In order to do this, "data" must be broken down into bits.
3196 */
3197 mask = 0x01;
3198 mask <<= (count - 1);
3199
3200 ctrl = E1000_READ_REG(hw, CTRL);
3201
3202 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3203 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
3204
8fc897b0 3205 while (mask) {
1da177e4
LT		 3206 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3207 * then raising and lowering the Management Data Clock. A "0" is
3208 * shifted out to the PHY by setting the MDIO bit to "0" and then
3209 * raising and lowering the clock.
3210 */
8fc897b0
AK		 3211 if (data & mask)
3212 ctrl |= E1000_CTRL_MDIO;
3213 else
3214 ctrl &= ~E1000_CTRL_MDIO;
1da177e4
LT		 3215
3216 E1000_WRITE_REG(hw, CTRL, ctrl);
3217 E1000_WRITE_FLUSH(hw);
3218
3219 udelay(10);
3220
3221 e1000_raise_mdi_clk(hw, &ctrl);
3222 e1000_lower_mdi_clk(hw, &ctrl);
3223
3224 mask = mask >> 1;
3225 }
3226}
3227
3228/******************************************************************************
3229* Shifts data bits in from the PHY
3230*
3231* hw - Struct containing variables accessed by shared code
3232*
3233* Bits are shifted in in MSB to LSB order.
3234******************************************************************************/
3235static uint16_t
3236e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3237{
3238 uint32_t ctrl;
3239 uint16_t data = 0;
3240 uint8_t i;
3241
3242 /* In order to read a register from the PHY, we need to shift in a total
3243 * of 18 bits from the PHY. The first two bit (turnaround) times are used
3244 * to avoid contention on the MDIO pin when a read operation is performed.
3245 * These two bits are ignored by us and thrown away. Bits are "shifted in"
3246 * by raising the input to the Management Data Clock (setting the MDC bit),
3247 * and then reading the value of the MDIO bit.
3248 */
3249 ctrl = E1000_READ_REG(hw, CTRL);
3250
3251 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3252 ctrl &= ~E1000_CTRL_MDIO_DIR;
3253 ctrl &= ~E1000_CTRL_MDIO;
3254
3255 E1000_WRITE_REG(hw, CTRL, ctrl);
3256 E1000_WRITE_FLUSH(hw);
3257
3258 /* Raise and Lower the clock before reading in the data. This accounts for
3259 * the turnaround bits. The first clock occurred when we clocked out the
3260 * last bit of the Register Address.
3261 */
3262 e1000_raise_mdi_clk(hw, &ctrl);
3263 e1000_lower_mdi_clk(hw, &ctrl);
3264
8fc897b0 3265 for (data = 0, i = 0; i < 16; i++) {
1da177e4
LT		 3266 data = data << 1;
3267 e1000_raise_mdi_clk(hw, &ctrl);
3268 ctrl = E1000_READ_REG(hw, CTRL);
3269 /* Check to see if we shifted in a "1". */
8fc897b0
AK		 3270 if (ctrl & E1000_CTRL_MDIO)
3271 data |= 1;
1da177e4
LT		 3272 e1000_lower_mdi_clk(hw, &ctrl);
3273 }
3274
3275 e1000_raise_mdi_clk(hw, &ctrl);
3276 e1000_lower_mdi_clk(hw, &ctrl);
3277
3278 return data;
3279}
3280
e4c780b1 3281static int32_t
6418ecc6
JK		 3282e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3283{
3284 uint32_t swfw_sync = 0;
3285 uint32_t swmask = mask;
3286 uint32_t fwmask = mask << 16;
3287 int32_t timeout = 200;
3288
3289 DEBUGFUNC("e1000_swfw_sync_acquire");
3290
cd94dd0b
AK		 3291 if (hw->swfwhw_semaphore_present)
3292 return e1000_get_software_flag(hw);
3293
6418ecc6
JK		 3294 if (!hw->swfw_sync_present)
3295 return e1000_get_hw_eeprom_semaphore(hw);
3296
8fc897b0 3297 while (timeout) {
6418ecc6
JK		 3298 if (e1000_get_hw_eeprom_semaphore(hw))
3299 return -E1000_ERR_SWFW_SYNC;
3300
3301 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3302 if (!(swfw_sync & (fwmask | swmask))) {
3303 break;
3304 }
3305
3306 /* firmware currently using resource (fwmask) */
3307 /* or other software thread currently using resource (swmask) */
3308 e1000_put_hw_eeprom_semaphore(hw);
3309 msec_delay_irq(5);
3310 timeout--;
3311 }
3312
3313 if (!timeout) {
3314 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3315 return -E1000_ERR_SWFW_SYNC;
3316 }
3317
3318 swfw_sync |= swmask;
3319 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3320
3321 e1000_put_hw_eeprom_semaphore(hw);
3322 return E1000_SUCCESS;
3323}
3324
e4c780b1 3325static void
6418ecc6
JK		 3326e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3327{
3328 uint32_t swfw_sync;
3329 uint32_t swmask = mask;
3330
3331 DEBUGFUNC("e1000_swfw_sync_release");
3332
cd94dd0b
AK		 3333 if (hw->swfwhw_semaphore_present) {
3334 e1000_release_software_flag(hw);
3335 return;
3336 }
3337
6418ecc6
JK		 3338 if (!hw->swfw_sync_present) {
3339 e1000_put_hw_eeprom_semaphore(hw);
3340 return;
3341 }
3342
3343 /* if (e1000_get_hw_eeprom_semaphore(hw))
3344 * return -E1000_ERR_SWFW_SYNC; */
3345 while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3346 /* empty */
3347
3348 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3349 swfw_sync &= ~swmask;
3350 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3351
3352 e1000_put_hw_eeprom_semaphore(hw);
3353}
3354
1da177e4
LT		 3355/*****************************************************************************
3356* Reads the value from a PHY register, if the value is on a specific non zero
3357* page, sets the page first.
3358* hw - Struct containing variables accessed by shared code
3359* reg_addr - address of the PHY register to read
3360******************************************************************************/
3361int32_t
3362e1000_read_phy_reg(struct e1000_hw *hw,
3363 uint32_t reg_addr,
3364 uint16_t *phy_data)
3365{
3366 uint32_t ret_val;
6418ecc6 3367 uint16_t swfw;
1da177e4
LT		 3368
3369 DEBUGFUNC("e1000_read_phy_reg");
3370
6418ecc6
JK		 3371 if ((hw->mac_type == e1000_80003es2lan) &&
3372 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3373 swfw = E1000_SWFW_PHY1_SM;
3374 } else {
3375 swfw = E1000_SWFW_PHY0_SM;
3376 }
3377 if (e1000_swfw_sync_acquire(hw, swfw))
3378 return -E1000_ERR_SWFW_SYNC;
3379
cd94dd0b
AK		 3380 if ((hw->phy_type == e1000_phy_igp ||
3381 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3382 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3383 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3384 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3385 (uint16_t)reg_addr);
8fc897b0 3386 if (ret_val) {
6418ecc6 3387 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3388 return ret_val;
3389 }
6418ecc6
JK		 3390 } else if (hw->phy_type == e1000_phy_gg82563) {
3391 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3392 (hw->mac_type == e1000_80003es2lan)) {
3393 /* Select Configuration Page */
3394 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3395 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3396 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3397 } else {
3398 /* Use Alternative Page Select register to access
3399 * registers 30 and 31
3400 */
3401 ret_val = e1000_write_phy_reg_ex(hw,
3402 GG82563_PHY_PAGE_SELECT_ALT,
3403 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3404 }
3405
3406 if (ret_val) {
3407 e1000_swfw_sync_release(hw, swfw);
3408 return ret_val;
3409 }
3410 }
1da177e4
LT		 3411 }
3412
3413 ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3414 phy_data);
3415
6418ecc6 3416 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3417 return ret_val;
3418}
3419
3420int32_t
3421e1000_read_phy_reg_ex(struct e1000_hw *hw,
3422 uint32_t reg_addr,
3423 uint16_t *phy_data)
3424{
3425 uint32_t i;
3426 uint32_t mdic = 0;
3427 const uint32_t phy_addr = 1;
3428
3429 DEBUGFUNC("e1000_read_phy_reg_ex");
3430
8fc897b0 3431 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3432 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3433 return -E1000_ERR_PARAM;
3434 }
3435
8fc897b0 3436 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3437 /* Set up Op-code, Phy Address, and register address in the MDI
3438 * Control register. The MAC will take care of interfacing with the
3439 * PHY to retrieve the desired data.
3440 */
3441 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
3442 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3443 (E1000_MDIC_OP_READ));
3444
3445 E1000_WRITE_REG(hw, MDIC, mdic);
3446
3447 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3448 for (i = 0; i < 64; i++) {
1da177e4
LT		 3449 udelay(50);
3450 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3451 if (mdic & E1000_MDIC_READY) break;
1da177e4 3452 }
8fc897b0 3453 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3454 DEBUGOUT("MDI Read did not complete\n");
3455 return -E1000_ERR_PHY;
3456 }
8fc897b0 3457 if (mdic & E1000_MDIC_ERROR) {
1da177e4
LT		 3458 DEBUGOUT("MDI Error\n");
3459 return -E1000_ERR_PHY;
3460 }
3461 *phy_data = (uint16_t) mdic;
3462 } else {
3463 /* We must first send a preamble through the MDIO pin to signal the
3464 * beginning of an MII instruction. This is done by sending 32
3465 * consecutive "1" bits.
3466 */
3467 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3468
3469 /* Now combine the next few fields that are required for a read
3470 * operation. We use this method instead of calling the
3471 * e1000_shift_out_mdi_bits routine five different times. The format of
3472 * a MII read instruction consists of a shift out of 14 bits and is
3473 * defined as follows:
3474 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3475 * followed by a shift in of 18 bits. This first two bits shifted in
3476 * are TurnAround bits used to avoid contention on the MDIO pin when a
3477 * READ operation is performed. These two bits are thrown away
3478 * followed by a shift in of 16 bits which contains the desired data.
3479 */
3480 mdic = ((reg_addr) | (phy_addr << 5) |
3481 (PHY_OP_READ << 10) | (PHY_SOF << 12));
3482
3483 e1000_shift_out_mdi_bits(hw, mdic, 14);
3484
3485 /* Now that we've shifted out the read command to the MII, we need to
3486 * "shift in" the 16-bit value (18 total bits) of the requested PHY
3487 * register address.
3488 */
3489 *phy_data = e1000_shift_in_mdi_bits(hw);
3490 }
3491 return E1000_SUCCESS;
3492}
3493
3494/******************************************************************************
3495* Writes a value to a PHY register
3496*
3497* hw - Struct containing variables accessed by shared code
3498* reg_addr - address of the PHY register to write
3499* data - data to write to the PHY
3500******************************************************************************/
3501int32_t
3502e1000_write_phy_reg(struct e1000_hw *hw,
3503 uint32_t reg_addr,
3504 uint16_t phy_data)
3505{
3506 uint32_t ret_val;
6418ecc6 3507 uint16_t swfw;
1da177e4
LT		 3508
3509 DEBUGFUNC("e1000_write_phy_reg");
3510
6418ecc6
JK		 3511 if ((hw->mac_type == e1000_80003es2lan) &&
3512 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3513 swfw = E1000_SWFW_PHY1_SM;
3514 } else {
3515 swfw = E1000_SWFW_PHY0_SM;
3516 }
3517 if (e1000_swfw_sync_acquire(hw, swfw))
3518 return -E1000_ERR_SWFW_SYNC;
3519
cd94dd0b
AK		 3520 if ((hw->phy_type == e1000_phy_igp ||
3521 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 3522 hw->phy_type == e1000_phy_igp_2) &&
1da177e4
LT		 3523 (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3524 ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3525 (uint16_t)reg_addr);
8fc897b0 3526 if (ret_val) {
6418ecc6 3527 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3528 return ret_val;
3529 }
6418ecc6
JK		 3530 } else if (hw->phy_type == e1000_phy_gg82563) {
3531 if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) ||
3532 (hw->mac_type == e1000_80003es2lan)) {
3533 /* Select Configuration Page */
3534 if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3535 ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3536 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3537 } else {
3538 /* Use Alternative Page Select register to access
3539 * registers 30 and 31
3540 */
3541 ret_val = e1000_write_phy_reg_ex(hw,
3542 GG82563_PHY_PAGE_SELECT_ALT,
3543 (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3544 }
3545
3546 if (ret_val) {
3547 e1000_swfw_sync_release(hw, swfw);
3548 return ret_val;
3549 }
3550 }
1da177e4
LT		 3551 }
3552
3553 ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3554 phy_data);
3555
6418ecc6 3556 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3557 return ret_val;
3558}
3559
3560int32_t
3561e1000_write_phy_reg_ex(struct e1000_hw *hw,
3562 uint32_t reg_addr,
3563 uint16_t phy_data)
3564{
3565 uint32_t i;
3566 uint32_t mdic = 0;
3567 const uint32_t phy_addr = 1;
3568
3569 DEBUGFUNC("e1000_write_phy_reg_ex");
3570
8fc897b0 3571 if (reg_addr > MAX_PHY_REG_ADDRESS) {
1da177e4
LT		 3572 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3573 return -E1000_ERR_PARAM;
3574 }
3575
8fc897b0 3576 if (hw->mac_type > e1000_82543) {
1da177e4
LT		 3577 /* Set up Op-code, Phy Address, register address, and data intended
3578 * for the PHY register in the MDI Control register. The MAC will take
3579 * care of interfacing with the PHY to send the desired data.
3580 */
3581 mdic = (((uint32_t) phy_data) |
3582 (reg_addr << E1000_MDIC_REG_SHIFT) |
3583 (phy_addr << E1000_MDIC_PHY_SHIFT) |
3584 (E1000_MDIC_OP_WRITE));
3585
3586 E1000_WRITE_REG(hw, MDIC, mdic);
3587
3588 /* Poll the ready bit to see if the MDI read completed */
8fc897b0 3589 for (i = 0; i < 641; i++) {
1da177e4
LT		 3590 udelay(5);
3591 mdic = E1000_READ_REG(hw, MDIC);
8fc897b0 3592 if (mdic & E1000_MDIC_READY) break;
1da177e4 3593 }
8fc897b0 3594 if (!(mdic & E1000_MDIC_READY)) {
1da177e4
LT		 3595 DEBUGOUT("MDI Write did not complete\n");
3596 return -E1000_ERR_PHY;
3597 }
3598 } else {
3599 /* We'll need to use the SW defined pins to shift the write command
3600 * out to the PHY. We first send a preamble to the PHY to signal the
3601 * beginning of the MII instruction. This is done by sending 32
3602 * consecutive "1" bits.
3603 */
3604 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3605
3606 /* Now combine the remaining required fields that will indicate a
3607 * write operation. We use this method instead of calling the
3608 * e1000_shift_out_mdi_bits routine for each field in the command. The
3609 * format of a MII write instruction is as follows:
3610 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3611 */
3612 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
3613 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
3614 mdic <<= 16;
3615 mdic |= (uint32_t) phy_data;
3616
3617 e1000_shift_out_mdi_bits(hw, mdic, 32);
3618 }
3619
3620 return E1000_SUCCESS;
3621}
3622
e4c780b1 3623static int32_t
6418ecc6
JK		 3624e1000_read_kmrn_reg(struct e1000_hw *hw,
3625 uint32_t reg_addr,
3626 uint16_t *data)
3627{
3628 uint32_t reg_val;
3629 uint16_t swfw;
3630 DEBUGFUNC("e1000_read_kmrn_reg");
3631
3632 if ((hw->mac_type == e1000_80003es2lan) &&
3633 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3634 swfw = E1000_SWFW_PHY1_SM;
3635 } else {
3636 swfw = E1000_SWFW_PHY0_SM;
3637 }
3638 if (e1000_swfw_sync_acquire(hw, swfw))
3639 return -E1000_ERR_SWFW_SYNC;
3640
3641 /* Write register address */
3642 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3643 E1000_KUMCTRLSTA_OFFSET) |
3644 E1000_KUMCTRLSTA_REN;
3645 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3646 udelay(2);
3647
3648 /* Read the data returned */
3649 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3650 *data = (uint16_t)reg_val;
3651
3652 e1000_swfw_sync_release(hw, swfw);
3653 return E1000_SUCCESS;
3654}
3655
e4c780b1 3656static int32_t
6418ecc6
JK		 3657e1000_write_kmrn_reg(struct e1000_hw *hw,
3658 uint32_t reg_addr,
3659 uint16_t data)
3660{
3661 uint32_t reg_val;
3662 uint16_t swfw;
3663 DEBUGFUNC("e1000_write_kmrn_reg");
3664
3665 if ((hw->mac_type == e1000_80003es2lan) &&
3666 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3667 swfw = E1000_SWFW_PHY1_SM;
3668 } else {
3669 swfw = E1000_SWFW_PHY0_SM;
3670 }
3671 if (e1000_swfw_sync_acquire(hw, swfw))
3672 return -E1000_ERR_SWFW_SYNC;
3673
3674 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3675 E1000_KUMCTRLSTA_OFFSET) | data;
3676 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3677 udelay(2);
3678
3679 e1000_swfw_sync_release(hw, swfw);
3680 return E1000_SUCCESS;
3681}
2d7edb92 3682
1da177e4
LT		 3683/******************************************************************************
3684* Returns the PHY to the power-on reset state
3685*
3686* hw - Struct containing variables accessed by shared code
3687******************************************************************************/
2d7edb92 3688int32_t
1da177e4
LT		 3689e1000_phy_hw_reset(struct e1000_hw *hw)
3690{
3691 uint32_t ctrl, ctrl_ext;
3692 uint32_t led_ctrl;
2d7edb92 3693 int32_t ret_val;
6418ecc6 3694 uint16_t swfw;
1da177e4
LT		 3695
3696 DEBUGFUNC("e1000_phy_hw_reset");
3697
2d7edb92
MC		 3698 /* In the case of the phy reset being blocked, it's not an error, we
3699 * simply return success without performing the reset. */
3700 ret_val = e1000_check_phy_reset_block(hw);
3701 if (ret_val)
3702 return E1000_SUCCESS;
3703
1da177e4
LT		 3704 DEBUGOUT("Resetting Phy...\n");
3705
8fc897b0 3706 if (hw->mac_type > e1000_82543) {
6418ecc6
JK		 3707 if ((hw->mac_type == e1000_80003es2lan) &&
3708 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3709 swfw = E1000_SWFW_PHY1_SM;
3710 } else {
3711 swfw = E1000_SWFW_PHY0_SM;
3712 }
3713 if (e1000_swfw_sync_acquire(hw, swfw)) {
3714 e1000_release_software_semaphore(hw);
3715 return -E1000_ERR_SWFW_SYNC;
3716 }
1da177e4
LT		 3717 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3718 * bit. Then, take it out of reset.
76c224bc 3719 * For pre-e1000_82571 hardware, we delay for 10ms between the assert
fd803241 3720 * and deassert. For e1000_82571 hardware and later, we instead delay
0f15a8fa 3721 * for 50us between and 10ms after the deassertion.
1da177e4
LT		 3722 */
3723 ctrl = E1000_READ_REG(hw, CTRL);
3724 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3725 E1000_WRITE_FLUSH(hw);
76c224bc
AK		 3726
3727 if (hw->mac_type < e1000_82571)
fd803241 3728 msec_delay(10);
b55ccb35
JK		 3729 else
3730 udelay(100);
76c224bc 3731
1da177e4
LT		 3732 E1000_WRITE_REG(hw, CTRL, ctrl);
3733 E1000_WRITE_FLUSH(hw);
76c224bc 3734
fd803241 3735 if (hw->mac_type >= e1000_82571)
cd94dd0b 3736 msec_delay_irq(10);
6418ecc6 3737 e1000_swfw_sync_release(hw, swfw);
1da177e4
LT		 3738 } else {
3739 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3740 * bit to put the PHY into reset. Then, take it out of reset.
3741 */
3742 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3743 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3744 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3745 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3746 E1000_WRITE_FLUSH(hw);
3747 msec_delay(10);
3748 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3749 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3750 E1000_WRITE_FLUSH(hw);
3751 }
3752 udelay(150);
3753
8fc897b0 3754 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1da177e4
LT		 3755 /* Configure activity LED after PHY reset */
3756 led_ctrl = E1000_READ_REG(hw, LEDCTL);
3757 led_ctrl &= IGP_ACTIVITY_LED_MASK;
3758 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
3759 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3760 }
2d7edb92
MC		 3761
3762 /* Wait for FW to finish PHY configuration. */
3763 ret_val = e1000_get_phy_cfg_done(hw);
8fc897b0
AK		 3764 if (ret_val != E1000_SUCCESS)
3765 return ret_val;
6418ecc6 3766 e1000_release_software_semaphore(hw);
2d7edb92 3767
8fc897b0
AK		 3768 if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3769 ret_val = e1000_init_lcd_from_nvm(hw);
3770
2d7edb92 3771 return ret_val;
1da177e4
LT		 3772}
3773
3774/******************************************************************************
3775* Resets the PHY
3776*
3777* hw - Struct containing variables accessed by shared code
3778*
3779* Sets bit 15 of the MII Control regiser
3780******************************************************************************/
3781int32_t
3782e1000_phy_reset(struct e1000_hw *hw)
3783{
3784 int32_t ret_val;
3785 uint16_t phy_data;
3786
3787 DEBUGFUNC("e1000_phy_reset");
3788
2d7edb92
MC		 3789 /* In the case of the phy reset being blocked, it's not an error, we
3790 * simply return success without performing the reset. */
3791 ret_val = e1000_check_phy_reset_block(hw);
3792 if (ret_val)
3793 return E1000_SUCCESS;
3794
3795 switch (hw->mac_type) {
3796 case e1000_82541_rev_2:
868d5309
MC		 3797 case e1000_82571:
3798 case e1000_82572:
cd94dd0b 3799 case e1000_ich8lan:
2d7edb92 3800 ret_val = e1000_phy_hw_reset(hw);
8fc897b0 3801 if (ret_val)
2d7edb92 3802 return ret_val;
cd94dd0b 3803
2d7edb92
MC		 3804 break;
3805 default:
1da177e4 3806 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
8fc897b0 3807 if (ret_val)
1da177e4
LT		 3808 return ret_val;
3809
3810 phy_data |= MII_CR_RESET;
3811 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
8fc897b0 3812 if (ret_val)
1da177e4
LT		 3813 return ret_val;
3814
3815 udelay(1);
2d7edb92
MC		 3816 break;
3817 }
1da177e4 3818
8fc897b0 3819 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
1da177e4
LT		 3820 e1000_phy_init_script(hw);
3821
3822 return E1000_SUCCESS;
3823}
3824
d37ea5d5
AK		 3825/******************************************************************************
3826* Work-around for 82566 power-down: on D3 entry-
3827* 1) disable gigabit link
3828* 2) write VR power-down enable
3829* 3) read it back
3830* if successful continue, else issue LCD reset and repeat
3831*
3832* hw - struct containing variables accessed by shared code
3833******************************************************************************/
3834void
3835e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3836{
3837 int32_t reg;
3838 uint16_t phy_data;
3839 int32_t retry = 0;
3840
3841 DEBUGFUNC("e1000_phy_powerdown_workaround");
3842
3843 if (hw->phy_type != e1000_phy_igp_3)
3844 return;
3845
3846 do {
3847 /* Disable link */
3848 reg = E1000_READ_REG(hw, PHY_CTRL);
3849 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3850 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3851
3852 /* Write VR power-down enable */
3853 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3854 e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data |
3855 IGP3_VR_CTRL_MODE_SHUT);
3856
3857 /* Read it back and test */
3858 e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
3859 if ((phy_data & IGP3_VR_CTRL_MODE_SHUT) || retry)
3860 break;
3861
3862 /* Issue PHY reset and repeat at most one more time */
3863 reg = E1000_READ_REG(hw, CTRL);
3864 E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST);
3865 retry++;
3866 } while (retry);
3867
3868 return;
3869
3870}
3871
3872/******************************************************************************
3873* Work-around for 82566 Kumeran PCS lock loss:
3874* On link status change (i.e. PCI reset, speed change) and link is up and
3875* speed is gigabit-
3876* 0) if workaround is optionally disabled do nothing
3877* 1) wait 1ms for Kumeran link to come up
3878* 2) check Kumeran Diagnostic register PCS lock loss bit
3879* 3) if not set the link is locked (all is good), otherwise...
3880* 4) reset the PHY
3881* 5) repeat up to 10 times
3882* Note: this is only called for IGP3 copper when speed is 1gb.
3883*
3884* hw - struct containing variables accessed by shared code
3885******************************************************************************/
e4c780b1 3886static int32_t
d37ea5d5
AK		 3887e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
3888{
3889 int32_t ret_val;
3890 int32_t reg;
3891 int32_t cnt;
3892 uint16_t phy_data;
3893
3894 if (hw->kmrn_lock_loss_workaround_disabled)
3895 return E1000_SUCCESS;
3896
8fc897b0
AK		 3897 /* Make sure link is up before proceeding. If not just return.
3898 * Attempting this while link is negotiating fouled up link
d37ea5d5
AK		 3899 * stability */
3900 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3901 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3902
3903 if (phy_data & MII_SR_LINK_STATUS) {
3904 for (cnt = 0; cnt < 10; cnt++) {
3905 /* read once to clear */
3906 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3907 if (ret_val)
3908 return ret_val;
3909 /* and again to get new status */
3910 ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
3911 if (ret_val)
3912 return ret_val;
3913
3914 /* check for PCS lock */
3915 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3916 return E1000_SUCCESS;
3917
3918 /* Issue PHY reset */
3919 e1000_phy_hw_reset(hw);
3920 msec_delay_irq(5);
3921 }
3922 /* Disable GigE link negotiation */
3923 reg = E1000_READ_REG(hw, PHY_CTRL);
3924 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE |
3925 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3926
3927 /* unable to acquire PCS lock */
3928 return E1000_ERR_PHY;
3929 }
3930
3931 return E1000_SUCCESS;
3932}
3933
1da177e4
LT		 3934/******************************************************************************
3935* Probes the expected PHY address for known PHY IDs
3936*
3937* hw - Struct containing variables accessed by shared code
3938******************************************************************************/
d37ea5d5 3939int32_t
1da177e4
LT		 3940e1000_detect_gig_phy(struct e1000_hw *hw)
3941{
3942 int32_t phy_init_status, ret_val;
3943 uint16_t phy_id_high, phy_id_low;
3944 boolean_t match = FALSE;
3945
3946 DEBUGFUNC("e1000_detect_gig_phy");
3947
868d5309
MC		 3948 /* The 82571 firmware may still be configuring the PHY. In this
3949 * case, we cannot access the PHY until the configuration is done. So
3950 * we explicitly set the PHY values. */
cd94dd0b
AK		 3951 if (hw->mac_type == e1000_82571 ||
3952 hw->mac_type == e1000_82572) {
868d5309
MC		 3953 hw->phy_id = IGP01E1000_I_PHY_ID;
3954 hw->phy_type = e1000_phy_igp_2;
3955 return E1000_SUCCESS;
3956 }
3957
6418ecc6
JK		 3958 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
3959 * around that forces PHY page 0 to be set or the reads fail. The rest of
3960 * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
3961 * So for ESB-2 we need to have this set so our reads won't fail. If the
3962 * attached PHY is not a e1000_phy_gg82563, the routines below will figure
3963 * this out as well. */
3964 if (hw->mac_type == e1000_80003es2lan)
3965 hw->phy_type = e1000_phy_gg82563;
3966
1da177e4
LT		 3967 /* Read the PHY ID Registers to identify which PHY is onboard. */
3968 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
cd94dd0b 3969 if (ret_val)
1da177e4
LT		 3970 return ret_val;
3971
3972 hw->phy_id = (uint32_t) (phy_id_high << 16);
3973 udelay(20);
3974 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
8fc897b0 3975 if (ret_val)
1da177e4
LT		 3976 return ret_val;
3977
3978 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3979 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3980
8fc897b0 3981 switch (hw->mac_type) {
1da177e4 3982 case e1000_82543:
8fc897b0 3983 if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
1da177e4
LT		 3984 break;
3985 case e1000_82544:
8fc897b0 3986 if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
1da177e4
LT		 3987 break;
3988 case e1000_82540:
3989 case e1000_82545:
3990 case e1000_82545_rev_3:
3991 case e1000_82546:
3992 case e1000_82546_rev_3:
8fc897b0 3993 if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
1da177e4
LT		 3994 break;
3995 case e1000_82541:
3996 case e1000_82541_rev_2:
3997 case e1000_82547:
3998 case e1000_82547_rev_2:
8fc897b0 3999 if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
1da177e4 4000 break;
2d7edb92 4001 case e1000_82573:
8fc897b0 4002 if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
2d7edb92 4003 break;
6418ecc6
JK		 4004 case e1000_80003es2lan:
4005 if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4006 break;
cd94dd0b
AK		 4007 case e1000_ich8lan:
4008 if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4009 if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4010 if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4011 if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4012 break;
1da177e4
LT		 4013 default:
4014 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4015 return -E1000_ERR_CONFIG;
4016 }
4017 phy_init_status = e1000_set_phy_type(hw);
4018
4019 if ((match) && (phy_init_status == E1000_SUCCESS)) {
4020 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
4021 return E1000_SUCCESS;
4022 }
4023 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
4024 return -E1000_ERR_PHY;
4025}
4026
4027/******************************************************************************
4028* Resets the PHY's DSP
4029*
4030* hw - Struct containing variables accessed by shared code
4031******************************************************************************/
4032static int32_t
4033e1000_phy_reset_dsp(struct e1000_hw *hw)
4034{
4035 int32_t ret_val;
4036 DEBUGFUNC("e1000_phy_reset_dsp");
4037
4038 do {
6418ecc6
JK		 4039 if (hw->phy_type != e1000_phy_gg82563) {
4040 ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
8fc897b0 4041 if (ret_val) break;
6418ecc6 4042 }
1da177e4 4043 ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
8fc897b0 4044 if (ret_val) break;
1da177e4 4045 ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
8fc897b0 4046 if (ret_val) break;
1da177e4 4047 ret_val = E1000_SUCCESS;
8fc897b0 4048 } while (0);
1da177e4
LT		 4049
4050 return ret_val;
4051}
4052
4053/******************************************************************************
4054* Get PHY information from various PHY registers for igp PHY only.
4055*
4056* hw - Struct containing variables accessed by shared code
4057* phy_info - PHY information structure
4058******************************************************************************/
cff93eb3 4059static int32_t
1da177e4
LT		 4060e1000_phy_igp_get_info(struct e1000_hw *hw,
4061 struct e1000_phy_info *phy_info)
4062{
4063 int32_t ret_val;
4064 uint16_t phy_data, polarity, min_length, max_length, average;
4065
4066 DEBUGFUNC("e1000_phy_igp_get_info");
4067
4068 /* The downshift status is checked only once, after link is established,
4069 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4070 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4071
4072 /* IGP01E1000 does not need to support it. */
4073 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4074
4075 /* IGP01E1000 always correct polarity reversal */
4076 phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4077
4078 /* Check polarity status */
4079 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4080 if (ret_val)
1da177e4
LT		 4081 return ret_val;
4082
4083 phy_info->cable_polarity = polarity;
4084
4085 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
8fc897b0 4086 if (ret_val)
1da177e4
LT		 4087 return ret_val;
4088
4089 phy_info->mdix_mode = (phy_data & IGP01E1000_PSSR_MDIX) >>
4090 IGP01E1000_PSSR_MDIX_SHIFT;
4091
8fc897b0 4092 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 4093 IGP01E1000_PSSR_SPEED_1000MBPS) {
4094 /* Local/Remote Receiver Information are only valid at 1000 Mbps */
4095 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4096 if (ret_val)
1da177e4
LT		 4097 return ret_val;
4098
4099 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4100 SR_1000T_LOCAL_RX_STATUS_SHIFT;
4101 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4102 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4103
4104 /* Get cable length */
4105 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
8fc897b0 4106 if (ret_val)
1da177e4
LT		 4107 return ret_val;
4108
2d7edb92 4109 /* Translate to old method */
1da177e4
LT		 4110 average = (max_length + min_length) / 2;
4111
8fc897b0 4112 if (average <= e1000_igp_cable_length_50)
1da177e4 4113 phy_info->cable_length = e1000_cable_length_50;
8fc897b0 4114 else if (average <= e1000_igp_cable_length_80)
1da177e4 4115 phy_info->cable_length = e1000_cable_length_50_80;
8fc897b0 4116 else if (average <= e1000_igp_cable_length_110)
1da177e4 4117 phy_info->cable_length = e1000_cable_length_80_110;
8fc897b0 4118 else if (average <= e1000_igp_cable_length_140)
1da177e4
LT		 4119 phy_info->cable_length = e1000_cable_length_110_140;
4120 else
4121 phy_info->cable_length = e1000_cable_length_140;
4122 }
4123
4124 return E1000_SUCCESS;
4125}
4126
d37ea5d5
AK		 4127/******************************************************************************
4128* Get PHY information from various PHY registers for ife PHY only.
4129*
4130* hw - Struct containing variables accessed by shared code
4131* phy_info - PHY information structure
4132******************************************************************************/
e4c780b1 4133static int32_t
d37ea5d5
AK		 4134e1000_phy_ife_get_info(struct e1000_hw *hw,
4135 struct e1000_phy_info *phy_info)
4136{
4137 int32_t ret_val;
4138 uint16_t phy_data, polarity;
4139
4140 DEBUGFUNC("e1000_phy_ife_get_info");
4141
4142 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4143 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4144
4145 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4146 if (ret_val)
4147 return ret_val;
4148 phy_info->polarity_correction =
4149 (phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4150 IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT;
4151
4152 if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4153 ret_val = e1000_check_polarity(hw, &polarity);
4154 if (ret_val)
4155 return ret_val;
4156 } else {
4157 /* Polarity is forced. */
4158 polarity = (phy_data & IFE_PSC_FORCE_POLARITY) >>
4159 IFE_PSC_FORCE_POLARITY_SHIFT;
4160 }
4161 phy_info->cable_polarity = polarity;
4162
4163 ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4164 if (ret_val)
4165 return ret_val;
4166
4167 phy_info->mdix_mode =
4168 (phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >>
4169 IFE_PMC_MDIX_MODE_SHIFT;
4170
4171 return E1000_SUCCESS;
4172}
4173
1da177e4
LT		 4174/******************************************************************************
4175* Get PHY information from various PHY registers fot m88 PHY only.
4176*
4177* hw - Struct containing variables accessed by shared code
4178* phy_info - PHY information structure
4179******************************************************************************/
3ad2cc67 4180static int32_t
1da177e4
LT		 4181e1000_phy_m88_get_info(struct e1000_hw *hw,
4182 struct e1000_phy_info *phy_info)
4183{
4184 int32_t ret_val;
4185 uint16_t phy_data, polarity;
4186
4187 DEBUGFUNC("e1000_phy_m88_get_info");
4188
4189 /* The downshift status is checked only once, after link is established,
4190 * and it stored in the hw->speed_downgraded parameter. */
2d7edb92 4191 phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
1da177e4
LT		 4192
4193 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
8fc897b0 4194 if (ret_val)
1da177e4
LT		 4195 return ret_val;
4196
4197 phy_info->extended_10bt_distance =
4198 (phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4199 M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT;
4200 phy_info->polarity_correction =
4201 (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4202 M88E1000_PSCR_POLARITY_REVERSAL_SHIFT;
4203
4204 /* Check polarity status */
4205 ret_val = e1000_check_polarity(hw, &polarity);
8fc897b0 4206 if (ret_val)
76c224bc 4207 return ret_val;
1da177e4
LT		 4208 phy_info->cable_polarity = polarity;
4209
4210 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
8fc897b0 4211 if (ret_val)
1da177e4
LT		 4212 return ret_val;
4213
4214 phy_info->mdix_mode = (phy_data & M88E1000_PSSR_MDIX) >>
4215 M88E1000_PSSR_MDIX_SHIFT;
4216
4217 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4218 /* Cable Length Estimation and Local/Remote Receiver Information
4219 * are only valid at 1000 Mbps.
4220 */
6418ecc6
JK		 4221 if (hw->phy_type != e1000_phy_gg82563) {
4222 phy_info->cable_length = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4223 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4224 } else {
4225 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4226 &phy_data);
4227 if (ret_val)
4228 return ret_val;
4229
4230 phy_info->cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
4231 }
1da177e4
LT		 4232
4233 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
8fc897b0 4234 if (ret_val)
1da177e4
LT		 4235 return ret_val;
4236
4237 phy_info->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4238 SR_1000T_LOCAL_RX_STATUS_SHIFT;
4239
4240 phy_info->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4241 SR_1000T_REMOTE_RX_STATUS_SHIFT;
4242 }
4243
4244 return E1000_SUCCESS;
4245}
4246
4247/******************************************************************************
4248* Get PHY information from various PHY registers
4249*
4250* hw - Struct containing variables accessed by shared code
4251* phy_info - PHY information structure
4252******************************************************************************/
4253int32_t
4254e1000_phy_get_info(struct e1000_hw *hw,
4255 struct e1000_phy_info *phy_info)
4256{
4257 int32_t ret_val;
4258 uint16_t phy_data;
4259
4260 DEBUGFUNC("e1000_phy_get_info");
4261
4262 phy_info->cable_length = e1000_cable_length_undefined;
4263 phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4264 phy_info->cable_polarity = e1000_rev_polarity_undefined;
4265 phy_info->downshift = e1000_downshift_undefined;
4266 phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4267 phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4268 phy_info->local_rx = e1000_1000t_rx_status_undefined;
4269 phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4270
8fc897b0 4271 if (hw->media_type != e1000_media_type_copper) {
1da177e4
LT		 4272 DEBUGOUT("PHY info is only valid for copper media\n");
4273 return -E1000_ERR_CONFIG;
4274 }
4275
4276 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4277 if (ret_val)
1da177e4
LT		 4278 return ret_val;
4279
4280 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
8fc897b0 4281 if (ret_val)
1da177e4
LT		 4282 return ret_val;
4283
8fc897b0 4284 if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
1da177e4
LT		 4285 DEBUGOUT("PHY info is only valid if link is up\n");
4286 return -E1000_ERR_CONFIG;
4287 }
4288
cd94dd0b
AK		 4289 if (hw->phy_type == e1000_phy_igp ||
4290 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 4291 hw->phy_type == e1000_phy_igp_2)
1da177e4 4292 return e1000_phy_igp_get_info(hw, phy_info);
cd94dd0b
AK		 4293 else if (hw->phy_type == e1000_phy_ife)
4294 return e1000_phy_ife_get_info(hw, phy_info);
1da177e4
LT		 4295 else
4296 return e1000_phy_m88_get_info(hw, phy_info);
4297}
4298
4299int32_t
4300e1000_validate_mdi_setting(struct e1000_hw *hw)
4301{
4302 DEBUGFUNC("e1000_validate_mdi_settings");
4303
8fc897b0 4304 if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) {
1da177e4
LT		 4305 DEBUGOUT("Invalid MDI setting detected\n");
4306 hw->mdix = 1;
4307 return -E1000_ERR_CONFIG;
4308 }
4309 return E1000_SUCCESS;
4310}
4311
4312
4313/******************************************************************************
4314 * Sets up eeprom variables in the hw struct. Must be called after mac_type
0f15a8fa
JK		 4315 * is configured. Additionally, if this is ICH8, the flash controller GbE
4316 * registers must be mapped, or this will crash.
1da177e4
LT		 4317 *
4318 * hw - Struct containing variables accessed by shared code
4319 *****************************************************************************/
2d7edb92 4320int32_t
1da177e4
LT		 4321e1000_init_eeprom_params(struct e1000_hw *hw)
4322{
4323 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4324 uint32_t eecd = E1000_READ_REG(hw, EECD);
2d7edb92 4325 int32_t ret_val = E1000_SUCCESS;
1da177e4
LT		 4326 uint16_t eeprom_size;
4327
4328 DEBUGFUNC("e1000_init_eeprom_params");
4329
4330 switch (hw->mac_type) {
4331 case e1000_82542_rev2_0:
4332 case e1000_82542_rev2_1:
4333 case e1000_82543:
4334 case e1000_82544:
4335 eeprom->type = e1000_eeprom_microwire;
4336 eeprom->word_size = 64;
4337 eeprom->opcode_bits = 3;
4338 eeprom->address_bits = 6;
4339 eeprom->delay_usec = 50;
2d7edb92
MC		 4340 eeprom->use_eerd = FALSE;
4341 eeprom->use_eewr = FALSE;
1da177e4
LT		 4342 break;
4343 case e1000_82540:
4344 case e1000_82545:
4345 case e1000_82545_rev_3:
4346 case e1000_82546:
4347 case e1000_82546_rev_3:
4348 eeprom->type = e1000_eeprom_microwire;
4349 eeprom->opcode_bits = 3;
4350 eeprom->delay_usec = 50;
8fc897b0 4351 if (eecd & E1000_EECD_SIZE) {
1da177e4
LT		 4352 eeprom->word_size = 256;
4353 eeprom->address_bits = 8;
4354 } else {
4355 eeprom->word_size = 64;
4356 eeprom->address_bits = 6;
4357 }
2d7edb92
MC		 4358 eeprom->use_eerd = FALSE;
4359 eeprom->use_eewr = FALSE;
1da177e4
LT		 4360 break;
4361 case e1000_82541:
4362 case e1000_82541_rev_2:
4363 case e1000_82547:
4364 case e1000_82547_rev_2:
4365 if (eecd & E1000_EECD_TYPE) {
4366 eeprom->type = e1000_eeprom_spi;
4367 eeprom->opcode_bits = 8;
4368 eeprom->delay_usec = 1;
4369 if (eecd & E1000_EECD_ADDR_BITS) {
4370 eeprom->page_size = 32;
4371 eeprom->address_bits = 16;
4372 } else {
4373 eeprom->page_size = 8;
4374 eeprom->address_bits = 8;
4375 }
4376 } else {
4377 eeprom->type = e1000_eeprom_microwire;
4378 eeprom->opcode_bits = 3;
4379 eeprom->delay_usec = 50;
4380 if (eecd & E1000_EECD_ADDR_BITS) {
4381 eeprom->word_size = 256;
4382 eeprom->address_bits = 8;
4383 } else {
4384 eeprom->word_size = 64;
4385 eeprom->address_bits = 6;
4386 }
4387 }
2d7edb92
MC		 4388 eeprom->use_eerd = FALSE;
4389 eeprom->use_eewr = FALSE;
4390 break;
868d5309
MC		 4391 case e1000_82571:
4392 case e1000_82572:
4393 eeprom->type = e1000_eeprom_spi;
4394 eeprom->opcode_bits = 8;
4395 eeprom->delay_usec = 1;
4396 if (eecd & E1000_EECD_ADDR_BITS) {
4397 eeprom->page_size = 32;
4398 eeprom->address_bits = 16;
4399 } else {
4400 eeprom->page_size = 8;
4401 eeprom->address_bits = 8;
4402 }
4403 eeprom->use_eerd = FALSE;
4404 eeprom->use_eewr = FALSE;
4405 break;
2d7edb92
MC		 4406 case e1000_82573:
4407 eeprom->type = e1000_eeprom_spi;
4408 eeprom->opcode_bits = 8;
4409 eeprom->delay_usec = 1;
4410 if (eecd & E1000_EECD_ADDR_BITS) {
4411 eeprom->page_size = 32;
4412 eeprom->address_bits = 16;
4413 } else {
4414 eeprom->page_size = 8;
4415 eeprom->address_bits = 8;
4416 }
4417 eeprom->use_eerd = TRUE;
4418 eeprom->use_eewr = TRUE;
8fc897b0 4419 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
2d7edb92
MC		 4420 eeprom->type = e1000_eeprom_flash;
4421 eeprom->word_size = 2048;
4422
4423 /* Ensure that the Autonomous FLASH update bit is cleared due to
4424 * Flash update issue on parts which use a FLASH for NVM. */
4425 eecd &= ~E1000_EECD_AUPDEN;
4426 E1000_WRITE_REG(hw, EECD, eecd);
4427 }
1da177e4 4428 break;
6418ecc6
JK		 4429 case e1000_80003es2lan:
4430 eeprom->type = e1000_eeprom_spi;
4431 eeprom->opcode_bits = 8;
4432 eeprom->delay_usec = 1;
4433 if (eecd & E1000_EECD_ADDR_BITS) {
4434 eeprom->page_size = 32;
4435 eeprom->address_bits = 16;
4436 } else {
4437 eeprom->page_size = 8;
4438 eeprom->address_bits = 8;
4439 }
4440 eeprom->use_eerd = TRUE;
4441 eeprom->use_eewr = FALSE;
4442 break;
cd94dd0b
AK		 4443 case e1000_ich8lan:
4444 {
4445 int32_t i = 0;
4446 uint32_t flash_size = E1000_READ_ICH8_REG(hw, ICH8_FLASH_GFPREG);
4447
4448 eeprom->type = e1000_eeprom_ich8;
4449 eeprom->use_eerd = FALSE;
4450 eeprom->use_eewr = FALSE;
4451 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4452
4453 /* Zero the shadow RAM structure. But don't load it from NVM
4454 * so as to save time for driver init */
4455 if (hw->eeprom_shadow_ram != NULL) {
4456 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4457 hw->eeprom_shadow_ram[i].modified = FALSE;
4458 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4459 }
4460 }
4461
4462 hw->flash_base_addr = (flash_size & ICH8_GFPREG_BASE_MASK) *
4463 ICH8_FLASH_SECTOR_SIZE;
4464
4465 hw->flash_bank_size = ((flash_size >> 16) & ICH8_GFPREG_BASE_MASK) + 1;
4466 hw->flash_bank_size -= (flash_size & ICH8_GFPREG_BASE_MASK);
4467 hw->flash_bank_size *= ICH8_FLASH_SECTOR_SIZE;
4468 hw->flash_bank_size /= 2 * sizeof(uint16_t);
4469
4470 break;
4471 }
1da177e4
LT		 4472 default:
4473 break;
4474 }
4475
4476 if (eeprom->type == e1000_eeprom_spi) {
2d7edb92
MC		 4477 /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4478 * 32KB (incremented by powers of 2).
4479 */
8fc897b0 4480 if (hw->mac_type <= e1000_82547_rev_2) {
2d7edb92
MC		 4481 /* Set to default value for initial eeprom read. */
4482 eeprom->word_size = 64;
4483 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
8fc897b0 4484 if (ret_val)
2d7edb92
MC		 4485 return ret_val;
4486 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4487 /* 256B eeprom size was not supported in earlier hardware, so we
4488 * bump eeprom_size up one to ensure that "1" (which maps to 256B)
4489 * is never the result used in the shifting logic below. */
8fc897b0 4490 if (eeprom_size)
2d7edb92
MC		 4491 eeprom_size++;
4492 } else {
4493 eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4494 E1000_EECD_SIZE_EX_SHIFT);
1da177e4 4495 }
2d7edb92
MC		 4496
4497 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
1da177e4 4498 }
2d7edb92 4499 return ret_val;
1da177e4
LT		 4500}
4501
4502/******************************************************************************
4503 * Raises the EEPROM's clock input.
4504 *
4505 * hw - Struct containing variables accessed by shared code
4506 * eecd - EECD's current value
4507 *****************************************************************************/
4508static void
4509e1000_raise_ee_clk(struct e1000_hw *hw,
4510 uint32_t *eecd)
4511{
4512 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
4513 * wait <delay> microseconds.
4514 */
4515 *eecd = *eecd | E1000_EECD_SK;
4516 E1000_WRITE_REG(hw, EECD, *eecd);
4517 E1000_WRITE_FLUSH(hw);
4518 udelay(hw->eeprom.delay_usec);
4519}
4520
4521/******************************************************************************
4522 * Lowers the EEPROM's clock input.
4523 *
4524 * hw - Struct containing variables accessed by shared code
4525 * eecd - EECD's current value
4526 *****************************************************************************/
4527static void
4528e1000_lower_ee_clk(struct e1000_hw *hw,
4529 uint32_t *eecd)
4530{
4531 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4532 * wait 50 microseconds.
4533 */
4534 *eecd = *eecd & ~E1000_EECD_SK;
4535 E1000_WRITE_REG(hw, EECD, *eecd);
4536 E1000_WRITE_FLUSH(hw);
4537 udelay(hw->eeprom.delay_usec);
4538}
4539
4540/******************************************************************************
4541 * Shift data bits out to the EEPROM.
4542 *
4543 * hw - Struct containing variables accessed by shared code
4544 * data - data to send to the EEPROM
4545 * count - number of bits to shift out
4546 *****************************************************************************/
4547static void
4548e1000_shift_out_ee_bits(struct e1000_hw *hw,
4549 uint16_t data,
4550 uint16_t count)
4551{
4552 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4553 uint32_t eecd;
4554 uint32_t mask;
4555
4556 /* We need to shift "count" bits out to the EEPROM. So, value in the
4557 * "data" parameter will be shifted out to the EEPROM one bit at a time.
4558 * In order to do this, "data" must be broken down into bits.
4559 */
4560 mask = 0x01 << (count - 1);
4561 eecd = E1000_READ_REG(hw, EECD);
4562 if (eeprom->type == e1000_eeprom_microwire) {
4563 eecd &= ~E1000_EECD_DO;
4564 } else if (eeprom->type == e1000_eeprom_spi) {
4565 eecd |= E1000_EECD_DO;
4566 }
4567 do {
4568 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4569 * and then raising and then lowering the clock (the SK bit controls
4570 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4571 * by setting "DI" to "0" and then raising and then lowering the clock.
4572 */
4573 eecd &= ~E1000_EECD_DI;
4574
8fc897b0 4575 if (data & mask)
1da177e4
LT		 4576 eecd |= E1000_EECD_DI;
4577
4578 E1000_WRITE_REG(hw, EECD, eecd);
4579 E1000_WRITE_FLUSH(hw);
4580
4581 udelay(eeprom->delay_usec);
4582
4583 e1000_raise_ee_clk(hw, &eecd);
4584 e1000_lower_ee_clk(hw, &eecd);
4585
4586 mask = mask >> 1;
4587
8fc897b0 4588 } while (mask);
1da177e4
LT		 4589
4590 /* We leave the "DI" bit set to "0" when we leave this routine. */
4591 eecd &= ~E1000_EECD_DI;
4592 E1000_WRITE_REG(hw, EECD, eecd);
4593}
4594
4595/******************************************************************************
4596 * Shift data bits in from the EEPROM
4597 *
4598 * hw - Struct containing variables accessed by shared code
4599 *****************************************************************************/
4600static uint16_t
4601e1000_shift_in_ee_bits(struct e1000_hw *hw,
4602 uint16_t count)
4603{
4604 uint32_t eecd;
4605 uint32_t i;
4606 uint16_t data;
4607
4608 /* In order to read a register from the EEPROM, we need to shift 'count'
4609 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
4610 * input to the EEPROM (setting the SK bit), and then reading the value of
4611 * the "DO" bit. During this "shifting in" process the "DI" bit should
4612 * always be clear.
4613 */
4614
4615 eecd = E1000_READ_REG(hw, EECD);
4616
4617 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
4618 data = 0;
4619
8fc897b0 4620 for (i = 0; i < count; i++) {
1da177e4
LT		 4621 data = data << 1;
4622 e1000_raise_ee_clk(hw, &eecd);
4623
4624 eecd = E1000_READ_REG(hw, EECD);
4625
4626 eecd &= ~(E1000_EECD_DI);
8fc897b0 4627 if (eecd & E1000_EECD_DO)
1da177e4
LT		 4628 data |= 1;
4629
4630 e1000_lower_ee_clk(hw, &eecd);
4631 }
4632
4633 return data;
4634}
4635
4636/******************************************************************************
4637 * Prepares EEPROM for access
4638 *
4639 * hw - Struct containing variables accessed by shared code
4640 *
4641 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4642 * function should be called before issuing a command to the EEPROM.
4643 *****************************************************************************/
4644static int32_t
4645e1000_acquire_eeprom(struct e1000_hw *hw)
4646{
4647 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4648 uint32_t eecd, i=0;
4649
4650 DEBUGFUNC("e1000_acquire_eeprom");
4651
6418ecc6
JK		 4652 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4653 return -E1000_ERR_SWFW_SYNC;
1da177e4
LT		 4654 eecd = E1000_READ_REG(hw, EECD);
4655
2d7edb92 4656 if (hw->mac_type != e1000_82573) {
868d5309 4657 /* Request EEPROM Access */
8fc897b0 4658 if (hw->mac_type > e1000_82544) {
868d5309 4659 eecd |= E1000_EECD_REQ;
1da177e4 4660 E1000_WRITE_REG(hw, EECD, eecd);
868d5309 4661 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 4662 while ((!(eecd & E1000_EECD_GNT)) &&
868d5309
MC		 4663 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4664 i++;
4665 udelay(5);
4666 eecd = E1000_READ_REG(hw, EECD);
4667 }
8fc897b0 4668 if (!(eecd & E1000_EECD_GNT)) {
868d5309
MC		 4669 eecd &= ~E1000_EECD_REQ;
4670 E1000_WRITE_REG(hw, EECD, eecd);
4671 DEBUGOUT("Could not acquire EEPROM grant\n");
6418ecc6 4672 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
868d5309
MC		 4673 return -E1000_ERR_EEPROM;
4674 }
1da177e4
LT		 4675 }
4676 }
4677
4678 /* Setup EEPROM for Read/Write */
4679
4680 if (eeprom->type == e1000_eeprom_microwire) {
4681 /* Clear SK and DI */
4682 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
4683 E1000_WRITE_REG(hw, EECD, eecd);
4684
4685 /* Set CS */
4686 eecd |= E1000_EECD_CS;
4687 E1000_WRITE_REG(hw, EECD, eecd);
4688 } else if (eeprom->type == e1000_eeprom_spi) {
4689 /* Clear SK and CS */
4690 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4691 E1000_WRITE_REG(hw, EECD, eecd);
4692 udelay(1);
4693 }
4694
4695 return E1000_SUCCESS;
4696}
4697
4698/******************************************************************************
4699 * Returns EEPROM to a "standby" state
4700 *
4701 * hw - Struct containing variables accessed by shared code
4702 *****************************************************************************/
4703static void
4704e1000_standby_eeprom(struct e1000_hw *hw)
4705{
4706 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4707 uint32_t eecd;
4708
4709 eecd = E1000_READ_REG(hw, EECD);
4710
8fc897b0 4711 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 4712 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
4713 E1000_WRITE_REG(hw, EECD, eecd);
4714 E1000_WRITE_FLUSH(hw);
4715 udelay(eeprom->delay_usec);
4716
4717 /* Clock high */
4718 eecd |= E1000_EECD_SK;
4719 E1000_WRITE_REG(hw, EECD, eecd);
4720 E1000_WRITE_FLUSH(hw);
4721 udelay(eeprom->delay_usec);
4722
4723 /* Select EEPROM */
4724 eecd |= E1000_EECD_CS;
4725 E1000_WRITE_REG(hw, EECD, eecd);
4726 E1000_WRITE_FLUSH(hw);
4727 udelay(eeprom->delay_usec);
4728
4729 /* Clock low */
4730 eecd &= ~E1000_EECD_SK;
4731 E1000_WRITE_REG(hw, EECD, eecd);
4732 E1000_WRITE_FLUSH(hw);
4733 udelay(eeprom->delay_usec);
8fc897b0 4734 } else if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 4735 /* Toggle CS to flush commands */
4736 eecd |= E1000_EECD_CS;
4737 E1000_WRITE_REG(hw, EECD, eecd);
4738 E1000_WRITE_FLUSH(hw);
4739 udelay(eeprom->delay_usec);
4740 eecd &= ~E1000_EECD_CS;
4741 E1000_WRITE_REG(hw, EECD, eecd);
4742 E1000_WRITE_FLUSH(hw);
4743 udelay(eeprom->delay_usec);
4744 }
4745}
4746
4747/******************************************************************************
4748 * Terminates a command by inverting the EEPROM's chip select pin
4749 *
4750 * hw - Struct containing variables accessed by shared code
4751 *****************************************************************************/
4752static void
4753e1000_release_eeprom(struct e1000_hw *hw)
4754{
4755 uint32_t eecd;
4756
4757 DEBUGFUNC("e1000_release_eeprom");
4758
4759 eecd = E1000_READ_REG(hw, EECD);
4760
4761 if (hw->eeprom.type == e1000_eeprom_spi) {
4762 eecd |= E1000_EECD_CS; /* Pull CS high */
4763 eecd &= ~E1000_EECD_SK; /* Lower SCK */
4764
4765 E1000_WRITE_REG(hw, EECD, eecd);
4766
4767 udelay(hw->eeprom.delay_usec);
8fc897b0 4768 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
1da177e4
LT		 4769 /* cleanup eeprom */
4770
4771 /* CS on Microwire is active-high */
4772 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
4773
4774 E1000_WRITE_REG(hw, EECD, eecd);
4775
4776 /* Rising edge of clock */
4777 eecd |= E1000_EECD_SK;
4778 E1000_WRITE_REG(hw, EECD, eecd);
4779 E1000_WRITE_FLUSH(hw);
4780 udelay(hw->eeprom.delay_usec);
4781
4782 /* Falling edge of clock */
4783 eecd &= ~E1000_EECD_SK;
4784 E1000_WRITE_REG(hw, EECD, eecd);
4785 E1000_WRITE_FLUSH(hw);
4786 udelay(hw->eeprom.delay_usec);
4787 }
4788
4789 /* Stop requesting EEPROM access */
8fc897b0 4790 if (hw->mac_type > e1000_82544) {
1da177e4
LT		 4791 eecd &= ~E1000_EECD_REQ;
4792 E1000_WRITE_REG(hw, EECD, eecd);
4793 }
2d7edb92 4794
6418ecc6 4795 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
1da177e4
LT		 4796}
4797
4798/******************************************************************************
4799 * Reads a 16 bit word from the EEPROM.
4800 *
4801 * hw - Struct containing variables accessed by shared code
4802 *****************************************************************************/
4803int32_t
4804e1000_spi_eeprom_ready(struct e1000_hw *hw)
4805{
4806 uint16_t retry_count = 0;
4807 uint8_t spi_stat_reg;
4808
4809 DEBUGFUNC("e1000_spi_eeprom_ready");
4810
4811 /* Read "Status Register" repeatedly until the LSB is cleared. The
4812 * EEPROM will signal that the command has been completed by clearing
4813 * bit 0 of the internal status register. If it's not cleared within
4814 * 5 milliseconds, then error out.
4815 */
4816 retry_count = 0;
4817 do {
4818 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
4819 hw->eeprom.opcode_bits);
4820 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
4821 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
4822 break;
4823
4824 udelay(5);
4825 retry_count += 5;
4826
4827 e1000_standby_eeprom(hw);
8fc897b0 4828 } while (retry_count < EEPROM_MAX_RETRY_SPI);
1da177e4
LT		 4829
4830 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
4831 * only 0-5mSec on 5V devices)
4832 */
8fc897b0 4833 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
1da177e4
LT		 4834 DEBUGOUT("SPI EEPROM Status error\n");
4835 return -E1000_ERR_EEPROM;
4836 }
4837
4838 return E1000_SUCCESS;
4839}
4840
4841/******************************************************************************
4842 * Reads a 16 bit word from the EEPROM.
4843 *
4844 * hw - Struct containing variables accessed by shared code
4845 * offset - offset of word in the EEPROM to read
4846 * data - word read from the EEPROM
4847 * words - number of words to read
4848 *****************************************************************************/
4849int32_t
4850e1000_read_eeprom(struct e1000_hw *hw,
4851 uint16_t offset,
4852 uint16_t words,
4853 uint16_t *data)
4854{
4855 struct e1000_eeprom_info *eeprom = &hw->eeprom;
4856 uint32_t i = 0;
2d7edb92 4857 int32_t ret_val;
1da177e4
LT		 4858
4859 DEBUGFUNC("e1000_read_eeprom");
2d7edb92 4860
1da177e4
LT		 4861 /* A check for invalid values: offset too large, too many words, and not
4862 * enough words.
4863 */
8fc897b0 4864 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4
LT		 4865 (words == 0)) {
4866 DEBUGOUT("\"words\" parameter out of bounds\n");
4867 return -E1000_ERR_EEPROM;
4868 }
4869
4d351858
JK		 4870 /* FLASH reads without acquiring the semaphore are safe */
4871 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
8fc897b0 4872 hw->eeprom.use_eerd == FALSE) {
4d351858 4873 switch (hw->mac_type) {
6418ecc6
JK		 4874 case e1000_80003es2lan:
4875 break;
4d351858
JK		 4876 default:
4877 /* Prepare the EEPROM for reading */
4878 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
4879 return -E1000_ERR_EEPROM;
4880 break;
4881 }
2d7edb92
MC		 4882 }
4883
96838a40 4884 if (eeprom->use_eerd == TRUE) {
2d7edb92
MC		 4885 ret_val = e1000_read_eeprom_eerd(hw, offset, words, data);
4886 if ((e1000_is_onboard_nvm_eeprom(hw) == TRUE) ||
4887 (hw->mac_type != e1000_82573))
4888 e1000_release_eeprom(hw);
4889 return ret_val;
4890 }
1da177e4 4891
cd94dd0b
AK		 4892 if (eeprom->type == e1000_eeprom_ich8)
4893 return e1000_read_eeprom_ich8(hw, offset, words, data);
4894
4895 if (eeprom->type == e1000_eeprom_spi) {
1da177e4
LT		 4896 uint16_t word_in;
4897 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
4898
8fc897b0 4899 if (e1000_spi_eeprom_ready(hw)) {
1da177e4
LT		 4900 e1000_release_eeprom(hw);
4901 return -E1000_ERR_EEPROM;
4902 }
4903
4904 e1000_standby_eeprom(hw);
4905
4906 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 4907 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 4908 read_opcode |= EEPROM_A8_OPCODE_SPI;
4909
4910 /* Send the READ command (opcode + addr) */
4911 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
4912 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
4913
4914 /* Read the data. The address of the eeprom internally increments with
4915 * each byte (spi) being read, saving on the overhead of eeprom setup
4916 * and tear-down. The address counter will roll over if reading beyond
4917 * the size of the eeprom, thus allowing the entire memory to be read
4918 * starting from any offset. */
4919 for (i = 0; i < words; i++) {
4920 word_in = e1000_shift_in_ee_bits(hw, 16);
4921 data[i] = (word_in >> 8) | (word_in << 8);
4922 }
8fc897b0 4923 } else if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 4924 for (i = 0; i < words; i++) {
4925 /* Send the READ command (opcode + addr) */
4926 e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
4927 eeprom->opcode_bits);
4928 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
4929 eeprom->address_bits);
4930
4931 /* Read the data. For microwire, each word requires the overhead
4932 * of eeprom setup and tear-down. */
4933 data[i] = e1000_shift_in_ee_bits(hw, 16);
4934 e1000_standby_eeprom(hw);
4935 }
4936 }
4937
4938 /* End this read operation */
4939 e1000_release_eeprom(hw);
4940
4941 return E1000_SUCCESS;
4942}
4943
4944/******************************************************************************
2d7edb92 4945 * Reads a 16 bit word from the EEPROM using the EERD register.
1da177e4
LT		 4946 *
4947 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 4948 * offset - offset of word in the EEPROM to read
4949 * data - word read from the EEPROM
4950 * words - number of words to read
1da177e4 4951 *****************************************************************************/
3ad2cc67 4952static int32_t
2d7edb92
MC		 4953e1000_read_eeprom_eerd(struct e1000_hw *hw,
4954 uint16_t offset,
4955 uint16_t words,
4956 uint16_t *data)
1da177e4 4957{
2d7edb92
MC		 4958 uint32_t i, eerd = 0;
4959 int32_t error = 0;
1da177e4 4960
2d7edb92
MC		 4961 for (i = 0; i < words; i++) {
4962 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
4963 E1000_EEPROM_RW_REG_START;
1da177e4 4964
2d7edb92
MC		 4965 E1000_WRITE_REG(hw, EERD, eerd);
4966 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
76c224bc 4967
8fc897b0 4968 if (error) {
2d7edb92 4969 break;
1da177e4 4970 }
2d7edb92 4971 data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
76c224bc 4972
1da177e4 4973 }
76c224bc 4974
2d7edb92 4975 return error;
1da177e4
LT		 4976}
4977
4978/******************************************************************************
2d7edb92 4979 * Writes a 16 bit word from the EEPROM using the EEWR register.
1da177e4
LT		 4980 *
4981 * hw - Struct containing variables accessed by shared code
2d7edb92
MC		 4982 * offset - offset of word in the EEPROM to read
4983 * data - word read from the EEPROM
4984 * words - number of words to read
1da177e4 4985 *****************************************************************************/
3ad2cc67 4986static int32_t
2d7edb92
MC		 4987e1000_write_eeprom_eewr(struct e1000_hw *hw,
4988 uint16_t offset,
4989 uint16_t words,
4990 uint16_t *data)
1da177e4 4991{
2d7edb92
MC		 4992 uint32_t register_value = 0;
4993 uint32_t i = 0;
4994 int32_t error = 0;
1da177e4 4995
6418ecc6
JK		 4996 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4997 return -E1000_ERR_SWFW_SYNC;
4998
2d7edb92 4999 for (i = 0; i < words; i++) {
76c224bc
AK		 5000 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) |
5001 ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) |
2d7edb92 5002 E1000_EEPROM_RW_REG_START;
1da177e4 5003
2d7edb92 5004 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
8fc897b0 5005 if (error) {
2d7edb92 5006 break;
76c224bc 5007 }
2d7edb92
MC		 5008
5009 E1000_WRITE_REG(hw, EEWR, register_value);
76c224bc 5010
2d7edb92 5011 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
76c224bc 5012
8fc897b0 5013 if (error) {
2d7edb92 5014 break;
76c224bc 5015 }
2d7edb92 5016 }
76c224bc 5017
6418ecc6 5018 e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
2d7edb92
MC		 5019 return error;
5020}
5021
5022/******************************************************************************
5023 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
5024 *
5025 * hw - Struct containing variables accessed by shared code
5026 *****************************************************************************/
3ad2cc67 5027static int32_t
2d7edb92
MC		 5028e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5029{
5030 uint32_t attempts = 100000;
5031 uint32_t i, reg = 0;
5032 int32_t done = E1000_ERR_EEPROM;
5033
8fc897b0
AK		 5034 for (i = 0; i < attempts; i++) {
5035 if (eerd == E1000_EEPROM_POLL_READ)
2d7edb92 5036 reg = E1000_READ_REG(hw, EERD);
76c224bc 5037 else
2d7edb92
MC		 5038 reg = E1000_READ_REG(hw, EEWR);
5039
8fc897b0 5040 if (reg & E1000_EEPROM_RW_REG_DONE) {
2d7edb92
MC		 5041 done = E1000_SUCCESS;
5042 break;
5043 }
5044 udelay(5);
5045 }
5046
5047 return done;
5048}
5049
5050/***************************************************************************
5051* Description: Determines if the onboard NVM is FLASH or EEPROM.
5052*
5053* hw - Struct containing variables accessed by shared code
5054****************************************************************************/
3ad2cc67 5055static boolean_t
2d7edb92
MC		 5056e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5057{
5058 uint32_t eecd = 0;
5059
6418ecc6
JK		 5060 DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5061
cd94dd0b
AK		 5062 if (hw->mac_type == e1000_ich8lan)
5063 return FALSE;
5064
5065 if (hw->mac_type == e1000_82573) {
2d7edb92
MC		 5066 eecd = E1000_READ_REG(hw, EECD);
5067
5068 /* Isolate bits 15 & 16 */
5069 eecd = ((eecd >> 15) & 0x03);
5070
5071 /* If both bits are set, device is Flash type */
8fc897b0 5072 if (eecd == 0x03) {
2d7edb92
MC		 5073 return FALSE;
5074 }
5075 }
5076 return TRUE;
5077}
5078
5079/******************************************************************************
5080 * Verifies that the EEPROM has a valid checksum
5081 *
5082 * hw - Struct containing variables accessed by shared code
5083 *
5084 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
5085 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5086 * valid.
5087 *****************************************************************************/
5088int32_t
5089e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5090{
5091 uint16_t checksum = 0;
5092 uint16_t i, eeprom_data;
5093
5094 DEBUGFUNC("e1000_validate_eeprom_checksum");
5095
5096 if ((hw->mac_type == e1000_82573) &&
5097 (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5098 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
5099 * 10h-12h. Checksum may need to be fixed. */
5100 e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5101 if ((eeprom_data & 0x10) == 0) {
5102 /* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5103 * has already been fixed. If the checksum is still wrong and this
5104 * bit is a 1, we need to return bad checksum. Otherwise, we need
5105 * to set this bit to a 1 and update the checksum. */
5106 e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5107 if ((eeprom_data & 0x8000) == 0) {
5108 eeprom_data |= 0x8000;
5109 e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5110 e1000_update_eeprom_checksum(hw);
5111 }
5112 }
5113 }
5114
cd94dd0b
AK		 5115 if (hw->mac_type == e1000_ich8lan) {
5116 /* Drivers must allocate the shadow ram structure for the
5117 * EEPROM checksum to be updated. Otherwise, this bit as well
5118 * as the checksum must both be set correctly for this
5119 * validation to pass.
5120 */
5121 e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5122 if ((eeprom_data & 0x40) == 0) {
5123 eeprom_data |= 0x40;
5124 e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5125 e1000_update_eeprom_checksum(hw);
5126 }
5127 }
5128
5129 for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5130 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5131 DEBUGOUT("EEPROM Read Error\n");
5132 return -E1000_ERR_EEPROM;
5133 }
5134 checksum += eeprom_data;
5135 }
5136
8fc897b0 5137 if (checksum == (uint16_t) EEPROM_SUM)
2d7edb92
MC		 5138 return E1000_SUCCESS;
5139 else {
5140 DEBUGOUT("EEPROM Checksum Invalid\n");
5141 return -E1000_ERR_EEPROM;
5142 }
5143}
5144
5145/******************************************************************************
5146 * Calculates the EEPROM checksum and writes it to the EEPROM
5147 *
5148 * hw - Struct containing variables accessed by shared code
5149 *
5150 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5151 * Writes the difference to word offset 63 of the EEPROM.
5152 *****************************************************************************/
5153int32_t
5154e1000_update_eeprom_checksum(struct e1000_hw *hw)
5155{
cd94dd0b 5156 uint32_t ctrl_ext;
2d7edb92
MC		 5157 uint16_t checksum = 0;
5158 uint16_t i, eeprom_data;
5159
5160 DEBUGFUNC("e1000_update_eeprom_checksum");
5161
8fc897b0
AK		 5162 for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5163 if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
2d7edb92
MC		 5164 DEBUGOUT("EEPROM Read Error\n");
5165 return -E1000_ERR_EEPROM;
5166 }
5167 checksum += eeprom_data;
5168 }
5169 checksum = (uint16_t) EEPROM_SUM - checksum;
8fc897b0 5170 if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
1da177e4
LT		 5171 DEBUGOUT("EEPROM Write Error\n");
5172 return -E1000_ERR_EEPROM;
2d7edb92
MC		 5173 } else if (hw->eeprom.type == e1000_eeprom_flash) {
5174 e1000_commit_shadow_ram(hw);
cd94dd0b
AK		 5175 } else if (hw->eeprom.type == e1000_eeprom_ich8) {
5176 e1000_commit_shadow_ram(hw);
5177 /* Reload the EEPROM, or else modifications will not appear
5178 * until after next adapter reset. */
5179 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5180 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
5181 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5182 msec_delay(10);
1da177e4
LT		 5183 }
5184 return E1000_SUCCESS;
5185}
5186
5187/******************************************************************************
5188 * Parent function for writing words to the different EEPROM types.
5189 *
5190 * hw - Struct containing variables accessed by shared code
5191 * offset - offset within the EEPROM to be written to
5192 * words - number of words to write
5193 * data - 16 bit word to be written to the EEPROM
5194 *
5195 * If e1000_update_eeprom_checksum is not called after this function, the
5196 * EEPROM will most likely contain an invalid checksum.
5197 *****************************************************************************/
5198int32_t
5199e1000_write_eeprom(struct e1000_hw *hw,
5200 uint16_t offset,
5201 uint16_t words,
5202 uint16_t *data)
5203{
5204 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5205 int32_t status = 0;
5206
5207 DEBUGFUNC("e1000_write_eeprom");
5208
5209 /* A check for invalid values: offset too large, too many words, and not
5210 * enough words.
5211 */
8fc897b0 5212 if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) ||
1da177e4
LT		 5213 (words == 0)) {
5214 DEBUGOUT("\"words\" parameter out of bounds\n");
5215 return -E1000_ERR_EEPROM;
5216 }
5217
868d5309 5218 /* 82573 writes only through eewr */
8fc897b0 5219 if (eeprom->use_eewr == TRUE)
2d7edb92
MC		 5220 return e1000_write_eeprom_eewr(hw, offset, words, data);
5221
cd94dd0b
AK		 5222 if (eeprom->type == e1000_eeprom_ich8)
5223 return e1000_write_eeprom_ich8(hw, offset, words, data);
5224
1da177e4
LT		 5225 /* Prepare the EEPROM for writing */
5226 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5227 return -E1000_ERR_EEPROM;
5228
8fc897b0 5229 if (eeprom->type == e1000_eeprom_microwire) {
1da177e4
LT		 5230 status = e1000_write_eeprom_microwire(hw, offset, words, data);
5231 } else {
5232 status = e1000_write_eeprom_spi(hw, offset, words, data);
5233 msec_delay(10);
5234 }
5235
5236 /* Done with writing */
5237 e1000_release_eeprom(hw);
5238
5239 return status;
5240}
5241
5242/******************************************************************************
5243 * Writes a 16 bit word to a given offset in an SPI EEPROM.
5244 *
5245 * hw - Struct containing variables accessed by shared code
5246 * offset - offset within the EEPROM to be written to
5247 * words - number of words to write
5248 * data - pointer to array of 8 bit words to be written to the EEPROM
5249 *
5250 *****************************************************************************/
5251int32_t
5252e1000_write_eeprom_spi(struct e1000_hw *hw,
5253 uint16_t offset,
5254 uint16_t words,
5255 uint16_t *data)
5256{
5257 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5258 uint16_t widx = 0;
5259
5260 DEBUGFUNC("e1000_write_eeprom_spi");
5261
5262 while (widx < words) {
5263 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5264
8fc897b0 5265 if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
1da177e4
LT		 5266
5267 e1000_standby_eeprom(hw);
5268
5269 /* Send the WRITE ENABLE command (8 bit opcode ) */
5270 e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5271 eeprom->opcode_bits);
5272
5273 e1000_standby_eeprom(hw);
5274
5275 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
8fc897b0 5276 if ((eeprom->address_bits == 8) && (offset >= 128))
1da177e4
LT		 5277 write_opcode |= EEPROM_A8_OPCODE_SPI;
5278
5279 /* Send the Write command (8-bit opcode + addr) */
5280 e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5281
5282 e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5283 eeprom->address_bits);
5284
5285 /* Send the data */
5286
5287 /* Loop to allow for up to whole page write (32 bytes) of eeprom */
5288 while (widx < words) {
5289 uint16_t word_out = data[widx];
5290 word_out = (word_out >> 8) | (word_out << 8);
5291 e1000_shift_out_ee_bits(hw, word_out, 16);
5292 widx++;
5293
5294 /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5295 * operation, while the smaller eeproms are capable of an 8-byte
5296 * PAGE WRITE operation. Break the inner loop to pass new address
5297 */
8fc897b0 5298 if ((((offset + widx)*2) % eeprom->page_size) == 0) {
1da177e4
LT		 5299 e1000_standby_eeprom(hw);
5300 break;
5301 }
5302 }
5303 }
5304
5305 return E1000_SUCCESS;
5306}
5307
5308/******************************************************************************
5309 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
5310 *
5311 * hw - Struct containing variables accessed by shared code
5312 * offset - offset within the EEPROM to be written to
5313 * words - number of words to write
5314 * data - pointer to array of 16 bit words to be written to the EEPROM
5315 *
5316 *****************************************************************************/
5317int32_t
5318e1000_write_eeprom_microwire(struct e1000_hw *hw,
5319 uint16_t offset,
5320 uint16_t words,
5321 uint16_t *data)
5322{
5323 struct e1000_eeprom_info *eeprom = &hw->eeprom;
5324 uint32_t eecd;
5325 uint16_t words_written = 0;
5326 uint16_t i = 0;
5327
5328 DEBUGFUNC("e1000_write_eeprom_microwire");
5329
5330 /* Send the write enable command to the EEPROM (3-bit opcode plus
5331 * 6/8-bit dummy address beginning with 11). It's less work to include
5332 * the 11 of the dummy address as part of the opcode than it is to shift
5333 * it over the correct number of bits for the address. This puts the
5334 * EEPROM into write/erase mode.
5335 */
5336 e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5337 (uint16_t)(eeprom->opcode_bits + 2));
5338
5339 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5340
5341 /* Prepare the EEPROM */
5342 e1000_standby_eeprom(hw);
5343
5344 while (words_written < words) {
5345 /* Send the Write command (3-bit opcode + addr) */
5346 e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5347 eeprom->opcode_bits);
5348
5349 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5350 eeprom->address_bits);
5351
5352 /* Send the data */
5353 e1000_shift_out_ee_bits(hw, data[words_written], 16);
5354
5355 /* Toggle the CS line. This in effect tells the EEPROM to execute
5356 * the previous command.
5357 */
5358 e1000_standby_eeprom(hw);
5359
5360 /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5361 * signal that the command has been completed by raising the DO signal.
5362 * If DO does not go high in 10 milliseconds, then error out.
5363 */
8fc897b0 5364 for (i = 0; i < 200; i++) {
1da177e4 5365 eecd = E1000_READ_REG(hw, EECD);
8fc897b0 5366 if (eecd & E1000_EECD_DO) break;
1da177e4
LT		 5367 udelay(50);
5368 }
8fc897b0 5369 if (i == 200) {
1da177e4
LT		 5370 DEBUGOUT("EEPROM Write did not complete\n");
5371 return -E1000_ERR_EEPROM;
5372 }
5373
5374 /* Recover from write */
5375 e1000_standby_eeprom(hw);
5376
5377 words_written++;
5378 }
5379
5380 /* Send the write disable command to the EEPROM (3-bit opcode plus
5381 * 6/8-bit dummy address beginning with 10). It's less work to include
5382 * the 10 of the dummy address as part of the opcode than it is to shift
5383 * it over the correct number of bits for the address. This takes the
5384 * EEPROM out of write/erase mode.
5385 */
5386 e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5387 (uint16_t)(eeprom->opcode_bits + 2));
5388
5389 e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5390
5391 return E1000_SUCCESS;
5392}
5393
2d7edb92
MC		 5394/******************************************************************************
5395 * Flushes the cached eeprom to NVM. This is done by saving the modified values
5396 * in the eeprom cache and the non modified values in the currently active bank
5397 * to the new bank.
5398 *
5399 * hw - Struct containing variables accessed by shared code
5400 * offset - offset of word in the EEPROM to read
5401 * data - word read from the EEPROM
5402 * words - number of words to read
5403 *****************************************************************************/
3ad2cc67 5404static int32_t
2d7edb92
MC		 5405e1000_commit_shadow_ram(struct e1000_hw *hw)
5406{
5407 uint32_t attempts = 100000;
5408 uint32_t eecd = 0;
5409 uint32_t flop = 0;
5410 uint32_t i = 0;
5411 int32_t error = E1000_SUCCESS;
cd94dd0b
AK		 5412 uint32_t old_bank_offset = 0;
5413 uint32_t new_bank_offset = 0;
5414 uint32_t sector_retries = 0;
5415 uint8_t low_byte = 0;
5416 uint8_t high_byte = 0;
5417 uint8_t temp_byte = 0;
5418 boolean_t sector_write_failed = FALSE;
2d7edb92
MC		 5419
5420 if (hw->mac_type == e1000_82573) {
cd94dd0b
AK		 5421 /* The flop register will be used to determine if flash type is STM */
5422 flop = E1000_READ_REG(hw, FLOP);
2d7edb92
MC		 5423 for (i=0; i < attempts; i++) {
5424 eecd = E1000_READ_REG(hw, EECD);
5425 if ((eecd & E1000_EECD_FLUPD) == 0) {
5426 break;
5427 }
5428 udelay(5);
5429 }
5430
5431 if (i == attempts) {
5432 return -E1000_ERR_EEPROM;
5433 }
5434
96838a40 5435 /* If STM opcode located in bits 15:8 of flop, reset firmware */
2d7edb92
MC		 5436 if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5437 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5438 }
5439
5440 /* Perform the flash update */
5441 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD);
5442
96838a40 5443 for (i=0; i < attempts; i++) {
2d7edb92
MC		 5444 eecd = E1000_READ_REG(hw, EECD);
5445 if ((eecd & E1000_EECD_FLUPD) == 0) {
5446 break;
5447 }
5448 udelay(5);
5449 }
5450
5451 if (i == attempts) {
5452 return -E1000_ERR_EEPROM;
5453 }
5454 }
5455
cd94dd0b
AK		 5456 if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5457 /* We're writing to the opposite bank so if we're on bank 1,
5458 * write to bank 0 etc. We also need to erase the segment that
5459 * is going to be written */
5460 if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5461 new_bank_offset = hw->flash_bank_size * 2;
5462 old_bank_offset = 0;
5463 e1000_erase_ich8_4k_segment(hw, 1);
5464 } else {
5465 old_bank_offset = hw->flash_bank_size * 2;
5466 new_bank_offset = 0;
5467 e1000_erase_ich8_4k_segment(hw, 0);
5468 }
5469
5470 do {
5471 sector_write_failed = FALSE;
5472 /* Loop for every byte in the shadow RAM,
5473 * which is in units of words. */
5474 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5475 /* Determine whether to write the value stored
5476 * in the other NVM bank or a modified value stored
5477 * in the shadow RAM */
5478 if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5479 low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5480 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5481 &temp_byte);
5482 udelay(100);
5483 error = e1000_verify_write_ich8_byte(hw,
5484 (i << 1) + new_bank_offset,
5485 low_byte);
5486 if (error != E1000_SUCCESS)
5487 sector_write_failed = TRUE;
5488 high_byte =
5489 (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5490 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5491 &temp_byte);
5492 udelay(100);
5493 } else {
5494 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5495 &low_byte);
5496 udelay(100);
5497 error = e1000_verify_write_ich8_byte(hw,
5498 (i << 1) + new_bank_offset, low_byte);
5499 if (error != E1000_SUCCESS)
5500 sector_write_failed = TRUE;
5501 e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5502 &high_byte);
5503 }
5504
5505 /* If the word is 0x13, then make sure the signature bits
5506 * (15:14) are 11b until the commit has completed.
5507 * This will allow us to write 10b which indicates the
5508 * signature is valid. We want to do this after the write
5509 * has completed so that we don't mark the segment valid
5510 * while the write is still in progress */
5511 if (i == E1000_ICH8_NVM_SIG_WORD)
5512 high_byte = E1000_ICH8_NVM_SIG_MASK | high_byte;
5513
5514 error = e1000_verify_write_ich8_byte(hw,
5515 (i << 1) + new_bank_offset + 1, high_byte);
5516 if (error != E1000_SUCCESS)
5517 sector_write_failed = TRUE;
5518
5519 if (sector_write_failed == FALSE) {
5520 /* Clear the now not used entry in the cache */
5521 hw->eeprom_shadow_ram[i].modified = FALSE;
5522 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5523 }
5524 }
5525
5526 /* Don't bother writing the segment valid bits if sector
5527 * programming failed. */
5528 if (sector_write_failed == FALSE) {
5529 /* Finally validate the new segment by setting bit 15:14
5530 * to 10b in word 0x13 , this can be done without an
5531 * erase as well since these bits are 11 to start with
5532 * and we need to change bit 14 to 0b */
5533 e1000_read_ich8_byte(hw,
5534 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5535 &high_byte);
5536 high_byte &= 0xBF;
5537 error = e1000_verify_write_ich8_byte(hw,
5538 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5539 high_byte);
5540 if (error != E1000_SUCCESS)
5541 sector_write_failed = TRUE;
5542
5543 /* And invalidate the previously valid segment by setting
5544 * its signature word (0x13) high_byte to 0b. This can be
5545 * done without an erase because flash erase sets all bits
5546 * to 1's. We can write 1's to 0's without an erase */
5547 error = e1000_verify_write_ich8_byte(hw,
5548 E1000_ICH8_NVM_SIG_WORD * 2 + 1 + old_bank_offset,
5549 0);
5550 if (error != E1000_SUCCESS)
5551 sector_write_failed = TRUE;
5552 }
5553 } while (++sector_retries < 10 && sector_write_failed == TRUE);
5554 }
5555
2d7edb92
MC		 5556 return error;
5557}
5558
1da177e4
LT		 5559/******************************************************************************
5560 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5561 * second function of dual function devices
5562 *
5563 * hw - Struct containing variables accessed by shared code
5564 *****************************************************************************/
5565int32_t
5566e1000_read_mac_addr(struct e1000_hw * hw)
5567{
5568 uint16_t offset;
5569 uint16_t eeprom_data, i;
5570
5571 DEBUGFUNC("e1000_read_mac_addr");
5572
8fc897b0 5573 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1da177e4 5574 offset = i >> 1;
8fc897b0 5575 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
1da177e4
LT		 5576 DEBUGOUT("EEPROM Read Error\n");
5577 return -E1000_ERR_EEPROM;
5578 }
5579 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5580 hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5581 }
96838a40 5582
868d5309
MC		 5583 switch (hw->mac_type) {
5584 default:
5585 break;
5586 case e1000_82546:
5587 case e1000_82546_rev_3:
5588 case e1000_82571:
6418ecc6 5589 case e1000_80003es2lan:
8fc897b0 5590 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1da177e4 5591 hw->perm_mac_addr[5] ^= 0x01;
868d5309
MC		 5592 break;
5593 }
1da177e4 5594
8fc897b0 5595 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
1da177e4
LT		 5596 hw->mac_addr[i] = hw->perm_mac_addr[i];
5597 return E1000_SUCCESS;
5598}
5599
5600/******************************************************************************
5601 * Initializes receive address filters.
5602 *
5603 * hw - Struct containing variables accessed by shared code
5604 *
5605 * Places the MAC address in receive address register 0 and clears the rest
5606 * of the receive addresss registers. Clears the multicast table. Assumes
5607 * the receiver is in reset when the routine is called.
5608 *****************************************************************************/
3ad2cc67 5609static void
1da177e4
LT		 5610e1000_init_rx_addrs(struct e1000_hw *hw)
5611{
5612 uint32_t i;
2d7edb92 5613 uint32_t rar_num;
1da177e4
LT		 5614
5615 DEBUGFUNC("e1000_init_rx_addrs");
5616
5617 /* Setup the receive address. */
5618 DEBUGOUT("Programming MAC Address into RAR[0]\n");
5619
5620 e1000_rar_set(hw, hw->mac_addr, 0);
5621
2d7edb92 5622 rar_num = E1000_RAR_ENTRIES;
868d5309
MC		 5623
5624 /* Reserve a spot for the Locally Administered Address to work around
5625 * an 82571 issue in which a reset on one port will reload the MAC on
5626 * the other port. */
5627 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5628 rar_num -= 1;
cd94dd0b
AK		 5629 if (hw->mac_type == e1000_ich8lan)
5630 rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5631
1da177e4
LT		 5632 /* Zero out the other 15 receive addresses. */
5633 DEBUGOUT("Clearing RAR[1-15]\n");
8fc897b0 5634 for (i = 1; i < rar_num; i++) {
1da177e4 5635 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4ca213a6 5636 E1000_WRITE_FLUSH(hw);
1da177e4 5637 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4ca213a6 5638 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5639 }
5640}
5641
5642/******************************************************************************
5643 * Updates the MAC's list of multicast addresses.
5644 *
5645 * hw - Struct containing variables accessed by shared code
5646 * mc_addr_list - the list of new multicast addresses
5647 * mc_addr_count - number of addresses
5648 * pad - number of bytes between addresses in the list
5649 * rar_used_count - offset where to start adding mc addresses into the RAR's
5650 *
5651 * The given list replaces any existing list. Clears the last 15 receive
5652 * address registers and the multicast table. Uses receive address registers
5653 * for the first 15 multicast addresses, and hashes the rest into the
5654 * multicast table.
5655 *****************************************************************************/
e4c780b1 5656#if 0
1da177e4
LT		 5657void
5658e1000_mc_addr_list_update(struct e1000_hw *hw,
5659 uint8_t *mc_addr_list,
5660 uint32_t mc_addr_count,
5661 uint32_t pad,
5662 uint32_t rar_used_count)
5663{
5664 uint32_t hash_value;
5665 uint32_t i;
2d7edb92
MC		 5666 uint32_t num_rar_entry;
5667 uint32_t num_mta_entry;
76c224bc 5668
1da177e4
LT		 5669 DEBUGFUNC("e1000_mc_addr_list_update");
5670
5671 /* Set the new number of MC addresses that we are being requested to use. */
5672 hw->num_mc_addrs = mc_addr_count;
5673
5674 /* Clear RAR[1-15] */
5675 DEBUGOUT(" Clearing RAR[1-15]\n");
2d7edb92 5676 num_rar_entry = E1000_RAR_ENTRIES;
cd94dd0b
AK		 5677 if (hw->mac_type == e1000_ich8lan)
5678 num_rar_entry = E1000_RAR_ENTRIES_ICH8LAN;
868d5309
MC		 5679 /* Reserve a spot for the Locally Administered Address to work around
5680 * an 82571 issue in which a reset on one port will reload the MAC on
5681 * the other port. */
5682 if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5683 num_rar_entry -= 1;
5684
8fc897b0 5685 for (i = rar_used_count; i < num_rar_entry; i++) {
1da177e4 5686 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
4ca213a6 5687 E1000_WRITE_FLUSH(hw);
1da177e4 5688 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
4ca213a6 5689 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5690 }
5691
5692 /* Clear the MTA */
5693 DEBUGOUT(" Clearing MTA\n");
2d7edb92 5694 num_mta_entry = E1000_NUM_MTA_REGISTERS;
cd94dd0b
AK		 5695 if (hw->mac_type == e1000_ich8lan)
5696 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN;
8fc897b0 5697 for (i = 0; i < num_mta_entry; i++) {
1da177e4 5698 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6 5699 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5700 }
5701
5702 /* Add the new addresses */
8fc897b0 5703 for (i = 0; i < mc_addr_count; i++) {
1da177e4
LT		 5704 DEBUGOUT(" Adding the multicast addresses:\n");
5705 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
5706 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
5707 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
5708 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
5709 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
5710 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
5711 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
5712
5713 hash_value = e1000_hash_mc_addr(hw,
5714 mc_addr_list +
5715 (i * (ETH_LENGTH_OF_ADDRESS + pad)));
5716
5717 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
5718
5719 /* Place this multicast address in the RAR if there is room, *
5720 * else put it in the MTA
5721 */
2d7edb92 5722 if (rar_used_count < num_rar_entry) {
1da177e4
LT		 5723 e1000_rar_set(hw,
5724 mc_addr_list + (i * (ETH_LENGTH_OF_ADDRESS + pad)),
5725 rar_used_count);
5726 rar_used_count++;
5727 } else {
5728 e1000_mta_set(hw, hash_value);
5729 }
5730 }
5731 DEBUGOUT("MC Update Complete\n");
5732}
e4c780b1 5733#endif /* 0 */
1da177e4
LT		 5734
5735/******************************************************************************
5736 * Hashes an address to determine its location in the multicast table
5737 *
5738 * hw - Struct containing variables accessed by shared code
5739 * mc_addr - the multicast address to hash
5740 *****************************************************************************/
5741uint32_t
5742e1000_hash_mc_addr(struct e1000_hw *hw,
5743 uint8_t *mc_addr)
5744{
5745 uint32_t hash_value = 0;
5746
5747 /* The portion of the address that is used for the hash table is
5748 * determined by the mc_filter_type setting.
5749 */
5750 switch (hw->mc_filter_type) {
5751 /* [0] [1] [2] [3] [4] [5]
5752 * 01 AA 00 12 34 56
5753 * LSB MSB
5754 */
5755 case 0:
cd94dd0b
AK		 5756 if (hw->mac_type == e1000_ich8lan) {
5757 /* [47:38] i.e. 0x158 for above example address */
5758 hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2));
5759 } else {
5760 /* [47:36] i.e. 0x563 for above example address */
5761 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5762 }
1da177e4
LT		 5763 break;
5764 case 1:
cd94dd0b
AK		 5765 if (hw->mac_type == e1000_ich8lan) {
5766 /* [46:37] i.e. 0x2B1 for above example address */
5767 hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3));
5768 } else {
5769 /* [46:35] i.e. 0xAC6 for above example address */
5770 hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5));
5771 }
1da177e4
LT		 5772 break;
5773 case 2:
cd94dd0b
AK		 5774 if (hw->mac_type == e1000_ich8lan) {
5775 /*[45:36] i.e. 0x163 for above example address */
5776 hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4));
5777 } else {
5778 /* [45:34] i.e. 0x5D8 for above example address */
5779 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5780 }
1da177e4
LT		 5781 break;
5782 case 3:
cd94dd0b
AK		 5783 if (hw->mac_type == e1000_ich8lan) {
5784 /* [43:34] i.e. 0x18D for above example address */
5785 hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6));
5786 } else {
5787 /* [43:32] i.e. 0x634 for above example address */
5788 hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8));
5789 }
1da177e4
LT		 5790 break;
5791 }
5792
5793 hash_value &= 0xFFF;
cd94dd0b
AK		 5794 if (hw->mac_type == e1000_ich8lan)
5795 hash_value &= 0x3FF;
2d7edb92 5796
1da177e4
LT		 5797 return hash_value;
5798}
5799
5800/******************************************************************************
5801 * Sets the bit in the multicast table corresponding to the hash value.
5802 *
5803 * hw - Struct containing variables accessed by shared code
5804 * hash_value - Multicast address hash value
5805 *****************************************************************************/
5806void
5807e1000_mta_set(struct e1000_hw *hw,
5808 uint32_t hash_value)
5809{
5810 uint32_t hash_bit, hash_reg;
5811 uint32_t mta;
5812 uint32_t temp;
5813
5814 /* The MTA is a register array of 128 32-bit registers.
5815 * It is treated like an array of 4096 bits. We want to set
5816 * bit BitArray[hash_value]. So we figure out what register
5817 * the bit is in, read it, OR in the new bit, then write
5818 * back the new value. The register is determined by the
5819 * upper 7 bits of the hash value and the bit within that
5820 * register are determined by the lower 5 bits of the value.
5821 */
5822 hash_reg = (hash_value >> 5) & 0x7F;
cd94dd0b
AK		 5823 if (hw->mac_type == e1000_ich8lan)
5824 hash_reg &= 0x1F;
1da177e4
LT		 5825 hash_bit = hash_value & 0x1F;
5826
5827 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5828
5829 mta |= (1 << hash_bit);
5830
5831 /* If we are on an 82544 and we are trying to write an odd offset
5832 * in the MTA, save off the previous entry before writing and
5833 * restore the old value after writing.
5834 */
8fc897b0 5835 if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
1da177e4
LT		 5836 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
5837 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5838 E1000_WRITE_FLUSH(hw);
1da177e4 5839 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
4ca213a6 5840 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5841 } else {
5842 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
4ca213a6 5843 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5844 }
5845}
5846
5847/******************************************************************************
5848 * Puts an ethernet address into a receive address register.
5849 *
5850 * hw - Struct containing variables accessed by shared code
5851 * addr - Address to put into receive address register
5852 * index - Receive address register to write
5853 *****************************************************************************/
5854void
5855e1000_rar_set(struct e1000_hw *hw,
5856 uint8_t *addr,
5857 uint32_t index)
5858{
5859 uint32_t rar_low, rar_high;
5860
5861 /* HW expects these in little endian so we reverse the byte order
5862 * from network order (big endian) to little endian
5863 */
5864 rar_low = ((uint32_t) addr[0] |
5865 ((uint32_t) addr[1] << 8) |
5866 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
8df06e50 5867 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
1da177e4 5868
8df06e50
JK		 5869 /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
5870 * unit hang.
5871 *
5872 * Description:
5873 * If there are any Rx frames queued up or otherwise present in the HW
5874 * before RSS is enabled, and then we enable RSS, the HW Rx unit will
5875 * hang. To work around this issue, we have to disable receives and
5876 * flush out all Rx frames before we enable RSS. To do so, we modify we
5877 * redirect all Rx traffic to manageability and then reset the HW.
5878 * This flushes away Rx frames, and (since the redirections to
5879 * manageability persists across resets) keeps new ones from coming in
5880 * while we work. Then, we clear the Address Valid AV bit for all MAC
5881 * addresses and undo the re-direction to manageability.
5882 * Now, frames are coming in again, but the MAC won't accept them, so
5883 * far so good. We now proceed to initialize RSS (if necessary) and
5884 * configure the Rx unit. Last, we re-enable the AV bits and continue
5885 * on our merry way.
5886 */
5887 switch (hw->mac_type) {
5888 case e1000_82571:
5889 case e1000_82572:
6418ecc6 5890 case e1000_80003es2lan:
8df06e50
JK		 5891 if (hw->leave_av_bit_off == TRUE)
5892 break;
5893 default:
5894 /* Indicate to hardware the Address is Valid. */
5895 rar_high |= E1000_RAH_AV;
5896 break;
5897 }
1da177e4
LT		 5898
5899 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
4ca213a6 5900 E1000_WRITE_FLUSH(hw);
1da177e4 5901 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
4ca213a6 5902 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5903}
5904
5905/******************************************************************************
5906 * Writes a value to the specified offset in the VLAN filter table.
5907 *
5908 * hw - Struct containing variables accessed by shared code
5909 * offset - Offset in VLAN filer table to write
5910 * value - Value to write into VLAN filter table
5911 *****************************************************************************/
5912void
5913e1000_write_vfta(struct e1000_hw *hw,
5914 uint32_t offset,
5915 uint32_t value)
5916{
5917 uint32_t temp;
5918
cd94dd0b
AK		 5919 if (hw->mac_type == e1000_ich8lan)
5920 return;
5921
5922 if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
1da177e4
LT		 5923 temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
5924 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5925 E1000_WRITE_FLUSH(hw);
1da177e4 5926 E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
4ca213a6 5927 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5928 } else {
5929 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
4ca213a6 5930 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 5931 }
5932}
5933
5934/******************************************************************************
5935 * Clears the VLAN filer table
5936 *
5937 * hw - Struct containing variables accessed by shared code
5938 *****************************************************************************/
3ad2cc67 5939static void
1da177e4
LT		 5940e1000_clear_vfta(struct e1000_hw *hw)
5941{
5942 uint32_t offset;
2d7edb92
MC		 5943 uint32_t vfta_value = 0;
5944 uint32_t vfta_offset = 0;
5945 uint32_t vfta_bit_in_reg = 0;
5946
cd94dd0b
AK		 5947 if (hw->mac_type == e1000_ich8lan)
5948 return;
5949
2d7edb92
MC		 5950 if (hw->mac_type == e1000_82573) {
5951 if (hw->mng_cookie.vlan_id != 0) {
5952 /* The VFTA is a 4096b bit-field, each identifying a single VLAN
5953 * ID. The following operations determine which 32b entry
5954 * (i.e. offset) into the array we want to set the VLAN ID
5955 * (i.e. bit) of the manageability unit. */
5956 vfta_offset = (hw->mng_cookie.vlan_id >>
5957 E1000_VFTA_ENTRY_SHIFT) &
5958 E1000_VFTA_ENTRY_MASK;
5959 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
5960 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
5961 }
5962 }
5963 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
5964 /* If the offset we want to clear is the same offset of the
5965 * manageability VLAN ID, then clear all bits except that of the
5966 * manageability unit */
5967 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
5968 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
4ca213a6 5969 E1000_WRITE_FLUSH(hw);
2d7edb92 5970 }
1da177e4
LT		 5971}
5972
3ad2cc67 5973static int32_t
1da177e4
LT		 5974e1000_id_led_init(struct e1000_hw * hw)
5975{
5976 uint32_t ledctl;
5977 const uint32_t ledctl_mask = 0x000000FF;
5978 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
5979 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
5980 uint16_t eeprom_data, i, temp;
5981 const uint16_t led_mask = 0x0F;
5982
5983 DEBUGFUNC("e1000_id_led_init");
5984
8fc897b0 5985 if (hw->mac_type < e1000_82540) {
1da177e4
LT		 5986 /* Nothing to do */
5987 return E1000_SUCCESS;
5988 }
5989
5990 ledctl = E1000_READ_REG(hw, LEDCTL);
5991 hw->ledctl_default = ledctl;
5992 hw->ledctl_mode1 = hw->ledctl_default;
5993 hw->ledctl_mode2 = hw->ledctl_default;
5994
8fc897b0 5995 if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
1da177e4
LT		 5996 DEBUGOUT("EEPROM Read Error\n");
5997 return -E1000_ERR_EEPROM;
5998 }
cd94dd0b
AK		 5999
6000 if ((hw->mac_type == e1000_82573) &&
6001 (eeprom_data == ID_LED_RESERVED_82573))
6002 eeprom_data = ID_LED_DEFAULT_82573;
6003 else if ((eeprom_data == ID_LED_RESERVED_0000) ||
6004 (eeprom_data == ID_LED_RESERVED_FFFF)) {
6005 if (hw->mac_type == e1000_ich8lan)
6006 eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6007 else
6008 eeprom_data = ID_LED_DEFAULT;
6009 }
6010 for (i = 0; i < 4; i++) {
1da177e4 6011 temp = (eeprom_data >> (i << 2)) & led_mask;
8fc897b0 6012 switch (temp) {
1da177e4
LT		 6013 case ID_LED_ON1_DEF2:
6014 case ID_LED_ON1_ON2:
6015 case ID_LED_ON1_OFF2:
6016 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6017 hw->ledctl_mode1 |= ledctl_on << (i << 3);
6018 break;
6019 case ID_LED_OFF1_DEF2:
6020 case ID_LED_OFF1_ON2:
6021 case ID_LED_OFF1_OFF2:
6022 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6023 hw->ledctl_mode1 |= ledctl_off << (i << 3);
6024 break;
6025 default:
6026 /* Do nothing */
6027 break;
6028 }
8fc897b0 6029 switch (temp) {
1da177e4
LT		 6030 case ID_LED_DEF1_ON2:
6031 case ID_LED_ON1_ON2:
6032 case ID_LED_OFF1_ON2:
6033 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6034 hw->ledctl_mode2 |= ledctl_on << (i << 3);
6035 break;
6036 case ID_LED_DEF1_OFF2:
6037 case ID_LED_ON1_OFF2:
6038 case ID_LED_OFF1_OFF2:
6039 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6040 hw->ledctl_mode2 |= ledctl_off << (i << 3);
6041 break;
6042 default:
6043 /* Do nothing */
6044 break;
6045 }
6046 }
6047 return E1000_SUCCESS;
6048}
6049
6050/******************************************************************************
6051 * Prepares SW controlable LED for use and saves the current state of the LED.
6052 *
6053 * hw - Struct containing variables accessed by shared code
6054 *****************************************************************************/
6055int32_t
6056e1000_setup_led(struct e1000_hw *hw)
6057{
6058 uint32_t ledctl;
6059 int32_t ret_val = E1000_SUCCESS;
6060
6061 DEBUGFUNC("e1000_setup_led");
6062
8fc897b0 6063 switch (hw->mac_type) {
1da177e4
LT		 6064 case e1000_82542_rev2_0:
6065 case e1000_82542_rev2_1:
6066 case e1000_82543:
6067 case e1000_82544:
6068 /* No setup necessary */
6069 break;
6070 case e1000_82541:
6071 case e1000_82547:
6072 case e1000_82541_rev_2:
6073 case e1000_82547_rev_2:
6074 /* Turn off PHY Smart Power Down (if enabled) */
6075 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6076 &hw->phy_spd_default);
8fc897b0 6077 if (ret_val)
1da177e4
LT		 6078 return ret_val;
6079 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6080 (uint16_t)(hw->phy_spd_default &
6081 ~IGP01E1000_GMII_SPD));
8fc897b0 6082 if (ret_val)
1da177e4
LT		 6083 return ret_val;
6084 /* Fall Through */
6085 default:
8fc897b0 6086 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6087 ledctl = E1000_READ_REG(hw, LEDCTL);
6088 /* Save current LEDCTL settings */
6089 hw->ledctl_default = ledctl;
6090 /* Turn off LED0 */
6091 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
6092 E1000_LEDCTL_LED0_BLINK |
6093 E1000_LEDCTL_LED0_MODE_MASK);
6094 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
6095 E1000_LEDCTL_LED0_MODE_SHIFT);
6096 E1000_WRITE_REG(hw, LEDCTL, ledctl);
8fc897b0 6097 } else if (hw->media_type == e1000_media_type_copper)
1da177e4
LT		 6098 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6099 break;
6100 }
6101
6102 return E1000_SUCCESS;
6103}
6104
8fc897b0 6105
f1b3a853
AK		 6106/******************************************************************************
6107 * Used on 82571 and later Si that has LED blink bits.
6108 * Callers must use their own timer and should have already called
6109 * e1000_id_led_init()
6110 * Call e1000_cleanup led() to stop blinking
6111 *
6112 * hw - Struct containing variables accessed by shared code
6113 *****************************************************************************/
6114int32_t
6115e1000_blink_led_start(struct e1000_hw *hw)
6116{
6117 int16_t i;
6118 uint32_t ledctl_blink = 0;
6119
6120 DEBUGFUNC("e1000_id_led_blink_on");
6121
6122 if (hw->mac_type < e1000_82571) {
6123 /* Nothing to do */
6124 return E1000_SUCCESS;
6125 }
6126 if (hw->media_type == e1000_media_type_fiber) {
6127 /* always blink LED0 for PCI-E fiber */
6128 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
6129 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6130 } else {
6131 /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6132 ledctl_blink = hw->ledctl_mode2;
6133 for (i=0; i < 4; i++)
6134 if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6135 E1000_LEDCTL_MODE_LED_ON)
6136 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6137 }
6138
6139 E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6140
6141 return E1000_SUCCESS;
6142}
6143
1da177e4
LT		 6144/******************************************************************************
6145 * Restores the saved state of the SW controlable LED.
6146 *
6147 * hw - Struct containing variables accessed by shared code
6148 *****************************************************************************/
6149int32_t
6150e1000_cleanup_led(struct e1000_hw *hw)
6151{
6152 int32_t ret_val = E1000_SUCCESS;
6153
6154 DEBUGFUNC("e1000_cleanup_led");
6155
8fc897b0 6156 switch (hw->mac_type) {
1da177e4
LT		 6157 case e1000_82542_rev2_0:
6158 case e1000_82542_rev2_1:
6159 case e1000_82543:
6160 case e1000_82544:
6161 /* No cleanup necessary */
6162 break;
6163 case e1000_82541:
6164 case e1000_82547:
6165 case e1000_82541_rev_2:
6166 case e1000_82547_rev_2:
6167 /* Turn on PHY Smart Power Down (if previously enabled) */
6168 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6169 hw->phy_spd_default);
8fc897b0 6170 if (ret_val)
1da177e4
LT		 6171 return ret_val;
6172 /* Fall Through */
6173 default:
cd94dd0b
AK		 6174 if (hw->phy_type == e1000_phy_ife) {
6175 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6176 break;
6177 }
1da177e4
LT		 6178 /* Restore LEDCTL settings */
6179 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6180 break;
6181 }
6182
6183 return E1000_SUCCESS;
6184}
6185
6186/******************************************************************************
6187 * Turns on the software controllable LED
6188 *
6189 * hw - Struct containing variables accessed by shared code
6190 *****************************************************************************/
6191int32_t
6192e1000_led_on(struct e1000_hw *hw)
6193{
6194 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6195
6196 DEBUGFUNC("e1000_led_on");
6197
8fc897b0 6198 switch (hw->mac_type) {
1da177e4
LT		 6199 case e1000_82542_rev2_0:
6200 case e1000_82542_rev2_1:
6201 case e1000_82543:
6202 /* Set SW Defineable Pin 0 to turn on the LED */
6203 ctrl |= E1000_CTRL_SWDPIN0;
6204 ctrl |= E1000_CTRL_SWDPIO0;
6205 break;
6206 case e1000_82544:
8fc897b0 6207 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6208 /* Set SW Defineable Pin 0 to turn on the LED */
6209 ctrl |= E1000_CTRL_SWDPIN0;
6210 ctrl |= E1000_CTRL_SWDPIO0;
6211 } else {
6212 /* Clear SW Defineable Pin 0 to turn on the LED */
6213 ctrl &= ~E1000_CTRL_SWDPIN0;
6214 ctrl |= E1000_CTRL_SWDPIO0;
6215 }
6216 break;
6217 default:
8fc897b0 6218 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6219 /* Clear SW Defineable Pin 0 to turn on the LED */
6220 ctrl &= ~E1000_CTRL_SWDPIN0;
6221 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6222 } else if (hw->phy_type == e1000_phy_ife) {
6223 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6224 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
6225 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6226 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6227 return E1000_SUCCESS;
6228 }
6229 break;
6230 }
6231
6232 E1000_WRITE_REG(hw, CTRL, ctrl);
6233
6234 return E1000_SUCCESS;
6235}
6236
6237/******************************************************************************
6238 * Turns off the software controllable LED
6239 *
6240 * hw - Struct containing variables accessed by shared code
6241 *****************************************************************************/
6242int32_t
6243e1000_led_off(struct e1000_hw *hw)
6244{
6245 uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6246
6247 DEBUGFUNC("e1000_led_off");
6248
8fc897b0 6249 switch (hw->mac_type) {
1da177e4
LT		 6250 case e1000_82542_rev2_0:
6251 case e1000_82542_rev2_1:
6252 case e1000_82543:
6253 /* Clear SW Defineable Pin 0 to turn off the LED */
6254 ctrl &= ~E1000_CTRL_SWDPIN0;
6255 ctrl |= E1000_CTRL_SWDPIO0;
6256 break;
6257 case e1000_82544:
8fc897b0 6258 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6259 /* Clear SW Defineable Pin 0 to turn off the LED */
6260 ctrl &= ~E1000_CTRL_SWDPIN0;
6261 ctrl |= E1000_CTRL_SWDPIO0;
6262 } else {
6263 /* Set SW Defineable Pin 0 to turn off the LED */
6264 ctrl |= E1000_CTRL_SWDPIN0;
6265 ctrl |= E1000_CTRL_SWDPIO0;
6266 }
6267 break;
6268 default:
8fc897b0 6269 if (hw->media_type == e1000_media_type_fiber) {
1da177e4
LT		 6270 /* Set SW Defineable Pin 0 to turn off the LED */
6271 ctrl |= E1000_CTRL_SWDPIN0;
6272 ctrl |= E1000_CTRL_SWDPIO0;
cd94dd0b
AK		 6273 } else if (hw->phy_type == e1000_phy_ife) {
6274 e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6275 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
6276 } else if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 6277 E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6278 return E1000_SUCCESS;
6279 }
6280 break;
6281 }
6282
6283 E1000_WRITE_REG(hw, CTRL, ctrl);
6284
6285 return E1000_SUCCESS;
6286}
6287
6288/******************************************************************************
6289 * Clears all hardware statistics counters.
6290 *
6291 * hw - Struct containing variables accessed by shared code
6292 *****************************************************************************/
8fc897b0 6293void
1da177e4
LT		 6294e1000_clear_hw_cntrs(struct e1000_hw *hw)
6295{
6296 volatile uint32_t temp;
6297
6298 temp = E1000_READ_REG(hw, CRCERRS);
6299 temp = E1000_READ_REG(hw, SYMERRS);
6300 temp = E1000_READ_REG(hw, MPC);
6301 temp = E1000_READ_REG(hw, SCC);
6302 temp = E1000_READ_REG(hw, ECOL);
6303 temp = E1000_READ_REG(hw, MCC);
6304 temp = E1000_READ_REG(hw, LATECOL);
6305 temp = E1000_READ_REG(hw, COLC);
6306 temp = E1000_READ_REG(hw, DC);
6307 temp = E1000_READ_REG(hw, SEC);
6308 temp = E1000_READ_REG(hw, RLEC);
6309 temp = E1000_READ_REG(hw, XONRXC);
6310 temp = E1000_READ_REG(hw, XONTXC);
6311 temp = E1000_READ_REG(hw, XOFFRXC);
6312 temp = E1000_READ_REG(hw, XOFFTXC);
6313 temp = E1000_READ_REG(hw, FCRUC);
cd94dd0b
AK		 6314
6315 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6316 temp = E1000_READ_REG(hw, PRC64);
6317 temp = E1000_READ_REG(hw, PRC127);
6318 temp = E1000_READ_REG(hw, PRC255);
6319 temp = E1000_READ_REG(hw, PRC511);
6320 temp = E1000_READ_REG(hw, PRC1023);
6321 temp = E1000_READ_REG(hw, PRC1522);
cd94dd0b
AK		 6322 }
6323
1da177e4
LT		 6324 temp = E1000_READ_REG(hw, GPRC);
6325 temp = E1000_READ_REG(hw, BPRC);
6326 temp = E1000_READ_REG(hw, MPRC);
6327 temp = E1000_READ_REG(hw, GPTC);
6328 temp = E1000_READ_REG(hw, GORCL);
6329 temp = E1000_READ_REG(hw, GORCH);
6330 temp = E1000_READ_REG(hw, GOTCL);
6331 temp = E1000_READ_REG(hw, GOTCH);
6332 temp = E1000_READ_REG(hw, RNBC);
6333 temp = E1000_READ_REG(hw, RUC);
6334 temp = E1000_READ_REG(hw, RFC);
6335 temp = E1000_READ_REG(hw, ROC);
6336 temp = E1000_READ_REG(hw, RJC);
6337 temp = E1000_READ_REG(hw, TORL);
6338 temp = E1000_READ_REG(hw, TORH);
6339 temp = E1000_READ_REG(hw, TOTL);
6340 temp = E1000_READ_REG(hw, TOTH);
6341 temp = E1000_READ_REG(hw, TPR);
6342 temp = E1000_READ_REG(hw, TPT);
cd94dd0b
AK		 6343
6344 if (hw->mac_type != e1000_ich8lan) {
1da177e4
LT		 6345 temp = E1000_READ_REG(hw, PTC64);
6346 temp = E1000_READ_REG(hw, PTC127);
6347 temp = E1000_READ_REG(hw, PTC255);
6348 temp = E1000_READ_REG(hw, PTC511);
6349 temp = E1000_READ_REG(hw, PTC1023);
6350 temp = E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 6351 }
6352
1da177e4
LT		 6353 temp = E1000_READ_REG(hw, MPTC);
6354 temp = E1000_READ_REG(hw, BPTC);
6355
8fc897b0 6356 if (hw->mac_type < e1000_82543) return;
1da177e4
LT		 6357
6358 temp = E1000_READ_REG(hw, ALGNERRC);
6359 temp = E1000_READ_REG(hw, RXERRC);
6360 temp = E1000_READ_REG(hw, TNCRS);
6361 temp = E1000_READ_REG(hw, CEXTERR);
6362 temp = E1000_READ_REG(hw, TSCTC);
6363 temp = E1000_READ_REG(hw, TSCTFC);
6364
8fc897b0 6365 if (hw->mac_type <= e1000_82544) return;
1da177e4
LT		 6366
6367 temp = E1000_READ_REG(hw, MGTPRC);
6368 temp = E1000_READ_REG(hw, MGTPDC);
6369 temp = E1000_READ_REG(hw, MGTPTC);
2d7edb92 6370
8fc897b0 6371 if (hw->mac_type <= e1000_82547_rev_2) return;
2d7edb92
MC		 6372
6373 temp = E1000_READ_REG(hw, IAC);
6374 temp = E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 6375
6376 if (hw->mac_type == e1000_ich8lan) return;
6377
2d7edb92
MC		 6378 temp = E1000_READ_REG(hw, ICRXPTC);
6379 temp = E1000_READ_REG(hw, ICRXATC);
6380 temp = E1000_READ_REG(hw, ICTXPTC);
6381 temp = E1000_READ_REG(hw, ICTXATC);
6382 temp = E1000_READ_REG(hw, ICTXQEC);
6383 temp = E1000_READ_REG(hw, ICTXQMTC);
6384 temp = E1000_READ_REG(hw, ICRXDMTC);
1da177e4
LT		 6385}
6386
6387/******************************************************************************
6388 * Resets Adaptive IFS to its default state.
6389 *
6390 * hw - Struct containing variables accessed by shared code
6391 *
6392 * Call this after e1000_init_hw. You may override the IFS defaults by setting
6393 * hw->ifs_params_forced to TRUE. However, you must initialize hw->
6394 * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6395 * before calling this function.
6396 *****************************************************************************/
6397void
6398e1000_reset_adaptive(struct e1000_hw *hw)
6399{
6400 DEBUGFUNC("e1000_reset_adaptive");
6401
8fc897b0
AK		 6402 if (hw->adaptive_ifs) {
6403 if (!hw->ifs_params_forced) {
1da177e4
LT		 6404 hw->current_ifs_val = 0;
6405 hw->ifs_min_val = IFS_MIN;
6406 hw->ifs_max_val = IFS_MAX;
6407 hw->ifs_step_size = IFS_STEP;
6408 hw->ifs_ratio = IFS_RATIO;
6409 }
6410 hw->in_ifs_mode = FALSE;
6411 E1000_WRITE_REG(hw, AIT, 0);
6412 } else {
6413 DEBUGOUT("Not in Adaptive IFS mode!\n");
6414 }
6415}
6416
6417/******************************************************************************
6418 * Called during the callback/watchdog routine to update IFS value based on
6419 * the ratio of transmits to collisions.
6420 *
6421 * hw - Struct containing variables accessed by shared code
6422 * tx_packets - Number of transmits since last callback
6423 * total_collisions - Number of collisions since last callback
6424 *****************************************************************************/
6425void
6426e1000_update_adaptive(struct e1000_hw *hw)
6427{
6428 DEBUGFUNC("e1000_update_adaptive");
6429
8fc897b0
AK		 6430 if (hw->adaptive_ifs) {
6431 if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6432 if (hw->tx_packet_delta > MIN_NUM_XMITS) {
1da177e4 6433 hw->in_ifs_mode = TRUE;
8fc897b0
AK		 6434 if (hw->current_ifs_val < hw->ifs_max_val) {
6435 if (hw->current_ifs_val == 0)
1da177e4
LT		 6436 hw->current_ifs_val = hw->ifs_min_val;
6437 else
6438 hw->current_ifs_val += hw->ifs_step_size;
6439 E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6440 }
6441 }
6442 } else {
8fc897b0 6443 if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
1da177e4
LT		 6444 hw->current_ifs_val = 0;
6445 hw->in_ifs_mode = FALSE;
6446 E1000_WRITE_REG(hw, AIT, 0);
6447 }
6448 }
6449 } else {
6450 DEBUGOUT("Not in Adaptive IFS mode!\n");
6451 }
6452}
6453
6454/******************************************************************************
6455 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6456 *
6457 * hw - Struct containing variables accessed by shared code
6458 * frame_len - The length of the frame in question
6459 * mac_addr - The Ethernet destination address of the frame in question
6460 *****************************************************************************/
6461void
6462e1000_tbi_adjust_stats(struct e1000_hw *hw,
6463 struct e1000_hw_stats *stats,
6464 uint32_t frame_len,
6465 uint8_t *mac_addr)
6466{
6467 uint64_t carry_bit;
6468
6469 /* First adjust the frame length. */
6470 frame_len--;
6471 /* We need to adjust the statistics counters, since the hardware
6472 * counters overcount this packet as a CRC error and undercount
6473 * the packet as a good packet
6474 */
6475 /* This packet should not be counted as a CRC error. */
6476 stats->crcerrs--;
6477 /* This packet does count as a Good Packet Received. */
6478 stats->gprc++;
6479
6480 /* Adjust the Good Octets received counters */
6481 carry_bit = 0x80000000 & stats->gorcl;
6482 stats->gorcl += frame_len;
6483 /* If the high bit of Gorcl (the low 32 bits of the Good Octets
6484 * Received Count) was one before the addition,
6485 * AND it is zero after, then we lost the carry out,
6486 * need to add one to Gorch (Good Octets Received Count High).
6487 * This could be simplified if all environments supported
6488 * 64-bit integers.
6489 */
8fc897b0 6490 if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
1da177e4
LT		 6491 stats->gorch++;
6492 /* Is this a broadcast or multicast? Check broadcast first,
6493 * since the test for a multicast frame will test positive on
6494 * a broadcast frame.
6495 */
8fc897b0 6496 if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
1da177e4
LT		 6497 /* Broadcast packet */
6498 stats->bprc++;
8fc897b0 6499 else if (*mac_addr & 0x01)
1da177e4
LT		 6500 /* Multicast packet */
6501 stats->mprc++;
6502
8fc897b0 6503 if (frame_len == hw->max_frame_size) {
1da177e4
LT		 6504 /* In this case, the hardware has overcounted the number of
6505 * oversize frames.
6506 */
8fc897b0 6507 if (stats->roc > 0)
1da177e4
LT		 6508 stats->roc--;
6509 }
6510
6511 /* Adjust the bin counters when the extra byte put the frame in the
6512 * wrong bin. Remember that the frame_len was adjusted above.
6513 */
8fc897b0 6514 if (frame_len == 64) {
1da177e4
LT		 6515 stats->prc64++;
6516 stats->prc127--;
8fc897b0 6517 } else if (frame_len == 127) {
1da177e4
LT		 6518 stats->prc127++;
6519 stats->prc255--;
8fc897b0 6520 } else if (frame_len == 255) {
1da177e4
LT		 6521 stats->prc255++;
6522 stats->prc511--;
8fc897b0 6523 } else if (frame_len == 511) {
1da177e4
LT		 6524 stats->prc511++;
6525 stats->prc1023--;
8fc897b0 6526 } else if (frame_len == 1023) {
1da177e4
LT		 6527 stats->prc1023++;
6528 stats->prc1522--;
8fc897b0 6529 } else if (frame_len == 1522) {
1da177e4
LT		 6530 stats->prc1522++;
6531 }
6532}
6533
6534/******************************************************************************
6535 * Gets the current PCI bus type, speed, and width of the hardware
6536 *
6537 * hw - Struct containing variables accessed by shared code
6538 *****************************************************************************/
6539void
6540e1000_get_bus_info(struct e1000_hw *hw)
6541{
6542 uint32_t status;
6543
6544 switch (hw->mac_type) {
6545 case e1000_82542_rev2_0:
6546 case e1000_82542_rev2_1:
6547 hw->bus_type = e1000_bus_type_unknown;
6548 hw->bus_speed = e1000_bus_speed_unknown;
6549 hw->bus_width = e1000_bus_width_unknown;
6550 break;
868d5309 6551 case e1000_82572:
2d7edb92 6552 case e1000_82573:
fd803241
JK		 6553 hw->bus_type = e1000_bus_type_pci_express;
6554 hw->bus_speed = e1000_bus_speed_2500;
6555 hw->bus_width = e1000_bus_width_pciex_1;
6556 break;
6557 case e1000_82571:
cd94dd0b 6558 case e1000_ich8lan:
6418ecc6 6559 case e1000_80003es2lan:
2d7edb92
MC		 6560 hw->bus_type = e1000_bus_type_pci_express;
6561 hw->bus_speed = e1000_bus_speed_2500;
6562 hw->bus_width = e1000_bus_width_pciex_4;
6563 break;
1da177e4
LT		 6564 default:
6565 status = E1000_READ_REG(hw, STATUS);
6566 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6567 e1000_bus_type_pcix : e1000_bus_type_pci;
6568
8fc897b0 6569 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
1da177e4
LT		 6570 hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6571 e1000_bus_speed_66 : e1000_bus_speed_120;
8fc897b0 6572 } else if (hw->bus_type == e1000_bus_type_pci) {
1da177e4
LT		 6573 hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6574 e1000_bus_speed_66 : e1000_bus_speed_33;
6575 } else {
6576 switch (status & E1000_STATUS_PCIX_SPEED) {
6577 case E1000_STATUS_PCIX_SPEED_66:
6578 hw->bus_speed = e1000_bus_speed_66;
6579 break;
6580 case E1000_STATUS_PCIX_SPEED_100:
6581 hw->bus_speed = e1000_bus_speed_100;
6582 break;
6583 case E1000_STATUS_PCIX_SPEED_133:
6584 hw->bus_speed = e1000_bus_speed_133;
6585 break;
6586 default:
6587 hw->bus_speed = e1000_bus_speed_reserved;
6588 break;
6589 }
6590 }
6591 hw->bus_width = (status & E1000_STATUS_BUS64) ?
6592 e1000_bus_width_64 : e1000_bus_width_32;
6593 break;
6594 }
6595}
6596/******************************************************************************
6597 * Reads a value from one of the devices registers using port I/O (as opposed
6598 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6599 *
6600 * hw - Struct containing variables accessed by shared code
6601 * offset - offset to read from
6602 *****************************************************************************/
e4c780b1 6603#if 0
1da177e4
LT		 6604uint32_t
6605e1000_read_reg_io(struct e1000_hw *hw,
6606 uint32_t offset)
6607{
6608 unsigned long io_addr = hw->io_base;
6609 unsigned long io_data = hw->io_base + 4;
6610
6611 e1000_io_write(hw, io_addr, offset);
6612 return e1000_io_read(hw, io_data);
6613}
e4c780b1 6614#endif /* 0 */
1da177e4
LT		 6615
6616/******************************************************************************
6617 * Writes a value to one of the devices registers using port I/O (as opposed to
6618 * memory mapped I/O). Only 82544 and newer devices support port I/O.
6619 *
6620 * hw - Struct containing variables accessed by shared code
6621 * offset - offset to write to
6622 * value - value to write
6623 *****************************************************************************/
3ad2cc67 6624static void
1da177e4
LT		 6625e1000_write_reg_io(struct e1000_hw *hw,
6626 uint32_t offset,
6627 uint32_t value)
6628{
6629 unsigned long io_addr = hw->io_base;
6630 unsigned long io_data = hw->io_base + 4;
6631
6632 e1000_io_write(hw, io_addr, offset);
6633 e1000_io_write(hw, io_data, value);
6634}
6635
6636
6637/******************************************************************************
6638 * Estimates the cable length.
6639 *
6640 * hw - Struct containing variables accessed by shared code
6641 * min_length - The estimated minimum length
6642 * max_length - The estimated maximum length
6643 *
6644 * returns: - E1000_ERR_XXX
6645 * E1000_SUCCESS
6646 *
6647 * This function always returns a ranged length (minimum & maximum).
6648 * So for M88 phy's, this function interprets the one value returned from the
6649 * register to the minimum and maximum range.
6650 * For IGP phy's, the function calculates the range by the AGC registers.
6651 *****************************************************************************/
3ad2cc67 6652static int32_t
1da177e4
LT		 6653e1000_get_cable_length(struct e1000_hw *hw,
6654 uint16_t *min_length,
6655 uint16_t *max_length)
6656{
6657 int32_t ret_val;
6658 uint16_t agc_value = 0;
1da177e4
LT		 6659 uint16_t i, phy_data;
6660 uint16_t cable_length;
6661
6662 DEBUGFUNC("e1000_get_cable_length");
6663
6664 *min_length = *max_length = 0;
6665
6666 /* Use old method for Phy older than IGP */
8fc897b0 6667 if (hw->phy_type == e1000_phy_m88) {
2d7edb92 6668
1da177e4
LT		 6669 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6670 &phy_data);
8fc897b0 6671 if (ret_val)
1da177e4
LT		 6672 return ret_val;
6673 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6674 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6675
6676 /* Convert the enum value to ranged values */
6677 switch (cable_length) {
6678 case e1000_cable_length_50:
6679 *min_length = 0;
6680 *max_length = e1000_igp_cable_length_50;
6681 break;
6682 case e1000_cable_length_50_80:
6683 *min_length = e1000_igp_cable_length_50;
6684 *max_length = e1000_igp_cable_length_80;
6685 break;
6686 case e1000_cable_length_80_110:
6687 *min_length = e1000_igp_cable_length_80;
6688 *max_length = e1000_igp_cable_length_110;
6689 break;
6690 case e1000_cable_length_110_140:
6691 *min_length = e1000_igp_cable_length_110;
6692 *max_length = e1000_igp_cable_length_140;
6693 break;
6694 case e1000_cable_length_140:
6695 *min_length = e1000_igp_cable_length_140;
6696 *max_length = e1000_igp_cable_length_170;
6697 break;
6698 default:
6699 return -E1000_ERR_PHY;
6700 break;
6701 }
6418ecc6
JK		 6702 } else if (hw->phy_type == e1000_phy_gg82563) {
6703 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6704 &phy_data);
6705 if (ret_val)
6706 return ret_val;
6707 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6708
6709 switch (cable_length) {
6710 case e1000_gg_cable_length_60:
6711 *min_length = 0;
6712 *max_length = e1000_igp_cable_length_60;
6713 break;
6714 case e1000_gg_cable_length_60_115:
6715 *min_length = e1000_igp_cable_length_60;
6716 *max_length = e1000_igp_cable_length_115;
6717 break;
6718 case e1000_gg_cable_length_115_150:
6719 *min_length = e1000_igp_cable_length_115;
6720 *max_length = e1000_igp_cable_length_150;
6721 break;
6722 case e1000_gg_cable_length_150:
6723 *min_length = e1000_igp_cable_length_150;
6724 *max_length = e1000_igp_cable_length_180;
6725 break;
6726 default:
6727 return -E1000_ERR_PHY;
6728 break;
6729 }
8fc897b0 6730 } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
cd94dd0b
AK		 6731 uint16_t cur_agc_value;
6732 uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
1da177e4
LT		 6733 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6734 {IGP01E1000_PHY_AGC_A,
6735 IGP01E1000_PHY_AGC_B,
6736 IGP01E1000_PHY_AGC_C,
6737 IGP01E1000_PHY_AGC_D};
6738 /* Read the AGC registers for all channels */
8fc897b0 6739 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 6740
6741 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
8fc897b0 6742 if (ret_val)
1da177e4
LT		 6743 return ret_val;
6744
cd94dd0b 6745 cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
1da177e4 6746
cd94dd0b
AK		 6747 /* Value bound check. */
6748 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
6749 (cur_agc_value == 0))
1da177e4
LT		 6750 return -E1000_ERR_PHY;
6751
cd94dd0b 6752 agc_value += cur_agc_value;
1da177e4
LT		 6753
6754 /* Update minimal AGC value. */
cd94dd0b
AK		 6755 if (min_agc_value > cur_agc_value)
6756 min_agc_value = cur_agc_value;
1da177e4
LT		 6757 }
6758
6759 /* Remove the minimal AGC result for length < 50m */
cd94dd0b
AK		 6760 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6761 agc_value -= min_agc_value;
1da177e4
LT		 6762
6763 /* Get the average length of the remaining 3 channels */
6764 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6765 } else {
6766 /* Get the average length of all the 4 channels. */
6767 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6768 }
6769
6770 /* Set the range of the calculated length. */
6771 *min_length = ((e1000_igp_cable_length_table[agc_value] -
6772 IGP01E1000_AGC_RANGE) > 0) ?
6773 (e1000_igp_cable_length_table[agc_value] -
6774 IGP01E1000_AGC_RANGE) : 0;
6775 *max_length = e1000_igp_cable_length_table[agc_value] +
6776 IGP01E1000_AGC_RANGE;
cd94dd0b
AK		 6777 } else if (hw->phy_type == e1000_phy_igp_2 ||
6778 hw->phy_type == e1000_phy_igp_3) {
6779 uint16_t cur_agc_index, max_agc_index = 0;
6780 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
868d5309
MC		 6781 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6782 {IGP02E1000_PHY_AGC_A,
6783 IGP02E1000_PHY_AGC_B,
6784 IGP02E1000_PHY_AGC_C,
6785 IGP02E1000_PHY_AGC_D};
6786 /* Read the AGC registers for all channels */
6787 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6788 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6789 if (ret_val)
6790 return ret_val;
6791
8fc897b0 6792 /* Getting bits 15:9, which represent the combination of course and
868d5309
MC		 6793 * fine gain values. The result is a number that can be put into
6794 * the lookup table to obtain the approximate cable length. */
cd94dd0b
AK		 6795 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6796 IGP02E1000_AGC_LENGTH_MASK;
868d5309 6797
cd94dd0b
AK		 6798 /* Array index bound check. */
6799 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) ||
6800 (cur_agc_index == 0))
6801 return -E1000_ERR_PHY;
868d5309 6802
cd94dd0b
AK		 6803 /* Remove min & max AGC values from calculation. */
6804 if (e1000_igp_2_cable_length_table[min_agc_index] >
6805 e1000_igp_2_cable_length_table[cur_agc_index])
6806 min_agc_index = cur_agc_index;
6807 if (e1000_igp_2_cable_length_table[max_agc_index] <
6808 e1000_igp_2_cable_length_table[cur_agc_index])
6809 max_agc_index = cur_agc_index;
6810
6811 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
868d5309
MC		 6812 }
6813
cd94dd0b
AK		 6814 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6815 e1000_igp_2_cable_length_table[max_agc_index]);
868d5309
MC		 6816 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6817
6818 /* Calculate cable length with the error range of +/- 10 meters. */
6819 *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6820 (agc_value - IGP02E1000_AGC_RANGE) : 0;
6821 *max_length = agc_value + IGP02E1000_AGC_RANGE;
1da177e4
LT		 6822 }
6823
6824 return E1000_SUCCESS;
6825}
6826
6827/******************************************************************************
6828 * Check the cable polarity
6829 *
6830 * hw - Struct containing variables accessed by shared code
6831 * polarity - output parameter : 0 - Polarity is not reversed
6832 * 1 - Polarity is reversed.
6833 *
6834 * returns: - E1000_ERR_XXX
6835 * E1000_SUCCESS
6836 *
6837 * For phy's older then IGP, this function simply reads the polarity bit in the
6838 * Phy Status register. For IGP phy's, this bit is valid only if link speed is
6839 * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
6840 * return 0. If the link speed is 1000 Mbps the polarity status is in the
6841 * IGP01E1000_PHY_PCS_INIT_REG.
6842 *****************************************************************************/
3ad2cc67 6843static int32_t
1da177e4
LT		 6844e1000_check_polarity(struct e1000_hw *hw,
6845 uint16_t *polarity)
6846{
6847 int32_t ret_val;
6848 uint16_t phy_data;
6849
6850 DEBUGFUNC("e1000_check_polarity");
6851
6418ecc6
JK		 6852 if ((hw->phy_type == e1000_phy_m88) ||
6853 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6854 /* return the Polarity bit in the Status register. */
6855 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6856 &phy_data);
8fc897b0 6857 if (ret_val)
1da177e4
LT		 6858 return ret_val;
6859 *polarity = (phy_data & M88E1000_PSSR_REV_POLARITY) >>
6860 M88E1000_PSSR_REV_POLARITY_SHIFT;
cd94dd0b
AK		 6861 } else if (hw->phy_type == e1000_phy_igp ||
6862 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6863 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6864 /* Read the Status register to check the speed */
6865 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
6866 &phy_data);
8fc897b0 6867 if (ret_val)
1da177e4
LT		 6868 return ret_val;
6869
6870 /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
6871 * find the polarity status */
8fc897b0 6872 if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1da177e4
LT		 6873 IGP01E1000_PSSR_SPEED_1000MBPS) {
6874
6875 /* Read the GIG initialization PCS register (0x00B4) */
6876 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
6877 &phy_data);
8fc897b0 6878 if (ret_val)
1da177e4
LT		 6879 return ret_val;
6880
6881 /* Check the polarity bits */
6882 *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? 1 : 0;
6883 } else {
6884 /* For 10 Mbps, read the polarity bit in the status register. (for
6885 * 100 Mbps this bit is always 0) */
6886 *polarity = phy_data & IGP01E1000_PSSR_POLARITY_REVERSED;
6887 }
cd94dd0b
AK		 6888 } else if (hw->phy_type == e1000_phy_ife) {
6889 ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
6890 &phy_data);
6891 if (ret_val)
6892 return ret_val;
6893 *polarity = (phy_data & IFE_PESC_POLARITY_REVERSED) >>
6894 IFE_PESC_POLARITY_REVERSED_SHIFT;
1da177e4
LT		 6895 }
6896 return E1000_SUCCESS;
6897}
6898
6899/******************************************************************************
6900 * Check if Downshift occured
6901 *
6902 * hw - Struct containing variables accessed by shared code
6903 * downshift - output parameter : 0 - No Downshift ocured.
6904 * 1 - Downshift ocured.
6905 *
6906 * returns: - E1000_ERR_XXX
76c224bc 6907 * E1000_SUCCESS
1da177e4
LT		 6908 *
6909 * For phy's older then IGP, this function reads the Downshift bit in the Phy
6910 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
6911 * Link Health register. In IGP this bit is latched high, so the driver must
6912 * read it immediately after link is established.
6913 *****************************************************************************/
3ad2cc67 6914static int32_t
1da177e4
LT		 6915e1000_check_downshift(struct e1000_hw *hw)
6916{
6917 int32_t ret_val;
6918 uint16_t phy_data;
6919
6920 DEBUGFUNC("e1000_check_downshift");
6921
cd94dd0b
AK		 6922 if (hw->phy_type == e1000_phy_igp ||
6923 hw->phy_type == e1000_phy_igp_3 ||
2d7edb92 6924 hw->phy_type == e1000_phy_igp_2) {
1da177e4
LT		 6925 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
6926 &phy_data);
8fc897b0 6927 if (ret_val)
1da177e4
LT		 6928 return ret_val;
6929
6930 hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
6418ecc6
JK		 6931 } else if ((hw->phy_type == e1000_phy_m88) ||
6932 (hw->phy_type == e1000_phy_gg82563)) {
1da177e4
LT		 6933 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6934 &phy_data);
8fc897b0 6935 if (ret_val)
1da177e4
LT		 6936 return ret_val;
6937
6938 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
6939 M88E1000_PSSR_DOWNSHIFT_SHIFT;
cd94dd0b
AK		 6940 } else if (hw->phy_type == e1000_phy_ife) {
6941 /* e1000_phy_ife supports 10/100 speed only */
6942 hw->speed_downgraded = FALSE;
1da177e4 6943 }
2d7edb92 6944
1da177e4
LT		 6945 return E1000_SUCCESS;
6946}
6947
6948/*****************************************************************************
6949 *
6950 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
6951 * gigabit link is achieved to improve link quality.
6952 *
6953 * hw: Struct containing variables accessed by shared code
6954 *
6955 * returns: - E1000_ERR_PHY if fail to read/write the PHY
6956 * E1000_SUCCESS at any other case.
6957 *
6958 ****************************************************************************/
6959
3ad2cc67 6960static int32_t
1da177e4
LT		 6961e1000_config_dsp_after_link_change(struct e1000_hw *hw,
6962 boolean_t link_up)
6963{
6964 int32_t ret_val;
6965 uint16_t phy_data, phy_saved_data, speed, duplex, i;
6966 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6967 {IGP01E1000_PHY_AGC_PARAM_A,
6968 IGP01E1000_PHY_AGC_PARAM_B,
6969 IGP01E1000_PHY_AGC_PARAM_C,
6970 IGP01E1000_PHY_AGC_PARAM_D};
6971 uint16_t min_length, max_length;
6972
6973 DEBUGFUNC("e1000_config_dsp_after_link_change");
6974
8fc897b0 6975 if (hw->phy_type != e1000_phy_igp)
1da177e4
LT		 6976 return E1000_SUCCESS;
6977
8fc897b0 6978 if (link_up) {
1da177e4 6979 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
8fc897b0 6980 if (ret_val) {
1da177e4
LT		 6981 DEBUGOUT("Error getting link speed and duplex\n");
6982 return ret_val;
6983 }
6984
8fc897b0 6985 if (speed == SPEED_1000) {
1da177e4 6986
cd94dd0b
AK		 6987 ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
6988 if (ret_val)
6989 return ret_val;
1da177e4 6990
8fc897b0 6991 if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
1da177e4
LT		 6992 min_length >= e1000_igp_cable_length_50) {
6993
8fc897b0 6994 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4
LT		 6995 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
6996 &phy_data);
8fc897b0 6997 if (ret_val)
1da177e4
LT		 6998 return ret_val;
6999
7000 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7001
7002 ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7003 phy_data);
8fc897b0 7004 if (ret_val)
1da177e4
LT		 7005 return ret_val;
7006 }
7007 hw->dsp_config_state = e1000_dsp_config_activated;
7008 }
7009
8fc897b0 7010 if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
1da177e4
LT		 7011 (min_length < e1000_igp_cable_length_50)) {
7012
7013 uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7014 uint32_t idle_errs = 0;
7015
7016 /* clear previous idle error counts */
7017 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7018 &phy_data);
8fc897b0 7019 if (ret_val)
1da177e4
LT		 7020 return ret_val;
7021
8fc897b0 7022 for (i = 0; i < ffe_idle_err_timeout; i++) {
1da177e4
LT		 7023 udelay(1000);
7024 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7025 &phy_data);
8fc897b0 7026 if (ret_val)
1da177e4
LT		 7027 return ret_val;
7028
7029 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
8fc897b0 7030 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
1da177e4
LT		 7031 hw->ffe_config_state = e1000_ffe_config_active;
7032
7033 ret_val = e1000_write_phy_reg(hw,
7034 IGP01E1000_PHY_DSP_FFE,
7035 IGP01E1000_PHY_DSP_FFE_CM_CP);
8fc897b0 7036 if (ret_val)
1da177e4
LT		 7037 return ret_val;
7038 break;
7039 }
7040
8fc897b0 7041 if (idle_errs)
1da177e4
LT		 7042 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7043 }
7044 }
7045 }
7046 } else {
8fc897b0 7047 if (hw->dsp_config_state == e1000_dsp_config_activated) {
1da177e4
LT		 7048 /* Save off the current value of register 0x2F5B to be restored at
7049 * the end of the routines. */
7050 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7051
8fc897b0 7052 if (ret_val)
1da177e4
LT		 7053 return ret_val;
7054
7055 /* Disable the PHY transmitter */
7056 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7057
8fc897b0 7058 if (ret_val)
1da177e4
LT		 7059 return ret_val;
7060
2d7edb92 7061 msec_delay_irq(20);
1da177e4
LT		 7062
7063 ret_val = e1000_write_phy_reg(hw, 0x0000,
7064 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7065 if (ret_val)
1da177e4 7066 return ret_val;
8fc897b0 7067 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
1da177e4 7068 ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
8fc897b0 7069 if (ret_val)
1da177e4
LT		 7070 return ret_val;
7071
7072 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7073 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7074
7075 ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
8fc897b0 7076 if (ret_val)
1da177e4
LT		 7077 return ret_val;
7078 }
7079
7080 ret_val = e1000_write_phy_reg(hw, 0x0000,
7081 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7082 if (ret_val)
1da177e4
LT		 7083 return ret_val;
7084
2d7edb92 7085 msec_delay_irq(20);
1da177e4
LT		 7086
7087 /* Now enable the transmitter */
7088 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7089
8fc897b0 7090 if (ret_val)
1da177e4
LT		 7091 return ret_val;
7092
7093 hw->dsp_config_state = e1000_dsp_config_enabled;
7094 }
7095
8fc897b0 7096 if (hw->ffe_config_state == e1000_ffe_config_active) {
1da177e4
LT		 7097 /* Save off the current value of register 0x2F5B to be restored at
7098 * the end of the routines. */
7099 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7100
8fc897b0 7101 if (ret_val)
1da177e4
LT		 7102 return ret_val;
7103
7104 /* Disable the PHY transmitter */
7105 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7106
8fc897b0 7107 if (ret_val)
1da177e4
LT		 7108 return ret_val;
7109
2d7edb92 7110 msec_delay_irq(20);
1da177e4
LT		 7111
7112 ret_val = e1000_write_phy_reg(hw, 0x0000,
7113 IGP01E1000_IEEE_FORCE_GIGA);
8fc897b0 7114 if (ret_val)
1da177e4
LT		 7115 return ret_val;
7116 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7117 IGP01E1000_PHY_DSP_FFE_DEFAULT);
8fc897b0 7118 if (ret_val)
1da177e4
LT		 7119 return ret_val;
7120
7121 ret_val = e1000_write_phy_reg(hw, 0x0000,
7122 IGP01E1000_IEEE_RESTART_AUTONEG);
8fc897b0 7123 if (ret_val)
1da177e4
LT		 7124 return ret_val;
7125
2d7edb92 7126 msec_delay_irq(20);
1da177e4
LT		 7127
7128 /* Now enable the transmitter */
7129 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7130
8fc897b0 7131 if (ret_val)
1da177e4
LT		 7132 return ret_val;
7133
7134 hw->ffe_config_state = e1000_ffe_config_enabled;
7135 }
7136 }
7137 return E1000_SUCCESS;
7138}
7139
7140/*****************************************************************************
7141 * Set PHY to class A mode
7142 * Assumes the following operations will follow to enable the new class mode.
7143 * 1. Do a PHY soft reset
7144 * 2. Restart auto-negotiation or force link.
7145 *
7146 * hw - Struct containing variables accessed by shared code
7147 ****************************************************************************/
7148static int32_t
7149e1000_set_phy_mode(struct e1000_hw *hw)
7150{
7151 int32_t ret_val;
7152 uint16_t eeprom_data;
7153
7154 DEBUGFUNC("e1000_set_phy_mode");
7155
8fc897b0
AK		 7156 if ((hw->mac_type == e1000_82545_rev_3) &&
7157 (hw->media_type == e1000_media_type_copper)) {
1da177e4 7158 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
8fc897b0 7159 if (ret_val) {
1da177e4
LT		 7160 return ret_val;
7161 }
7162
8fc897b0
AK		 7163 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7164 (eeprom_data & EEPROM_PHY_CLASS_A)) {
1da177e4 7165 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
8fc897b0 7166 if (ret_val)
1da177e4
LT		 7167 return ret_val;
7168 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
8fc897b0 7169 if (ret_val)
1da177e4
LT		 7170 return ret_val;
7171
7172 hw->phy_reset_disable = FALSE;
7173 }
7174 }
7175
7176 return E1000_SUCCESS;
7177}
7178
7179/*****************************************************************************
7180 *
7181 * This function sets the lplu state according to the active flag. When
7182 * activating lplu this function also disables smart speed and vise versa.
7183 * lplu will not be activated unless the device autonegotiation advertisment
7184 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7185 * hw: Struct containing variables accessed by shared code
7186 * active - true to enable lplu false to disable lplu.
7187 *
7188 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7189 * E1000_SUCCESS at any other case.
7190 *
7191 ****************************************************************************/
7192
3ad2cc67 7193static int32_t
1da177e4
LT		 7194e1000_set_d3_lplu_state(struct e1000_hw *hw,
7195 boolean_t active)
7196{
cd94dd0b 7197 uint32_t phy_ctrl = 0;
1da177e4
LT		 7198 int32_t ret_val;
7199 uint16_t phy_data;
7200 DEBUGFUNC("e1000_set_d3_lplu_state");
7201
cd94dd0b
AK		 7202 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7203 && hw->phy_type != e1000_phy_igp_3)
1da177e4
LT		 7204 return E1000_SUCCESS;
7205
7206 /* During driver activity LPLU should not be used or it will attain link
7207 * from the lowest speeds starting from 10Mbps. The capability is used for
7208 * Dx transitions and states */
cd94dd0b 7209 if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
2d7edb92 7210 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
cd94dd0b 7211 if (ret_val)
2d7edb92 7212 return ret_val;
cd94dd0b
AK		 7213 } else if (hw->mac_type == e1000_ich8lan) {
7214 /* MAC writes into PHY register based on the state transition
7215 * and start auto-negotiation. SW driver can overwrite the settings
7216 * in CSR PHY power control E1000_PHY_CTRL register. */
7217 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2d7edb92
MC		 7218 } else {
7219 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7220 if (ret_val)
1da177e4 7221 return ret_val;
2d7edb92
MC		 7222 }
7223
8fc897b0
AK		 7224 if (!active) {
7225 if (hw->mac_type == e1000_82541_rev_2 ||
7226 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7227 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7228 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7229 if (ret_val)
2d7edb92
MC		 7230 return ret_val;
7231 } else {
cd94dd0b
AK		 7232 if (hw->mac_type == e1000_ich8lan) {
7233 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7234 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7235 } else {
2d7edb92
MC		 7236 phy_data &= ~IGP02E1000_PM_D3_LPLU;
7237 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7238 phy_data);
7239 if (ret_val)
7240 return ret_val;
cd94dd0b 7241 }
2d7edb92 7242 }
1da177e4
LT		 7243
7244 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7245 * Dx states where the power conservation is most important. During
7246 * driver activity we should enable SmartSpeed, so performance is
7247 * maintained. */
7248 if (hw->smart_speed == e1000_smart_speed_on) {
7249 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7250 &phy_data);
8fc897b0 7251 if (ret_val)
1da177e4
LT		 7252 return ret_val;
7253
7254 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7255 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7256 phy_data);
8fc897b0 7257 if (ret_val)
1da177e4
LT		 7258 return ret_val;
7259 } else if (hw->smart_speed == e1000_smart_speed_off) {
7260 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7261 &phy_data);
7262 if (ret_val)
7263 return ret_val;
7264
7265 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7266 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7267 phy_data);
8fc897b0 7268 if (ret_val)
1da177e4
LT		 7269 return ret_val;
7270 }
7271
8fc897b0
AK		 7272 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) ||
7273 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) ||
7274 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
1da177e4 7275
8fc897b0 7276 if (hw->mac_type == e1000_82541_rev_2 ||
cd94dd0b 7277 hw->mac_type == e1000_82547_rev_2) {
2d7edb92
MC		 7278 phy_data |= IGP01E1000_GMII_FLEX_SPD;
7279 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
8fc897b0 7280 if (ret_val)
2d7edb92
MC		 7281 return ret_val;
7282 } else {
cd94dd0b
AK		 7283 if (hw->mac_type == e1000_ich8lan) {
7284 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
7285 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7286 } else {
2d7edb92
MC		 7287 phy_data |= IGP02E1000_PM_D3_LPLU;
7288 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7289 phy_data);
7290 if (ret_val)
7291 return ret_val;
cd94dd0b 7292 }
2d7edb92
MC		 7293 }
7294
7295 /* When LPLU is enabled we should disable SmartSpeed */
7296 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7297 if (ret_val)
2d7edb92
MC		 7298 return ret_val;
7299
7300 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7301 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7302 if (ret_val)
2d7edb92
MC		 7303 return ret_val;
7304
7305 }
7306 return E1000_SUCCESS;
7307}
7308
7309/*****************************************************************************
7310 *
7311 * This function sets the lplu d0 state according to the active flag. When
7312 * activating lplu this function also disables smart speed and vise versa.
7313 * lplu will not be activated unless the device autonegotiation advertisment
7314 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7315 * hw: Struct containing variables accessed by shared code
7316 * active - true to enable lplu false to disable lplu.
7317 *
7318 * returns: - E1000_ERR_PHY if fail to read/write the PHY
7319 * E1000_SUCCESS at any other case.
7320 *
7321 ****************************************************************************/
7322
3ad2cc67 7323static int32_t
2d7edb92
MC		 7324e1000_set_d0_lplu_state(struct e1000_hw *hw,
7325 boolean_t active)
7326{
cd94dd0b 7327 uint32_t phy_ctrl = 0;
2d7edb92
MC		 7328 int32_t ret_val;
7329 uint16_t phy_data;
7330 DEBUGFUNC("e1000_set_d0_lplu_state");
7331
8fc897b0 7332 if (hw->mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 7333 return E1000_SUCCESS;
7334
cd94dd0b
AK		 7335 if (hw->mac_type == e1000_ich8lan) {
7336 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7337 } else {
2d7edb92 7338 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
8fc897b0 7339 if (ret_val)
1da177e4 7340 return ret_val;
cd94dd0b 7341 }
1da177e4 7342
2d7edb92 7343 if (!active) {
cd94dd0b
AK		 7344 if (hw->mac_type == e1000_ich8lan) {
7345 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7346 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7347 } else {
2d7edb92
MC		 7348 phy_data &= ~IGP02E1000_PM_D0_LPLU;
7349 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7350 if (ret_val)
7351 return ret_val;
cd94dd0b 7352 }
2d7edb92
MC		 7353
7354 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7355 * Dx states where the power conservation is most important. During
7356 * driver activity we should enable SmartSpeed, so performance is
7357 * maintained. */
7358 if (hw->smart_speed == e1000_smart_speed_on) {
7359 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7360 &phy_data);
8fc897b0 7361 if (ret_val)
2d7edb92
MC		 7362 return ret_val;
7363
7364 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
7365 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7366 phy_data);
8fc897b0 7367 if (ret_val)
2d7edb92
MC		 7368 return ret_val;
7369 } else if (hw->smart_speed == e1000_smart_speed_off) {
7370 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7371 &phy_data);
7372 if (ret_val)
7373 return ret_val;
7374
7375 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7376 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7377 phy_data);
8fc897b0 7378 if (ret_val)
2d7edb92
MC		 7379 return ret_val;
7380 }
7381
7382
7383 } else {
76c224bc 7384
cd94dd0b
AK		 7385 if (hw->mac_type == e1000_ich8lan) {
7386 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
7387 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7388 } else {
76c224bc 7389 phy_data |= IGP02E1000_PM_D0_LPLU;
2d7edb92
MC		 7390 ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7391 if (ret_val)
7392 return ret_val;
cd94dd0b 7393 }
2d7edb92 7394
1da177e4
LT		 7395 /* When LPLU is enabled we should disable SmartSpeed */
7396 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
8fc897b0 7397 if (ret_val)
1da177e4
LT		 7398 return ret_val;
7399
7400 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7401 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
8fc897b0 7402 if (ret_val)
1da177e4
LT		 7403 return ret_val;
7404
7405 }
7406 return E1000_SUCCESS;
7407}
7408
7409/******************************************************************************
7410 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
7411 *
7412 * hw - Struct containing variables accessed by shared code
7413 *****************************************************************************/
7414static int32_t
7415e1000_set_vco_speed(struct e1000_hw *hw)
7416{
7417 int32_t ret_val;
7418 uint16_t default_page = 0;
7419 uint16_t phy_data;
7420
7421 DEBUGFUNC("e1000_set_vco_speed");
7422
8fc897b0 7423 switch (hw->mac_type) {
1da177e4
LT		 7424 case e1000_82545_rev_3:
7425 case e1000_82546_rev_3:
7426 break;
7427 default:
7428 return E1000_SUCCESS;
7429 }
7430
7431 /* Set PHY register 30, page 5, bit 8 to 0 */
7432
7433 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
8fc897b0 7434 if (ret_val)
1da177e4
LT		 7435 return ret_val;
7436
7437 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
8fc897b0 7438 if (ret_val)
1da177e4
LT		 7439 return ret_val;
7440
7441 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7442 if (ret_val)
1da177e4
LT		 7443 return ret_val;
7444
7445 phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7446 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7447 if (ret_val)
1da177e4
LT		 7448 return ret_val;
7449
7450 /* Set PHY register 30, page 4, bit 11 to 1 */
7451
7452 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
8fc897b0 7453 if (ret_val)
1da177e4
LT		 7454 return ret_val;
7455
7456 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
8fc897b0 7457 if (ret_val)
1da177e4
LT		 7458 return ret_val;
7459
7460 phy_data |= M88E1000_PHY_VCO_REG_BIT11;
7461 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
8fc897b0 7462 if (ret_val)
1da177e4
LT		 7463 return ret_val;
7464
7465 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
8fc897b0 7466 if (ret_val)
1da177e4
LT		 7467 return ret_val;
7468
7469 return E1000_SUCCESS;
7470}
7471
1da177e4 7472
2d7edb92
MC		 7473/*****************************************************************************
7474 * This function reads the cookie from ARC ram.
7475 *
7476 * returns: - E1000_SUCCESS .
7477 ****************************************************************************/
7478int32_t
7479e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7480{
7481 uint8_t i;
76c224bc 7482 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
2d7edb92 7483 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
1da177e4 7484
2d7edb92
MC		 7485 length = (length >> 2);
7486 offset = (offset >> 2);
1da177e4 7487
2d7edb92
MC		 7488 for (i = 0; i < length; i++) {
7489 *((uint32_t *) buffer + i) =
7490 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7491 }
7492 return E1000_SUCCESS;
7493}
7494
7495
7496/*****************************************************************************
7497 * This function checks whether the HOST IF is enabled for command operaton
7498 * and also checks whether the previous command is completed.
7499 * It busy waits in case of previous command is not completed.
7500 *
76c224bc 7501 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
2d7edb92
MC		 7502 * timeout
7503 * - E1000_SUCCESS for success.
7504 ****************************************************************************/
3ad2cc67 7505static int32_t
2d7edb92
MC		 7506e1000_mng_enable_host_if(struct e1000_hw * hw)
7507{
7508 uint32_t hicr;
7509 uint8_t i;
7510
7511 /* Check that the host interface is enabled. */
7512 hicr = E1000_READ_REG(hw, HICR);
7513 if ((hicr & E1000_HICR_EN) == 0) {
7514 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7515 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7516 }
7517 /* check the previous command is completed */
7518 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7519 hicr = E1000_READ_REG(hw, HICR);
7520 if (!(hicr & E1000_HICR_C))
7521 break;
7522 msec_delay_irq(1);
7523 }
7524
76c224bc 7525 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
2d7edb92
MC		 7526 DEBUGOUT("Previous command timeout failed .\n");
7527 return -E1000_ERR_HOST_INTERFACE_COMMAND;
7528 }
7529 return E1000_SUCCESS;
7530}
7531
7532/*****************************************************************************
7533 * This function writes the buffer content at the offset given on the host if.
7534 * It also does alignment considerations to do the writes in most efficient way.
7535 * Also fills up the sum of the buffer in *buffer parameter.
7536 *
7537 * returns - E1000_SUCCESS for success.
7538 ****************************************************************************/
3ad2cc67 7539static int32_t
2d7edb92
MC		 7540e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7541 uint16_t length, uint16_t offset, uint8_t *sum)
7542{
7543 uint8_t *tmp;
7544 uint8_t *bufptr = buffer;
8fc897b0 7545 uint32_t data = 0;
2d7edb92
MC		 7546 uint16_t remaining, i, j, prev_bytes;
7547
7548 /* sum = only sum of the data and it is not checksum */
7549
7550 if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7551 return -E1000_ERR_PARAM;
7552 }
7553
7554 tmp = (uint8_t *)&data;
7555 prev_bytes = offset & 0x3;
7556 offset &= 0xFFFC;
7557 offset >>= 2;
7558
7559 if (prev_bytes) {
7560 data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7561 for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7562 *(tmp + j) = *bufptr++;
7563 *sum += *(tmp + j);
7564 }
7565 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7566 length -= j - prev_bytes;
7567 offset++;
7568 }
7569
7570 remaining = length & 0x3;
7571 length -= remaining;
7572
7573 /* Calculate length in DWORDs */
7574 length >>= 2;
7575
7576 /* The device driver writes the relevant command block into the
7577 * ram area. */
7578 for (i = 0; i < length; i++) {
7579 for (j = 0; j < sizeof(uint32_t); j++) {
7580 *(tmp + j) = *bufptr++;
7581 *sum += *(tmp + j);
7582 }
7583
7584 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7585 }
7586 if (remaining) {
7587 for (j = 0; j < sizeof(uint32_t); j++) {
7588 if (j < remaining)
7589 *(tmp + j) = *bufptr++;
7590 else
7591 *(tmp + j) = 0;
7592
7593 *sum += *(tmp + j);
7594 }
7595 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7596 }
7597
7598 return E1000_SUCCESS;
7599}
7600
7601
7602/*****************************************************************************
7603 * This function writes the command header after does the checksum calculation.
7604 *
7605 * returns - E1000_SUCCESS for success.
7606 ****************************************************************************/
3ad2cc67 7607static int32_t
2d7edb92
MC		 7608e1000_mng_write_cmd_header(struct e1000_hw * hw,
7609 struct e1000_host_mng_command_header * hdr)
7610{
7611 uint16_t i;
7612 uint8_t sum;
7613 uint8_t *buffer;
7614
7615 /* Write the whole command header structure which includes sum of
7616 * the buffer */
7617
7618 uint16_t length = sizeof(struct e1000_host_mng_command_header);
7619
7620 sum = hdr->checksum;
7621 hdr->checksum = 0;
7622
7623 buffer = (uint8_t *) hdr;
7624 i = length;
8fc897b0 7625 while (i--)
2d7edb92
MC		 7626 sum += buffer[i];
7627
7628 hdr->checksum = 0 - sum;
7629
7630 length >>= 2;
7631 /* The device driver writes the relevant command block into the ram area. */
4ca213a6 7632 for (i = 0; i < length; i++) {
2d7edb92 7633 E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i));
4ca213a6
AK		 7634 E1000_WRITE_FLUSH(hw);
7635 }
2d7edb92
MC		 7636
7637 return E1000_SUCCESS;
7638}
7639
7640
7641/*****************************************************************************
7642 * This function indicates to ARC that a new command is pending which completes
7643 * one write operation by the driver.
7644 *
7645 * returns - E1000_SUCCESS for success.
7646 ****************************************************************************/
3ad2cc67 7647static int32_t
8fc897b0 7648e1000_mng_write_commit(struct e1000_hw * hw)
2d7edb92
MC		 7649{
7650 uint32_t hicr;
7651
7652 hicr = E1000_READ_REG(hw, HICR);
7653 /* Setting this bit tells the ARC that a new command is pending. */
7654 E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C);
7655
7656 return E1000_SUCCESS;
7657}
7658
7659
7660/*****************************************************************************
7661 * This function checks the mode of the firmware.
7662 *
7663 * returns - TRUE when the mode is IAMT or FALSE.
7664 ****************************************************************************/
7665boolean_t
cd94dd0b 7666e1000_check_mng_mode(struct e1000_hw *hw)
2d7edb92
MC		 7667{
7668 uint32_t fwsm;
7669
7670 fwsm = E1000_READ_REG(hw, FWSM);
7671
cd94dd0b
AK		 7672 if (hw->mac_type == e1000_ich8lan) {
7673 if ((fwsm & E1000_FWSM_MODE_MASK) ==
7674 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7675 return TRUE;
7676 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7677 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2d7edb92
MC		 7678 return TRUE;
7679
7680 return FALSE;
7681}
7682
7683
7684/*****************************************************************************
7685 * This function writes the dhcp info .
7686 ****************************************************************************/
7687int32_t
7688e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7689 uint16_t length)
7690{
7691 int32_t ret_val;
7692 struct e1000_host_mng_command_header hdr;
7693
7694 hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7695 hdr.command_length = length;
7696 hdr.reserved1 = 0;
7697 hdr.reserved2 = 0;
7698 hdr.checksum = 0;
7699
7700 ret_val = e1000_mng_enable_host_if(hw);
7701 if (ret_val == E1000_SUCCESS) {
7702 ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7703 &(hdr.checksum));
7704 if (ret_val == E1000_SUCCESS) {
7705 ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7706 if (ret_val == E1000_SUCCESS)
7707 ret_val = e1000_mng_write_commit(hw);
7708 }
7709 }
7710 return ret_val;
7711}
7712
7713
7714/*****************************************************************************
7715 * This function calculates the checksum.
7716 *
7717 * returns - checksum of buffer contents.
7718 ****************************************************************************/
7719uint8_t
7720e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7721{
7722 uint8_t sum = 0;
7723 uint32_t i;
7724
7725 if (!buffer)
7726 return 0;
7727
7728 for (i=0; i < length; i++)
7729 sum += buffer[i];
7730
7731 return (uint8_t) (0 - sum);
7732}
7733
7734/*****************************************************************************
7735 * This function checks whether tx pkt filtering needs to be enabled or not.
7736 *
7737 * returns - TRUE for packet filtering or FALSE.
7738 ****************************************************************************/
7739boolean_t
7740e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7741{
7742 /* called in init as well as watchdog timer functions */
7743
7744 int32_t ret_val, checksum;
7745 boolean_t tx_filter = FALSE;
7746 struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7747 uint8_t *buffer = (uint8_t *) &(hw->mng_cookie);
7748
7749 if (e1000_check_mng_mode(hw)) {
7750 ret_val = e1000_mng_enable_host_if(hw);
7751 if (ret_val == E1000_SUCCESS) {
7752 ret_val = e1000_host_if_read_cookie(hw, buffer);
7753 if (ret_val == E1000_SUCCESS) {
7754 checksum = hdr->checksum;
7755 hdr->checksum = 0;
7756 if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7757 checksum == e1000_calculate_mng_checksum((char *)buffer,
7758 E1000_MNG_DHCP_COOKIE_LENGTH)) {
7759 if (hdr->status &
7760 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7761 tx_filter = TRUE;
7762 } else
7763 tx_filter = TRUE;
7764 } else
7765 tx_filter = TRUE;
7766 }
7767 }
7768
7769 hw->tx_pkt_filtering = tx_filter;
7770 return tx_filter;
7771}
7772
7773/******************************************************************************
7774 * Verifies the hardware needs to allow ARPs to be processed by the host
7775 *
7776 * hw - Struct containing variables accessed by shared code
7777 *
7778 * returns: - TRUE/FALSE
7779 *
7780 *****************************************************************************/
7781uint32_t
7782e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7783{
7784 uint32_t manc;
7785 uint32_t fwsm, factps;
7786
7787 if (hw->asf_firmware_present) {
7788 manc = E1000_READ_REG(hw, MANC);
7789
7790 if (!(manc & E1000_MANC_RCV_TCO_EN) ||
7791 !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7792 return FALSE;
7793 if (e1000_arc_subsystem_valid(hw) == TRUE) {
7794 fwsm = E1000_READ_REG(hw, FWSM);
7795 factps = E1000_READ_REG(hw, FACTPS);
7796
7797 if (((fwsm & E1000_FWSM_MODE_MASK) ==
7798 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)) &&
7799 (factps & E1000_FACTPS_MNGCG))
7800 return TRUE;
7801 } else
7802 if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7803 return TRUE;
7804 }
7805 return FALSE;
7806}
7807
7808static int32_t
7809e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7810{
7811 int32_t ret_val;
7812 uint16_t mii_status_reg;
7813 uint16_t i;
7814
7815 /* Polarity reversal workaround for forced 10F/10H links. */
7816
7817 /* Disable the transmitter on the PHY */
7818
7819 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7820 if (ret_val)
1da177e4
LT		 7821 return ret_val;
7822 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
8fc897b0 7823 if (ret_val)
1da177e4
LT		 7824 return ret_val;
7825
7826 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7827 if (ret_val)
1da177e4
LT		 7828 return ret_val;
7829
7830 /* This loop will early-out if the NO link condition has been met. */
8fc897b0 7831 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7832 /* Read the MII Status Register and wait for Link Status bit
7833 * to be clear.
7834 */
7835
7836 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7837 if (ret_val)
1da177e4
LT		 7838 return ret_val;
7839
7840 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7841 if (ret_val)
1da177e4
LT		 7842 return ret_val;
7843
8fc897b0 7844 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
1da177e4
LT		 7845 msec_delay_irq(100);
7846 }
7847
7848 /* Recommended delay time after link has been lost */
7849 msec_delay_irq(1000);
7850
7851 /* Now we will re-enable th transmitter on the PHY */
7852
7853 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8fc897b0 7854 if (ret_val)
1da177e4
LT		 7855 return ret_val;
7856 msec_delay_irq(50);
7857 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8fc897b0 7858 if (ret_val)
1da177e4
LT		 7859 return ret_val;
7860 msec_delay_irq(50);
7861 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8fc897b0 7862 if (ret_val)
1da177e4
LT		 7863 return ret_val;
7864 msec_delay_irq(50);
7865 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8fc897b0 7866 if (ret_val)
1da177e4
LT		 7867 return ret_val;
7868
7869 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8fc897b0 7870 if (ret_val)
1da177e4
LT		 7871 return ret_val;
7872
7873 /* This loop will early-out if the link condition has been met. */
8fc897b0 7874 for (i = PHY_FORCE_TIME; i > 0; i--) {
1da177e4
LT		 7875 /* Read the MII Status Register and wait for Link Status bit
7876 * to be set.
7877 */
7878
7879 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7880 if (ret_val)
1da177e4
LT		 7881 return ret_val;
7882
7883 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8fc897b0 7884 if (ret_val)
1da177e4
LT		 7885 return ret_val;
7886
8fc897b0 7887 if (mii_status_reg & MII_SR_LINK_STATUS) break;
1da177e4
LT		 7888 msec_delay_irq(100);
7889 }
7890 return E1000_SUCCESS;
7891}
7892
2d7edb92
MC		 7893/***************************************************************************
7894 *
7895 * Disables PCI-Express master access.
7896 *
7897 * hw: Struct containing variables accessed by shared code
7898 *
7899 * returns: - none.
7900 *
7901 ***************************************************************************/
3ad2cc67 7902static void
2d7edb92
MC		 7903e1000_set_pci_express_master_disable(struct e1000_hw *hw)
7904{
7905 uint32_t ctrl;
7906
7907 DEBUGFUNC("e1000_set_pci_express_master_disable");
7908
7909 if (hw->bus_type != e1000_bus_type_pci_express)
7910 return;
7911
7912 ctrl = E1000_READ_REG(hw, CTRL);
7913 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
7914 E1000_WRITE_REG(hw, CTRL, ctrl);
7915}
7916
7917/***************************************************************************
7918 *
7919 * Enables PCI-Express master access.
7920 *
7921 * hw: Struct containing variables accessed by shared code
7922 *
7923 * returns: - none.
7924 *
7925 ***************************************************************************/
e4c780b1 7926#if 0
2d7edb92
MC		 7927void
7928e1000_enable_pciex_master(struct e1000_hw *hw)
7929{
7930 uint32_t ctrl;
7931
7932 DEBUGFUNC("e1000_enable_pciex_master");
7933
7934 if (hw->bus_type != e1000_bus_type_pci_express)
7935 return;
7936
7937 ctrl = E1000_READ_REG(hw, CTRL);
7938 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE;
7939 E1000_WRITE_REG(hw, CTRL, ctrl);
7940}
e4c780b1 7941#endif /* 0 */
2d7edb92
MC		 7942
7943/*******************************************************************************
7944 *
7945 * Disables PCI-Express master access and verifies there are no pending requests
7946 *
7947 * hw: Struct containing variables accessed by shared code
7948 *
7949 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
7950 * caused the master requests to be disabled.
7951 * E1000_SUCCESS master requests disabled.
7952 *
7953 ******************************************************************************/
7954int32_t
7955e1000_disable_pciex_master(struct e1000_hw *hw)
7956{
7957 int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
7958
7959 DEBUGFUNC("e1000_disable_pciex_master");
7960
7961 if (hw->bus_type != e1000_bus_type_pci_express)
7962 return E1000_SUCCESS;
7963
7964 e1000_set_pci_express_master_disable(hw);
7965
8fc897b0
AK		 7966 while (timeout) {
7967 if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
2d7edb92
MC		 7968 break;
7969 else
7970 udelay(100);
7971 timeout--;
7972 }
7973
8fc897b0 7974 if (!timeout) {
2d7edb92
MC		 7975 DEBUGOUT("Master requests are pending.\n");
7976 return -E1000_ERR_MASTER_REQUESTS_PENDING;
7977 }
7978
7979 return E1000_SUCCESS;
7980}
7981
7982/*******************************************************************************
7983 *
7984 * Check for EEPROM Auto Read bit done.
7985 *
7986 * hw: Struct containing variables accessed by shared code
7987 *
7988 * returns: - E1000_ERR_RESET if fail to reset MAC
7989 * E1000_SUCCESS at any other case.
7990 *
7991 ******************************************************************************/
3ad2cc67 7992static int32_t
2d7edb92
MC		 7993e1000_get_auto_rd_done(struct e1000_hw *hw)
7994{
7995 int32_t timeout = AUTO_READ_DONE_TIMEOUT;
7996
7997 DEBUGFUNC("e1000_get_auto_rd_done");
7998
7999 switch (hw->mac_type) {
8000 default:
8001 msec_delay(5);
8002 break;
868d5309
MC		 8003 case e1000_82571:
8004 case e1000_82572:
2d7edb92 8005 case e1000_82573:
6418ecc6 8006 case e1000_80003es2lan:
cd94dd0b
AK		 8007 case e1000_ich8lan:
8008 while (timeout) {
8009 if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8010 break;
2d7edb92
MC		 8011 else msec_delay(1);
8012 timeout--;
8013 }
8014
8fc897b0 8015 if (!timeout) {
2d7edb92
MC		 8016 DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8017 return -E1000_ERR_RESET;
8018 }
8019 break;
8020 }
8021
fd803241
JK		 8022 /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8023 * Need to wait for PHY configuration completion before accessing NVM
8024 * and PHY. */
8025 if (hw->mac_type == e1000_82573)
8026 msec_delay(25);
8027
2d7edb92
MC		 8028 return E1000_SUCCESS;
8029}
8030
8031/***************************************************************************
8032 * Checks if the PHY configuration is done
8033 *
8034 * hw: Struct containing variables accessed by shared code
8035 *
8036 * returns: - E1000_ERR_RESET if fail to reset MAC
8037 * E1000_SUCCESS at any other case.
8038 *
8039 ***************************************************************************/
3ad2cc67 8040static int32_t
2d7edb92
MC		 8041e1000_get_phy_cfg_done(struct e1000_hw *hw)
8042{
868d5309
MC		 8043 int32_t timeout = PHY_CFG_TIMEOUT;
8044 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8045
2d7edb92
MC		 8046 DEBUGFUNC("e1000_get_phy_cfg_done");
8047
868d5309
MC		 8048 switch (hw->mac_type) {
8049 default:
cd94dd0b 8050 msec_delay_irq(10);
868d5309 8051 break;
6418ecc6
JK		 8052 case e1000_80003es2lan:
8053 /* Separate *_CFG_DONE_* bit for each port */
8054 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8055 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8056 /* Fall Through */
868d5309
MC		 8057 case e1000_82571:
8058 case e1000_82572:
8059 while (timeout) {
8060 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8061 break;
8062 else
8063 msec_delay(1);
8064 timeout--;
8065 }
8066
8067 if (!timeout) {
8068 DEBUGOUT("MNG configuration cycle has not completed.\n");
8069 return -E1000_ERR_RESET;
8070 }
8071 break;
8072 }
2d7edb92
MC		 8073
8074 return E1000_SUCCESS;
8075}
8076
8077/***************************************************************************
8078 *
8079 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
8080 * adapter or Eeprom access.
8081 *
8082 * hw: Struct containing variables accessed by shared code
8083 *
8084 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8085 * E1000_SUCCESS at any other case.
8086 *
8087 ***************************************************************************/
3ad2cc67 8088static int32_t
2d7edb92
MC		 8089e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8090{
8091 int32_t timeout;
8092 uint32_t swsm;
8093
8094 DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8095
8fc897b0 8096 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8097 return E1000_SUCCESS;
8098
6418ecc6
JK		 8099 if (hw->mac_type == e1000_80003es2lan) {
8100 /* Get the SW semaphore. */
8101 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8102 return -E1000_ERR_EEPROM;
8103 }
2d7edb92
MC		 8104
8105 /* Get the FW semaphore. */
8106 timeout = hw->eeprom.word_size + 1;
8fc897b0 8107 while (timeout) {
2d7edb92
MC		 8108 swsm = E1000_READ_REG(hw, SWSM);
8109 swsm |= E1000_SWSM_SWESMBI;
8110 E1000_WRITE_REG(hw, SWSM, swsm);
8111 /* if we managed to set the bit we got the semaphore. */
8112 swsm = E1000_READ_REG(hw, SWSM);
8fc897b0 8113 if (swsm & E1000_SWSM_SWESMBI)
2d7edb92
MC		 8114 break;
8115
8116 udelay(50);
8117 timeout--;
8118 }
8119
8fc897b0 8120 if (!timeout) {
2d7edb92
MC		 8121 /* Release semaphores */
8122 e1000_put_hw_eeprom_semaphore(hw);
8123 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8124 return -E1000_ERR_EEPROM;
8125 }
8126
8127 return E1000_SUCCESS;
8128}
8129
8130/***************************************************************************
8131 * This function clears HW semaphore bits.
8132 *
8133 * hw: Struct containing variables accessed by shared code
8134 *
8135 * returns: - None.
8136 *
8137 ***************************************************************************/
3ad2cc67 8138static void
2d7edb92
MC		 8139e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8140{
8141 uint32_t swsm;
8142
8143 DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8144
8fc897b0 8145 if (!hw->eeprom_semaphore_present)
2d7edb92
MC		 8146 return;
8147
8148 swsm = E1000_READ_REG(hw, SWSM);
6418ecc6
JK		 8149 if (hw->mac_type == e1000_80003es2lan) {
8150 /* Release both semaphores. */
8151 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
8152 } else
868d5309 8153 swsm &= ~(E1000_SWSM_SWESMBI);
2d7edb92
MC		 8154 E1000_WRITE_REG(hw, SWSM, swsm);
8155}
8156
6418ecc6
JK		 8157/***************************************************************************
8158 *
8159 * Obtaining software semaphore bit (SMBI) before resetting PHY.
8160 *
8161 * hw: Struct containing variables accessed by shared code
8162 *
8163 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
8164 * E1000_SUCCESS at any other case.
8165 *
8166 ***************************************************************************/
e4c780b1 8167static int32_t
6418ecc6
JK		 8168e1000_get_software_semaphore(struct e1000_hw *hw)
8169{
8170 int32_t timeout = hw->eeprom.word_size + 1;
8171 uint32_t swsm;
8172
8173 DEBUGFUNC("e1000_get_software_semaphore");
8174
8175 if (hw->mac_type != e1000_80003es2lan)
8176 return E1000_SUCCESS;
8177
8fc897b0 8178 while (timeout) {
6418ecc6
JK		 8179 swsm = E1000_READ_REG(hw, SWSM);
8180 /* If SMBI bit cleared, it is now set and we hold the semaphore */
8fc897b0 8181 if (!(swsm & E1000_SWSM_SMBI))
6418ecc6
JK		 8182 break;
8183 msec_delay_irq(1);
8184 timeout--;
8185 }
8186
8fc897b0 8187 if (!timeout) {
6418ecc6
JK		 8188 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8189 return -E1000_ERR_RESET;
8190 }
8191
8192 return E1000_SUCCESS;
8193}
8194
8195/***************************************************************************
8196 *
8197 * Release semaphore bit (SMBI).
8198 *
8199 * hw: Struct containing variables accessed by shared code
8200 *
8201 ***************************************************************************/
e4c780b1 8202static void
6418ecc6
JK		 8203e1000_release_software_semaphore(struct e1000_hw *hw)
8204{
8205 uint32_t swsm;
8206
8207 DEBUGFUNC("e1000_release_software_semaphore");
8208
8209 if (hw->mac_type != e1000_80003es2lan)
8210 return;
8211
8212 swsm = E1000_READ_REG(hw, SWSM);
8213 /* Release the SW semaphores.*/
8214 swsm &= ~E1000_SWSM_SMBI;
8215 E1000_WRITE_REG(hw, SWSM, swsm);
8216}
8217
2d7edb92
MC		 8218/******************************************************************************
8219 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
8220 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8221 * the caller to figure out how to deal with it.
8222 *
8223 * hw - Struct containing variables accessed by shared code
8224 *
8225 * returns: - E1000_BLK_PHY_RESET
8226 * E1000_SUCCESS
8227 *
8228 *****************************************************************************/
8229int32_t
8230e1000_check_phy_reset_block(struct e1000_hw *hw)
8231{
8232 uint32_t manc = 0;
cd94dd0b
AK		 8233 uint32_t fwsm = 0;
8234
8235 if (hw->mac_type == e1000_ich8lan) {
8236 fwsm = E1000_READ_REG(hw, FWSM);
8237 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8238 : E1000_BLK_PHY_RESET;
8239 }
96838a40
JB		 8240
8241 if (hw->mac_type > e1000_82547_rev_2)
2d7edb92
MC		 8242 manc = E1000_READ_REG(hw, MANC);
8243 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8244 E1000_BLK_PHY_RESET : E1000_SUCCESS;
8245}
8246
3ad2cc67 8247static uint8_t
2d7edb92
MC		 8248e1000_arc_subsystem_valid(struct e1000_hw *hw)
8249{
8250 uint32_t fwsm;
8251
8252 /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8253 * may not be provided a DMA clock when no manageability features are
8254 * enabled. We do not want to perform any reads/writes to these registers
8255 * if this is the case. We read FWSM to determine the manageability mode.
8256 */
8257 switch (hw->mac_type) {
868d5309
MC		 8258 case e1000_82571:
8259 case e1000_82572:
2d7edb92 8260 case e1000_82573:
6418ecc6 8261 case e1000_80003es2lan:
2d7edb92 8262 fwsm = E1000_READ_REG(hw, FWSM);
8fc897b0 8263 if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
2d7edb92
MC		 8264 return TRUE;
8265 break;
cd94dd0b
AK		 8266 case e1000_ich8lan:
8267 return TRUE;
2d7edb92
MC		 8268 default:
8269 break;
8270 }
8271 return FALSE;
8272}
8273
8274
d37ea5d5
AK		 8275/******************************************************************************
8276 * Configure PCI-Ex no-snoop
8277 *
8278 * hw - Struct containing variables accessed by shared code.
8279 * no_snoop - Bitmap of no-snoop events.
8280 *
8281 * returns: E1000_SUCCESS
8282 *
8283 *****************************************************************************/
e4c780b1 8284static int32_t
d37ea5d5
AK		 8285e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8286{
8287 uint32_t gcr_reg = 0;
8288
8289 DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8290
8291 if (hw->bus_type == e1000_bus_type_unknown)
8292 e1000_get_bus_info(hw);
8293
8294 if (hw->bus_type != e1000_bus_type_pci_express)
8295 return E1000_SUCCESS;
8296
8297 if (no_snoop) {
8298 gcr_reg = E1000_READ_REG(hw, GCR);
8299 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8300 gcr_reg |= no_snoop;
8301 E1000_WRITE_REG(hw, GCR, gcr_reg);
8302 }
8303 if (hw->mac_type == e1000_ich8lan) {
8304 uint32_t ctrl_ext;
8305
8306 E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8307
8308 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8309 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
8310 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8311 }
8312
8313 return E1000_SUCCESS;
8314}
8315
8316/***************************************************************************
8317 *
8318 * Get software semaphore FLAG bit (SWFLAG).
8319 * SWFLAG is used to synchronize the access to all shared resource between
8320 * SW, FW and HW.
8321 *
8322 * hw: Struct containing variables accessed by shared code
8323 *
8324 ***************************************************************************/
e4c780b1 8325static int32_t
d37ea5d5
AK		 8326e1000_get_software_flag(struct e1000_hw *hw)
8327{
8328 int32_t timeout = PHY_CFG_TIMEOUT;
8329 uint32_t extcnf_ctrl;
8330
8331 DEBUGFUNC("e1000_get_software_flag");
8332
8333 if (hw->mac_type == e1000_ich8lan) {
8334 while (timeout) {
8335 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8336 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
8337 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8338
8339 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8340 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8341 break;
8342 msec_delay_irq(1);
8343 timeout--;
8344 }
8345
8346 if (!timeout) {
8347 DEBUGOUT("FW or HW locks the resource too long.\n");
8348 return -E1000_ERR_CONFIG;
8349 }
8350 }
8351
8352 return E1000_SUCCESS;
8353}
8354
8355/***************************************************************************
8356 *
8357 * Release software semaphore FLAG bit (SWFLAG).
8358 * SWFLAG is used to synchronize the access to all shared resource between
8359 * SW, FW and HW.
8360 *
8361 * hw: Struct containing variables accessed by shared code
8362 *
8363 ***************************************************************************/
e4c780b1 8364static void
d37ea5d5
AK		 8365e1000_release_software_flag(struct e1000_hw *hw)
8366{
8367 uint32_t extcnf_ctrl;
8368
8369 DEBUGFUNC("e1000_release_software_flag");
8370
8371 if (hw->mac_type == e1000_ich8lan) {
8372 extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8373 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8374 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8375 }
8376
8377 return;
8378}
8379
8380/***************************************************************************
8381 *
8382 * Disable dynamic power down mode in ife PHY.
8383 * It can be used to workaround band-gap problem.
8384 *
8385 * hw: Struct containing variables accessed by shared code
8386 *
8387 ***************************************************************************/
e4c780b1 8388#if 0
d37ea5d5
AK		 8389int32_t
8390e1000_ife_disable_dynamic_power_down(struct e1000_hw *hw)
8391{
8392 uint16_t phy_data;
8393 int32_t ret_val = E1000_SUCCESS;
8394
8395 DEBUGFUNC("e1000_ife_disable_dynamic_power_down");
8396
8397 if (hw->phy_type == e1000_phy_ife) {
8398 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8399 if (ret_val)
8400 return ret_val;
8401
8402 phy_data |= IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8403 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8404 }
8405
8406 return ret_val;
8407}
e4c780b1 8408#endif /* 0 */
d37ea5d5
AK		 8409
8410/***************************************************************************
8411 *
8412 * Enable dynamic power down mode in ife PHY.
8413 * It can be used to workaround band-gap problem.
8414 *
8415 * hw: Struct containing variables accessed by shared code
8416 *
8417 ***************************************************************************/
e4c780b1 8418#if 0
d37ea5d5
AK		 8419int32_t
8420e1000_ife_enable_dynamic_power_down(struct e1000_hw *hw)
8421{
8422 uint16_t phy_data;
8423 int32_t ret_val = E1000_SUCCESS;
8424
8425 DEBUGFUNC("e1000_ife_enable_dynamic_power_down");
8426
8427 if (hw->phy_type == e1000_phy_ife) {
8428 ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
8429 if (ret_val)
8430 return ret_val;
8431
8432 phy_data &= ~IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN;
8433 ret_val = e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, phy_data);
8434 }
8435
8436 return ret_val;
8437}
e4c780b1 8438#endif /* 0 */
d37ea5d5
AK		 8439
8440/******************************************************************************
8441 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8442 * register.
8443 *
8444 * hw - Struct containing variables accessed by shared code
8445 * offset - offset of word in the EEPROM to read
8446 * data - word read from the EEPROM
8447 * words - number of words to read
8448 *****************************************************************************/
e4c780b1 8449static int32_t
d37ea5d5
AK		 8450e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8451 uint16_t *data)
8452{
8453 int32_t error = E1000_SUCCESS;
8454 uint32_t flash_bank = 0;
8455 uint32_t act_offset = 0;
8456 uint32_t bank_offset = 0;
8457 uint16_t word = 0;
8458 uint16_t i = 0;
8459
8460 /* We need to know which is the valid flash bank. In the event
8461 * that we didn't allocate eeprom_shadow_ram, we may not be
8462 * managing flash_bank. So it cannot be trusted and needs
8463 * to be updated with each read.
8464 */
8465 /* Value of bit 22 corresponds to the flash bank we're on. */
8466 flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8467
8468 /* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8469 bank_offset = flash_bank * (hw->flash_bank_size * 2);
8470
8471 error = e1000_get_software_flag(hw);
8472 if (error != E1000_SUCCESS)
8473 return error;
8474
8475 for (i = 0; i < words; i++) {
8476 if (hw->eeprom_shadow_ram != NULL &&
8477 hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8478 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8479 } else {
8480 /* The NVM part needs a byte offset, hence * 2 */
8481 act_offset = bank_offset + ((offset + i) * 2);
8482 error = e1000_read_ich8_word(hw, act_offset, &word);
8483 if (error != E1000_SUCCESS)
8484 break;
8485 data[i] = word;
8486 }
8487 }
8488
8489 e1000_release_software_flag(hw);
8490
8491 return error;
8492}
8493
8494/******************************************************************************
8495 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8496 * register. Actually, writes are written to the shadow ram cache in the hw
8497 * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8498 * the NVM, which occurs when the NVM checksum is updated.
8499 *
8500 * hw - Struct containing variables accessed by shared code
8501 * offset - offset of word in the EEPROM to write
8502 * words - number of words to write
8503 * data - words to write to the EEPROM
8504 *****************************************************************************/
e4c780b1 8505static int32_t
d37ea5d5
AK		 8506e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8507 uint16_t *data)
8508{
8509 uint32_t i = 0;
8510 int32_t error = E1000_SUCCESS;
8511
8512 error = e1000_get_software_flag(hw);
8513 if (error != E1000_SUCCESS)
8514 return error;
8515
8516 /* A driver can write to the NVM only if it has eeprom_shadow_ram
8517 * allocated. Subsequent reads to the modified words are read from
8518 * this cached structure as well. Writes will only go into this
8519 * cached structure unless it's followed by a call to
8520 * e1000_update_eeprom_checksum() where it will commit the changes
8521 * and clear the "modified" field.
8522 */
8523 if (hw->eeprom_shadow_ram != NULL) {
8524 for (i = 0; i < words; i++) {
8525 if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8526 hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8527 hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8528 } else {
8529 error = -E1000_ERR_EEPROM;
8530 break;
8531 }
8532 }
8533 } else {
8534 /* Drivers have the option to not allocate eeprom_shadow_ram as long
8535 * as they don't perform any NVM writes. An attempt in doing so
8536 * will result in this error.
8537 */
8538 error = -E1000_ERR_EEPROM;
8539 }
8540
8541 e1000_release_software_flag(hw);
8542
8543 return error;
8544}
8545
8546/******************************************************************************
8547 * This function does initial flash setup so that a new read/write/erase cycle
8548 * can be started.
8549 *
8550 * hw - The pointer to the hw structure
8551 ****************************************************************************/
e4c780b1 8552static int32_t
d37ea5d5
AK		 8553e1000_ich8_cycle_init(struct e1000_hw *hw)
8554{
8555 union ich8_hws_flash_status hsfsts;
8556 int32_t error = E1000_ERR_EEPROM;
8557 int32_t i = 0;
8558
8559 DEBUGFUNC("e1000_ich8_cycle_init");
8560
8561 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8562
8563 /* May be check the Flash Des Valid bit in Hw status */
8564 if (hsfsts.hsf_status.fldesvalid == 0) {
8565 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8566 return error;
8567 }
8568
8569 /* Clear FCERR in Hw status by writing 1 */
8570 /* Clear DAEL in Hw status by writing a 1 */
8571 hsfsts.hsf_status.flcerr = 1;
8572 hsfsts.hsf_status.dael = 1;
8573
8574 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8575
8576 /* Either we should have a hardware SPI cycle in progress bit to check
8577 * against, in order to start a new cycle or FDONE bit should be changed
8578 * in the hardware so that it is 1 after harware reset, which can then be
8579 * used as an indication whether a cycle is in progress or has been
8580 * completed .. we should also have some software semaphore mechanism to
8581 * guard FDONE or the cycle in progress bit so that two threads access to
8582 * those bits can be sequentiallized or a way so that 2 threads dont
8583 * start the cycle at the same time */
8584
8585 if (hsfsts.hsf_status.flcinprog == 0) {
8586 /* There is no cycle running at present, so we can start a cycle */
8587 /* Begin by setting Flash Cycle Done. */
8588 hsfsts.hsf_status.flcdone = 1;
8589 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8590 error = E1000_SUCCESS;
8591 } else {
8592 /* otherwise poll for sometime so the current cycle has a chance
8593 * to end before giving up. */
8594 for (i = 0; i < ICH8_FLASH_COMMAND_TIMEOUT; i++) {
8595 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8596 if (hsfsts.hsf_status.flcinprog == 0) {
8597 error = E1000_SUCCESS;
8598 break;
8599 }
8600 udelay(1);
8601 }
8602 if (error == E1000_SUCCESS) {
8603 /* Successful in waiting for previous cycle to timeout,
8604 * now set the Flash Cycle Done. */
8605 hsfsts.hsf_status.flcdone = 1;
8606 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFSTS, hsfsts.regval);
8607 } else {
8608 DEBUGOUT("Flash controller busy, cannot get access");
8609 }
8610 }
8611 return error;
8612}
8613
8614/******************************************************************************
8615 * This function starts a flash cycle and waits for its completion
8616 *
8617 * hw - The pointer to the hw structure
8618 ****************************************************************************/
e4c780b1 8619static int32_t
d37ea5d5
AK		 8620e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8621{
8622 union ich8_hws_flash_ctrl hsflctl;
8623 union ich8_hws_flash_status hsfsts;
8624 int32_t error = E1000_ERR_EEPROM;
8625 uint32_t i = 0;
8626
8627 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8628 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8629 hsflctl.hsf_ctrl.flcgo = 1;
8630 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8631
8632 /* wait till FDONE bit is set to 1 */
8633 do {
8634 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8635 if (hsfsts.hsf_status.flcdone == 1)
8636 break;
8637 udelay(1);
8638 i++;
8639 } while (i < timeout);
8640 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8641 error = E1000_SUCCESS;
8642 }
8643 return error;
8644}
8645
8646/******************************************************************************
8647 * Reads a byte or word from the NVM using the ICH8 flash access registers.
8648 *
8649 * hw - The pointer to the hw structure
8650 * index - The index of the byte or word to read.
8651 * size - Size of data to read, 1=byte 2=word
8652 * data - Pointer to the word to store the value read.
8653 *****************************************************************************/
e4c780b1 8654static int32_t
d37ea5d5
AK		 8655e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8656 uint32_t size, uint16_t* data)
8657{
8658 union ich8_hws_flash_status hsfsts;
8659 union ich8_hws_flash_ctrl hsflctl;
8660 uint32_t flash_linear_address;
8661 uint32_t flash_data = 0;
8662 int32_t error = -E1000_ERR_EEPROM;
8663 int32_t count = 0;
8664
8665 DEBUGFUNC("e1000_read_ich8_data");
8666
8667 if (size < 1 || size > 2 || data == 0x0 ||
8668 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8669 return error;
8670
8671 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8672 hw->flash_base_addr;
8673
8674 do {
8675 udelay(1);
8676 /* Steps */
8677 error = e1000_ich8_cycle_init(hw);
8678 if (error != E1000_SUCCESS)
8679 break;
8680
8681 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8682 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8683 hsflctl.hsf_ctrl.fldbcount = size - 1;
8684 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_READ;
8685 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8686
8687 /* Write the last 24 bits of index into Flash Linear address field in
8688 * Flash Address */
8689 /* TODO: TBD maybe check the index against the size of flash */
8690
8691 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8692
8693 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8694
8695 /* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8696 * sequence a few more times, else read in (shift in) the Flash Data0,
8697 * the order is least significant byte first msb to lsb */
8698 if (error == E1000_SUCCESS) {
8699 flash_data = E1000_READ_ICH8_REG(hw, ICH8_FLASH_FDATA0);
8700 if (size == 1) {
8701 *data = (uint8_t)(flash_data & 0x000000FF);
8702 } else if (size == 2) {
8703 *data = (uint16_t)(flash_data & 0x0000FFFF);
8704 }
8705 break;
8706 } else {
8707 /* If we've gotten here, then things are probably completely hosed,
8708 * but if the error condition is detected, it won't hurt to give
8709 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8710 */
8711 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8712 if (hsfsts.hsf_status.flcerr == 1) {
8713 /* Repeat for some time before giving up. */
8714 continue;
8715 } else if (hsfsts.hsf_status.flcdone == 0) {
8716 DEBUGOUT("Timeout error - flash cycle did not complete.");
8717 break;
8718 }
8719 }
8720 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8721
8722 return error;
8723}
8724
8725/******************************************************************************
8726 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
8727 *
8728 * hw - The pointer to the hw structure
8729 * index - The index of the byte/word to read.
8730 * size - Size of data to read, 1=byte 2=word
8731 * data - The byte(s) to write to the NVM.
8732 *****************************************************************************/
e4c780b1 8733static int32_t
d37ea5d5
AK		 8734e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8735 uint16_t data)
8736{
8737 union ich8_hws_flash_status hsfsts;
8738 union ich8_hws_flash_ctrl hsflctl;
8739 uint32_t flash_linear_address;
8740 uint32_t flash_data = 0;
8741 int32_t error = -E1000_ERR_EEPROM;
8742 int32_t count = 0;
8743
8744 DEBUGFUNC("e1000_write_ich8_data");
8745
8746 if (size < 1 || size > 2 || data > size * 0xff ||
8747 index > ICH8_FLASH_LINEAR_ADDR_MASK)
8748 return error;
8749
8750 flash_linear_address = (ICH8_FLASH_LINEAR_ADDR_MASK & index) +
8751 hw->flash_base_addr;
8752
8753 do {
8754 udelay(1);
8755 /* Steps */
8756 error = e1000_ich8_cycle_init(hw);
8757 if (error != E1000_SUCCESS)
8758 break;
8759
8760 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8761 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8762 hsflctl.hsf_ctrl.fldbcount = size -1;
8763 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_WRITE;
8764 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8765
8766 /* Write the last 24 bits of index into Flash Linear address field in
8767 * Flash Address */
8768 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8769
8770 if (size == 1)
8771 flash_data = (uint32_t)data & 0x00FF;
8772 else
8773 flash_data = (uint32_t)data;
8774
8775 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FDATA0, flash_data);
8776
8777 /* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8778 * sequence a few more times else done */
8779 error = e1000_ich8_flash_cycle(hw, ICH8_FLASH_COMMAND_TIMEOUT);
8780 if (error == E1000_SUCCESS) {
8781 break;
8782 } else {
8783 /* If we're here, then things are most likely completely hosed,
8784 * but if the error condition is detected, it won't hurt to give
8785 * it another try...ICH8_FLASH_CYCLE_REPEAT_COUNT times.
8786 */
8787 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8788 if (hsfsts.hsf_status.flcerr == 1) {
8789 /* Repeat for some time before giving up. */
8790 continue;
8791 } else if (hsfsts.hsf_status.flcdone == 0) {
8792 DEBUGOUT("Timeout error - flash cycle did not complete.");
8793 break;
8794 }
8795 }
8796 } while (count++ < ICH8_FLASH_CYCLE_REPEAT_COUNT);
8797
8798 return error;
8799}
8800
8801/******************************************************************************
8802 * Reads a single byte from the NVM using the ICH8 flash access registers.
8803 *
8804 * hw - pointer to e1000_hw structure
8805 * index - The index of the byte to read.
8806 * data - Pointer to a byte to store the value read.
8807 *****************************************************************************/
e4c780b1 8808static int32_t
d37ea5d5
AK		 8809e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data)
8810{
8811 int32_t status = E1000_SUCCESS;
8812 uint16_t word = 0;
8813
8814 status = e1000_read_ich8_data(hw, index, 1, &word);
8815 if (status == E1000_SUCCESS) {
8816 *data = (uint8_t)word;
8817 }
8818
8819 return status;
8820}
8821
8822/******************************************************************************
8823 * Writes a single byte to the NVM using the ICH8 flash access registers.
8824 * Performs verification by reading back the value and then going through
8825 * a retry algorithm before giving up.
8826 *
8827 * hw - pointer to e1000_hw structure
8828 * index - The index of the byte to write.
8829 * byte - The byte to write to the NVM.
8830 *****************************************************************************/
e4c780b1 8831static int32_t
d37ea5d5
AK		 8832e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8833{
8834 int32_t error = E1000_SUCCESS;
8835 int32_t program_retries;
8836 uint8_t temp_byte;
8837
8838 e1000_write_ich8_byte(hw, index, byte);
8839 udelay(100);
8840
8841 for (program_retries = 0; program_retries < 100; program_retries++) {
8842 e1000_read_ich8_byte(hw, index, &temp_byte);
8843 if (temp_byte == byte)
8844 break;
8845 udelay(10);
8846 e1000_write_ich8_byte(hw, index, byte);
8847 udelay(100);
8848 }
8849 if (program_retries == 100)
8850 error = E1000_ERR_EEPROM;
8851
8852 return error;
8853}
8854
8855/******************************************************************************
8856 * Writes a single byte to the NVM using the ICH8 flash access registers.
8857 *
8858 * hw - pointer to e1000_hw structure
8859 * index - The index of the byte to read.
8860 * data - The byte to write to the NVM.
8861 *****************************************************************************/
e4c780b1 8862static int32_t
d37ea5d5
AK		 8863e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8864{
8865 int32_t status = E1000_SUCCESS;
8866 uint16_t word = (uint16_t)data;
8867
8868 status = e1000_write_ich8_data(hw, index, 1, word);
8869
8870 return status;
8871}
8872
8873/******************************************************************************
8874 * Reads a word from the NVM using the ICH8 flash access registers.
8875 *
8876 * hw - pointer to e1000_hw structure
8877 * index - The starting byte index of the word to read.
8878 * data - Pointer to a word to store the value read.
8879 *****************************************************************************/
e4c780b1 8880static int32_t
d37ea5d5
AK		 8881e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data)
8882{
8883 int32_t status = E1000_SUCCESS;
8884 status = e1000_read_ich8_data(hw, index, 2, data);
8885 return status;
8886}
8887
8888/******************************************************************************
8889 * Writes a word to the NVM using the ICH8 flash access registers.
8890 *
8891 * hw - pointer to e1000_hw structure
8892 * index - The starting byte index of the word to read.
8893 * data - The word to write to the NVM.
8894 *****************************************************************************/
e4c780b1 8895#if 0
d37ea5d5
AK		 8896int32_t
8897e1000_write_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t data)
8898{
8899 int32_t status = E1000_SUCCESS;
8900 status = e1000_write_ich8_data(hw, index, 2, data);
8901 return status;
8902}
e4c780b1 8903#endif /* 0 */
d37ea5d5
AK		 8904
8905/******************************************************************************
8906 * Erases the bank specified. Each bank is a 4k block. Segments are 0 based.
8907 * segment N is 4096 * N + flash_reg_addr.
8908 *
8909 * hw - pointer to e1000_hw structure
8910 * segment - 0 for first segment, 1 for second segment, etc.
8911 *****************************************************************************/
e4c780b1 8912static int32_t
d37ea5d5
AK		 8913e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t segment)
8914{
8915 union ich8_hws_flash_status hsfsts;
8916 union ich8_hws_flash_ctrl hsflctl;
8917 uint32_t flash_linear_address;
8918 int32_t count = 0;
8919 int32_t error = E1000_ERR_EEPROM;
8920 int32_t iteration, seg_size;
8921 int32_t sector_size;
8922 int32_t j = 0;
8923 int32_t error_flag = 0;
8924
8925 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8926
8927 /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
8928 /* 00: The Hw sector is 256 bytes, hence we need to erase 16
8929 * consecutive sectors. The start index for the nth Hw sector can be
8930 * calculated as = segment * 4096 + n * 256
8931 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
8932 * The start index for the nth Hw sector can be calculated
8933 * as = segment * 4096
8934 * 10: Error condition
8935 * 11: The Hw sector size is much bigger than the size asked to
8936 * erase...error condition */
8937 if (hsfsts.hsf_status.berasesz == 0x0) {
8938 /* Hw sector size 256 */
8939 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_256;
8940 iteration = ICH8_FLASH_SECTOR_SIZE / ICH8_FLASH_SEG_SIZE_256;
8941 } else if (hsfsts.hsf_status.berasesz == 0x1) {
8942 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_4K;
8943 iteration = 1;
8944 } else if (hsfsts.hsf_status.berasesz == 0x3) {
8945 sector_size = seg_size = ICH8_FLASH_SEG_SIZE_64K;
8946 iteration = 1;
8947 } else {
8948 return error;
8949 }
8950
8951 for (j = 0; j < iteration ; j++) {
8952 do {
8953 count++;
8954 /* Steps */
8955 error = e1000_ich8_cycle_init(hw);
8956 if (error != E1000_SUCCESS) {
8957 error_flag = 1;
8958 break;
8959 }
8960
8961 /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
8962 * Control */
8963 hsflctl.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFCTL);
8964 hsflctl.hsf_ctrl.flcycle = ICH8_CYCLE_ERASE;
8965 E1000_WRITE_ICH8_REG16(hw, ICH8_FLASH_HSFCTL, hsflctl.regval);
8966
8967 /* Write the last 24 bits of an index within the block into Flash
8968 * Linear address field in Flash Address. This probably needs to
8969 * be calculated here based off the on-chip segment size and the
8970 * software segment size assumed (4K) */
8971 /* TBD */
8972 flash_linear_address = segment * sector_size + j * seg_size;
8973 flash_linear_address &= ICH8_FLASH_LINEAR_ADDR_MASK;
8974 flash_linear_address += hw->flash_base_addr;
8975
8976 E1000_WRITE_ICH8_REG(hw, ICH8_FLASH_FADDR, flash_linear_address);
8977
8978 error = e1000_ich8_flash_cycle(hw, 1000000);
8979 /* Check if FCERR is set to 1. If 1, clear it and try the whole
8980 * sequence a few more times else Done */
8981 if (error == E1000_SUCCESS) {
8982 break;
8983 } else {
8984 hsfsts.regval = E1000_READ_ICH8_REG16(hw, ICH8_FLASH_HSFSTS);
8985 if (hsfsts.hsf_status.flcerr == 1) {
8986 /* repeat for some time before giving up */
8987 continue;
8988 } else if (hsfsts.hsf_status.flcdone == 0) {
8989 error_flag = 1;
8990 break;
8991 }
8992 }
8993 } while ((count < ICH8_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
8994 if (error_flag == 1)
8995 break;
8996 }
8997 if (error_flag != 1)
8998 error = E1000_SUCCESS;
8999 return error;
9000}
9001
9002/******************************************************************************
9003 *
9004 * Reverse duplex setting without breaking the link.
9005 *
9006 * hw: Struct containing variables accessed by shared code
9007 *
9008 *****************************************************************************/
e4c780b1 9009#if 0
d37ea5d5
AK		 9010int32_t
9011e1000_duplex_reversal(struct e1000_hw *hw)
9012{
9013 int32_t ret_val;
9014 uint16_t phy_data;
9015
9016 if (hw->phy_type != e1000_phy_igp_3)
9017 return E1000_SUCCESS;
9018
9019 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
9020 if (ret_val)
9021 return ret_val;
9022
9023 phy_data ^= MII_CR_FULL_DUPLEX;
9024
9025 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
9026 if (ret_val)
9027 return ret_val;
9028
9029 ret_val = e1000_read_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, &phy_data);
9030 if (ret_val)
9031 return ret_val;
9032
9033 phy_data |= IGP3_PHY_MISC_DUPLEX_MANUAL_SET;
9034 ret_val = e1000_write_phy_reg(hw, IGP3E1000_PHY_MISC_CTRL, phy_data);
9035
9036 return ret_val;
9037}
e4c780b1 9038#endif /* 0 */
d37ea5d5 9039
e4c780b1 9040static int32_t
d37ea5d5
AK		 9041e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9042 uint32_t cnf_base_addr, uint32_t cnf_size)
9043{
9044 uint32_t ret_val = E1000_SUCCESS;
9045 uint16_t word_addr, reg_data, reg_addr;
9046 uint16_t i;
9047
9048 /* cnf_base_addr is in DWORD */
9049 word_addr = (uint16_t)(cnf_base_addr << 1);
9050
9051 /* cnf_size is returned in size of dwords */
9052 for (i = 0; i < cnf_size; i++) {
9053 ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9054 if (ret_val)
9055 return ret_val;
9056
9057 ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9058 if (ret_val)
9059 return ret_val;
9060
9061 ret_val = e1000_get_software_flag(hw);
9062 if (ret_val != E1000_SUCCESS)
9063 return ret_val;
9064
9065 ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9066
9067 e1000_release_software_flag(hw);
9068 }
9069
9070 return ret_val;
9071}
9072
9073
e4c780b1 9074static int32_t
d37ea5d5
AK		 9075e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9076{
9077 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9078
9079 if (hw->phy_type != e1000_phy_igp_3)
9080 return E1000_SUCCESS;
9081
9082 /* Check if SW needs configure the PHY */
9083 reg_data = E1000_READ_REG(hw, FEXTNVM);
9084 if (!(reg_data & FEXTNVM_SW_CONFIG))
9085 return E1000_SUCCESS;
9086
9087 /* Wait for basic configuration completes before proceeding*/
9088 loop = 0;
9089 do {
9090 reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9091 udelay(100);
9092 loop++;
9093 } while ((!reg_data) && (loop < 50));
9094
9095 /* Clear the Init Done bit for the next init event */
9096 reg_data = E1000_READ_REG(hw, STATUS);
9097 reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9098 E1000_WRITE_REG(hw, STATUS, reg_data);
9099
9100 /* Make sure HW does not configure LCD from PHY extended configuration
9101 before SW configuration */
9102 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9103 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9104 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9105 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9106 cnf_size >>= 16;
9107 if (cnf_size) {
9108 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9109 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9110 /* cnf_base_addr is in DWORD */
9111 cnf_base_addr >>= 16;
9112
9113 /* Configure LCD from extended configuration region. */
9114 ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9115 cnf_size);
9116 if (ret_val)
9117 return ret_val;
9118 }
9119 }
9120
9121 return E1000_SUCCESS;
9122}
9123
9124
2d7edb92 9125
Linux kernel - Deliverables
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