projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'master'
[deliverable/linux.git] / drivers / net / e1000 / e1000_hw.h
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include "e1000_osdep.h"
37
38
39/* Forward declarations of structures used by the shared code */
40struct e1000_hw;
41struct e1000_hw_stats;
42
43/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controlers */
45typedef enum {
46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_82546_rev_3,
56 e1000_82541,
57 e1000_82541_rev_2,
58 e1000_82547,
59 e1000_82547_rev_2,
868d5309
MC		 60 e1000_82571,
61 e1000_82572,
2d7edb92 62 e1000_82573,
1da177e4
LT		 63 e1000_num_macs
64} e1000_mac_type;
65
66typedef enum {
67 e1000_eeprom_uninitialized = 0,
68 e1000_eeprom_spi,
69 e1000_eeprom_microwire,
2d7edb92 70 e1000_eeprom_flash,
3893d547 71 e1000_eeprom_none, /* No NVM support */
1da177e4
LT		 72 e1000_num_eeprom_types
73} e1000_eeprom_type;
74
75/* Media Types */
76typedef enum {
77 e1000_media_type_copper = 0,
78 e1000_media_type_fiber = 1,
79 e1000_media_type_internal_serdes = 2,
80 e1000_num_media_types
81} e1000_media_type;
82
83typedef enum {
84 e1000_10_half = 0,
85 e1000_10_full = 1,
86 e1000_100_half = 2,
87 e1000_100_full = 3
88} e1000_speed_duplex_type;
89
90/* Flow Control Settings */
91typedef enum {
92 e1000_fc_none = 0,
93 e1000_fc_rx_pause = 1,
94 e1000_fc_tx_pause = 2,
95 e1000_fc_full = 3,
96 e1000_fc_default = 0xFF
97} e1000_fc_type;
98
99/* PCI bus types */
100typedef enum {
101 e1000_bus_type_unknown = 0,
102 e1000_bus_type_pci,
103 e1000_bus_type_pcix,
2d7edb92 104 e1000_bus_type_pci_express,
1da177e4
LT		 105 e1000_bus_type_reserved
106} e1000_bus_type;
107
108/* PCI bus speeds */
109typedef enum {
110 e1000_bus_speed_unknown = 0,
111 e1000_bus_speed_33,
112 e1000_bus_speed_66,
113 e1000_bus_speed_100,
114 e1000_bus_speed_120,
115 e1000_bus_speed_133,
2d7edb92 116 e1000_bus_speed_2500,
1da177e4
LT		 117 e1000_bus_speed_reserved
118} e1000_bus_speed;
119
120/* PCI bus widths */
121typedef enum {
122 e1000_bus_width_unknown = 0,
123 e1000_bus_width_32,
124 e1000_bus_width_64,
2d7edb92
MC		 125 e1000_bus_width_pciex_1,
126 e1000_bus_width_pciex_4,
1da177e4
LT		 127 e1000_bus_width_reserved
128} e1000_bus_width;
129
130/* PHY status info structure and supporting enums */
131typedef enum {
132 e1000_cable_length_50 = 0,
133 e1000_cable_length_50_80,
134 e1000_cable_length_80_110,
135 e1000_cable_length_110_140,
136 e1000_cable_length_140,
137 e1000_cable_length_undefined = 0xFF
138} e1000_cable_length;
139
140typedef enum {
141 e1000_igp_cable_length_10 = 10,
142 e1000_igp_cable_length_20 = 20,
143 e1000_igp_cable_length_30 = 30,
144 e1000_igp_cable_length_40 = 40,
145 e1000_igp_cable_length_50 = 50,
146 e1000_igp_cable_length_60 = 60,
147 e1000_igp_cable_length_70 = 70,
148 e1000_igp_cable_length_80 = 80,
149 e1000_igp_cable_length_90 = 90,
150 e1000_igp_cable_length_100 = 100,
151 e1000_igp_cable_length_110 = 110,
152 e1000_igp_cable_length_120 = 120,
153 e1000_igp_cable_length_130 = 130,
154 e1000_igp_cable_length_140 = 140,
155 e1000_igp_cable_length_150 = 150,
156 e1000_igp_cable_length_160 = 160,
157 e1000_igp_cable_length_170 = 170,
158 e1000_igp_cable_length_180 = 180
159} e1000_igp_cable_length;
160
161typedef enum {
162 e1000_10bt_ext_dist_enable_normal = 0,
163 e1000_10bt_ext_dist_enable_lower,
164 e1000_10bt_ext_dist_enable_undefined = 0xFF
165} e1000_10bt_ext_dist_enable;
166
167typedef enum {
168 e1000_rev_polarity_normal = 0,
169 e1000_rev_polarity_reversed,
170 e1000_rev_polarity_undefined = 0xFF
171} e1000_rev_polarity;
172
173typedef enum {
174 e1000_downshift_normal = 0,
175 e1000_downshift_activated,
176 e1000_downshift_undefined = 0xFF
177} e1000_downshift;
178
179typedef enum {
180 e1000_smart_speed_default = 0,
181 e1000_smart_speed_on,
182 e1000_smart_speed_off
183} e1000_smart_speed;
184
185typedef enum {
186 e1000_polarity_reversal_enabled = 0,
187 e1000_polarity_reversal_disabled,
188 e1000_polarity_reversal_undefined = 0xFF
189} e1000_polarity_reversal;
190
191typedef enum {
192 e1000_auto_x_mode_manual_mdi = 0,
193 e1000_auto_x_mode_manual_mdix,
194 e1000_auto_x_mode_auto1,
195 e1000_auto_x_mode_auto2,
196 e1000_auto_x_mode_undefined = 0xFF
197} e1000_auto_x_mode;
198
199typedef enum {
200 e1000_1000t_rx_status_not_ok = 0,
201 e1000_1000t_rx_status_ok,
202 e1000_1000t_rx_status_undefined = 0xFF
203} e1000_1000t_rx_status;
204
205typedef enum {
206 e1000_phy_m88 = 0,
207 e1000_phy_igp,
2d7edb92 208 e1000_phy_igp_2,
1da177e4
LT		 209 e1000_phy_undefined = 0xFF
210} e1000_phy_type;
211
212typedef enum {
213 e1000_ms_hw_default = 0,
214 e1000_ms_force_master,
215 e1000_ms_force_slave,
216 e1000_ms_auto
217} e1000_ms_type;
218
219typedef enum {
220 e1000_ffe_config_enabled = 0,
221 e1000_ffe_config_active,
222 e1000_ffe_config_blocked
223} e1000_ffe_config;
224
225typedef enum {
226 e1000_dsp_config_disabled = 0,
227 e1000_dsp_config_enabled,
228 e1000_dsp_config_activated,
229 e1000_dsp_config_undefined = 0xFF
230} e1000_dsp_config;
231
232struct e1000_phy_info {
233 e1000_cable_length cable_length;
234 e1000_10bt_ext_dist_enable extended_10bt_distance;
235 e1000_rev_polarity cable_polarity;
236 e1000_downshift downshift;
237 e1000_polarity_reversal polarity_correction;
238 e1000_auto_x_mode mdix_mode;
239 e1000_1000t_rx_status local_rx;
240 e1000_1000t_rx_status remote_rx;
241};
242
243struct e1000_phy_stats {
244 uint32_t idle_errors;
245 uint32_t receive_errors;
246};
247
248struct e1000_eeprom_info {
249 e1000_eeprom_type type;
250 uint16_t word_size;
251 uint16_t opcode_bits;
252 uint16_t address_bits;
253 uint16_t delay_usec;
254 uint16_t page_size;
2d7edb92
MC		 255 boolean_t use_eerd;
256 boolean_t use_eewr;
1da177e4
LT		 257};
258
2d7edb92
MC		 259/* Flex ASF Information */
260#define E1000_HOST_IF_MAX_SIZE 2048
261
262typedef enum {
263 e1000_byte_align = 0,
264 e1000_word_align = 1,
265 e1000_dword_align = 2
266} e1000_align_type;
267
1da177e4
LT		 268
269
270/* Error Codes */
271#define E1000_SUCCESS 0
272#define E1000_ERR_EEPROM 1
273#define E1000_ERR_PHY 2
274#define E1000_ERR_CONFIG 3
275#define E1000_ERR_PARAM 4
276#define E1000_ERR_MAC_TYPE 5
277#define E1000_ERR_PHY_TYPE 6
2d7edb92
MC		 278#define E1000_ERR_RESET 9
279#define E1000_ERR_MASTER_REQUESTS_PENDING 10
280#define E1000_ERR_HOST_INTERFACE_COMMAND 11
281#define E1000_BLK_PHY_RESET 12
1da177e4
LT		 282
283/* Function prototypes */
284/* Initialization */
285int32_t e1000_reset_hw(struct e1000_hw *hw);
286int32_t e1000_init_hw(struct e1000_hw *hw);
2d7edb92 287int32_t e1000_id_led_init(struct e1000_hw * hw);
1da177e4
LT		 288int32_t e1000_set_mac_type(struct e1000_hw *hw);
289void e1000_set_media_type(struct e1000_hw *hw);
290
291/* Link Configuration */
292int32_t e1000_setup_link(struct e1000_hw *hw);
293int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
294void e1000_config_collision_dist(struct e1000_hw *hw);
295int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
296int32_t e1000_check_for_link(struct e1000_hw *hw);
297int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
298int32_t e1000_wait_autoneg(struct e1000_hw *hw);
299int32_t e1000_force_mac_fc(struct e1000_hw *hw);
300
301/* PHY */
302int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
303int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
2d7edb92 304int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
1da177e4
LT		 305int32_t e1000_phy_reset(struct e1000_hw *hw);
306int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
307int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
308int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
309int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
310int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
311int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
312int32_t e1000_check_downshift(struct e1000_hw *hw);
313int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
314
315/* EEPROM Functions */
2d7edb92
MC		 316int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
317boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
318int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
319int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
320int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
321
322/* MNG HOST IF functions */
323uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
324
325#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
326#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
327
328#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
329#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
330#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
331#define E1000_MNG_IAMT_MODE 0x3
332#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
333
334#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
335#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
336#define E1000_VFTA_ENTRY_SHIFT 0x5
337#define E1000_VFTA_ENTRY_MASK 0x7F
338#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
339
340struct e1000_host_mng_command_header {
341 uint8_t command_id;
342 uint8_t checksum;
343 uint16_t reserved1;
344 uint16_t reserved2;
345 uint16_t command_length;
346};
347
348struct e1000_host_mng_command_info {
349 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
350 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
351};
352#ifdef __BIG_ENDIAN
353struct e1000_host_mng_dhcp_cookie{
354 uint32_t signature;
355 uint16_t vlan_id;
356 uint8_t reserved0;
357 uint8_t status;
358 uint32_t reserved1;
359 uint8_t checksum;
360 uint8_t reserved3;
361 uint16_t reserved2;
362};
363#else
364struct e1000_host_mng_dhcp_cookie{
365 uint32_t signature;
366 uint8_t status;
367 uint8_t reserved0;
368 uint16_t vlan_id;
369 uint32_t reserved1;
370 uint16_t reserved2;
371 uint8_t reserved3;
372 uint8_t checksum;
373};
374#endif
375
376int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
377 uint16_t length);
378boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
379boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
380int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
381int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer,
382 uint16_t length, uint16_t offset, uint8_t *sum);
383int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw,
384 struct e1000_host_mng_command_header* hdr);
385
386int32_t e1000_mng_write_commit(struct e1000_hw *hw);
387
1da177e4
LT		 388int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
389int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
390int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
391int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
392int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
393int32_t e1000_read_mac_addr(struct e1000_hw * hw);
2d7edb92
MC		 394int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
395void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
1da177e4
LT		 396
397/* Filters (multicast, vlan, receive) */
398void e1000_init_rx_addrs(struct e1000_hw *hw);
399void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
400uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
401void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
402void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
403void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
404void e1000_clear_vfta(struct e1000_hw *hw);
405
406/* LED functions */
407int32_t e1000_setup_led(struct e1000_hw *hw);
408int32_t e1000_cleanup_led(struct e1000_hw *hw);
409int32_t e1000_led_on(struct e1000_hw *hw);
410int32_t e1000_led_off(struct e1000_hw *hw);
411
412/* Adaptive IFS Functions */
413
414/* Everything else */
1da177e4
LT		 415void e1000_clear_hw_cntrs(struct e1000_hw *hw);
416void e1000_reset_adaptive(struct e1000_hw *hw);
417void e1000_update_adaptive(struct e1000_hw *hw);
418void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
419void e1000_get_bus_info(struct e1000_hw *hw);
420void e1000_pci_set_mwi(struct e1000_hw *hw);
421void e1000_pci_clear_mwi(struct e1000_hw *hw);
422void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
423void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
424/* Port I/O is only supported on 82544 and newer */
425uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
426uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
427void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
428void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
429int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
430int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
2d7edb92
MC		 431int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
432void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
433void e1000_enable_pciex_master(struct e1000_hw *hw);
434int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
435int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
436int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
437int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
438void e1000_release_software_semaphore(struct e1000_hw *hw);
439int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
440int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
441void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
442int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
443uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
1da177e4
LT		 444
445#define E1000_READ_REG_IO(a, reg) \
446 e1000_read_reg_io((a), E1000_##reg)
447#define E1000_WRITE_REG_IO(a, reg, val) \
448 e1000_write_reg_io((a), E1000_##reg, val)
449
450/* PCI Device IDs */
451#define E1000_DEV_ID_82542 0x1000
452#define E1000_DEV_ID_82543GC_FIBER 0x1001
453#define E1000_DEV_ID_82543GC_COPPER 0x1004
454#define E1000_DEV_ID_82544EI_COPPER 0x1008
455#define E1000_DEV_ID_82544EI_FIBER 0x1009
456#define E1000_DEV_ID_82544GC_COPPER 0x100C
457#define E1000_DEV_ID_82544GC_LOM 0x100D
458#define E1000_DEV_ID_82540EM 0x100E
459#define E1000_DEV_ID_82540EM_LOM 0x1015
460#define E1000_DEV_ID_82540EP_LOM 0x1016
461#define E1000_DEV_ID_82540EP 0x1017
462#define E1000_DEV_ID_82540EP_LP 0x101E
463#define E1000_DEV_ID_82545EM_COPPER 0x100F
464#define E1000_DEV_ID_82545EM_FIBER 0x1011
465#define E1000_DEV_ID_82545GM_COPPER 0x1026
466#define E1000_DEV_ID_82545GM_FIBER 0x1027
467#define E1000_DEV_ID_82545GM_SERDES 0x1028
468#define E1000_DEV_ID_82546EB_COPPER 0x1010
469#define E1000_DEV_ID_82546EB_FIBER 0x1012
470#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
471#define E1000_DEV_ID_82541EI 0x1013
472#define E1000_DEV_ID_82541EI_MOBILE 0x1018
473#define E1000_DEV_ID_82541ER 0x1078
474#define E1000_DEV_ID_82547GI 0x1075
475#define E1000_DEV_ID_82541GI 0x1076
476#define E1000_DEV_ID_82541GI_MOBILE 0x1077
477#define E1000_DEV_ID_82541GI_LF 0x107C
478#define E1000_DEV_ID_82546GB_COPPER 0x1079
479#define E1000_DEV_ID_82546GB_FIBER 0x107A
480#define E1000_DEV_ID_82546GB_SERDES 0x107B
481#define E1000_DEV_ID_82546GB_PCIE 0x108A
482#define E1000_DEV_ID_82547EI 0x1019
868d5309
MC		 483#define E1000_DEV_ID_82571EB_COPPER 0x105E
484#define E1000_DEV_ID_82571EB_FIBER 0x105F
485#define E1000_DEV_ID_82571EB_SERDES 0x1060
486#define E1000_DEV_ID_82572EI_COPPER 0x107D
487#define E1000_DEV_ID_82572EI_FIBER 0x107E
488#define E1000_DEV_ID_82572EI_SERDES 0x107F
2d7edb92
MC		 489#define E1000_DEV_ID_82573E 0x108B
490#define E1000_DEV_ID_82573E_IAMT 0x108C
868d5309 491#define E1000_DEV_ID_82573L 0x109A
2d7edb92 492
1da177e4
LT		 493
494#define NODE_ADDRESS_SIZE 6
495#define ETH_LENGTH_OF_ADDRESS 6
496
497/* MAC decode size is 128K - This is the size of BAR0 */
498#define MAC_DECODE_SIZE (128 * 1024)
499
500#define E1000_82542_2_0_REV_ID 2
501#define E1000_82542_2_1_REV_ID 3
502#define E1000_REVISION_0 0
503#define E1000_REVISION_1 1
504#define E1000_REVISION_2 2
2d7edb92 505#define E1000_REVISION_3 3
1da177e4
LT		 506
507#define SPEED_10 10
508#define SPEED_100 100
509#define SPEED_1000 1000
510#define HALF_DUPLEX 1
511#define FULL_DUPLEX 2
512
513/* The sizes (in bytes) of a ethernet packet */
514#define ENET_HEADER_SIZE 14
515#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
516#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
517#define ETHERNET_FCS_SIZE 4
518#define MAXIMUM_ETHERNET_PACKET_SIZE \
519 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
520#define MINIMUM_ETHERNET_PACKET_SIZE \
521 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
522#define CRC_LENGTH ETHERNET_FCS_SIZE
523#define MAX_JUMBO_FRAME_SIZE 0x3F00
524
525
526/* 802.1q VLAN Packet Sizes */
527#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
528
529/* Ethertype field values */
530#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
531#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
532#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
533
534/* Packet Header defines */
535#define IP_PROTOCOL_TCP 6
536#define IP_PROTOCOL_UDP 0x11
537
538/* This defines the bits that are set in the Interrupt Mask
539 * Set/Read Register. Each bit is documented below:
540 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
541 * o RXSEQ = Receive Sequence Error
542 */
543#define POLL_IMS_ENABLE_MASK ( \
544 E1000_IMS_RXDMT0 | \
545 E1000_IMS_RXSEQ)
546
547/* This defines the bits that are set in the Interrupt Mask
548 * Set/Read Register. Each bit is documented below:
549 * o RXT0 = Receiver Timer Interrupt (ring 0)
550 * o TXDW = Transmit Descriptor Written Back
551 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
552 * o RXSEQ = Receive Sequence Error
553 * o LSC = Link Status Change
554 */
555#define IMS_ENABLE_MASK ( \
556 E1000_IMS_RXT0 | \
557 E1000_IMS_TXDW | \
558 E1000_IMS_RXDMT0 | \
559 E1000_IMS_RXSEQ | \
560 E1000_IMS_LSC)
561
2d7edb92 562
1da177e4
LT		 563/* Number of high/low register pairs in the RAR. The RAR (Receive Address
564 * Registers) holds the directed and multicast addresses that we monitor. We
565 * reserve one of these spots for our directed address, allowing us room for
566 * E1000_RAR_ENTRIES - 1 multicast addresses.
567 */
568#define E1000_RAR_ENTRIES 15
569
570#define MIN_NUMBER_OF_DESCRIPTORS 8
571#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
572
573/* Receive Descriptor */
574struct e1000_rx_desc {
575 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
576 uint16_t length; /* Length of data DMAed into data buffer */
577 uint16_t csum; /* Packet checksum */
578 uint8_t status; /* Descriptor status */
579 uint8_t errors; /* Descriptor Errors */
580 uint16_t special;
581};
582
2d7edb92
MC		 583/* Receive Descriptor - Extended */
584union e1000_rx_desc_extended {
585 struct {
586 uint64_t buffer_addr;
587 uint64_t reserved;
588 } read;
589 struct {
590 struct {
591 uint32_t mrq; /* Multiple Rx Queues */
592 union {
593 uint32_t rss; /* RSS Hash */
594 struct {
595 uint16_t ip_id; /* IP id */
596 uint16_t csum; /* Packet Checksum */
597 } csum_ip;
598 } hi_dword;
599 } lower;
600 struct {
601 uint32_t status_error; /* ext status/error */
602 uint16_t length;
603 uint16_t vlan; /* VLAN tag */
604 } upper;
605 } wb; /* writeback */
606};
607
608#define MAX_PS_BUFFERS 4
609/* Receive Descriptor - Packet Split */
610union e1000_rx_desc_packet_split {
611 struct {
612 /* one buffer for protocol header(s), three data buffers */
613 uint64_t buffer_addr[MAX_PS_BUFFERS];
614 } read;
615 struct {
616 struct {
617 uint32_t mrq; /* Multiple Rx Queues */
618 union {
619 uint32_t rss; /* RSS Hash */
620 struct {
621 uint16_t ip_id; /* IP id */
622 uint16_t csum; /* Packet Checksum */
623 } csum_ip;
624 } hi_dword;
625 } lower;
626 struct {
627 uint32_t status_error; /* ext status/error */
628 uint16_t length0; /* length of buffer 0 */
629 uint16_t vlan; /* VLAN tag */
630 } middle;
631 struct {
632 uint16_t header_status;
633 uint16_t length[3]; /* length of buffers 1-3 */
634 } upper;
635 uint64_t reserved;
636 } wb; /* writeback */
637};
638
1da177e4
LT		 639/* Receive Decriptor bit definitions */
640#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
641#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
642#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
643#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
2d7edb92 644#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
1da177e4
LT		 645#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
646#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
647#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
2d7edb92
MC		 648#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
649#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
650#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1da177e4
LT		 651#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
652#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
653#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
654#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
655#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
656#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
657#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
658#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
659#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2d7edb92 660#define E1000_RXD_SPC_PRI_SHIFT 13
1da177e4 661#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
2d7edb92
MC		 662#define E1000_RXD_SPC_CFI_SHIFT 12
663
664#define E1000_RXDEXT_STATERR_CE 0x01000000
665#define E1000_RXDEXT_STATERR_SE 0x02000000
666#define E1000_RXDEXT_STATERR_SEQ 0x04000000
667#define E1000_RXDEXT_STATERR_CXE 0x10000000
668#define E1000_RXDEXT_STATERR_TCPE 0x20000000
669#define E1000_RXDEXT_STATERR_IPE 0x40000000
670#define E1000_RXDEXT_STATERR_RXE 0x80000000
671
672#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
673#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1da177e4
LT		 674
675/* mask to determine if packets should be dropped due to frame errors */
676#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
677 E1000_RXD_ERR_CE | \
678 E1000_RXD_ERR_SE | \
679 E1000_RXD_ERR_SEQ | \
680 E1000_RXD_ERR_CXE | \
681 E1000_RXD_ERR_RXE)
682
2d7edb92
MC		 683
684/* Same mask, but for extended and packet split descriptors */
685#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
686 E1000_RXDEXT_STATERR_CE | \
687 E1000_RXDEXT_STATERR_SE | \
688 E1000_RXDEXT_STATERR_SEQ | \
689 E1000_RXDEXT_STATERR_CXE | \
690 E1000_RXDEXT_STATERR_RXE)
691
1da177e4
LT		 692/* Transmit Descriptor */
693struct e1000_tx_desc {
694 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
695 union {
696 uint32_t data;
697 struct {
698 uint16_t length; /* Data buffer length */
699 uint8_t cso; /* Checksum offset */
700 uint8_t cmd; /* Descriptor control */
701 } flags;
702 } lower;
703 union {
704 uint32_t data;
705 struct {
706 uint8_t status; /* Descriptor status */
707 uint8_t css; /* Checksum start */
708 uint16_t special;
709 } fields;
710 } upper;
711};
712
713/* Transmit Descriptor bit definitions */
714#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
715#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
716#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
717#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
718#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
719#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
720#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
721#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
722#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
723#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
724#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
725#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
726#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
727#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
728#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
729#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
730#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
731#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
732#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
733#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
734
735/* Offload Context Descriptor */
736struct e1000_context_desc {
737 union {
738 uint32_t ip_config;
739 struct {
740 uint8_t ipcss; /* IP checksum start */
741 uint8_t ipcso; /* IP checksum offset */
742 uint16_t ipcse; /* IP checksum end */
743 } ip_fields;
744 } lower_setup;
745 union {
746 uint32_t tcp_config;
747 struct {
748 uint8_t tucss; /* TCP checksum start */
749 uint8_t tucso; /* TCP checksum offset */
750 uint16_t tucse; /* TCP checksum end */
751 } tcp_fields;
752 } upper_setup;
753 uint32_t cmd_and_length; /* */
754 union {
755 uint32_t data;
756 struct {
757 uint8_t status; /* Descriptor status */
758 uint8_t hdr_len; /* Header length */
759 uint16_t mss; /* Maximum segment size */
760 } fields;
761 } tcp_seg_setup;
762};
763
764/* Offload data descriptor */
765struct e1000_data_desc {
766 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
767 union {
768 uint32_t data;
769 struct {
770 uint16_t length; /* Data buffer length */
771 uint8_t typ_len_ext; /* */
772 uint8_t cmd; /* */
773 } flags;
774 } lower;
775 union {
776 uint32_t data;
777 struct {
778 uint8_t status; /* Descriptor status */
779 uint8_t popts; /* Packet Options */
780 uint16_t special; /* */
781 } fields;
782 } upper;
783};
784
785/* Filters */
786#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
787#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
788#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
789
790
791/* Receive Address Register */
792struct e1000_rar {
793 volatile uint32_t low; /* receive address low */
794 volatile uint32_t high; /* receive address high */
795};
796
797/* Number of entries in the Multicast Table Array (MTA). */
798#define E1000_NUM_MTA_REGISTERS 128
799
800/* IPv4 Address Table Entry */
801struct e1000_ipv4_at_entry {
802 volatile uint32_t ipv4_addr; /* IP Address (RW) */
803 volatile uint32_t reserved;
804};
805
806/* Four wakeup IP addresses are supported */
807#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
808#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
809#define E1000_IP6AT_SIZE 1
810
811/* IPv6 Address Table Entry */
812struct e1000_ipv6_at_entry {
813 volatile uint8_t ipv6_addr[16];
814};
815
816/* Flexible Filter Length Table Entry */
817struct e1000_fflt_entry {
818 volatile uint32_t length; /* Flexible Filter Length (RW) */
819 volatile uint32_t reserved;
820};
821
822/* Flexible Filter Mask Table Entry */
823struct e1000_ffmt_entry {
824 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
825 volatile uint32_t reserved;
826};
827
828/* Flexible Filter Value Table Entry */
829struct e1000_ffvt_entry {
830 volatile uint32_t value; /* Flexible Filter Value (RW) */
831 volatile uint32_t reserved;
832};
833
834/* Four Flexible Filters are supported */
835#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
836
837/* Each Flexible Filter is at most 128 (0x80) bytes in length */
838#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
839
840#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
841#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
842#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
843
868d5309
MC		 844#define E1000_DISABLE_SERDES_LOOPBACK 0x0400
845
1da177e4
LT		 846/* Register Set. (82543, 82544)
847 *
848 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
849 * These registers are physically located on the NIC, but are mapped into the
850 * host memory address space.
851 *
852 * RW - register is both readable and writable
853 * RO - register is read only
854 * WO - register is write only
855 * R/clr - register is read only and is cleared when read
856 * A - register array
857 */
858#define E1000_CTRL 0x00000 /* Device Control - RW */
859#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
860#define E1000_STATUS 0x00008 /* Device Status - RO */
861#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
862#define E1000_EERD 0x00014 /* EEPROM Read - RW */
863#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
864#define E1000_FLA 0x0001C /* Flash Access - RW */
865#define E1000_MDIC 0x00020 /* MDI Control - RW */
868d5309 866#define E1000_SCTL 0x00024 /* SerDes Control - RW */
1da177e4
LT		 867#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
868#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
869#define E1000_FCT 0x00030 /* Flow Control Type - RW */
870#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
871#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
872#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
873#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
874#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
875#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
2d7edb92 876#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
1da177e4 877#define E1000_RCTL 0x00100 /* RX Control - RW */
868d5309
MC		 878#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
879#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
880#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
881#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
882#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
883#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
1da177e4
LT		 884#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
885#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
886#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
887#define E1000_TCTL 0x00400 /* TX Control - RW */
888#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
889#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
890#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
891#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
2d7edb92
MC		 892#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
893#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
1da177e4 894#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
2d7edb92
MC		 895#define E1000_PBS 0x01008 /* Packet Buffer Size */
896#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
897#define E1000_FLASH_UPDATES 1000
898#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
899#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
900#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
901#define E1000_FLSWCTL 0x01030 /* FLASH control register */
902#define E1000_FLSWDATA 0x01034 /* FLASH data register */
903#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
904#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
905#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
1da177e4
LT		 906#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
907#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
2d7edb92 908#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
1da177e4
LT		 909#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
910#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
911#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
912#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
913#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
914#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
868d5309
MC		 915#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
916#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
917#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
918#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
919#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
920#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
1da177e4
LT		 921#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
922#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
923#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
2d7edb92 924#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
1da177e4
LT		 925#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
926#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
927#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
928#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
929#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
930#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
931#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
932#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
933#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
934#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
935#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
936#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
937#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
938#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
939#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
2d7edb92
MC		 940#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
941#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
942#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
943#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
944#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
945#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
946#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
947#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
1da177e4
LT		 948#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
949#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
950#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
951#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
952#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
953#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
954#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
955#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
956#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
957#define E1000_COLC 0x04028 /* Collision Count - R/clr */
958#define E1000_DC 0x04030 /* Defer Count - R/clr */
959#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
960#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
961#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
962#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
963#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
964#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
965#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
966#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
967#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
968#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
969#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
970#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
971#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
972#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
973#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
974#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
975#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
976#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
977#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
978#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
979#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
980#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
981#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
982#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
983#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
984#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
985#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
986#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
987#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
988#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
989#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
990#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
991#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
992#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
993#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
994#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
995#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
996#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
997#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
998#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
999#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
1000#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
1001#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
1002#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
1003#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
1004#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
1005#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
868d5309
MC		 1006#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
1007#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
1008#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
1009#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
1010#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
1011#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
1012#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
1013#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
1014#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
1da177e4 1015#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
2d7edb92 1016#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
1da177e4
LT		 1017#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
1018#define E1000_RA 0x05400 /* Receive Address - RW Array */
1019#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
1020#define E1000_WUC 0x05800 /* Wakeup Control - RW */
1021#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
1022#define E1000_WUS 0x05810 /* Wakeup Status - RO */
1023#define E1000_MANC 0x05820 /* Management Control - RW */
1024#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
1025#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
1026#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
1027#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
1028#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
1029#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
1030#define E1000_HOST_IF 0x08800 /* Host Interface */
1031#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
1032#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
1033
2d7edb92
MC		 1034#define E1000_GCR 0x05B00 /* PCI-Ex Control */
1035#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
1036#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
1037#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
1038#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
1039#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1040#define E1000_SWSM 0x05B50 /* SW Semaphore */
1041#define E1000_FWSM 0x05B54 /* FW Semaphore */
1042#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1043#define E1000_HICR 0x08F00 /* Host Inteface Control */
868d5309
MC		 1044
1045/* RSS registers */
1046#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1047#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1048#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1049#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1050#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1051#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1da177e4
LT		 1052/* Register Set (82542)
1053 *
1054 * Some of the 82542 registers are located at different offsets than they are
1055 * in more current versions of the 8254x. Despite the difference in location,
1056 * the registers function in the same manner.
1057 */
1058#define E1000_82542_CTRL E1000_CTRL
1059#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1060#define E1000_82542_STATUS E1000_STATUS
1061#define E1000_82542_EECD E1000_EECD
1062#define E1000_82542_EERD E1000_EERD
1063#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1064#define E1000_82542_FLA E1000_FLA
1065#define E1000_82542_MDIC E1000_MDIC
868d5309 1066#define E1000_82542_SCTL E1000_SCTL
1da177e4
LT		 1067#define E1000_82542_FCAL E1000_FCAL
1068#define E1000_82542_FCAH E1000_FCAH
1069#define E1000_82542_FCT E1000_FCT
1070#define E1000_82542_VET E1000_VET
1071#define E1000_82542_RA 0x00040
1072#define E1000_82542_ICR E1000_ICR
1073#define E1000_82542_ITR E1000_ITR
1074#define E1000_82542_ICS E1000_ICS
1075#define E1000_82542_IMS E1000_IMS
1076#define E1000_82542_IMC E1000_IMC
1077#define E1000_82542_RCTL E1000_RCTL
1078#define E1000_82542_RDTR 0x00108
1079#define E1000_82542_RDBAL 0x00110
1080#define E1000_82542_RDBAH 0x00114
1081#define E1000_82542_RDLEN 0x00118
1082#define E1000_82542_RDH 0x00120
1083#define E1000_82542_RDT 0x00128
868d5309
MC		 1084#define E1000_82542_RDTR0 E1000_82542_RDTR
1085#define E1000_82542_RDBAL0 E1000_82542_RDBAL
1086#define E1000_82542_RDBAH0 E1000_82542_RDBAH
1087#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1088#define E1000_82542_RDH0 E1000_82542_RDH
1089#define E1000_82542_RDT0 E1000_82542_RDT
1090#define E1000_82542_RDTR1 0x00130
1091#define E1000_82542_RDBAL1 0x00138
1092#define E1000_82542_RDBAH1 0x0013C
1093#define E1000_82542_RDLEN1 0x00140
1094#define E1000_82542_RDH1 0x00148
1095#define E1000_82542_RDT1 0x00150
1da177e4
LT		 1096#define E1000_82542_FCRTH 0x00160
1097#define E1000_82542_FCRTL 0x00168
1098#define E1000_82542_FCTTV E1000_FCTTV
1099#define E1000_82542_TXCW E1000_TXCW
1100#define E1000_82542_RXCW E1000_RXCW
1101#define E1000_82542_MTA 0x00200
1102#define E1000_82542_TCTL E1000_TCTL
1103#define E1000_82542_TIPG E1000_TIPG
1104#define E1000_82542_TDBAL 0x00420
1105#define E1000_82542_TDBAH 0x00424
1106#define E1000_82542_TDLEN 0x00428
1107#define E1000_82542_TDH 0x00430
1108#define E1000_82542_TDT 0x00438
1109#define E1000_82542_TIDV 0x00440
1110#define E1000_82542_TBT E1000_TBT
1111#define E1000_82542_AIT E1000_AIT
1112#define E1000_82542_VFTA 0x00600
1113#define E1000_82542_LEDCTL E1000_LEDCTL
1114#define E1000_82542_PBA E1000_PBA
2d7edb92
MC		 1115#define E1000_82542_PBS E1000_PBS
1116#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1117#define E1000_82542_EEARBC E1000_EEARBC
1118#define E1000_82542_FLASHT E1000_FLASHT
1119#define E1000_82542_EEWR E1000_EEWR
1120#define E1000_82542_FLSWCTL E1000_FLSWCTL
1121#define E1000_82542_FLSWDATA E1000_FLSWDATA
1122#define E1000_82542_FLSWCNT E1000_FLSWCNT
1123#define E1000_82542_FLOP E1000_FLOP
1124#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1125#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1126#define E1000_82542_ERT E1000_ERT
1da177e4
LT		 1127#define E1000_82542_RXDCTL E1000_RXDCTL
1128#define E1000_82542_RADV E1000_RADV
1129#define E1000_82542_RSRPD E1000_RSRPD
1130#define E1000_82542_TXDMAC E1000_TXDMAC
1131#define E1000_82542_TDFHS E1000_TDFHS
1132#define E1000_82542_TDFTS E1000_TDFTS
1133#define E1000_82542_TDFPC E1000_TDFPC
1134#define E1000_82542_TXDCTL E1000_TXDCTL
1135#define E1000_82542_TADV E1000_TADV
1136#define E1000_82542_TSPMT E1000_TSPMT
1137#define E1000_82542_CRCERRS E1000_CRCERRS
1138#define E1000_82542_ALGNERRC E1000_ALGNERRC
1139#define E1000_82542_SYMERRS E1000_SYMERRS
1140#define E1000_82542_RXERRC E1000_RXERRC
1141#define E1000_82542_MPC E1000_MPC
1142#define E1000_82542_SCC E1000_SCC
1143#define E1000_82542_ECOL E1000_ECOL
1144#define E1000_82542_MCC E1000_MCC
1145#define E1000_82542_LATECOL E1000_LATECOL
1146#define E1000_82542_COLC E1000_COLC
1147#define E1000_82542_DC E1000_DC
1148#define E1000_82542_TNCRS E1000_TNCRS
1149#define E1000_82542_SEC E1000_SEC
1150#define E1000_82542_CEXTERR E1000_CEXTERR
1151#define E1000_82542_RLEC E1000_RLEC
1152#define E1000_82542_XONRXC E1000_XONRXC
1153#define E1000_82542_XONTXC E1000_XONTXC
1154#define E1000_82542_XOFFRXC E1000_XOFFRXC
1155#define E1000_82542_XOFFTXC E1000_XOFFTXC
1156#define E1000_82542_FCRUC E1000_FCRUC
1157#define E1000_82542_PRC64 E1000_PRC64
1158#define E1000_82542_PRC127 E1000_PRC127
1159#define E1000_82542_PRC255 E1000_PRC255
1160#define E1000_82542_PRC511 E1000_PRC511
1161#define E1000_82542_PRC1023 E1000_PRC1023
1162#define E1000_82542_PRC1522 E1000_PRC1522
1163#define E1000_82542_GPRC E1000_GPRC
1164#define E1000_82542_BPRC E1000_BPRC
1165#define E1000_82542_MPRC E1000_MPRC
1166#define E1000_82542_GPTC E1000_GPTC
1167#define E1000_82542_GORCL E1000_GORCL
1168#define E1000_82542_GORCH E1000_GORCH
1169#define E1000_82542_GOTCL E1000_GOTCL
1170#define E1000_82542_GOTCH E1000_GOTCH
1171#define E1000_82542_RNBC E1000_RNBC
1172#define E1000_82542_RUC E1000_RUC
1173#define E1000_82542_RFC E1000_RFC
1174#define E1000_82542_ROC E1000_ROC
1175#define E1000_82542_RJC E1000_RJC
1176#define E1000_82542_MGTPRC E1000_MGTPRC
1177#define E1000_82542_MGTPDC E1000_MGTPDC
1178#define E1000_82542_MGTPTC E1000_MGTPTC
1179#define E1000_82542_TORL E1000_TORL
1180#define E1000_82542_TORH E1000_TORH
1181#define E1000_82542_TOTL E1000_TOTL
1182#define E1000_82542_TOTH E1000_TOTH
1183#define E1000_82542_TPR E1000_TPR
1184#define E1000_82542_TPT E1000_TPT
1185#define E1000_82542_PTC64 E1000_PTC64
1186#define E1000_82542_PTC127 E1000_PTC127
1187#define E1000_82542_PTC255 E1000_PTC255
1188#define E1000_82542_PTC511 E1000_PTC511
1189#define E1000_82542_PTC1023 E1000_PTC1023
1190#define E1000_82542_PTC1522 E1000_PTC1522
1191#define E1000_82542_MPTC E1000_MPTC
1192#define E1000_82542_BPTC E1000_BPTC
1193#define E1000_82542_TSCTC E1000_TSCTC
1194#define E1000_82542_TSCTFC E1000_TSCTFC
1195#define E1000_82542_RXCSUM E1000_RXCSUM
1196#define E1000_82542_WUC E1000_WUC
1197#define E1000_82542_WUFC E1000_WUFC
1198#define E1000_82542_WUS E1000_WUS
1199#define E1000_82542_MANC E1000_MANC
1200#define E1000_82542_IPAV E1000_IPAV
1201#define E1000_82542_IP4AT E1000_IP4AT
1202#define E1000_82542_IP6AT E1000_IP6AT
1203#define E1000_82542_WUPL E1000_WUPL
1204#define E1000_82542_WUPM E1000_WUPM
1205#define E1000_82542_FFLT E1000_FFLT
1206#define E1000_82542_TDFH 0x08010
1207#define E1000_82542_TDFT 0x08018
1208#define E1000_82542_FFMT E1000_FFMT
1209#define E1000_82542_FFVT E1000_FFVT
1210#define E1000_82542_HOST_IF E1000_HOST_IF
2d7edb92
MC		 1211#define E1000_82542_IAM E1000_IAM
1212#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1213#define E1000_82542_PSRCTL E1000_PSRCTL
1214#define E1000_82542_RAID E1000_RAID
1215#define E1000_82542_TARC0 E1000_TARC0
1216#define E1000_82542_TDBAL1 E1000_TDBAL1
1217#define E1000_82542_TDBAH1 E1000_TDBAH1
1218#define E1000_82542_TDLEN1 E1000_TDLEN1
1219#define E1000_82542_TDH1 E1000_TDH1
1220#define E1000_82542_TDT1 E1000_TDT1
1221#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1222#define E1000_82542_TARC1 E1000_TARC1
1223#define E1000_82542_RFCTL E1000_RFCTL
1224#define E1000_82542_GCR E1000_GCR
1225#define E1000_82542_GSCL_1 E1000_GSCL_1
1226#define E1000_82542_GSCL_2 E1000_GSCL_2
1227#define E1000_82542_GSCL_3 E1000_GSCL_3
1228#define E1000_82542_GSCL_4 E1000_GSCL_4
1229#define E1000_82542_FACTPS E1000_FACTPS
1230#define E1000_82542_SWSM E1000_SWSM
1231#define E1000_82542_FWSM E1000_FWSM
1232#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1233#define E1000_82542_IAC E1000_IAC
1234#define E1000_82542_ICRXPTC E1000_ICRXPTC
1235#define E1000_82542_ICRXATC E1000_ICRXATC
1236#define E1000_82542_ICTXPTC E1000_ICTXPTC
1237#define E1000_82542_ICTXATC E1000_ICTXATC
1238#define E1000_82542_ICTXQEC E1000_ICTXQEC
1239#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1240#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1241#define E1000_82542_ICRXOC E1000_ICRXOC
1242#define E1000_82542_HICR E1000_HICR
1da177e4 1243
868d5309
MC		 1244#define E1000_82542_CPUVEC E1000_CPUVEC
1245#define E1000_82542_MRQC E1000_MRQC
1246#define E1000_82542_RETA E1000_RETA
1247#define E1000_82542_RSSRK E1000_RSSRK
1248#define E1000_82542_RSSIM E1000_RSSIM
1249#define E1000_82542_RSSIR E1000_RSSIR
1250
1da177e4
LT		 1251/* Statistics counters collected by the MAC */
1252struct e1000_hw_stats {
1253 uint64_t crcerrs;
1254 uint64_t algnerrc;
1255 uint64_t symerrs;
1256 uint64_t rxerrc;
1257 uint64_t mpc;
1258 uint64_t scc;
1259 uint64_t ecol;
1260 uint64_t mcc;
1261 uint64_t latecol;
1262 uint64_t colc;
1263 uint64_t dc;
1264 uint64_t tncrs;
1265 uint64_t sec;
1266 uint64_t cexterr;
1267 uint64_t rlec;
1268 uint64_t xonrxc;
1269 uint64_t xontxc;
1270 uint64_t xoffrxc;
1271 uint64_t xofftxc;
1272 uint64_t fcruc;
1273 uint64_t prc64;
1274 uint64_t prc127;
1275 uint64_t prc255;
1276 uint64_t prc511;
1277 uint64_t prc1023;
1278 uint64_t prc1522;
1279 uint64_t gprc;
1280 uint64_t bprc;
1281 uint64_t mprc;
1282 uint64_t gptc;
1283 uint64_t gorcl;
1284 uint64_t gorch;
1285 uint64_t gotcl;
1286 uint64_t gotch;
1287 uint64_t rnbc;
1288 uint64_t ruc;
1289 uint64_t rfc;
1290 uint64_t roc;
1291 uint64_t rjc;
1292 uint64_t mgprc;
1293 uint64_t mgpdc;
1294 uint64_t mgptc;
1295 uint64_t torl;
1296 uint64_t torh;
1297 uint64_t totl;
1298 uint64_t toth;
1299 uint64_t tpr;
1300 uint64_t tpt;
1301 uint64_t ptc64;
1302 uint64_t ptc127;
1303 uint64_t ptc255;
1304 uint64_t ptc511;
1305 uint64_t ptc1023;
1306 uint64_t ptc1522;
1307 uint64_t mptc;
1308 uint64_t bptc;
1309 uint64_t tsctc;
1310 uint64_t tsctfc;
2d7edb92
MC		 1311 uint64_t iac;
1312 uint64_t icrxptc;
1313 uint64_t icrxatc;
1314 uint64_t ictxptc;
1315 uint64_t ictxatc;
1316 uint64_t ictxqec;
1317 uint64_t ictxqmtc;
1318 uint64_t icrxdmtc;
1319 uint64_t icrxoc;
1da177e4
LT		 1320};
1321
1322/* Structure containing variables used by the shared code (e1000_hw.c) */
1323struct e1000_hw {
1bea9add 1324 uint8_t __iomem *hw_addr;
2d7edb92 1325 uint8_t *flash_address;
1da177e4
LT		 1326 e1000_mac_type mac_type;
1327 e1000_phy_type phy_type;
1328 uint32_t phy_init_script;
1329 e1000_media_type media_type;
1330 void *back;
1331 e1000_fc_type fc;
1332 e1000_bus_speed bus_speed;
1333 e1000_bus_width bus_width;
1334 e1000_bus_type bus_type;
1335 struct e1000_eeprom_info eeprom;
1336 e1000_ms_type master_slave;
1337 e1000_ms_type original_master_slave;
1338 e1000_ffe_config ffe_config_state;
1339 uint32_t asf_firmware_present;
2d7edb92 1340 uint32_t eeprom_semaphore_present;
1da177e4
LT		 1341 unsigned long io_base;
1342 uint32_t phy_id;
1343 uint32_t phy_revision;
1344 uint32_t phy_addr;
1345 uint32_t original_fc;
1346 uint32_t txcw;
1347 uint32_t autoneg_failed;
1348 uint32_t max_frame_size;
1349 uint32_t min_frame_size;
1350 uint32_t mc_filter_type;
1351 uint32_t num_mc_addrs;
1352 uint32_t collision_delta;
1353 uint32_t tx_packet_delta;
1354 uint32_t ledctl_default;
1355 uint32_t ledctl_mode1;
1356 uint32_t ledctl_mode2;
2d7edb92
MC		 1357 boolean_t tx_pkt_filtering;
1358 struct e1000_host_mng_dhcp_cookie mng_cookie;
1da177e4
LT		 1359 uint16_t phy_spd_default;
1360 uint16_t autoneg_advertised;
1361 uint16_t pci_cmd_word;
1362 uint16_t fc_high_water;
1363 uint16_t fc_low_water;
1364 uint16_t fc_pause_time;
1365 uint16_t current_ifs_val;
1366 uint16_t ifs_min_val;
1367 uint16_t ifs_max_val;
1368 uint16_t ifs_step_size;
1369 uint16_t ifs_ratio;
1370 uint16_t device_id;
1371 uint16_t vendor_id;
1372 uint16_t subsystem_id;
1373 uint16_t subsystem_vendor_id;
1374 uint8_t revision_id;
1375 uint8_t autoneg;
1376 uint8_t mdix;
1377 uint8_t forced_speed_duplex;
1378 uint8_t wait_autoneg_complete;
1379 uint8_t dma_fairness;
1380 uint8_t mac_addr[NODE_ADDRESS_SIZE];
1381 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1382 boolean_t disable_polarity_correction;
1383 boolean_t speed_downgraded;
1384 e1000_smart_speed smart_speed;
1385 e1000_dsp_config dsp_config_state;
1386 boolean_t get_link_status;
1387 boolean_t serdes_link_down;
1388 boolean_t tbi_compatibility_en;
1389 boolean_t tbi_compatibility_on;
868d5309 1390 boolean_t laa_is_present;
1da177e4
LT		 1391 boolean_t phy_reset_disable;
1392 boolean_t fc_send_xon;
1393 boolean_t fc_strict_ieee;
1394 boolean_t report_tx_early;
1395 boolean_t adaptive_ifs;
1396 boolean_t ifs_params_forced;
1397 boolean_t in_ifs_mode;
2d7edb92 1398 boolean_t mng_reg_access_disabled;
1da177e4
LT		 1399};
1400
1401
1402#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1403#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
2d7edb92
MC		 1404#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1405#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1406#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1407#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1408#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1409#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1da177e4
LT		 1410/* Register Bit Masks */
1411/* Device Control */
1412#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1413#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1414#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
2d7edb92 1415#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1da177e4
LT		 1416#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1417#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1418#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1419#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1420#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1421#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1422#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1423#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1424#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1425#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1426#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1427#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1428#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
868d5309 1429#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
2d7edb92 1430#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1da177e4
LT		 1431#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1432#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1433#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1434#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1435#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1436#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1437#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1438#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1439#define E1000_CTRL_RST 0x04000000 /* Global reset */
1440#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1441#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1442#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1443#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1444#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1445
1446/* Device Status */
1447#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1448#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1449#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
2d7edb92 1450#define E1000_STATUS_FUNC_SHIFT 2
1da177e4
LT		 1451#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1452#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1453#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1454#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1455#define E1000_STATUS_SPEED_MASK 0x000000C0
1456#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1457#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1458#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1459#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
2d7edb92
MC		 1460#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1461#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1da177e4
LT		 1462#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1463#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1464#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1465#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1466#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1467
1468/* Constants used to intrepret the masked PCI-X bus speed. */
1469#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1470#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1471#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1472
1473/* EEPROM/Flash Control */
1474#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1475#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1476#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1477#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1478#define E1000_EECD_FWE_MASK 0x00000030
1479#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1480#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1481#define E1000_EECD_FWE_SHIFT 4
1482#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1483#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1484#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1485#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1486#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1487 * (0-small, 1-large) */
1488#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1489#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1490#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1491#endif
2d7edb92
MC		 1492#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1493#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1494#define E1000_EECD_SIZE_EX_SHIFT 11
1495#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1496#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1497#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1498#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1499#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1500#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1501#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
1502#define E1000_STM_OPCODE 0xDB00
1503#define E1000_HICR_FW_RESET 0xC0
1da177e4
LT		 1504
1505/* EEPROM Read */
1506#define E1000_EERD_START 0x00000001 /* Start Read */
1507#define E1000_EERD_DONE 0x00000010 /* Read Done */
1508#define E1000_EERD_ADDR_SHIFT 8
1509#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1510#define E1000_EERD_DATA_SHIFT 16
1511#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1512
1513/* SPI EEPROM Status Register */
1514#define EEPROM_STATUS_RDY_SPI 0x01
1515#define EEPROM_STATUS_WEN_SPI 0x02
1516#define EEPROM_STATUS_BP0_SPI 0x04
1517#define EEPROM_STATUS_BP1_SPI 0x08
1518#define EEPROM_STATUS_WPEN_SPI 0x80
1519
1520/* Extended Device Control */
1521#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1522#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1523#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1524#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1525#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1526#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1527#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1528#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1529#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1530#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1531#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1532#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1533#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1534#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1535#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1536#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1537#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1538#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1539#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1540#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1541#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1542#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1543#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1544#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1545#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1546#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
868d5309
MC		 1547#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
1548#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
2d7edb92
MC		 1549#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1550#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1da177e4
LT		 1551
1552/* MDI Control */
1553#define E1000_MDIC_DATA_MASK 0x0000FFFF
1554#define E1000_MDIC_REG_MASK 0x001F0000
1555#define E1000_MDIC_REG_SHIFT 16
1556#define E1000_MDIC_PHY_MASK 0x03E00000
1557#define E1000_MDIC_PHY_SHIFT 21
1558#define E1000_MDIC_OP_WRITE 0x04000000
1559#define E1000_MDIC_OP_READ 0x08000000
1560#define E1000_MDIC_READY 0x10000000
1561#define E1000_MDIC_INT_EN 0x20000000
1562#define E1000_MDIC_ERROR 0x40000000
1563
1564/* LED Control */
1565#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1566#define E1000_LEDCTL_LED0_MODE_SHIFT 0
2d7edb92 1567#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1da177e4
LT		 1568#define E1000_LEDCTL_LED0_IVRT 0x00000040
1569#define E1000_LEDCTL_LED0_BLINK 0x00000080
1570#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1571#define E1000_LEDCTL_LED1_MODE_SHIFT 8
2d7edb92 1572#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1da177e4
LT		 1573#define E1000_LEDCTL_LED1_IVRT 0x00004000
1574#define E1000_LEDCTL_LED1_BLINK 0x00008000
1575#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1576#define E1000_LEDCTL_LED2_MODE_SHIFT 16
2d7edb92 1577#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1da177e4
LT		 1578#define E1000_LEDCTL_LED2_IVRT 0x00400000
1579#define E1000_LEDCTL_LED2_BLINK 0x00800000
1580#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1581#define E1000_LEDCTL_LED3_MODE_SHIFT 24
868d5309 1582#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
1da177e4
LT		 1583#define E1000_LEDCTL_LED3_IVRT 0x40000000
1584#define E1000_LEDCTL_LED3_BLINK 0x80000000
1585
1586#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1587#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1588#define E1000_LEDCTL_MODE_LINK_UP 0x2
1589#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1590#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1591#define E1000_LEDCTL_MODE_LINK_10 0x5
1592#define E1000_LEDCTL_MODE_LINK_100 0x6
1593#define E1000_LEDCTL_MODE_LINK_1000 0x7
1594#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1595#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1596#define E1000_LEDCTL_MODE_COLLISION 0xA
1597#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1598#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1599#define E1000_LEDCTL_MODE_PAUSED 0xD
1600#define E1000_LEDCTL_MODE_LED_ON 0xE
1601#define E1000_LEDCTL_MODE_LED_OFF 0xF
1602
1603/* Receive Address */
1604#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1605
1606/* Interrupt Cause Read */
1607#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1608#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1609#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1610#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1611#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1612#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1613#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1614#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1615#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1616#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1617#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1618#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1619#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1620#define E1000_ICR_TXD_LOW 0x00008000
1621#define E1000_ICR_SRPD 0x00010000
2d7edb92
MC		 1622#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1623#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1624#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1625#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1da177e4
LT		 1626
1627/* Interrupt Cause Set */
1628#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1629#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1630#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1631#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1632#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1633#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1634#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1635#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1636#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1637#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1638#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1639#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1640#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1641#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1642#define E1000_ICS_SRPD E1000_ICR_SRPD
2d7edb92
MC		 1643#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1644#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1645#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1da177e4
LT		 1646
1647/* Interrupt Mask Set */
1648#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1649#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1650#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1651#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1652#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1653#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1654#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1655#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1656#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1657#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1658#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1659#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1660#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1661#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1662#define E1000_IMS_SRPD E1000_ICR_SRPD
2d7edb92
MC		 1663#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1664#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1665#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1da177e4
LT		 1666
1667/* Interrupt Mask Clear */
1668#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1669#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1670#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1671#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1672#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1673#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1674#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1675#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1676#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1677#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1678#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1679#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1680#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1681#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1682#define E1000_IMC_SRPD E1000_ICR_SRPD
2d7edb92
MC		 1683#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1684#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1685#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1da177e4
LT		 1686
1687/* Receive Control */
1688#define E1000_RCTL_RST 0x00000001 /* Software reset */
1689#define E1000_RCTL_EN 0x00000002 /* enable */
1690#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1691#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1692#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1693#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1694#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1695#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1696#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1697#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
2d7edb92
MC		 1698#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1699#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1da177e4
LT		 1700#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1701#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1702#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1703#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1704#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1705#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1706#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1707#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1708#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1709#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1710/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1711#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1712#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1713#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1714#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1715/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1716#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1717#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1718#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1719#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1720#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1721#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1722#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1723#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1724#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1725#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
2d7edb92
MC		 1726#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1727#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1728
1729/* Use byte values for the following shift parameters
1730 * Usage:
1731 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1732 * E1000_PSRCTL_BSIZE0_MASK) |
1733 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1734 * E1000_PSRCTL_BSIZE1_MASK) |
1735 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1736 * E1000_PSRCTL_BSIZE2_MASK) |
1737 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1738 * E1000_PSRCTL_BSIZE3_MASK))
1739 * where value0 = [128..16256], default=256
1740 * value1 = [1024..64512], default=4096
1741 * value2 = [0..64512], default=4096
1742 * value3 = [0..64512], default=0
1743 */
1744
1745#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1746#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1747#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1748#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1749
1750#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1751#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1752#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1753#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1da177e4
LT		 1754
1755/* Receive Descriptor */
1756#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1757#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1758#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1759#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1760#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1761
1762/* Flow Control */
1763#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1764#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1765#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1766#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1767
2d7edb92
MC		 1768/* Header split receive */
1769#define E1000_RFCTL_ISCSI_DIS 0x00000001
1770#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1771#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1772#define E1000_RFCTL_NFSW_DIS 0x00000040
1773#define E1000_RFCTL_NFSR_DIS 0x00000080
1774#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1775#define E1000_RFCTL_NFS_VER_SHIFT 8
1776#define E1000_RFCTL_IPV6_DIS 0x00000400
1777#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1778#define E1000_RFCTL_ACK_DIS 0x00001000
1779#define E1000_RFCTL_ACKD_DIS 0x00002000
1780#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1781#define E1000_RFCTL_EXTEN 0x00008000
1782#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1783#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1784
1da177e4
LT		 1785/* Receive Descriptor Control */
1786#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1787#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1788#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1789#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1790
1791/* Transmit Descriptor Control */
1792#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1793#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1794#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1795#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1796#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1797#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
2d7edb92
MC		 1798#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1799 still to be processed. */
1da177e4
LT		 1800
1801/* Transmit Configuration Word */
1802#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1803#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1804#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1805#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1806#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1807#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1808#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1809#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1810#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1811#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1812
1813/* Receive Configuration Word */
1814#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1815#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1816#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1817#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1818#define E1000_RXCW_C 0x20000000 /* Receive config */
1819#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1820#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1821
1822/* Transmit Control */
1823#define E1000_TCTL_RST 0x00000001 /* software reset */
1824#define E1000_TCTL_EN 0x00000002 /* enable tx */
1825#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1826#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1827#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1828#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1829#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1830#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1831#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1832#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
2d7edb92 1833#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1da177e4
LT		 1834
1835/* Receive Checksum Control */
1836#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1837#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1838#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1839#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
2d7edb92
MC		 1840#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1841#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1842
868d5309
MC		 1843/* Multiple Receive Queue Control */
1844#define E1000_MRQC_ENABLE_MASK 0x00000003
1845#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
1846#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
1847#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1848#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1849#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1850#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000
1851#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1852#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
1da177e4
LT		 1853
1854/* Definitions for power management and wakeup registers */
1855/* Wake Up Control */
1856#define E1000_WUC_APME 0x00000001 /* APM Enable */
1857#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1858#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1859#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1860#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1861
1862/* Wake Up Filter Control */
1863#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1864#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1865#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1866#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1867#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1868#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1869#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1870#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
2d7edb92 1871#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1da177e4
LT		 1872#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1873#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1874#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1875#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1876#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1877#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1878#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1879
1880/* Wake Up Status */
1881#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1882#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1883#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1884#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1885#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1886#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1887#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1888#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1889#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1890#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1891#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1892#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1893#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1894
1895/* Management Control */
1896#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1897#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1898#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1899#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1900#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1901#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1902#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1903#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1904#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1905#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1906 * Filtering */
2d7edb92 1907#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
1da177e4
LT		 1908#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1909#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1910#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2d7edb92 1911#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1da177e4
LT		 1912#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1913 * filtering */
1914#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1915 * memory */
2d7edb92
MC		 1916#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
1917 * filtering */
1918#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
1919#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
1da177e4
LT		 1920#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1921#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1922#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1923#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1924#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1925#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1926
1927#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1928#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1929
2d7edb92
MC		 1930/* SW Semaphore Register */
1931#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1932#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1933#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1934#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
1935
1936/* FW Semaphore Register */
1937#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
1938#define E1000_FWSM_MODE_SHIFT 1
1939#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
1940
1941/* FFLT Debug Register */
1942#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
1943
1944typedef enum {
1945 e1000_mng_mode_none = 0,
1946 e1000_mng_mode_asf,
1947 e1000_mng_mode_pt,
1948 e1000_mng_mode_ipmi,
1949 e1000_mng_mode_host_interface_only
1950} e1000_mng_mode;
1951
1952/* Host Inteface Control Register */
1953#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
1954#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
1955 * to put command in RAM */
1956#define E1000_HICR_SV 0x00000004 /* Status Validity */
1957#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
1958
1959/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
1960#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
1961#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
1962#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
1963#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
1964
1965struct e1000_host_command_header {
1966 uint8_t command_id;
1967 uint8_t command_length;
1968 uint8_t command_options; /* I/F bits for command, status for return */
1969 uint8_t checksum;
1970};
1971struct e1000_host_command_info {
1972 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
1973 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
1974};
1975
1976/* Host SMB register #0 */
1977#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
1978#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
1979#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
1980#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
1981
1982/* Host SMB register #1 */
1983#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
1984#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
1985#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
1986#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
1987
1988/* FW Status Register */
1989#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
1990
1da177e4
LT		 1991/* Wake Up Packet Length */
1992#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1993
1994#define E1000_MDALIGN 4096
1995
2d7edb92 1996#define E1000_GCR_BEM32 0x00400000
868d5309 1997#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2d7edb92
MC		 1998/* Function Active and Power State to MNG */
1999#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2000#define E1000_FACTPS_LAN0_VALID 0x00000004
2001#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2002#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2003#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2004#define E1000_FACTPS_LAN1_VALID 0x00000100
2005#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2006#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2007#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2008#define E1000_FACTPS_IDE_ENABLE 0x00004000
2009#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2010#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2011#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2012#define E1000_FACTPS_SP_ENABLE 0x00100000
2013#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2014#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2015#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2016#define E1000_FACTPS_IPMI_ENABLE 0x04000000
2017#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2018#define E1000_FACTPS_MNGCG 0x20000000
2019#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2020#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2021
1da177e4
LT		 2022/* EEPROM Commands - Microwire */
2023#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2024#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2025#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2026#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2027#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
2028
2029/* EEPROM Commands - SPI */
2030#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2d7edb92
MC		 2031#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2032#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2033#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2034#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2035#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2036#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2037#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2038#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2039#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2040#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1da177e4
LT		 2041
2042/* EEPROM Size definitions */
2d7edb92
MC		 2043#define EEPROM_WORD_SIZE_SHIFT 6
2044#define EEPROM_SIZE_SHIFT 10
1da177e4
LT		 2045#define EEPROM_SIZE_MASK 0x1C00
2046
2047/* EEPROM Word Offsets */
2048#define EEPROM_COMPAT 0x0003
2049#define EEPROM_ID_LED_SETTINGS 0x0004
868d5309 2050#define EEPROM_VERSION 0x0005
1da177e4
LT		 2051#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2052#define EEPROM_PHY_CLASS_WORD 0x0007
2053#define EEPROM_INIT_CONTROL1_REG 0x000A
2054#define EEPROM_INIT_CONTROL2_REG 0x000F
2055#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2056#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2057#define EEPROM_CFG 0x0012
2058#define EEPROM_FLASH_VERSION 0x0032
2059#define EEPROM_CHECKSUM_REG 0x003F
2060
868d5309
MC		 2061#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2062
1da177e4
LT		 2063/* Word definitions for ID LED Settings */
2064#define ID_LED_RESERVED_0000 0x0000
2065#define ID_LED_RESERVED_FFFF 0xFFFF
2066#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2067 (ID_LED_OFF1_OFF2 << 8) | \
2068 (ID_LED_DEF1_DEF2 << 4) | \
2069 (ID_LED_DEF1_DEF2))
2070#define ID_LED_DEF1_DEF2 0x1
2071#define ID_LED_DEF1_ON2 0x2
2072#define ID_LED_DEF1_OFF2 0x3
2073#define ID_LED_ON1_DEF2 0x4
2074#define ID_LED_ON1_ON2 0x5
2075#define ID_LED_ON1_OFF2 0x6
2076#define ID_LED_OFF1_DEF2 0x7
2077#define ID_LED_OFF1_ON2 0x8
2078#define ID_LED_OFF1_OFF2 0x9
2079
2080#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2081#define IGP_ACTIVITY_LED_ENABLE 0x0300
2082#define IGP_LED3_MODE 0x07000000
2083
2084
2085/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2086#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2087
2088/* Mask bit for PHY class in Word 7 of the EEPROM */
2089#define EEPROM_PHY_CLASS_A 0x8000
2090
2091/* Mask bits for fields in Word 0x0a of the EEPROM */
2092#define EEPROM_WORD0A_ILOS 0x0010
2093#define EEPROM_WORD0A_SWDPIO 0x01E0
2094#define EEPROM_WORD0A_LRST 0x0200
2095#define EEPROM_WORD0A_FD 0x0400
2096#define EEPROM_WORD0A_66MHZ 0x0800
2097
2098/* Mask bits for fields in Word 0x0f of the EEPROM */
2099#define EEPROM_WORD0F_PAUSE_MASK 0x3000
2100#define EEPROM_WORD0F_PAUSE 0x1000
2101#define EEPROM_WORD0F_ASM_DIR 0x2000
2102#define EEPROM_WORD0F_ANE 0x0800
2103#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2104
2105/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2106#define EEPROM_SUM 0xBABA
2107
2108/* EEPROM Map defines (WORD OFFSETS)*/
2109#define EEPROM_NODE_ADDRESS_BYTE_0 0
2110#define EEPROM_PBA_BYTE_1 8
2111
2112#define EEPROM_RESERVED_WORD 0xFFFF
2113
2114/* EEPROM Map Sizes (Byte Counts) */
2115#define PBA_SIZE 4
2116
2117/* Collision related configuration parameters */
2118#define E1000_COLLISION_THRESHOLD 15
2119#define E1000_CT_SHIFT 4
2120#define E1000_COLLISION_DISTANCE 64
2121#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2122#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2123#define E1000_COLD_SHIFT 12
2124
2125/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2126#define REQ_TX_DESCRIPTOR_MULTIPLE 8
2127#define REQ_RX_DESCRIPTOR_MULTIPLE 8
2128
2129/* Default values for the transmit IPG register */
2130#define DEFAULT_82542_TIPG_IPGT 10
2131#define DEFAULT_82543_TIPG_IPGT_FIBER 9
2132#define DEFAULT_82543_TIPG_IPGT_COPPER 8
2133
2134#define E1000_TIPG_IPGT_MASK 0x000003FF
2135#define E1000_TIPG_IPGR1_MASK 0x000FFC00
2136#define E1000_TIPG_IPGR2_MASK 0x3FF00000
2137
2138#define DEFAULT_82542_TIPG_IPGR1 2
2139#define DEFAULT_82543_TIPG_IPGR1 8
2140#define E1000_TIPG_IPGR1_SHIFT 10
2141
2142#define DEFAULT_82542_TIPG_IPGR2 10
2143#define DEFAULT_82543_TIPG_IPGR2 6
2144#define E1000_TIPG_IPGR2_SHIFT 20
2145
2146#define E1000_TXDMAC_DPP 0x00000001
2147
2148/* Adaptive IFS defines */
2149#define TX_THRESHOLD_START 8
2150#define TX_THRESHOLD_INCREMENT 10
2151#define TX_THRESHOLD_DECREMENT 1
2152#define TX_THRESHOLD_STOP 190
2153#define TX_THRESHOLD_DISABLE 0
2154#define TX_THRESHOLD_TIMER_MS 10000
2155#define MIN_NUM_XMITS 1000
2156#define IFS_MAX 80
2157#define IFS_STEP 10
2158#define IFS_MIN 40
2159#define IFS_RATIO 4
2160
2d7edb92
MC		 2161/* Extended Configuration Control and Size */
2162#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2163#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2164#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2165#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2166#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2167#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2168#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2169#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000
2170
2171#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2172#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2173#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2174
1da177e4 2175/* PBA constants */
2d7edb92 2176#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
1da177e4
LT		 2177#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2178#define E1000_PBA_22K 0x0016
2179#define E1000_PBA_24K 0x0018
2180#define E1000_PBA_30K 0x001E
868d5309
MC		 2181#define E1000_PBA_32K 0x0020
2182#define E1000_PBA_38K 0x0026
1da177e4
LT		 2183#define E1000_PBA_40K 0x0028
2184#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2185
2186/* Flow Control Constants */
2187#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2188#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2189#define FLOW_CONTROL_TYPE 0x8808
2190
2191/* The historical defaults for the flow control values are given below. */
2192#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2193#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2194#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2195
2196/* PCIX Config space */
2197#define PCIX_COMMAND_REGISTER 0xE6
2198#define PCIX_STATUS_REGISTER_LO 0xE8
2199#define PCIX_STATUS_REGISTER_HI 0xEA
2200
2201#define PCIX_COMMAND_MMRBC_MASK 0x000C
2202#define PCIX_COMMAND_MMRBC_SHIFT 0x2
2203#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2204#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2205#define PCIX_STATUS_HI_MMRBC_4K 0x3
2206#define PCIX_STATUS_HI_MMRBC_2K 0x2
2207
2208
2209/* Number of bits required to shift right the "pause" bits from the
2210 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2211 */
2212#define PAUSE_SHIFT 5
2213
2214/* Number of bits required to shift left the "SWDPIO" bits from the
2215 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2216 */
2217#define SWDPIO_SHIFT 17
2218
2219/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2220 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2221 */
2222#define SWDPIO__EXT_SHIFT 4
2223
2224/* Number of bits required to shift left the "ILOS" bit from the EEPROM
2225 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2226 */
2227#define ILOS_SHIFT 3
2228
2229
2230#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2231
2232/* Number of milliseconds we wait for auto-negotiation to complete */
2233#define LINK_UP_TIMEOUT 500
2234
2d7edb92
MC		 2235/* Number of 100 microseconds we wait for PCI Express master disable */
2236#define MASTER_DISABLE_TIMEOUT 800
2237/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2238#define AUTO_READ_DONE_TIMEOUT 10
2239/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2240#define PHY_CFG_TIMEOUT 40
2241
1da177e4
LT		 2242#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2243
2244/* The carrier extension symbol, as received by the NIC. */
2245#define CARRIER_EXTENSION 0x0F
2246
2247/* TBI_ACCEPT macro definition:
2248 *
2249 * This macro requires:
2250 * adapter = a pointer to struct e1000_hw
2251 * status = the 8 bit status field of the RX descriptor with EOP set
2252 * error = the 8 bit error field of the RX descriptor with EOP set
2253 * length = the sum of all the length fields of the RX descriptors that
2254 * make up the current frame
2255 * last_byte = the last byte of the frame DMAed by the hardware
2256 * max_frame_length = the maximum frame length we want to accept.
2257 * min_frame_length = the minimum frame length we want to accept.
2258 *
2259 * This macro is a conditional that should be used in the interrupt
2260 * handler's Rx processing routine when RxErrors have been detected.
2261 *
2262 * Typical use:
2263 * ...
2264 * if (TBI_ACCEPT) {
2265 * accept_frame = TRUE;
2266 * e1000_tbi_adjust_stats(adapter, MacAddress);
2267 * frame_length--;
2268 * } else {
2269 * accept_frame = FALSE;
2270 * }
2271 * ...
2272 */
2273
2274#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2275 ((adapter)->tbi_compatibility_on && \
2276 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2277 ((last_byte) == CARRIER_EXTENSION) && \
2278 (((status) & E1000_RXD_STAT_VP) ? \
2279 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2280 ((length) <= ((adapter)->max_frame_size + 1))) : \
2281 (((length) > (adapter)->min_frame_size) && \
2282 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2283
2284
2285/* Structures, enums, and macros for the PHY */
2286
2287/* Bit definitions for the Management Data IO (MDIO) and Management Data
2288 * Clock (MDC) pins in the Device Control Register.
2289 */
2290#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2291#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2292#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2293#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2294#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2295#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2296#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2297#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2298
2299/* PHY 1000 MII Register/Bit Definitions */
2300/* PHY Registers defined by IEEE */
2301#define PHY_CTRL 0x00 /* Control Register */
2302#define PHY_STATUS 0x01 /* Status Regiser */
2303#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2304#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2305#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2306#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2307#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2308#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2309#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2310#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2311#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2312#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2313
2314#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2315#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2316
2317/* M88E1000 Specific Registers */
2318#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2319#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2320#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2321#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2322#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2323#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2324
2325#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2326#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2327#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2328#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2329#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2330
2331#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2332#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2333#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2334
2335/* IGP01E1000 Specific Registers */
2336#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2337#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2338#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2339#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2340#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2341#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2d7edb92 2342#define IGP02E1000_PHY_POWER_MGMT 0x19
1da177e4
LT		 2343#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2344
2345/* IGP01E1000 AGC Registers - stores the cable length values*/
2346#define IGP01E1000_PHY_AGC_A 0x1172
2347#define IGP01E1000_PHY_AGC_B 0x1272
2348#define IGP01E1000_PHY_AGC_C 0x1472
2349#define IGP01E1000_PHY_AGC_D 0x1872
2350
2d7edb92
MC		 2351/* IGP02E1000 AGC Registers for cable length values */
2352#define IGP02E1000_PHY_AGC_A 0x11B1
2353#define IGP02E1000_PHY_AGC_B 0x12B1
2354#define IGP02E1000_PHY_AGC_C 0x14B1
2355#define IGP02E1000_PHY_AGC_D 0x18B1
2356
1da177e4
LT		 2357/* IGP01E1000 DSP Reset Register */
2358#define IGP01E1000_PHY_DSP_RESET 0x1F33
2359#define IGP01E1000_PHY_DSP_SET 0x1F71
2360#define IGP01E1000_PHY_DSP_FFE 0x1F35
2361
2362#define IGP01E1000_PHY_CHANNEL_NUM 4
2d7edb92
MC		 2363#define IGP02E1000_PHY_CHANNEL_NUM 4
2364
1da177e4
LT		 2365#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2366#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2367#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2368#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2369
2370#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2371#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2372
2373#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2374#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2375#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2376#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2377
2378#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2379/* IGP01E1000 PCS Initialization register - stores the polarity status when
2380 * speed = 1000 Mbps. */
2381#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2382#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2383
2384#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2385
2386
2387/* PHY Control Register */
2388#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2389#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2390#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2391#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2392#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2393#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2394#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2395#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2396#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2397#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2398
2399/* PHY Status Register */
2400#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2401#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2402#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2403#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2404#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2405#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2406#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2407#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2408#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2409#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2410#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2411#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2412#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2413#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2414#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2415
2416/* Autoneg Advertisement Register */
2417#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2418#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2419#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2420#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2421#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2422#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2423#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2424#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2425#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2426#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2427
2428/* Link Partner Ability Register (Base Page) */
2429#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2430#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2431#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2432#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2433#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2434#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2435#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2436#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2437#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2438#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2439#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2440
2441/* Autoneg Expansion Register */
2442#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2443#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2444#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2445#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2446#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2447
2448/* Next Page TX Register */
2449#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2450#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2451 * of different NP
2452 */
2453#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2454 * 0 = cannot comply with msg
2455 */
2456#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2457#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2458 * 0 = sending last NP
2459 */
2460
2461/* Link Partner Next Page Register */
2462#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2463#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2464 * of different NP
2465 */
2466#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2467 * 0 = cannot comply with msg
2468 */
2469#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2470#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2471#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2472 * 0 = sending last NP
2473 */
2474
2475/* 1000BASE-T Control Register */
2476#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2477#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2478#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2479#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2480 /* 0=DTE device */
2481#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2482 /* 0=Configure PHY as Slave */
2483#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2484 /* 0=Automatic Master/Slave config */
2485#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2486#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2487#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2488#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2489#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2490
2491/* 1000BASE-T Status Register */
2492#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2493#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2494#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2495#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2496#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2497#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2498#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2499#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2500#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2501#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2502#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2503#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2504#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2505
2506/* Extended Status Register */
2507#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2508#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2509#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2510#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2511
2512#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2513#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2514
2515#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2516 /* (0=enable, 1=disable) */
2517
2518/* M88E1000 PHY Specific Control Register */
2519#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2520#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2521#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2522#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2523 * 0=CLK125 toggling
2524 */
2525#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2526 /* Manual MDI configuration */
2527#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2528#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2529 * 100BASE-TX/10BASE-T:
2530 * MDI Mode
2531 */
2532#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2533 * all speeds.
2534 */
2535#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2536 /* 1=Enable Extended 10BASE-T distance
2537 * (Lower 10BASE-T RX Threshold)
2538 * 0=Normal 10BASE-T RX Threshold */
2539#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2540 /* 1=5-Bit interface in 100BASE-TX
2541 * 0=MII interface in 100BASE-TX */
2542#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2543#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2544#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2545
2546#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2547#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2548#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2549
2550/* M88E1000 PHY Specific Status Register */
2551#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2552#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2553#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2554#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2555#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2556 * 3=110-140M;4=>140M */
2557#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2558#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2559#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2560#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2561#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2562#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2563#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2564#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2565
2566#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2567#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2568#define M88E1000_PSSR_MDIX_SHIFT 6
2569#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2570
2571/* M88E1000 Extended PHY Specific Control Register */
2572#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2573#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2574 * Will assert lost lock and bring
2575 * link down if idle not seen
2576 * within 1ms in 1000BASE-T
2577 */
2578/* Number of times we will attempt to autonegotiate before downshifting if we
2579 * are the master */
2580#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2581#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2582#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2583#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2584#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2585/* Number of times we will attempt to autonegotiate before downshifting if we
2586 * are the slave */
2587#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2588#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2589#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2590#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2591#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2592#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2593#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2594#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2595
2596/* IGP01E1000 Specific Port Config Register - R/W */
2597#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2598#define IGP01E1000_PSCFR_PRE_EN 0x0020
2599#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2600#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2601#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2602#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2603
2604/* IGP01E1000 Specific Port Status Register - R/O */
2605#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2606#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2607#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2608#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2609#define IGP01E1000_PSSR_LINK_UP 0x0400
2610#define IGP01E1000_PSSR_MDIX 0x0800
2611#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2612#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2613#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2614#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2615#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2616#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2617
2618/* IGP01E1000 Specific Port Control Register - R/W */
2619#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2620#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2621#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2622#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2623#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2624#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2625
2626/* IGP01E1000 Specific Port Link Health Register */
2627#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2628#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2629#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2630#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2631#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2632#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2633#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2634#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2635#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2636#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2637#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2638#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2639#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2640#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2641
2642/* IGP01E1000 Channel Quality Register */
2643#define IGP01E1000_MSE_CHANNEL_D 0x000F
2644#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2645#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2646#define IGP01E1000_MSE_CHANNEL_A 0xF000
2647
2d7edb92
MC		 2648#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2649#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2650#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2651
1da177e4
LT		 2652/* IGP01E1000 DSP reset macros */
2653#define DSP_RESET_ENABLE 0x0
2654#define DSP_RESET_DISABLE 0x2
2655#define E1000_MAX_DSP_RESETS 10
2656
2d7edb92 2657/* IGP01E1000 & IGP02E1000 AGC Registers */
1da177e4
LT		 2658
2659#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2d7edb92
MC		 2660#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2661
2662/* IGP02E1000 AGC Register Length 9-bit mask */
2663#define IGP02E1000_AGC_LENGTH_MASK 0x7F
1da177e4
LT		 2664
2665/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2666#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
868d5309 2667#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
1da177e4 2668
2d7edb92 2669/* The precision error of the cable length is +/- 10 meters */
1da177e4 2670#define IGP01E1000_AGC_RANGE 10
868d5309 2671#define IGP02E1000_AGC_RANGE 15
1da177e4
LT		 2672
2673/* IGP01E1000 PCS Initialization register */
2674/* bits 3:6 in the PCS registers stores the channels polarity */
2675#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2676
2677/* IGP01E1000 GMII FIFO Register */
2678#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2679 * on Link-Up */
2680#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2681
2682/* IGP01E1000 Analog Register */
2683#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2684#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2685#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2686#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2687
2688#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2689#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2690#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2691#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2692#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2693
2694#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2695#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2696#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2697#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2698
2699
2700/* Bit definitions for valid PHY IDs. */
2701/* I = Integrated
2702 * E = External
2703 */
2704#define M88E1000_E_PHY_ID 0x01410C50
2705#define M88E1000_I_PHY_ID 0x01410C30
2706#define M88E1011_I_PHY_ID 0x01410C20
2707#define IGP01E1000_I_PHY_ID 0x02A80380
2708#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2709#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2710#define M88E1011_I_REV_4 0x04
2d7edb92
MC		 2711#define M88E1111_I_PHY_ID 0x01410CC0
2712#define L1LXT971A_PHY_ID 0x001378E0
1da177e4
LT		 2713
2714/* Miscellaneous PHY bit definitions. */
2715#define PHY_PREAMBLE 0xFFFFFFFF
2716#define PHY_SOF 0x01
2717#define PHY_OP_READ 0x02
2718#define PHY_OP_WRITE 0x01
2719#define PHY_TURNAROUND 0x02
2720#define PHY_PREAMBLE_SIZE 32
2721#define MII_CR_SPEED_1000 0x0040
2722#define MII_CR_SPEED_100 0x2000
2723#define MII_CR_SPEED_10 0x0000
2724#define E1000_PHY_ADDRESS 0x01
2725#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2726#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
2727#define PHY_REVISION_MASK 0xFFFFFFF0
2728#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
2729#define REG4_SPEED_MASK 0x01E0
2730#define REG9_SPEED_MASK 0x0300
2731#define ADVERTISE_10_HALF 0x0001
2732#define ADVERTISE_10_FULL 0x0002
2733#define ADVERTISE_100_HALF 0x0004
2734#define ADVERTISE_100_FULL 0x0008
2735#define ADVERTISE_1000_HALF 0x0010
2736#define ADVERTISE_1000_FULL 0x0020
2737#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2738#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
2739#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
2740
2741#endif /* _E1000_HW_H_ */
Linux kernel - Deliverables
This page took 0.181071 seconds and 5 git commands to generate.