projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
tree-wide: fix comment/printk typos
[deliverable/linux.git] / drivers / net / e1000 / e1000_hw.h
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include "e1000_osdep.h"
37
675ad473 38
1da177e4
LT		 39/* Forward declarations of structures used by the shared code */
40struct e1000_hw;
41struct e1000_hw_stats;
42
43/* Enumerated types specific to the e1000 hardware */
b595076a 44/* Media Access Controllers */
1da177e4 45typedef enum {
120a5d0d
JB		 46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_82546_rev_3,
56 e1000_82541,
57 e1000_82541_rev_2,
58 e1000_82547,
59 e1000_82547_rev_2,
60 e1000_num_macs
1da177e4
LT		 61} e1000_mac_type;
62
63typedef enum {
120a5d0d
JB		 64 e1000_eeprom_uninitialized = 0,
65 e1000_eeprom_spi,
66 e1000_eeprom_microwire,
67 e1000_eeprom_flash,
68 e1000_eeprom_none, /* No NVM support */
69 e1000_num_eeprom_types
1da177e4
LT		 70} e1000_eeprom_type;
71
72/* Media Types */
73typedef enum {
120a5d0d
JB		 74 e1000_media_type_copper = 0,
75 e1000_media_type_fiber = 1,
76 e1000_media_type_internal_serdes = 2,
77 e1000_num_media_types
1da177e4
LT		 78} e1000_media_type;
79
80typedef enum {
120a5d0d
JB		 81 e1000_10_half = 0,
82 e1000_10_full = 1,
83 e1000_100_half = 2,
84 e1000_100_full = 3
1da177e4
LT		 85} e1000_speed_duplex_type;
86
87/* Flow Control Settings */
88typedef enum {
120a5d0d
JB		 89 E1000_FC_NONE = 0,
90 E1000_FC_RX_PAUSE = 1,
91 E1000_FC_TX_PAUSE = 2,
92 E1000_FC_FULL = 3,
93 E1000_FC_DEFAULT = 0xFF
1da177e4
LT		 94} e1000_fc_type;
95
d37ea5d5 96struct e1000_shadow_ram {
120a5d0d
JB		 97 u16 eeprom_word;
98 bool modified;
d37ea5d5
AK		 99};
100
1da177e4
LT		 101/* PCI bus types */
102typedef enum {
120a5d0d
JB		 103 e1000_bus_type_unknown = 0,
104 e1000_bus_type_pci,
105 e1000_bus_type_pcix,
106 e1000_bus_type_reserved
1da177e4
LT		 107} e1000_bus_type;
108
109/* PCI bus speeds */
110typedef enum {
120a5d0d
JB		 111 e1000_bus_speed_unknown = 0,
112 e1000_bus_speed_33,
113 e1000_bus_speed_66,
114 e1000_bus_speed_100,
115 e1000_bus_speed_120,
116 e1000_bus_speed_133,
117 e1000_bus_speed_reserved
1da177e4
LT		 118} e1000_bus_speed;
119
120/* PCI bus widths */
121typedef enum {
120a5d0d
JB		 122 e1000_bus_width_unknown = 0,
123 e1000_bus_width_32,
124 e1000_bus_width_64,
125 e1000_bus_width_reserved
1da177e4
LT		 126} e1000_bus_width;
127
128/* PHY status info structure and supporting enums */
129typedef enum {
120a5d0d
JB		 130 e1000_cable_length_50 = 0,
131 e1000_cable_length_50_80,
132 e1000_cable_length_80_110,
133 e1000_cable_length_110_140,
134 e1000_cable_length_140,
135 e1000_cable_length_undefined = 0xFF
1da177e4
LT		 136} e1000_cable_length;
137
6418ecc6 138typedef enum {
120a5d0d
JB		 139 e1000_gg_cable_length_60 = 0,
140 e1000_gg_cable_length_60_115 = 1,
141 e1000_gg_cable_length_115_150 = 2,
142 e1000_gg_cable_length_150 = 4
6418ecc6
JK		 143} e1000_gg_cable_length;
144
1da177e4 145typedef enum {
120a5d0d
JB		 146 e1000_igp_cable_length_10 = 10,
147 e1000_igp_cable_length_20 = 20,
148 e1000_igp_cable_length_30 = 30,
149 e1000_igp_cable_length_40 = 40,
150 e1000_igp_cable_length_50 = 50,
151 e1000_igp_cable_length_60 = 60,
152 e1000_igp_cable_length_70 = 70,
153 e1000_igp_cable_length_80 = 80,
154 e1000_igp_cable_length_90 = 90,
155 e1000_igp_cable_length_100 = 100,
156 e1000_igp_cable_length_110 = 110,
157 e1000_igp_cable_length_115 = 115,
158 e1000_igp_cable_length_120 = 120,
159 e1000_igp_cable_length_130 = 130,
160 e1000_igp_cable_length_140 = 140,
161 e1000_igp_cable_length_150 = 150,
162 e1000_igp_cable_length_160 = 160,
163 e1000_igp_cable_length_170 = 170,
164 e1000_igp_cable_length_180 = 180
1da177e4
LT		 165} e1000_igp_cable_length;
166
167typedef enum {
120a5d0d
JB		 168 e1000_10bt_ext_dist_enable_normal = 0,
169 e1000_10bt_ext_dist_enable_lower,
170 e1000_10bt_ext_dist_enable_undefined = 0xFF
1da177e4
LT		 171} e1000_10bt_ext_dist_enable;
172
173typedef enum {
120a5d0d
JB		 174 e1000_rev_polarity_normal = 0,
175 e1000_rev_polarity_reversed,
176 e1000_rev_polarity_undefined = 0xFF
1da177e4
LT		 177} e1000_rev_polarity;
178
179typedef enum {
120a5d0d
JB		 180 e1000_downshift_normal = 0,
181 e1000_downshift_activated,
182 e1000_downshift_undefined = 0xFF
1da177e4
LT		 183} e1000_downshift;
184
185typedef enum {
120a5d0d
JB		 186 e1000_smart_speed_default = 0,
187 e1000_smart_speed_on,
188 e1000_smart_speed_off
1da177e4
LT		 189} e1000_smart_speed;
190
191typedef enum {
120a5d0d
JB		 192 e1000_polarity_reversal_enabled = 0,
193 e1000_polarity_reversal_disabled,
194 e1000_polarity_reversal_undefined = 0xFF
1da177e4
LT		 195} e1000_polarity_reversal;
196
197typedef enum {
120a5d0d
JB		 198 e1000_auto_x_mode_manual_mdi = 0,
199 e1000_auto_x_mode_manual_mdix,
200 e1000_auto_x_mode_auto1,
201 e1000_auto_x_mode_auto2,
202 e1000_auto_x_mode_undefined = 0xFF
1da177e4
LT		 203} e1000_auto_x_mode;
204
205typedef enum {
120a5d0d
JB		 206 e1000_1000t_rx_status_not_ok = 0,
207 e1000_1000t_rx_status_ok,
208 e1000_1000t_rx_status_undefined = 0xFF
1da177e4
LT		 209} e1000_1000t_rx_status;
210
211typedef enum {
212 e1000_phy_m88 = 0,
213 e1000_phy_igp,
214 e1000_phy_undefined = 0xFF
215} e1000_phy_type;
216
217typedef enum {
120a5d0d
JB		 218 e1000_ms_hw_default = 0,
219 e1000_ms_force_master,
220 e1000_ms_force_slave,
221 e1000_ms_auto
1da177e4
LT		 222} e1000_ms_type;
223
224typedef enum {
120a5d0d
JB		 225 e1000_ffe_config_enabled = 0,
226 e1000_ffe_config_active,
227 e1000_ffe_config_blocked
1da177e4
LT		 228} e1000_ffe_config;
229
230typedef enum {
120a5d0d
JB		 231 e1000_dsp_config_disabled = 0,
232 e1000_dsp_config_enabled,
233 e1000_dsp_config_activated,
234 e1000_dsp_config_undefined = 0xFF
1da177e4
LT		 235} e1000_dsp_config;
236
237struct e1000_phy_info {
120a5d0d
JB		 238 e1000_cable_length cable_length;
239 e1000_10bt_ext_dist_enable extended_10bt_distance;
240 e1000_rev_polarity cable_polarity;
241 e1000_downshift downshift;
242 e1000_polarity_reversal polarity_correction;
243 e1000_auto_x_mode mdix_mode;
244 e1000_1000t_rx_status local_rx;
245 e1000_1000t_rx_status remote_rx;
1da177e4
LT		 246};
247
248struct e1000_phy_stats {
120a5d0d
JB		 249 u32 idle_errors;
250 u32 receive_errors;
1da177e4
LT		 251};
252
253struct e1000_eeprom_info {
120a5d0d
JB		 254 e1000_eeprom_type type;
255 u16 word_size;
256 u16 opcode_bits;
257 u16 address_bits;
258 u16 delay_usec;
259 u16 page_size;
1da177e4
LT		 260};
261
2d7edb92
MC		 262/* Flex ASF Information */
263#define E1000_HOST_IF_MAX_SIZE 2048
264
265typedef enum {
120a5d0d
JB		 266 e1000_byte_align = 0,
267 e1000_word_align = 1,
268 e1000_dword_align = 2
2d7edb92
MC		 269} e1000_align_type;
270
1da177e4
LT		 271/* Error Codes */
272#define E1000_SUCCESS 0
273#define E1000_ERR_EEPROM 1
274#define E1000_ERR_PHY 2
275#define E1000_ERR_CONFIG 3
276#define E1000_ERR_PARAM 4
277#define E1000_ERR_MAC_TYPE 5
278#define E1000_ERR_PHY_TYPE 6
2d7edb92
MC		 279#define E1000_ERR_RESET 9
280#define E1000_ERR_MASTER_REQUESTS_PENDING 10
281#define E1000_ERR_HOST_INTERFACE_COMMAND 11
282#define E1000_BLK_PHY_RESET 12
1da177e4 283
2a88c173
JK		 284#define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \
285 (((_value) & 0xff00) >> 8))
286
1da177e4
LT		 287/* Function prototypes */
288/* Initialization */
406874a7
JP		 289s32 e1000_reset_hw(struct e1000_hw *hw);
290s32 e1000_init_hw(struct e1000_hw *hw);
291s32 e1000_set_mac_type(struct e1000_hw *hw);
1da177e4
LT		 292void e1000_set_media_type(struct e1000_hw *hw);
293
294/* Link Configuration */
406874a7
JP		 295s32 e1000_setup_link(struct e1000_hw *hw);
296s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
1da177e4 297void e1000_config_collision_dist(struct e1000_hw *hw);
406874a7 298s32 e1000_check_for_link(struct e1000_hw *hw);
120a5d0d 299s32 e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 * speed, u16 * duplex);
406874a7 300s32 e1000_force_mac_fc(struct e1000_hw *hw);
1da177e4
LT		 301
302/* PHY */
120a5d0d 303s32 e1000_read_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 * phy_data);
406874a7
JP		 304s32 e1000_write_phy_reg(struct e1000_hw *hw, u32 reg_addr, u16 data);
305s32 e1000_phy_hw_reset(struct e1000_hw *hw);
306s32 e1000_phy_reset(struct e1000_hw *hw);
307s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
308s32 e1000_validate_mdi_setting(struct e1000_hw *hw);
90fb5135 309
1da177e4 310/* EEPROM Functions */
406874a7 311s32 e1000_init_eeprom_params(struct e1000_hw *hw);
2d7edb92
MC		 312
313/* MNG HOST IF functions */
406874a7 314u32 e1000_enable_mng_pass_thru(struct e1000_hw *hw);
2d7edb92
MC		 315
316#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
120a5d0d 317#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
2d7edb92 318
120a5d0d
JB		 319#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
320#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
321#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
8fc897b0 322#define E1000_MNG_IAMT_MODE 0x3
d37ea5d5 323#define E1000_MNG_ICH_IAMT_MODE 0x2
120a5d0d 324#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
2d7edb92 325
120a5d0d
JB		 326#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
327#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
2d7edb92
MC		 328#define E1000_VFTA_ENTRY_SHIFT 0x5
329#define E1000_VFTA_ENTRY_MASK 0x7F
330#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
331
332struct e1000_host_mng_command_header {
120a5d0d
JB		 333 u8 command_id;
334 u8 checksum;
335 u16 reserved1;
336 u16 reserved2;
337 u16 command_length;
2d7edb92
MC		 338};
339
340struct e1000_host_mng_command_info {
120a5d0d
JB		 341 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
342 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658 */
2d7edb92
MC		 343};
344#ifdef __BIG_ENDIAN
120a5d0d
JB		 345struct e1000_host_mng_dhcp_cookie {
346 u32 signature;
347 u16 vlan_id;
348 u8 reserved0;
349 u8 status;
350 u32 reserved1;
351 u8 checksum;
352 u8 reserved3;
353 u16 reserved2;
2d7edb92
MC		 354};
355#else
120a5d0d
JB		 356struct e1000_host_mng_dhcp_cookie {
357 u32 signature;
358 u8 status;
359 u8 reserved0;
360 u16 vlan_id;
361 u32 reserved1;
362 u16 reserved2;
363 u8 reserved3;
364 u8 checksum;
2d7edb92
MC		 365};
366#endif
367
c3033b01 368bool e1000_check_mng_mode(struct e1000_hw *hw);
120a5d0d 369s32 e1000_read_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
406874a7
JP		 370s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw);
371s32 e1000_update_eeprom_checksum(struct e1000_hw *hw);
120a5d0d
JB		 372s32 e1000_write_eeprom(struct e1000_hw *hw, u16 reg, u16 words, u16 * data);
373s32 e1000_read_mac_addr(struct e1000_hw *hw);
1da177e4
LT		 374
375/* Filters (multicast, vlan, receive) */
406874a7
JP		 376u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 * mc_addr);
377void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
378void e1000_rar_set(struct e1000_hw *hw, u8 * mc_addr, u32 rar_index);
379void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
1da177e4
LT		 380
381/* LED functions */
406874a7
JP		 382s32 e1000_setup_led(struct e1000_hw *hw);
383s32 e1000_cleanup_led(struct e1000_hw *hw);
384s32 e1000_led_on(struct e1000_hw *hw);
385s32 e1000_led_off(struct e1000_hw *hw);
386s32 e1000_blink_led_start(struct e1000_hw *hw);
1da177e4
LT		 387
388/* Adaptive IFS Functions */
389
390/* Everything else */
1da177e4
LT		 391void e1000_reset_adaptive(struct e1000_hw *hw);
392void e1000_update_adaptive(struct e1000_hw *hw);
120a5d0d
JB		 393void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats,
394 u32 frame_len, u8 * mac_addr);
1da177e4
LT		 395void e1000_get_bus_info(struct e1000_hw *hw);
396void e1000_pci_set_mwi(struct e1000_hw *hw);
397void e1000_pci_clear_mwi(struct e1000_hw *hw);
007755eb
PO		 398void e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc);
399int e1000_pcix_get_mmrbc(struct e1000_hw *hw);
1da177e4 400/* Port I/O is only supported on 82544 and newer */
406874a7 401void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
d37ea5d5 402
d37ea5d5
AK		 403#define E1000_READ_REG_IO(a, reg) \
404 e1000_read_reg_io((a), E1000_##reg)
405#define E1000_WRITE_REG_IO(a, reg, val) \
406 e1000_write_reg_io((a), E1000_##reg, val)
1da177e4
LT		 407
408/* PCI Device IDs */
409#define E1000_DEV_ID_82542 0x1000
410#define E1000_DEV_ID_82543GC_FIBER 0x1001
411#define E1000_DEV_ID_82543GC_COPPER 0x1004
412#define E1000_DEV_ID_82544EI_COPPER 0x1008
413#define E1000_DEV_ID_82544EI_FIBER 0x1009
414#define E1000_DEV_ID_82544GC_COPPER 0x100C
415#define E1000_DEV_ID_82544GC_LOM 0x100D
416#define E1000_DEV_ID_82540EM 0x100E
417#define E1000_DEV_ID_82540EM_LOM 0x1015
418#define E1000_DEV_ID_82540EP_LOM 0x1016
419#define E1000_DEV_ID_82540EP 0x1017
420#define E1000_DEV_ID_82540EP_LP 0x101E
421#define E1000_DEV_ID_82545EM_COPPER 0x100F
422#define E1000_DEV_ID_82545EM_FIBER 0x1011
423#define E1000_DEV_ID_82545GM_COPPER 0x1026
424#define E1000_DEV_ID_82545GM_FIBER 0x1027
425#define E1000_DEV_ID_82545GM_SERDES 0x1028
426#define E1000_DEV_ID_82546EB_COPPER 0x1010
427#define E1000_DEV_ID_82546EB_FIBER 0x1012
428#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
429#define E1000_DEV_ID_82541EI 0x1013
430#define E1000_DEV_ID_82541EI_MOBILE 0x1018
d37ea5d5 431#define E1000_DEV_ID_82541ER_LOM 0x1014
1da177e4
LT		 432#define E1000_DEV_ID_82541ER 0x1078
433#define E1000_DEV_ID_82547GI 0x1075
434#define E1000_DEV_ID_82541GI 0x1076
435#define E1000_DEV_ID_82541GI_MOBILE 0x1077
436#define E1000_DEV_ID_82541GI_LF 0x107C
437#define E1000_DEV_ID_82546GB_COPPER 0x1079
438#define E1000_DEV_ID_82546GB_FIBER 0x107A
439#define E1000_DEV_ID_82546GB_SERDES 0x107B
440#define E1000_DEV_ID_82546GB_PCIE 0x108A
b7ee49db 441#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
1da177e4 442#define E1000_DEV_ID_82547EI 0x1019
d37ea5d5 443#define E1000_DEV_ID_82547EI_MOBILE 0x101A
b7ee49db 444#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
1da177e4
LT		 445
446#define NODE_ADDRESS_SIZE 6
447#define ETH_LENGTH_OF_ADDRESS 6
448
449/* MAC decode size is 128K - This is the size of BAR0 */
450#define MAC_DECODE_SIZE (128 * 1024)
451
452#define E1000_82542_2_0_REV_ID 2
453#define E1000_82542_2_1_REV_ID 3
454#define E1000_REVISION_0 0
455#define E1000_REVISION_1 1
456#define E1000_REVISION_2 2
2d7edb92 457#define E1000_REVISION_3 3
1da177e4
LT		 458
459#define SPEED_10 10
460#define SPEED_100 100
461#define SPEED_1000 1000
462#define HALF_DUPLEX 1
463#define FULL_DUPLEX 2
464
465/* The sizes (in bytes) of a ethernet packet */
466#define ENET_HEADER_SIZE 14
120a5d0d 467#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
1da177e4 468#define ETHERNET_FCS_SIZE 4
1da177e4
LT		 469#define MINIMUM_ETHERNET_PACKET_SIZE \
470 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
471#define CRC_LENGTH ETHERNET_FCS_SIZE
472#define MAX_JUMBO_FRAME_SIZE 0x3F00
473
1da177e4 474/* 802.1q VLAN Packet Sizes */
120a5d0d 475#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
1da177e4
LT		 476
477/* Ethertype field values */
120a5d0d
JB		 478#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
479#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
480#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
1da177e4
LT		 481
482/* Packet Header defines */
483#define IP_PROTOCOL_TCP 6
484#define IP_PROTOCOL_UDP 0x11
485
486/* This defines the bits that are set in the Interrupt Mask
487 * Set/Read Register. Each bit is documented below:
488 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
489 * o RXSEQ = Receive Sequence Error
490 */
491#define POLL_IMS_ENABLE_MASK ( \
492 E1000_IMS_RXDMT0 | \
493 E1000_IMS_RXSEQ)
494
495/* This defines the bits that are set in the Interrupt Mask
496 * Set/Read Register. Each bit is documented below:
497 * o RXT0 = Receiver Timer Interrupt (ring 0)
498 * o TXDW = Transmit Descriptor Written Back
499 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
500 * o RXSEQ = Receive Sequence Error
501 * o LSC = Link Status Change
502 */
503#define IMS_ENABLE_MASK ( \
504 E1000_IMS_RXT0 | \
505 E1000_IMS_TXDW | \
506 E1000_IMS_RXDMT0 | \
507 E1000_IMS_RXSEQ | \
508 E1000_IMS_LSC)
509
510/* Number of high/low register pairs in the RAR. The RAR (Receive Address
511 * Registers) holds the directed and multicast addresses that we monitor. We
512 * reserve one of these spots for our directed address, allowing us room for
513 * E1000_RAR_ENTRIES - 1 multicast addresses.
514 */
515#define E1000_RAR_ENTRIES 15
90fb5135 516
4f5f2317
JK		 517#define MIN_NUMBER_OF_DESCRIPTORS 8
518#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
1da177e4
LT		 519
520/* Receive Descriptor */
521struct e1000_rx_desc {
120a5d0d
JB		 522 __le64 buffer_addr; /* Address of the descriptor's data buffer */
523 __le16 length; /* Length of data DMAed into data buffer */
524 __le16 csum; /* Packet checksum */
525 u8 status; /* Descriptor status */
526 u8 errors; /* Descriptor Errors */
527 __le16 special;
1da177e4
LT		 528};
529
2d7edb92
MC		 530/* Receive Descriptor - Extended */
531union e1000_rx_desc_extended {
120a5d0d
JB		 532 struct {
533 __le64 buffer_addr;
534 __le64 reserved;
535 } read;
536 struct {
537 struct {
538 __le32 mrq; /* Multiple Rx Queues */
539 union {
540 __le32 rss; /* RSS Hash */
541 struct {
542 __le16 ip_id; /* IP id */
543 __le16 csum; /* Packet Checksum */
544 } csum_ip;
545 } hi_dword;
546 } lower;
547 struct {
548 __le32 status_error; /* ext status/error */
549 __le16 length;
550 __le16 vlan; /* VLAN tag */
551 } upper;
552 } wb; /* writeback */
2d7edb92
MC		 553};
554
555#define MAX_PS_BUFFERS 4
556/* Receive Descriptor - Packet Split */
557union e1000_rx_desc_packet_split {
120a5d0d
JB		 558 struct {
559 /* one buffer for protocol header(s), three data buffers */
560 __le64 buffer_addr[MAX_PS_BUFFERS];
561 } read;
562 struct {
563 struct {
564 __le32 mrq; /* Multiple Rx Queues */
565 union {
566 __le32 rss; /* RSS Hash */
567 struct {
568 __le16 ip_id; /* IP id */
569 __le16 csum; /* Packet Checksum */
570 } csum_ip;
571 } hi_dword;
572 } lower;
573 struct {
574 __le32 status_error; /* ext status/error */
575 __le16 length0; /* length of buffer 0 */
576 __le16 vlan; /* VLAN tag */
577 } middle;
578 struct {
579 __le16 header_status;
580 __le16 length[3]; /* length of buffers 1-3 */
581 } upper;
582 __le64 reserved;
583 } wb; /* writeback */
2d7edb92
MC		 584};
585
120a5d0d
JB		 586/* Receive Descriptor bit definitions */
587#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
588#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
589#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
590#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
591#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
592#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
593#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
594#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
595#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
596#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
597#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
598#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
599#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
600#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
601#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
602#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
603#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
604#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
605#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
606#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2d7edb92 607#define E1000_RXD_SPC_PRI_SHIFT 13
120a5d0d 608#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
2d7edb92
MC		 609#define E1000_RXD_SPC_CFI_SHIFT 12
610
611#define E1000_RXDEXT_STATERR_CE 0x01000000
612#define E1000_RXDEXT_STATERR_SE 0x02000000
613#define E1000_RXDEXT_STATERR_SEQ 0x04000000
614#define E1000_RXDEXT_STATERR_CXE 0x10000000
615#define E1000_RXDEXT_STATERR_TCPE 0x20000000
616#define E1000_RXDEXT_STATERR_IPE 0x40000000
617#define E1000_RXDEXT_STATERR_RXE 0x80000000
618
619#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
620#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1da177e4
LT		 621
622/* mask to determine if packets should be dropped due to frame errors */
623#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
624 E1000_RXD_ERR_CE | \
625 E1000_RXD_ERR_SE | \
626 E1000_RXD_ERR_SEQ | \
627 E1000_RXD_ERR_CXE | \
628 E1000_RXD_ERR_RXE)
629
2d7edb92
MC		 630/* Same mask, but for extended and packet split descriptors */
631#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
632 E1000_RXDEXT_STATERR_CE | \
633 E1000_RXDEXT_STATERR_SE | \
634 E1000_RXDEXT_STATERR_SEQ | \
635 E1000_RXDEXT_STATERR_CXE | \
636 E1000_RXDEXT_STATERR_RXE)
637
1da177e4
LT		 638/* Transmit Descriptor */
639struct e1000_tx_desc {
120a5d0d
JB		 640 __le64 buffer_addr; /* Address of the descriptor's data buffer */
641 union {
642 __le32 data;
643 struct {
644 __le16 length; /* Data buffer length */
645 u8 cso; /* Checksum offset */
646 u8 cmd; /* Descriptor control */
647 } flags;
648 } lower;
649 union {
650 __le32 data;
651 struct {
652 u8 status; /* Descriptor status */
653 u8 css; /* Checksum start */
654 __le16 special;
655 } fields;
656 } upper;
1da177e4
LT		 657};
658
659/* Transmit Descriptor bit definitions */
120a5d0d
JB		 660#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
661#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
662#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
663#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
664#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
665#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
666#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
667#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
668#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
669#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
670#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
671#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
672#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
673#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
674#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
675#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
676#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
677#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
678#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
679#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
1da177e4
LT		 680
681/* Offload Context Descriptor */
682struct e1000_context_desc {
120a5d0d
JB		 683 union {
684 __le32 ip_config;
685 struct {
686 u8 ipcss; /* IP checksum start */
687 u8 ipcso; /* IP checksum offset */
688 __le16 ipcse; /* IP checksum end */
689 } ip_fields;
690 } lower_setup;
691 union {
692 __le32 tcp_config;
693 struct {
694 u8 tucss; /* TCP checksum start */
695 u8 tucso; /* TCP checksum offset */
696 __le16 tucse; /* TCP checksum end */
697 } tcp_fields;
698 } upper_setup;
699 __le32 cmd_and_length; /* */
700 union {
701 __le32 data;
702 struct {
703 u8 status; /* Descriptor status */
704 u8 hdr_len; /* Header length */
705 __le16 mss; /* Maximum segment size */
706 } fields;
707 } tcp_seg_setup;
1da177e4
LT		 708};
709
710/* Offload data descriptor */
711struct e1000_data_desc {
120a5d0d
JB		 712 __le64 buffer_addr; /* Address of the descriptor's buffer address */
713 union {
714 __le32 data;
715 struct {
716 __le16 length; /* Data buffer length */
717 u8 typ_len_ext; /* */
718 u8 cmd; /* */
719 } flags;
720 } lower;
721 union {
722 __le32 data;
723 struct {
724 u8 status; /* Descriptor status */
725 u8 popts; /* Packet Options */
726 __le16 special; /* */
727 } fields;
728 } upper;
1da177e4
LT		 729};
730
731/* Filters */
120a5d0d
JB		 732#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
733#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
734#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
1da177e4 735
1da177e4
LT		 736/* Receive Address Register */
737struct e1000_rar {
120a5d0d
JB		 738 volatile __le32 low; /* receive address low */
739 volatile __le32 high; /* receive address high */
1da177e4
LT		 740};
741
742/* Number of entries in the Multicast Table Array (MTA). */
743#define E1000_NUM_MTA_REGISTERS 128
744
745/* IPv4 Address Table Entry */
746struct e1000_ipv4_at_entry {
120a5d0d
JB		 747 volatile u32 ipv4_addr; /* IP Address (RW) */
748 volatile u32 reserved;
1da177e4
LT		 749};
750
751/* Four wakeup IP addresses are supported */
752#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
753#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
754#define E1000_IP6AT_SIZE 1
755
756/* IPv6 Address Table Entry */
757struct e1000_ipv6_at_entry {
120a5d0d 758 volatile u8 ipv6_addr[16];
1da177e4
LT		 759};
760
761/* Flexible Filter Length Table Entry */
762struct e1000_fflt_entry {
120a5d0d
JB		 763 volatile u32 length; /* Flexible Filter Length (RW) */
764 volatile u32 reserved;
1da177e4
LT		 765};
766
767/* Flexible Filter Mask Table Entry */
768struct e1000_ffmt_entry {
120a5d0d
JB		 769 volatile u32 mask; /* Flexible Filter Mask (RW) */
770 volatile u32 reserved;
1da177e4
LT		 771};
772
773/* Flexible Filter Value Table Entry */
774struct e1000_ffvt_entry {
120a5d0d
JB		 775 volatile u32 value; /* Flexible Filter Value (RW) */
776 volatile u32 reserved;
1da177e4
LT		 777};
778
779/* Four Flexible Filters are supported */
780#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
781
782/* Each Flexible Filter is at most 128 (0x80) bytes in length */
783#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
784
785#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
786#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
787#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
788
868d5309
MC		 789#define E1000_DISABLE_SERDES_LOOPBACK 0x0400
790
1da177e4
LT		 791/* Register Set. (82543, 82544)
792 *
793 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
794 * These registers are physically located on the NIC, but are mapped into the
795 * host memory address space.
796 *
797 * RW - register is both readable and writable
798 * RO - register is read only
799 * WO - register is write only
800 * R/clr - register is read only and is cleared when read
801 * A - register array
802 */
120a5d0d
JB		 803#define E1000_CTRL 0x00000 /* Device Control - RW */
804#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
805#define E1000_STATUS 0x00008 /* Device Status - RO */
806#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
807#define E1000_EERD 0x00014 /* EEPROM Read - RW */
808#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
809#define E1000_FLA 0x0001C /* Flash Access - RW */
810#define E1000_MDIC 0x00020 /* MDI Control - RW */
811#define E1000_SCTL 0x00024 /* SerDes Control - RW */
812#define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */
813#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
814#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
815#define E1000_FCT 0x00030 /* Flow Control Type - RW */
816#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
817#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
818#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
819#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
820#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
821#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
822#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
823#define E1000_RCTL 0x00100 /* RX Control - RW */
824#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
825#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
826#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
827#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
828#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
829#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
830#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
831#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
832#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
833#define E1000_TCTL 0x00400 /* TX Control - RW */
834#define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */
835#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
836#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
837#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
838#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
839#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
840#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
841#define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
d37ea5d5 842#define FEXTNVM_SW_CONFIG 0x0001
120a5d0d
JB		 843#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
844#define E1000_PBS 0x01008 /* Packet Buffer Size */
845#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
2d7edb92 846#define E1000_FLASH_UPDATES 1000
120a5d0d
JB		 847#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
848#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
849#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
850#define E1000_FLSWCTL 0x01030 /* FLASH control register */
851#define E1000_FLSWDATA 0x01034 /* FLASH data register */
852#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
853#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
854#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
855#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
856#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
857#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
858#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
859#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
860#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
861#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
862#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
863#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
864#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
865#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
866#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
867#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
868#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
869#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
870#define E1000_RXDCTL 0x02828 /* RX Descriptor Control queue 0 - RW */
871#define E1000_RXDCTL1 0x02928 /* RX Descriptor Control queue 1 - RW */
872#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
873#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
874#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
875#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
876#define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */
877#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
878#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
879#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
880#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
881#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
882#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
883#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
884#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
885#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
886#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
887#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
888#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
889#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
890#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
891#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
892#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
893#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
894#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
895#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
896#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
897#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
898#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
899#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
900#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
901#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
902#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
903#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
904#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
905#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
906#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
907#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
908#define E1000_COLC 0x04028 /* Collision Count - R/clr */
909#define E1000_DC 0x04030 /* Defer Count - R/clr */
910#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
911#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
912#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
913#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
914#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
915#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
916#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
917#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
918#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
919#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
920#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
921#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
922#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
923#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
924#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
925#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
926#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
927#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
928#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
929#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
930#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
931#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
932#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
933#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
934#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
935#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
936#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
937#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
938#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
939#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
940#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
941#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
942#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
943#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
944#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
945#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
946#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
947#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
948#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
949#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
950#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
951#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
952#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
953#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
954#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
955#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
956#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
957#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
958#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
959#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
960#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
961#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
962#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
963#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
964#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
965#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
966#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
967#define E1000_RFCTL 0x05008 /* Receive Filter Control */
968#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
969#define E1000_RA 0x05400 /* Receive Address - RW Array */
970#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
971#define E1000_WUC 0x05800 /* Wakeup Control - RW */
972#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
973#define E1000_WUS 0x05810 /* Wakeup Status - RO */
974#define E1000_MANC 0x05820 /* Management Control - RW */
975#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
976#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
977#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
978#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
979#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
980#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
981#define E1000_HOST_IF 0x08800 /* Host Interface */
982#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
983#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
984
985#define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
986#define E1000_MDPHYA 0x0003C /* PHY address - RW */
987#define E1000_MANC2H 0x05860 /* Managment Control To Host - RW */
988#define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
989
990#define E1000_GCR 0x05B00 /* PCI-Ex Control */
991#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
992#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
993#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
994#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
995#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
996#define E1000_SWSM 0x05B50 /* SW Semaphore */
997#define E1000_FWSM 0x05B54 /* FW Semaphore */
998#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
999#define E1000_HICR 0x08F00 /* Host Interface Control */
868d5309
MC		 1000
1001/* RSS registers */
120a5d0d
JB		 1002#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1003#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1004#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1005#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1006#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1007#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1da177e4
LT		 1008/* Register Set (82542)
1009 *
1010 * Some of the 82542 registers are located at different offsets than they are
1011 * in more current versions of the 8254x. Despite the difference in location,
1012 * the registers function in the same manner.
1013 */
1014#define E1000_82542_CTRL E1000_CTRL
1015#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1016#define E1000_82542_STATUS E1000_STATUS
1017#define E1000_82542_EECD E1000_EECD
1018#define E1000_82542_EERD E1000_EERD
1019#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1020#define E1000_82542_FLA E1000_FLA
1021#define E1000_82542_MDIC E1000_MDIC
868d5309 1022#define E1000_82542_SCTL E1000_SCTL
d37ea5d5 1023#define E1000_82542_FEXTNVM E1000_FEXTNVM
1da177e4
LT		 1024#define E1000_82542_FCAL E1000_FCAL
1025#define E1000_82542_FCAH E1000_FCAH
1026#define E1000_82542_FCT E1000_FCT
1027#define E1000_82542_VET E1000_VET
1028#define E1000_82542_RA 0x00040
1029#define E1000_82542_ICR E1000_ICR
1030#define E1000_82542_ITR E1000_ITR
1031#define E1000_82542_ICS E1000_ICS
1032#define E1000_82542_IMS E1000_IMS
1033#define E1000_82542_IMC E1000_IMC
1034#define E1000_82542_RCTL E1000_RCTL
1035#define E1000_82542_RDTR 0x00108
1036#define E1000_82542_RDBAL 0x00110
1037#define E1000_82542_RDBAH 0x00114
1038#define E1000_82542_RDLEN 0x00118
1039#define E1000_82542_RDH 0x00120
1040#define E1000_82542_RDT 0x00128
868d5309
MC		 1041#define E1000_82542_RDTR0 E1000_82542_RDTR
1042#define E1000_82542_RDBAL0 E1000_82542_RDBAL
1043#define E1000_82542_RDBAH0 E1000_82542_RDBAH
1044#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1045#define E1000_82542_RDH0 E1000_82542_RDH
1046#define E1000_82542_RDT0 E1000_82542_RDT
120a5d0d
JB		 1047#define E1000_82542_SRRCTL(_n) (0x280C + ((_n) << 8)) /* Split and Replication
1048 * RX Control - RW */
d37ea5d5 1049#define E1000_82542_DCA_RXCTRL(_n) (0x02814 + ((_n) << 8))
120a5d0d
JB		 1050#define E1000_82542_RDBAH3 0x02B04 /* RX Desc Base High Queue 3 - RW */
1051#define E1000_82542_RDBAL3 0x02B00 /* RX Desc Low Queue 3 - RW */
1052#define E1000_82542_RDLEN3 0x02B08 /* RX Desc Length Queue 3 - RW */
1053#define E1000_82542_RDH3 0x02B10 /* RX Desc Head Queue 3 - RW */
1054#define E1000_82542_RDT3 0x02B18 /* RX Desc Tail Queue 3 - RW */
1055#define E1000_82542_RDBAL2 0x02A00 /* RX Desc Base Low Queue 2 - RW */
1056#define E1000_82542_RDBAH2 0x02A04 /* RX Desc Base High Queue 2 - RW */
1057#define E1000_82542_RDLEN2 0x02A08 /* RX Desc Length Queue 2 - RW */
1058#define E1000_82542_RDH2 0x02A10 /* RX Desc Head Queue 2 - RW */
1059#define E1000_82542_RDT2 0x02A18 /* RX Desc Tail Queue 2 - RW */
868d5309
MC		 1060#define E1000_82542_RDTR1 0x00130
1061#define E1000_82542_RDBAL1 0x00138
1062#define E1000_82542_RDBAH1 0x0013C
1063#define E1000_82542_RDLEN1 0x00140
1064#define E1000_82542_RDH1 0x00148
1065#define E1000_82542_RDT1 0x00150
1da177e4
LT		 1066#define E1000_82542_FCRTH 0x00160
1067#define E1000_82542_FCRTL 0x00168
1068#define E1000_82542_FCTTV E1000_FCTTV
1069#define E1000_82542_TXCW E1000_TXCW
1070#define E1000_82542_RXCW E1000_RXCW
1071#define E1000_82542_MTA 0x00200
1072#define E1000_82542_TCTL E1000_TCTL
6418ecc6 1073#define E1000_82542_TCTL_EXT E1000_TCTL_EXT
1da177e4
LT		 1074#define E1000_82542_TIPG E1000_TIPG
1075#define E1000_82542_TDBAL 0x00420
1076#define E1000_82542_TDBAH 0x00424
1077#define E1000_82542_TDLEN 0x00428
1078#define E1000_82542_TDH 0x00430
1079#define E1000_82542_TDT 0x00438
1080#define E1000_82542_TIDV 0x00440
1081#define E1000_82542_TBT E1000_TBT
1082#define E1000_82542_AIT E1000_AIT
1083#define E1000_82542_VFTA 0x00600
1084#define E1000_82542_LEDCTL E1000_LEDCTL
1085#define E1000_82542_PBA E1000_PBA
2d7edb92
MC		 1086#define E1000_82542_PBS E1000_PBS
1087#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1088#define E1000_82542_EEARBC E1000_EEARBC
1089#define E1000_82542_FLASHT E1000_FLASHT
1090#define E1000_82542_EEWR E1000_EEWR
1091#define E1000_82542_FLSWCTL E1000_FLSWCTL
1092#define E1000_82542_FLSWDATA E1000_FLSWDATA
1093#define E1000_82542_FLSWCNT E1000_FLSWCNT
1094#define E1000_82542_FLOP E1000_FLOP
1095#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1096#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
d37ea5d5 1097#define E1000_82542_PHY_CTRL E1000_PHY_CTRL
2d7edb92 1098#define E1000_82542_ERT E1000_ERT
1da177e4 1099#define E1000_82542_RXDCTL E1000_RXDCTL
d37ea5d5 1100#define E1000_82542_RXDCTL1 E1000_RXDCTL1
1da177e4
LT		 1101#define E1000_82542_RADV E1000_RADV
1102#define E1000_82542_RSRPD E1000_RSRPD
1103#define E1000_82542_TXDMAC E1000_TXDMAC
d37ea5d5 1104#define E1000_82542_KABGTXD E1000_KABGTXD
1da177e4
LT		 1105#define E1000_82542_TDFHS E1000_TDFHS
1106#define E1000_82542_TDFTS E1000_TDFTS
1107#define E1000_82542_TDFPC E1000_TDFPC
1108#define E1000_82542_TXDCTL E1000_TXDCTL
1109#define E1000_82542_TADV E1000_TADV
1110#define E1000_82542_TSPMT E1000_TSPMT
1111#define E1000_82542_CRCERRS E1000_CRCERRS
1112#define E1000_82542_ALGNERRC E1000_ALGNERRC
1113#define E1000_82542_SYMERRS E1000_SYMERRS
1114#define E1000_82542_RXERRC E1000_RXERRC
1115#define E1000_82542_MPC E1000_MPC
1116#define E1000_82542_SCC E1000_SCC
1117#define E1000_82542_ECOL E1000_ECOL
1118#define E1000_82542_MCC E1000_MCC
1119#define E1000_82542_LATECOL E1000_LATECOL
1120#define E1000_82542_COLC E1000_COLC
1121#define E1000_82542_DC E1000_DC
1122#define E1000_82542_TNCRS E1000_TNCRS
1123#define E1000_82542_SEC E1000_SEC
1124#define E1000_82542_CEXTERR E1000_CEXTERR
1125#define E1000_82542_RLEC E1000_RLEC
1126#define E1000_82542_XONRXC E1000_XONRXC
1127#define E1000_82542_XONTXC E1000_XONTXC
1128#define E1000_82542_XOFFRXC E1000_XOFFRXC
1129#define E1000_82542_XOFFTXC E1000_XOFFTXC
1130#define E1000_82542_FCRUC E1000_FCRUC
1131#define E1000_82542_PRC64 E1000_PRC64
1132#define E1000_82542_PRC127 E1000_PRC127
1133#define E1000_82542_PRC255 E1000_PRC255
1134#define E1000_82542_PRC511 E1000_PRC511
1135#define E1000_82542_PRC1023 E1000_PRC1023
1136#define E1000_82542_PRC1522 E1000_PRC1522
1137#define E1000_82542_GPRC E1000_GPRC
1138#define E1000_82542_BPRC E1000_BPRC
1139#define E1000_82542_MPRC E1000_MPRC
1140#define E1000_82542_GPTC E1000_GPTC
1141#define E1000_82542_GORCL E1000_GORCL
1142#define E1000_82542_GORCH E1000_GORCH
1143#define E1000_82542_GOTCL E1000_GOTCL
1144#define E1000_82542_GOTCH E1000_GOTCH
1145#define E1000_82542_RNBC E1000_RNBC
1146#define E1000_82542_RUC E1000_RUC
1147#define E1000_82542_RFC E1000_RFC
1148#define E1000_82542_ROC E1000_ROC
1149#define E1000_82542_RJC E1000_RJC
1150#define E1000_82542_MGTPRC E1000_MGTPRC
1151#define E1000_82542_MGTPDC E1000_MGTPDC
1152#define E1000_82542_MGTPTC E1000_MGTPTC
1153#define E1000_82542_TORL E1000_TORL
1154#define E1000_82542_TORH E1000_TORH
1155#define E1000_82542_TOTL E1000_TOTL
1156#define E1000_82542_TOTH E1000_TOTH
1157#define E1000_82542_TPR E1000_TPR
1158#define E1000_82542_TPT E1000_TPT
1159#define E1000_82542_PTC64 E1000_PTC64
1160#define E1000_82542_PTC127 E1000_PTC127
1161#define E1000_82542_PTC255 E1000_PTC255
1162#define E1000_82542_PTC511 E1000_PTC511
1163#define E1000_82542_PTC1023 E1000_PTC1023
1164#define E1000_82542_PTC1522 E1000_PTC1522
1165#define E1000_82542_MPTC E1000_MPTC
1166#define E1000_82542_BPTC E1000_BPTC
1167#define E1000_82542_TSCTC E1000_TSCTC
1168#define E1000_82542_TSCTFC E1000_TSCTFC
1169#define E1000_82542_RXCSUM E1000_RXCSUM
1170#define E1000_82542_WUC E1000_WUC
1171#define E1000_82542_WUFC E1000_WUFC
1172#define E1000_82542_WUS E1000_WUS
1173#define E1000_82542_MANC E1000_MANC
1174#define E1000_82542_IPAV E1000_IPAV
1175#define E1000_82542_IP4AT E1000_IP4AT
1176#define E1000_82542_IP6AT E1000_IP6AT
1177#define E1000_82542_WUPL E1000_WUPL
1178#define E1000_82542_WUPM E1000_WUPM
1179#define E1000_82542_FFLT E1000_FFLT
1180#define E1000_82542_TDFH 0x08010
1181#define E1000_82542_TDFT 0x08018
1182#define E1000_82542_FFMT E1000_FFMT
1183#define E1000_82542_FFVT E1000_FFVT
1184#define E1000_82542_HOST_IF E1000_HOST_IF
2d7edb92
MC		 1185#define E1000_82542_IAM E1000_IAM
1186#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1187#define E1000_82542_PSRCTL E1000_PSRCTL
1188#define E1000_82542_RAID E1000_RAID
1189#define E1000_82542_TARC0 E1000_TARC0
1190#define E1000_82542_TDBAL1 E1000_TDBAL1
1191#define E1000_82542_TDBAH1 E1000_TDBAH1
1192#define E1000_82542_TDLEN1 E1000_TDLEN1
1193#define E1000_82542_TDH1 E1000_TDH1
1194#define E1000_82542_TDT1 E1000_TDT1
1195#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1196#define E1000_82542_TARC1 E1000_TARC1
1197#define E1000_82542_RFCTL E1000_RFCTL
1198#define E1000_82542_GCR E1000_GCR
1199#define E1000_82542_GSCL_1 E1000_GSCL_1
1200#define E1000_82542_GSCL_2 E1000_GSCL_2
1201#define E1000_82542_GSCL_3 E1000_GSCL_3
1202#define E1000_82542_GSCL_4 E1000_GSCL_4
1203#define E1000_82542_FACTPS E1000_FACTPS
1204#define E1000_82542_SWSM E1000_SWSM
1205#define E1000_82542_FWSM E1000_FWSM
1206#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1207#define E1000_82542_IAC E1000_IAC
1208#define E1000_82542_ICRXPTC E1000_ICRXPTC
1209#define E1000_82542_ICRXATC E1000_ICRXATC
1210#define E1000_82542_ICTXPTC E1000_ICTXPTC
1211#define E1000_82542_ICTXATC E1000_ICTXATC
1212#define E1000_82542_ICTXQEC E1000_ICTXQEC
1213#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1214#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1215#define E1000_82542_ICRXOC E1000_ICRXOC
1216#define E1000_82542_HICR E1000_HICR
1da177e4 1217
868d5309
MC		 1218#define E1000_82542_CPUVEC E1000_CPUVEC
1219#define E1000_82542_MRQC E1000_MRQC
1220#define E1000_82542_RETA E1000_RETA
1221#define E1000_82542_RSSRK E1000_RSSRK
1222#define E1000_82542_RSSIM E1000_RSSIM
1223#define E1000_82542_RSSIR E1000_RSSIR
6418ecc6
JK		 1224#define E1000_82542_KUMCTRLSTA E1000_KUMCTRLSTA
1225#define E1000_82542_SW_FW_SYNC E1000_SW_FW_SYNC
868d5309 1226
1da177e4
LT		 1227/* Statistics counters collected by the MAC */
1228struct e1000_hw_stats {
120a5d0d
JB		 1229 u64 crcerrs;
1230 u64 algnerrc;
1231 u64 symerrs;
1232 u64 rxerrc;
1233 u64 txerrc;
1234 u64 mpc;
1235 u64 scc;
1236 u64 ecol;
1237 u64 mcc;
1238 u64 latecol;
1239 u64 colc;
1240 u64 dc;
1241 u64 tncrs;
1242 u64 sec;
1243 u64 cexterr;
1244 u64 rlec;
1245 u64 xonrxc;
1246 u64 xontxc;
1247 u64 xoffrxc;
1248 u64 xofftxc;
1249 u64 fcruc;
1250 u64 prc64;
1251 u64 prc127;
1252 u64 prc255;
1253 u64 prc511;
1254 u64 prc1023;
1255 u64 prc1522;
1256 u64 gprc;
1257 u64 bprc;
1258 u64 mprc;
1259 u64 gptc;
1260 u64 gorcl;
1261 u64 gorch;
1262 u64 gotcl;
1263 u64 gotch;
1264 u64 rnbc;
1265 u64 ruc;
1266 u64 rfc;
1267 u64 roc;
1268 u64 rlerrc;
1269 u64 rjc;
1270 u64 mgprc;
1271 u64 mgpdc;
1272 u64 mgptc;
1273 u64 torl;
1274 u64 torh;
1275 u64 totl;
1276 u64 toth;
1277 u64 tpr;
1278 u64 tpt;
1279 u64 ptc64;
1280 u64 ptc127;
1281 u64 ptc255;
1282 u64 ptc511;
1283 u64 ptc1023;
1284 u64 ptc1522;
1285 u64 mptc;
1286 u64 bptc;
1287 u64 tsctc;
1288 u64 tsctfc;
1289 u64 iac;
1290 u64 icrxptc;
1291 u64 icrxatc;
1292 u64 ictxptc;
1293 u64 ictxatc;
1294 u64 ictxqec;
1295 u64 ictxqmtc;
1296 u64 icrxdmtc;
1297 u64 icrxoc;
1da177e4
LT		 1298};
1299
1300/* Structure containing variables used by the shared code (e1000_hw.c) */
1301struct e1000_hw {
120a5d0d
JB		 1302 u8 __iomem *hw_addr;
1303 u8 __iomem *flash_address;
1304 e1000_mac_type mac_type;
1305 e1000_phy_type phy_type;
1306 u32 phy_init_script;
1307 e1000_media_type media_type;
1308 void *back;
1309 struct e1000_shadow_ram *eeprom_shadow_ram;
1310 u32 flash_bank_size;
1311 u32 flash_base_addr;
1312 e1000_fc_type fc;
1313 e1000_bus_speed bus_speed;
1314 e1000_bus_width bus_width;
1315 e1000_bus_type bus_type;
bd2371eb 1316 struct e1000_eeprom_info eeprom;
120a5d0d
JB		 1317 e1000_ms_type master_slave;
1318 e1000_ms_type original_master_slave;
1319 e1000_ffe_config ffe_config_state;
1320 u32 asf_firmware_present;
1321 u32 eeprom_semaphore_present;
1322 unsigned long io_base;
1323 u32 phy_id;
1324 u32 phy_revision;
1325 u32 phy_addr;
1326 u32 original_fc;
1327 u32 txcw;
1328 u32 autoneg_failed;
1329 u32 max_frame_size;
1330 u32 min_frame_size;
1331 u32 mc_filter_type;
1332 u32 num_mc_addrs;
1333 u32 collision_delta;
1334 u32 tx_packet_delta;
1335 u32 ledctl_default;
1336 u32 ledctl_mode1;
1337 u32 ledctl_mode2;
1338 bool tx_pkt_filtering;
bd2371eb 1339 struct e1000_host_mng_dhcp_cookie mng_cookie;
120a5d0d
JB		 1340 u16 phy_spd_default;
1341 u16 autoneg_advertised;
1342 u16 pci_cmd_word;
1343 u16 fc_high_water;
1344 u16 fc_low_water;
1345 u16 fc_pause_time;
1346 u16 current_ifs_val;
1347 u16 ifs_min_val;
1348 u16 ifs_max_val;
1349 u16 ifs_step_size;
1350 u16 ifs_ratio;
1351 u16 device_id;
1352 u16 vendor_id;
1353 u16 subsystem_id;
1354 u16 subsystem_vendor_id;
1355 u8 revision_id;
1356 u8 autoneg;
1357 u8 mdix;
1358 u8 forced_speed_duplex;
1359 u8 wait_autoneg_complete;
1360 u8 dma_fairness;
1361 u8 mac_addr[NODE_ADDRESS_SIZE];
1362 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
1363 bool disable_polarity_correction;
1364 bool speed_downgraded;
1365 e1000_smart_speed smart_speed;
1366 e1000_dsp_config dsp_config_state;
1367 bool get_link_status;
1368 bool serdes_has_link;
1369 bool tbi_compatibility_en;
1370 bool tbi_compatibility_on;
1371 bool laa_is_present;
1372 bool phy_reset_disable;
1373 bool initialize_hw_bits_disable;
1374 bool fc_send_xon;
1375 bool fc_strict_ieee;
1376 bool report_tx_early;
1377 bool adaptive_ifs;
1378 bool ifs_params_forced;
1379 bool in_ifs_mode;
1380 bool mng_reg_access_disabled;
1381 bool leave_av_bit_off;
1382 bool bad_tx_carr_stats_fd;
1383 bool has_smbus;
1da177e4
LT		 1384};
1385
120a5d0d
JB		 1386#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1387#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
1388#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1389#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1390#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1391#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1392#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1393#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1da177e4
LT		 1394/* Register Bit Masks */
1395/* Device Control */
120a5d0d
JB		 1396#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1397#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1398#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
1399#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1400#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1401#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1402#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1403#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1404#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1405#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1406#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1407#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1408#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1409#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1410#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1411#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1412#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
1413#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
1414#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1415#define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
1416#define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
1417#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1418#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1419#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1420#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1421#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1422#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1423#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1424#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1425#define E1000_CTRL_RST 0x04000000 /* Global reset */
1426#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1427#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1428#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1429#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1430#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1431#define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */
1da177e4
LT		 1432
1433/* Device Status */
120a5d0d
JB		 1434#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1435#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1436#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
2d7edb92 1437#define E1000_STATUS_FUNC_SHIFT 2
120a5d0d
JB		 1438#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1439#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1440#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1441#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1da177e4 1442#define E1000_STATUS_SPEED_MASK 0x000000C0
120a5d0d
JB		 1443#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1444#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1445#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1446#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion
1447 by EEPROM/Flash */
1448#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
1449#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1450#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
1451#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1452#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1453#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1454#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1455#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1456#define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */
1457#define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */
1458#define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */
1459#define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
1460#define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */
1461#define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
6418ecc6
JK		 1462#define E1000_STATUS_FUSE_8 0x04000000
1463#define E1000_STATUS_FUSE_9 0x08000000
120a5d0d
JB		 1464#define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */
1465#define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */
1da177e4 1466
120a5d0d
JB		 1467/* Constants used to interpret the masked PCI-X bus speed. */
1468#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1469#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1470#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1da177e4
LT		 1471
1472/* EEPROM/Flash Control */
120a5d0d
JB		 1473#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1474#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1475#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1476#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1da177e4 1477#define E1000_EECD_FWE_MASK 0x00000030
120a5d0d
JB		 1478#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1479#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1da177e4 1480#define E1000_EECD_FWE_SHIFT 4
120a5d0d
JB		 1481#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1482#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1483#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1484#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1485#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1486 * (0-small, 1-large) */
1487#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1da177e4 1488#ifndef E1000_EEPROM_GRANT_ATTEMPTS
120a5d0d 1489#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1da177e4 1490#endif
120a5d0d
JB		 1491#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1492#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
2d7edb92 1493#define E1000_EECD_SIZE_EX_SHIFT 11
120a5d0d
JB		 1494#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1495#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1496#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1497#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1498#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1499#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1500#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
fd803241 1501#define E1000_EECD_SECVAL_SHIFT 22
2d7edb92
MC		 1502#define E1000_STM_OPCODE 0xDB00
1503#define E1000_HICR_FW_RESET 0xC0
1da177e4 1504
d37ea5d5 1505#define E1000_SHADOW_RAM_WORDS 2048
2df7d59f
JK		 1506#define E1000_ICH_NVM_SIG_WORD 0x13
1507#define E1000_ICH_NVM_SIG_MASK 0xC0
d37ea5d5 1508
1da177e4 1509/* EEPROM Read */
120a5d0d
JB		 1510#define E1000_EERD_START 0x00000001 /* Start Read */
1511#define E1000_EERD_DONE 0x00000010 /* Read Done */
1da177e4 1512#define E1000_EERD_ADDR_SHIFT 8
120a5d0d 1513#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1da177e4 1514#define E1000_EERD_DATA_SHIFT 16
120a5d0d 1515#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1da177e4
LT		 1516
1517/* SPI EEPROM Status Register */
1518#define EEPROM_STATUS_RDY_SPI 0x01
1519#define EEPROM_STATUS_WEN_SPI 0x02
1520#define EEPROM_STATUS_BP0_SPI 0x04
1521#define EEPROM_STATUS_BP1_SPI 0x08
1522#define EEPROM_STATUS_WPEN_SPI 0x80
1523
1524/* Extended Device Control */
120a5d0d
JB		 1525#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1526#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1da177e4 1527#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
120a5d0d
JB		 1528#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1529#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1530#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1531#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1da177e4 1532#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
120a5d0d
JB		 1533#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1534#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1535#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1536#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1537#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1538#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1539#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1540#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1541#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1542#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
1543#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
1da177e4
LT		 1544#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1545#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1546#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
35574764 1547#define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000
6418ecc6 1548#define E1000_CTRL_EXT_LINK_MODE_SERDES 0x00C00000
35574764 1549#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
1da177e4
LT		 1550#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1551#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1552#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1553#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1554#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
120a5d0d
JB		 1555#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
1556#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1557#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
1558#define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */
1559#define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */
6418ecc6 1560#define E1000_CTRL_EXT_GHOST_PAREN 0x40000000
1da177e4
LT		 1561
1562/* MDI Control */
1563#define E1000_MDIC_DATA_MASK 0x0000FFFF
1564#define E1000_MDIC_REG_MASK 0x001F0000
1565#define E1000_MDIC_REG_SHIFT 16
1566#define E1000_MDIC_PHY_MASK 0x03E00000
1567#define E1000_MDIC_PHY_SHIFT 21
1568#define E1000_MDIC_OP_WRITE 0x04000000
1569#define E1000_MDIC_OP_READ 0x08000000
1570#define E1000_MDIC_READY 0x10000000
1571#define E1000_MDIC_INT_EN 0x20000000
1572#define E1000_MDIC_ERROR 0x40000000
1573
6418ecc6
JK		 1574#define E1000_KUMCTRLSTA_MASK 0x0000FFFF
1575#define E1000_KUMCTRLSTA_OFFSET 0x001F0000
1576#define E1000_KUMCTRLSTA_OFFSET_SHIFT 16
1577#define E1000_KUMCTRLSTA_REN 0x00200000
1578
1579#define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000
1580#define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001
1581#define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002
1582#define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003
1583#define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004
1584#define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009
1585#define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010
1586#define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E
1587#define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F
1588
1589/* FIFO Control */
1590#define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008
1591#define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800
1592
1593/* In-Band Control */
d37ea5d5 1594#define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500
6418ecc6
JK		 1595#define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010
1596
1597/* Half-Duplex Control */
1598#define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004
1599#define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000
1600
d37ea5d5
AK		 1601#define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E
1602
1603#define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000
1604#define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000
1605
1606#define E1000_KUMCTRLSTA_K0S_100_EN 0x2000
1607#define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000
1608#define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003
1609
1610#define E1000_KABGTXD_BGSQLBIAS 0x00050000
1611
1612#define E1000_PHY_CTRL_SPD_EN 0x00000001
1613#define E1000_PHY_CTRL_D0A_LPLU 0x00000002
1614#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004
1615#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
1616#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040
1617#define E1000_PHY_CTRL_B2B_EN 0x00000080
1618
1da177e4
LT		 1619/* LED Control */
1620#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1621#define E1000_LEDCTL_LED0_MODE_SHIFT 0
2d7edb92 1622#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
1da177e4
LT		 1623#define E1000_LEDCTL_LED0_IVRT 0x00000040
1624#define E1000_LEDCTL_LED0_BLINK 0x00000080
1625#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1626#define E1000_LEDCTL_LED1_MODE_SHIFT 8
2d7edb92 1627#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
1da177e4
LT		 1628#define E1000_LEDCTL_LED1_IVRT 0x00004000
1629#define E1000_LEDCTL_LED1_BLINK 0x00008000
1630#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1631#define E1000_LEDCTL_LED2_MODE_SHIFT 16
2d7edb92 1632#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
1da177e4
LT		 1633#define E1000_LEDCTL_LED2_IVRT 0x00400000
1634#define E1000_LEDCTL_LED2_BLINK 0x00800000
1635#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1636#define E1000_LEDCTL_LED3_MODE_SHIFT 24
868d5309 1637#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
1da177e4
LT		 1638#define E1000_LEDCTL_LED3_IVRT 0x40000000
1639#define E1000_LEDCTL_LED3_BLINK 0x80000000
1640
1641#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1642#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1643#define E1000_LEDCTL_MODE_LINK_UP 0x2
1644#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1645#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1646#define E1000_LEDCTL_MODE_LINK_10 0x5
1647#define E1000_LEDCTL_MODE_LINK_100 0x6
1648#define E1000_LEDCTL_MODE_LINK_1000 0x7
1649#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1650#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1651#define E1000_LEDCTL_MODE_COLLISION 0xA
1652#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1653#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1654#define E1000_LEDCTL_MODE_PAUSED 0xD
1655#define E1000_LEDCTL_MODE_LED_ON 0xE
1656#define E1000_LEDCTL_MODE_LED_OFF 0xF
1657
1658/* Receive Address */
120a5d0d 1659#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1da177e4
LT		 1660
1661/* Interrupt Cause Read */
120a5d0d
JB		 1662#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1663#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1664#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1665#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1666#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1667#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1668#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1669#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1670#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1671#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1672#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1673#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1674#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1da177e4
LT		 1675#define E1000_ICR_TXD_LOW 0x00008000
1676#define E1000_ICR_SRPD 0x00010000
120a5d0d
JB		 1677#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1678#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1679#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1680#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
1681#define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
1682#define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
1683#define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */
1684#define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */
1685#define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
1686#define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
1687#define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */
1688#define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */
1689#define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */
1690#define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */
1da177e4
LT		 1691
1692/* Interrupt Cause Set */
120a5d0d
JB		 1693#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1694#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1695#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1696#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1697#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1698#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1699#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1700#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1701#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1702#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1703#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1704#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1705#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1da177e4
LT		 1706#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1707#define E1000_ICS_SRPD E1000_ICR_SRPD
120a5d0d
JB		 1708#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1709#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1710#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1711#define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1712#define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1713#define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1714#define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1715#define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1716#define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
d37ea5d5
AK		 1717#define E1000_ICS_DSW E1000_ICR_DSW
1718#define E1000_ICS_PHYINT E1000_ICR_PHYINT
1719#define E1000_ICS_EPRST E1000_ICR_EPRST
1da177e4
LT		 1720
1721/* Interrupt Mask Set */
120a5d0d
JB		 1722#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1723#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1724#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1725#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1726#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1727#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1728#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1729#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1730#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1731#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1732#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1733#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1734#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1da177e4
LT		 1735#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1736#define E1000_IMS_SRPD E1000_ICR_SRPD
120a5d0d
JB		 1737#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1738#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1739#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
1740#define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1741#define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1742#define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1743#define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1744#define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1745#define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
d37ea5d5
AK		 1746#define E1000_IMS_DSW E1000_ICR_DSW
1747#define E1000_IMS_PHYINT E1000_ICR_PHYINT
1748#define E1000_IMS_EPRST E1000_ICR_EPRST
1da177e4
LT		 1749
1750/* Interrupt Mask Clear */
120a5d0d
JB		 1751#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1752#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1753#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1754#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1755#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1756#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1757#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1758#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1759#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1760#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1761#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1762#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1763#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1da177e4
LT		 1764#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1765#define E1000_IMC_SRPD E1000_ICR_SRPD
120a5d0d
JB		 1766#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1767#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1768#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
1769#define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
1770#define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
1771#define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */
1772#define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */
1773#define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
1774#define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
d37ea5d5
AK		 1775#define E1000_IMC_DSW E1000_ICR_DSW
1776#define E1000_IMC_PHYINT E1000_ICR_PHYINT
1777#define E1000_IMC_EPRST E1000_ICR_EPRST
1da177e4
LT		 1778
1779/* Receive Control */
120a5d0d
JB		 1780#define E1000_RCTL_RST 0x00000001 /* Software reset */
1781#define E1000_RCTL_EN 0x00000002 /* enable */
1782#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1783#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1784#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1785#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1786#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1787#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1788#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1789#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
1790#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1791#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
1792#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1793#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1794#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1795#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1796#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1797#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1798#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1799#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1800#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1801#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1da177e4 1802/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
120a5d0d
JB		 1803#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1804#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1805#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1806#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1da177e4 1807/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
120a5d0d
JB		 1808#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1809#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1810#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1811#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1812#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1813#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1814#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1815#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1816#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1817#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
1818#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1819#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
2d7edb92
MC		 1820
1821/* Use byte values for the following shift parameters
1822 * Usage:
1823 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1824 * E1000_PSRCTL_BSIZE0_MASK) |
1825 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1826 * E1000_PSRCTL_BSIZE1_MASK) |
1827 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1828 * E1000_PSRCTL_BSIZE2_MASK) |
1829 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1830 * E1000_PSRCTL_BSIZE3_MASK))
1831 * where value0 = [128..16256], default=256
1832 * value1 = [1024..64512], default=4096
1833 * value2 = [0..64512], default=4096
1834 * value3 = [0..64512], default=0
1835 */
76c224bc 1836
2d7edb92
MC		 1837#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1838#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1839#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1840#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1841
120a5d0d
JB		 1842#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1843#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1844#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1845#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
1da177e4 1846
6418ecc6
JK		 1847/* SW_W_SYNC definitions */
1848#define E1000_SWFW_EEP_SM 0x0001
1849#define E1000_SWFW_PHY0_SM 0x0002
1850#define E1000_SWFW_PHY1_SM 0x0004
1851#define E1000_SWFW_MAC_CSR_SM 0x0008
1852
1da177e4 1853/* Receive Descriptor */
120a5d0d
JB		 1854#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1855#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1856#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1857#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1858#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1da177e4
LT		 1859
1860/* Flow Control */
120a5d0d
JB		 1861#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1862#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1863#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1864#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1da177e4 1865
2d7edb92
MC		 1866/* Header split receive */
1867#define E1000_RFCTL_ISCSI_DIS 0x00000001
1868#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1869#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1870#define E1000_RFCTL_NFSW_DIS 0x00000040
1871#define E1000_RFCTL_NFSR_DIS 0x00000080
1872#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1873#define E1000_RFCTL_NFS_VER_SHIFT 8
1874#define E1000_RFCTL_IPV6_DIS 0x00000400
1875#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1876#define E1000_RFCTL_ACK_DIS 0x00001000
1877#define E1000_RFCTL_ACKD_DIS 0x00002000
1878#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1879#define E1000_RFCTL_EXTEN 0x00008000
1880#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1881#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1882
1da177e4 1883/* Receive Descriptor Control */
120a5d0d
JB		 1884#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1885#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1886#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1887#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1da177e4
LT		 1888
1889/* Transmit Descriptor Control */
120a5d0d
JB		 1890#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
1891#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
1892#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
1893#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1894#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1895#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
1896#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1897 still to be processed. */
1da177e4 1898/* Transmit Configuration Word */
120a5d0d
JB		 1899#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1900#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1901#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1902#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1903#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1904#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1905#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1906#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1907#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1908#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1da177e4
LT		 1909
1910/* Receive Configuration Word */
120a5d0d
JB		 1911#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1912#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1913#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1914#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1915#define E1000_RXCW_C 0x20000000 /* Receive config */
1916#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1917#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1da177e4
LT		 1918
1919/* Transmit Control */
120a5d0d
JB		 1920#define E1000_TCTL_RST 0x00000001 /* software reset */
1921#define E1000_TCTL_EN 0x00000002 /* enable tx */
1922#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1923#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1924#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1925#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1926#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1927#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1928#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1929#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
1930#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
6418ecc6 1931/* Extended Transmit Control */
120a5d0d
JB		 1932#define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */
1933#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
6418ecc6 1934
1da177e4 1935/* Receive Checksum Control */
120a5d0d
JB		 1936#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1937#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1938#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1939#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
1940#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1941#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
2d7edb92 1942
868d5309
MC		 1943/* Multiple Receive Queue Control */
1944#define E1000_MRQC_ENABLE_MASK 0x00000003
1945#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
1946#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
1947#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1948#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1949#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
d37ea5d5 1950#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
868d5309
MC		 1951#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1952#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
d37ea5d5 1953#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1da177e4
LT		 1954
1955/* Definitions for power management and wakeup registers */
1956/* Wake Up Control */
120a5d0d
JB		 1957#define E1000_WUC_APME 0x00000001 /* APM Enable */
1958#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1959#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1960#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1961#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1da177e4
LT		 1962
1963/* Wake Up Filter Control */
120a5d0d
JB		 1964#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1965#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1966#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1967#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1968#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1969#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1970#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1971#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
1972#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1973#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1974#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1975#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1976#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1977#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1978#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1979#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1da177e4
LT		 1980
1981/* Wake Up Status */
120a5d0d
JB		 1982#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1983#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1984#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1985#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1986#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1987#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1988#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1989#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1990#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1991#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1992#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1993#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1994#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1da177e4
LT		 1995
1996/* Management Control */
120a5d0d
JB		 1997#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1998#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1999#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
2000#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
2001#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
2002#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
2003#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
2004#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
2005#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
2006#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
2007 * Filtering */
2008#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
2009#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
2010#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
2011#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2012#define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */
2013#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
2014#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
2015 * filtering */
2016#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
2017 * memory */
2018#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
2019 * filtering */
2020#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
2021#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
2022#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
2023#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
2024#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
2025#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
2026#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
2027#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
2028
2029#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
2030#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1da177e4 2031
2d7edb92 2032/* SW Semaphore Register */
120a5d0d
JB		 2033#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
2034#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
2035#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
2036#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
2d7edb92
MC		 2037
2038/* FW Semaphore Register */
120a5d0d 2039#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
2d7edb92 2040#define E1000_FWSM_MODE_SHIFT 1
120a5d0d 2041#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
2d7edb92 2042
120a5d0d
JB		 2043#define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */
2044#define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */
2045#define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */
d37ea5d5 2046#define E1000_FWSM_SKUEL_SHIFT 29
120a5d0d
JB		 2047#define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */
2048#define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */
2049#define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */
2050#define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */
d37ea5d5 2051
2d7edb92 2052/* FFLT Debug Register */
120a5d0d 2053#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
2d7edb92
MC		 2054
2055typedef enum {
120a5d0d
JB		 2056 e1000_mng_mode_none = 0,
2057 e1000_mng_mode_asf,
2058 e1000_mng_mode_pt,
2059 e1000_mng_mode_ipmi,
2060 e1000_mng_mode_host_interface_only
2d7edb92
MC		 2061} e1000_mng_mode;
2062
120a5d0d
JB		 2063/* Host Interface Control Register */
2064#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
2065#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
2066 * to put command in RAM */
2067#define E1000_HICR_SV 0x00000004 /* Status Validity */
2068#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
2d7edb92
MC		 2069
2070/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
120a5d0d
JB		 2071#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
2072#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
2073#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
2074#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
2d7edb92
MC		 2075
2076struct e1000_host_command_header {
120a5d0d
JB		 2077 u8 command_id;
2078 u8 command_length;
2079 u8 command_options; /* I/F bits for command, status for return */
2080 u8 checksum;
2d7edb92
MC		 2081};
2082struct e1000_host_command_info {
120a5d0d
JB		 2083 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
2084 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
2d7edb92
MC		 2085};
2086
2087/* Host SMB register #0 */
120a5d0d
JB		 2088#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
2089#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
2090#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
2091#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
2d7edb92
MC		 2092
2093/* Host SMB register #1 */
2094#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
2095#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
2096#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
2097#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
2098
2099/* FW Status Register */
120a5d0d 2100#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
2d7edb92 2101
1da177e4 2102/* Wake Up Packet Length */
120a5d0d 2103#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1da177e4
LT		 2104
2105#define E1000_MDALIGN 4096
2106
8fc897b0 2107/* PCI-Ex registers*/
b7ee49db
JK		 2108
2109/* PCI-Ex Control Register */
0f15a8fa
JK		 2110#define E1000_GCR_RXD_NO_SNOOP 0x00000001
2111#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002
2112#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004
2113#define E1000_GCR_TXD_NO_SNOOP 0x00000008
2114#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010
2115#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020
2116
2117#define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \
2118 E1000_GCR_RXDSCW_NO_SNOOP | \
2119 E1000_GCR_RXDSCR_NO_SNOOP | \
2120 E1000_GCR_TXD_NO_SNOOP | \
2121 E1000_GCR_TXDSCW_NO_SNOOP | \
2122 E1000_GCR_TXDSCR_NO_SNOOP)
b7ee49db 2123
d37ea5d5
AK		 2124#define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL
2125
868d5309 2126#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2d7edb92
MC		 2127/* Function Active and Power State to MNG */
2128#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
2129#define E1000_FACTPS_LAN0_VALID 0x00000004
2130#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
2131#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
2132#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
2133#define E1000_FACTPS_LAN1_VALID 0x00000100
2134#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
2135#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
2136#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
2137#define E1000_FACTPS_IDE_ENABLE 0x00004000
2138#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
2139#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
2140#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
2141#define E1000_FACTPS_SP_ENABLE 0x00100000
2142#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
2143#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
2144#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
2145#define E1000_FACTPS_IPMI_ENABLE 0x04000000
2146#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
2147#define E1000_FACTPS_MNGCG 0x20000000
2148#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
2149#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
2150
caeccb68
JK		 2151/* PCI-Ex Config Space */
2152#define PCI_EX_LINK_STATUS 0x12
2153#define PCI_EX_LINK_WIDTH_MASK 0x3F0
2154#define PCI_EX_LINK_WIDTH_SHIFT 4
2155
1da177e4 2156/* EEPROM Commands - Microwire */
120a5d0d
JB		 2157#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
2158#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
2159#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
2160#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
2161#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */
1da177e4
LT		 2162
2163/* EEPROM Commands - SPI */
120a5d0d
JB		 2164#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2165#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
2166#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
2167#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
2168#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
2169#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
2170#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
2171#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
2172#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2173#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2174#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1da177e4
LT		 2175
2176/* EEPROM Size definitions */
2d7edb92
MC		 2177#define EEPROM_WORD_SIZE_SHIFT 6
2178#define EEPROM_SIZE_SHIFT 10
1da177e4
LT		 2179#define EEPROM_SIZE_MASK 0x1C00
2180
2181/* EEPROM Word Offsets */
2182#define EEPROM_COMPAT 0x0003
2183#define EEPROM_ID_LED_SETTINGS 0x0004
868d5309 2184#define EEPROM_VERSION 0x0005
120a5d0d 2185#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
1da177e4
LT		 2186#define EEPROM_PHY_CLASS_WORD 0x0007
2187#define EEPROM_INIT_CONTROL1_REG 0x000A
2188#define EEPROM_INIT_CONTROL2_REG 0x000F
d37ea5d5 2189#define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
1da177e4 2190#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
85b22eb6 2191#define EEPROM_INIT_3GIO_3 0x001A
d37ea5d5 2192#define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
1da177e4
LT		 2193#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2194#define EEPROM_CFG 0x0012
2195#define EEPROM_FLASH_VERSION 0x0032
2196#define EEPROM_CHECKSUM_REG 0x003F
2197
120a5d0d
JB		 2198#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2199#define E1000_EEPROM_CFG_DONE_PORT_1 0x00080000 /* ...for second port */
868d5309 2200
1da177e4
LT		 2201/* Word definitions for ID LED Settings */
2202#define ID_LED_RESERVED_0000 0x0000
2203#define ID_LED_RESERVED_FFFF 0xFFFF
2204#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2205 (ID_LED_OFF1_OFF2 << 8) | \
2206 (ID_LED_DEF1_DEF2 << 4) | \
2207 (ID_LED_DEF1_DEF2))
2208#define ID_LED_DEF1_DEF2 0x1
2209#define ID_LED_DEF1_ON2 0x2
2210#define ID_LED_DEF1_OFF2 0x3
2211#define ID_LED_ON1_DEF2 0x4
2212#define ID_LED_ON1_ON2 0x5
2213#define ID_LED_ON1_OFF2 0x6
2214#define ID_LED_OFF1_DEF2 0x7
2215#define ID_LED_OFF1_ON2 0x8
2216#define ID_LED_OFF1_OFF2 0x9
2217
2218#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2219#define IGP_ACTIVITY_LED_ENABLE 0x0300
2220#define IGP_LED3_MODE 0x07000000
2221
1da177e4
LT		 2222/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2223#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2224
2225/* Mask bit for PHY class in Word 7 of the EEPROM */
2226#define EEPROM_PHY_CLASS_A 0x8000
2227
2228/* Mask bits for fields in Word 0x0a of the EEPROM */
2229#define EEPROM_WORD0A_ILOS 0x0010
2230#define EEPROM_WORD0A_SWDPIO 0x01E0
2231#define EEPROM_WORD0A_LRST 0x0200
2232#define EEPROM_WORD0A_FD 0x0400
2233#define EEPROM_WORD0A_66MHZ 0x0800
2234
2235/* Mask bits for fields in Word 0x0f of the EEPROM */
2236#define EEPROM_WORD0F_PAUSE_MASK 0x3000
2237#define EEPROM_WORD0F_PAUSE 0x1000
2238#define EEPROM_WORD0F_ASM_DIR 0x2000
2239#define EEPROM_WORD0F_ANE 0x0800
2240#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
d37ea5d5
AK		 2241#define EEPROM_WORD0F_LPLU 0x0001
2242
2243/* Mask bits for fields in Word 0x10/0x20 of the EEPROM */
2244#define EEPROM_WORD1020_GIGA_DISABLE 0x0010
2245#define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008
1da177e4 2246
85b22eb6
JK		 2247/* Mask bits for fields in Word 0x1a of the EEPROM */
2248#define EEPROM_WORD1A_ASPM_MASK 0x000C
2249
1da177e4
LT		 2250/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2251#define EEPROM_SUM 0xBABA
2252
2253/* EEPROM Map defines (WORD OFFSETS)*/
2254#define EEPROM_NODE_ADDRESS_BYTE_0 0
2255#define EEPROM_PBA_BYTE_1 8
2256
2257#define EEPROM_RESERVED_WORD 0xFFFF
2258
2259/* EEPROM Map Sizes (Byte Counts) */
2260#define PBA_SIZE 4
2261
2262/* Collision related configuration parameters */
2263#define E1000_COLLISION_THRESHOLD 15
2264#define E1000_CT_SHIFT 4
0fadb059
JK		 2265/* Collision distance is a 0-based value that applies to
2266 * half-duplex-capable hardware only. */
2267#define E1000_COLLISION_DISTANCE 63
2268#define E1000_COLLISION_DISTANCE_82542 64
1da177e4
LT		 2269#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2270#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2271#define E1000_COLD_SHIFT 12
2272
2273/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2274#define REQ_TX_DESCRIPTOR_MULTIPLE 8
2275#define REQ_RX_DESCRIPTOR_MULTIPLE 8
2276
2277/* Default values for the transmit IPG register */
2278#define DEFAULT_82542_TIPG_IPGT 10
2279#define DEFAULT_82543_TIPG_IPGT_FIBER 9
2280#define DEFAULT_82543_TIPG_IPGT_COPPER 8
2281
2282#define E1000_TIPG_IPGT_MASK 0x000003FF
2283#define E1000_TIPG_IPGR1_MASK 0x000FFC00
2284#define E1000_TIPG_IPGR2_MASK 0x3FF00000
2285
2286#define DEFAULT_82542_TIPG_IPGR1 2
2287#define DEFAULT_82543_TIPG_IPGR1 8
2288#define E1000_TIPG_IPGR1_SHIFT 10
2289
2290#define DEFAULT_82542_TIPG_IPGR2 10
2291#define DEFAULT_82543_TIPG_IPGR2 6
2292#define E1000_TIPG_IPGR2_SHIFT 20
2293
2294#define E1000_TXDMAC_DPP 0x00000001
2295
2296/* Adaptive IFS defines */
2297#define TX_THRESHOLD_START 8
2298#define TX_THRESHOLD_INCREMENT 10
2299#define TX_THRESHOLD_DECREMENT 1
2300#define TX_THRESHOLD_STOP 190
2301#define TX_THRESHOLD_DISABLE 0
2302#define TX_THRESHOLD_TIMER_MS 10000
2303#define MIN_NUM_XMITS 1000
2304#define IFS_MAX 80
2305#define IFS_STEP 10
2306#define IFS_MIN 40
2307#define IFS_RATIO 4
2308
2d7edb92
MC		 2309/* Extended Configuration Control and Size */
2310#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2311#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2312#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2313#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2314#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2315#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2316#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
d37ea5d5 2317#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000
2d7edb92
MC		 2318
2319#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2320#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2321#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
d37ea5d5
AK		 2322#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001
2323#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020
2d7edb92 2324
1da177e4 2325/* PBA constants */
120a5d0d
JB		 2326#define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */
2327#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
2328#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
018ea44e 2329#define E1000_PBA_20K 0x0014
1da177e4
LT		 2330#define E1000_PBA_22K 0x0016
2331#define E1000_PBA_24K 0x0018
2332#define E1000_PBA_30K 0x001E
868d5309 2333#define E1000_PBA_32K 0x0020
d37ea5d5 2334#define E1000_PBA_34K 0x0022
868d5309 2335#define E1000_PBA_38K 0x0026
1da177e4 2336#define E1000_PBA_40K 0x0028
120a5d0d 2337#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
1da177e4 2338
d37ea5d5
AK		 2339#define E1000_PBS_16K E1000_PBA_16K
2340
1da177e4
LT		 2341/* Flow Control Constants */
2342#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2343#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2344#define FLOW_CONTROL_TYPE 0x8808
2345
2346/* The historical defaults for the flow control values are given below. */
120a5d0d
JB		 2347#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2348#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2349#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
1da177e4
LT		 2350
2351/* PCIX Config space */
2352#define PCIX_COMMAND_REGISTER 0xE6
2353#define PCIX_STATUS_REGISTER_LO 0xE8
2354#define PCIX_STATUS_REGISTER_HI 0xEA
2355
2356#define PCIX_COMMAND_MMRBC_MASK 0x000C
2357#define PCIX_COMMAND_MMRBC_SHIFT 0x2
2358#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2359#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2360#define PCIX_STATUS_HI_MMRBC_4K 0x3
2361#define PCIX_STATUS_HI_MMRBC_2K 0x2
2362
1da177e4
LT		 2363/* Number of bits required to shift right the "pause" bits from the
2364 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2365 */
2366#define PAUSE_SHIFT 5
2367
2368/* Number of bits required to shift left the "SWDPIO" bits from the
2369 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2370 */
2371#define SWDPIO_SHIFT 17
2372
2373/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2374 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2375 */
2376#define SWDPIO__EXT_SHIFT 4
2377
2378/* Number of bits required to shift left the "ILOS" bit from the EEPROM
2379 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2380 */
2381#define ILOS_SHIFT 3
2382
1da177e4
LT		 2383#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2384
2385/* Number of milliseconds we wait for auto-negotiation to complete */
2386#define LINK_UP_TIMEOUT 500
2387
2d7edb92
MC		 2388/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2389#define AUTO_READ_DONE_TIMEOUT 10
2390/* Number of milliseconds we wait for PHY configuration done after MAC reset */
d37ea5d5 2391#define PHY_CFG_TIMEOUT 100
2d7edb92 2392
406874a7 2393#define E1000_TX_BUFFER_SIZE ((u32)1514)
1da177e4
LT		 2394
2395/* The carrier extension symbol, as received by the NIC. */
2396#define CARRIER_EXTENSION 0x0F
2397
2398/* TBI_ACCEPT macro definition:
2399 *
2400 * This macro requires:
2401 * adapter = a pointer to struct e1000_hw
2402 * status = the 8 bit status field of the RX descriptor with EOP set
2403 * error = the 8 bit error field of the RX descriptor with EOP set
2404 * length = the sum of all the length fields of the RX descriptors that
2405 * make up the current frame
2406 * last_byte = the last byte of the frame DMAed by the hardware
2407 * max_frame_length = the maximum frame length we want to accept.
2408 * min_frame_length = the minimum frame length we want to accept.
2409 *
2410 * This macro is a conditional that should be used in the interrupt
2411 * handler's Rx processing routine when RxErrors have been detected.
2412 *
2413 * Typical use:
2414 * ...
2415 * if (TBI_ACCEPT) {
c3033b01 2416 * accept_frame = true;
1da177e4
LT		 2417 * e1000_tbi_adjust_stats(adapter, MacAddress);
2418 * frame_length--;
2419 * } else {
c3033b01 2420 * accept_frame = false;
1da177e4
LT		 2421 * }
2422 * ...
2423 */
2424
2425#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2426 ((adapter)->tbi_compatibility_on && \
2427 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2428 ((last_byte) == CARRIER_EXTENSION) && \
2429 (((status) & E1000_RXD_STAT_VP) ? \
2430 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2431 ((length) <= ((adapter)->max_frame_size + 1))) : \
2432 (((length) > (adapter)->min_frame_size) && \
2433 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2434
1da177e4
LT		 2435/* Structures, enums, and macros for the PHY */
2436
2437/* Bit definitions for the Management Data IO (MDIO) and Management Data
2438 * Clock (MDC) pins in the Device Control Register.
2439 */
2440#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2441#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2442#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2443#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2444#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2445#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2446#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2447#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2448
2449/* PHY 1000 MII Register/Bit Definitions */
2450/* PHY Registers defined by IEEE */
120a5d0d
JB		 2451#define PHY_CTRL 0x00 /* Control Register */
2452#define PHY_STATUS 0x01 /* Status Register */
2453#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2454#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2455#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2456#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2457#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2458#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2459#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2460#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2461#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2462#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2463
2464#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2465#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
1da177e4
LT		 2466
2467/* M88E1000 Specific Registers */
120a5d0d
JB		 2468#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2469#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2470#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2471#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2472#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2473#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2474
2475#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2476#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2477#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2478#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2479#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
1da177e4
LT		 2480
2481#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2482#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2483#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2484
2485/* IGP01E1000 Specific Registers */
120a5d0d
JB		 2486#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2487#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2488#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2489#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2490#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2491#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2d7edb92 2492#define IGP02E1000_PHY_POWER_MGMT 0x19
120a5d0d 2493#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
1da177e4
LT		 2494
2495/* IGP01E1000 AGC Registers - stores the cable length values*/
2496#define IGP01E1000_PHY_AGC_A 0x1172
2497#define IGP01E1000_PHY_AGC_B 0x1272
2498#define IGP01E1000_PHY_AGC_C 0x1472
2499#define IGP01E1000_PHY_AGC_D 0x1872
2500
2d7edb92
MC		 2501/* IGP02E1000 AGC Registers for cable length values */
2502#define IGP02E1000_PHY_AGC_A 0x11B1
2503#define IGP02E1000_PHY_AGC_B 0x12B1
2504#define IGP02E1000_PHY_AGC_C 0x14B1
2505#define IGP02E1000_PHY_AGC_D 0x18B1
2506
1da177e4
LT		 2507/* IGP01E1000 DSP Reset Register */
2508#define IGP01E1000_PHY_DSP_RESET 0x1F33
2509#define IGP01E1000_PHY_DSP_SET 0x1F71
2510#define IGP01E1000_PHY_DSP_FFE 0x1F35
2511
2512#define IGP01E1000_PHY_CHANNEL_NUM 4
2d7edb92
MC		 2513#define IGP02E1000_PHY_CHANNEL_NUM 4
2514
1da177e4
LT		 2515#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2516#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2517#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2518#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2519
2520#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2521#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2522
2523#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2524#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2525#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2526#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2527
2528#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2529/* IGP01E1000 PCS Initialization register - stores the polarity status when
2530 * speed = 1000 Mbps. */
2531#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2532#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2533
2534#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2535
1da177e4 2536/* PHY Control Register */
120a5d0d
JB		 2537#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2538#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2539#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2540#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2541#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2542#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2543#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2544#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2545#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2546#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
1da177e4
LT		 2547
2548/* PHY Status Register */
120a5d0d
JB		 2549#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2550#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2551#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2552#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2553#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2554#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2555#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2556#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2557#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2558#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2559#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2560#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2561#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2562#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2563#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
1da177e4
LT		 2564
2565/* Autoneg Advertisement Register */
120a5d0d
JB		 2566#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2567#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2568#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2569#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2570#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2571#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2572#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2573#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2574#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2575#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1da177e4
LT		 2576
2577/* Link Partner Ability Register (Base Page) */
120a5d0d
JB		 2578#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2579#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2580#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2581#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2582#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2583#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2584#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2585#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2586#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2587#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2588#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
1da177e4
LT		 2589
2590/* Autoneg Expansion Register */
120a5d0d
JB		 2591#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2592#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2593#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2594#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2595#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
1da177e4
LT		 2596
2597/* Next Page TX Register */
120a5d0d
JB		 2598#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2599#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2600 * of different NP
2601 */
2602#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2603 * 0 = cannot comply with msg
2604 */
2605#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2606#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2607 * 0 = sending last NP
2608 */
1da177e4
LT		 2609
2610/* Link Partner Next Page Register */
120a5d0d
JB		 2611#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2612#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2613 * of different NP
2614 */
2615#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2616 * 0 = cannot comply with msg
2617 */
2618#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2619#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2620#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2621 * 0 = sending last NP
2622 */
1da177e4
LT		 2623
2624/* 1000BASE-T Control Register */
120a5d0d
JB		 2625#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2626#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2627#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2628#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2629 /* 0=DTE device */
2630#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2631 /* 0=Configure PHY as Slave */
2632#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2633 /* 0=Automatic Master/Slave config */
2634#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2635#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2636#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2637#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2638#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
1da177e4
LT		 2639
2640/* 1000BASE-T Status Register */
120a5d0d
JB		 2641#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2642#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2643#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2644#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2645#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2646#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2647#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2648#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
1da177e4
LT		 2649#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2650#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2651#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2652#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2653#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2654
2655/* Extended Status Register */
120a5d0d
JB		 2656#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2657#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2658#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2659#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
1da177e4 2660
120a5d0d
JB		 2661#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2662#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
1da177e4 2663
120a5d0d
JB		 2664#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2665 /* (0=enable, 1=disable) */
1da177e4
LT		 2666
2667/* M88E1000 PHY Specific Control Register */
120a5d0d
JB		 2668#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2669#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2670#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2671#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2672 * 0=CLK125 toggling
2673 */
2674#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2675 /* Manual MDI configuration */
2676#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2677#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2678 * 100BASE-TX/10BASE-T:
2679 * MDI Mode
2680 */
2681#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2682 * all speeds.
2683 */
1da177e4 2684#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
120a5d0d
JB		 2685 /* 1=Enable Extended 10BASE-T distance
2686 * (Lower 10BASE-T RX Threshold)
2687 * 0=Normal 10BASE-T RX Threshold */
1da177e4 2688#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
120a5d0d
JB		 2689 /* 1=5-Bit interface in 100BASE-TX
2690 * 0=MII interface in 100BASE-TX */
2691#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2692#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2693#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1da177e4
LT		 2694
2695#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2696#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2697#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2698
2699/* M88E1000 PHY Specific Status Register */
120a5d0d
JB		 2700#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2701#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2702#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2703#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2704#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2705 * 3=110-140M;4=>140M */
2706#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2707#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2708#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2709#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2710#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2711#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2712#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2713#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1da177e4
LT		 2714
2715#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2716#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2717#define M88E1000_PSSR_MDIX_SHIFT 6
2718#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2719
2720/* M88E1000 Extended PHY Specific Control Register */
120a5d0d
JB		 2721#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2722#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2723 * Will assert lost lock and bring
2724 * link down if idle not seen
2725 * within 1ms in 1000BASE-T
2726 */
1da177e4
LT		 2727/* Number of times we will attempt to autonegotiate before downshifting if we
2728 * are the master */
2729#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2730#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2731#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2732#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2733#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2734/* Number of times we will attempt to autonegotiate before downshifting if we
2735 * are the slave */
2736#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2737#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2738#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2739#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2740#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
120a5d0d
JB		 2741#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2742#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2743#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
1da177e4 2744
ee04022a
AK		 2745/* M88EC018 Rev 2 specific DownShift settings */
2746#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00
2747#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000
2748#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200
2749#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400
2750#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600
2751#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800
2752#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00
2753#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00
2754#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00
2755
1da177e4
LT		 2756/* IGP01E1000 Specific Port Config Register - R/W */
2757#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2758#define IGP01E1000_PSCFR_PRE_EN 0x0020
2759#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2760#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2761#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2762#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2763
2764/* IGP01E1000 Specific Port Status Register - R/O */
120a5d0d 2765#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
1da177e4
LT		 2766#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2767#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2768#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2769#define IGP01E1000_PSSR_LINK_UP 0x0400
2770#define IGP01E1000_PSSR_MDIX 0x0800
120a5d0d 2771#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
1da177e4
LT		 2772#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2773#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2774#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
120a5d0d
JB		 2775#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2776#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
1da177e4
LT		 2777
2778/* IGP01E1000 Specific Port Control Register - R/W */
2779#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2780#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2781#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2782#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2783#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
120a5d0d 2784#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
1da177e4
LT		 2785
2786/* IGP01E1000 Specific Port Link Health Register */
2787#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2788#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2789#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2790#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
120a5d0d
JB		 2791#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2792#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2793#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
1da177e4
LT		 2794#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2795#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2796#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2797#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2798#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2799#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2800#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2801
2802/* IGP01E1000 Channel Quality Register */
2803#define IGP01E1000_MSE_CHANNEL_D 0x000F
2804#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2805#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2806#define IGP01E1000_MSE_CHANNEL_A 0xF000
2807
120a5d0d
JB		 2808#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2809#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2810#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2d7edb92 2811
1da177e4
LT		 2812/* IGP01E1000 DSP reset macros */
2813#define DSP_RESET_ENABLE 0x0
2814#define DSP_RESET_DISABLE 0x2
2815#define E1000_MAX_DSP_RESETS 10
2816
2d7edb92 2817/* IGP01E1000 & IGP02E1000 AGC Registers */
1da177e4 2818
120a5d0d
JB		 2819#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2820#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2d7edb92
MC		 2821
2822/* IGP02E1000 AGC Register Length 9-bit mask */
2823#define IGP02E1000_AGC_LENGTH_MASK 0x7F
1da177e4
LT		 2824
2825/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2826#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
868d5309 2827#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
1da177e4 2828
2d7edb92 2829/* The precision error of the cable length is +/- 10 meters */
1da177e4 2830#define IGP01E1000_AGC_RANGE 10
868d5309 2831#define IGP02E1000_AGC_RANGE 15
1da177e4
LT		 2832
2833/* IGP01E1000 PCS Initialization register */
2834/* bits 3:6 in the PCS registers stores the channels polarity */
2835#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2836
2837/* IGP01E1000 GMII FIFO Register */
120a5d0d
JB		 2838#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2839 * on Link-Up */
2840#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
1da177e4
LT		 2841
2842/* IGP01E1000 Analog Register */
2843#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2844#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2845#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2846#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2847
2848#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2849#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2850#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2851#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2852#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2853
2854#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2855#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2856#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2857#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2858
1da177e4
LT		 2859/* Bit definitions for valid PHY IDs. */
2860/* I = Integrated
2861 * E = External
2862 */
2a88c173 2863#define M88_VENDOR 0x0141
1da177e4
LT		 2864#define M88E1000_E_PHY_ID 0x01410C50
2865#define M88E1000_I_PHY_ID 0x01410C30
2866#define M88E1011_I_PHY_ID 0x01410C20
2867#define IGP01E1000_I_PHY_ID 0x02A80380
2868#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2869#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2870#define M88E1011_I_REV_4 0x04
2d7edb92
MC		 2871#define M88E1111_I_PHY_ID 0x01410CC0
2872#define L1LXT971A_PHY_ID 0x001378E0
1da177e4 2873
d37ea5d5
AK		 2874/* Bits...
2875 * 15-5: page
2876 * 4-0: register offset
2877 */
2878#define PHY_PAGE_SHIFT 5
2879#define PHY_REG(page, reg) \
2880 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
2881
2882#define IGP3_PHY_PORT_CTRL \
120a5d0d 2883 PHY_REG(769, 17) /* Port General Configuration */
d37ea5d5 2884#define IGP3_PHY_RATE_ADAPT_CTRL \
120a5d0d 2885 PHY_REG(769, 25) /* Rate Adapter Control Register */
d37ea5d5
AK		 2886
2887#define IGP3_KMRN_FIFO_CTRL_STATS \
120a5d0d 2888 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
d37ea5d5 2889#define IGP3_KMRN_POWER_MNG_CTRL \
120a5d0d 2890 PHY_REG(770, 17) /* KMRN Power Management Control Register */
d37ea5d5 2891#define IGP3_KMRN_INBAND_CTRL \
120a5d0d 2892 PHY_REG(770, 18) /* KMRN Inband Control Register */
d37ea5d5 2893#define IGP3_KMRN_DIAG \
120a5d0d
JB		 2894 PHY_REG(770, 19) /* KMRN Diagnostic register */
2895#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */
d37ea5d5 2896#define IGP3_KMRN_ACK_TIMEOUT \
120a5d0d 2897 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
d37ea5d5
AK		 2898
2899#define IGP3_VR_CTRL \
120a5d0d
JB		 2900 PHY_REG(776, 18) /* Voltage regulator control register */
2901#define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */
2902#define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */
d37ea5d5
AK		 2903
2904#define IGP3_CAPABILITY \
120a5d0d 2905 PHY_REG(776, 19) /* IGP3 Capability Register */
d37ea5d5
AK		 2906
2907/* Capabilities for SKU Control */
120a5d0d
JB		 2908#define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */
2909#define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */
2910#define IGP3_CAP_ASF 0x0004 /* Support ASF */
2911#define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */
2912#define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */
2913#define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */
2914#define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */
2915#define IGP3_CAP_RSS 0x0080 /* Support RSS */
2916#define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */
2917#define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */
d37ea5d5
AK		 2918
2919#define IGP3_PPC_JORDAN_EN 0x0001
2920#define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002
2921
2922#define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001
2923#define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E
2924#define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020
2925#define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040
2926
120a5d0d
JB		 2927#define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */
2928#define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */
d37ea5d5
AK		 2929
2930#define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18)
2931#define IGP3_KMRN_EC_DIS_INBAND 0x0080
2932
2933#define IGP03E1000_E_PHY_ID 0x02A80390
120a5d0d 2934#define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */
d37ea5d5
AK		 2935#define IFE_PLUS_E_PHY_ID 0x02A80320
2936#define IFE_C_E_PHY_ID 0x02A80310
2937
120a5d0d
JB		 2938#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */
2939#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */
2940#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */
2941#define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */
2942#define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */
2943#define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */
2944#define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */
2945#define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */
2946#define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */
2947#define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */
2948#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */
2949#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */
2950#define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */
2951
2952#define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */
2953#define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
2954#define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
2955#define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
2956#define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */
2957#define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */
2958#define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */
d37ea5d5
AK		 2959#define IFE_PESC_POLARITY_REVERSED_SHIFT 8
2960
120a5d0d
JB		 2961#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */
2962#define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */
2963#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */
2964#define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */
d37ea5d5
AK		 2965#define IFE_PSC_FORCE_POLARITY_SHIFT 5
2966#define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4
2967
120a5d0d
JB		 2968#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */
2969#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */
2970#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */
2971#define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */
d37ea5d5 2972#define IFE_PMC_MDIX_MODE_SHIFT 6
120a5d0d
JB		 2973#define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */
2974
2975#define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */
2976#define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */
2977#define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */
2978#define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */
2979#define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */
2980#define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */
2981#define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */
2982#define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */
2983#define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */
2984#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */
2985#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
2986
2987#define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */
2988#define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */
2989#define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */
2df7d59f
JK		 2990#define ICH_FLASH_SEG_SIZE_256 256
2991#define ICH_FLASH_SEG_SIZE_4K 4096
2992#define ICH_FLASH_SEG_SIZE_64K 65536
2993
2994#define ICH_CYCLE_READ 0x0
2995#define ICH_CYCLE_RESERVED 0x1
2996#define ICH_CYCLE_WRITE 0x2
2997#define ICH_CYCLE_ERASE 0x3
2998
2999#define ICH_FLASH_GFPREG 0x0000
3000#define ICH_FLASH_HSFSTS 0x0004
3001#define ICH_FLASH_HSFCTL 0x0006
3002#define ICH_FLASH_FADDR 0x0008
3003#define ICH_FLASH_FDATA0 0x0010
3004#define ICH_FLASH_FRACC 0x0050
3005#define ICH_FLASH_FREG0 0x0054
3006#define ICH_FLASH_FREG1 0x0058
3007#define ICH_FLASH_FREG2 0x005C
3008#define ICH_FLASH_FREG3 0x0060
3009#define ICH_FLASH_FPR0 0x0074
3010#define ICH_FLASH_FPR1 0x0078
3011#define ICH_FLASH_SSFSTS 0x0090
3012#define ICH_FLASH_SSFCTL 0x0092
3013#define ICH_FLASH_PREOP 0x0094
3014#define ICH_FLASH_OPTYPE 0x0096
3015#define ICH_FLASH_OPMENU 0x0098
3016
3017#define ICH_FLASH_REG_MAPSIZE 0x00A0
3018#define ICH_FLASH_SECTOR_SIZE 4096
3019#define ICH_GFPREG_BASE_MASK 0x1FFF
3020#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
d37ea5d5 3021
1da177e4
LT		 3022/* Miscellaneous PHY bit definitions. */
3023#define PHY_PREAMBLE 0xFFFFFFFF
3024#define PHY_SOF 0x01
3025#define PHY_OP_READ 0x02
3026#define PHY_OP_WRITE 0x01
3027#define PHY_TURNAROUND 0x02
3028#define PHY_PREAMBLE_SIZE 32
3029#define MII_CR_SPEED_1000 0x0040
3030#define MII_CR_SPEED_100 0x2000
3031#define MII_CR_SPEED_10 0x0000
3032#define E1000_PHY_ADDRESS 0x01
120a5d0d
JB		 3033#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
3034#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
1da177e4 3035#define PHY_REVISION_MASK 0xFFFFFFF0
120a5d0d 3036#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
1da177e4
LT		 3037#define REG4_SPEED_MASK 0x01E0
3038#define REG9_SPEED_MASK 0x0300
3039#define ADVERTISE_10_HALF 0x0001
3040#define ADVERTISE_10_FULL 0x0002
3041#define ADVERTISE_100_HALF 0x0004
3042#define ADVERTISE_100_FULL 0x0008
3043#define ADVERTISE_1000_HALF 0x0010
3044#define ADVERTISE_1000_FULL 0x0020
120a5d0d
JB		 3045#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
3046#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */
3047#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */
1da177e4
LT		 3048
3049#endif /* _E1000_HW_H_ */
Linux kernel - Deliverables
This page took 0.760935 seconds and 5 git commands to generate.