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[PATCH] e1000: Fix adapter structure and prepare for multique fix
[deliverable/linux.git] / drivers / net / e1000 / e1000_hw.h
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* e1000_hw.h
30 * Structures, enums, and macros for the MAC
31 */
32
33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include "e1000_osdep.h"
37
38
39/* Forward declarations of structures used by the shared code */
40struct e1000_hw;
41struct e1000_hw_stats;
42
43/* Enumerated types specific to the e1000 hardware */
44/* Media Access Controlers */
45typedef enum {
46 e1000_undefined = 0,
47 e1000_82542_rev2_0,
48 e1000_82542_rev2_1,
49 e1000_82543,
50 e1000_82544,
51 e1000_82540,
52 e1000_82545,
53 e1000_82545_rev_3,
54 e1000_82546,
55 e1000_82546_rev_3,
56 e1000_82541,
57 e1000_82541_rev_2,
58 e1000_82547,
59 e1000_82547_rev_2,
868d5309
MC		 60 e1000_82571,
61 e1000_82572,
2d7edb92 62 e1000_82573,
1da177e4
LT		 63 e1000_num_macs
64} e1000_mac_type;
65
66typedef enum {
67 e1000_eeprom_uninitialized = 0,
68 e1000_eeprom_spi,
69 e1000_eeprom_microwire,
2d7edb92 70 e1000_eeprom_flash,
3893d547 71 e1000_eeprom_none, /* No NVM support */
1da177e4
LT		 72 e1000_num_eeprom_types
73} e1000_eeprom_type;
74
75/* Media Types */
76typedef enum {
77 e1000_media_type_copper = 0,
78 e1000_media_type_fiber = 1,
79 e1000_media_type_internal_serdes = 2,
80 e1000_num_media_types
81} e1000_media_type;
82
83typedef enum {
84 e1000_10_half = 0,
85 e1000_10_full = 1,
86 e1000_100_half = 2,
87 e1000_100_full = 3
88} e1000_speed_duplex_type;
89
90/* Flow Control Settings */
91typedef enum {
92 e1000_fc_none = 0,
93 e1000_fc_rx_pause = 1,
94 e1000_fc_tx_pause = 2,
95 e1000_fc_full = 3,
96 e1000_fc_default = 0xFF
97} e1000_fc_type;
98
99/* PCI bus types */
100typedef enum {
101 e1000_bus_type_unknown = 0,
102 e1000_bus_type_pci,
103 e1000_bus_type_pcix,
2d7edb92 104 e1000_bus_type_pci_express,
1da177e4
LT		 105 e1000_bus_type_reserved
106} e1000_bus_type;
107
108/* PCI bus speeds */
109typedef enum {
110 e1000_bus_speed_unknown = 0,
111 e1000_bus_speed_33,
112 e1000_bus_speed_66,
113 e1000_bus_speed_100,
114 e1000_bus_speed_120,
115 e1000_bus_speed_133,
2d7edb92 116 e1000_bus_speed_2500,
1da177e4
LT		 117 e1000_bus_speed_reserved
118} e1000_bus_speed;
119
120/* PCI bus widths */
121typedef enum {
122 e1000_bus_width_unknown = 0,
123 e1000_bus_width_32,
124 e1000_bus_width_64,
2d7edb92 125 e1000_bus_width_pciex_1,
fd803241 126 e1000_bus_width_pciex_2,
2d7edb92 127 e1000_bus_width_pciex_4,
1da177e4
LT		 128 e1000_bus_width_reserved
129} e1000_bus_width;
130
131/* PHY status info structure and supporting enums */
132typedef enum {
133 e1000_cable_length_50 = 0,
134 e1000_cable_length_50_80,
135 e1000_cable_length_80_110,
136 e1000_cable_length_110_140,
137 e1000_cable_length_140,
138 e1000_cable_length_undefined = 0xFF
139} e1000_cable_length;
140
141typedef enum {
142 e1000_igp_cable_length_10 = 10,
143 e1000_igp_cable_length_20 = 20,
144 e1000_igp_cable_length_30 = 30,
145 e1000_igp_cable_length_40 = 40,
146 e1000_igp_cable_length_50 = 50,
147 e1000_igp_cable_length_60 = 60,
148 e1000_igp_cable_length_70 = 70,
149 e1000_igp_cable_length_80 = 80,
150 e1000_igp_cable_length_90 = 90,
151 e1000_igp_cable_length_100 = 100,
152 e1000_igp_cable_length_110 = 110,
fd803241 153 e1000_igp_cable_length_115 = 115,
1da177e4
LT		 154 e1000_igp_cable_length_120 = 120,
155 e1000_igp_cable_length_130 = 130,
156 e1000_igp_cable_length_140 = 140,
157 e1000_igp_cable_length_150 = 150,
158 e1000_igp_cable_length_160 = 160,
159 e1000_igp_cable_length_170 = 170,
160 e1000_igp_cable_length_180 = 180
161} e1000_igp_cable_length;
162
163typedef enum {
164 e1000_10bt_ext_dist_enable_normal = 0,
165 e1000_10bt_ext_dist_enable_lower,
166 e1000_10bt_ext_dist_enable_undefined = 0xFF
167} e1000_10bt_ext_dist_enable;
168
169typedef enum {
170 e1000_rev_polarity_normal = 0,
171 e1000_rev_polarity_reversed,
172 e1000_rev_polarity_undefined = 0xFF
173} e1000_rev_polarity;
174
175typedef enum {
176 e1000_downshift_normal = 0,
177 e1000_downshift_activated,
178 e1000_downshift_undefined = 0xFF
179} e1000_downshift;
180
181typedef enum {
182 e1000_smart_speed_default = 0,
183 e1000_smart_speed_on,
184 e1000_smart_speed_off
185} e1000_smart_speed;
186
187typedef enum {
188 e1000_polarity_reversal_enabled = 0,
189 e1000_polarity_reversal_disabled,
190 e1000_polarity_reversal_undefined = 0xFF
191} e1000_polarity_reversal;
192
193typedef enum {
194 e1000_auto_x_mode_manual_mdi = 0,
195 e1000_auto_x_mode_manual_mdix,
196 e1000_auto_x_mode_auto1,
197 e1000_auto_x_mode_auto2,
198 e1000_auto_x_mode_undefined = 0xFF
199} e1000_auto_x_mode;
200
201typedef enum {
202 e1000_1000t_rx_status_not_ok = 0,
203 e1000_1000t_rx_status_ok,
204 e1000_1000t_rx_status_undefined = 0xFF
205} e1000_1000t_rx_status;
206
207typedef enum {
208 e1000_phy_m88 = 0,
209 e1000_phy_igp,
2d7edb92 210 e1000_phy_igp_2,
1da177e4
LT		 211 e1000_phy_undefined = 0xFF
212} e1000_phy_type;
213
214typedef enum {
215 e1000_ms_hw_default = 0,
216 e1000_ms_force_master,
217 e1000_ms_force_slave,
218 e1000_ms_auto
219} e1000_ms_type;
220
221typedef enum {
222 e1000_ffe_config_enabled = 0,
223 e1000_ffe_config_active,
224 e1000_ffe_config_blocked
225} e1000_ffe_config;
226
227typedef enum {
228 e1000_dsp_config_disabled = 0,
229 e1000_dsp_config_enabled,
230 e1000_dsp_config_activated,
231 e1000_dsp_config_undefined = 0xFF
232} e1000_dsp_config;
233
234struct e1000_phy_info {
235 e1000_cable_length cable_length;
236 e1000_10bt_ext_dist_enable extended_10bt_distance;
237 e1000_rev_polarity cable_polarity;
238 e1000_downshift downshift;
239 e1000_polarity_reversal polarity_correction;
240 e1000_auto_x_mode mdix_mode;
241 e1000_1000t_rx_status local_rx;
242 e1000_1000t_rx_status remote_rx;
243};
244
245struct e1000_phy_stats {
246 uint32_t idle_errors;
247 uint32_t receive_errors;
248};
249
250struct e1000_eeprom_info {
251 e1000_eeprom_type type;
252 uint16_t word_size;
253 uint16_t opcode_bits;
254 uint16_t address_bits;
255 uint16_t delay_usec;
256 uint16_t page_size;
2d7edb92
MC		 257 boolean_t use_eerd;
258 boolean_t use_eewr;
1da177e4
LT		 259};
260
2d7edb92
MC		 261/* Flex ASF Information */
262#define E1000_HOST_IF_MAX_SIZE 2048
263
264typedef enum {
265 e1000_byte_align = 0,
266 e1000_word_align = 1,
267 e1000_dword_align = 2
268} e1000_align_type;
269
1da177e4
LT		 270
271
272/* Error Codes */
273#define E1000_SUCCESS 0
274#define E1000_ERR_EEPROM 1
275#define E1000_ERR_PHY 2
276#define E1000_ERR_CONFIG 3
277#define E1000_ERR_PARAM 4
278#define E1000_ERR_MAC_TYPE 5
279#define E1000_ERR_PHY_TYPE 6
2d7edb92
MC		 280#define E1000_ERR_RESET 9
281#define E1000_ERR_MASTER_REQUESTS_PENDING 10
282#define E1000_ERR_HOST_INTERFACE_COMMAND 11
283#define E1000_BLK_PHY_RESET 12
1da177e4
LT		 284
285/* Function prototypes */
286/* Initialization */
287int32_t e1000_reset_hw(struct e1000_hw *hw);
288int32_t e1000_init_hw(struct e1000_hw *hw);
289int32_t e1000_set_mac_type(struct e1000_hw *hw);
290void e1000_set_media_type(struct e1000_hw *hw);
291
292/* Link Configuration */
293int32_t e1000_setup_link(struct e1000_hw *hw);
294int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
295void e1000_config_collision_dist(struct e1000_hw *hw);
1da177e4
LT		 296int32_t e1000_check_for_link(struct e1000_hw *hw);
297int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
1da177e4
LT		 298int32_t e1000_force_mac_fc(struct e1000_hw *hw);
299
300/* PHY */
301int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
302int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
2d7edb92 303int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
1da177e4 304int32_t e1000_phy_reset(struct e1000_hw *hw);
1da177e4 305int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
1da177e4
LT		 306int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
307
308/* EEPROM Functions */
2d7edb92 309int32_t e1000_init_eeprom_params(struct e1000_hw *hw);
2d7edb92
MC		 310
311/* MNG HOST IF functions */
312uint32_t e1000_enable_mng_pass_thru(struct e1000_hw *hw);
313
314#define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64
315#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */
316
317#define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */
318#define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */
319#define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */
320#define E1000_MNG_IAMT_MODE 0x3
321#define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */
322
323#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */
324#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */
325#define E1000_VFTA_ENTRY_SHIFT 0x5
326#define E1000_VFTA_ENTRY_MASK 0x7F
327#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
328
329struct e1000_host_mng_command_header {
330 uint8_t command_id;
331 uint8_t checksum;
332 uint16_t reserved1;
333 uint16_t reserved2;
334 uint16_t command_length;
335};
336
337struct e1000_host_mng_command_info {
338 struct e1000_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
339 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/
340};
341#ifdef __BIG_ENDIAN
342struct e1000_host_mng_dhcp_cookie{
343 uint32_t signature;
344 uint16_t vlan_id;
345 uint8_t reserved0;
346 uint8_t status;
347 uint32_t reserved1;
348 uint8_t checksum;
349 uint8_t reserved3;
350 uint16_t reserved2;
351};
352#else
353struct e1000_host_mng_dhcp_cookie{
354 uint32_t signature;
355 uint8_t status;
356 uint8_t reserved0;
357 uint16_t vlan_id;
358 uint32_t reserved1;
359 uint16_t reserved2;
360 uint8_t reserved3;
361 uint8_t checksum;
362};
363#endif
364
365int32_t e1000_mng_write_dhcp_info(struct e1000_hw *hw, uint8_t *buffer,
366 uint16_t length);
367boolean_t e1000_check_mng_mode(struct e1000_hw *hw);
368boolean_t e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
2d7edb92 369
1da177e4
LT		 370int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
371int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
372int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
373int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
374int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
375int32_t e1000_read_mac_addr(struct e1000_hw * hw);
2d7edb92
MC		 376int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
377void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
1da177e4
LT		 378
379/* Filters (multicast, vlan, receive) */
1da177e4
LT		 380uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
381void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
382void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
383void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
1da177e4
LT		 384
385/* LED functions */
386int32_t e1000_setup_led(struct e1000_hw *hw);
387int32_t e1000_cleanup_led(struct e1000_hw *hw);
388int32_t e1000_led_on(struct e1000_hw *hw);
389int32_t e1000_led_off(struct e1000_hw *hw);
390
391/* Adaptive IFS Functions */
392
393/* Everything else */
1da177e4
LT		 394void e1000_reset_adaptive(struct e1000_hw *hw);
395void e1000_update_adaptive(struct e1000_hw *hw);
396void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
397void e1000_get_bus_info(struct e1000_hw *hw);
398void e1000_pci_set_mwi(struct e1000_hw *hw);
399void e1000_pci_clear_mwi(struct e1000_hw *hw);
400void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
401void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
402/* Port I/O is only supported on 82544 and newer */
403uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
1da177e4 404void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
2d7edb92 405int32_t e1000_disable_pciex_master(struct e1000_hw *hw);
2d7edb92
MC		 406int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
407void e1000_release_software_semaphore(struct e1000_hw *hw);
408int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
1da177e4
LT		 409
410/* PCI Device IDs */
411#define E1000_DEV_ID_82542 0x1000
412#define E1000_DEV_ID_82543GC_FIBER 0x1001
413#define E1000_DEV_ID_82543GC_COPPER 0x1004
414#define E1000_DEV_ID_82544EI_COPPER 0x1008
415#define E1000_DEV_ID_82544EI_FIBER 0x1009
416#define E1000_DEV_ID_82544GC_COPPER 0x100C
417#define E1000_DEV_ID_82544GC_LOM 0x100D
418#define E1000_DEV_ID_82540EM 0x100E
419#define E1000_DEV_ID_82540EM_LOM 0x1015
420#define E1000_DEV_ID_82540EP_LOM 0x1016
421#define E1000_DEV_ID_82540EP 0x1017
422#define E1000_DEV_ID_82540EP_LP 0x101E
423#define E1000_DEV_ID_82545EM_COPPER 0x100F
424#define E1000_DEV_ID_82545EM_FIBER 0x1011
425#define E1000_DEV_ID_82545GM_COPPER 0x1026
426#define E1000_DEV_ID_82545GM_FIBER 0x1027
427#define E1000_DEV_ID_82545GM_SERDES 0x1028
428#define E1000_DEV_ID_82546EB_COPPER 0x1010
429#define E1000_DEV_ID_82546EB_FIBER 0x1012
430#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
431#define E1000_DEV_ID_82541EI 0x1013
432#define E1000_DEV_ID_82541EI_MOBILE 0x1018
433#define E1000_DEV_ID_82541ER 0x1078
434#define E1000_DEV_ID_82547GI 0x1075
435#define E1000_DEV_ID_82541GI 0x1076
436#define E1000_DEV_ID_82541GI_MOBILE 0x1077
437#define E1000_DEV_ID_82541GI_LF 0x107C
438#define E1000_DEV_ID_82546GB_COPPER 0x1079
439#define E1000_DEV_ID_82546GB_FIBER 0x107A
440#define E1000_DEV_ID_82546GB_SERDES 0x107B
441#define E1000_DEV_ID_82546GB_PCIE 0x108A
442#define E1000_DEV_ID_82547EI 0x1019
868d5309
MC		 443#define E1000_DEV_ID_82571EB_COPPER 0x105E
444#define E1000_DEV_ID_82571EB_FIBER 0x105F
445#define E1000_DEV_ID_82571EB_SERDES 0x1060
446#define E1000_DEV_ID_82572EI_COPPER 0x107D
447#define E1000_DEV_ID_82572EI_FIBER 0x107E
448#define E1000_DEV_ID_82572EI_SERDES 0x107F
2d7edb92
MC		 449#define E1000_DEV_ID_82573E 0x108B
450#define E1000_DEV_ID_82573E_IAMT 0x108C
868d5309 451#define E1000_DEV_ID_82573L 0x109A
2d7edb92 452
1da177e4
LT		 453
454#define NODE_ADDRESS_SIZE 6
455#define ETH_LENGTH_OF_ADDRESS 6
456
457/* MAC decode size is 128K - This is the size of BAR0 */
458#define MAC_DECODE_SIZE (128 * 1024)
459
460#define E1000_82542_2_0_REV_ID 2
461#define E1000_82542_2_1_REV_ID 3
462#define E1000_REVISION_0 0
463#define E1000_REVISION_1 1
464#define E1000_REVISION_2 2
2d7edb92 465#define E1000_REVISION_3 3
1da177e4
LT		 466
467#define SPEED_10 10
468#define SPEED_100 100
469#define SPEED_1000 1000
470#define HALF_DUPLEX 1
471#define FULL_DUPLEX 2
472
473/* The sizes (in bytes) of a ethernet packet */
474#define ENET_HEADER_SIZE 14
475#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
476#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
477#define ETHERNET_FCS_SIZE 4
478#define MAXIMUM_ETHERNET_PACKET_SIZE \
479 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
480#define MINIMUM_ETHERNET_PACKET_SIZE \
481 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
482#define CRC_LENGTH ETHERNET_FCS_SIZE
483#define MAX_JUMBO_FRAME_SIZE 0x3F00
484
485
486/* 802.1q VLAN Packet Sizes */
487#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
488
489/* Ethertype field values */
490#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
491#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
492#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
493
494/* Packet Header defines */
495#define IP_PROTOCOL_TCP 6
496#define IP_PROTOCOL_UDP 0x11
497
498/* This defines the bits that are set in the Interrupt Mask
499 * Set/Read Register. Each bit is documented below:
500 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
501 * o RXSEQ = Receive Sequence Error
502 */
503#define POLL_IMS_ENABLE_MASK ( \
504 E1000_IMS_RXDMT0 | \
505 E1000_IMS_RXSEQ)
506
507/* This defines the bits that are set in the Interrupt Mask
508 * Set/Read Register. Each bit is documented below:
509 * o RXT0 = Receiver Timer Interrupt (ring 0)
510 * o TXDW = Transmit Descriptor Written Back
511 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
512 * o RXSEQ = Receive Sequence Error
513 * o LSC = Link Status Change
514 */
515#define IMS_ENABLE_MASK ( \
516 E1000_IMS_RXT0 | \
517 E1000_IMS_TXDW | \
518 E1000_IMS_RXDMT0 | \
519 E1000_IMS_RXSEQ | \
520 E1000_IMS_LSC)
521
2d7edb92 522
1da177e4
LT		 523/* Number of high/low register pairs in the RAR. The RAR (Receive Address
524 * Registers) holds the directed and multicast addresses that we monitor. We
525 * reserve one of these spots for our directed address, allowing us room for
526 * E1000_RAR_ENTRIES - 1 multicast addresses.
527 */
528#define E1000_RAR_ENTRIES 15
529
530#define MIN_NUMBER_OF_DESCRIPTORS 8
531#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
532
533/* Receive Descriptor */
534struct e1000_rx_desc {
535 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
536 uint16_t length; /* Length of data DMAed into data buffer */
537 uint16_t csum; /* Packet checksum */
538 uint8_t status; /* Descriptor status */
539 uint8_t errors; /* Descriptor Errors */
540 uint16_t special;
541};
542
2d7edb92
MC		 543/* Receive Descriptor - Extended */
544union e1000_rx_desc_extended {
545 struct {
546 uint64_t buffer_addr;
547 uint64_t reserved;
548 } read;
549 struct {
550 struct {
551 uint32_t mrq; /* Multiple Rx Queues */
552 union {
553 uint32_t rss; /* RSS Hash */
554 struct {
555 uint16_t ip_id; /* IP id */
556 uint16_t csum; /* Packet Checksum */
557 } csum_ip;
558 } hi_dword;
559 } lower;
560 struct {
561 uint32_t status_error; /* ext status/error */
562 uint16_t length;
563 uint16_t vlan; /* VLAN tag */
564 } upper;
565 } wb; /* writeback */
566};
567
568#define MAX_PS_BUFFERS 4
569/* Receive Descriptor - Packet Split */
570union e1000_rx_desc_packet_split {
571 struct {
572 /* one buffer for protocol header(s), three data buffers */
573 uint64_t buffer_addr[MAX_PS_BUFFERS];
574 } read;
575 struct {
576 struct {
577 uint32_t mrq; /* Multiple Rx Queues */
578 union {
579 uint32_t rss; /* RSS Hash */
580 struct {
581 uint16_t ip_id; /* IP id */
582 uint16_t csum; /* Packet Checksum */
583 } csum_ip;
584 } hi_dword;
585 } lower;
586 struct {
587 uint32_t status_error; /* ext status/error */
588 uint16_t length0; /* length of buffer 0 */
589 uint16_t vlan; /* VLAN tag */
590 } middle;
591 struct {
592 uint16_t header_status;
593 uint16_t length[3]; /* length of buffers 1-3 */
594 } upper;
595 uint64_t reserved;
596 } wb; /* writeback */
597};
598
1da177e4
LT		 599/* Receive Decriptor bit definitions */
600#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
601#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
602#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
603#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
2d7edb92 604#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum caculated */
1da177e4
LT		 605#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
606#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
607#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
2d7edb92
MC		 608#define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */
609#define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
610#define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1da177e4
LT		 611#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
612#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
613#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
614#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
615#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
616#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
617#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
618#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
619#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
2d7edb92 620#define E1000_RXD_SPC_PRI_SHIFT 13
1da177e4 621#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
2d7edb92
MC		 622#define E1000_RXD_SPC_CFI_SHIFT 12
623
624#define E1000_RXDEXT_STATERR_CE 0x01000000
625#define E1000_RXDEXT_STATERR_SE 0x02000000
626#define E1000_RXDEXT_STATERR_SEQ 0x04000000
627#define E1000_RXDEXT_STATERR_CXE 0x10000000
628#define E1000_RXDEXT_STATERR_TCPE 0x20000000
629#define E1000_RXDEXT_STATERR_IPE 0x40000000
630#define E1000_RXDEXT_STATERR_RXE 0x80000000
631
632#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000
633#define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1da177e4
LT		 634
635/* mask to determine if packets should be dropped due to frame errors */
636#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
637 E1000_RXD_ERR_CE | \
638 E1000_RXD_ERR_SE | \
639 E1000_RXD_ERR_SEQ | \
640 E1000_RXD_ERR_CXE | \
641 E1000_RXD_ERR_RXE)
642
2d7edb92
MC		 643
644/* Same mask, but for extended and packet split descriptors */
645#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
646 E1000_RXDEXT_STATERR_CE | \
647 E1000_RXDEXT_STATERR_SE | \
648 E1000_RXDEXT_STATERR_SEQ | \
649 E1000_RXDEXT_STATERR_CXE | \
650 E1000_RXDEXT_STATERR_RXE)
651
1da177e4
LT		 652/* Transmit Descriptor */
653struct e1000_tx_desc {
654 uint64_t buffer_addr; /* Address of the descriptor's data buffer */
655 union {
656 uint32_t data;
657 struct {
658 uint16_t length; /* Data buffer length */
659 uint8_t cso; /* Checksum offset */
660 uint8_t cmd; /* Descriptor control */
661 } flags;
662 } lower;
663 union {
664 uint32_t data;
665 struct {
666 uint8_t status; /* Descriptor status */
667 uint8_t css; /* Checksum start */
668 uint16_t special;
669 } fields;
670 } upper;
671};
672
673/* Transmit Descriptor bit definitions */
674#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
675#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
676#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
677#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
678#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
679#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
680#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
681#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
682#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
683#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
684#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
685#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
686#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
687#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
688#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
689#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
690#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
691#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
692#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
693#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
694
695/* Offload Context Descriptor */
696struct e1000_context_desc {
697 union {
698 uint32_t ip_config;
699 struct {
700 uint8_t ipcss; /* IP checksum start */
701 uint8_t ipcso; /* IP checksum offset */
702 uint16_t ipcse; /* IP checksum end */
703 } ip_fields;
704 } lower_setup;
705 union {
706 uint32_t tcp_config;
707 struct {
708 uint8_t tucss; /* TCP checksum start */
709 uint8_t tucso; /* TCP checksum offset */
710 uint16_t tucse; /* TCP checksum end */
711 } tcp_fields;
712 } upper_setup;
713 uint32_t cmd_and_length; /* */
714 union {
715 uint32_t data;
716 struct {
717 uint8_t status; /* Descriptor status */
718 uint8_t hdr_len; /* Header length */
719 uint16_t mss; /* Maximum segment size */
720 } fields;
721 } tcp_seg_setup;
722};
723
724/* Offload data descriptor */
725struct e1000_data_desc {
726 uint64_t buffer_addr; /* Address of the descriptor's buffer address */
727 union {
728 uint32_t data;
729 struct {
730 uint16_t length; /* Data buffer length */
731 uint8_t typ_len_ext; /* */
732 uint8_t cmd; /* */
733 } flags;
734 } lower;
735 union {
736 uint32_t data;
737 struct {
738 uint8_t status; /* Descriptor status */
739 uint8_t popts; /* Packet Options */
740 uint16_t special; /* */
741 } fields;
742 } upper;
743};
744
745/* Filters */
746#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
747#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
748#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
749
750
751/* Receive Address Register */
752struct e1000_rar {
753 volatile uint32_t low; /* receive address low */
754 volatile uint32_t high; /* receive address high */
755};
756
757/* Number of entries in the Multicast Table Array (MTA). */
758#define E1000_NUM_MTA_REGISTERS 128
759
760/* IPv4 Address Table Entry */
761struct e1000_ipv4_at_entry {
762 volatile uint32_t ipv4_addr; /* IP Address (RW) */
763 volatile uint32_t reserved;
764};
765
766/* Four wakeup IP addresses are supported */
767#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
768#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
769#define E1000_IP6AT_SIZE 1
770
771/* IPv6 Address Table Entry */
772struct e1000_ipv6_at_entry {
773 volatile uint8_t ipv6_addr[16];
774};
775
776/* Flexible Filter Length Table Entry */
777struct e1000_fflt_entry {
778 volatile uint32_t length; /* Flexible Filter Length (RW) */
779 volatile uint32_t reserved;
780};
781
782/* Flexible Filter Mask Table Entry */
783struct e1000_ffmt_entry {
784 volatile uint32_t mask; /* Flexible Filter Mask (RW) */
785 volatile uint32_t reserved;
786};
787
788/* Flexible Filter Value Table Entry */
789struct e1000_ffvt_entry {
790 volatile uint32_t value; /* Flexible Filter Value (RW) */
791 volatile uint32_t reserved;
792};
793
794/* Four Flexible Filters are supported */
795#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
796
797/* Each Flexible Filter is at most 128 (0x80) bytes in length */
798#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
799
800#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
801#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
802#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
803
868d5309
MC		 804#define E1000_DISABLE_SERDES_LOOPBACK 0x0400
805
1da177e4
LT		 806/* Register Set. (82543, 82544)
807 *
808 * Registers are defined to be 32 bits and should be accessed as 32 bit values.
809 * These registers are physically located on the NIC, but are mapped into the
810 * host memory address space.
811 *
812 * RW - register is both readable and writable
813 * RO - register is read only
814 * WO - register is write only
815 * R/clr - register is read only and is cleared when read
816 * A - register array
817 */
818#define E1000_CTRL 0x00000 /* Device Control - RW */
819#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
820#define E1000_STATUS 0x00008 /* Device Status - RO */
821#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
822#define E1000_EERD 0x00014 /* EEPROM Read - RW */
823#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
824#define E1000_FLA 0x0001C /* Flash Access - RW */
825#define E1000_MDIC 0x00020 /* MDI Control - RW */
868d5309 826#define E1000_SCTL 0x00024 /* SerDes Control - RW */
1da177e4
LT		 827#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
828#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
829#define E1000_FCT 0x00030 /* Flow Control Type - RW */
830#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
831#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
832#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
833#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
834#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
835#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
2d7edb92 836#define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */
1da177e4 837#define E1000_RCTL 0x00100 /* RX Control - RW */
868d5309
MC		 838#define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */
839#define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */
840#define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */
841#define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */
842#define E1000_RDH1 0x02910 /* RX Descriptor Head (1) - RW */
843#define E1000_RDT1 0x02918 /* RX Descriptor Tail (1) - RW */
1da177e4
LT		 844#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
845#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
846#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
847#define E1000_TCTL 0x00400 /* TX Control - RW */
848#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
849#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
850#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
851#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
2d7edb92
MC		 852#define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */
853#define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */
1da177e4 854#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
2d7edb92
MC		 855#define E1000_PBS 0x01008 /* Packet Buffer Size */
856#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
857#define E1000_FLASH_UPDATES 1000
858#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
859#define E1000_FLASHT 0x01028 /* FLASH Timer Register */
860#define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */
861#define E1000_FLSWCTL 0x01030 /* FLASH control register */
862#define E1000_FLSWDATA 0x01034 /* FLASH data register */
863#define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */
864#define E1000_FLOP 0x0103C /* FLASH Opcode Register */
865#define E1000_ERT 0x02008 /* Early Rx Threshold - RW */
1da177e4
LT		 866#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
867#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
2d7edb92 868#define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
1da177e4
LT		 869#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
870#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
871#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
872#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
873#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
874#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
868d5309
MC		 875#define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
876#define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */
877#define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */
878#define E1000_RDH0 E1000_RDH /* RX Desc Head (0) - RW */
879#define E1000_RDT0 E1000_RDT /* RX Desc Tail (0) - RW */
880#define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */
1da177e4
LT		 881#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
882#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
883#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
2d7edb92 884#define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
1da177e4
LT		 885#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
886#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
887#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
888#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
889#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
890#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
891#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
892#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
893#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
894#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
895#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
896#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
897#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
898#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
899#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
2d7edb92
MC		 900#define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */
901#define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */
902#define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */
903#define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */
904#define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */
905#define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */
906#define E1000_TXDCTL1 0x03928 /* TX Descriptor Control (1) - RW */
907#define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */
1da177e4
LT		 908#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
909#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
910#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
911#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
912#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
913#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
914#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
915#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
916#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
917#define E1000_COLC 0x04028 /* Collision Count - R/clr */
918#define E1000_DC 0x04030 /* Defer Count - R/clr */
919#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
920#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
921#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
922#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
923#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
924#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
925#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
926#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
927#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
928#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
929#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
930#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
931#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
932#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
933#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
934#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
935#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
936#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
937#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
938#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
939#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
940#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
941#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
942#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
943#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
944#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
945#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
946#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
947#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
948#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
949#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
950#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
951#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
952#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
953#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
954#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
955#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
956#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
957#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
958#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
959#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
960#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
961#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
962#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
963#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
964#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
965#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
868d5309
MC		 966#define E1000_IAC 0x04100 /* Interrupt Assertion Count */
967#define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */
968#define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */
969#define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */
970#define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */
971#define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */
972#define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */
973#define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
974#define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */
1da177e4 975#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
2d7edb92 976#define E1000_RFCTL 0x05008 /* Receive Filter Control*/
1da177e4
LT		 977#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
978#define E1000_RA 0x05400 /* Receive Address - RW Array */
979#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
980#define E1000_WUC 0x05800 /* Wakeup Control - RW */
981#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
982#define E1000_WUS 0x05810 /* Wakeup Status - RO */
983#define E1000_MANC 0x05820 /* Management Control - RW */
984#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
985#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
986#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
987#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
988#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
989#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
990#define E1000_HOST_IF 0x08800 /* Host Interface */
991#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
992#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
993
2d7edb92
MC		 994#define E1000_GCR 0x05B00 /* PCI-Ex Control */
995#define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */
996#define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */
997#define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */
998#define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */
999#define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */
1000#define E1000_SWSM 0x05B50 /* SW Semaphore */
1001#define E1000_FWSM 0x05B54 /* FW Semaphore */
1002#define E1000_FFLT_DBG 0x05F04 /* Debug Register */
1003#define E1000_HICR 0x08F00 /* Host Inteface Control */
868d5309
MC		 1004
1005/* RSS registers */
1006#define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */
1007#define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */
1008#define E1000_RETA 0x05C00 /* Redirection Table - RW Array */
1009#define E1000_RSSRK 0x05C80 /* RSS Random Key - RW Array */
1010#define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */
1011#define E1000_RSSIR 0x05868 /* RSS Interrupt Request */
1da177e4
LT		 1012/* Register Set (82542)
1013 *
1014 * Some of the 82542 registers are located at different offsets than they are
1015 * in more current versions of the 8254x. Despite the difference in location,
1016 * the registers function in the same manner.
1017 */
1018#define E1000_82542_CTRL E1000_CTRL
1019#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
1020#define E1000_82542_STATUS E1000_STATUS
1021#define E1000_82542_EECD E1000_EECD
1022#define E1000_82542_EERD E1000_EERD
1023#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
1024#define E1000_82542_FLA E1000_FLA
1025#define E1000_82542_MDIC E1000_MDIC
868d5309 1026#define E1000_82542_SCTL E1000_SCTL
1da177e4
LT		 1027#define E1000_82542_FCAL E1000_FCAL
1028#define E1000_82542_FCAH E1000_FCAH
1029#define E1000_82542_FCT E1000_FCT
1030#define E1000_82542_VET E1000_VET
1031#define E1000_82542_RA 0x00040
1032#define E1000_82542_ICR E1000_ICR
1033#define E1000_82542_ITR E1000_ITR
1034#define E1000_82542_ICS E1000_ICS
1035#define E1000_82542_IMS E1000_IMS
1036#define E1000_82542_IMC E1000_IMC
1037#define E1000_82542_RCTL E1000_RCTL
1038#define E1000_82542_RDTR 0x00108
1039#define E1000_82542_RDBAL 0x00110
1040#define E1000_82542_RDBAH 0x00114
1041#define E1000_82542_RDLEN 0x00118
1042#define E1000_82542_RDH 0x00120
1043#define E1000_82542_RDT 0x00128
868d5309
MC		 1044#define E1000_82542_RDTR0 E1000_82542_RDTR
1045#define E1000_82542_RDBAL0 E1000_82542_RDBAL
1046#define E1000_82542_RDBAH0 E1000_82542_RDBAH
1047#define E1000_82542_RDLEN0 E1000_82542_RDLEN
1048#define E1000_82542_RDH0 E1000_82542_RDH
1049#define E1000_82542_RDT0 E1000_82542_RDT
1050#define E1000_82542_RDTR1 0x00130
1051#define E1000_82542_RDBAL1 0x00138
1052#define E1000_82542_RDBAH1 0x0013C
1053#define E1000_82542_RDLEN1 0x00140
1054#define E1000_82542_RDH1 0x00148
1055#define E1000_82542_RDT1 0x00150
1da177e4
LT		 1056#define E1000_82542_FCRTH 0x00160
1057#define E1000_82542_FCRTL 0x00168
1058#define E1000_82542_FCTTV E1000_FCTTV
1059#define E1000_82542_TXCW E1000_TXCW
1060#define E1000_82542_RXCW E1000_RXCW
1061#define E1000_82542_MTA 0x00200
1062#define E1000_82542_TCTL E1000_TCTL
1063#define E1000_82542_TIPG E1000_TIPG
1064#define E1000_82542_TDBAL 0x00420
1065#define E1000_82542_TDBAH 0x00424
1066#define E1000_82542_TDLEN 0x00428
1067#define E1000_82542_TDH 0x00430
1068#define E1000_82542_TDT 0x00438
1069#define E1000_82542_TIDV 0x00440
1070#define E1000_82542_TBT E1000_TBT
1071#define E1000_82542_AIT E1000_AIT
1072#define E1000_82542_VFTA 0x00600
1073#define E1000_82542_LEDCTL E1000_LEDCTL
1074#define E1000_82542_PBA E1000_PBA
2d7edb92
MC		 1075#define E1000_82542_PBS E1000_PBS
1076#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1077#define E1000_82542_EEARBC E1000_EEARBC
1078#define E1000_82542_FLASHT E1000_FLASHT
1079#define E1000_82542_EEWR E1000_EEWR
1080#define E1000_82542_FLSWCTL E1000_FLSWCTL
1081#define E1000_82542_FLSWDATA E1000_FLSWDATA
1082#define E1000_82542_FLSWCNT E1000_FLSWCNT
1083#define E1000_82542_FLOP E1000_FLOP
1084#define E1000_82542_EXTCNF_CTRL E1000_EXTCNF_CTRL
1085#define E1000_82542_EXTCNF_SIZE E1000_EXTCNF_SIZE
1086#define E1000_82542_ERT E1000_ERT
1da177e4
LT		 1087#define E1000_82542_RXDCTL E1000_RXDCTL
1088#define E1000_82542_RADV E1000_RADV
1089#define E1000_82542_RSRPD E1000_RSRPD
1090#define E1000_82542_TXDMAC E1000_TXDMAC
1091#define E1000_82542_TDFHS E1000_TDFHS
1092#define E1000_82542_TDFTS E1000_TDFTS
1093#define E1000_82542_TDFPC E1000_TDFPC
1094#define E1000_82542_TXDCTL E1000_TXDCTL
1095#define E1000_82542_TADV E1000_TADV
1096#define E1000_82542_TSPMT E1000_TSPMT
1097#define E1000_82542_CRCERRS E1000_CRCERRS
1098#define E1000_82542_ALGNERRC E1000_ALGNERRC
1099#define E1000_82542_SYMERRS E1000_SYMERRS
1100#define E1000_82542_RXERRC E1000_RXERRC
1101#define E1000_82542_MPC E1000_MPC
1102#define E1000_82542_SCC E1000_SCC
1103#define E1000_82542_ECOL E1000_ECOL
1104#define E1000_82542_MCC E1000_MCC
1105#define E1000_82542_LATECOL E1000_LATECOL
1106#define E1000_82542_COLC E1000_COLC
1107#define E1000_82542_DC E1000_DC
1108#define E1000_82542_TNCRS E1000_TNCRS
1109#define E1000_82542_SEC E1000_SEC
1110#define E1000_82542_CEXTERR E1000_CEXTERR
1111#define E1000_82542_RLEC E1000_RLEC
1112#define E1000_82542_XONRXC E1000_XONRXC
1113#define E1000_82542_XONTXC E1000_XONTXC
1114#define E1000_82542_XOFFRXC E1000_XOFFRXC
1115#define E1000_82542_XOFFTXC E1000_XOFFTXC
1116#define E1000_82542_FCRUC E1000_FCRUC
1117#define E1000_82542_PRC64 E1000_PRC64
1118#define E1000_82542_PRC127 E1000_PRC127
1119#define E1000_82542_PRC255 E1000_PRC255
1120#define E1000_82542_PRC511 E1000_PRC511
1121#define E1000_82542_PRC1023 E1000_PRC1023
1122#define E1000_82542_PRC1522 E1000_PRC1522
1123#define E1000_82542_GPRC E1000_GPRC
1124#define E1000_82542_BPRC E1000_BPRC
1125#define E1000_82542_MPRC E1000_MPRC
1126#define E1000_82542_GPTC E1000_GPTC
1127#define E1000_82542_GORCL E1000_GORCL
1128#define E1000_82542_GORCH E1000_GORCH
1129#define E1000_82542_GOTCL E1000_GOTCL
1130#define E1000_82542_GOTCH E1000_GOTCH
1131#define E1000_82542_RNBC E1000_RNBC
1132#define E1000_82542_RUC E1000_RUC
1133#define E1000_82542_RFC E1000_RFC
1134#define E1000_82542_ROC E1000_ROC
1135#define E1000_82542_RJC E1000_RJC
1136#define E1000_82542_MGTPRC E1000_MGTPRC
1137#define E1000_82542_MGTPDC E1000_MGTPDC
1138#define E1000_82542_MGTPTC E1000_MGTPTC
1139#define E1000_82542_TORL E1000_TORL
1140#define E1000_82542_TORH E1000_TORH
1141#define E1000_82542_TOTL E1000_TOTL
1142#define E1000_82542_TOTH E1000_TOTH
1143#define E1000_82542_TPR E1000_TPR
1144#define E1000_82542_TPT E1000_TPT
1145#define E1000_82542_PTC64 E1000_PTC64
1146#define E1000_82542_PTC127 E1000_PTC127
1147#define E1000_82542_PTC255 E1000_PTC255
1148#define E1000_82542_PTC511 E1000_PTC511
1149#define E1000_82542_PTC1023 E1000_PTC1023
1150#define E1000_82542_PTC1522 E1000_PTC1522
1151#define E1000_82542_MPTC E1000_MPTC
1152#define E1000_82542_BPTC E1000_BPTC
1153#define E1000_82542_TSCTC E1000_TSCTC
1154#define E1000_82542_TSCTFC E1000_TSCTFC
1155#define E1000_82542_RXCSUM E1000_RXCSUM
1156#define E1000_82542_WUC E1000_WUC
1157#define E1000_82542_WUFC E1000_WUFC
1158#define E1000_82542_WUS E1000_WUS
1159#define E1000_82542_MANC E1000_MANC
1160#define E1000_82542_IPAV E1000_IPAV
1161#define E1000_82542_IP4AT E1000_IP4AT
1162#define E1000_82542_IP6AT E1000_IP6AT
1163#define E1000_82542_WUPL E1000_WUPL
1164#define E1000_82542_WUPM E1000_WUPM
1165#define E1000_82542_FFLT E1000_FFLT
1166#define E1000_82542_TDFH 0x08010
1167#define E1000_82542_TDFT 0x08018
1168#define E1000_82542_FFMT E1000_FFMT
1169#define E1000_82542_FFVT E1000_FFVT
1170#define E1000_82542_HOST_IF E1000_HOST_IF
2d7edb92
MC		 1171#define E1000_82542_IAM E1000_IAM
1172#define E1000_82542_EEMNGCTL E1000_EEMNGCTL
1173#define E1000_82542_PSRCTL E1000_PSRCTL
1174#define E1000_82542_RAID E1000_RAID
1175#define E1000_82542_TARC0 E1000_TARC0
1176#define E1000_82542_TDBAL1 E1000_TDBAL1
1177#define E1000_82542_TDBAH1 E1000_TDBAH1
1178#define E1000_82542_TDLEN1 E1000_TDLEN1
1179#define E1000_82542_TDH1 E1000_TDH1
1180#define E1000_82542_TDT1 E1000_TDT1
1181#define E1000_82542_TXDCTL1 E1000_TXDCTL1
1182#define E1000_82542_TARC1 E1000_TARC1
1183#define E1000_82542_RFCTL E1000_RFCTL
1184#define E1000_82542_GCR E1000_GCR
1185#define E1000_82542_GSCL_1 E1000_GSCL_1
1186#define E1000_82542_GSCL_2 E1000_GSCL_2
1187#define E1000_82542_GSCL_3 E1000_GSCL_3
1188#define E1000_82542_GSCL_4 E1000_GSCL_4
1189#define E1000_82542_FACTPS E1000_FACTPS
1190#define E1000_82542_SWSM E1000_SWSM
1191#define E1000_82542_FWSM E1000_FWSM
1192#define E1000_82542_FFLT_DBG E1000_FFLT_DBG
1193#define E1000_82542_IAC E1000_IAC
1194#define E1000_82542_ICRXPTC E1000_ICRXPTC
1195#define E1000_82542_ICRXATC E1000_ICRXATC
1196#define E1000_82542_ICTXPTC E1000_ICTXPTC
1197#define E1000_82542_ICTXATC E1000_ICTXATC
1198#define E1000_82542_ICTXQEC E1000_ICTXQEC
1199#define E1000_82542_ICTXQMTC E1000_ICTXQMTC
1200#define E1000_82542_ICRXDMTC E1000_ICRXDMTC
1201#define E1000_82542_ICRXOC E1000_ICRXOC
1202#define E1000_82542_HICR E1000_HICR
1da177e4 1203
868d5309
MC		 1204#define E1000_82542_CPUVEC E1000_CPUVEC
1205#define E1000_82542_MRQC E1000_MRQC
1206#define E1000_82542_RETA E1000_RETA
1207#define E1000_82542_RSSRK E1000_RSSRK
1208#define E1000_82542_RSSIM E1000_RSSIM
1209#define E1000_82542_RSSIR E1000_RSSIR
1210
1da177e4
LT		 1211/* Statistics counters collected by the MAC */
1212struct e1000_hw_stats {
1213 uint64_t crcerrs;
1214 uint64_t algnerrc;
1215 uint64_t symerrs;
1216 uint64_t rxerrc;
1217 uint64_t mpc;
1218 uint64_t scc;
1219 uint64_t ecol;
1220 uint64_t mcc;
1221 uint64_t latecol;
1222 uint64_t colc;
1223 uint64_t dc;
1224 uint64_t tncrs;
1225 uint64_t sec;
1226 uint64_t cexterr;
1227 uint64_t rlec;
1228 uint64_t xonrxc;
1229 uint64_t xontxc;
1230 uint64_t xoffrxc;
1231 uint64_t xofftxc;
1232 uint64_t fcruc;
1233 uint64_t prc64;
1234 uint64_t prc127;
1235 uint64_t prc255;
1236 uint64_t prc511;
1237 uint64_t prc1023;
1238 uint64_t prc1522;
1239 uint64_t gprc;
1240 uint64_t bprc;
1241 uint64_t mprc;
1242 uint64_t gptc;
1243 uint64_t gorcl;
1244 uint64_t gorch;
1245 uint64_t gotcl;
1246 uint64_t gotch;
1247 uint64_t rnbc;
1248 uint64_t ruc;
1249 uint64_t rfc;
1250 uint64_t roc;
1251 uint64_t rjc;
1252 uint64_t mgprc;
1253 uint64_t mgpdc;
1254 uint64_t mgptc;
1255 uint64_t torl;
1256 uint64_t torh;
1257 uint64_t totl;
1258 uint64_t toth;
1259 uint64_t tpr;
1260 uint64_t tpt;
1261 uint64_t ptc64;
1262 uint64_t ptc127;
1263 uint64_t ptc255;
1264 uint64_t ptc511;
1265 uint64_t ptc1023;
1266 uint64_t ptc1522;
1267 uint64_t mptc;
1268 uint64_t bptc;
1269 uint64_t tsctc;
1270 uint64_t tsctfc;
2d7edb92
MC		 1271 uint64_t iac;
1272 uint64_t icrxptc;
1273 uint64_t icrxatc;
1274 uint64_t ictxptc;
1275 uint64_t ictxatc;
1276 uint64_t ictxqec;
1277 uint64_t ictxqmtc;
1278 uint64_t icrxdmtc;
1279 uint64_t icrxoc;
1da177e4
LT		 1280};
1281
1282/* Structure containing variables used by the shared code (e1000_hw.c) */
1283struct e1000_hw {
1bea9add 1284 uint8_t __iomem *hw_addr;
2d7edb92 1285 uint8_t *flash_address;
1da177e4
LT		 1286 e1000_mac_type mac_type;
1287 e1000_phy_type phy_type;
1288 uint32_t phy_init_script;
1289 e1000_media_type media_type;
1290 void *back;
1291 e1000_fc_type fc;
1292 e1000_bus_speed bus_speed;
1293 e1000_bus_width bus_width;
1294 e1000_bus_type bus_type;
1295 struct e1000_eeprom_info eeprom;
1296 e1000_ms_type master_slave;
1297 e1000_ms_type original_master_slave;
1298 e1000_ffe_config ffe_config_state;
1299 uint32_t asf_firmware_present;
2d7edb92 1300 uint32_t eeprom_semaphore_present;
1da177e4
LT		 1301 unsigned long io_base;
1302 uint32_t phy_id;
1303 uint32_t phy_revision;
1304 uint32_t phy_addr;
1305 uint32_t original_fc;
1306 uint32_t txcw;
1307 uint32_t autoneg_failed;
1308 uint32_t max_frame_size;
1309 uint32_t min_frame_size;
1310 uint32_t mc_filter_type;
1311 uint32_t num_mc_addrs;
1312 uint32_t collision_delta;
1313 uint32_t tx_packet_delta;
1314 uint32_t ledctl_default;
1315 uint32_t ledctl_mode1;
1316 uint32_t ledctl_mode2;
2d7edb92
MC		 1317 boolean_t tx_pkt_filtering;
1318 struct e1000_host_mng_dhcp_cookie mng_cookie;
1da177e4
LT		 1319 uint16_t phy_spd_default;
1320 uint16_t autoneg_advertised;
1321 uint16_t pci_cmd_word;
1322 uint16_t fc_high_water;
1323 uint16_t fc_low_water;
1324 uint16_t fc_pause_time;
1325 uint16_t current_ifs_val;
1326 uint16_t ifs_min_val;
1327 uint16_t ifs_max_val;
1328 uint16_t ifs_step_size;
1329 uint16_t ifs_ratio;
1330 uint16_t device_id;
1331 uint16_t vendor_id;
1332 uint16_t subsystem_id;
1333 uint16_t subsystem_vendor_id;
1334 uint8_t revision_id;
1335 uint8_t autoneg;
1336 uint8_t mdix;
1337 uint8_t forced_speed_duplex;
1338 uint8_t wait_autoneg_complete;
1339 uint8_t dma_fairness;
1340 uint8_t mac_addr[NODE_ADDRESS_SIZE];
1341 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
1342 boolean_t disable_polarity_correction;
1343 boolean_t speed_downgraded;
1344 e1000_smart_speed smart_speed;
1345 e1000_dsp_config dsp_config_state;
1346 boolean_t get_link_status;
1347 boolean_t serdes_link_down;
1348 boolean_t tbi_compatibility_en;
1349 boolean_t tbi_compatibility_on;
868d5309 1350 boolean_t laa_is_present;
1da177e4
LT		 1351 boolean_t phy_reset_disable;
1352 boolean_t fc_send_xon;
1353 boolean_t fc_strict_ieee;
1354 boolean_t report_tx_early;
1355 boolean_t adaptive_ifs;
1356 boolean_t ifs_params_forced;
1357 boolean_t in_ifs_mode;
2d7edb92 1358 boolean_t mng_reg_access_disabled;
1da177e4
LT		 1359};
1360
1361
1362#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
1363#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
2d7edb92
MC		 1364#define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */
1365#define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
1366#define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */
1367#define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1368#define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */
1369#define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */
1da177e4
LT		 1370/* Register Bit Masks */
1371/* Device Control */
1372#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
1373#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
1374#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
2d7edb92 1375#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
1da177e4
LT		 1376#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
1377#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
1378#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
1379#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
1380#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
1381#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
1382#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
1383#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
1384#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
1385#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
1386#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
1387#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
1388#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
868d5309 1389#define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */
2d7edb92 1390#define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
1da177e4
LT		 1391#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
1392#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
1393#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
1394#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
1395#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
1396#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
1397#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
1398#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
1399#define E1000_CTRL_RST 0x04000000 /* Global reset */
1400#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
1401#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
1402#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
1403#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
1404#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
1405
1406/* Device Status */
1407#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
1408#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
1409#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
2d7edb92 1410#define E1000_STATUS_FUNC_SHIFT 2
1da177e4
LT		 1411#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
1412#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
1413#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
1414#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
1415#define E1000_STATUS_SPEED_MASK 0x000000C0
1416#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
1417#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
1418#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
1419#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
2d7edb92
MC		 1420#define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */
1421#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
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LT		 1422#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
1423#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
1424#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
1425#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
1426#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
1427
1428/* Constants used to intrepret the masked PCI-X bus speed. */
1429#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
1430#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
1431#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
1432
1433/* EEPROM/Flash Control */
1434#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
1435#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
1436#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
1437#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
1438#define E1000_EECD_FWE_MASK 0x00000030
1439#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
1440#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
1441#define E1000_EECD_FWE_SHIFT 4
1442#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
1443#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
1444#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
1445#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
1446#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
1447 * (0-small, 1-large) */
1448#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
1449#ifndef E1000_EEPROM_GRANT_ATTEMPTS
1450#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1451#endif
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MC		 1452#define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */
1453#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */
1454#define E1000_EECD_SIZE_EX_SHIFT 11
1455#define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */
1456#define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */
1457#define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */
1458#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
1459#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
1460#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */
1461#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
fd803241 1462#define E1000_EECD_SECVAL_SHIFT 22
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MC		 1463#define E1000_STM_OPCODE 0xDB00
1464#define E1000_HICR_FW_RESET 0xC0
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LT		 1465
1466/* EEPROM Read */
1467#define E1000_EERD_START 0x00000001 /* Start Read */
1468#define E1000_EERD_DONE 0x00000010 /* Read Done */
1469#define E1000_EERD_ADDR_SHIFT 8
1470#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
1471#define E1000_EERD_DATA_SHIFT 16
1472#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
1473
1474/* SPI EEPROM Status Register */
1475#define EEPROM_STATUS_RDY_SPI 0x01
1476#define EEPROM_STATUS_WEN_SPI 0x02
1477#define EEPROM_STATUS_BP0_SPI 0x04
1478#define EEPROM_STATUS_BP1_SPI 0x08
1479#define EEPROM_STATUS_WPEN_SPI 0x80
1480
1481/* Extended Device Control */
1482#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
1483#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
1484#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
1485#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
1486#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
1487#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
1488#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
1489#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
1490#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
1491#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
1492#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
1493#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
1494#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
1495#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
1496#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
1497#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
1498#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
1499#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
f56799ea 1500#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
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LT		 1501#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
1502#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
1503#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
1504#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
1505#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
1506#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
1507#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
1508#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
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MC		 1509#define E1000_CTRL_EXT_CANC 0x04000000 /* Interrupt delay cancellation */
1510#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
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MC		 1511#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
1512#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */
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LT		 1513
1514/* MDI Control */
1515#define E1000_MDIC_DATA_MASK 0x0000FFFF
1516#define E1000_MDIC_REG_MASK 0x001F0000
1517#define E1000_MDIC_REG_SHIFT 16
1518#define E1000_MDIC_PHY_MASK 0x03E00000
1519#define E1000_MDIC_PHY_SHIFT 21
1520#define E1000_MDIC_OP_WRITE 0x04000000
1521#define E1000_MDIC_OP_READ 0x08000000
1522#define E1000_MDIC_READY 0x10000000
1523#define E1000_MDIC_INT_EN 0x20000000
1524#define E1000_MDIC_ERROR 0x40000000
1525
1526/* LED Control */
1527#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1528#define E1000_LEDCTL_LED0_MODE_SHIFT 0
2d7edb92 1529#define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020
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LT		 1530#define E1000_LEDCTL_LED0_IVRT 0x00000040
1531#define E1000_LEDCTL_LED0_BLINK 0x00000080
1532#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1533#define E1000_LEDCTL_LED1_MODE_SHIFT 8
2d7edb92 1534#define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000
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LT		 1535#define E1000_LEDCTL_LED1_IVRT 0x00004000
1536#define E1000_LEDCTL_LED1_BLINK 0x00008000
1537#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1538#define E1000_LEDCTL_LED2_MODE_SHIFT 16
2d7edb92 1539#define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000
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LT		 1540#define E1000_LEDCTL_LED2_IVRT 0x00400000
1541#define E1000_LEDCTL_LED2_BLINK 0x00800000
1542#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1543#define E1000_LEDCTL_LED3_MODE_SHIFT 24
868d5309 1544#define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000
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LT		 1545#define E1000_LEDCTL_LED3_IVRT 0x40000000
1546#define E1000_LEDCTL_LED3_BLINK 0x80000000
1547
1548#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1549#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1550#define E1000_LEDCTL_MODE_LINK_UP 0x2
1551#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1552#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1553#define E1000_LEDCTL_MODE_LINK_10 0x5
1554#define E1000_LEDCTL_MODE_LINK_100 0x6
1555#define E1000_LEDCTL_MODE_LINK_1000 0x7
1556#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1557#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1558#define E1000_LEDCTL_MODE_COLLISION 0xA
1559#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1560#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1561#define E1000_LEDCTL_MODE_PAUSED 0xD
1562#define E1000_LEDCTL_MODE_LED_ON 0xE
1563#define E1000_LEDCTL_MODE_LED_OFF 0xF
1564
1565/* Receive Address */
1566#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
1567
1568/* Interrupt Cause Read */
1569#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
1570#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
1571#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
1572#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
1573#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
1574#define E1000_ICR_RXO 0x00000040 /* rx overrun */
1575#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
1576#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
1577#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
1578#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
1579#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
1580#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
1581#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
1582#define E1000_ICR_TXD_LOW 0x00008000
1583#define E1000_ICR_SRPD 0x00010000
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MC		 1584#define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */
1585#define E1000_ICR_MNG 0x00040000 /* Manageability event */
1586#define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */
1587#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
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LT		 1588
1589/* Interrupt Cause Set */
1590#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1591#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1592#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
1593#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1594#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1595#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
1596#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1597#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1598#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1599#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1600#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1601#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1602#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1603#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1604#define E1000_ICS_SRPD E1000_ICR_SRPD
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MC		 1605#define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */
1606#define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */
1607#define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */
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LT		 1608
1609/* Interrupt Mask Set */
1610#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1611#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1612#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
1613#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1614#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1615#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
1616#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1617#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
1618#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1619#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1620#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1621#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1622#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1623#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1624#define E1000_IMS_SRPD E1000_ICR_SRPD
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MC		 1625#define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */
1626#define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */
1627#define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */
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LT		 1628
1629/* Interrupt Mask Clear */
1630#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
1631#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
1632#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
1633#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
1634#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
1635#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
1636#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
1637#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
1638#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
1639#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
1640#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
1641#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
1642#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
1643#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1644#define E1000_IMC_SRPD E1000_ICR_SRPD
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MC		 1645#define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */
1646#define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */
1647#define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */
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LT		 1648
1649/* Receive Control */
1650#define E1000_RCTL_RST 0x00000001 /* Software reset */
1651#define E1000_RCTL_EN 0x00000002 /* enable */
1652#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
1653#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
1654#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
1655#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
1656#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
1657#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
1658#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
1659#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
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MC		 1660#define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */
1661#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
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LT		 1662#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
1663#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
1664#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
1665#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
1666#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
1667#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
1668#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
1669#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
1670#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
1671#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
1672/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
1673#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
1674#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
1675#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
1676#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
1677/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
1678#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
1679#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
1680#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
1681#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
1682#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
1683#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
1684#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
1685#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
1686#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
1687#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
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MC		 1688#define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */
1689#define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */
1690
1691/* Use byte values for the following shift parameters
1692 * Usage:
1693 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
1694 * E1000_PSRCTL_BSIZE0_MASK) |
1695 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
1696 * E1000_PSRCTL_BSIZE1_MASK) |
1697 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
1698 * E1000_PSRCTL_BSIZE2_MASK) |
1699 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
1700 * E1000_PSRCTL_BSIZE3_MASK))
1701 * where value0 = [128..16256], default=256
1702 * value1 = [1024..64512], default=4096
1703 * value2 = [0..64512], default=4096
1704 * value3 = [0..64512], default=0
1705 */
1706
1707#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F
1708#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00
1709#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000
1710#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000
1711
1712#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */
1713#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
1714#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */
1715#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */
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LT		 1716
1717/* Receive Descriptor */
1718#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
1719#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
1720#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
1721#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
1722#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
1723
1724/* Flow Control */
1725#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
1726#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
1727#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
1728#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
1729
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MC		 1730/* Header split receive */
1731#define E1000_RFCTL_ISCSI_DIS 0x00000001
1732#define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E
1733#define E1000_RFCTL_ISCSI_DWC_SHIFT 1
1734#define E1000_RFCTL_NFSW_DIS 0x00000040
1735#define E1000_RFCTL_NFSR_DIS 0x00000080
1736#define E1000_RFCTL_NFS_VER_MASK 0x00000300
1737#define E1000_RFCTL_NFS_VER_SHIFT 8
1738#define E1000_RFCTL_IPV6_DIS 0x00000400
1739#define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800
1740#define E1000_RFCTL_ACK_DIS 0x00001000
1741#define E1000_RFCTL_ACKD_DIS 0x00002000
1742#define E1000_RFCTL_IPFRSP_DIS 0x00004000
1743#define E1000_RFCTL_EXTEN 0x00008000
1744#define E1000_RFCTL_IPV6_EX_DIS 0x00010000
1745#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1746
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LT		 1747/* Receive Descriptor Control */
1748#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
1749#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
1750#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
1751#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
1752
1753/* Transmit Descriptor Control */
1754#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
1755#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
1756#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
1757#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
1758#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
1759#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
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MC		 1760#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
1761 still to be processed. */
1da177e4
LT		 1762
1763/* Transmit Configuration Word */
1764#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
1765#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
1766#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
1767#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
1768#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
1769#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
1770#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
1771#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
1772#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
1773#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
1774
1775/* Receive Configuration Word */
1776#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
1777#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
1778#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
1779#define E1000_RXCW_CC 0x10000000 /* Receive config change */
1780#define E1000_RXCW_C 0x20000000 /* Receive config */
1781#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
1782#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
1783
1784/* Transmit Control */
1785#define E1000_TCTL_RST 0x00000001 /* software reset */
1786#define E1000_TCTL_EN 0x00000002 /* enable tx */
1787#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
1788#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
1789#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
1790#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
1791#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
1792#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
1793#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
1794#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
2d7edb92 1795#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */
1da177e4
LT		 1796
1797/* Receive Checksum Control */
1798#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
1799#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
1800#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
1801#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
2d7edb92
MC		 1802#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1803#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1804
868d5309
MC		 1805/* Multiple Receive Queue Control */
1806#define E1000_MRQC_ENABLE_MASK 0x00000003
1807#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
1808#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
1809#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
1810#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1811#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000
1812#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00040000
1813#define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1814#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000
1da177e4
LT		 1815
1816/* Definitions for power management and wakeup registers */
1817/* Wake Up Control */
1818#define E1000_WUC_APME 0x00000001 /* APM Enable */
1819#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
1820#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
1821#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
1822#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
1823
1824/* Wake Up Filter Control */
1825#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
1826#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
1827#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
1828#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
1829#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
1830#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
1831#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
1832#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
2d7edb92 1833#define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
1da177e4
LT		 1834#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
1835#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
1836#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
1837#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
1838#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
1839#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
1840#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1841
1842/* Wake Up Status */
1843#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
1844#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
1845#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
1846#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
1847#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
1848#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
1849#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
1850#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
1851#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
1852#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
1853#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
1854#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
1855#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
1856
1857/* Management Control */
1858#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
1859#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
1860#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
1861#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
1862#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
1863#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
1864#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
1865#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
1866#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
1867#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
1868 * Filtering */
2d7edb92 1869#define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */
1da177e4
LT		 1870#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
1871#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
1872#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
2d7edb92 1873#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
1da177e4
LT		 1874#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address
1875 * filtering */
1876#define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host
1877 * memory */
2d7edb92
MC		 1878#define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address
1879 * filtering */
1880#define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */
1881#define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */
1da177e4
LT		 1882#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
1883#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
1884#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
1885#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
1886#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
1887#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
1888
1889#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
1890#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
1891
2d7edb92
MC		 1892/* SW Semaphore Register */
1893#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1894#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1895#define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1896#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */
1897
1898/* FW Semaphore Register */
1899#define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */
1900#define E1000_FWSM_MODE_SHIFT 1
1901#define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */
1902
1903/* FFLT Debug Register */
1904#define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */
1905
1906typedef enum {
1907 e1000_mng_mode_none = 0,
1908 e1000_mng_mode_asf,
1909 e1000_mng_mode_pt,
1910 e1000_mng_mode_ipmi,
1911 e1000_mng_mode_host_interface_only
1912} e1000_mng_mode;
1913
1914/* Host Inteface Control Register */
1915#define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */
1916#define E1000_HICR_C 0x00000002 /* Driver sets this bit when done
1917 * to put command in RAM */
1918#define E1000_HICR_SV 0x00000004 /* Status Validity */
1919#define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */
1920
1921/* Host Interface Command Interface - Address range 0x8800-0x8EFF */
1922#define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */
1923#define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */
1924#define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */
1925#define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */
1926
1927struct e1000_host_command_header {
1928 uint8_t command_id;
1929 uint8_t command_length;
1930 uint8_t command_options; /* I/F bits for command, status for return */
1931 uint8_t checksum;
1932};
1933struct e1000_host_command_info {
1934 struct e1000_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */
1935 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */
1936};
1937
1938/* Host SMB register #0 */
1939#define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */
1940#define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */
1941#define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */
1942#define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */
1943
1944/* Host SMB register #1 */
1945#define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN
1946#define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN
1947#define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT
1948#define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT
1949
1950/* FW Status Register */
1951#define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */
1952
1da177e4
LT		 1953/* Wake Up Packet Length */
1954#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
1955
1956#define E1000_MDALIGN 4096
1957
868d5309 1958#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
2d7edb92
MC		 1959/* Function Active and Power State to MNG */
1960#define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003
1961#define E1000_FACTPS_LAN0_VALID 0x00000004
1962#define E1000_FACTPS_FUNC0_AUX_EN 0x00000008
1963#define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0
1964#define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6
1965#define E1000_FACTPS_LAN1_VALID 0x00000100
1966#define E1000_FACTPS_FUNC1_AUX_EN 0x00000200
1967#define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000
1968#define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12
1969#define E1000_FACTPS_IDE_ENABLE 0x00004000
1970#define E1000_FACTPS_FUNC2_AUX_EN 0x00008000
1971#define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000
1972#define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18
1973#define E1000_FACTPS_SP_ENABLE 0x00100000
1974#define E1000_FACTPS_FUNC3_AUX_EN 0x00200000
1975#define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000
1976#define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24
1977#define E1000_FACTPS_IPMI_ENABLE 0x04000000
1978#define E1000_FACTPS_FUNC4_AUX_EN 0x08000000
1979#define E1000_FACTPS_MNGCG 0x20000000
1980#define E1000_FACTPS_LAN_FUNC_SEL 0x40000000
1981#define E1000_FACTPS_PM_STATE_CHANGED 0x80000000
1982
1da177e4
LT		 1983/* EEPROM Commands - Microwire */
1984#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
1985#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
1986#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
1987#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
1988#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
1989
1990/* EEPROM Commands - SPI */
1991#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
2d7edb92
MC		 1992#define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1993#define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1994#define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1995#define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */
1996#define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */
1997#define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */
1998#define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */
1999#define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
2000#define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
2001#define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1da177e4
LT		 2002
2003/* EEPROM Size definitions */
2d7edb92
MC		 2004#define EEPROM_WORD_SIZE_SHIFT 6
2005#define EEPROM_SIZE_SHIFT 10
1da177e4
LT		 2006#define EEPROM_SIZE_MASK 0x1C00
2007
2008/* EEPROM Word Offsets */
2009#define EEPROM_COMPAT 0x0003
2010#define EEPROM_ID_LED_SETTINGS 0x0004
868d5309 2011#define EEPROM_VERSION 0x0005
1da177e4
LT		 2012#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
2013#define EEPROM_PHY_CLASS_WORD 0x0007
2014#define EEPROM_INIT_CONTROL1_REG 0x000A
2015#define EEPROM_INIT_CONTROL2_REG 0x000F
2016#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
2017#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
2018#define EEPROM_CFG 0x0012
2019#define EEPROM_FLASH_VERSION 0x0032
2020#define EEPROM_CHECKSUM_REG 0x003F
2021
868d5309
MC		 2022#define E1000_EEPROM_CFG_DONE 0x00040000 /* MNG config cycle done */
2023
1da177e4
LT		 2024/* Word definitions for ID LED Settings */
2025#define ID_LED_RESERVED_0000 0x0000
2026#define ID_LED_RESERVED_FFFF 0xFFFF
2027#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
2028 (ID_LED_OFF1_OFF2 << 8) | \
2029 (ID_LED_DEF1_DEF2 << 4) | \
2030 (ID_LED_DEF1_DEF2))
2031#define ID_LED_DEF1_DEF2 0x1
2032#define ID_LED_DEF1_ON2 0x2
2033#define ID_LED_DEF1_OFF2 0x3
2034#define ID_LED_ON1_DEF2 0x4
2035#define ID_LED_ON1_ON2 0x5
2036#define ID_LED_ON1_OFF2 0x6
2037#define ID_LED_OFF1_DEF2 0x7
2038#define ID_LED_OFF1_ON2 0x8
2039#define ID_LED_OFF1_OFF2 0x9
2040
2041#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
2042#define IGP_ACTIVITY_LED_ENABLE 0x0300
2043#define IGP_LED3_MODE 0x07000000
2044
2045
2046/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
2047#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
2048
2049/* Mask bit for PHY class in Word 7 of the EEPROM */
2050#define EEPROM_PHY_CLASS_A 0x8000
2051
2052/* Mask bits for fields in Word 0x0a of the EEPROM */
2053#define EEPROM_WORD0A_ILOS 0x0010
2054#define EEPROM_WORD0A_SWDPIO 0x01E0
2055#define EEPROM_WORD0A_LRST 0x0200
2056#define EEPROM_WORD0A_FD 0x0400
2057#define EEPROM_WORD0A_66MHZ 0x0800
2058
2059/* Mask bits for fields in Word 0x0f of the EEPROM */
2060#define EEPROM_WORD0F_PAUSE_MASK 0x3000
2061#define EEPROM_WORD0F_PAUSE 0x1000
2062#define EEPROM_WORD0F_ASM_DIR 0x2000
2063#define EEPROM_WORD0F_ANE 0x0800
2064#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
2065
2066/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
2067#define EEPROM_SUM 0xBABA
2068
2069/* EEPROM Map defines (WORD OFFSETS)*/
2070#define EEPROM_NODE_ADDRESS_BYTE_0 0
2071#define EEPROM_PBA_BYTE_1 8
2072
2073#define EEPROM_RESERVED_WORD 0xFFFF
2074
2075/* EEPROM Map Sizes (Byte Counts) */
2076#define PBA_SIZE 4
2077
2078/* Collision related configuration parameters */
2079#define E1000_COLLISION_THRESHOLD 15
2080#define E1000_CT_SHIFT 4
2081#define E1000_COLLISION_DISTANCE 64
2082#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2083#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
2084#define E1000_COLD_SHIFT 12
2085
2086/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
2087#define REQ_TX_DESCRIPTOR_MULTIPLE 8
2088#define REQ_RX_DESCRIPTOR_MULTIPLE 8
2089
2090/* Default values for the transmit IPG register */
2091#define DEFAULT_82542_TIPG_IPGT 10
2092#define DEFAULT_82543_TIPG_IPGT_FIBER 9
2093#define DEFAULT_82543_TIPG_IPGT_COPPER 8
2094
2095#define E1000_TIPG_IPGT_MASK 0x000003FF
2096#define E1000_TIPG_IPGR1_MASK 0x000FFC00
2097#define E1000_TIPG_IPGR2_MASK 0x3FF00000
2098
2099#define DEFAULT_82542_TIPG_IPGR1 2
2100#define DEFAULT_82543_TIPG_IPGR1 8
2101#define E1000_TIPG_IPGR1_SHIFT 10
2102
2103#define DEFAULT_82542_TIPG_IPGR2 10
2104#define DEFAULT_82543_TIPG_IPGR2 6
2105#define E1000_TIPG_IPGR2_SHIFT 20
2106
2107#define E1000_TXDMAC_DPP 0x00000001
2108
2109/* Adaptive IFS defines */
2110#define TX_THRESHOLD_START 8
2111#define TX_THRESHOLD_INCREMENT 10
2112#define TX_THRESHOLD_DECREMENT 1
2113#define TX_THRESHOLD_STOP 190
2114#define TX_THRESHOLD_DISABLE 0
2115#define TX_THRESHOLD_TIMER_MS 10000
2116#define MIN_NUM_XMITS 1000
2117#define IFS_MAX 80
2118#define IFS_STEP 10
2119#define IFS_MIN 40
2120#define IFS_RATIO 4
2121
2d7edb92
MC		 2122/* Extended Configuration Control and Size */
2123#define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001
2124#define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002
2125#define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004
2126#define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008
2127#define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010
2128#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020
2129#define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040
2130#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x1FFF0000
2131
2132#define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF
2133#define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00
2134#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000
2135
1da177e4 2136/* PBA constants */
2d7edb92 2137#define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */
1da177e4
LT		 2138#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
2139#define E1000_PBA_22K 0x0016
2140#define E1000_PBA_24K 0x0018
2141#define E1000_PBA_30K 0x001E
868d5309
MC		 2142#define E1000_PBA_32K 0x0020
2143#define E1000_PBA_38K 0x0026
1da177e4
LT		 2144#define E1000_PBA_40K 0x0028
2145#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
2146
2147/* Flow Control Constants */
2148#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
2149#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
2150#define FLOW_CONTROL_TYPE 0x8808
2151
2152/* The historical defaults for the flow control values are given below. */
2153#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
2154#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
2155#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
2156
2157/* PCIX Config space */
2158#define PCIX_COMMAND_REGISTER 0xE6
2159#define PCIX_STATUS_REGISTER_LO 0xE8
2160#define PCIX_STATUS_REGISTER_HI 0xEA
2161
2162#define PCIX_COMMAND_MMRBC_MASK 0x000C
2163#define PCIX_COMMAND_MMRBC_SHIFT 0x2
2164#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
2165#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
2166#define PCIX_STATUS_HI_MMRBC_4K 0x3
2167#define PCIX_STATUS_HI_MMRBC_2K 0x2
2168
2169
2170/* Number of bits required to shift right the "pause" bits from the
2171 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
2172 */
2173#define PAUSE_SHIFT 5
2174
2175/* Number of bits required to shift left the "SWDPIO" bits from the
2176 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
2177 */
2178#define SWDPIO_SHIFT 17
2179
2180/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
2181 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
2182 */
2183#define SWDPIO__EXT_SHIFT 4
2184
2185/* Number of bits required to shift left the "ILOS" bit from the EEPROM
2186 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
2187 */
2188#define ILOS_SHIFT 3
2189
2190
2191#define RECEIVE_BUFFER_ALIGN_SIZE (256)
2192
2193/* Number of milliseconds we wait for auto-negotiation to complete */
2194#define LINK_UP_TIMEOUT 500
2195
2d7edb92
MC		 2196/* Number of 100 microseconds we wait for PCI Express master disable */
2197#define MASTER_DISABLE_TIMEOUT 800
2198/* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */
2199#define AUTO_READ_DONE_TIMEOUT 10
2200/* Number of milliseconds we wait for PHY configuration done after MAC reset */
2201#define PHY_CFG_TIMEOUT 40
2202
1da177e4
LT		 2203#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
2204
2205/* The carrier extension symbol, as received by the NIC. */
2206#define CARRIER_EXTENSION 0x0F
2207
2208/* TBI_ACCEPT macro definition:
2209 *
2210 * This macro requires:
2211 * adapter = a pointer to struct e1000_hw
2212 * status = the 8 bit status field of the RX descriptor with EOP set
2213 * error = the 8 bit error field of the RX descriptor with EOP set
2214 * length = the sum of all the length fields of the RX descriptors that
2215 * make up the current frame
2216 * last_byte = the last byte of the frame DMAed by the hardware
2217 * max_frame_length = the maximum frame length we want to accept.
2218 * min_frame_length = the minimum frame length we want to accept.
2219 *
2220 * This macro is a conditional that should be used in the interrupt
2221 * handler's Rx processing routine when RxErrors have been detected.
2222 *
2223 * Typical use:
2224 * ...
2225 * if (TBI_ACCEPT) {
2226 * accept_frame = TRUE;
2227 * e1000_tbi_adjust_stats(adapter, MacAddress);
2228 * frame_length--;
2229 * } else {
2230 * accept_frame = FALSE;
2231 * }
2232 * ...
2233 */
2234
2235#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
2236 ((adapter)->tbi_compatibility_on && \
2237 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
2238 ((last_byte) == CARRIER_EXTENSION) && \
2239 (((status) & E1000_RXD_STAT_VP) ? \
2240 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
2241 ((length) <= ((adapter)->max_frame_size + 1))) : \
2242 (((length) > (adapter)->min_frame_size) && \
2243 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
2244
2245
2246/* Structures, enums, and macros for the PHY */
2247
2248/* Bit definitions for the Management Data IO (MDIO) and Management Data
2249 * Clock (MDC) pins in the Device Control Register.
2250 */
2251#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
2252#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
2253#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
2254#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
2255#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
2256#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
2257#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
2258#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
2259
2260/* PHY 1000 MII Register/Bit Definitions */
2261/* PHY Registers defined by IEEE */
2262#define PHY_CTRL 0x00 /* Control Register */
2263#define PHY_STATUS 0x01 /* Status Regiser */
2264#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
2265#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
2266#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
2267#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
2268#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
2269#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
2270#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
2271#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
2272#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
2273#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
2274
2275#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
2276#define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */
2277
2278/* M88E1000 Specific Registers */
2279#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
2280#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
2281#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
2282#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
2283#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
2284#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
2285
2286#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
2287#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
2288#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
2289#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
2290#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
2291
2292#define IGP01E1000_IEEE_REGS_PAGE 0x0000
2293#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
2294#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
2295
2296/* IGP01E1000 Specific Registers */
2297#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
2298#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
2299#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
2300#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
2301#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
2302#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
2d7edb92 2303#define IGP02E1000_PHY_POWER_MGMT 0x19
1da177e4
LT		 2304#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
2305
2306/* IGP01E1000 AGC Registers - stores the cable length values*/
2307#define IGP01E1000_PHY_AGC_A 0x1172
2308#define IGP01E1000_PHY_AGC_B 0x1272
2309#define IGP01E1000_PHY_AGC_C 0x1472
2310#define IGP01E1000_PHY_AGC_D 0x1872
2311
2d7edb92
MC		 2312/* IGP02E1000 AGC Registers for cable length values */
2313#define IGP02E1000_PHY_AGC_A 0x11B1
2314#define IGP02E1000_PHY_AGC_B 0x12B1
2315#define IGP02E1000_PHY_AGC_C 0x14B1
2316#define IGP02E1000_PHY_AGC_D 0x18B1
2317
1da177e4
LT		 2318/* IGP01E1000 DSP Reset Register */
2319#define IGP01E1000_PHY_DSP_RESET 0x1F33
2320#define IGP01E1000_PHY_DSP_SET 0x1F71
2321#define IGP01E1000_PHY_DSP_FFE 0x1F35
2322
2323#define IGP01E1000_PHY_CHANNEL_NUM 4
2d7edb92
MC		 2324#define IGP02E1000_PHY_CHANNEL_NUM 4
2325
1da177e4
LT		 2326#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
2327#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
2328#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
2329#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
2330
2331#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
2332#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
2333
2334#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
2335#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
2336#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
2337#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
2338
2339#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
2340/* IGP01E1000 PCS Initialization register - stores the polarity status when
2341 * speed = 1000 Mbps. */
2342#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
2343#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
2344
2345#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
2346
2347
2348/* PHY Control Register */
2349#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
2350#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
2351#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
2352#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
2353#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
2354#define MII_CR_POWER_DOWN 0x0800 /* Power down */
2355#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
2356#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
2357#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
2358#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
2359
2360/* PHY Status Register */
2361#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
2362#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
2363#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
2364#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
2365#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
2366#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
2367#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
2368#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
2369#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
2370#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
2371#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
2372#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
2373#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
2374#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
2375#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
2376
2377/* Autoneg Advertisement Register */
2378#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
2379#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
2380#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
2381#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
2382#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
2383#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
2384#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
2385#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
2386#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
2387#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2388
2389/* Link Partner Ability Register (Base Page) */
2390#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
2391#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
2392#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
2393#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
2394#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
2395#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
2396#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
2397#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
2398#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
2399#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
2400#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
2401
2402/* Autoneg Expansion Register */
2403#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
2404#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
2405#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
2406#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
2407#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
2408
2409/* Next Page TX Register */
2410#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2411#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
2412 * of different NP
2413 */
2414#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2415 * 0 = cannot comply with msg
2416 */
2417#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2418#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2419 * 0 = sending last NP
2420 */
2421
2422/* Link Partner Next Page Register */
2423#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
2424#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
2425 * of different NP
2426 */
2427#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
2428 * 0 = cannot comply with msg
2429 */
2430#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
2431#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
2432#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
2433 * 0 = sending last NP
2434 */
2435
2436/* 1000BASE-T Control Register */
2437#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
2438#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
2439#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
2440#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
2441 /* 0=DTE device */
2442#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
2443 /* 0=Configure PHY as Slave */
2444#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
2445 /* 0=Automatic Master/Slave config */
2446#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
2447#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
2448#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
2449#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
2450#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
2451
2452/* 1000BASE-T Status Register */
2453#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
2454#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
2455#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
2456#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
2457#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
2458#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
2459#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
2460#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
2461#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
2462#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
2463#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
2464#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
2465#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
2466
2467/* Extended Status Register */
2468#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
2469#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
2470#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
2471#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
2472
2473#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
2474#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
2475
2476#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
2477 /* (0=enable, 1=disable) */
2478
2479/* M88E1000 PHY Specific Control Register */
2480#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
2481#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
2482#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
2483#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
2484 * 0=CLK125 toggling
2485 */
2486#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
2487 /* Manual MDI configuration */
2488#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
2489#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2490 * 100BASE-TX/10BASE-T:
2491 * MDI Mode
2492 */
2493#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
2494 * all speeds.
2495 */
2496#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
2497 /* 1=Enable Extended 10BASE-T distance
2498 * (Lower 10BASE-T RX Threshold)
2499 * 0=Normal 10BASE-T RX Threshold */
2500#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
2501 /* 1=5-Bit interface in 100BASE-TX
2502 * 0=MII interface in 100BASE-TX */
2503#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
2504#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
2505#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
2506
2507#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
2508#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
2509#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
2510
2511/* M88E1000 PHY Specific Status Register */
2512#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
2513#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
2514#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
2515#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
2516#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
2517 * 3=110-140M;4=>140M */
2518#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
2519#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
2520#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
2521#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
2522#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
2523#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
2524#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
2525#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
2526
2527#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
2528#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
2529#define M88E1000_PSSR_MDIX_SHIFT 6
2530#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
2531
2532/* M88E1000 Extended PHY Specific Control Register */
2533#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
2534#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
2535 * Will assert lost lock and bring
2536 * link down if idle not seen
2537 * within 1ms in 1000BASE-T
2538 */
2539/* Number of times we will attempt to autonegotiate before downshifting if we
2540 * are the master */
2541#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
2542#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
2543#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
2544#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
2545#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
2546/* Number of times we will attempt to autonegotiate before downshifting if we
2547 * are the slave */
2548#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
2549#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
2550#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
2551#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
2552#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
2553#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
2554#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
2555#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
2556
2557/* IGP01E1000 Specific Port Config Register - R/W */
2558#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
2559#define IGP01E1000_PSCFR_PRE_EN 0x0020
2560#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
2561#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
2562#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
2563#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
2564
2565/* IGP01E1000 Specific Port Status Register - R/O */
2566#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
2567#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
2568#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
2569#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
2570#define IGP01E1000_PSSR_LINK_UP 0x0400
2571#define IGP01E1000_PSSR_MDIX 0x0800
2572#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
2573#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
2574#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
2575#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
2576#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
2577#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
2578
2579/* IGP01E1000 Specific Port Control Register - R/W */
2580#define IGP01E1000_PSCR_TP_LOOPBACK 0x0010
2581#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
2582#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
2583#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
2584#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
2585#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
2586
2587/* IGP01E1000 Specific Port Link Health Register */
2588#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
2589#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
2590#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
2591#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
2592#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
2593#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
2594#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
2595#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
2596#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040
2597#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010
2598#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008
2599#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004
2600#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002
2601#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001
2602
2603/* IGP01E1000 Channel Quality Register */
2604#define IGP01E1000_MSE_CHANNEL_D 0x000F
2605#define IGP01E1000_MSE_CHANNEL_C 0x00F0
2606#define IGP01E1000_MSE_CHANNEL_B 0x0F00
2607#define IGP01E1000_MSE_CHANNEL_A 0xF000
2608
2d7edb92
MC		 2609#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */
2610#define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */
2611#define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */
2612
1da177e4
LT		 2613/* IGP01E1000 DSP reset macros */
2614#define DSP_RESET_ENABLE 0x0
2615#define DSP_RESET_DISABLE 0x2
2616#define E1000_MAX_DSP_RESETS 10
2617
2d7edb92 2618/* IGP01E1000 & IGP02E1000 AGC Registers */
1da177e4
LT		 2619
2620#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
2d7edb92
MC		 2621#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */
2622
2623/* IGP02E1000 AGC Register Length 9-bit mask */
2624#define IGP02E1000_AGC_LENGTH_MASK 0x7F
1da177e4
LT		 2625
2626/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
2627#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
868d5309 2628#define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113
1da177e4 2629
2d7edb92 2630/* The precision error of the cable length is +/- 10 meters */
1da177e4 2631#define IGP01E1000_AGC_RANGE 10
868d5309 2632#define IGP02E1000_AGC_RANGE 15
1da177e4
LT		 2633
2634/* IGP01E1000 PCS Initialization register */
2635/* bits 3:6 in the PCS registers stores the channels polarity */
2636#define IGP01E1000_PHY_POLARITY_MASK 0x0078
2637
2638/* IGP01E1000 GMII FIFO Register */
2639#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
2640 * on Link-Up */
2641#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
2642
2643/* IGP01E1000 Analog Register */
2644#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
2645#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
2646#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
2647#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
2648
2649#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
2650#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
2651#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
2652#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
2653#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
2654
2655#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
2656#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
2657#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
2658#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
2659
2660
2661/* Bit definitions for valid PHY IDs. */
2662/* I = Integrated
2663 * E = External
2664 */
2665#define M88E1000_E_PHY_ID 0x01410C50
2666#define M88E1000_I_PHY_ID 0x01410C30
2667#define M88E1011_I_PHY_ID 0x01410C20
2668#define IGP01E1000_I_PHY_ID 0x02A80380
2669#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
2670#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
2671#define M88E1011_I_REV_4 0x04
2d7edb92
MC		 2672#define M88E1111_I_PHY_ID 0x01410CC0
2673#define L1LXT971A_PHY_ID 0x001378E0
1da177e4
LT		 2674
2675/* Miscellaneous PHY bit definitions. */
2676#define PHY_PREAMBLE 0xFFFFFFFF
2677#define PHY_SOF 0x01
2678#define PHY_OP_READ 0x02
2679#define PHY_OP_WRITE 0x01
2680#define PHY_TURNAROUND 0x02
2681#define PHY_PREAMBLE_SIZE 32
2682#define MII_CR_SPEED_1000 0x0040
2683#define MII_CR_SPEED_100 0x2000
2684#define MII_CR_SPEED_10 0x0000
2685#define E1000_PHY_ADDRESS 0x01
2686#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
2687#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
2688#define PHY_REVISION_MASK 0xFFFFFFF0
2689#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
2690#define REG4_SPEED_MASK 0x01E0
2691#define REG9_SPEED_MASK 0x0300
2692#define ADVERTISE_10_HALF 0x0001
2693#define ADVERTISE_10_FULL 0x0002
2694#define ADVERTISE_100_HALF 0x0004
2695#define ADVERTISE_100_FULL 0x0008
2696#define ADVERTISE_1000_HALF 0x0010
2697#define ADVERTISE_1000_FULL 0x0020
2698#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
2699#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
2700#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
2701
2702#endif /* _E1000_HW_H_ */
Linux kernel - Deliverables
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