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[PATCH] e1000: Fix SoL/IDER link and loopback
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
3
2648345f 4 Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
1da177e4
LT		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
9 any later version.
10
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
20 The full GNU General Public License is included in this distribution in the
21 file called LICENSE.
22
23 Contact Information:
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
30
31/* Change Log
2b02893e
MC		 32 * 6.0.58 4/20/05
33 * o Accepted ethtool cleanup patch from Stephen Hemminger
2648345f
MC		 34 * 6.0.44+ 2/15/05
35 * o applied Anton's patch to resolve tx hang in hardware
36 * o Applied Andrew Mortons patch - e1000 stops working after resume
1da177e4
LT		 37 */
38
39char e1000_driver_name[] = "e1000";
3ad2cc67 40static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 41#ifndef CONFIG_E1000_NAPI
42#define DRIVERNAPI
43#else
44#define DRIVERNAPI "-NAPI"
45#endif
4ee9c020 46#define DRV_VERSION "6.3.9-k2"DRIVERNAPI
1da177e4 47char e1000_driver_version[] = DRV_VERSION;
3ad2cc67 48static char e1000_copyright[] = "Copyright (c) 1999-2005 Intel Corporation.";
1da177e4
LT		 49
50/* e1000_pci_tbl - PCI Device ID Table
51 *
52 * Last entry must be all 0s
53 *
54 * Macro expands to...
55 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
56 */
57static struct pci_device_id e1000_pci_tbl[] = {
58 INTEL_E1000_ETHERNET_DEVICE(0x1000),
59 INTEL_E1000_ETHERNET_DEVICE(0x1001),
60 INTEL_E1000_ETHERNET_DEVICE(0x1004),
61 INTEL_E1000_ETHERNET_DEVICE(0x1008),
62 INTEL_E1000_ETHERNET_DEVICE(0x1009),
63 INTEL_E1000_ETHERNET_DEVICE(0x100C),
64 INTEL_E1000_ETHERNET_DEVICE(0x100D),
65 INTEL_E1000_ETHERNET_DEVICE(0x100E),
66 INTEL_E1000_ETHERNET_DEVICE(0x100F),
67 INTEL_E1000_ETHERNET_DEVICE(0x1010),
68 INTEL_E1000_ETHERNET_DEVICE(0x1011),
69 INTEL_E1000_ETHERNET_DEVICE(0x1012),
70 INTEL_E1000_ETHERNET_DEVICE(0x1013),
71 INTEL_E1000_ETHERNET_DEVICE(0x1014),
72 INTEL_E1000_ETHERNET_DEVICE(0x1015),
73 INTEL_E1000_ETHERNET_DEVICE(0x1016),
74 INTEL_E1000_ETHERNET_DEVICE(0x1017),
75 INTEL_E1000_ETHERNET_DEVICE(0x1018),
76 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 77 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 78 INTEL_E1000_ETHERNET_DEVICE(0x101D),
79 INTEL_E1000_ETHERNET_DEVICE(0x101E),
80 INTEL_E1000_ETHERNET_DEVICE(0x1026),
81 INTEL_E1000_ETHERNET_DEVICE(0x1027),
82 INTEL_E1000_ETHERNET_DEVICE(0x1028),
07b8fede
MC		 83 INTEL_E1000_ETHERNET_DEVICE(0x105E),
84 INTEL_E1000_ETHERNET_DEVICE(0x105F),
85 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 86 INTEL_E1000_ETHERNET_DEVICE(0x1075),
87 INTEL_E1000_ETHERNET_DEVICE(0x1076),
88 INTEL_E1000_ETHERNET_DEVICE(0x1077),
89 INTEL_E1000_ETHERNET_DEVICE(0x1078),
90 INTEL_E1000_ETHERNET_DEVICE(0x1079),
91 INTEL_E1000_ETHERNET_DEVICE(0x107A),
92 INTEL_E1000_ETHERNET_DEVICE(0x107B),
93 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 94 INTEL_E1000_ETHERNET_DEVICE(0x107D),
95 INTEL_E1000_ETHERNET_DEVICE(0x107E),
96 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 97 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 98 INTEL_E1000_ETHERNET_DEVICE(0x108B),
99 INTEL_E1000_ETHERNET_DEVICE(0x108C),
07b8fede 100 INTEL_E1000_ETHERNET_DEVICE(0x109A),
1da177e4
LT		 101 /* required last entry */
102 {0,}
103};
104
105MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
106
107int e1000_up(struct e1000_adapter *adapter);
108void e1000_down(struct e1000_adapter *adapter);
109void e1000_reset(struct e1000_adapter *adapter);
110int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
581d708e
MC		 111int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
112int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
113void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
114void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67
AB		 115static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
116 struct e1000_tx_ring *txdr);
117static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
118 struct e1000_rx_ring *rxdr);
119static void e1000_free_tx_resources(struct e1000_adapter *adapter,
120 struct e1000_tx_ring *tx_ring);
121static void e1000_free_rx_resources(struct e1000_adapter *adapter,
122 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 123void e1000_update_stats(struct e1000_adapter *adapter);
124
125/* Local Function Prototypes */
126
127static int e1000_init_module(void);
128static void e1000_exit_module(void);
129static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
130static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e
MC		 131static int e1000_alloc_queues(struct e1000_adapter *adapter);
132#ifdef CONFIG_E1000_MQ
133static void e1000_setup_queue_mapping(struct e1000_adapter *adapter);
134#endif
1da177e4
LT		 135static int e1000_sw_init(struct e1000_adapter *adapter);
136static int e1000_open(struct net_device *netdev);
137static int e1000_close(struct net_device *netdev);
138static void e1000_configure_tx(struct e1000_adapter *adapter);
139static void e1000_configure_rx(struct e1000_adapter *adapter);
140static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 141static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
142static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
143static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
144 struct e1000_tx_ring *tx_ring);
145static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
146 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 147static void e1000_set_multi(struct net_device *netdev);
148static void e1000_update_phy_info(unsigned long data);
149static void e1000_watchdog(unsigned long data);
150static void e1000_watchdog_task(struct e1000_adapter *adapter);
151static void e1000_82547_tx_fifo_stall(unsigned long data);
152static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
153static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
154static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
155static int e1000_set_mac(struct net_device *netdev, void *p);
156static irqreturn_t e1000_intr(int irq, void *data, struct pt_regs *regs);
581d708e
MC		 157static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
158 struct e1000_tx_ring *tx_ring);
1da177e4 159#ifdef CONFIG_E1000_NAPI
581d708e 160static int e1000_clean(struct net_device *poll_dev, int *budget);
1da177e4 161static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 162 struct e1000_rx_ring *rx_ring,
1da177e4 163 int *work_done, int work_to_do);
2d7edb92 164static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 165 struct e1000_rx_ring *rx_ring,
2d7edb92 166 int *work_done, int work_to_do);
1da177e4 167#else
581d708e
MC		 168static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
169 struct e1000_rx_ring *rx_ring);
170static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
171 struct e1000_rx_ring *rx_ring);
1da177e4 172#endif
581d708e
MC		 173static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
174 struct e1000_rx_ring *rx_ring);
175static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
176 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 177static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
178static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
179 int cmd);
180void e1000_set_ethtool_ops(struct net_device *netdev);
181static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
182static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
183static void e1000_tx_timeout(struct net_device *dev);
184static void e1000_tx_timeout_task(struct net_device *dev);
185static void e1000_smartspeed(struct e1000_adapter *adapter);
186static inline int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
187 struct sk_buff *skb);
188
189static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
190static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
191static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
192static void e1000_restore_vlan(struct e1000_adapter *adapter);
193
1da177e4 194#ifdef CONFIG_PM
977e74b5 195static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
1da177e4
LT		 196static int e1000_resume(struct pci_dev *pdev);
197#endif
198
199#ifdef CONFIG_NET_POLL_CONTROLLER
200/* for netdump / net console */
201static void e1000_netpoll (struct net_device *netdev);
202#endif
203
24025e4e
MC		 204#ifdef CONFIG_E1000_MQ
205/* for multiple Rx queues */
206void e1000_rx_schedule(void *data);
207#endif
208
1da177e4
LT		 209/* Exported from other modules */
210
211extern void e1000_check_options(struct e1000_adapter *adapter);
212
213static struct pci_driver e1000_driver = {
214 .name = e1000_driver_name,
215 .id_table = e1000_pci_tbl,
216 .probe = e1000_probe,
217 .remove = __devexit_p(e1000_remove),
218 /* Power Managment Hooks */
219#ifdef CONFIG_PM
220 .suspend = e1000_suspend,
221 .resume = e1000_resume
222#endif
223};
224
225MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
226MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
227MODULE_LICENSE("GPL");
228MODULE_VERSION(DRV_VERSION);
229
230static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
231module_param(debug, int, 0);
232MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
233
234/**
235 * e1000_init_module - Driver Registration Routine
236 *
237 * e1000_init_module is the first routine called when the driver is
238 * loaded. All it does is register with the PCI subsystem.
239 **/
240
241static int __init
242e1000_init_module(void)
243{
244 int ret;
245 printk(KERN_INFO "%s - version %s\n",
246 e1000_driver_string, e1000_driver_version);
247
248 printk(KERN_INFO "%s\n", e1000_copyright);
249
250 ret = pci_module_init(&e1000_driver);
8b378def 251
1da177e4
LT		 252 return ret;
253}
254
255module_init(e1000_init_module);
256
257/**
258 * e1000_exit_module - Driver Exit Cleanup Routine
259 *
260 * e1000_exit_module is called just before the driver is removed
261 * from memory.
262 **/
263
264static void __exit
265e1000_exit_module(void)
266{
1da177e4
LT		 267 pci_unregister_driver(&e1000_driver);
268}
269
270module_exit(e1000_exit_module);
271
272/**
273 * e1000_irq_disable - Mask off interrupt generation on the NIC
274 * @adapter: board private structure
275 **/
276
277static inline void
278e1000_irq_disable(struct e1000_adapter *adapter)
279{
280 atomic_inc(&adapter->irq_sem);
281 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
282 E1000_WRITE_FLUSH(&adapter->hw);
283 synchronize_irq(adapter->pdev->irq);
284}
285
286/**
287 * e1000_irq_enable - Enable default interrupt generation settings
288 * @adapter: board private structure
289 **/
290
291static inline void
292e1000_irq_enable(struct e1000_adapter *adapter)
293{
294 if(likely(atomic_dec_and_test(&adapter->irq_sem))) {
295 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
296 E1000_WRITE_FLUSH(&adapter->hw);
297 }
298}
3ad2cc67
AB		 299
300static void
2d7edb92
MC		 301e1000_update_mng_vlan(struct e1000_adapter *adapter)
302{
303 struct net_device *netdev = adapter->netdev;
304 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
305 uint16_t old_vid = adapter->mng_vlan_id;
306 if(adapter->vlgrp) {
307 if(!adapter->vlgrp->vlan_devices[vid]) {
308 if(adapter->hw.mng_cookie.status &
309 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
310 e1000_vlan_rx_add_vid(netdev, vid);
311 adapter->mng_vlan_id = vid;
312 } else
313 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
314
315 if((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
316 (vid != old_vid) &&
317 !adapter->vlgrp->vlan_devices[old_vid])
318 e1000_vlan_rx_kill_vid(netdev, old_vid);
319 }
320 }
321}
322
1da177e4
LT		 323int
324e1000_up(struct e1000_adapter *adapter)
325{
326 struct net_device *netdev = adapter->netdev;
581d708e 327 int i, err;
1da177e4
LT		 328
329 /* hardware has been reset, we need to reload some things */
330
331 /* Reset the PHY if it was previously powered down */
332 if(adapter->hw.media_type == e1000_media_type_copper) {
333 uint16_t mii_reg;
334 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
335 if(mii_reg & MII_CR_POWER_DOWN)
336 e1000_phy_reset(&adapter->hw);
337 }
338
339 e1000_set_multi(netdev);
340
341 e1000_restore_vlan(adapter);
342
343 e1000_configure_tx(adapter);
344 e1000_setup_rctl(adapter);
345 e1000_configure_rx(adapter);
581d708e
MC		 346 for (i = 0; i < adapter->num_queues; i++)
347 adapter->alloc_rx_buf(adapter, &adapter->rx_ring[i]);
1da177e4 348
fa4f7ef3
MC		 349#ifdef CONFIG_PCI_MSI
350 if(adapter->hw.mac_type > e1000_82547_rev_2) {
351 adapter->have_msi = TRUE;
352 if((err = pci_enable_msi(adapter->pdev))) {
353 DPRINTK(PROBE, ERR,
354 "Unable to allocate MSI interrupt Error: %d\n", err);
355 adapter->have_msi = FALSE;
356 }
357 }
358#endif
1da177e4
LT		 359 if((err = request_irq(adapter->pdev->irq, &e1000_intr,
360 SA_SHIRQ | SA_SAMPLE_RANDOM,
2648345f
MC		 361 netdev->name, netdev))) {
362 DPRINTK(PROBE, ERR,
363 "Unable to allocate interrupt Error: %d\n", err);
1da177e4 364 return err;
2648345f 365 }
1da177e4
LT		 366
367 mod_timer(&adapter->watchdog_timer, jiffies);
1da177e4
LT		 368
369#ifdef CONFIG_E1000_NAPI
370 netif_poll_enable(netdev);
371#endif
5de55624
MC		 372 e1000_irq_enable(adapter);
373
1da177e4
LT		 374 return 0;
375}
376
377void
378e1000_down(struct e1000_adapter *adapter)
379{
380 struct net_device *netdev = adapter->netdev;
57128197
JK		 381 boolean_t mng_mode_enabled = (adapter->hw.mac_type >= e1000_82571) &&
382 e1000_check_mng_mode(&adapter->hw);
1da177e4
LT		 383
384 e1000_irq_disable(adapter);
24025e4e
MC		 385#ifdef CONFIG_E1000_MQ
386 while (atomic_read(&adapter->rx_sched_call_data.count) != 0);
387#endif
1da177e4 388 free_irq(adapter->pdev->irq, netdev);
fa4f7ef3
MC		 389#ifdef CONFIG_PCI_MSI
390 if(adapter->hw.mac_type > e1000_82547_rev_2 &&
391 adapter->have_msi == TRUE)
392 pci_disable_msi(adapter->pdev);
393#endif
1da177e4
LT		 394 del_timer_sync(&adapter->tx_fifo_stall_timer);
395 del_timer_sync(&adapter->watchdog_timer);
396 del_timer_sync(&adapter->phy_info_timer);
397
398#ifdef CONFIG_E1000_NAPI
399 netif_poll_disable(netdev);
400#endif
401 adapter->link_speed = 0;
402 adapter->link_duplex = 0;
403 netif_carrier_off(netdev);
404 netif_stop_queue(netdev);
405
406 e1000_reset(adapter);
581d708e
MC		 407 e1000_clean_all_tx_rings(adapter);
408 e1000_clean_all_rx_rings(adapter);
1da177e4 409
57128197
JK		 410 /* Power down the PHY so no link is implied when interface is down *
411 * The PHY cannot be powered down if any of the following is TRUE *
412 * (a) WoL is enabled
413 * (b) AMT is active
414 * (c) SoL/IDER session is active */
415 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
2d7edb92 416 adapter->hw.media_type == e1000_media_type_copper &&
57128197
JK		 417 !(E1000_READ_REG(&adapter->hw, MANC) & E1000_MANC_SMBUS_EN) &&
418 !mng_mode_enabled &&
419 !e1000_check_phy_reset_block(&adapter->hw)) {
1da177e4
LT		 420 uint16_t mii_reg;
421 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
422 mii_reg |= MII_CR_POWER_DOWN;
423 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
4e48a2b9 424 mdelay(1);
1da177e4
LT		 425 }
426}
427
428void
429e1000_reset(struct e1000_adapter *adapter)
430{
1125ecbc 431 struct net_device *netdev = adapter->netdev;
2d7edb92 432 uint32_t pba, manc;
1125ecbc
MC		 433 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
434 uint16_t fc_low_water_mark = E1000_FC_LOW_DIFF;
1da177e4
LT		 435
436 /* Repartition Pba for greater than 9k mtu
437 * To take effect CTRL.RST is required.
438 */
439
2d7edb92
MC		 440 switch (adapter->hw.mac_type) {
441 case e1000_82547:
0e6ef3e0 442 case e1000_82547_rev_2:
2d7edb92
MC		 443 pba = E1000_PBA_30K;
444 break;
868d5309
MC		 445 case e1000_82571:
446 case e1000_82572:
447 pba = E1000_PBA_38K;
448 break;
2d7edb92
MC		 449 case e1000_82573:
450 pba = E1000_PBA_12K;
451 break;
452 default:
453 pba = E1000_PBA_48K;
454 break;
455 }
456
1125ecbc 457 if((adapter->hw.mac_type != e1000_82573) &&
4ee9c020 458 (adapter->netdev->mtu > E1000_RXBUFFER_8192)) {
1125ecbc
MC		 459 pba -= 8; /* allocate more FIFO for Tx */
460 /* send an XOFF when there is enough space in the
461 * Rx FIFO to hold one extra full size Rx packet
462 */
463 fc_high_water_mark = netdev->mtu + ENET_HEADER_SIZE +
464 ETHERNET_FCS_SIZE + 1;
465 fc_low_water_mark = fc_high_water_mark + 8;
466 }
2d7edb92
MC		 467
468
469 if(adapter->hw.mac_type == e1000_82547) {
1da177e4
LT		 470 adapter->tx_fifo_head = 0;
471 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
472 adapter->tx_fifo_size =
473 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
474 atomic_set(&adapter->tx_fifo_stall, 0);
475 }
2d7edb92 476
1da177e4
LT		 477 E1000_WRITE_REG(&adapter->hw, PBA, pba);
478
479 /* flow control settings */
480 adapter->hw.fc_high_water = (pba << E1000_PBA_BYTES_SHIFT) -
1125ecbc 481 fc_high_water_mark;
1da177e4 482 adapter->hw.fc_low_water = (pba << E1000_PBA_BYTES_SHIFT) -
1125ecbc 483 fc_low_water_mark;
1da177e4
LT		 484 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
485 adapter->hw.fc_send_xon = 1;
486 adapter->hw.fc = adapter->hw.original_fc;
487
2d7edb92 488 /* Allow time for pending master requests to run */
1da177e4
LT		 489 e1000_reset_hw(&adapter->hw);
490 if(adapter->hw.mac_type >= e1000_82544)
491 E1000_WRITE_REG(&adapter->hw, WUC, 0);
492 if(e1000_init_hw(&adapter->hw))
493 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 494 e1000_update_mng_vlan(adapter);
1da177e4
LT		 495 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
496 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
497
498 e1000_reset_adaptive(&adapter->hw);
499 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2d7edb92
MC		 500 if (adapter->en_mng_pt) {
501 manc = E1000_READ_REG(&adapter->hw, MANC);
502 manc |= (E1000_MANC_ARP_EN | E1000_MANC_EN_MNG2HOST);
503 E1000_WRITE_REG(&adapter->hw, MANC, manc);
504 }
1da177e4
LT		 505}
506
507/**
508 * e1000_probe - Device Initialization Routine
509 * @pdev: PCI device information struct
510 * @ent: entry in e1000_pci_tbl
511 *
512 * Returns 0 on success, negative on failure
513 *
514 * e1000_probe initializes an adapter identified by a pci_dev structure.
515 * The OS initialization, configuring of the adapter private structure,
516 * and a hardware reset occur.
517 **/
518
519static int __devinit
520e1000_probe(struct pci_dev *pdev,
521 const struct pci_device_id *ent)
522{
523 struct net_device *netdev;
524 struct e1000_adapter *adapter;
2d7edb92 525 unsigned long mmio_start, mmio_len;
868d5309 526 uint32_t ctrl_ext;
2d7edb92
MC		 527 uint32_t swsm;
528
1da177e4 529 static int cards_found = 0;
2d7edb92 530 int i, err, pci_using_dac;
1da177e4
LT		 531 uint16_t eeprom_data;
532 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
1da177e4
LT		 533 if((err = pci_enable_device(pdev)))
534 return err;
535
536 if(!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
537 pci_using_dac = 1;
538 } else {
539 if((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
540 E1000_ERR("No usable DMA configuration, aborting\n");
541 return err;
542 }
543 pci_using_dac = 0;
544 }
545
546 if((err = pci_request_regions(pdev, e1000_driver_name)))
547 return err;
548
549 pci_set_master(pdev);
550
551 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
552 if(!netdev) {
553 err = -ENOMEM;
554 goto err_alloc_etherdev;
555 }
556
557 SET_MODULE_OWNER(netdev);
558 SET_NETDEV_DEV(netdev, &pdev->dev);
559
560 pci_set_drvdata(pdev, netdev);
60490fe0 561 adapter = netdev_priv(netdev);
1da177e4
LT		 562 adapter->netdev = netdev;
563 adapter->pdev = pdev;
564 adapter->hw.back = adapter;
565 adapter->msg_enable = (1 << debug) - 1;
566
567 mmio_start = pci_resource_start(pdev, BAR_0);
568 mmio_len = pci_resource_len(pdev, BAR_0);
569
570 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
571 if(!adapter->hw.hw_addr) {
572 err = -EIO;
573 goto err_ioremap;
574 }
575
576 for(i = BAR_1; i <= BAR_5; i++) {
577 if(pci_resource_len(pdev, i) == 0)
578 continue;
579 if(pci_resource_flags(pdev, i) & IORESOURCE_IO) {
580 adapter->hw.io_base = pci_resource_start(pdev, i);
581 break;
582 }
583 }
584
585 netdev->open = &e1000_open;
586 netdev->stop = &e1000_close;
587 netdev->hard_start_xmit = &e1000_xmit_frame;
588 netdev->get_stats = &e1000_get_stats;
589 netdev->set_multicast_list = &e1000_set_multi;
590 netdev->set_mac_address = &e1000_set_mac;
591 netdev->change_mtu = &e1000_change_mtu;
592 netdev->do_ioctl = &e1000_ioctl;
593 e1000_set_ethtool_ops(netdev);
594 netdev->tx_timeout = &e1000_tx_timeout;
595 netdev->watchdog_timeo = 5 * HZ;
596#ifdef CONFIG_E1000_NAPI
597 netdev->poll = &e1000_clean;
598 netdev->weight = 64;
599#endif
600 netdev->vlan_rx_register = e1000_vlan_rx_register;
601 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
602 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
603#ifdef CONFIG_NET_POLL_CONTROLLER
604 netdev->poll_controller = e1000_netpoll;
605#endif
606 strcpy(netdev->name, pci_name(pdev));
607
608 netdev->mem_start = mmio_start;
609 netdev->mem_end = mmio_start + mmio_len;
610 netdev->base_addr = adapter->hw.io_base;
611
612 adapter->bd_number = cards_found;
613
614 /* setup the private structure */
615
616 if((err = e1000_sw_init(adapter)))
617 goto err_sw_init;
618
2d7edb92
MC		 619 if((err = e1000_check_phy_reset_block(&adapter->hw)))
620 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
621
1da177e4
LT		 622 if(adapter->hw.mac_type >= e1000_82543) {
623 netdev->features = NETIF_F_SG |
624 NETIF_F_HW_CSUM |
625 NETIF_F_HW_VLAN_TX |
626 NETIF_F_HW_VLAN_RX |
627 NETIF_F_HW_VLAN_FILTER;
628 }
629
630#ifdef NETIF_F_TSO
631 if((adapter->hw.mac_type >= e1000_82544) &&
632 (adapter->hw.mac_type != e1000_82547))
633 netdev->features |= NETIF_F_TSO;
2d7edb92
MC		 634
635#ifdef NETIF_F_TSO_IPV6
636 if(adapter->hw.mac_type > e1000_82547_rev_2)
637 netdev->features |= NETIF_F_TSO_IPV6;
638#endif
1da177e4
LT		 639#endif
640 if(pci_using_dac)
641 netdev->features |= NETIF_F_HIGHDMA;
642
643 /* hard_start_xmit is safe against parallel locking */
644 netdev->features |= NETIF_F_LLTX;
645
2d7edb92
MC		 646 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
647
1da177e4
LT		 648 /* before reading the EEPROM, reset the controller to
649 * put the device in a known good starting state */
650
651 e1000_reset_hw(&adapter->hw);
652
653 /* make sure the EEPROM is good */
654
655 if(e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
656 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
657 err = -EIO;
658 goto err_eeprom;
659 }
660
661 /* copy the MAC address out of the EEPROM */
662
2648345f 663 if(e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 664 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
665 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 666 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 667
9beb0ac1 668 if(!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4
LT		 669 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
670 err = -EIO;
671 goto err_eeprom;
672 }
673
674 e1000_read_part_num(&adapter->hw, &(adapter->part_num));
675
676 e1000_get_bus_info(&adapter->hw);
677
678 init_timer(&adapter->tx_fifo_stall_timer);
679 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
680 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
681
682 init_timer(&adapter->watchdog_timer);
683 adapter->watchdog_timer.function = &e1000_watchdog;
684 adapter->watchdog_timer.data = (unsigned long) adapter;
685
686 INIT_WORK(&adapter->watchdog_task,
687 (void (*)(void *))e1000_watchdog_task, adapter);
688
689 init_timer(&adapter->phy_info_timer);
690 adapter->phy_info_timer.function = &e1000_update_phy_info;
691 adapter->phy_info_timer.data = (unsigned long) adapter;
692
693 INIT_WORK(&adapter->tx_timeout_task,
694 (void (*)(void *))e1000_tx_timeout_task, netdev);
695
696 /* we're going to reset, so assume we have no link for now */
697
698 netif_carrier_off(netdev);
699 netif_stop_queue(netdev);
700
701 e1000_check_options(adapter);
702
703 /* Initial Wake on LAN setting
704 * If APM wake is enabled in the EEPROM,
705 * enable the ACPI Magic Packet filter
706 */
707
708 switch(adapter->hw.mac_type) {
709 case e1000_82542_rev2_0:
710 case e1000_82542_rev2_1:
711 case e1000_82543:
712 break;
713 case e1000_82544:
714 e1000_read_eeprom(&adapter->hw,
715 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
716 eeprom_apme_mask = E1000_EEPROM_82544_APM;
717 break;
718 case e1000_82546:
719 case e1000_82546_rev_3:
fd803241 720 case e1000_82571:
1da177e4
LT		 721 if((E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
722 && (adapter->hw.media_type == e1000_media_type_copper)) {
723 e1000_read_eeprom(&adapter->hw,
724 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
725 break;
726 }
727 /* Fall Through */
728 default:
729 e1000_read_eeprom(&adapter->hw,
730 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
731 break;
732 }
733 if(eeprom_data & eeprom_apme_mask)
734 adapter->wol |= E1000_WUFC_MAG;
735
736 /* reset the hardware with the new settings */
737 e1000_reset(adapter);
738
2d7edb92
MC		 739 /* Let firmware know the driver has taken over */
740 switch(adapter->hw.mac_type) {
868d5309
MC		 741 case e1000_82571:
742 case e1000_82572:
743 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
744 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
745 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
746 break;
2d7edb92
MC		 747 case e1000_82573:
748 swsm = E1000_READ_REG(&adapter->hw, SWSM);
749 E1000_WRITE_REG(&adapter->hw, SWSM,
750 swsm | E1000_SWSM_DRV_LOAD);
751 break;
752 default:
753 break;
754 }
755
1da177e4
LT		 756 strcpy(netdev->name, "eth%d");
757 if((err = register_netdev(netdev)))
758 goto err_register;
759
760 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
761
762 cards_found++;
763 return 0;
764
765err_register:
766err_sw_init:
767err_eeprom:
768 iounmap(adapter->hw.hw_addr);
769err_ioremap:
770 free_netdev(netdev);
771err_alloc_etherdev:
772 pci_release_regions(pdev);
773 return err;
774}
775
776/**
777 * e1000_remove - Device Removal Routine
778 * @pdev: PCI device information struct
779 *
780 * e1000_remove is called by the PCI subsystem to alert the driver
781 * that it should release a PCI device. The could be caused by a
782 * Hot-Plug event, or because the driver is going to be removed from
783 * memory.
784 **/
785
786static void __devexit
787e1000_remove(struct pci_dev *pdev)
788{
789 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 790 struct e1000_adapter *adapter = netdev_priv(netdev);
868d5309 791 uint32_t ctrl_ext;
2d7edb92 792 uint32_t manc, swsm;
581d708e
MC		 793#ifdef CONFIG_E1000_NAPI
794 int i;
795#endif
1da177e4 796
be2b28ed
JG		 797 flush_scheduled_work();
798
1da177e4
LT		 799 if(adapter->hw.mac_type >= e1000_82540 &&
800 adapter->hw.media_type == e1000_media_type_copper) {
801 manc = E1000_READ_REG(&adapter->hw, MANC);
802 if(manc & E1000_MANC_SMBUS_EN) {
803 manc |= E1000_MANC_ARP_EN;
804 E1000_WRITE_REG(&adapter->hw, MANC, manc);
805 }
806 }
807
2d7edb92 808 switch(adapter->hw.mac_type) {
868d5309
MC		 809 case e1000_82571:
810 case e1000_82572:
811 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
812 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
813 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
814 break;
2d7edb92
MC		 815 case e1000_82573:
816 swsm = E1000_READ_REG(&adapter->hw, SWSM);
817 E1000_WRITE_REG(&adapter->hw, SWSM,
818 swsm & ~E1000_SWSM_DRV_LOAD);
819 break;
820
821 default:
822 break;
823 }
824
1da177e4 825 unregister_netdev(netdev);
581d708e
MC		 826#ifdef CONFIG_E1000_NAPI
827 for (i = 0; i < adapter->num_queues; i++)
828 __dev_put(&adapter->polling_netdev[i]);
829#endif
1da177e4 830
2d7edb92
MC		 831 if(!e1000_check_phy_reset_block(&adapter->hw))
832 e1000_phy_hw_reset(&adapter->hw);
1da177e4 833
24025e4e
MC		 834 kfree(adapter->tx_ring);
835 kfree(adapter->rx_ring);
836#ifdef CONFIG_E1000_NAPI
837 kfree(adapter->polling_netdev);
838#endif
839
1da177e4
LT		 840 iounmap(adapter->hw.hw_addr);
841 pci_release_regions(pdev);
842
24025e4e
MC		 843#ifdef CONFIG_E1000_MQ
844 free_percpu(adapter->cpu_netdev);
845 free_percpu(adapter->cpu_tx_ring);
846#endif
1da177e4
LT		 847 free_netdev(netdev);
848
849 pci_disable_device(pdev);
850}
851
852/**
853 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
854 * @adapter: board private structure to initialize
855 *
856 * e1000_sw_init initializes the Adapter private data structure.
857 * Fields are initialized based on PCI device information and
858 * OS network device settings (MTU size).
859 **/
860
861static int __devinit
862e1000_sw_init(struct e1000_adapter *adapter)
863{
864 struct e1000_hw *hw = &adapter->hw;
865 struct net_device *netdev = adapter->netdev;
866 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 867#ifdef CONFIG_E1000_NAPI
868 int i;
869#endif
1da177e4
LT		 870
871 /* PCI config space info */
872
873 hw->vendor_id = pdev->vendor;
874 hw->device_id = pdev->device;
875 hw->subsystem_vendor_id = pdev->subsystem_vendor;
876 hw->subsystem_id = pdev->subsystem_device;
877
878 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
879
880 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
881
882 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2d7edb92 883 adapter->rx_ps_bsize0 = E1000_RXBUFFER_256;
1da177e4
LT		 884 hw->max_frame_size = netdev->mtu +
885 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
886 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
887
888 /* identify the MAC */
889
890 if(e1000_set_mac_type(hw)) {
891 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
892 return -EIO;
893 }
894
895 /* initialize eeprom parameters */
896
2d7edb92
MC		 897 if(e1000_init_eeprom_params(hw)) {
898 E1000_ERR("EEPROM initialization failed\n");
899 return -EIO;
900 }
1da177e4
LT		 901
902 switch(hw->mac_type) {
903 default:
904 break;
905 case e1000_82541:
906 case e1000_82547:
907 case e1000_82541_rev_2:
908 case e1000_82547_rev_2:
909 hw->phy_init_script = 1;
910 break;
911 }
912
913 e1000_set_media_type(hw);
914
915 hw->wait_autoneg_complete = FALSE;
916 hw->tbi_compatibility_en = TRUE;
917 hw->adaptive_ifs = TRUE;
918
919 /* Copper options */
920
921 if(hw->media_type == e1000_media_type_copper) {
922 hw->mdix = AUTO_ALL_MODES;
923 hw->disable_polarity_correction = FALSE;
924 hw->master_slave = E1000_MASTER_SLAVE;
925 }
926
24025e4e
MC		 927#ifdef CONFIG_E1000_MQ
928 /* Number of supported queues */
929 switch (hw->mac_type) {
930 case e1000_82571:
931 case e1000_82572:
932 adapter->num_queues = 2;
933 break;
934 default:
935 adapter->num_queues = 1;
936 break;
937 }
938 adapter->num_queues = min(adapter->num_queues, num_online_cpus());
939#else
581d708e 940 adapter->num_queues = 1;
24025e4e 941#endif
581d708e
MC		 942
943 if (e1000_alloc_queues(adapter)) {
944 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
945 return -ENOMEM;
946 }
947
948#ifdef CONFIG_E1000_NAPI
949 for (i = 0; i < adapter->num_queues; i++) {
950 adapter->polling_netdev[i].priv = adapter;
951 adapter->polling_netdev[i].poll = &e1000_clean;
952 adapter->polling_netdev[i].weight = 64;
953 dev_hold(&adapter->polling_netdev[i]);
954 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
955 }
956#endif
24025e4e
MC		 957
958#ifdef CONFIG_E1000_MQ
959 e1000_setup_queue_mapping(adapter);
960#endif
961
1da177e4
LT		 962 atomic_set(&adapter->irq_sem, 1);
963 spin_lock_init(&adapter->stats_lock);
1da177e4
LT		 964
965 return 0;
966}
967
581d708e
MC		 968/**
969 * e1000_alloc_queues - Allocate memory for all rings
970 * @adapter: board private structure to initialize
971 *
972 * We allocate one ring per queue at run-time since we don't know the
973 * number of queues at compile-time. The polling_netdev array is
974 * intended for Multiqueue, but should work fine with a single queue.
975 **/
976
977static int __devinit
978e1000_alloc_queues(struct e1000_adapter *adapter)
979{
980 int size;
981
982 size = sizeof(struct e1000_tx_ring) * adapter->num_queues;
983 adapter->tx_ring = kmalloc(size, GFP_KERNEL);
984 if (!adapter->tx_ring)
985 return -ENOMEM;
986 memset(adapter->tx_ring, 0, size);
987
988 size = sizeof(struct e1000_rx_ring) * adapter->num_queues;
989 adapter->rx_ring = kmalloc(size, GFP_KERNEL);
990 if (!adapter->rx_ring) {
991 kfree(adapter->tx_ring);
992 return -ENOMEM;
993 }
994 memset(adapter->rx_ring, 0, size);
995
996#ifdef CONFIG_E1000_NAPI
997 size = sizeof(struct net_device) * adapter->num_queues;
998 adapter->polling_netdev = kmalloc(size, GFP_KERNEL);
999 if (!adapter->polling_netdev) {
1000 kfree(adapter->tx_ring);
1001 kfree(adapter->rx_ring);
1002 return -ENOMEM;
1003 }
1004 memset(adapter->polling_netdev, 0, size);
1005#endif
1006
1007 return E1000_SUCCESS;
1008}
1009
24025e4e
MC		 1010#ifdef CONFIG_E1000_MQ
1011static void __devinit
1012e1000_setup_queue_mapping(struct e1000_adapter *adapter)
1013{
1014 int i, cpu;
1015
1016 adapter->rx_sched_call_data.func = e1000_rx_schedule;
1017 adapter->rx_sched_call_data.info = adapter->netdev;
1018 cpus_clear(adapter->rx_sched_call_data.cpumask);
1019
1020 adapter->cpu_netdev = alloc_percpu(struct net_device *);
1021 adapter->cpu_tx_ring = alloc_percpu(struct e1000_tx_ring *);
1022
1023 lock_cpu_hotplug();
1024 i = 0;
1025 for_each_online_cpu(cpu) {
1026 *per_cpu_ptr(adapter->cpu_tx_ring, cpu) = &adapter->tx_ring[i % adapter->num_queues];
1027 /* This is incomplete because we'd like to assign separate
1028 * physical cpus to these netdev polling structures and
1029 * avoid saturating a subset of cpus.
1030 */
1031 if (i < adapter->num_queues) {
1032 *per_cpu_ptr(adapter->cpu_netdev, cpu) = &adapter->polling_netdev[i];
1033 adapter->cpu_for_queue[i] = cpu;
1034 } else
1035 *per_cpu_ptr(adapter->cpu_netdev, cpu) = NULL;
1036
1037 i++;
1038 }
1039 unlock_cpu_hotplug();
1040}
1041#endif
1042
1da177e4
LT		 1043/**
1044 * e1000_open - Called when a network interface is made active
1045 * @netdev: network interface device structure
1046 *
1047 * Returns 0 on success, negative value on failure
1048 *
1049 * The open entry point is called when a network interface is made
1050 * active by the system (IFF_UP). At this point all resources needed
1051 * for transmit and receive operations are allocated, the interrupt
1052 * handler is registered with the OS, the watchdog timer is started,
1053 * and the stack is notified that the interface is ready.
1054 **/
1055
1056static int
1057e1000_open(struct net_device *netdev)
1058{
60490fe0 1059 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1060 int err;
1061
1062 /* allocate transmit descriptors */
1063
581d708e 1064 if ((err = e1000_setup_all_tx_resources(adapter)))
1da177e4
LT		 1065 goto err_setup_tx;
1066
1067 /* allocate receive descriptors */
1068
581d708e 1069 if ((err = e1000_setup_all_rx_resources(adapter)))
1da177e4
LT		 1070 goto err_setup_rx;
1071
1072 if((err = e1000_up(adapter)))
1073 goto err_up;
2d7edb92
MC		 1074 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
1075 if((adapter->hw.mng_cookie.status &
1076 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1077 e1000_update_mng_vlan(adapter);
1078 }
1da177e4
LT		 1079
1080 return E1000_SUCCESS;
1081
1082err_up:
581d708e 1083 e1000_free_all_rx_resources(adapter);
1da177e4 1084err_setup_rx:
581d708e 1085 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1086err_setup_tx:
1087 e1000_reset(adapter);
1088
1089 return err;
1090}
1091
1092/**
1093 * e1000_close - Disables a network interface
1094 * @netdev: network interface device structure
1095 *
1096 * Returns 0, this is not allowed to fail
1097 *
1098 * The close entry point is called when an interface is de-activated
1099 * by the OS. The hardware is still under the drivers control, but
1100 * needs to be disabled. A global MAC reset is issued to stop the
1101 * hardware, and all transmit and receive resources are freed.
1102 **/
1103
1104static int
1105e1000_close(struct net_device *netdev)
1106{
60490fe0 1107 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1108
1109 e1000_down(adapter);
1110
581d708e
MC		 1111 e1000_free_all_tx_resources(adapter);
1112 e1000_free_all_rx_resources(adapter);
1da177e4 1113
2d7edb92
MC		 1114 if((adapter->hw.mng_cookie.status &
1115 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1116 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1117 }
1da177e4
LT		 1118 return 0;
1119}
1120
1121/**
1122 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1123 * @adapter: address of board private structure
2d7edb92
MC		 1124 * @start: address of beginning of memory
1125 * @len: length of memory
1da177e4
LT		 1126 **/
1127static inline boolean_t
1128e1000_check_64k_bound(struct e1000_adapter *adapter,
1129 void *start, unsigned long len)
1130{
1131 unsigned long begin = (unsigned long) start;
1132 unsigned long end = begin + len;
1133
2648345f
MC		 1134 /* First rev 82545 and 82546 need to not allow any memory
1135 * write location to cross 64k boundary due to errata 23 */
1da177e4 1136 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1137 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1138 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1139 }
1140
1141 return TRUE;
1142}
1143
1144/**
1145 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1146 * @adapter: board private structure
581d708e 1147 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1148 *
1149 * Return 0 on success, negative on failure
1150 **/
1151
3ad2cc67 1152static int
581d708e
MC		 1153e1000_setup_tx_resources(struct e1000_adapter *adapter,
1154 struct e1000_tx_ring *txdr)
1da177e4 1155{
1da177e4
LT		 1156 struct pci_dev *pdev = adapter->pdev;
1157 int size;
1158
1159 size = sizeof(struct e1000_buffer) * txdr->count;
a7ec15da
RT		 1160
1161 txdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
1da177e4 1162 if(!txdr->buffer_info) {
2648345f
MC		 1163 DPRINTK(PROBE, ERR,
1164 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1165 return -ENOMEM;
1166 }
1167 memset(txdr->buffer_info, 0, size);
1168
1169 /* round up to nearest 4K */
1170
1171 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
1172 E1000_ROUNDUP(txdr->size, 4096);
1173
1174 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1175 if(!txdr->desc) {
1176setup_tx_desc_die:
1da177e4 1177 vfree(txdr->buffer_info);
2648345f
MC		 1178 DPRINTK(PROBE, ERR,
1179 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1180 return -ENOMEM;
1181 }
1182
2648345f 1183 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1184 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1185 void *olddesc = txdr->desc;
1186 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1187 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1188 "at %p\n", txdr->size, txdr->desc);
1189 /* Try again, without freeing the previous */
1da177e4 1190 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
1da177e4 1191 if(!txdr->desc) {
2648345f 1192 /* Failed allocation, critical failure */
1da177e4
LT		 1193 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1194 goto setup_tx_desc_die;
1195 }
1196
1197 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1198 /* give up */
2648345f
MC		 1199 pci_free_consistent(pdev, txdr->size, txdr->desc,
1200 txdr->dma);
1da177e4
LT		 1201 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1202 DPRINTK(PROBE, ERR,
2648345f
MC		 1203 "Unable to allocate aligned memory "
1204 "for the transmit descriptor ring\n");
1da177e4
LT		 1205 vfree(txdr->buffer_info);
1206 return -ENOMEM;
1207 } else {
2648345f 1208 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1209 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1210 }
1211 }
1212 memset(txdr->desc, 0, txdr->size);
1213
1214 txdr->next_to_use = 0;
1215 txdr->next_to_clean = 0;
2ae76d98 1216 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1217
1218 return 0;
1219}
1220
581d708e
MC		 1221/**
1222 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1223 * (Descriptors) for all queues
1224 * @adapter: board private structure
1225 *
1226 * If this function returns with an error, then it's possible one or
1227 * more of the rings is populated (while the rest are not). It is the
1228 * callers duty to clean those orphaned rings.
1229 *
1230 * Return 0 on success, negative on failure
1231 **/
1232
1233int
1234e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1235{
1236 int i, err = 0;
1237
1238 for (i = 0; i < adapter->num_queues; i++) {
1239 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1240 if (err) {
1241 DPRINTK(PROBE, ERR,
1242 "Allocation for Tx Queue %u failed\n", i);
1243 break;
1244 }
1245 }
1246
1247 return err;
1248}
1249
1da177e4
LT		 1250/**
1251 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1252 * @adapter: board private structure
1253 *
1254 * Configure the Tx unit of the MAC after a reset.
1255 **/
1256
1257static void
1258e1000_configure_tx(struct e1000_adapter *adapter)
1259{
581d708e
MC		 1260 uint64_t tdba;
1261 struct e1000_hw *hw = &adapter->hw;
1262 uint32_t tdlen, tctl, tipg, tarc;
1da177e4
LT		 1263
1264 /* Setup the HW Tx Head and Tail descriptor pointers */
1265
24025e4e
MC		 1266 switch (adapter->num_queues) {
1267 case 2:
1268 tdba = adapter->tx_ring[1].dma;
1269 tdlen = adapter->tx_ring[1].count *
1270 sizeof(struct e1000_tx_desc);
1271 E1000_WRITE_REG(hw, TDBAL1, (tdba & 0x00000000ffffffffULL));
1272 E1000_WRITE_REG(hw, TDBAH1, (tdba >> 32));
1273 E1000_WRITE_REG(hw, TDLEN1, tdlen);
1274 E1000_WRITE_REG(hw, TDH1, 0);
1275 E1000_WRITE_REG(hw, TDT1, 0);
1276 adapter->tx_ring[1].tdh = E1000_TDH1;
1277 adapter->tx_ring[1].tdt = E1000_TDT1;
1278 /* Fall Through */
1279 case 1:
1280 default:
581d708e
MC		 1281 tdba = adapter->tx_ring[0].dma;
1282 tdlen = adapter->tx_ring[0].count *
1283 sizeof(struct e1000_tx_desc);
1284 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
1285 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1286 E1000_WRITE_REG(hw, TDLEN, tdlen);
1287 E1000_WRITE_REG(hw, TDH, 0);
1288 E1000_WRITE_REG(hw, TDT, 0);
1289 adapter->tx_ring[0].tdh = E1000_TDH;
1290 adapter->tx_ring[0].tdt = E1000_TDT;
24025e4e
MC		 1291 break;
1292 }
1da177e4
LT		 1293
1294 /* Set the default values for the Tx Inter Packet Gap timer */
1295
581d708e 1296 switch (hw->mac_type) {
1da177e4
LT		 1297 case e1000_82542_rev2_0:
1298 case e1000_82542_rev2_1:
1299 tipg = DEFAULT_82542_TIPG_IPGT;
1300 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1301 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1302 break;
1303 default:
581d708e
MC		 1304 if (hw->media_type == e1000_media_type_fiber ||
1305 hw->media_type == e1000_media_type_internal_serdes)
1da177e4
LT		 1306 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1307 else
1308 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1309 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
1310 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
1311 }
581d708e 1312 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1313
1314 /* Set the Tx Interrupt Delay register */
1315
581d708e
MC		 1316 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1317 if (hw->mac_type >= e1000_82540)
1318 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1319
1320 /* Program the Transmit Control Register */
1321
581d708e 1322 tctl = E1000_READ_REG(hw, TCTL);
1da177e4
LT		 1323
1324 tctl &= ~E1000_TCTL_CT;
24025e4e 1325 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1326 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1327
581d708e 1328 E1000_WRITE_REG(hw, TCTL, tctl);
1da177e4 1329
2ae76d98
MC		 1330 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1331 tarc = E1000_READ_REG(hw, TARC0);
1332 tarc |= ((1 << 25) | (1 << 21));
1333 E1000_WRITE_REG(hw, TARC0, tarc);
1334 tarc = E1000_READ_REG(hw, TARC1);
1335 tarc |= (1 << 25);
1336 if (tctl & E1000_TCTL_MULR)
1337 tarc &= ~(1 << 28);
1338 else
1339 tarc |= (1 << 28);
1340 E1000_WRITE_REG(hw, TARC1, tarc);
1341 }
1342
581d708e 1343 e1000_config_collision_dist(hw);
1da177e4
LT		 1344
1345 /* Setup Transmit Descriptor Settings for eop descriptor */
1346 adapter->txd_cmd = E1000_TXD_CMD_IDE | E1000_TXD_CMD_EOP |
1347 E1000_TXD_CMD_IFCS;
1348
581d708e 1349 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1350 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1351 else
1352 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1353
1354 /* Cache if we're 82544 running in PCI-X because we'll
1355 * need this to apply a workaround later in the send path. */
581d708e
MC		 1356 if (hw->mac_type == e1000_82544 &&
1357 hw->bus_type == e1000_bus_type_pcix)
1da177e4
LT		 1358 adapter->pcix_82544 = 1;
1359}
1360
1361/**
1362 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1363 * @adapter: board private structure
581d708e 1364 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1365 *
1366 * Returns 0 on success, negative on failure
1367 **/
1368
3ad2cc67 1369static int
581d708e
MC		 1370e1000_setup_rx_resources(struct e1000_adapter *adapter,
1371 struct e1000_rx_ring *rxdr)
1da177e4 1372{
1da177e4 1373 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1374 int size, desc_len;
1da177e4
LT		 1375
1376 size = sizeof(struct e1000_buffer) * rxdr->count;
a7ec15da 1377 rxdr->buffer_info = vmalloc_node(size, pcibus_to_node(pdev->bus));
581d708e 1378 if (!rxdr->buffer_info) {
2648345f
MC		 1379 DPRINTK(PROBE, ERR,
1380 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1381 return -ENOMEM;
1382 }
1383 memset(rxdr->buffer_info, 0, size);
1384
2d7edb92
MC		 1385 size = sizeof(struct e1000_ps_page) * rxdr->count;
1386 rxdr->ps_page = kmalloc(size, GFP_KERNEL);
1387 if(!rxdr->ps_page) {
1388 vfree(rxdr->buffer_info);
1389 DPRINTK(PROBE, ERR,
1390 "Unable to allocate memory for the receive descriptor ring\n");
1391 return -ENOMEM;
1392 }
1393 memset(rxdr->ps_page, 0, size);
1394
1395 size = sizeof(struct e1000_ps_page_dma) * rxdr->count;
1396 rxdr->ps_page_dma = kmalloc(size, GFP_KERNEL);
1397 if(!rxdr->ps_page_dma) {
1398 vfree(rxdr->buffer_info);
1399 kfree(rxdr->ps_page);
1400 DPRINTK(PROBE, ERR,
1401 "Unable to allocate memory for the receive descriptor ring\n");
1402 return -ENOMEM;
1403 }
1404 memset(rxdr->ps_page_dma, 0, size);
1405
1406 if(adapter->hw.mac_type <= e1000_82547_rev_2)
1407 desc_len = sizeof(struct e1000_rx_desc);
1408 else
1409 desc_len = sizeof(union e1000_rx_desc_packet_split);
1410
1da177e4
LT		 1411 /* Round up to nearest 4K */
1412
2d7edb92 1413 rxdr->size = rxdr->count * desc_len;
1da177e4
LT		 1414 E1000_ROUNDUP(rxdr->size, 4096);
1415
1416 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1417
581d708e
MC		 1418 if (!rxdr->desc) {
1419 DPRINTK(PROBE, ERR,
1420 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1421setup_rx_desc_die:
1da177e4 1422 vfree(rxdr->buffer_info);
2d7edb92
MC		 1423 kfree(rxdr->ps_page);
1424 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1425 return -ENOMEM;
1426 }
1427
2648345f 1428 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1429 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1430 void *olddesc = rxdr->desc;
1431 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1432 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1433 "at %p\n", rxdr->size, rxdr->desc);
1434 /* Try again, without freeing the previous */
1da177e4 1435 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1436 /* Failed allocation, critical failure */
581d708e 1437 if (!rxdr->desc) {
1da177e4 1438 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1439 DPRINTK(PROBE, ERR,
1440 "Unable to allocate memory "
1441 "for the receive descriptor ring\n");
1da177e4
LT		 1442 goto setup_rx_desc_die;
1443 }
1444
1445 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1446 /* give up */
2648345f
MC		 1447 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1448 rxdr->dma);
1da177e4 1449 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1450 DPRINTK(PROBE, ERR,
1451 "Unable to allocate aligned memory "
1452 "for the receive descriptor ring\n");
581d708e 1453 goto setup_rx_desc_die;
1da177e4 1454 } else {
2648345f 1455 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1456 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1457 }
1458 }
1459 memset(rxdr->desc, 0, rxdr->size);
1460
1461 rxdr->next_to_clean = 0;
1462 rxdr->next_to_use = 0;
1463
1464 return 0;
1465}
1466
581d708e
MC		 1467/**
1468 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1469 * (Descriptors) for all queues
1470 * @adapter: board private structure
1471 *
1472 * If this function returns with an error, then it's possible one or
1473 * more of the rings is populated (while the rest are not). It is the
1474 * callers duty to clean those orphaned rings.
1475 *
1476 * Return 0 on success, negative on failure
1477 **/
1478
1479int
1480e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1481{
1482 int i, err = 0;
1483
1484 for (i = 0; i < adapter->num_queues; i++) {
1485 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1486 if (err) {
1487 DPRINTK(PROBE, ERR,
1488 "Allocation for Rx Queue %u failed\n", i);
1489 break;
1490 }
1491 }
1492
1493 return err;
1494}
1495
1da177e4 1496/**
2648345f 1497 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1498 * @adapter: Board private structure
1499 **/
e4c811c9
MC		 1500#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1501 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1502static void
1503e1000_setup_rctl(struct e1000_adapter *adapter)
1504{
2d7edb92
MC		 1505 uint32_t rctl, rfctl;
1506 uint32_t psrctl = 0;
e4c811c9
MC		 1507#ifdef CONFIG_E1000_PACKET_SPLIT
1508 uint32_t pages = 0;
1509#endif
1da177e4
LT		 1510
1511 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1512
1513 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1514
1515 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1516 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1517 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1518
1519 if(adapter->hw.tbi_compatibility_on == 1)
1520 rctl |= E1000_RCTL_SBP;
1521 else
1522 rctl &= ~E1000_RCTL_SBP;
1523
2d7edb92
MC		 1524 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1525 rctl &= ~E1000_RCTL_LPE;
1526 else
1527 rctl |= E1000_RCTL_LPE;
1528
1da177e4 1529 /* Setup buffer sizes */
868d5309 1530 if(adapter->hw.mac_type >= e1000_82571) {
2d7edb92
MC		 1531 /* We can now specify buffers in 1K increments.
1532 * BSIZE and BSEX are ignored in this case. */
1533 rctl |= adapter->rx_buffer_len << 0x11;
1534 } else {
1535 rctl &= ~E1000_RCTL_SZ_4096;
1536 rctl |= E1000_RCTL_BSEX;
1537 switch (adapter->rx_buffer_len) {
1538 case E1000_RXBUFFER_2048:
1539 default:
1540 rctl |= E1000_RCTL_SZ_2048;
1541 rctl &= ~E1000_RCTL_BSEX;
1542 break;
1543 case E1000_RXBUFFER_4096:
1544 rctl |= E1000_RCTL_SZ_4096;
1545 break;
1546 case E1000_RXBUFFER_8192:
1547 rctl |= E1000_RCTL_SZ_8192;
1548 break;
1549 case E1000_RXBUFFER_16384:
1550 rctl |= E1000_RCTL_SZ_16384;
1551 break;
1552 }
1553 }
1554
1555#ifdef CONFIG_E1000_PACKET_SPLIT
1556 /* 82571 and greater support packet-split where the protocol
1557 * header is placed in skb->data and the packet data is
1558 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1559 * In the case of a non-split, skb->data is linearly filled,
1560 * followed by the page buffers. Therefore, skb->data is
1561 * sized to hold the largest protocol header.
1562 */
e4c811c9
MC		 1563 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1564 if ((adapter->hw.mac_type > e1000_82547_rev_2) && (pages <= 3) &&
1565 PAGE_SIZE <= 16384)
1566 adapter->rx_ps_pages = pages;
1567 else
1568 adapter->rx_ps_pages = 0;
2d7edb92 1569#endif
e4c811c9 1570 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1571 /* Configure extra packet-split registers */
1572 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1573 rfctl |= E1000_RFCTL_EXTEN;
1574 /* disable IPv6 packet split support */
1575 rfctl |= E1000_RFCTL_IPV6_DIS;
1576 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1577
1578 rctl |= E1000_RCTL_DTYP_PS | E1000_RCTL_SECRC;
1579
1580 psrctl |= adapter->rx_ps_bsize0 >>
1581 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1582
1583 switch (adapter->rx_ps_pages) {
1584 case 3:
1585 psrctl |= PAGE_SIZE <<
1586 E1000_PSRCTL_BSIZE3_SHIFT;
1587 case 2:
1588 psrctl |= PAGE_SIZE <<
1589 E1000_PSRCTL_BSIZE2_SHIFT;
1590 case 1:
1591 psrctl |= PAGE_SIZE >>
1592 E1000_PSRCTL_BSIZE1_SHIFT;
1593 break;
1594 }
2d7edb92
MC		 1595
1596 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1597 }
1598
1599 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1600}
1601
1602/**
1603 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1604 * @adapter: board private structure
1605 *
1606 * Configure the Rx unit of the MAC after a reset.
1607 **/
1608
1609static void
1610e1000_configure_rx(struct e1000_adapter *adapter)
1611{
581d708e
MC		 1612 uint64_t rdba;
1613 struct e1000_hw *hw = &adapter->hw;
1614 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
1615#ifdef CONFIG_E1000_MQ
1616 uint32_t reta, mrqc;
1617 int i;
1618#endif
2d7edb92 1619
e4c811c9 1620 if (adapter->rx_ps_pages) {
581d708e 1621 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1622 sizeof(union e1000_rx_desc_packet_split);
1623 adapter->clean_rx = e1000_clean_rx_irq_ps;
1624 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1625 } else {
581d708e
MC		 1626 rdlen = adapter->rx_ring[0].count *
1627 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1628 adapter->clean_rx = e1000_clean_rx_irq;
1629 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1630 }
1da177e4
LT		 1631
1632 /* disable receives while setting up the descriptors */
581d708e
MC		 1633 rctl = E1000_READ_REG(hw, RCTL);
1634 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1635
1636 /* set the Receive Delay Timer Register */
581d708e 1637 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 1638
581d708e
MC		 1639 if (hw->mac_type >= e1000_82540) {
1640 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
1da177e4 1641 if(adapter->itr > 1)
581d708e 1642 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 1643 1000000000 / (adapter->itr * 256));
1644 }
1645
2ae76d98
MC		 1646 if (hw->mac_type >= e1000_82571) {
1647 /* Reset delay timers after every interrupt */
1648 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1649 ctrl_ext |= E1000_CTRL_EXT_CANC;
1650 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1651 E1000_WRITE_FLUSH(hw);
1652 }
1653
581d708e
MC		 1654 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1655 * the Base and Length of the Rx Descriptor Ring */
24025e4e
MC		 1656 switch (adapter->num_queues) {
1657#ifdef CONFIG_E1000_MQ
1658 case 2:
1659 rdba = adapter->rx_ring[1].dma;
1660 E1000_WRITE_REG(hw, RDBAL1, (rdba & 0x00000000ffffffffULL));
1661 E1000_WRITE_REG(hw, RDBAH1, (rdba >> 32));
1662 E1000_WRITE_REG(hw, RDLEN1, rdlen);
1663 E1000_WRITE_REG(hw, RDH1, 0);
1664 E1000_WRITE_REG(hw, RDT1, 0);
1665 adapter->rx_ring[1].rdh = E1000_RDH1;
1666 adapter->rx_ring[1].rdt = E1000_RDT1;
1667 /* Fall Through */
1668#endif
1669 case 1:
1670 default:
581d708e
MC		 1671 rdba = adapter->rx_ring[0].dma;
1672 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
1673 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
1674 E1000_WRITE_REG(hw, RDLEN, rdlen);
1675 E1000_WRITE_REG(hw, RDH, 0);
1676 E1000_WRITE_REG(hw, RDT, 0);
1677 adapter->rx_ring[0].rdh = E1000_RDH;
1678 adapter->rx_ring[0].rdt = E1000_RDT;
1679 break;
24025e4e
MC		 1680 }
1681
1682#ifdef CONFIG_E1000_MQ
1683 if (adapter->num_queues > 1) {
1684 uint32_t random[10];
1685
1686 get_random_bytes(&random[0], 40);
1687
1688 if (hw->mac_type <= e1000_82572) {
1689 E1000_WRITE_REG(hw, RSSIR, 0);
1690 E1000_WRITE_REG(hw, RSSIM, 0);
1691 }
1692
1693 switch (adapter->num_queues) {
1694 case 2:
1695 default:
1696 reta = 0x00800080;
1697 mrqc = E1000_MRQC_ENABLE_RSS_2Q;
1698 break;
1699 }
1700
1701 /* Fill out redirection table */
1702 for (i = 0; i < 32; i++)
1703 E1000_WRITE_REG_ARRAY(hw, RETA, i, reta);
1704 /* Fill out hash function seeds */
1705 for (i = 0; i < 10; i++)
1706 E1000_WRITE_REG_ARRAY(hw, RSSRK, i, random[i]);
1707
1708 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1709 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1710 E1000_WRITE_REG(hw, MRQC, mrqc);
1711 }
1712
1713 /* Multiqueue and packet checksumming are mutually exclusive. */
1714 if (hw->mac_type >= e1000_82571) {
1715 rxcsum = E1000_READ_REG(hw, RXCSUM);
1716 rxcsum |= E1000_RXCSUM_PCSD;
1717 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1718 }
1719
1720#else
1da177e4
LT		 1721
1722 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 1723 if (hw->mac_type >= e1000_82543) {
1724 rxcsum = E1000_READ_REG(hw, RXCSUM);
2d7edb92
MC		 1725 if(adapter->rx_csum == TRUE) {
1726 rxcsum |= E1000_RXCSUM_TUOFL;
1727
868d5309 1728 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 1729 * Must be used in conjunction with packet-split. */
e4c811c9
MC		 1730 if ((hw->mac_type >= e1000_82571) &&
1731 (adapter->rx_ps_pages)) {
2d7edb92
MC		 1732 rxcsum |= E1000_RXCSUM_IPPCSE;
1733 }
1734 } else {
1735 rxcsum &= ~E1000_RXCSUM_TUOFL;
1736 /* don't need to clear IPPCSE as it defaults to 0 */
1737 }
581d708e 1738 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4 1739 }
24025e4e 1740#endif /* CONFIG_E1000_MQ */
1da177e4 1741
581d708e
MC		 1742 if (hw->mac_type == e1000_82573)
1743 E1000_WRITE_REG(hw, ERT, 0x0100);
2d7edb92 1744
1da177e4 1745 /* Enable Receives */
581d708e 1746 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 1747}
1748
1749/**
581d708e 1750 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 1751 * @adapter: board private structure
581d708e 1752 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 1753 *
1754 * Free all transmit software resources
1755 **/
1756
3ad2cc67 1757static void
581d708e
MC		 1758e1000_free_tx_resources(struct e1000_adapter *adapter,
1759 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 1760{
1761 struct pci_dev *pdev = adapter->pdev;
1762
581d708e 1763 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 1764
581d708e
MC		 1765 vfree(tx_ring->buffer_info);
1766 tx_ring->buffer_info = NULL;
1da177e4 1767
581d708e 1768 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 1769
581d708e
MC		 1770 tx_ring->desc = NULL;
1771}
1772
1773/**
1774 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
1775 * @adapter: board private structure
1776 *
1777 * Free all transmit software resources
1778 **/
1779
1780void
1781e1000_free_all_tx_resources(struct e1000_adapter *adapter)
1782{
1783 int i;
1784
1785 for (i = 0; i < adapter->num_queues; i++)
1786 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1787}
1788
1789static inline void
1790e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
1791 struct e1000_buffer *buffer_info)
1792{
1da177e4 1793 if(buffer_info->dma) {
2648345f
MC		 1794 pci_unmap_page(adapter->pdev,
1795 buffer_info->dma,
1796 buffer_info->length,
1797 PCI_DMA_TODEVICE);
1da177e4
LT		 1798 buffer_info->dma = 0;
1799 }
1800 if(buffer_info->skb) {
1801 dev_kfree_skb_any(buffer_info->skb);
1802 buffer_info->skb = NULL;
1803 }
1804}
1805
1806/**
1807 * e1000_clean_tx_ring - Free Tx Buffers
1808 * @adapter: board private structure
581d708e 1809 * @tx_ring: ring to be cleaned
1da177e4
LT		 1810 **/
1811
1812static void
581d708e
MC		 1813e1000_clean_tx_ring(struct e1000_adapter *adapter,
1814 struct e1000_tx_ring *tx_ring)
1da177e4 1815{
1da177e4
LT		 1816 struct e1000_buffer *buffer_info;
1817 unsigned long size;
1818 unsigned int i;
1819
1820 /* Free all the Tx ring sk_buffs */
1821
1da177e4
LT		 1822 for(i = 0; i < tx_ring->count; i++) {
1823 buffer_info = &tx_ring->buffer_info[i];
1824 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1825 }
1826
1827 size = sizeof(struct e1000_buffer) * tx_ring->count;
1828 memset(tx_ring->buffer_info, 0, size);
1829
1830 /* Zero out the descriptor ring */
1831
1832 memset(tx_ring->desc, 0, tx_ring->size);
1833
1834 tx_ring->next_to_use = 0;
1835 tx_ring->next_to_clean = 0;
fd803241 1836 tx_ring->last_tx_tso = 0;
1da177e4 1837
581d708e
MC		 1838 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
1839 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
1840}
1841
1842/**
1843 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
1844 * @adapter: board private structure
1845 **/
1846
1847static void
1848e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
1849{
1850 int i;
1851
1852 for (i = 0; i < adapter->num_queues; i++)
1853 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 1854}
1855
1856/**
1857 * e1000_free_rx_resources - Free Rx Resources
1858 * @adapter: board private structure
581d708e 1859 * @rx_ring: ring to clean the resources from
1da177e4
LT		 1860 *
1861 * Free all receive software resources
1862 **/
1863
3ad2cc67 1864static void
581d708e
MC		 1865e1000_free_rx_resources(struct e1000_adapter *adapter,
1866 struct e1000_rx_ring *rx_ring)
1da177e4 1867{
1da177e4
LT		 1868 struct pci_dev *pdev = adapter->pdev;
1869
581d708e 1870 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 1871
1872 vfree(rx_ring->buffer_info);
1873 rx_ring->buffer_info = NULL;
2d7edb92
MC		 1874 kfree(rx_ring->ps_page);
1875 rx_ring->ps_page = NULL;
1876 kfree(rx_ring->ps_page_dma);
1877 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 1878
1879 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1880
1881 rx_ring->desc = NULL;
1882}
1883
1884/**
581d708e 1885 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 1886 * @adapter: board private structure
581d708e
MC		 1887 *
1888 * Free all receive software resources
1889 **/
1890
1891void
1892e1000_free_all_rx_resources(struct e1000_adapter *adapter)
1893{
1894 int i;
1895
1896 for (i = 0; i < adapter->num_queues; i++)
1897 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
1898}
1899
1900/**
1901 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1902 * @adapter: board private structure
1903 * @rx_ring: ring to free buffers from
1da177e4
LT		 1904 **/
1905
1906static void
581d708e
MC		 1907e1000_clean_rx_ring(struct e1000_adapter *adapter,
1908 struct e1000_rx_ring *rx_ring)
1da177e4 1909{
1da177e4 1910 struct e1000_buffer *buffer_info;
2d7edb92
MC		 1911 struct e1000_ps_page *ps_page;
1912 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 1913 struct pci_dev *pdev = adapter->pdev;
1914 unsigned long size;
2d7edb92 1915 unsigned int i, j;
1da177e4
LT		 1916
1917 /* Free all the Rx ring sk_buffs */
1918
1919 for(i = 0; i < rx_ring->count; i++) {
1920 buffer_info = &rx_ring->buffer_info[i];
1921 if(buffer_info->skb) {
2d7edb92
MC		 1922 ps_page = &rx_ring->ps_page[i];
1923 ps_page_dma = &rx_ring->ps_page_dma[i];
1da177e4
LT		 1924 pci_unmap_single(pdev,
1925 buffer_info->dma,
1926 buffer_info->length,
1927 PCI_DMA_FROMDEVICE);
1928
1929 dev_kfree_skb(buffer_info->skb);
1930 buffer_info->skb = NULL;
2d7edb92 1931
e4c811c9 1932 for(j = 0; j < adapter->rx_ps_pages; j++) {
2d7edb92
MC		 1933 if(!ps_page->ps_page[j]) break;
1934 pci_unmap_single(pdev,
1935 ps_page_dma->ps_page_dma[j],
1936 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1937 ps_page_dma->ps_page_dma[j] = 0;
1938 put_page(ps_page->ps_page[j]);
1939 ps_page->ps_page[j] = NULL;
1940 }
1da177e4
LT		 1941 }
1942 }
1943
1944 size = sizeof(struct e1000_buffer) * rx_ring->count;
1945 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 1946 size = sizeof(struct e1000_ps_page) * rx_ring->count;
1947 memset(rx_ring->ps_page, 0, size);
1948 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
1949 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 1950
1951 /* Zero out the descriptor ring */
1952
1953 memset(rx_ring->desc, 0, rx_ring->size);
1954
1955 rx_ring->next_to_clean = 0;
1956 rx_ring->next_to_use = 0;
1957
581d708e
MC		 1958 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
1959 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
1960}
1961
1962/**
1963 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
1964 * @adapter: board private structure
1965 **/
1966
1967static void
1968e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
1969{
1970 int i;
1971
1972 for (i = 0; i < adapter->num_queues; i++)
1973 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 1974}
1975
1976/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
1977 * and memory write and invalidate disabled for certain operations
1978 */
1979static void
1980e1000_enter_82542_rst(struct e1000_adapter *adapter)
1981{
1982 struct net_device *netdev = adapter->netdev;
1983 uint32_t rctl;
1984
1985 e1000_pci_clear_mwi(&adapter->hw);
1986
1987 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1988 rctl |= E1000_RCTL_RST;
1989 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1990 E1000_WRITE_FLUSH(&adapter->hw);
1991 mdelay(5);
1992
1993 if(netif_running(netdev))
581d708e 1994 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 1995}
1996
1997static void
1998e1000_leave_82542_rst(struct e1000_adapter *adapter)
1999{
2000 struct net_device *netdev = adapter->netdev;
2001 uint32_t rctl;
2002
2003 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2004 rctl &= ~E1000_RCTL_RST;
2005 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2006 E1000_WRITE_FLUSH(&adapter->hw);
2007 mdelay(5);
2008
2009 if(adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
2010 e1000_pci_set_mwi(&adapter->hw);
2011
2012 if(netif_running(netdev)) {
2013 e1000_configure_rx(adapter);
581d708e 2014 e1000_alloc_rx_buffers(adapter, &adapter->rx_ring[0]);
1da177e4
LT		 2015 }
2016}
2017
2018/**
2019 * e1000_set_mac - Change the Ethernet Address of the NIC
2020 * @netdev: network interface device structure
2021 * @p: pointer to an address structure
2022 *
2023 * Returns 0 on success, negative on failure
2024 **/
2025
2026static int
2027e1000_set_mac(struct net_device *netdev, void *p)
2028{
60490fe0 2029 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2030 struct sockaddr *addr = p;
2031
2032 if(!is_valid_ether_addr(addr->sa_data))
2033 return -EADDRNOTAVAIL;
2034
2035 /* 82542 2.0 needs to be in reset to write receive address registers */
2036
2037 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2038 e1000_enter_82542_rst(adapter);
2039
2040 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2041 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2042
2043 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2044
868d5309
MC		 2045 /* With 82571 controllers, LAA may be overwritten (with the default)
2046 * due to controller reset from the other port. */
2047 if (adapter->hw.mac_type == e1000_82571) {
2048 /* activate the work around */
2049 adapter->hw.laa_is_present = 1;
2050
2051 /* Hold a copy of the LAA in RAR[14] This is done so that
2052 * between the time RAR[0] gets clobbered and the time it
2053 * gets fixed (in e1000_watchdog), the actual LAA is in one
2054 * of the RARs and no incoming packets directed to this port
2055 * are dropped. Eventaully the LAA will be in RAR[0] and
2056 * RAR[14] */
2057 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
2058 E1000_RAR_ENTRIES - 1);
2059 }
2060
1da177e4
LT		 2061 if(adapter->hw.mac_type == e1000_82542_rev2_0)
2062 e1000_leave_82542_rst(adapter);
2063
2064 return 0;
2065}
2066
2067/**
2068 * e1000_set_multi - Multicast and Promiscuous mode set
2069 * @netdev: network interface device structure
2070 *
2071 * The set_multi entry point is called whenever the multicast address
2072 * list or the network interface flags are updated. This routine is
2073 * responsible for configuring the hardware for proper multicast,
2074 * promiscuous mode, and all-multi behavior.
2075 **/
2076
2077static void
2078e1000_set_multi(struct net_device *netdev)
2079{
60490fe0 2080 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2081 struct e1000_hw *hw = &adapter->hw;
2082 struct dev_mc_list *mc_ptr;
2083 uint32_t rctl;
2084 uint32_t hash_value;
868d5309 2085 int i, rar_entries = E1000_RAR_ENTRIES;
1da177e4 2086
868d5309
MC		 2087 /* reserve RAR[14] for LAA over-write work-around */
2088 if (adapter->hw.mac_type == e1000_82571)
2089 rar_entries--;
1da177e4 2090
2648345f
MC		 2091 /* Check for Promiscuous and All Multicast modes */
2092
1da177e4
LT		 2093 rctl = E1000_READ_REG(hw, RCTL);
2094
2095 if(netdev->flags & IFF_PROMISC) {
2096 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2097 } else if(netdev->flags & IFF_ALLMULTI) {
2098 rctl |= E1000_RCTL_MPE;
2099 rctl &= ~E1000_RCTL_UPE;
2100 } else {
2101 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2102 }
2103
2104 E1000_WRITE_REG(hw, RCTL, rctl);
2105
2106 /* 82542 2.0 needs to be in reset to write receive address registers */
2107
2108 if(hw->mac_type == e1000_82542_rev2_0)
2109 e1000_enter_82542_rst(adapter);
2110
2111 /* load the first 14 multicast address into the exact filters 1-14
2112 * RAR 0 is used for the station MAC adddress
2113 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2114 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2115 */
2116 mc_ptr = netdev->mc_list;
2117
868d5309
MC		 2118 for(i = 1; i < rar_entries; i++) {
2119 if (mc_ptr) {
1da177e4
LT		 2120 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2121 mc_ptr = mc_ptr->next;
2122 } else {
2123 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
2124 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
2125 }
2126 }
2127
2128 /* clear the old settings from the multicast hash table */
2129
2130 for(i = 0; i < E1000_NUM_MTA_REGISTERS; i++)
2131 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
2132
2133 /* load any remaining addresses into the hash table */
2134
2135 for(; mc_ptr; mc_ptr = mc_ptr->next) {
2136 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2137 e1000_mta_set(hw, hash_value);
2138 }
2139
2140 if(hw->mac_type == e1000_82542_rev2_0)
2141 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2142}
2143
2144/* Need to wait a few seconds after link up to get diagnostic information from
2145 * the phy */
2146
2147static void
2148e1000_update_phy_info(unsigned long data)
2149{
2150 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2151 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2152}
2153
2154/**
2155 * e1000_82547_tx_fifo_stall - Timer Call-back
2156 * @data: pointer to adapter cast into an unsigned long
2157 **/
2158
2159static void
2160e1000_82547_tx_fifo_stall(unsigned long data)
2161{
2162 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2163 struct net_device *netdev = adapter->netdev;
2164 uint32_t tctl;
2165
2166 if(atomic_read(&adapter->tx_fifo_stall)) {
2167 if((E1000_READ_REG(&adapter->hw, TDT) ==
2168 E1000_READ_REG(&adapter->hw, TDH)) &&
2169 (E1000_READ_REG(&adapter->hw, TDFT) ==
2170 E1000_READ_REG(&adapter->hw, TDFH)) &&
2171 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2172 E1000_READ_REG(&adapter->hw, TDFHS))) {
2173 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2174 E1000_WRITE_REG(&adapter->hw, TCTL,
2175 tctl & ~E1000_TCTL_EN);
2176 E1000_WRITE_REG(&adapter->hw, TDFT,
2177 adapter->tx_head_addr);
2178 E1000_WRITE_REG(&adapter->hw, TDFH,
2179 adapter->tx_head_addr);
2180 E1000_WRITE_REG(&adapter->hw, TDFTS,
2181 adapter->tx_head_addr);
2182 E1000_WRITE_REG(&adapter->hw, TDFHS,
2183 adapter->tx_head_addr);
2184 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2185 E1000_WRITE_FLUSH(&adapter->hw);
2186
2187 adapter->tx_fifo_head = 0;
2188 atomic_set(&adapter->tx_fifo_stall, 0);
2189 netif_wake_queue(netdev);
2190 } else {
2191 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2192 }
2193 }
2194}
2195
2196/**
2197 * e1000_watchdog - Timer Call-back
2198 * @data: pointer to adapter cast into an unsigned long
2199 **/
2200static void
2201e1000_watchdog(unsigned long data)
2202{
2203 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2204
2205 /* Do the rest outside of interrupt context */
2206 schedule_work(&adapter->watchdog_task);
2207}
2208
2209static void
2210e1000_watchdog_task(struct e1000_adapter *adapter)
2211{
2212 struct net_device *netdev = adapter->netdev;
545c67c0 2213 struct e1000_tx_ring *txdr = adapter->tx_ring;
1da177e4
LT		 2214 uint32_t link;
2215
2216 e1000_check_for_link(&adapter->hw);
2d7edb92
MC		 2217 if (adapter->hw.mac_type == e1000_82573) {
2218 e1000_enable_tx_pkt_filtering(&adapter->hw);
2219 if(adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2220 e1000_update_mng_vlan(adapter);
2221 }
1da177e4
LT		 2222
2223 if((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
2224 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2225 link = !adapter->hw.serdes_link_down;
2226 else
2227 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2228
2229 if(link) {
2230 if(!netif_carrier_ok(netdev)) {
2231 e1000_get_speed_and_duplex(&adapter->hw,
2232 &adapter->link_speed,
2233 &adapter->link_duplex);
2234
2235 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s\n",
2236 adapter->link_speed,
2237 adapter->link_duplex == FULL_DUPLEX ?
2238 "Full Duplex" : "Half Duplex");
2239
2240 netif_carrier_on(netdev);
2241 netif_wake_queue(netdev);
2242 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2243 adapter->smartspeed = 0;
2244 }
2245 } else {
2246 if(netif_carrier_ok(netdev)) {
2247 adapter->link_speed = 0;
2248 adapter->link_duplex = 0;
2249 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2250 netif_carrier_off(netdev);
2251 netif_stop_queue(netdev);
2252 mod_timer(&adapter->phy_info_timer, jiffies + 2 * HZ);
2253 }
2254
2255 e1000_smartspeed(adapter);
2256 }
2257
2258 e1000_update_stats(adapter);
2259
2260 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2261 adapter->tpt_old = adapter->stats.tpt;
2262 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2263 adapter->colc_old = adapter->stats.colc;
2264
2265 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2266 adapter->gorcl_old = adapter->stats.gorcl;
2267 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2268 adapter->gotcl_old = adapter->stats.gotcl;
2269
2270 e1000_update_adaptive(&adapter->hw);
2271
581d708e
MC		 2272 if (adapter->num_queues == 1 && !netif_carrier_ok(netdev)) {
2273 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2274 /* We've lost link, so the controller stops DMA,
2275 * but we've got queued Tx work that's never going
2276 * to get done, so reset controller to flush Tx.
2277 * (Do the reset outside of interrupt context). */
2278 schedule_work(&adapter->tx_timeout_task);
2279 }
2280 }
2281
2282 /* Dynamic mode for Interrupt Throttle Rate (ITR) */
2283 if(adapter->hw.mac_type >= e1000_82540 && adapter->itr == 1) {
2284 /* Symmetric Tx/Rx gets a reduced ITR=2000; Total
2285 * asymmetrical Tx or Rx gets ITR=8000; everyone
2286 * else is between 2000-8000. */
2287 uint32_t goc = (adapter->gotcl + adapter->gorcl) / 10000;
2288 uint32_t dif = (adapter->gotcl > adapter->gorcl ?
2289 adapter->gotcl - adapter->gorcl :
2290 adapter->gorcl - adapter->gotcl) / 10000;
2291 uint32_t itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
2292 E1000_WRITE_REG(&adapter->hw, ITR, 1000000000 / (itr * 256));
2293 }
2294
2295 /* Cause software interrupt to ensure rx ring is cleaned */
2296 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2297
2648345f 2298 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2299 adapter->detect_tx_hung = TRUE;
2300
868d5309
MC		 2301 /* With 82571 controllers, LAA may be overwritten due to controller
2302 * reset from the other port. Set the appropriate LAA in RAR[0] */
2303 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2304 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2305
1da177e4
LT		 2306 /* Reset the timer */
2307 mod_timer(&adapter->watchdog_timer, jiffies + 2 * HZ);
2308}
2309
2310#define E1000_TX_FLAGS_CSUM 0x00000001
2311#define E1000_TX_FLAGS_VLAN 0x00000002
2312#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2313#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2314#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2315#define E1000_TX_FLAGS_VLAN_SHIFT 16
2316
2317static inline int
581d708e
MC		 2318e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2319 struct sk_buff *skb)
1da177e4
LT		 2320{
2321#ifdef NETIF_F_TSO
2322 struct e1000_context_desc *context_desc;
545c67c0 2323 struct e1000_buffer *buffer_info;
1da177e4
LT		 2324 unsigned int i;
2325 uint32_t cmd_length = 0;
2d7edb92 2326 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2327 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2328 int err;
2329
2330 if(skb_shinfo(skb)->tso_size) {
2331 if (skb_header_cloned(skb)) {
2332 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2333 if (err)
2334 return err;
2335 }
2336
2337 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2338 mss = skb_shinfo(skb)->tso_size;
2d7edb92
MC		 2339 if(skb->protocol == ntohs(ETH_P_IP)) {
2340 skb->nh.iph->tot_len = 0;
2341 skb->nh.iph->check = 0;
2342 skb->h.th->check =
2343 ~csum_tcpudp_magic(skb->nh.iph->saddr,
2344 skb->nh.iph->daddr,
2345 0,
2346 IPPROTO_TCP,
2347 0);
2348 cmd_length = E1000_TXD_CMD_IP;
2349 ipcse = skb->h.raw - skb->data - 1;
2350#ifdef NETIF_F_TSO_IPV6
2351 } else if(skb->protocol == ntohs(ETH_P_IPV6)) {
2352 skb->nh.ipv6h->payload_len = 0;
2353 skb->h.th->check =
2354 ~csum_ipv6_magic(&skb->nh.ipv6h->saddr,
2355 &skb->nh.ipv6h->daddr,
2356 0,
2357 IPPROTO_TCP,
2358 0);
2359 ipcse = 0;
2360#endif
2361 }
1da177e4
LT		 2362 ipcss = skb->nh.raw - skb->data;
2363 ipcso = (void *)&(skb->nh.iph->check) - (void *)skb->data;
1da177e4
LT		 2364 tucss = skb->h.raw - skb->data;
2365 tucso = (void *)&(skb->h.th->check) - (void *)skb->data;
2366 tucse = 0;
2367
2368 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2369 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2370
581d708e
MC		 2371 i = tx_ring->next_to_use;
2372 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2373 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2374
2375 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2376 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2377 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2378 context_desc->upper_setup.tcp_fields.tucss = tucss;
2379 context_desc->upper_setup.tcp_fields.tucso = tucso;
2380 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2381 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2382 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2383 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2384
545c67c0
JK		 2385 buffer_info->time_stamp = jiffies;
2386
581d708e
MC		 2387 if (++i == tx_ring->count) i = 0;
2388 tx_ring->next_to_use = i;
1da177e4
LT		 2389
2390 return 1;
2391 }
2392#endif
2393
2394 return 0;
2395}
2396
2397static inline boolean_t
581d708e
MC		 2398e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2399 struct sk_buff *skb)
1da177e4
LT		 2400{
2401 struct e1000_context_desc *context_desc;
545c67c0 2402 struct e1000_buffer *buffer_info;
1da177e4
LT		 2403 unsigned int i;
2404 uint8_t css;
2405
2406 if(likely(skb->ip_summed == CHECKSUM_HW)) {
2407 css = skb->h.raw - skb->data;
2408
581d708e 2409 i = tx_ring->next_to_use;
545c67c0 2410 buffer_info = &tx_ring->buffer_info[i];
581d708e 2411 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4
LT		 2412
2413 context_desc->upper_setup.tcp_fields.tucss = css;
2414 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum;
2415 context_desc->upper_setup.tcp_fields.tucse = 0;
2416 context_desc->tcp_seg_setup.data = 0;
2417 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2418
545c67c0
JK		 2419 buffer_info->time_stamp = jiffies;
2420
581d708e
MC		 2421 if (unlikely(++i == tx_ring->count)) i = 0;
2422 tx_ring->next_to_use = i;
1da177e4
LT		 2423
2424 return TRUE;
2425 }
2426
2427 return FALSE;
2428}
2429
2430#define E1000_MAX_TXD_PWR 12
2431#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2432
2433static inline int
581d708e
MC		 2434e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2435 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2436 unsigned int nr_frags, unsigned int mss)
1da177e4 2437{
1da177e4
LT		 2438 struct e1000_buffer *buffer_info;
2439 unsigned int len = skb->len;
2440 unsigned int offset = 0, size, count = 0, i;
2441 unsigned int f;
2442 len -= skb->data_len;
2443
2444 i = tx_ring->next_to_use;
2445
2446 while(len) {
2447 buffer_info = &tx_ring->buffer_info[i];
2448 size = min(len, max_per_txd);
2449#ifdef NETIF_F_TSO
fd803241
JK		 2450 /* Workaround for Controller erratum --
2451 * descriptor for non-tso packet in a linear SKB that follows a
2452 * tso gets written back prematurely before the data is fully
2453 * DMAd to the controller */
2454 if (!skb->data_len && tx_ring->last_tx_tso &&
2455 !skb_shinfo(skb)->tso_size) {
2456 tx_ring->last_tx_tso = 0;
2457 size -= 4;
2458 }
2459
1da177e4
LT		 2460 /* Workaround for premature desc write-backs
2461 * in TSO mode. Append 4-byte sentinel desc */
2462 if(unlikely(mss && !nr_frags && size == len && size > 8))
2463 size -= 4;
2464#endif
97338bde
MC		 2465 /* work-around for errata 10 and it applies
2466 * to all controllers in PCI-X mode
2467 * The fix is to make sure that the first descriptor of a
2468 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
2469 */
2470 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2471 (size > 2015) && count == 0))
2472 size = 2015;
2473
1da177e4
LT		 2474 /* Workaround for potential 82544 hang in PCI-X. Avoid
2475 * terminating buffers within evenly-aligned dwords. */
2476 if(unlikely(adapter->pcix_82544 &&
2477 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
2478 size > 4))
2479 size -= 4;
2480
2481 buffer_info->length = size;
2482 buffer_info->dma =
2483 pci_map_single(adapter->pdev,
2484 skb->data + offset,
2485 size,
2486 PCI_DMA_TODEVICE);
2487 buffer_info->time_stamp = jiffies;
2488
2489 len -= size;
2490 offset += size;
2491 count++;
2492 if(unlikely(++i == tx_ring->count)) i = 0;
2493 }
2494
2495 for(f = 0; f < nr_frags; f++) {
2496 struct skb_frag_struct *frag;
2497
2498 frag = &skb_shinfo(skb)->frags[f];
2499 len = frag->size;
2500 offset = frag->page_offset;
2501
2502 while(len) {
2503 buffer_info = &tx_ring->buffer_info[i];
2504 size = min(len, max_per_txd);
2505#ifdef NETIF_F_TSO
2506 /* Workaround for premature desc write-backs
2507 * in TSO mode. Append 4-byte sentinel desc */
2508 if(unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
2509 size -= 4;
2510#endif
2511 /* Workaround for potential 82544 hang in PCI-X.
2512 * Avoid terminating buffers within evenly-aligned
2513 * dwords. */
2514 if(unlikely(adapter->pcix_82544 &&
2515 !((unsigned long)(frag->page+offset+size-1) & 4) &&
2516 size > 4))
2517 size -= 4;
2518
2519 buffer_info->length = size;
2520 buffer_info->dma =
2521 pci_map_page(adapter->pdev,
2522 frag->page,
2523 offset,
2524 size,
2525 PCI_DMA_TODEVICE);
2526 buffer_info->time_stamp = jiffies;
2527
2528 len -= size;
2529 offset += size;
2530 count++;
2531 if(unlikely(++i == tx_ring->count)) i = 0;
2532 }
2533 }
2534
2535 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2536 tx_ring->buffer_info[i].skb = skb;
2537 tx_ring->buffer_info[first].next_to_watch = i;
2538
2539 return count;
2540}
2541
2542static inline void
581d708e
MC		 2543e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2544 int tx_flags, int count)
1da177e4 2545{
1da177e4
LT		 2546 struct e1000_tx_desc *tx_desc = NULL;
2547 struct e1000_buffer *buffer_info;
2548 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
2549 unsigned int i;
2550
2551 if(likely(tx_flags & E1000_TX_FLAGS_TSO)) {
2552 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
2553 E1000_TXD_CMD_TSE;
2d7edb92
MC		 2554 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2555
2556 if(likely(tx_flags & E1000_TX_FLAGS_IPV4))
2557 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 2558 }
2559
2560 if(likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
2561 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2562 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2563 }
2564
2565 if(unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
2566 txd_lower |= E1000_TXD_CMD_VLE;
2567 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
2568 }
2569
2570 i = tx_ring->next_to_use;
2571
2572 while(count--) {
2573 buffer_info = &tx_ring->buffer_info[i];
2574 tx_desc = E1000_TX_DESC(*tx_ring, i);
2575 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
2576 tx_desc->lower.data =
2577 cpu_to_le32(txd_lower | buffer_info->length);
2578 tx_desc->upper.data = cpu_to_le32(txd_upper);
2579 if(unlikely(++i == tx_ring->count)) i = 0;
2580 }
2581
2582 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
2583
2584 /* Force memory writes to complete before letting h/w
2585 * know there are new descriptors to fetch. (Only
2586 * applicable for weak-ordered memory model archs,
2587 * such as IA-64). */
2588 wmb();
2589
2590 tx_ring->next_to_use = i;
581d708e 2591 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
1da177e4
LT		 2592}
2593
2594/**
2595 * 82547 workaround to avoid controller hang in half-duplex environment.
2596 * The workaround is to avoid queuing a large packet that would span
2597 * the internal Tx FIFO ring boundary by notifying the stack to resend
2598 * the packet at a later time. This gives the Tx FIFO an opportunity to
2599 * flush all packets. When that occurs, we reset the Tx FIFO pointers
2600 * to the beginning of the Tx FIFO.
2601 **/
2602
2603#define E1000_FIFO_HDR 0x10
2604#define E1000_82547_PAD_LEN 0x3E0
2605
2606static inline int
2607e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
2608{
2609 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
2610 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
2611
2612 E1000_ROUNDUP(skb_fifo_len, E1000_FIFO_HDR);
2613
2614 if(adapter->link_duplex != HALF_DUPLEX)
2615 goto no_fifo_stall_required;
2616
2617 if(atomic_read(&adapter->tx_fifo_stall))
2618 return 1;
2619
2620 if(skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
2621 atomic_set(&adapter->tx_fifo_stall, 1);
2622 return 1;
2623 }
2624
2625no_fifo_stall_required:
2626 adapter->tx_fifo_head += skb_fifo_len;
2627 if(adapter->tx_fifo_head >= adapter->tx_fifo_size)
2628 adapter->tx_fifo_head -= adapter->tx_fifo_size;
2629 return 0;
2630}
2631
2d7edb92
MC		 2632#define MINIMUM_DHCP_PACKET_SIZE 282
2633static inline int
2634e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
2635{
2636 struct e1000_hw *hw = &adapter->hw;
2637 uint16_t length, offset;
2638 if(vlan_tx_tag_present(skb)) {
2639 if(!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2640 ( adapter->hw.mng_cookie.status &
2641 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
2642 return 0;
2643 }
a174fd88 2644 if ((skb->len > MINIMUM_DHCP_PACKET_SIZE) && (!skb->protocol)) {
2d7edb92
MC		 2645 struct ethhdr *eth = (struct ethhdr *) skb->data;
2646 if((htons(ETH_P_IP) == eth->h_proto)) {
2647 const struct iphdr *ip =
2648 (struct iphdr *)((uint8_t *)skb->data+14);
2649 if(IPPROTO_UDP == ip->protocol) {
2650 struct udphdr *udp =
2651 (struct udphdr *)((uint8_t *)ip +
2652 (ip->ihl << 2));
2653 if(ntohs(udp->dest) == 67) {
2654 offset = (uint8_t *)udp + 8 - skb->data;
2655 length = skb->len - offset;
2656
2657 return e1000_mng_write_dhcp_info(hw,
2658 (uint8_t *)udp + 8,
2659 length);
2660 }
2661 }
2662 }
2663 }
2664 return 0;
2665}
2666
1da177e4
LT		 2667#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
2668static int
2669e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2670{
60490fe0 2671 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 2672 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 2673 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
2674 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
2675 unsigned int tx_flags = 0;
2676 unsigned int len = skb->len;
2677 unsigned long flags;
2678 unsigned int nr_frags = 0;
2679 unsigned int mss = 0;
2680 int count = 0;
2681 int tso;
2682 unsigned int f;
2683 len -= skb->data_len;
2684
24025e4e
MC		 2685#ifdef CONFIG_E1000_MQ
2686 tx_ring = *per_cpu_ptr(adapter->cpu_tx_ring, smp_processor_id());
2687#else
581d708e 2688 tx_ring = adapter->tx_ring;
24025e4e
MC		 2689#endif
2690
581d708e 2691 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 2692 dev_kfree_skb_any(skb);
2693 return NETDEV_TX_OK;
2694 }
2695
2696#ifdef NETIF_F_TSO
2697 mss = skb_shinfo(skb)->tso_size;
2648345f 2698 /* The controller does a simple calculation to
1da177e4
LT		 2699 * make sure there is enough room in the FIFO before
2700 * initiating the DMA for each buffer. The calc is:
2701 * 4 = ceil(buffer len/mss). To make sure we don't
2702 * overrun the FIFO, adjust the max buffer len if mss
2703 * drops. */
2704 if(mss) {
9a3056da 2705 uint8_t hdr_len;
1da177e4
LT		 2706 max_per_txd = min(mss << 2, max_per_txd);
2707 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da
JK		 2708
2709 /* TSO Workaround for 82571/2 Controllers -- if skb->data
2710 * points to just header, pull a few bytes of payload from
2711 * frags into skb->data */
2712 hdr_len = ((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2713 if (skb->data_len && (hdr_len == (skb->len - skb->data_len)) &&
2714 (adapter->hw.mac_type == e1000_82571 ||
2715 adapter->hw.mac_type == e1000_82572)) {
2716 len = skb->len - skb->data_len;
2717 }
1da177e4
LT		 2718 }
2719
2720 if((mss) || (skb->ip_summed == CHECKSUM_HW))
9a3056da 2721 /* reserve a descriptor for the offload context */
1da177e4 2722 count++;
2648345f 2723 count++;
1da177e4
LT		 2724#else
2725 if(skb->ip_summed == CHECKSUM_HW)
2726 count++;
2727#endif
fd803241
JK		 2728
2729#ifdef NETIF_F_TSO
2730 /* Controller Erratum workaround */
2731 if (!skb->data_len && tx_ring->last_tx_tso &&
2732 !skb_shinfo(skb)->tso_size)
2733 count++;
2734#endif
2735
1da177e4
LT		 2736 count += TXD_USE_COUNT(len, max_txd_pwr);
2737
2738 if(adapter->pcix_82544)
2739 count++;
2740
97338bde
MC		 2741 /* work-around for errata 10 and it applies to all controllers
2742 * in PCI-X mode, so add one more descriptor to the count
2743 */
2744 if(unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
2745 (len > 2015)))
2746 count++;
2747
1da177e4
LT		 2748 nr_frags = skb_shinfo(skb)->nr_frags;
2749 for(f = 0; f < nr_frags; f++)
2750 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
2751 max_txd_pwr);
2752 if(adapter->pcix_82544)
2753 count += nr_frags;
2754
9a3056da
JK		 2755 unsigned int pull_size;
2756 pull_size = min((unsigned int)4, skb->data_len);
2757 if (!__pskb_pull_tail(skb, pull_size)) {
2758 printk(KERN_ERR "__pskb_pull_tail failed.\n");
2759 dev_kfree_skb_any(skb);
2760 return -EFAULT;
868d5309 2761 }
868d5309 2762
2d7edb92
MC		 2763 if(adapter->hw.tx_pkt_filtering && (adapter->hw.mac_type == e1000_82573) )
2764 e1000_transfer_dhcp_info(adapter, skb);
2765
581d708e
MC		 2766 local_irq_save(flags);
2767 if (!spin_trylock(&tx_ring->tx_lock)) {
2768 /* Collision - tell upper layer to requeue */
2769 local_irq_restore(flags);
2770 return NETDEV_TX_LOCKED;
2771 }
1da177e4
LT		 2772
2773 /* need: count + 2 desc gap to keep tail from touching
2774 * head, otherwise try next time */
581d708e 2775 if (unlikely(E1000_DESC_UNUSED(tx_ring) < count + 2)) {
1da177e4 2776 netif_stop_queue(netdev);
581d708e 2777 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2778 return NETDEV_TX_BUSY;
2779 }
2780
2781 if(unlikely(adapter->hw.mac_type == e1000_82547)) {
2782 if(unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
2783 netif_stop_queue(netdev);
2784 mod_timer(&adapter->tx_fifo_stall_timer, jiffies);
581d708e 2785 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2786 return NETDEV_TX_BUSY;
2787 }
2788 }
2789
2790 if(unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
2791 tx_flags |= E1000_TX_FLAGS_VLAN;
2792 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
2793 }
2794
581d708e 2795 first = tx_ring->next_to_use;
1da177e4 2796
581d708e 2797 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 2798 if (tso < 0) {
2799 dev_kfree_skb_any(skb);
581d708e 2800 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2801 return NETDEV_TX_OK;
2802 }
2803
fd803241
JK		 2804 if (likely(tso)) {
2805 tx_ring->last_tx_tso = 1;
1da177e4 2806 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 2807 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 2808 tx_flags |= E1000_TX_FLAGS_CSUM;
2809
2d7edb92 2810 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 2811 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 2812 * no longer assume, we must. */
581d708e 2813 if (likely(skb->protocol == ntohs(ETH_P_IP)))
2d7edb92
MC		 2814 tx_flags |= E1000_TX_FLAGS_IPV4;
2815
581d708e
MC		 2816 e1000_tx_queue(adapter, tx_ring, tx_flags,
2817 e1000_tx_map(adapter, tx_ring, skb, first,
2818 max_per_txd, nr_frags, mss));
1da177e4
LT		 2819
2820 netdev->trans_start = jiffies;
2821
2822 /* Make sure there is space in the ring for the next send. */
581d708e 2823 if (unlikely(E1000_DESC_UNUSED(tx_ring) < MAX_SKB_FRAGS + 2))
1da177e4
LT		 2824 netif_stop_queue(netdev);
2825
581d708e 2826 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 2827 return NETDEV_TX_OK;
2828}
2829
2830/**
2831 * e1000_tx_timeout - Respond to a Tx Hang
2832 * @netdev: network interface device structure
2833 **/
2834
2835static void
2836e1000_tx_timeout(struct net_device *netdev)
2837{
60490fe0 2838 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2839
2840 /* Do the reset outside of interrupt context */
2841 schedule_work(&adapter->tx_timeout_task);
2842}
2843
2844static void
2845e1000_tx_timeout_task(struct net_device *netdev)
2846{
60490fe0 2847 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2848
2849 e1000_down(adapter);
2850 e1000_up(adapter);
2851}
2852
2853/**
2854 * e1000_get_stats - Get System Network Statistics
2855 * @netdev: network interface device structure
2856 *
2857 * Returns the address of the device statistics structure.
2858 * The statistics are actually updated from the timer callback.
2859 **/
2860
2861static struct net_device_stats *
2862e1000_get_stats(struct net_device *netdev)
2863{
60490fe0 2864 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2865
2866 e1000_update_stats(adapter);
2867 return &adapter->net_stats;
2868}
2869
2870/**
2871 * e1000_change_mtu - Change the Maximum Transfer Unit
2872 * @netdev: network interface device structure
2873 * @new_mtu: new value for maximum frame size
2874 *
2875 * Returns 0 on success, negative on failure
2876 **/
2877
2878static int
2879e1000_change_mtu(struct net_device *netdev, int new_mtu)
2880{
60490fe0 2881 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2882 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
2883
2884 if((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
2885 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2886 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
2887 return -EINVAL;
2888 }
2889
868d5309 2890#define MAX_STD_JUMBO_FRAME_SIZE 9234
2d7edb92 2891 /* might want this to be bigger enum check... */
868d5309
MC		 2892 /* 82571 controllers limit jumbo frame size to 10500 bytes */
2893 if ((adapter->hw.mac_type == e1000_82571 ||
2894 adapter->hw.mac_type == e1000_82572) &&
2895 max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2896 DPRINTK(PROBE, ERR, "MTU > 9216 bytes not supported "
2897 "on 82571 and 82572 controllers.\n");
2898 return -EINVAL;
2899 }
2900
2901 if(adapter->hw.mac_type == e1000_82573 &&
2d7edb92
MC		 2902 max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
2903 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2904 "on 82573\n");
1da177e4 2905 return -EINVAL;
2d7edb92 2906 }
1da177e4 2907
2d7edb92
MC		 2908 if(adapter->hw.mac_type > e1000_82547_rev_2) {
2909 adapter->rx_buffer_len = max_frame;
2910 E1000_ROUNDUP(adapter->rx_buffer_len, 1024);
1da177e4 2911 } else {
2d7edb92
MC		 2912 if(unlikely((adapter->hw.mac_type < e1000_82543) &&
2913 (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE))) {
2914 DPRINTK(PROBE, ERR, "Jumbo Frames not supported "
2915 "on 82542\n");
2916 return -EINVAL;
2917
2918 } else {
2919 if(max_frame <= E1000_RXBUFFER_2048) {
2920 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
2921 } else if(max_frame <= E1000_RXBUFFER_4096) {
2922 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
2923 } else if(max_frame <= E1000_RXBUFFER_8192) {
2924 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
2925 } else if(max_frame <= E1000_RXBUFFER_16384) {
2926 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
2927 }
2928 }
1da177e4
LT		 2929 }
2930
2d7edb92
MC		 2931 netdev->mtu = new_mtu;
2932
2933 if(netif_running(netdev)) {
1da177e4
LT		 2934 e1000_down(adapter);
2935 e1000_up(adapter);
2936 }
2937
1da177e4
LT		 2938 adapter->hw.max_frame_size = max_frame;
2939
2940 return 0;
2941}
2942
2943/**
2944 * e1000_update_stats - Update the board statistics counters
2945 * @adapter: board private structure
2946 **/
2947
2948void
2949e1000_update_stats(struct e1000_adapter *adapter)
2950{
2951 struct e1000_hw *hw = &adapter->hw;
2952 unsigned long flags;
2953 uint16_t phy_tmp;
2954
2955#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2956
2957 spin_lock_irqsave(&adapter->stats_lock, flags);
2958
2959 /* these counters are modified from e1000_adjust_tbi_stats,
2960 * called from the interrupt context, so they must only
2961 * be written while holding adapter->stats_lock
2962 */
2963
2964 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
2965 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
2966 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
2967 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
2968 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
2969 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
2970 adapter->stats.roc += E1000_READ_REG(hw, ROC);
2971 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
2972 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
2973 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
2974 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
2975 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
2976 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
2977
2978 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
2979 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
2980 adapter->stats.scc += E1000_READ_REG(hw, SCC);
2981 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
2982 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
2983 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
2984 adapter->stats.dc += E1000_READ_REG(hw, DC);
2985 adapter->stats.sec += E1000_READ_REG(hw, SEC);
2986 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
2987 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
2988 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
2989 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
2990 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
2991 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
2992 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
2993 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
2994 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
2995 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
2996 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
2997 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
2998 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
2999 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3000 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3001 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3002 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3003 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
3004 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3005 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3006 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3007 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3008 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3009 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
3010 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3011 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3012
3013 /* used for adaptive IFS */
3014
3015 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3016 adapter->stats.tpt += hw->tx_packet_delta;
3017 hw->collision_delta = E1000_READ_REG(hw, COLC);
3018 adapter->stats.colc += hw->collision_delta;
3019
3020 if(hw->mac_type >= e1000_82543) {
3021 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3022 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3023 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3024 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3025 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3026 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3027 }
2d7edb92
MC		 3028 if(hw->mac_type > e1000_82547_rev_2) {
3029 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3030 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
3031 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3032 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3033 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3034 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3035 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3036 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3037 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
3038 }
1da177e4
LT		 3039
3040 /* Fill out the OS statistics structure */
3041
3042 adapter->net_stats.rx_packets = adapter->stats.gprc;
3043 adapter->net_stats.tx_packets = adapter->stats.gptc;
3044 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3045 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3046 adapter->net_stats.multicast = adapter->stats.mprc;
3047 adapter->net_stats.collisions = adapter->stats.colc;
3048
3049 /* Rx Errors */
3050
3051 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3052 adapter->stats.crcerrs + adapter->stats.algnerrc +
6d915757
MC		 3053 adapter->stats.rlec + adapter->stats.mpc +
3054 adapter->stats.cexterr;
1da177e4
LT		 3055 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3056 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3057 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
3058 adapter->net_stats.rx_fifo_errors = adapter->stats.mpc;
3059 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3060
3061 /* Tx Errors */
3062
3063 adapter->net_stats.tx_errors = adapter->stats.ecol +
3064 adapter->stats.latecol;
3065 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3066 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3067 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3068
3069 /* Tx Dropped needs to be maintained elsewhere */
3070
3071 /* Phy Stats */
3072
3073 if(hw->media_type == e1000_media_type_copper) {
3074 if((adapter->link_speed == SPEED_1000) &&
3075 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3076 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3077 adapter->phy_stats.idle_errors += phy_tmp;
3078 }
3079
3080 if((hw->mac_type <= e1000_82546) &&
3081 (hw->phy_type == e1000_phy_m88) &&
3082 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3083 adapter->phy_stats.receive_errors += phy_tmp;
3084 }
3085
3086 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3087}
3088
24025e4e
MC		 3089#ifdef CONFIG_E1000_MQ
3090void
3091e1000_rx_schedule(void *data)
3092{
3093 struct net_device *poll_dev, *netdev = data;
3094 struct e1000_adapter *adapter = netdev->priv;
3095 int this_cpu = get_cpu();
3096
3097 poll_dev = *per_cpu_ptr(adapter->cpu_netdev, this_cpu);
3098 if (poll_dev == NULL) {
3099 put_cpu();
3100 return;
3101 }
3102
3103 if (likely(netif_rx_schedule_prep(poll_dev)))
3104 __netif_rx_schedule(poll_dev);
3105 else
3106 e1000_irq_enable(adapter);
3107
3108 put_cpu();
3109}
3110#endif
3111
1da177e4
LT		 3112/**
3113 * e1000_intr - Interrupt Handler
3114 * @irq: interrupt number
3115 * @data: pointer to a network interface device structure
3116 * @pt_regs: CPU registers structure
3117 **/
3118
3119static irqreturn_t
3120e1000_intr(int irq, void *data, struct pt_regs *regs)
3121{
3122 struct net_device *netdev = data;
60490fe0 3123 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3124 struct e1000_hw *hw = &adapter->hw;
3125 uint32_t icr = E1000_READ_REG(hw, ICR);
166d823d 3126#if defined(CONFIG_E1000_NAPI) && defined(CONFIG_E1000_MQ) || !defined(CONFIG_E1000_NAPI)
581d708e 3127 int i;
be2b28ed 3128#endif
1da177e4
LT		 3129
3130 if(unlikely(!icr))
3131 return IRQ_NONE; /* Not our interrupt */
3132
3133 if(unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
3134 hw->get_link_status = 1;
3135 mod_timer(&adapter->watchdog_timer, jiffies);
3136 }
3137
3138#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3139 atomic_inc(&adapter->irq_sem);
3140 E1000_WRITE_REG(hw, IMC, ~0);
3141 E1000_WRITE_FLUSH(hw);
24025e4e
MC		 3142#ifdef CONFIG_E1000_MQ
3143 if (atomic_read(&adapter->rx_sched_call_data.count) == 0) {
3144 cpu_set(adapter->cpu_for_queue[0],
3145 adapter->rx_sched_call_data.cpumask);
3146 for (i = 1; i < adapter->num_queues; i++) {
3147 cpu_set(adapter->cpu_for_queue[i],
3148 adapter->rx_sched_call_data.cpumask);
3149 atomic_inc(&adapter->irq_sem);
3150 }
3151 atomic_set(&adapter->rx_sched_call_data.count, i);
3152 smp_call_async_mask(&adapter->rx_sched_call_data);
3153 } else {
3154 printk("call_data.count == %u\n", atomic_read(&adapter->rx_sched_call_data.count));
1da177e4 3155 }
be2b28ed 3156#else /* if !CONFIG_E1000_MQ */
581d708e
MC		 3157 if (likely(netif_rx_schedule_prep(&adapter->polling_netdev[0])))
3158 __netif_rx_schedule(&adapter->polling_netdev[0]);
3159 else
3160 e1000_irq_enable(adapter);
be2b28ed
JG		 3161#endif /* CONFIG_E1000_MQ */
3162
3163#else /* if !CONFIG_E1000_NAPI */
1da177e4
LT		 3164 /* Writing IMC and IMS is needed for 82547.
3165 Due to Hub Link bus being occupied, an interrupt
3166 de-assertion message is not able to be sent.
3167 When an interrupt assertion message is generated later,
3168 two messages are re-ordered and sent out.
3169 That causes APIC to think 82547 is in de-assertion
3170 state, while 82547 is in assertion state, resulting
3171 in dead lock. Writing IMC forces 82547 into
3172 de-assertion state.
3173 */
3174 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2){
3175 atomic_inc(&adapter->irq_sem);
2648345f 3176 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3177 }
3178
3179 for(i = 0; i < E1000_MAX_INTR; i++)
581d708e
MC		 3180 if(unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
3181 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3182 break;
3183
3184 if(hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
3185 e1000_irq_enable(adapter);
581d708e 3186
be2b28ed 3187#endif /* CONFIG_E1000_NAPI */
1da177e4
LT		 3188
3189 return IRQ_HANDLED;
3190}
3191
3192#ifdef CONFIG_E1000_NAPI
3193/**
3194 * e1000_clean - NAPI Rx polling callback
3195 * @adapter: board private structure
3196 **/
3197
3198static int
581d708e 3199e1000_clean(struct net_device *poll_dev, int *budget)
1da177e4 3200{
581d708e
MC		 3201 struct e1000_adapter *adapter;
3202 int work_to_do = min(*budget, poll_dev->quota);
3203 int tx_cleaned, i = 0, work_done = 0;
3204
3205 /* Must NOT use netdev_priv macro here. */
3206 adapter = poll_dev->priv;
3207
3208 /* Keep link state information with original netdev */
3209 if (!netif_carrier_ok(adapter->netdev))
3210 goto quit_polling;
2648345f 3211
581d708e
MC		 3212 while (poll_dev != &adapter->polling_netdev[i]) {
3213 i++;
3214 if (unlikely(i == adapter->num_queues))
3215 BUG();
3216 }
3217
3218 tx_cleaned = e1000_clean_tx_irq(adapter, &adapter->tx_ring[i]);
3219 adapter->clean_rx(adapter, &adapter->rx_ring[i],
3220 &work_done, work_to_do);
1da177e4
LT		 3221
3222 *budget -= work_done;
581d708e 3223 poll_dev->quota -= work_done;
1da177e4 3224
2b02893e 3225 /* If no Tx and not enough Rx work done, exit the polling mode */
581d708e
MC		 3226 if((!tx_cleaned && (work_done == 0)) ||
3227 !netif_running(adapter->netdev)) {
3228quit_polling:
3229 netif_rx_complete(poll_dev);
1da177e4
LT		 3230 e1000_irq_enable(adapter);
3231 return 0;
3232 }
3233
3234 return 1;
3235}
3236
3237#endif
3238/**
3239 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3240 * @adapter: board private structure
3241 **/
3242
3243static boolean_t
581d708e
MC		 3244e1000_clean_tx_irq(struct e1000_adapter *adapter,
3245 struct e1000_tx_ring *tx_ring)
1da177e4 3246{
1da177e4
LT		 3247 struct net_device *netdev = adapter->netdev;
3248 struct e1000_tx_desc *tx_desc, *eop_desc;
3249 struct e1000_buffer *buffer_info;
3250 unsigned int i, eop;
3251 boolean_t cleaned = FALSE;
3252
3253 i = tx_ring->next_to_clean;
3254 eop = tx_ring->buffer_info[i].next_to_watch;
3255 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3256
581d708e 3257 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
1da177e4
LT		 3258 for(cleaned = FALSE; !cleaned; ) {
3259 tx_desc = E1000_TX_DESC(*tx_ring, i);
3260 buffer_info = &tx_ring->buffer_info[i];
3261 cleaned = (i == eop);
3262
fd803241 3263 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
1da177e4
LT		 3264
3265 tx_desc->buffer_addr = 0;
3266 tx_desc->lower.data = 0;
3267 tx_desc->upper.data = 0;
3268
1da177e4
LT		 3269 if(unlikely(++i == tx_ring->count)) i = 0;
3270 }
581d708e 3271
1da177e4
LT		 3272 eop = tx_ring->buffer_info[i].next_to_watch;
3273 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3274 }
3275
3276 tx_ring->next_to_clean = i;
3277
581d708e 3278 spin_lock(&tx_ring->tx_lock);
1da177e4
LT		 3279
3280 if(unlikely(cleaned && netif_queue_stopped(netdev) &&
3281 netif_carrier_ok(netdev)))
3282 netif_wake_queue(netdev);
3283
581d708e 3284 spin_unlock(&tx_ring->tx_lock);
2648345f 3285
581d708e 3286 if (adapter->detect_tx_hung) {
2648345f 3287 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 3288 * check with the clearing of time_stamp and movement of i */
3289 adapter->detect_tx_hung = FALSE;
70b8f1e1
MC		 3290 if (tx_ring->buffer_info[i].dma &&
3291 time_after(jiffies, tx_ring->buffer_info[i].time_stamp + HZ)
3292 && !(E1000_READ_REG(&adapter->hw, STATUS) &
3293 E1000_STATUS_TXOFF)) {
3294
3295 /* detected Tx unit hang */
3296 i = tx_ring->next_to_clean;
3297 eop = tx_ring->buffer_info[i].next_to_watch;
3298 eop_desc = E1000_TX_DESC(*tx_ring, eop);
c6963ef5 3299 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
70b8f1e1
MC		 3300 " TDH <%x>\n"
3301 " TDT <%x>\n"
3302 " next_to_use <%x>\n"
3303 " next_to_clean <%x>\n"
3304 "buffer_info[next_to_clean]\n"
b4ee21f4 3305 " dma <%llx>\n"
70b8f1e1
MC		 3306 " time_stamp <%lx>\n"
3307 " next_to_watch <%x>\n"
3308 " jiffies <%lx>\n"
3309 " next_to_watch.status <%x>\n",
581d708e
MC		 3310 readl(adapter->hw.hw_addr + tx_ring->tdh),
3311 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1
MC		 3312 tx_ring->next_to_use,
3313 i,
b4ee21f4 3314 (unsigned long long)tx_ring->buffer_info[i].dma,
70b8f1e1
MC		 3315 tx_ring->buffer_info[i].time_stamp,
3316 eop,
3317 jiffies,
3318 eop_desc->upper.fields.status);
1da177e4 3319 netif_stop_queue(netdev);
70b8f1e1 3320 }
1da177e4 3321 }
1da177e4
LT		 3322 return cleaned;
3323}
3324
3325/**
3326 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 3327 * @adapter: board private structure
3328 * @status_err: receive descriptor status and error fields
3329 * @csum: receive descriptor csum field
3330 * @sk_buff: socket buffer with received data
1da177e4
LT		 3331 **/
3332
3333static inline void
3334e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 3335 uint32_t status_err, uint32_t csum,
3336 struct sk_buff *skb)
1da177e4 3337{
2d7edb92
MC		 3338 uint16_t status = (uint16_t)status_err;
3339 uint8_t errors = (uint8_t)(status_err >> 24);
3340 skb->ip_summed = CHECKSUM_NONE;
3341
1da177e4 3342 /* 82543 or newer only */
2d7edb92 3343 if(unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 3344 /* Ignore Checksum bit is set */
2d7edb92
MC		 3345 if(unlikely(status & E1000_RXD_STAT_IXSM)) return;
3346 /* TCP/UDP checksum error bit is set */
3347 if(unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 3348 /* let the stack verify checksum errors */
1da177e4 3349 adapter->hw_csum_err++;
2d7edb92
MC		 3350 return;
3351 }
3352 /* TCP/UDP Checksum has not been calculated */
3353 if(adapter->hw.mac_type <= e1000_82547_rev_2) {
3354 if(!(status & E1000_RXD_STAT_TCPCS))
3355 return;
1da177e4 3356 } else {
2d7edb92
MC		 3357 if(!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
3358 return;
3359 }
3360 /* It must be a TCP or UDP packet with a valid checksum */
3361 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 3362 /* TCP checksum is good */
3363 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 3364 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
3365 /* IP fragment with UDP payload */
3366 /* Hardware complements the payload checksum, so we undo it
3367 * and then put the value in host order for further stack use.
3368 */
3369 csum = ntohl(csum ^ 0xFFFF);
3370 skb->csum = csum;
3371 skb->ip_summed = CHECKSUM_HW;
1da177e4 3372 }
2d7edb92 3373 adapter->hw_csum_good++;
1da177e4
LT		 3374}
3375
3376/**
2d7edb92 3377 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 3378 * @adapter: board private structure
3379 **/
3380
3381static boolean_t
3382#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3383e1000_clean_rx_irq(struct e1000_adapter *adapter,
3384 struct e1000_rx_ring *rx_ring,
3385 int *work_done, int work_to_do)
1da177e4 3386#else
581d708e
MC		 3387e1000_clean_rx_irq(struct e1000_adapter *adapter,
3388 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 3389#endif
3390{
1da177e4
LT		 3391 struct net_device *netdev = adapter->netdev;
3392 struct pci_dev *pdev = adapter->pdev;
3393 struct e1000_rx_desc *rx_desc;
3394 struct e1000_buffer *buffer_info;
3395 struct sk_buff *skb;
3396 unsigned long flags;
3397 uint32_t length;
3398 uint8_t last_byte;
3399 unsigned int i;
3400 boolean_t cleaned = FALSE;
3401
3402 i = rx_ring->next_to_clean;
3403 rx_desc = E1000_RX_DESC(*rx_ring, i);
3404
3405 while(rx_desc->status & E1000_RXD_STAT_DD) {
3406 buffer_info = &rx_ring->buffer_info[i];
3407#ifdef CONFIG_E1000_NAPI
3408 if(*work_done >= work_to_do)
3409 break;
3410 (*work_done)++;
3411#endif
3412 cleaned = TRUE;
3413
3414 pci_unmap_single(pdev,
3415 buffer_info->dma,
3416 buffer_info->length,
3417 PCI_DMA_FROMDEVICE);
3418
3419 skb = buffer_info->skb;
3420 length = le16_to_cpu(rx_desc->length);
3421
3422 if(unlikely(!(rx_desc->status & E1000_RXD_STAT_EOP))) {
3423 /* All receives must fit into a single buffer */
3424 E1000_DBG("%s: Receive packet consumed multiple"
2648345f 3425 " buffers\n", netdev->name);
1da177e4
LT		 3426 dev_kfree_skb_irq(skb);
3427 goto next_desc;
3428 }
3429
3430 if(unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
3431 last_byte = *(skb->data + length - 1);
3432 if(TBI_ACCEPT(&adapter->hw, rx_desc->status,
3433 rx_desc->errors, length, last_byte)) {
3434 spin_lock_irqsave(&adapter->stats_lock, flags);
3435 e1000_tbi_adjust_stats(&adapter->hw,
3436 &adapter->stats,
3437 length, skb->data);
3438 spin_unlock_irqrestore(&adapter->stats_lock,
3439 flags);
3440 length--;
3441 } else {
3442 dev_kfree_skb_irq(skb);
3443 goto next_desc;
3444 }
3445 }
3446
3447 /* Good Receive */
3448 skb_put(skb, length - ETHERNET_FCS_SIZE);
3449
3450 /* Receive Checksum Offload */
2d7edb92
MC		 3451 e1000_rx_checksum(adapter,
3452 (uint32_t)(rx_desc->status) |
3453 ((uint32_t)(rx_desc->errors) << 24),
3454 rx_desc->csum, skb);
1da177e4
LT		 3455 skb->protocol = eth_type_trans(skb, netdev);
3456#ifdef CONFIG_E1000_NAPI
3457 if(unlikely(adapter->vlgrp &&
3458 (rx_desc->status & E1000_RXD_STAT_VP))) {
3459 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 3460 le16_to_cpu(rx_desc->special) &
3461 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 3462 } else {
3463 netif_receive_skb(skb);
3464 }
3465#else /* CONFIG_E1000_NAPI */
3466 if(unlikely(adapter->vlgrp &&
3467 (rx_desc->status & E1000_RXD_STAT_VP))) {
3468 vlan_hwaccel_rx(skb, adapter->vlgrp,
3469 le16_to_cpu(rx_desc->special) &
3470 E1000_RXD_SPC_VLAN_MASK);
3471 } else {
3472 netif_rx(skb);
3473 }
3474#endif /* CONFIG_E1000_NAPI */
3475 netdev->last_rx = jiffies;
3476
3477next_desc:
3478 rx_desc->status = 0;
3479 buffer_info->skb = NULL;
3480 if(unlikely(++i == rx_ring->count)) i = 0;
3481
3482 rx_desc = E1000_RX_DESC(*rx_ring, i);
3483 }
1da177e4 3484 rx_ring->next_to_clean = i;
581d708e 3485 adapter->alloc_rx_buf(adapter, rx_ring);
2d7edb92
MC		 3486
3487 return cleaned;
3488}
3489
3490/**
3491 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
3492 * @adapter: board private structure
3493 **/
3494
3495static boolean_t
3496#ifdef CONFIG_E1000_NAPI
581d708e
MC		 3497e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3498 struct e1000_rx_ring *rx_ring,
3499 int *work_done, int work_to_do)
2d7edb92 3500#else
581d708e
MC		 3501e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
3502 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 3503#endif
3504{
2d7edb92
MC		 3505 union e1000_rx_desc_packet_split *rx_desc;
3506 struct net_device *netdev = adapter->netdev;
3507 struct pci_dev *pdev = adapter->pdev;
3508 struct e1000_buffer *buffer_info;
3509 struct e1000_ps_page *ps_page;
3510 struct e1000_ps_page_dma *ps_page_dma;
3511 struct sk_buff *skb;
3512 unsigned int i, j;
3513 uint32_t length, staterr;
3514 boolean_t cleaned = FALSE;
3515
3516 i = rx_ring->next_to_clean;
3517 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3518 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3519
3520 while(staterr & E1000_RXD_STAT_DD) {
3521 buffer_info = &rx_ring->buffer_info[i];
3522 ps_page = &rx_ring->ps_page[i];
3523 ps_page_dma = &rx_ring->ps_page_dma[i];
3524#ifdef CONFIG_E1000_NAPI
3525 if(unlikely(*work_done >= work_to_do))
3526 break;
3527 (*work_done)++;
3528#endif
3529 cleaned = TRUE;
3530 pci_unmap_single(pdev, buffer_info->dma,
3531 buffer_info->length,
3532 PCI_DMA_FROMDEVICE);
3533
3534 skb = buffer_info->skb;
3535
3536 if(unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
3537 E1000_DBG("%s: Packet Split buffers didn't pick up"
3538 " the full packet\n", netdev->name);
3539 dev_kfree_skb_irq(skb);
3540 goto next_desc;
3541 }
1da177e4 3542
2d7edb92
MC		 3543 if(unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3544 dev_kfree_skb_irq(skb);
3545 goto next_desc;
3546 }
3547
3548 length = le16_to_cpu(rx_desc->wb.middle.length0);
3549
3550 if(unlikely(!length)) {
3551 E1000_DBG("%s: Last part of the packet spanning"
3552 " multiple descriptors\n", netdev->name);
3553 dev_kfree_skb_irq(skb);
3554 goto next_desc;
3555 }
3556
3557 /* Good Receive */
3558 skb_put(skb, length);
3559
e4c811c9 3560 for(j = 0; j < adapter->rx_ps_pages; j++) {
2d7edb92
MC		 3561 if(!(length = le16_to_cpu(rx_desc->wb.upper.length[j])))
3562 break;
3563
3564 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
3565 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3566 ps_page_dma->ps_page_dma[j] = 0;
3567 skb_shinfo(skb)->frags[j].page =
3568 ps_page->ps_page[j];
3569 ps_page->ps_page[j] = NULL;
3570 skb_shinfo(skb)->frags[j].page_offset = 0;
3571 skb_shinfo(skb)->frags[j].size = length;
3572 skb_shinfo(skb)->nr_frags++;
3573 skb->len += length;
3574 skb->data_len += length;
3575 }
3576
3577 e1000_rx_checksum(adapter, staterr,
3578 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
3579 skb->protocol = eth_type_trans(skb, netdev);
3580
2d7edb92 3581 if(likely(rx_desc->wb.upper.header_status &
e4c811c9
MC		 3582 E1000_RXDPS_HDRSTAT_HDRSP)) {
3583 adapter->rx_hdr_split++;
3584#ifdef HAVE_RX_ZERO_COPY
2d7edb92
MC		 3585 skb_shinfo(skb)->zero_copy = TRUE;
3586#endif
e4c811c9 3587 }
2d7edb92
MC		 3588#ifdef CONFIG_E1000_NAPI
3589 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3590 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 3591 le16_to_cpu(rx_desc->wb.middle.vlan) &
3592 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3593 } else {
3594 netif_receive_skb(skb);
3595 }
3596#else /* CONFIG_E1000_NAPI */
3597 if(unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
3598 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 3599 le16_to_cpu(rx_desc->wb.middle.vlan) &
3600 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 3601 } else {
3602 netif_rx(skb);
3603 }
3604#endif /* CONFIG_E1000_NAPI */
3605 netdev->last_rx = jiffies;
3606
3607next_desc:
3608 rx_desc->wb.middle.status_error &= ~0xFF;
3609 buffer_info->skb = NULL;
3610 if(unlikely(++i == rx_ring->count)) i = 0;
3611
3612 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 3613 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 3614 }
3615 rx_ring->next_to_clean = i;
581d708e 3616 adapter->alloc_rx_buf(adapter, rx_ring);
1da177e4
LT		 3617
3618 return cleaned;
3619}
3620
3621/**
2d7edb92 3622 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 3623 * @adapter: address of board private structure
3624 **/
3625
3626static void
581d708e
MC		 3627e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
3628 struct e1000_rx_ring *rx_ring)
1da177e4 3629{
1da177e4
LT		 3630 struct net_device *netdev = adapter->netdev;
3631 struct pci_dev *pdev = adapter->pdev;
3632 struct e1000_rx_desc *rx_desc;
3633 struct e1000_buffer *buffer_info;
3634 struct sk_buff *skb;
2648345f
MC		 3635 unsigned int i;
3636 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 3637
3638 i = rx_ring->next_to_use;
3639 buffer_info = &rx_ring->buffer_info[i];
3640
3641 while(!buffer_info->skb) {
1da177e4 3642 skb = dev_alloc_skb(bufsz);
2648345f 3643
1da177e4
LT		 3644 if(unlikely(!skb)) {
3645 /* Better luck next round */
3646 break;
3647 }
3648
2648345f 3649 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 3650 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3651 struct sk_buff *oldskb = skb;
2648345f
MC		 3652 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
3653 "at %p\n", bufsz, skb->data);
3654 /* Try again, without freeing the previous */
1da177e4 3655 skb = dev_alloc_skb(bufsz);
2648345f 3656 /* Failed allocation, critical failure */
1da177e4
LT		 3657 if (!skb) {
3658 dev_kfree_skb(oldskb);
3659 break;
3660 }
2648345f 3661
1da177e4
LT		 3662 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
3663 /* give up */
3664 dev_kfree_skb(skb);
3665 dev_kfree_skb(oldskb);
3666 break; /* while !buffer_info->skb */
3667 } else {
2648345f 3668 /* Use new allocation */
1da177e4
LT		 3669 dev_kfree_skb(oldskb);
3670 }
3671 }
1da177e4
LT		 3672 /* Make buffer alignment 2 beyond a 16 byte boundary
3673 * this will result in a 16 byte aligned IP header after
3674 * the 14 byte MAC header is removed
3675 */
3676 skb_reserve(skb, NET_IP_ALIGN);
3677
3678 skb->dev = netdev;
3679
3680 buffer_info->skb = skb;
3681 buffer_info->length = adapter->rx_buffer_len;
3682 buffer_info->dma = pci_map_single(pdev,
3683 skb->data,
3684 adapter->rx_buffer_len,
3685 PCI_DMA_FROMDEVICE);
3686
2648345f
MC		 3687 /* Fix for errata 23, can't cross 64kB boundary */
3688 if (!e1000_check_64k_bound(adapter,
3689 (void *)(unsigned long)buffer_info->dma,
3690 adapter->rx_buffer_len)) {
3691 DPRINTK(RX_ERR, ERR,
3692 "dma align check failed: %u bytes at %p\n",
3693 adapter->rx_buffer_len,
3694 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 3695 dev_kfree_skb(skb);
3696 buffer_info->skb = NULL;
3697
2648345f 3698 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 3699 adapter->rx_buffer_len,
3700 PCI_DMA_FROMDEVICE);
3701
3702 break; /* while !buffer_info->skb */
3703 }
1da177e4
LT		 3704 rx_desc = E1000_RX_DESC(*rx_ring, i);
3705 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3706
3707 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3708 /* Force memory writes to complete before letting h/w
3709 * know there are new descriptors to fetch. (Only
3710 * applicable for weak-ordered memory model archs,
3711 * such as IA-64). */
3712 wmb();
581d708e 3713 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
1da177e4
LT		 3714 }
3715
3716 if(unlikely(++i == rx_ring->count)) i = 0;
3717 buffer_info = &rx_ring->buffer_info[i];
3718 }
3719
3720 rx_ring->next_to_use = i;
3721}
3722
2d7edb92
MC		 3723/**
3724 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
3725 * @adapter: address of board private structure
3726 **/
3727
3728static void
581d708e
MC		 3729e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
3730 struct e1000_rx_ring *rx_ring)
2d7edb92 3731{
2d7edb92
MC		 3732 struct net_device *netdev = adapter->netdev;
3733 struct pci_dev *pdev = adapter->pdev;
3734 union e1000_rx_desc_packet_split *rx_desc;
3735 struct e1000_buffer *buffer_info;
3736 struct e1000_ps_page *ps_page;
3737 struct e1000_ps_page_dma *ps_page_dma;
3738 struct sk_buff *skb;
3739 unsigned int i, j;
3740
3741 i = rx_ring->next_to_use;
3742 buffer_info = &rx_ring->buffer_info[i];
3743 ps_page = &rx_ring->ps_page[i];
3744 ps_page_dma = &rx_ring->ps_page_dma[i];
3745
3746 while(!buffer_info->skb) {
3747 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
3748
3749 for(j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 3750 if (j < adapter->rx_ps_pages) {
3751 if (likely(!ps_page->ps_page[j])) {
3752 ps_page->ps_page[j] =
3753 alloc_page(GFP_ATOMIC);
3754 if (unlikely(!ps_page->ps_page[j]))
3755 goto no_buffers;
3756 ps_page_dma->ps_page_dma[j] =
3757 pci_map_page(pdev,
3758 ps_page->ps_page[j],
3759 0, PAGE_SIZE,
3760 PCI_DMA_FROMDEVICE);
3761 }
3762 /* Refresh the desc even if buffer_addrs didn't
3763 * change because each write-back erases
3764 * this info.
3765 */
3766 rx_desc->read.buffer_addr[j+1] =
3767 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
3768 } else
3769 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 3770 }
3771
3772 skb = dev_alloc_skb(adapter->rx_ps_bsize0 + NET_IP_ALIGN);
3773
3774 if(unlikely(!skb))
3775 break;
3776
3777 /* Make buffer alignment 2 beyond a 16 byte boundary
3778 * this will result in a 16 byte aligned IP header after
3779 * the 14 byte MAC header is removed
3780 */
3781 skb_reserve(skb, NET_IP_ALIGN);
3782
3783 skb->dev = netdev;
3784
3785 buffer_info->skb = skb;
3786 buffer_info->length = adapter->rx_ps_bsize0;
3787 buffer_info->dma = pci_map_single(pdev, skb->data,
3788 adapter->rx_ps_bsize0,
3789 PCI_DMA_FROMDEVICE);
3790
3791 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
3792
3793 if(unlikely((i & ~(E1000_RX_BUFFER_WRITE - 1)) == i)) {
3794 /* Force memory writes to complete before letting h/w
3795 * know there are new descriptors to fetch. (Only
3796 * applicable for weak-ordered memory model archs,
3797 * such as IA-64). */
3798 wmb();
3799 /* Hardware increments by 16 bytes, but packet split
3800 * descriptors are 32 bytes...so we increment tail
3801 * twice as much.
3802 */
581d708e 3803 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
2d7edb92
MC		 3804 }
3805
3806 if(unlikely(++i == rx_ring->count)) i = 0;
3807 buffer_info = &rx_ring->buffer_info[i];
3808 ps_page = &rx_ring->ps_page[i];
3809 ps_page_dma = &rx_ring->ps_page_dma[i];
3810 }
3811
3812no_buffers:
3813 rx_ring->next_to_use = i;
3814}
3815
1da177e4
LT		 3816/**
3817 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
3818 * @adapter:
3819 **/
3820
3821static void
3822e1000_smartspeed(struct e1000_adapter *adapter)
3823{
3824 uint16_t phy_status;
3825 uint16_t phy_ctrl;
3826
3827 if((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
3828 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
3829 return;
3830
3831 if(adapter->smartspeed == 0) {
3832 /* If Master/Slave config fault is asserted twice,
3833 * we assume back-to-back */
3834 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3835 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3836 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
3837 if(!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
3838 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3839 if(phy_ctrl & CR_1000T_MS_ENABLE) {
3840 phy_ctrl &= ~CR_1000T_MS_ENABLE;
3841 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
3842 phy_ctrl);
3843 adapter->smartspeed++;
3844 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3845 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
3846 &phy_ctrl)) {
3847 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3848 MII_CR_RESTART_AUTO_NEG);
3849 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
3850 phy_ctrl);
3851 }
3852 }
3853 return;
3854 } else if(adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
3855 /* If still no link, perhaps using 2/3 pair cable */
3856 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
3857 phy_ctrl |= CR_1000T_MS_ENABLE;
3858 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
3859 if(!e1000_phy_setup_autoneg(&adapter->hw) &&
3860 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
3861 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
3862 MII_CR_RESTART_AUTO_NEG);
3863 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
3864 }
3865 }
3866 /* Restart process after E1000_SMARTSPEED_MAX iterations */
3867 if(adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
3868 adapter->smartspeed = 0;
3869}
3870
3871/**
3872 * e1000_ioctl -
3873 * @netdev:
3874 * @ifreq:
3875 * @cmd:
3876 **/
3877
3878static int
3879e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3880{
3881 switch (cmd) {
3882 case SIOCGMIIPHY:
3883 case SIOCGMIIREG:
3884 case SIOCSMIIREG:
3885 return e1000_mii_ioctl(netdev, ifr, cmd);
3886 default:
3887 return -EOPNOTSUPP;
3888 }
3889}
3890
3891/**
3892 * e1000_mii_ioctl -
3893 * @netdev:
3894 * @ifreq:
3895 * @cmd:
3896 **/
3897
3898static int
3899e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3900{
60490fe0 3901 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3902 struct mii_ioctl_data *data = if_mii(ifr);
3903 int retval;
3904 uint16_t mii_reg;
3905 uint16_t spddplx;
97876fc6 3906 unsigned long flags;
1da177e4
LT		 3907
3908 if(adapter->hw.media_type != e1000_media_type_copper)
3909 return -EOPNOTSUPP;
3910
3911 switch (cmd) {
3912 case SIOCGMIIPHY:
3913 data->phy_id = adapter->hw.phy_addr;
3914 break;
3915 case SIOCGMIIREG:
97876fc6 3916 if(!capable(CAP_NET_ADMIN))
1da177e4 3917 return -EPERM;
97876fc6
MC		 3918 spin_lock_irqsave(&adapter->stats_lock, flags);
3919 if(e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
3920 &data->val_out)) {
3921 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 3922 return -EIO;
97876fc6
MC		 3923 }
3924 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 3925 break;
3926 case SIOCSMIIREG:
97876fc6 3927 if(!capable(CAP_NET_ADMIN))
1da177e4 3928 return -EPERM;
97876fc6 3929 if(data->reg_num & ~(0x1F))
1da177e4
LT		 3930 return -EFAULT;
3931 mii_reg = data->val_in;
97876fc6
MC		 3932 spin_lock_irqsave(&adapter->stats_lock, flags);
3933 if(e1000_write_phy_reg(&adapter->hw, data->reg_num,
3934 mii_reg)) {
3935 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 3936 return -EIO;
97876fc6
MC		 3937 }
3938 if(adapter->hw.phy_type == e1000_phy_m88) {
1da177e4
LT		 3939 switch (data->reg_num) {
3940 case PHY_CTRL:
3941 if(mii_reg & MII_CR_POWER_DOWN)
3942 break;
3943 if(mii_reg & MII_CR_AUTO_NEG_EN) {
3944 adapter->hw.autoneg = 1;
3945 adapter->hw.autoneg_advertised = 0x2F;
3946 } else {
3947 if (mii_reg & 0x40)
3948 spddplx = SPEED_1000;
3949 else if (mii_reg & 0x2000)
3950 spddplx = SPEED_100;
3951 else
3952 spddplx = SPEED_10;
3953 spddplx += (mii_reg & 0x100)
3954 ? FULL_DUPLEX :
3955 HALF_DUPLEX;
3956 retval = e1000_set_spd_dplx(adapter,
3957 spddplx);
97876fc6
MC		 3958 if(retval) {
3959 spin_unlock_irqrestore(
3960 &adapter->stats_lock,
3961 flags);
1da177e4 3962 return retval;
97876fc6 3963 }
1da177e4
LT		 3964 }
3965 if(netif_running(adapter->netdev)) {
3966 e1000_down(adapter);
3967 e1000_up(adapter);
3968 } else
3969 e1000_reset(adapter);
3970 break;
3971 case M88E1000_PHY_SPEC_CTRL:
3972 case M88E1000_EXT_PHY_SPEC_CTRL:
97876fc6
MC		 3973 if(e1000_phy_reset(&adapter->hw)) {
3974 spin_unlock_irqrestore(
3975 &adapter->stats_lock, flags);
1da177e4 3976 return -EIO;
97876fc6 3977 }
1da177e4
LT		 3978 break;
3979 }
3980 } else {
3981 switch (data->reg_num) {
3982 case PHY_CTRL:
3983 if(mii_reg & MII_CR_POWER_DOWN)
3984 break;
3985 if(netif_running(adapter->netdev)) {
3986 e1000_down(adapter);
3987 e1000_up(adapter);
3988 } else
3989 e1000_reset(adapter);
3990 break;
3991 }
3992 }
97876fc6 3993 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 3994 break;
3995 default:
3996 return -EOPNOTSUPP;
3997 }
3998 return E1000_SUCCESS;
3999}
4000
4001void
4002e1000_pci_set_mwi(struct e1000_hw *hw)
4003{
4004 struct e1000_adapter *adapter = hw->back;
2648345f 4005 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4006
2648345f
MC		 4007 if(ret_val)
4008 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4009}
4010
4011void
4012e1000_pci_clear_mwi(struct e1000_hw *hw)
4013{
4014 struct e1000_adapter *adapter = hw->back;
4015
4016 pci_clear_mwi(adapter->pdev);
4017}
4018
4019void
4020e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4021{
4022 struct e1000_adapter *adapter = hw->back;
4023
4024 pci_read_config_word(adapter->pdev, reg, value);
4025}
4026
4027void
4028e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4029{
4030 struct e1000_adapter *adapter = hw->back;
4031
4032 pci_write_config_word(adapter->pdev, reg, *value);
4033}
4034
4035uint32_t
4036e1000_io_read(struct e1000_hw *hw, unsigned long port)
4037{
4038 return inl(port);
4039}
4040
4041void
4042e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4043{
4044 outl(value, port);
4045}
4046
4047static void
4048e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4049{
60490fe0 4050 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4051 uint32_t ctrl, rctl;
4052
4053 e1000_irq_disable(adapter);
4054 adapter->vlgrp = grp;
4055
4056 if(grp) {
4057 /* enable VLAN tag insert/strip */
4058 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4059 ctrl |= E1000_CTRL_VME;
4060 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4061
4062 /* enable VLAN receive filtering */
4063 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4064 rctl |= E1000_RCTL_VFE;
4065 rctl &= ~E1000_RCTL_CFIEN;
4066 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92 4067 e1000_update_mng_vlan(adapter);
1da177e4
LT		 4068 } else {
4069 /* disable VLAN tag insert/strip */
4070 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4071 ctrl &= ~E1000_CTRL_VME;
4072 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4073
4074 /* disable VLAN filtering */
4075 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4076 rctl &= ~E1000_RCTL_VFE;
4077 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2d7edb92
MC		 4078 if(adapter->mng_vlan_id != (uint16_t)E1000_MNG_VLAN_NONE) {
4079 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
4080 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4081 }
1da177e4
LT		 4082 }
4083
4084 e1000_irq_enable(adapter);
4085}
4086
4087static void
4088e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4089{
60490fe0 4090 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4091 uint32_t vfta, index;
2d7edb92
MC		 4092 if((adapter->hw.mng_cookie.status &
4093 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4094 (vid == adapter->mng_vlan_id))
4095 return;
1da177e4
LT		 4096 /* add VID to filter table */
4097 index = (vid >> 5) & 0x7F;
4098 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4099 vfta |= (1 << (vid & 0x1F));
4100 e1000_write_vfta(&adapter->hw, index, vfta);
4101}
4102
4103static void
4104e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4105{
60490fe0 4106 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4107 uint32_t vfta, index;
4108
4109 e1000_irq_disable(adapter);
4110
4111 if(adapter->vlgrp)
4112 adapter->vlgrp->vlan_devices[vid] = NULL;
4113
4114 e1000_irq_enable(adapter);
4115
2d7edb92
MC		 4116 if((adapter->hw.mng_cookie.status &
4117 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4118 (vid == adapter->mng_vlan_id))
4119 return;
1da177e4
LT		 4120 /* remove VID from filter table */
4121 index = (vid >> 5) & 0x7F;
4122 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4123 vfta &= ~(1 << (vid & 0x1F));
4124 e1000_write_vfta(&adapter->hw, index, vfta);
4125}
4126
4127static void
4128e1000_restore_vlan(struct e1000_adapter *adapter)
4129{
4130 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4131
4132 if(adapter->vlgrp) {
4133 uint16_t vid;
4134 for(vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
4135 if(!adapter->vlgrp->vlan_devices[vid])
4136 continue;
4137 e1000_vlan_rx_add_vid(adapter->netdev, vid);
4138 }
4139 }
4140}
4141
4142int
4143e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
4144{
4145 adapter->hw.autoneg = 0;
4146
6921368f
MC		 4147 /* Fiber NICs only allow 1000 gbps Full duplex */
4148 if((adapter->hw.media_type == e1000_media_type_fiber) &&
4149 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
4150 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
4151 return -EINVAL;
4152 }
4153
1da177e4
LT		 4154 switch(spddplx) {
4155 case SPEED_10 + DUPLEX_HALF:
4156 adapter->hw.forced_speed_duplex = e1000_10_half;
4157 break;
4158 case SPEED_10 + DUPLEX_FULL:
4159 adapter->hw.forced_speed_duplex = e1000_10_full;
4160 break;
4161 case SPEED_100 + DUPLEX_HALF:
4162 adapter->hw.forced_speed_duplex = e1000_100_half;
4163 break;
4164 case SPEED_100 + DUPLEX_FULL:
4165 adapter->hw.forced_speed_duplex = e1000_100_full;
4166 break;
4167 case SPEED_1000 + DUPLEX_FULL:
4168 adapter->hw.autoneg = 1;
4169 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
4170 break;
4171 case SPEED_1000 + DUPLEX_HALF: /* not supported */
4172 default:
2648345f 4173 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 4174 return -EINVAL;
4175 }
4176 return 0;
4177}
4178
b6a1d5f8 4179#ifdef CONFIG_PM
1da177e4 4180static int
829ca9a3 4181e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 4182{
4183 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4184 struct e1000_adapter *adapter = netdev_priv(netdev);
2d7edb92 4185 uint32_t ctrl, ctrl_ext, rctl, manc, status, swsm;
1da177e4
LT		 4186 uint32_t wufc = adapter->wol;
4187
4188 netif_device_detach(netdev);
4189
4190 if(netif_running(netdev))
4191 e1000_down(adapter);
4192
4193 status = E1000_READ_REG(&adapter->hw, STATUS);
4194 if(status & E1000_STATUS_LU)
4195 wufc &= ~E1000_WUFC_LNKC;
4196
4197 if(wufc) {
4198 e1000_setup_rctl(adapter);
4199 e1000_set_multi(netdev);
4200
4201 /* turn on all-multi mode if wake on multicast is enabled */
4202 if(adapter->wol & E1000_WUFC_MC) {
4203 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4204 rctl |= E1000_RCTL_MPE;
4205 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4206 }
4207
4208 if(adapter->hw.mac_type >= e1000_82540) {
4209 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4210 /* advertise wake from D3Cold */
4211 #define E1000_CTRL_ADVD3WUC 0x00100000
4212 /* phy power management enable */
4213 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
4214 ctrl |= E1000_CTRL_ADVD3WUC |
4215 E1000_CTRL_EN_PHY_PWR_MGMT;
4216 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4217 }
4218
4219 if(adapter->hw.media_type == e1000_media_type_fiber ||
4220 adapter->hw.media_type == e1000_media_type_internal_serdes) {
4221 /* keep the laser running in D3 */
4222 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4223 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
4224 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
4225 }
4226
2d7edb92
MC		 4227 /* Allow time for pending master requests to run */
4228 e1000_disable_pciex_master(&adapter->hw);
4229
1da177e4
LT		 4230 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
4231 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
4232 pci_enable_wake(pdev, 3, 1);
4233 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
4234 } else {
4235 E1000_WRITE_REG(&adapter->hw, WUC, 0);
4236 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
4237 pci_enable_wake(pdev, 3, 0);
4238 pci_enable_wake(pdev, 4, 0); /* 4 == D3 cold */
4239 }
4240
4241 pci_save_state(pdev);
4242
4243 if(adapter->hw.mac_type >= e1000_82540 &&
4244 adapter->hw.media_type == e1000_media_type_copper) {
4245 manc = E1000_READ_REG(&adapter->hw, MANC);
4246 if(manc & E1000_MANC_SMBUS_EN) {
4247 manc |= E1000_MANC_ARP_EN;
4248 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4249 pci_enable_wake(pdev, 3, 1);
4250 pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
4251 }
4252 }
4253
2d7edb92 4254 switch(adapter->hw.mac_type) {
868d5309
MC		 4255 case e1000_82571:
4256 case e1000_82572:
4257 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4258 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
4259 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
4260 break;
2d7edb92
MC		 4261 case e1000_82573:
4262 swsm = E1000_READ_REG(&adapter->hw, SWSM);
4263 E1000_WRITE_REG(&adapter->hw, SWSM,
4264 swsm & ~E1000_SWSM_DRV_LOAD);
4265 break;
4266 default:
4267 break;
4268 }
4269
1da177e4 4270 pci_disable_device(pdev);
829ca9a3 4271 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 4272
4273 return 0;
4274}
4275
1da177e4
LT		 4276static int
4277e1000_resume(struct pci_dev *pdev)
4278{
4279 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 4280 struct e1000_adapter *adapter = netdev_priv(netdev);
2b02893e 4281 uint32_t manc, ret_val, swsm;
868d5309 4282 uint32_t ctrl_ext;
1da177e4 4283
829ca9a3 4284 pci_set_power_state(pdev, PCI_D0);
1da177e4 4285 pci_restore_state(pdev);
2b02893e 4286 ret_val = pci_enable_device(pdev);
a4cb847d 4287 pci_set_master(pdev);
1da177e4 4288
829ca9a3
PM		 4289 pci_enable_wake(pdev, PCI_D3hot, 0);
4290 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 4291
4292 e1000_reset(adapter);
4293 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
4294
4295 if(netif_running(netdev))
4296 e1000_up(adapter);
4297
4298 netif_device_attach(netdev);
4299
4300 if(adapter->hw.mac_type >= e1000_82540 &&
4301 adapter->hw.media_type == e1000_media_type_copper) {
4302 manc = E1000_READ_REG(&adapter->hw, MANC);
4303 manc &= ~(E1000_MANC_ARP_EN);
4304 E1000_WRITE_REG(&adapter->hw, MANC, manc);
4305 }
4306
2d7edb92 4307 switch(adapter->hw.mac_type) {
868d5309
MC		 4308 case e1000_82571:
4309 case e1000_82572:
4310 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
4311 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
4312 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
4313 break;
2d7edb92
MC		 4314 case e1000_82573:
4315 swsm = E1000_READ_REG(&adapter->hw, SWSM);
4316 E1000_WRITE_REG(&adapter->hw, SWSM,
4317 swsm | E1000_SWSM_DRV_LOAD);
4318 break;
4319 default:
4320 break;
4321 }
4322
1da177e4
LT		 4323 return 0;
4324}
4325#endif
1da177e4
LT		 4326#ifdef CONFIG_NET_POLL_CONTROLLER
4327/*
4328 * Polling 'interrupt' - used by things like netconsole to send skbs
4329 * without having to re-enable interrupts. It's not called while
4330 * the interrupt routine is executing.
4331 */
4332static void
2648345f 4333e1000_netpoll(struct net_device *netdev)
1da177e4 4334{
60490fe0 4335 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4336 disable_irq(adapter->pdev->irq);
4337 e1000_intr(adapter->pdev->irq, netdev, NULL);
c4cfe567 4338 e1000_clean_tx_irq(adapter, adapter->tx_ring);
1da177e4
LT		 4339 enable_irq(adapter->pdev->irq);
4340}
4341#endif
4342
4343/* e1000_main.c */
Linux kernel - Deliverables
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