projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgb: enable sun hardware support for broadcom phy
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
d0bb53e1 30#include <net/ip6_checksum.h>
1da177e4 31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
7e721579 39#define DRV_VERSION "7.3.20-k2"DRIVERNAPI
abec42a4
SH		 40const char e1000_driver_version[] = DRV_VERSION;
41static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
51 INTEL_E1000_ETHERNET_DEVICE(0x1000),
52 INTEL_E1000_ETHERNET_DEVICE(0x1001),
53 INTEL_E1000_ETHERNET_DEVICE(0x1004),
54 INTEL_E1000_ETHERNET_DEVICE(0x1008),
55 INTEL_E1000_ETHERNET_DEVICE(0x1009),
56 INTEL_E1000_ETHERNET_DEVICE(0x100C),
57 INTEL_E1000_ETHERNET_DEVICE(0x100D),
58 INTEL_E1000_ETHERNET_DEVICE(0x100E),
59 INTEL_E1000_ETHERNET_DEVICE(0x100F),
60 INTEL_E1000_ETHERNET_DEVICE(0x1010),
61 INTEL_E1000_ETHERNET_DEVICE(0x1011),
62 INTEL_E1000_ETHERNET_DEVICE(0x1012),
63 INTEL_E1000_ETHERNET_DEVICE(0x1013),
64 INTEL_E1000_ETHERNET_DEVICE(0x1014),
65 INTEL_E1000_ETHERNET_DEVICE(0x1015),
66 INTEL_E1000_ETHERNET_DEVICE(0x1016),
67 INTEL_E1000_ETHERNET_DEVICE(0x1017),
68 INTEL_E1000_ETHERNET_DEVICE(0x1018),
69 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 70 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 71 INTEL_E1000_ETHERNET_DEVICE(0x101D),
72 INTEL_E1000_ETHERNET_DEVICE(0x101E),
73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
76 INTEL_E1000_ETHERNET_DEVICE(0x1075),
77 INTEL_E1000_ETHERNET_DEVICE(0x1076),
78 INTEL_E1000_ETHERNET_DEVICE(0x1077),
79 INTEL_E1000_ETHERNET_DEVICE(0x1078),
80 INTEL_E1000_ETHERNET_DEVICE(0x1079),
81 INTEL_E1000_ETHERNET_DEVICE(0x107A),
82 INTEL_E1000_ETHERNET_DEVICE(0x107B),
83 INTEL_E1000_ETHERNET_DEVICE(0x107C),
84 INTEL_E1000_ETHERNET_DEVICE(0x108A),
b7ee49db 85 INTEL_E1000_ETHERNET_DEVICE(0x1099),
b7ee49db 86 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
1da177e4
LT		 87 /* required last entry */
88 {0,}
89};
90
91MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
92
35574764
NN		 93int e1000_up(struct e1000_adapter *adapter);
94void e1000_down(struct e1000_adapter *adapter);
95void e1000_reinit_locked(struct e1000_adapter *adapter);
96void e1000_reset(struct e1000_adapter *adapter);
97int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
98int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
99int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
100void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
101void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67 102static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
35574764 103 struct e1000_tx_ring *txdr);
3ad2cc67 104static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
35574764 105 struct e1000_rx_ring *rxdr);
3ad2cc67 106static void e1000_free_tx_resources(struct e1000_adapter *adapter,
35574764 107 struct e1000_tx_ring *tx_ring);
3ad2cc67 108static void e1000_free_rx_resources(struct e1000_adapter *adapter,
35574764
NN		 109 struct e1000_rx_ring *rx_ring);
110void e1000_update_stats(struct e1000_adapter *adapter);
1da177e4
LT		 111
112static int e1000_init_module(void);
113static void e1000_exit_module(void);
114static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
115static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 116static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 117static int e1000_sw_init(struct e1000_adapter *adapter);
118static int e1000_open(struct net_device *netdev);
119static int e1000_close(struct net_device *netdev);
120static void e1000_configure_tx(struct e1000_adapter *adapter);
121static void e1000_configure_rx(struct e1000_adapter *adapter);
122static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 123static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
124static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
125static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
126 struct e1000_tx_ring *tx_ring);
127static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
128 struct e1000_rx_ring *rx_ring);
db0ce50d 129static void e1000_set_rx_mode(struct net_device *netdev);
1da177e4
LT		 130static void e1000_update_phy_info(unsigned long data);
131static void e1000_watchdog(unsigned long data);
1da177e4
LT		 132static void e1000_82547_tx_fifo_stall(unsigned long data);
133static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
134static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
135static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
136static int e1000_set_mac(struct net_device *netdev, void *p);
7d12e780 137static irqreturn_t e1000_intr(int irq, void *data);
9ac98284 138static irqreturn_t e1000_intr_msi(int irq, void *data);
581d708e
MC		 139static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
140 struct e1000_tx_ring *tx_ring);
1da177e4 141#ifdef CONFIG_E1000_NAPI
bea3348e 142static int e1000_clean(struct napi_struct *napi, int budget);
1da177e4 143static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 144 struct e1000_rx_ring *rx_ring,
1da177e4 145 int *work_done, int work_to_do);
2d7edb92 146static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 147 struct e1000_rx_ring *rx_ring,
2d7edb92 148 int *work_done, int work_to_do);
1da177e4 149#else
581d708e
MC		 150static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
151 struct e1000_rx_ring *rx_ring);
152static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
153 struct e1000_rx_ring *rx_ring);
1da177e4 154#endif
581d708e 155static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 156 struct e1000_rx_ring *rx_ring,
157 int cleaned_count);
581d708e 158static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 159 struct e1000_rx_ring *rx_ring,
160 int cleaned_count);
1da177e4
LT		 161static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
162static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
163 int cmd);
1da177e4
LT		 164static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
165static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
166static void e1000_tx_timeout(struct net_device *dev);
65f27f38 167static void e1000_reset_task(struct work_struct *work);
1da177e4 168static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 169static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
170 struct sk_buff *skb);
1da177e4
LT		 171
172static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
173static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
174static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
175static void e1000_restore_vlan(struct e1000_adapter *adapter);
176
977e74b5 177static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 178#ifdef CONFIG_PM
1da177e4
LT		 179static int e1000_resume(struct pci_dev *pdev);
180#endif
c653e635 181static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 182
183#ifdef CONFIG_NET_POLL_CONTROLLER
184/* for netdump / net console */
185static void e1000_netpoll (struct net_device *netdev);
186#endif
187
1f753861
JB		 188#define COPYBREAK_DEFAULT 256
189static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT;
190module_param(copybreak, uint, 0644);
191MODULE_PARM_DESC(copybreak,
192 "Maximum size of packet that is copied to a new buffer on receive");
193
9026729b
AK		 194static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
195 pci_channel_state_t state);
196static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
197static void e1000_io_resume(struct pci_dev *pdev);
198
199static struct pci_error_handlers e1000_err_handler = {
200 .error_detected = e1000_io_error_detected,
201 .slot_reset = e1000_io_slot_reset,
202 .resume = e1000_io_resume,
203};
24025e4e 204
1da177e4
LT		 205static struct pci_driver e1000_driver = {
206 .name = e1000_driver_name,
207 .id_table = e1000_pci_tbl,
208 .probe = e1000_probe,
209 .remove = __devexit_p(e1000_remove),
c4e24f01 210#ifdef CONFIG_PM
1da177e4 211 /* Power Managment Hooks */
1da177e4 212 .suspend = e1000_suspend,
c653e635 213 .resume = e1000_resume,
1da177e4 214#endif
9026729b
AK		 215 .shutdown = e1000_shutdown,
216 .err_handler = &e1000_err_handler
1da177e4
LT		 217};
218
219MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
220MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
221MODULE_LICENSE("GPL");
222MODULE_VERSION(DRV_VERSION);
223
224static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
225module_param(debug, int, 0);
226MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
227
228/**
229 * e1000_init_module - Driver Registration Routine
230 *
231 * e1000_init_module is the first routine called when the driver is
232 * loaded. All it does is register with the PCI subsystem.
233 **/
234
235static int __init
236e1000_init_module(void)
237{
238 int ret;
239 printk(KERN_INFO "%s - version %s\n",
240 e1000_driver_string, e1000_driver_version);
241
242 printk(KERN_INFO "%s\n", e1000_copyright);
243
29917620 244 ret = pci_register_driver(&e1000_driver);
1f753861
JB		 245 if (copybreak != COPYBREAK_DEFAULT) {
246 if (copybreak == 0)
247 printk(KERN_INFO "e1000: copybreak disabled\n");
248 else
249 printk(KERN_INFO "e1000: copybreak enabled for "
250 "packets <= %u bytes\n", copybreak);
251 }
1da177e4
LT		 252 return ret;
253}
254
255module_init(e1000_init_module);
256
257/**
258 * e1000_exit_module - Driver Exit Cleanup Routine
259 *
260 * e1000_exit_module is called just before the driver is removed
261 * from memory.
262 **/
263
264static void __exit
265e1000_exit_module(void)
266{
1da177e4
LT		 267 pci_unregister_driver(&e1000_driver);
268}
269
270module_exit(e1000_exit_module);
271
2db10a08
AK		 272static int e1000_request_irq(struct e1000_adapter *adapter)
273{
274 struct net_device *netdev = adapter->netdev;
3e18826c 275 irq_handler_t handler = e1000_intr;
e94bd23f
AK		 276 int irq_flags = IRQF_SHARED;
277 int err;
2db10a08 278
9ac98284 279 if (adapter->hw.mac_type >= e1000_82571) {
e94bd23f
AK		 280 adapter->have_msi = !pci_enable_msi(adapter->pdev);
281 if (adapter->have_msi) {
3e18826c 282 handler = e1000_intr_msi;
e94bd23f 283 irq_flags = 0;
2db10a08
AK		 284 }
285 }
e94bd23f
AK		 286
287 err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name,
288 netdev);
289 if (err) {
290 if (adapter->have_msi)
291 pci_disable_msi(adapter->pdev);
2db10a08
AK		 292 DPRINTK(PROBE, ERR,
293 "Unable to allocate interrupt Error: %d\n", err);
e94bd23f 294 }
2db10a08
AK		 295
296 return err;
297}
298
299static void e1000_free_irq(struct e1000_adapter *adapter)
300{
301 struct net_device *netdev = adapter->netdev;
302
303 free_irq(adapter->pdev->irq, netdev);
304
2db10a08
AK		 305 if (adapter->have_msi)
306 pci_disable_msi(adapter->pdev);
2db10a08
AK		 307}
308
1da177e4
LT		 309/**
310 * e1000_irq_disable - Mask off interrupt generation on the NIC
311 * @adapter: board private structure
312 **/
313
e619d523 314static void
1da177e4
LT		 315e1000_irq_disable(struct e1000_adapter *adapter)
316{
317 atomic_inc(&adapter->irq_sem);
318 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
319 E1000_WRITE_FLUSH(&adapter->hw);
320 synchronize_irq(adapter->pdev->irq);
321}
322
323/**
324 * e1000_irq_enable - Enable default interrupt generation settings
325 * @adapter: board private structure
326 **/
327
e619d523 328static void
1da177e4
LT		 329e1000_irq_enable(struct e1000_adapter *adapter)
330{
96838a40 331 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 332 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
333 E1000_WRITE_FLUSH(&adapter->hw);
334 }
335}
3ad2cc67
AB		 336
337static void
2d7edb92
MC		 338e1000_update_mng_vlan(struct e1000_adapter *adapter)
339{
340 struct net_device *netdev = adapter->netdev;
341 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
342 uint16_t old_vid = adapter->mng_vlan_id;
96838a40 343 if (adapter->vlgrp) {
5c15bdec 344 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
96838a40 345 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 346 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
347 e1000_vlan_rx_add_vid(netdev, vid);
348 adapter->mng_vlan_id = vid;
349 } else
350 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 351
352 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
353 (vid != old_vid) &&
5c15bdec 354 !vlan_group_get_device(adapter->vlgrp, old_vid))
2d7edb92 355 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 356 } else
357 adapter->mng_vlan_id = vid;
2d7edb92
MC		 358 }
359}
b55ccb35
JK		 360
361/**
362 * e1000_release_hw_control - release control of the h/w to f/w
363 * @adapter: address of board private structure
364 *
365 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
366 * For ASF and Pass Through versions of f/w this means that the
367 * driver is no longer loaded. For AMT version (only with 82573) i
90fb5135 368 * of the f/w this means that the network i/f is closed.
76c224bc 369 *
b55ccb35
JK		 370 **/
371
e619d523 372static void
b55ccb35
JK		 373e1000_release_hw_control(struct e1000_adapter *adapter)
374{
375 uint32_t ctrl_ext;
376 uint32_t swsm;
377
378 /* Let firmware taken over control of h/w */
379 switch (adapter->hw.mac_type) {
b55ccb35
JK		 380 case e1000_82573:
381 swsm = E1000_READ_REG(&adapter->hw, SWSM);
382 E1000_WRITE_REG(&adapter->hw, SWSM,
383 swsm & ~E1000_SWSM_DRV_LOAD);
31d76442
BA		 384 break;
385 case e1000_82571:
386 case e1000_82572:
387 case e1000_80003es2lan:
cd94dd0b 388 case e1000_ich8lan:
31d76442 389 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
cd94dd0b 390 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
31d76442 391 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 392 break;
b55ccb35
JK		 393 default:
394 break;
395 }
396}
397
398/**
399 * e1000_get_hw_control - get control of the h/w from f/w
400 * @adapter: address of board private structure
401 *
402 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 403 * For ASF and Pass Through versions of f/w this means that
404 * the driver is loaded. For AMT version (only with 82573)
90fb5135 405 * of the f/w this means that the network i/f is open.
76c224bc 406 *
b55ccb35
JK		 407 **/
408
e619d523 409static void
b55ccb35
JK		 410e1000_get_hw_control(struct e1000_adapter *adapter)
411{
412 uint32_t ctrl_ext;
413 uint32_t swsm;
90fb5135 414
b55ccb35
JK		 415 /* Let firmware know the driver has taken over */
416 switch (adapter->hw.mac_type) {
b55ccb35
JK		 417 case e1000_82573:
418 swsm = E1000_READ_REG(&adapter->hw, SWSM);
419 E1000_WRITE_REG(&adapter->hw, SWSM,
420 swsm | E1000_SWSM_DRV_LOAD);
421 break;
31d76442
BA		 422 case e1000_82571:
423 case e1000_82572:
424 case e1000_80003es2lan:
cd94dd0b 425 case e1000_ich8lan:
31d76442
BA		 426 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
427 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
428 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 429 break;
b55ccb35
JK		 430 default:
431 break;
432 }
433}
434
0fccd0e9
JG		 435static void
436e1000_init_manageability(struct e1000_adapter *adapter)
437{
438 if (adapter->en_mng_pt) {
439 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
440
441 /* disable hardware interception of ARP */
442 manc &= ~(E1000_MANC_ARP_EN);
443
444 /* enable receiving management packets to the host */
445 /* this will probably generate destination unreachable messages
446 * from the host OS, but the packets will be handled on SMBUS */
447 if (adapter->hw.has_manc2h) {
448 uint32_t manc2h = E1000_READ_REG(&adapter->hw, MANC2H);
449
450 manc |= E1000_MANC_EN_MNG2HOST;
451#define E1000_MNG2HOST_PORT_623 (1 << 5)
452#define E1000_MNG2HOST_PORT_664 (1 << 6)
453 manc2h |= E1000_MNG2HOST_PORT_623;
454 manc2h |= E1000_MNG2HOST_PORT_664;
455 E1000_WRITE_REG(&adapter->hw, MANC2H, manc2h);
456 }
457
458 E1000_WRITE_REG(&adapter->hw, MANC, manc);
459 }
460}
461
462static void
463e1000_release_manageability(struct e1000_adapter *adapter)
464{
465 if (adapter->en_mng_pt) {
466 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
467
468 /* re-enable hardware interception of ARP */
469 manc |= E1000_MANC_ARP_EN;
470
471 if (adapter->hw.has_manc2h)
472 manc &= ~E1000_MANC_EN_MNG2HOST;
473
474 /* don't explicitly have to mess with MANC2H since
475 * MANC has an enable disable that gates MANC2H */
476
477 E1000_WRITE_REG(&adapter->hw, MANC, manc);
478 }
479}
480
e0aac5a2
AK		 481/**
482 * e1000_configure - configure the hardware for RX and TX
483 * @adapter = private board structure
484 **/
485static void e1000_configure(struct e1000_adapter *adapter)
1da177e4
LT		 486{
487 struct net_device *netdev = adapter->netdev;
2db10a08 488 int i;
1da177e4 489
db0ce50d 490 e1000_set_rx_mode(netdev);
1da177e4
LT		 491
492 e1000_restore_vlan(adapter);
0fccd0e9 493 e1000_init_manageability(adapter);
1da177e4
LT		 494
495 e1000_configure_tx(adapter);
496 e1000_setup_rctl(adapter);
497 e1000_configure_rx(adapter);
72d64a43
JK		 498 /* call E1000_DESC_UNUSED which always leaves
499 * at least 1 descriptor unused to make sure
500 * next_to_use != next_to_clean */
f56799ea 501 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 502 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 503 adapter->alloc_rx_buf(adapter, ring,
504 E1000_DESC_UNUSED(ring));
f56799ea 505 }
1da177e4 506
7bfa4816 507 adapter->tx_queue_len = netdev->tx_queue_len;
e0aac5a2
AK		 508}
509
510int e1000_up(struct e1000_adapter *adapter)
511{
512 /* hardware has been reset, we need to reload some things */
513 e1000_configure(adapter);
514
515 clear_bit(__E1000_DOWN, &adapter->flags);
7bfa4816 516
1da177e4 517#ifdef CONFIG_E1000_NAPI
bea3348e 518 napi_enable(&adapter->napi);
1da177e4 519#endif
5de55624
MC		 520 e1000_irq_enable(adapter);
521
79f3d399
JB		 522 /* fire a link change interrupt to start the watchdog */
523 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1da177e4
LT		 524 return 0;
525}
526
79f05bf0
AK		 527/**
528 * e1000_power_up_phy - restore link in case the phy was powered down
529 * @adapter: address of board private structure
530 *
531 * The phy may be powered down to save power and turn off link when the
532 * driver is unloaded and wake on lan is not enabled (among others)
533 * *** this routine MUST be followed by a call to e1000_reset ***
534 *
535 **/
536
d658266e 537void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0
AK		 538{
539 uint16_t mii_reg = 0;
540
541 /* Just clear the power down bit to wake the phy back up */
542 if (adapter->hw.media_type == e1000_media_type_copper) {
543 /* according to the manual, the phy will retain its
544 * settings across a power-down/up cycle */
545 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
546 mii_reg &= ~MII_CR_POWER_DOWN;
547 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
548 }
549}
550
551static void e1000_power_down_phy(struct e1000_adapter *adapter)
552{
61c2505f
BA		 553 /* Power down the PHY so no link is implied when interface is down *
554 * The PHY cannot be powered down if any of the following is TRUE *
79f05bf0
AK		 555 * (a) WoL is enabled
556 * (b) AMT is active
557 * (c) SoL/IDER session is active */
558 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
61c2505f 559 adapter->hw.media_type == e1000_media_type_copper) {
79f05bf0 560 uint16_t mii_reg = 0;
61c2505f
BA		 561
562 switch (adapter->hw.mac_type) {
563 case e1000_82540:
564 case e1000_82545:
565 case e1000_82545_rev_3:
566 case e1000_82546:
567 case e1000_82546_rev_3:
568 case e1000_82541:
569 case e1000_82541_rev_2:
570 case e1000_82547:
571 case e1000_82547_rev_2:
572 if (E1000_READ_REG(&adapter->hw, MANC) &
573 E1000_MANC_SMBUS_EN)
574 goto out;
575 break;
576 case e1000_82571:
577 case e1000_82572:
578 case e1000_82573:
579 case e1000_80003es2lan:
580 case e1000_ich8lan:
581 if (e1000_check_mng_mode(&adapter->hw) ||
582 e1000_check_phy_reset_block(&adapter->hw))
583 goto out;
584 break;
585 default:
586 goto out;
587 }
79f05bf0
AK		 588 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
589 mii_reg |= MII_CR_POWER_DOWN;
590 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
591 mdelay(1);
592 }
61c2505f
BA		 593out:
594 return;
79f05bf0
AK		 595}
596
1da177e4
LT		 597void
598e1000_down(struct e1000_adapter *adapter)
599{
600 struct net_device *netdev = adapter->netdev;
601
1314bbf3
AK		 602 /* signal that we're down so the interrupt handler does not
603 * reschedule our watchdog timer */
604 set_bit(__E1000_DOWN, &adapter->flags);
605
e0aac5a2 606#ifdef CONFIG_E1000_NAPI
bea3348e 607 napi_disable(&adapter->napi);
49d85c50 608 atomic_set(&adapter->irq_sem, 0);
e0aac5a2 609#endif
1da177e4 610 e1000_irq_disable(adapter);
c1605eb3 611
1da177e4
LT		 612 del_timer_sync(&adapter->tx_fifo_stall_timer);
613 del_timer_sync(&adapter->watchdog_timer);
614 del_timer_sync(&adapter->phy_info_timer);
615
7bfa4816 616 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 617 adapter->link_speed = 0;
618 adapter->link_duplex = 0;
619 netif_carrier_off(netdev);
620 netif_stop_queue(netdev);
621
622 e1000_reset(adapter);
581d708e
MC		 623 e1000_clean_all_tx_rings(adapter);
624 e1000_clean_all_rx_rings(adapter);
1da177e4 625}
1da177e4 626
2db10a08
AK		 627void
628e1000_reinit_locked(struct e1000_adapter *adapter)
629{
630 WARN_ON(in_interrupt());
631 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
632 msleep(1);
633 e1000_down(adapter);
634 e1000_up(adapter);
635 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 636}
637
638void
639e1000_reset(struct e1000_adapter *adapter)
640{
018ea44e 641 uint32_t pba = 0, tx_space, min_tx_space, min_rx_space;
1125ecbc 642 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
018ea44e 643 boolean_t legacy_pba_adjust = FALSE;
1da177e4
LT		 644
645 /* Repartition Pba for greater than 9k mtu
646 * To take effect CTRL.RST is required.
647 */
648
2d7edb92 649 switch (adapter->hw.mac_type) {
018ea44e
BA		 650 case e1000_82542_rev2_0:
651 case e1000_82542_rev2_1:
652 case e1000_82543:
653 case e1000_82544:
654 case e1000_82540:
655 case e1000_82541:
656 case e1000_82541_rev_2:
657 legacy_pba_adjust = TRUE;
658 pba = E1000_PBA_48K;
659 break;
660 case e1000_82545:
661 case e1000_82545_rev_3:
662 case e1000_82546:
663 case e1000_82546_rev_3:
664 pba = E1000_PBA_48K;
665 break;
2d7edb92 666 case e1000_82547:
0e6ef3e0 667 case e1000_82547_rev_2:
018ea44e 668 legacy_pba_adjust = TRUE;
2d7edb92
MC		 669 pba = E1000_PBA_30K;
670 break;
868d5309
MC		 671 case e1000_82571:
672 case e1000_82572:
6418ecc6 673 case e1000_80003es2lan:
868d5309
MC		 674 pba = E1000_PBA_38K;
675 break;
2d7edb92 676 case e1000_82573:
018ea44e 677 pba = E1000_PBA_20K;
2d7edb92 678 break;
cd94dd0b
AK		 679 case e1000_ich8lan:
680 pba = E1000_PBA_8K;
018ea44e
BA		 681 case e1000_undefined:
682 case e1000_num_macs:
2d7edb92
MC		 683 break;
684 }
685
018ea44e
BA		 686 if (legacy_pba_adjust == TRUE) {
687 if (adapter->netdev->mtu > E1000_RXBUFFER_8192)
688 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92 689
018ea44e
BA		 690 if (adapter->hw.mac_type == e1000_82547) {
691 adapter->tx_fifo_head = 0;
692 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
693 adapter->tx_fifo_size =
694 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
695 atomic_set(&adapter->tx_fifo_stall, 0);
696 }
697 } else if (adapter->hw.max_frame_size > MAXIMUM_ETHERNET_FRAME_SIZE) {
698 /* adjust PBA for jumbo frames */
699 E1000_WRITE_REG(&adapter->hw, PBA, pba);
700
701 /* To maintain wire speed transmits, the Tx FIFO should be
702 * large enough to accomodate two full transmit packets,
703 * rounded up to the next 1KB and expressed in KB. Likewise,
704 * the Rx FIFO should be large enough to accomodate at least
705 * one full receive packet and is similarly rounded up and
706 * expressed in KB. */
707 pba = E1000_READ_REG(&adapter->hw, PBA);
708 /* upper 16 bits has Tx packet buffer allocation size in KB */
709 tx_space = pba >> 16;
710 /* lower 16 bits has Rx packet buffer allocation size in KB */
711 pba &= 0xffff;
712 /* don't include ethernet FCS because hardware appends/strips */
713 min_rx_space = adapter->netdev->mtu + ENET_HEADER_SIZE +
714 VLAN_TAG_SIZE;
715 min_tx_space = min_rx_space;
716 min_tx_space *= 2;
9099cfb9 717 min_tx_space = ALIGN(min_tx_space, 1024);
018ea44e 718 min_tx_space >>= 10;
9099cfb9 719 min_rx_space = ALIGN(min_rx_space, 1024);
018ea44e
BA		 720 min_rx_space >>= 10;
721
722 /* If current Tx allocation is less than the min Tx FIFO size,
723 * and the min Tx FIFO size is less than the current Rx FIFO
724 * allocation, take space away from current Rx allocation */
725 if (tx_space < min_tx_space &&
726 ((min_tx_space - tx_space) < pba)) {
727 pba = pba - (min_tx_space - tx_space);
728
729 /* PCI/PCIx hardware has PBA alignment constraints */
730 switch (adapter->hw.mac_type) {
731 case e1000_82545 ... e1000_82546_rev_3:
732 pba &= ~(E1000_PBA_8K - 1);
733 break;
734 default:
735 break;
736 }
737
738 /* if short on rx space, rx wins and must trump tx
739 * adjustment or use Early Receive if available */
740 if (pba < min_rx_space) {
741 switch (adapter->hw.mac_type) {
742 case e1000_82573:
743 /* ERT enabled in e1000_configure_rx */
744 break;
745 default:
746 pba = min_rx_space;
747 break;
748 }
749 }
750 }
1da177e4 751 }
2d7edb92 752
1da177e4
LT		 753 E1000_WRITE_REG(&adapter->hw, PBA, pba);
754
755 /* flow control settings */
f11b7f85
JK		 756 /* Set the FC high water mark to 90% of the FIFO size.
757 * Required to clear last 3 LSB */
758 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 759 /* We can't use 90% on small FIFOs because the remainder
760 * would be less than 1 full frame. In this case, we size
761 * it to allow at least a full frame above the high water
762 * mark. */
763 if (pba < E1000_PBA_16K)
764 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 765
766 adapter->hw.fc_high_water = fc_high_water_mark;
767 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 768 if (adapter->hw.mac_type == e1000_80003es2lan)
769 adapter->hw.fc_pause_time = 0xFFFF;
770 else
771 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 772 adapter->hw.fc_send_xon = 1;
773 adapter->hw.fc = adapter->hw.original_fc;
774
2d7edb92 775 /* Allow time for pending master requests to run */
1da177e4 776 e1000_reset_hw(&adapter->hw);
96838a40 777 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 778 E1000_WRITE_REG(&adapter->hw, WUC, 0);
09ae3e88 779
96838a40 780 if (e1000_init_hw(&adapter->hw))
1da177e4 781 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 782 e1000_update_mng_vlan(adapter);
3d5460a0
JB		 783
784 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
785 if (adapter->hw.mac_type >= e1000_82544 &&
786 adapter->hw.mac_type <= e1000_82547_rev_2 &&
787 adapter->hw.autoneg == 1 &&
788 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
789 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL);
790 /* clear phy power management bit if we are in gig only mode,
791 * which if enabled will attempt negotiation to 100Mb, which
792 * can cause a loss of link at power off or driver unload */
793 ctrl &= ~E1000_CTRL_SWDPIN3;
794 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
795 }
796
1da177e4
LT		 797 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
798 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
799
800 e1000_reset_adaptive(&adapter->hw);
801 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 802
803 if (!adapter->smart_power_down &&
804 (adapter->hw.mac_type == e1000_82571 ||
805 adapter->hw.mac_type == e1000_82572)) {
806 uint16_t phy_data = 0;
807 /* speed up time to link by disabling smart power down, ignore
808 * the return value of this function because there is nothing
809 * different we would do if it failed */
810 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
811 &phy_data);
812 phy_data &= ~IGP02E1000_PM_SPD;
813 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
814 phy_data);
815 }
816
0fccd0e9 817 e1000_release_manageability(adapter);
1da177e4
LT		 818}
819
820/**
821 * e1000_probe - Device Initialization Routine
822 * @pdev: PCI device information struct
823 * @ent: entry in e1000_pci_tbl
824 *
825 * Returns 0 on success, negative on failure
826 *
827 * e1000_probe initializes an adapter identified by a pci_dev structure.
828 * The OS initialization, configuring of the adapter private structure,
829 * and a hardware reset occur.
830 **/
831
832static int __devinit
833e1000_probe(struct pci_dev *pdev,
834 const struct pci_device_id *ent)
835{
836 struct net_device *netdev;
837 struct e1000_adapter *adapter;
2d7edb92 838 unsigned long mmio_start, mmio_len;
cd94dd0b 839 unsigned long flash_start, flash_len;
2d7edb92 840
1da177e4 841 static int cards_found = 0;
120cd576 842 static int global_quad_port_a = 0; /* global ksp3 port a indication */
2d7edb92 843 int i, err, pci_using_dac;
120cd576 844 uint16_t eeprom_data = 0;
1da177e4 845 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
0795af57
JP		 846 DECLARE_MAC_BUF(mac);
847
96838a40 848 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 849 return err;
850
cd94dd0b
AK		 851 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
852 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 853 pci_using_dac = 1;
854 } else {
cd94dd0b
AK		 855 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
856 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4 857 E1000_ERR("No usable DMA configuration, aborting\n");
6dd62ab0 858 goto err_dma;
1da177e4
LT		 859 }
860 pci_using_dac = 0;
861 }
862
96838a40 863 if ((err = pci_request_regions(pdev, e1000_driver_name)))
6dd62ab0 864 goto err_pci_reg;
1da177e4
LT		 865
866 pci_set_master(pdev);
867
6dd62ab0 868 err = -ENOMEM;
1da177e4 869 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6dd62ab0 870 if (!netdev)
1da177e4 871 goto err_alloc_etherdev;
1da177e4 872
1da177e4
LT		 873 SET_NETDEV_DEV(netdev, &pdev->dev);
874
875 pci_set_drvdata(pdev, netdev);
60490fe0 876 adapter = netdev_priv(netdev);
1da177e4
LT		 877 adapter->netdev = netdev;
878 adapter->pdev = pdev;
879 adapter->hw.back = adapter;
880 adapter->msg_enable = (1 << debug) - 1;
881
882 mmio_start = pci_resource_start(pdev, BAR_0);
883 mmio_len = pci_resource_len(pdev, BAR_0);
884
6dd62ab0 885 err = -EIO;
1da177e4 886 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6dd62ab0 887 if (!adapter->hw.hw_addr)
1da177e4 888 goto err_ioremap;
1da177e4 889
96838a40
JB		 890 for (i = BAR_1; i <= BAR_5; i++) {
891 if (pci_resource_len(pdev, i) == 0)
1da177e4 892 continue;
96838a40 893 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 894 adapter->hw.io_base = pci_resource_start(pdev, i);
895 break;
896 }
897 }
898
899 netdev->open = &e1000_open;
900 netdev->stop = &e1000_close;
901 netdev->hard_start_xmit = &e1000_xmit_frame;
902 netdev->get_stats = &e1000_get_stats;
db0ce50d 903 netdev->set_rx_mode = &e1000_set_rx_mode;
1da177e4
LT		 904 netdev->set_mac_address = &e1000_set_mac;
905 netdev->change_mtu = &e1000_change_mtu;
906 netdev->do_ioctl = &e1000_ioctl;
907 e1000_set_ethtool_ops(netdev);
908 netdev->tx_timeout = &e1000_tx_timeout;
909 netdev->watchdog_timeo = 5 * HZ;
910#ifdef CONFIG_E1000_NAPI
bea3348e 911 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
1da177e4
LT		 912#endif
913 netdev->vlan_rx_register = e1000_vlan_rx_register;
914 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
915 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
916#ifdef CONFIG_NET_POLL_CONTROLLER
917 netdev->poll_controller = e1000_netpoll;
918#endif
0eb5a34c 919 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4
LT		 920
921 netdev->mem_start = mmio_start;
922 netdev->mem_end = mmio_start + mmio_len;
923 netdev->base_addr = adapter->hw.io_base;
924
925 adapter->bd_number = cards_found;
926
927 /* setup the private structure */
928
96838a40 929 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 930 goto err_sw_init;
931
6dd62ab0 932 err = -EIO;
cd94dd0b
AK		 933 /* Flash BAR mapping must happen after e1000_sw_init
934 * because it depends on mac_type */
935 if ((adapter->hw.mac_type == e1000_ich8lan) &&
936 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
937 flash_start = pci_resource_start(pdev, 1);
938 flash_len = pci_resource_len(pdev, 1);
939 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6dd62ab0 940 if (!adapter->hw.flash_address)
cd94dd0b 941 goto err_flashmap;
cd94dd0b
AK		 942 }
943
6dd62ab0 944 if (e1000_check_phy_reset_block(&adapter->hw))
2d7edb92
MC		 945 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
946
96838a40 947 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 948 netdev->features = NETIF_F_SG |
949 NETIF_F_HW_CSUM |
950 NETIF_F_HW_VLAN_TX |
951 NETIF_F_HW_VLAN_RX |
952 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 953 if (adapter->hw.mac_type == e1000_ich8lan)
954 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 955 }
956
96838a40 957 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 958 (adapter->hw.mac_type != e1000_82547))
959 netdev->features |= NETIF_F_TSO;
2d7edb92 960
96838a40 961 if (adapter->hw.mac_type > e1000_82547_rev_2)
87ca4e5b 962 netdev->features |= NETIF_F_TSO6;
96838a40 963 if (pci_using_dac)
1da177e4
LT		 964 netdev->features |= NETIF_F_HIGHDMA;
965
76c224bc
AK		 966 netdev->features |= NETIF_F_LLTX;
967
2d7edb92
MC		 968 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
969
cd94dd0b
AK		 970 /* initialize eeprom parameters */
971
972 if (e1000_init_eeprom_params(&adapter->hw)) {
973 E1000_ERR("EEPROM initialization failed\n");
6dd62ab0 974 goto err_eeprom;
cd94dd0b
AK		 975 }
976
96838a40 977 /* before reading the EEPROM, reset the controller to
1da177e4 978 * put the device in a known good starting state */
96838a40 979
1da177e4
LT		 980 e1000_reset_hw(&adapter->hw);
981
982 /* make sure the EEPROM is good */
983
96838a40 984 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4 985 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
1da177e4
LT		 986 goto err_eeprom;
987 }
988
989 /* copy the MAC address out of the EEPROM */
990
96838a40 991 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 992 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
993 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 994 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 995
96838a40 996 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4 997 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
1da177e4
LT		 998 goto err_eeprom;
999 }
1000
1da177e4
LT		 1001 e1000_get_bus_info(&adapter->hw);
1002
1003 init_timer(&adapter->tx_fifo_stall_timer);
1004 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
1005 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
1006
1007 init_timer(&adapter->watchdog_timer);
1008 adapter->watchdog_timer.function = &e1000_watchdog;
1009 adapter->watchdog_timer.data = (unsigned long) adapter;
1010
1da177e4
LT		 1011 init_timer(&adapter->phy_info_timer);
1012 adapter->phy_info_timer.function = &e1000_update_phy_info;
1013 adapter->phy_info_timer.data = (unsigned long) adapter;
1014
65f27f38 1015 INIT_WORK(&adapter->reset_task, e1000_reset_task);
1da177e4 1016
1da177e4
LT		 1017 e1000_check_options(adapter);
1018
1019 /* Initial Wake on LAN setting
1020 * If APM wake is enabled in the EEPROM,
1021 * enable the ACPI Magic Packet filter
1022 */
1023
96838a40 1024 switch (adapter->hw.mac_type) {
1da177e4
LT		 1025 case e1000_82542_rev2_0:
1026 case e1000_82542_rev2_1:
1027 case e1000_82543:
1028 break;
1029 case e1000_82544:
1030 e1000_read_eeprom(&adapter->hw,
1031 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1032 eeprom_apme_mask = E1000_EEPROM_82544_APM;
1033 break;
cd94dd0b
AK		 1034 case e1000_ich8lan:
1035 e1000_read_eeprom(&adapter->hw,
1036 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
1037 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
1038 break;
1da177e4
LT		 1039 case e1000_82546:
1040 case e1000_82546_rev_3:
fd803241 1041 case e1000_82571:
6418ecc6 1042 case e1000_80003es2lan:
96838a40 1043 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 1044 e1000_read_eeprom(&adapter->hw,
1045 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1046 break;
1047 }
1048 /* Fall Through */
1049 default:
1050 e1000_read_eeprom(&adapter->hw,
1051 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1052 break;
1053 }
96838a40 1054 if (eeprom_data & eeprom_apme_mask)
120cd576
JB		 1055 adapter->eeprom_wol |= E1000_WUFC_MAG;
1056
1057 /* now that we have the eeprom settings, apply the special cases
1058 * where the eeprom may be wrong or the board simply won't support
1059 * wake on lan on a particular port */
1060 switch (pdev->device) {
1061 case E1000_DEV_ID_82546GB_PCIE:
1062 adapter->eeprom_wol = 0;
1063 break;
1064 case E1000_DEV_ID_82546EB_FIBER:
1065 case E1000_DEV_ID_82546GB_FIBER:
1066 case E1000_DEV_ID_82571EB_FIBER:
1067 /* Wake events only supported on port A for dual fiber
1068 * regardless of eeprom setting */
1069 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
1070 adapter->eeprom_wol = 0;
1071 break;
1072 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
5881cde8 1073 case E1000_DEV_ID_82571EB_QUAD_COPPER:
ce57a02c 1074 case E1000_DEV_ID_82571EB_QUAD_FIBER:
fc2307d0 1075 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
f4ec7f98 1076 case E1000_DEV_ID_82571PT_QUAD_COPPER:
120cd576
JB		 1077 /* if quad port adapter, disable WoL on all but port A */
1078 if (global_quad_port_a != 0)
1079 adapter->eeprom_wol = 0;
1080 else
1081 adapter->quad_port_a = 1;
1082 /* Reset for multiple quad port adapters */
1083 if (++global_quad_port_a == 4)
1084 global_quad_port_a = 0;
1085 break;
1086 }
1087
1088 /* initialize the wol settings based on the eeprom settings */
1089 adapter->wol = adapter->eeprom_wol;
1da177e4 1090
fb3d47d4
JK		 1091 /* print bus type/speed/width info */
1092 {
1093 struct e1000_hw *hw = &adapter->hw;
1094 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
1095 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
1096 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
1097 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1098 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
1099 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
1100 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
1101 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
1102 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
1103 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
1104 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
1105 "32-bit"));
1106 }
1107
0795af57 1108 printk("%s\n", print_mac(mac, netdev->dev_addr));
fb3d47d4 1109
1da177e4
LT		 1110 /* reset the hardware with the new settings */
1111 e1000_reset(adapter);
1112
b55ccb35
JK		 1113 /* If the controller is 82573 and f/w is AMT, do not set
1114 * DRV_LOAD until the interface is up. For all other cases,
1115 * let the f/w know that the h/w is now under the control
1116 * of the driver. */
1117 if (adapter->hw.mac_type != e1000_82573 ||
1118 !e1000_check_mng_mode(&adapter->hw))
1119 e1000_get_hw_control(adapter);
2d7edb92 1120
1314bbf3
AK		 1121 /* tell the stack to leave us alone until e1000_open() is called */
1122 netif_carrier_off(netdev);
1123 netif_stop_queue(netdev);
416b5d10
AK		 1124
1125 strcpy(netdev->name, "eth%d");
1126 if ((err = register_netdev(netdev)))
1127 goto err_register;
1314bbf3 1128
1da177e4
LT		 1129 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
1130
1131 cards_found++;
1132 return 0;
1133
1134err_register:
6dd62ab0
VA		 1135 e1000_release_hw_control(adapter);
1136err_eeprom:
1137 if (!e1000_check_phy_reset_block(&adapter->hw))
1138 e1000_phy_hw_reset(&adapter->hw);
1139
cd94dd0b
AK		 1140 if (adapter->hw.flash_address)
1141 iounmap(adapter->hw.flash_address);
1142err_flashmap:
6dd62ab0
VA		 1143#ifdef CONFIG_E1000_NAPI
1144 for (i = 0; i < adapter->num_rx_queues; i++)
1145 dev_put(&adapter->polling_netdev[i]);
1146#endif
1147
1148 kfree(adapter->tx_ring);
1149 kfree(adapter->rx_ring);
1150#ifdef CONFIG_E1000_NAPI
1151 kfree(adapter->polling_netdev);
1152#endif
1da177e4 1153err_sw_init:
1da177e4
LT		 1154 iounmap(adapter->hw.hw_addr);
1155err_ioremap:
1156 free_netdev(netdev);
1157err_alloc_etherdev:
1158 pci_release_regions(pdev);
6dd62ab0
VA		 1159err_pci_reg:
1160err_dma:
1161 pci_disable_device(pdev);
1da177e4
LT		 1162 return err;
1163}
1164
1165/**
1166 * e1000_remove - Device Removal Routine
1167 * @pdev: PCI device information struct
1168 *
1169 * e1000_remove is called by the PCI subsystem to alert the driver
1170 * that it should release a PCI device. The could be caused by a
1171 * Hot-Plug event, or because the driver is going to be removed from
1172 * memory.
1173 **/
1174
1175static void __devexit
1176e1000_remove(struct pci_dev *pdev)
1177{
1178 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 1179 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e
MC		 1180#ifdef CONFIG_E1000_NAPI
1181 int i;
1182#endif
1da177e4 1183
28e53bdd 1184 cancel_work_sync(&adapter->reset_task);
be2b28ed 1185
0fccd0e9 1186 e1000_release_manageability(adapter);
1da177e4 1187
b55ccb35
JK		 1188 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1189 * would have already happened in close and is redundant. */
1190 e1000_release_hw_control(adapter);
2d7edb92 1191
581d708e 1192#ifdef CONFIG_E1000_NAPI
f56799ea 1193 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1194 dev_put(&adapter->polling_netdev[i]);
581d708e 1195#endif
1da177e4 1196
bea3348e
SH		 1197 unregister_netdev(netdev);
1198
96838a40 1199 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1200 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1201
24025e4e
MC		 1202 kfree(adapter->tx_ring);
1203 kfree(adapter->rx_ring);
1204#ifdef CONFIG_E1000_NAPI
1205 kfree(adapter->polling_netdev);
1206#endif
1207
1da177e4 1208 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1209 if (adapter->hw.flash_address)
1210 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1211 pci_release_regions(pdev);
1212
1213 free_netdev(netdev);
1214
1215 pci_disable_device(pdev);
1216}
1217
1218/**
1219 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1220 * @adapter: board private structure to initialize
1221 *
1222 * e1000_sw_init initializes the Adapter private data structure.
1223 * Fields are initialized based on PCI device information and
1224 * OS network device settings (MTU size).
1225 **/
1226
1227static int __devinit
1228e1000_sw_init(struct e1000_adapter *adapter)
1229{
1230 struct e1000_hw *hw = &adapter->hw;
1231 struct net_device *netdev = adapter->netdev;
1232 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1233#ifdef CONFIG_E1000_NAPI
1234 int i;
1235#endif
1da177e4
LT		 1236
1237 /* PCI config space info */
1238
1239 hw->vendor_id = pdev->vendor;
1240 hw->device_id = pdev->device;
1241 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1242 hw->subsystem_id = pdev->subsystem_device;
44c10138 1243 hw->revision_id = pdev->revision;
1da177e4
LT		 1244
1245 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1246
eb0f8054 1247 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1248 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1249 hw->max_frame_size = netdev->mtu +
1250 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1251 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1252
1253 /* identify the MAC */
1254
96838a40 1255 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1256 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1257 return -EIO;
1258 }
1259
96838a40 1260 switch (hw->mac_type) {
1da177e4
LT		 1261 default:
1262 break;
1263 case e1000_82541:
1264 case e1000_82547:
1265 case e1000_82541_rev_2:
1266 case e1000_82547_rev_2:
1267 hw->phy_init_script = 1;
1268 break;
1269 }
1270
1271 e1000_set_media_type(hw);
1272
1273 hw->wait_autoneg_complete = FALSE;
1274 hw->tbi_compatibility_en = TRUE;
1275 hw->adaptive_ifs = TRUE;
1276
1277 /* Copper options */
1278
96838a40 1279 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1280 hw->mdix = AUTO_ALL_MODES;
1281 hw->disable_polarity_correction = FALSE;
1282 hw->master_slave = E1000_MASTER_SLAVE;
1283 }
1284
f56799ea
JK		 1285 adapter->num_tx_queues = 1;
1286 adapter->num_rx_queues = 1;
581d708e
MC		 1287
1288 if (e1000_alloc_queues(adapter)) {
1289 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1290 return -ENOMEM;
1291 }
1292
1293#ifdef CONFIG_E1000_NAPI
f56799ea 1294 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e 1295 adapter->polling_netdev[i].priv = adapter;
581d708e
MC		 1296 dev_hold(&adapter->polling_netdev[i]);
1297 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1298 }
7bfa4816 1299 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1300#endif
1301
47313054
HX		 1302 /* Explicitly disable IRQ since the NIC can be in any state. */
1303 atomic_set(&adapter->irq_sem, 0);
1304 e1000_irq_disable(adapter);
1305
1da177e4 1306 spin_lock_init(&adapter->stats_lock);
1da177e4 1307
1314bbf3
AK		 1308 set_bit(__E1000_DOWN, &adapter->flags);
1309
1da177e4
LT		 1310 return 0;
1311}
1312
581d708e
MC		 1313/**
1314 * e1000_alloc_queues - Allocate memory for all rings
1315 * @adapter: board private structure to initialize
1316 *
1317 * We allocate one ring per queue at run-time since we don't know the
1318 * number of queues at compile-time. The polling_netdev array is
1319 * intended for Multiqueue, but should work fine with a single queue.
1320 **/
1321
1322static int __devinit
1323e1000_alloc_queues(struct e1000_adapter *adapter)
1324{
1c7e5b12
YB		 1325 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1326 sizeof(struct e1000_tx_ring), GFP_KERNEL);
581d708e
MC		 1327 if (!adapter->tx_ring)
1328 return -ENOMEM;
581d708e 1329
1c7e5b12
YB		 1330 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1331 sizeof(struct e1000_rx_ring), GFP_KERNEL);
581d708e
MC		 1332 if (!adapter->rx_ring) {
1333 kfree(adapter->tx_ring);
1334 return -ENOMEM;
1335 }
581d708e
MC		 1336
1337#ifdef CONFIG_E1000_NAPI
1c7e5b12
YB		 1338 adapter->polling_netdev = kcalloc(adapter->num_rx_queues,
1339 sizeof(struct net_device),
1340 GFP_KERNEL);
581d708e
MC		 1341 if (!adapter->polling_netdev) {
1342 kfree(adapter->tx_ring);
1343 kfree(adapter->rx_ring);
1344 return -ENOMEM;
1345 }
581d708e
MC		 1346#endif
1347
1348 return E1000_SUCCESS;
1349}
1350
1da177e4
LT		 1351/**
1352 * e1000_open - Called when a network interface is made active
1353 * @netdev: network interface device structure
1354 *
1355 * Returns 0 on success, negative value on failure
1356 *
1357 * The open entry point is called when a network interface is made
1358 * active by the system (IFF_UP). At this point all resources needed
1359 * for transmit and receive operations are allocated, the interrupt
1360 * handler is registered with the OS, the watchdog timer is started,
1361 * and the stack is notified that the interface is ready.
1362 **/
1363
1364static int
1365e1000_open(struct net_device *netdev)
1366{
60490fe0 1367 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1368 int err;
1369
2db10a08 1370 /* disallow open during test */
1314bbf3 1371 if (test_bit(__E1000_TESTING, &adapter->flags))
2db10a08
AK		 1372 return -EBUSY;
1373
1da177e4 1374 /* allocate transmit descriptors */
e0aac5a2
AK		 1375 err = e1000_setup_all_tx_resources(adapter);
1376 if (err)
1da177e4
LT		 1377 goto err_setup_tx;
1378
1379 /* allocate receive descriptors */
e0aac5a2 1380 err = e1000_setup_all_rx_resources(adapter);
b5bf28cd 1381 if (err)
e0aac5a2 1382 goto err_setup_rx;
b5bf28cd 1383
79f05bf0
AK		 1384 e1000_power_up_phy(adapter);
1385
2d7edb92 1386 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1387 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1388 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1389 e1000_update_mng_vlan(adapter);
1390 }
1da177e4 1391
b55ccb35
JK		 1392 /* If AMT is enabled, let the firmware know that the network
1393 * interface is now open */
1394 if (adapter->hw.mac_type == e1000_82573 &&
1395 e1000_check_mng_mode(&adapter->hw))
1396 e1000_get_hw_control(adapter);
1397
e0aac5a2
AK		 1398 /* before we allocate an interrupt, we must be ready to handle it.
1399 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1400 * as soon as we call pci_request_irq, so we have to setup our
1401 * clean_rx handler before we do so. */
1402 e1000_configure(adapter);
1403
1404 err = e1000_request_irq(adapter);
1405 if (err)
1406 goto err_req_irq;
1407
1408 /* From here on the code is the same as e1000_up() */
1409 clear_bit(__E1000_DOWN, &adapter->flags);
1410
47313054 1411#ifdef CONFIG_E1000_NAPI
bea3348e 1412 napi_enable(&adapter->napi);
47313054
HX		 1413#endif
1414
e0aac5a2
AK		 1415 e1000_irq_enable(adapter);
1416
1417 /* fire a link status change interrupt to start the watchdog */
1418 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1419
1da177e4
LT		 1420 return E1000_SUCCESS;
1421
b5bf28cd 1422err_req_irq:
e0aac5a2
AK		 1423 e1000_release_hw_control(adapter);
1424 e1000_power_down_phy(adapter);
581d708e 1425 e1000_free_all_rx_resources(adapter);
1da177e4 1426err_setup_rx:
581d708e 1427 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1428err_setup_tx:
1429 e1000_reset(adapter);
1430
1431 return err;
1432}
1433
1434/**
1435 * e1000_close - Disables a network interface
1436 * @netdev: network interface device structure
1437 *
1438 * Returns 0, this is not allowed to fail
1439 *
1440 * The close entry point is called when an interface is de-activated
1441 * by the OS. The hardware is still under the drivers control, but
1442 * needs to be disabled. A global MAC reset is issued to stop the
1443 * hardware, and all transmit and receive resources are freed.
1444 **/
1445
1446static int
1447e1000_close(struct net_device *netdev)
1448{
60490fe0 1449 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1450
2db10a08 1451 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1452 e1000_down(adapter);
79f05bf0 1453 e1000_power_down_phy(adapter);
2db10a08 1454 e1000_free_irq(adapter);
1da177e4 1455
581d708e
MC		 1456 e1000_free_all_tx_resources(adapter);
1457 e1000_free_all_rx_resources(adapter);
1da177e4 1458
4666560a
BA		 1459 /* kill manageability vlan ID if supported, but not if a vlan with
1460 * the same ID is registered on the host OS (let 8021q kill it) */
96838a40 1461 if ((adapter->hw.mng_cookie.status &
4666560a
BA		 1462 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
1463 !(adapter->vlgrp &&
5c15bdec 1464 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) {
2d7edb92
MC		 1465 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1466 }
b55ccb35
JK		 1467
1468 /* If AMT is enabled, let the firmware know that the network
1469 * interface is now closed */
1470 if (adapter->hw.mac_type == e1000_82573 &&
1471 e1000_check_mng_mode(&adapter->hw))
1472 e1000_release_hw_control(adapter);
1473
1da177e4
LT		 1474 return 0;
1475}
1476
1477/**
1478 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1479 * @adapter: address of board private structure
2d7edb92
MC		 1480 * @start: address of beginning of memory
1481 * @len: length of memory
1da177e4 1482 **/
e619d523 1483static boolean_t
1da177e4
LT		 1484e1000_check_64k_bound(struct e1000_adapter *adapter,
1485 void *start, unsigned long len)
1486{
1487 unsigned long begin = (unsigned long) start;
1488 unsigned long end = begin + len;
1489
2648345f
MC		 1490 /* First rev 82545 and 82546 need to not allow any memory
1491 * write location to cross 64k boundary due to errata 23 */
1da177e4 1492 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1493 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1494 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1495 }
1496
1497 return TRUE;
1498}
1499
1500/**
1501 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1502 * @adapter: board private structure
581d708e 1503 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1504 *
1505 * Return 0 on success, negative on failure
1506 **/
1507
3ad2cc67 1508static int
581d708e
MC		 1509e1000_setup_tx_resources(struct e1000_adapter *adapter,
1510 struct e1000_tx_ring *txdr)
1da177e4 1511{
1da177e4
LT		 1512 struct pci_dev *pdev = adapter->pdev;
1513 int size;
1514
1515 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1516 txdr->buffer_info = vmalloc(size);
96838a40 1517 if (!txdr->buffer_info) {
2648345f
MC		 1518 DPRINTK(PROBE, ERR,
1519 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1520 return -ENOMEM;
1521 }
1522 memset(txdr->buffer_info, 0, size);
1523
1524 /* round up to nearest 4K */
1525
1526 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
9099cfb9 1527 txdr->size = ALIGN(txdr->size, 4096);
1da177e4
LT		 1528
1529 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1530 if (!txdr->desc) {
1da177e4 1531setup_tx_desc_die:
1da177e4 1532 vfree(txdr->buffer_info);
2648345f
MC		 1533 DPRINTK(PROBE, ERR,
1534 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1535 return -ENOMEM;
1536 }
1537
2648345f 1538 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1539 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1540 void *olddesc = txdr->desc;
1541 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1542 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1543 "at %p\n", txdr->size, txdr->desc);
1544 /* Try again, without freeing the previous */
1da177e4 1545 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1546 /* Failed allocation, critical failure */
96838a40 1547 if (!txdr->desc) {
1da177e4
LT		 1548 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1549 goto setup_tx_desc_die;
1550 }
1551
1552 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1553 /* give up */
2648345f
MC		 1554 pci_free_consistent(pdev, txdr->size, txdr->desc,
1555 txdr->dma);
1da177e4
LT		 1556 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1557 DPRINTK(PROBE, ERR,
2648345f
MC		 1558 "Unable to allocate aligned memory "
1559 "for the transmit descriptor ring\n");
1da177e4
LT		 1560 vfree(txdr->buffer_info);
1561 return -ENOMEM;
1562 } else {
2648345f 1563 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1564 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1565 }
1566 }
1567 memset(txdr->desc, 0, txdr->size);
1568
1569 txdr->next_to_use = 0;
1570 txdr->next_to_clean = 0;
2ae76d98 1571 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1572
1573 return 0;
1574}
1575
581d708e
MC		 1576/**
1577 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1578 * (Descriptors) for all queues
1579 * @adapter: board private structure
1580 *
581d708e
MC		 1581 * Return 0 on success, negative on failure
1582 **/
1583
1584int
1585e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1586{
1587 int i, err = 0;
1588
f56799ea 1589 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1590 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1591 if (err) {
1592 DPRINTK(PROBE, ERR,
1593 "Allocation for Tx Queue %u failed\n", i);
3fbbc72e
VA		 1594 for (i-- ; i >= 0; i--)
1595 e1000_free_tx_resources(adapter,
1596 &adapter->tx_ring[i]);
581d708e
MC		 1597 break;
1598 }
1599 }
1600
1601 return err;
1602}
1603
1da177e4
LT		 1604/**
1605 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1606 * @adapter: board private structure
1607 *
1608 * Configure the Tx unit of the MAC after a reset.
1609 **/
1610
1611static void
1612e1000_configure_tx(struct e1000_adapter *adapter)
1613{
581d708e
MC		 1614 uint64_t tdba;
1615 struct e1000_hw *hw = &adapter->hw;
1616 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1617 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1618
1619 /* Setup the HW Tx Head and Tail descriptor pointers */
1620
f56799ea 1621 switch (adapter->num_tx_queues) {
24025e4e
MC		 1622 case 1:
1623 default:
581d708e
MC		 1624 tdba = adapter->tx_ring[0].dma;
1625 tdlen = adapter->tx_ring[0].count *
1626 sizeof(struct e1000_tx_desc);
581d708e 1627 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1628 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1629 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1630 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1631 E1000_WRITE_REG(hw, TDH, 0);
6a951698
AK		 1632 adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH);
1633 adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT);
24025e4e
MC		 1634 break;
1635 }
1da177e4
LT		 1636
1637 /* Set the default values for the Tx Inter Packet Gap timer */
d89b6c67
JB		 1638 if (adapter->hw.mac_type <= e1000_82547_rev_2 &&
1639 (hw->media_type == e1000_media_type_fiber ||
1640 hw->media_type == e1000_media_type_internal_serdes))
0fadb059
JK		 1641 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1642 else
1643 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1644
581d708e 1645 switch (hw->mac_type) {
1da177e4
LT		 1646 case e1000_82542_rev2_0:
1647 case e1000_82542_rev2_1:
1648 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1649 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1650 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1651 break;
87041639
JK		 1652 case e1000_80003es2lan:
1653 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1654 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1655 break;
1da177e4 1656 default:
0fadb059
JK		 1657 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1658 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1659 break;
1da177e4 1660 }
0fadb059
JK		 1661 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1662 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1663 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1664
1665 /* Set the Tx Interrupt Delay register */
1666
581d708e
MC		 1667 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1668 if (hw->mac_type >= e1000_82540)
1669 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1670
1671 /* Program the Transmit Control Register */
1672
581d708e 1673 tctl = E1000_READ_REG(hw, TCTL);
1da177e4 1674 tctl &= ~E1000_TCTL_CT;
7e6c9861 1675 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1676 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1677
2ae76d98
MC		 1678 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1679 tarc = E1000_READ_REG(hw, TARC0);
90fb5135
AK		 1680 /* set the speed mode bit, we'll clear it if we're not at
1681 * gigabit link later */
09ae3e88 1682 tarc |= (1 << 21);
2ae76d98 1683 E1000_WRITE_REG(hw, TARC0, tarc);
87041639
JK		 1684 } else if (hw->mac_type == e1000_80003es2lan) {
1685 tarc = E1000_READ_REG(hw, TARC0);
1686 tarc |= 1;
87041639
JK		 1687 E1000_WRITE_REG(hw, TARC0, tarc);
1688 tarc = E1000_READ_REG(hw, TARC1);
1689 tarc |= 1;
1690 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1691 }
1692
581d708e 1693 e1000_config_collision_dist(hw);
1da177e4
LT		 1694
1695 /* Setup Transmit Descriptor Settings for eop descriptor */
6a042dab
JB		 1696 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1697
1698 /* only set IDE if we are delaying interrupts using the timers */
1699 if (adapter->tx_int_delay)
1700 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1da177e4 1701
581d708e 1702 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1703 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1704 else
1705 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1706
1707 /* Cache if we're 82544 running in PCI-X because we'll
1708 * need this to apply a workaround later in the send path. */
581d708e
MC		 1709 if (hw->mac_type == e1000_82544 &&
1710 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1711 adapter->pcix_82544 = 1;
7e6c9861
JK		 1712
1713 E1000_WRITE_REG(hw, TCTL, tctl);
1714
1da177e4
LT		 1715}
1716
1717/**
1718 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1719 * @adapter: board private structure
581d708e 1720 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1721 *
1722 * Returns 0 on success, negative on failure
1723 **/
1724
3ad2cc67 1725static int
581d708e
MC		 1726e1000_setup_rx_resources(struct e1000_adapter *adapter,
1727 struct e1000_rx_ring *rxdr)
1da177e4 1728{
1da177e4 1729 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1730 int size, desc_len;
1da177e4
LT		 1731
1732 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1733 rxdr->buffer_info = vmalloc(size);
581d708e 1734 if (!rxdr->buffer_info) {
2648345f
MC		 1735 DPRINTK(PROBE, ERR,
1736 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1737 return -ENOMEM;
1738 }
1739 memset(rxdr->buffer_info, 0, size);
1740
1c7e5b12
YB		 1741 rxdr->ps_page = kcalloc(rxdr->count, sizeof(struct e1000_ps_page),
1742 GFP_KERNEL);
96838a40 1743 if (!rxdr->ps_page) {
2d7edb92
MC		 1744 vfree(rxdr->buffer_info);
1745 DPRINTK(PROBE, ERR,
1746 "Unable to allocate memory for the receive descriptor ring\n");
1747 return -ENOMEM;
1748 }
2d7edb92 1749
1c7e5b12
YB		 1750 rxdr->ps_page_dma = kcalloc(rxdr->count,
1751 sizeof(struct e1000_ps_page_dma),
1752 GFP_KERNEL);
96838a40 1753 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1754 vfree(rxdr->buffer_info);
1755 kfree(rxdr->ps_page);
1756 DPRINTK(PROBE, ERR,
1757 "Unable to allocate memory for the receive descriptor ring\n");
1758 return -ENOMEM;
1759 }
2d7edb92 1760
96838a40 1761 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1762 desc_len = sizeof(struct e1000_rx_desc);
1763 else
1764 desc_len = sizeof(union e1000_rx_desc_packet_split);
1765
1da177e4
LT		 1766 /* Round up to nearest 4K */
1767
2d7edb92 1768 rxdr->size = rxdr->count * desc_len;
9099cfb9 1769 rxdr->size = ALIGN(rxdr->size, 4096);
1da177e4
LT		 1770
1771 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1772
581d708e
MC		 1773 if (!rxdr->desc) {
1774 DPRINTK(PROBE, ERR,
1775 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1776setup_rx_desc_die:
1da177e4 1777 vfree(rxdr->buffer_info);
2d7edb92
MC		 1778 kfree(rxdr->ps_page);
1779 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1780 return -ENOMEM;
1781 }
1782
2648345f 1783 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1784 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1785 void *olddesc = rxdr->desc;
1786 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1787 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1788 "at %p\n", rxdr->size, rxdr->desc);
1789 /* Try again, without freeing the previous */
1da177e4 1790 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1791 /* Failed allocation, critical failure */
581d708e 1792 if (!rxdr->desc) {
1da177e4 1793 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1794 DPRINTK(PROBE, ERR,
1795 "Unable to allocate memory "
1796 "for the receive descriptor ring\n");
1da177e4
LT		 1797 goto setup_rx_desc_die;
1798 }
1799
1800 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1801 /* give up */
2648345f
MC		 1802 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1803 rxdr->dma);
1da177e4 1804 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1805 DPRINTK(PROBE, ERR,
1806 "Unable to allocate aligned memory "
1807 "for the receive descriptor ring\n");
581d708e 1808 goto setup_rx_desc_die;
1da177e4 1809 } else {
2648345f 1810 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1811 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1812 }
1813 }
1814 memset(rxdr->desc, 0, rxdr->size);
1815
1816 rxdr->next_to_clean = 0;
1817 rxdr->next_to_use = 0;
1818
1819 return 0;
1820}
1821
581d708e
MC		 1822/**
1823 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1824 * (Descriptors) for all queues
1825 * @adapter: board private structure
1826 *
581d708e
MC		 1827 * Return 0 on success, negative on failure
1828 **/
1829
1830int
1831e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1832{
1833 int i, err = 0;
1834
f56799ea 1835 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1836 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1837 if (err) {
1838 DPRINTK(PROBE, ERR,
1839 "Allocation for Rx Queue %u failed\n", i);
3fbbc72e
VA		 1840 for (i-- ; i >= 0; i--)
1841 e1000_free_rx_resources(adapter,
1842 &adapter->rx_ring[i]);
581d708e
MC		 1843 break;
1844 }
1845 }
1846
1847 return err;
1848}
1849
1da177e4 1850/**
2648345f 1851 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1852 * @adapter: Board private structure
1853 **/
e4c811c9
MC		 1854#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1855 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1856static void
1857e1000_setup_rctl(struct e1000_adapter *adapter)
1858{
2d7edb92
MC		 1859 uint32_t rctl, rfctl;
1860 uint32_t psrctl = 0;
35ec56bb 1861#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1862 uint32_t pages = 0;
1863#endif
1da177e4
LT		 1864
1865 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1866
1867 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1868
1869 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1870 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1871 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1872
0fadb059 1873 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1874 rctl |= E1000_RCTL_SBP;
1875 else
1876 rctl &= ~E1000_RCTL_SBP;
1877
2d7edb92
MC		 1878 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1879 rctl &= ~E1000_RCTL_LPE;
1880 else
1881 rctl |= E1000_RCTL_LPE;
1882
1da177e4 1883 /* Setup buffer sizes */
9e2feace
AK		 1884 rctl &= ~E1000_RCTL_SZ_4096;
1885 rctl |= E1000_RCTL_BSEX;
1886 switch (adapter->rx_buffer_len) {
1887 case E1000_RXBUFFER_256:
1888 rctl |= E1000_RCTL_SZ_256;
1889 rctl &= ~E1000_RCTL_BSEX;
1890 break;
1891 case E1000_RXBUFFER_512:
1892 rctl |= E1000_RCTL_SZ_512;
1893 rctl &= ~E1000_RCTL_BSEX;
1894 break;
1895 case E1000_RXBUFFER_1024:
1896 rctl |= E1000_RCTL_SZ_1024;
1897 rctl &= ~E1000_RCTL_BSEX;
1898 break;
a1415ee6
JK		 1899 case E1000_RXBUFFER_2048:
1900 default:
1901 rctl |= E1000_RCTL_SZ_2048;
1902 rctl &= ~E1000_RCTL_BSEX;
1903 break;
1904 case E1000_RXBUFFER_4096:
1905 rctl |= E1000_RCTL_SZ_4096;
1906 break;
1907 case E1000_RXBUFFER_8192:
1908 rctl |= E1000_RCTL_SZ_8192;
1909 break;
1910 case E1000_RXBUFFER_16384:
1911 rctl |= E1000_RCTL_SZ_16384;
1912 break;
2d7edb92
MC		 1913 }
1914
35ec56bb 1915#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1916 /* 82571 and greater support packet-split where the protocol
1917 * header is placed in skb->data and the packet data is
1918 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1919 * In the case of a non-split, skb->data is linearly filled,
1920 * followed by the page buffers. Therefore, skb->data is
1921 * sized to hold the largest protocol header.
1922 */
e64d7d02
JB		 1923 /* allocations using alloc_page take too long for regular MTU
1924 * so only enable packet split for jumbo frames */
e4c811c9 1925 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
e64d7d02
JB		 1926 if ((adapter->hw.mac_type >= e1000_82571) && (pages <= 3) &&
1927 PAGE_SIZE <= 16384 && (rctl & E1000_RCTL_LPE))
e4c811c9
MC		 1928 adapter->rx_ps_pages = pages;
1929 else
1930 adapter->rx_ps_pages = 0;
2d7edb92 1931#endif
e4c811c9 1932 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1933 /* Configure extra packet-split registers */
1934 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1935 rfctl |= E1000_RFCTL_EXTEN;
87ca4e5b
AK		 1936 /* disable packet split support for IPv6 extension headers,
1937 * because some malformed IPv6 headers can hang the RX */
1938 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
1939 E1000_RFCTL_NEW_IPV6_EXT_DIS);
1940
2d7edb92
MC		 1941 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1942
7dfee0cb 1943 rctl |= E1000_RCTL_DTYP_PS;
96838a40 1944
2d7edb92
MC		 1945 psrctl |= adapter->rx_ps_bsize0 >>
1946 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1947
1948 switch (adapter->rx_ps_pages) {
1949 case 3:
1950 psrctl |= PAGE_SIZE <<
1951 E1000_PSRCTL_BSIZE3_SHIFT;
1952 case 2:
1953 psrctl |= PAGE_SIZE <<
1954 E1000_PSRCTL_BSIZE2_SHIFT;
1955 case 1:
1956 psrctl |= PAGE_SIZE >>
1957 E1000_PSRCTL_BSIZE1_SHIFT;
1958 break;
1959 }
2d7edb92
MC		 1960
1961 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1962 }
1963
1964 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1965}
1966
1967/**
1968 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1969 * @adapter: board private structure
1970 *
1971 * Configure the Rx unit of the MAC after a reset.
1972 **/
1973
1974static void
1975e1000_configure_rx(struct e1000_adapter *adapter)
1976{
581d708e
MC		 1977 uint64_t rdba;
1978 struct e1000_hw *hw = &adapter->hw;
1979 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 1980
e4c811c9 1981 if (adapter->rx_ps_pages) {
0f15a8fa 1982 /* this is a 32 byte descriptor */
581d708e 1983 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 1984 sizeof(union e1000_rx_desc_packet_split);
1985 adapter->clean_rx = e1000_clean_rx_irq_ps;
1986 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
1987 } else {
581d708e
MC		 1988 rdlen = adapter->rx_ring[0].count *
1989 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 1990 adapter->clean_rx = e1000_clean_rx_irq;
1991 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
1992 }
1da177e4
LT		 1993
1994 /* disable receives while setting up the descriptors */
581d708e
MC		 1995 rctl = E1000_READ_REG(hw, RCTL);
1996 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 1997
1998 /* set the Receive Delay Timer Register */
581d708e 1999 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 2000
581d708e
MC		 2001 if (hw->mac_type >= e1000_82540) {
2002 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
835bb129 2003 if (adapter->itr_setting != 0)
581d708e 2004 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 2005 1000000000 / (adapter->itr * 256));
2006 }
2007
2ae76d98 2008 if (hw->mac_type >= e1000_82571) {
2ae76d98 2009 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 2010 /* Reset delay timers after every interrupt */
6fc7a7ec 2011 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9 2012#ifdef CONFIG_E1000_NAPI
835bb129 2013 /* Auto-Mask interrupts upon ICR access */
1e613fd9 2014 ctrl_ext |= E1000_CTRL_EXT_IAME;
835bb129 2015 E1000_WRITE_REG(hw, IAM, 0xffffffff);
1e613fd9 2016#endif
2ae76d98
MC		 2017 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2018 E1000_WRITE_FLUSH(hw);
2019 }
2020
581d708e
MC		 2021 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2022 * the Base and Length of the Rx Descriptor Ring */
f56799ea 2023 switch (adapter->num_rx_queues) {
24025e4e
MC		 2024 case 1:
2025 default:
581d708e 2026 rdba = adapter->rx_ring[0].dma;
581d708e 2027 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 2028 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
2029 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 2030 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 2031 E1000_WRITE_REG(hw, RDH, 0);
6a951698
AK		 2032 adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH);
2033 adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT);
581d708e 2034 break;
24025e4e
MC		 2035 }
2036
1da177e4 2037 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 2038 if (hw->mac_type >= e1000_82543) {
2039 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 2040 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 2041 rxcsum |= E1000_RXCSUM_TUOFL;
2042
868d5309 2043 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 2044 * Must be used in conjunction with packet-split. */
96838a40
JB		 2045 if ((hw->mac_type >= e1000_82571) &&
2046 (adapter->rx_ps_pages)) {
2d7edb92
MC		 2047 rxcsum |= E1000_RXCSUM_IPPCSE;
2048 }
2049 } else {
2050 rxcsum &= ~E1000_RXCSUM_TUOFL;
2051 /* don't need to clear IPPCSE as it defaults to 0 */
2052 }
581d708e 2053 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 2054 }
2055
21c4d5e0
AK		 2056 /* enable early receives on 82573, only takes effect if using > 2048
2057 * byte total frame size. for example only for jumbo frames */
2058#define E1000_ERT_2048 0x100
2059 if (hw->mac_type == e1000_82573)
2060 E1000_WRITE_REG(hw, ERT, E1000_ERT_2048);
2061
1da177e4 2062 /* Enable Receives */
581d708e 2063 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 2064}
2065
2066/**
581d708e 2067 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 2068 * @adapter: board private structure
581d708e 2069 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 2070 *
2071 * Free all transmit software resources
2072 **/
2073
3ad2cc67 2074static void
581d708e
MC		 2075e1000_free_tx_resources(struct e1000_adapter *adapter,
2076 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 2077{
2078 struct pci_dev *pdev = adapter->pdev;
2079
581d708e 2080 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 2081
581d708e
MC		 2082 vfree(tx_ring->buffer_info);
2083 tx_ring->buffer_info = NULL;
1da177e4 2084
581d708e 2085 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 2086
581d708e
MC		 2087 tx_ring->desc = NULL;
2088}
2089
2090/**
2091 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
2092 * @adapter: board private structure
2093 *
2094 * Free all transmit software resources
2095 **/
2096
2097void
2098e1000_free_all_tx_resources(struct e1000_adapter *adapter)
2099{
2100 int i;
2101
f56799ea 2102 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2103 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2104}
2105
e619d523 2106static void
1da177e4
LT		 2107e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
2108 struct e1000_buffer *buffer_info)
2109{
96838a40 2110 if (buffer_info->dma) {
2648345f
MC		 2111 pci_unmap_page(adapter->pdev,
2112 buffer_info->dma,
2113 buffer_info->length,
2114 PCI_DMA_TODEVICE);
a9ebadd6 2115 buffer_info->dma = 0;
1da177e4 2116 }
a9ebadd6 2117 if (buffer_info->skb) {
1da177e4 2118 dev_kfree_skb_any(buffer_info->skb);
a9ebadd6
JB		 2119 buffer_info->skb = NULL;
2120 }
2121 /* buffer_info must be completely set up in the transmit path */
1da177e4
LT		 2122}
2123
2124/**
2125 * e1000_clean_tx_ring - Free Tx Buffers
2126 * @adapter: board private structure
581d708e 2127 * @tx_ring: ring to be cleaned
1da177e4
LT		 2128 **/
2129
2130static void
581d708e
MC		 2131e1000_clean_tx_ring(struct e1000_adapter *adapter,
2132 struct e1000_tx_ring *tx_ring)
1da177e4 2133{
1da177e4
LT		 2134 struct e1000_buffer *buffer_info;
2135 unsigned long size;
2136 unsigned int i;
2137
2138 /* Free all the Tx ring sk_buffs */
2139
96838a40 2140 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 2141 buffer_info = &tx_ring->buffer_info[i];
2142 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
2143 }
2144
2145 size = sizeof(struct e1000_buffer) * tx_ring->count;
2146 memset(tx_ring->buffer_info, 0, size);
2147
2148 /* Zero out the descriptor ring */
2149
2150 memset(tx_ring->desc, 0, tx_ring->size);
2151
2152 tx_ring->next_to_use = 0;
2153 tx_ring->next_to_clean = 0;
fd803241 2154 tx_ring->last_tx_tso = 0;
1da177e4 2155
581d708e
MC		 2156 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
2157 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
2158}
2159
2160/**
2161 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
2162 * @adapter: board private structure
2163 **/
2164
2165static void
2166e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
2167{
2168 int i;
2169
f56799ea 2170 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2171 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2172}
2173
2174/**
2175 * e1000_free_rx_resources - Free Rx Resources
2176 * @adapter: board private structure
581d708e 2177 * @rx_ring: ring to clean the resources from
1da177e4
LT		 2178 *
2179 * Free all receive software resources
2180 **/
2181
3ad2cc67 2182static void
581d708e
MC		 2183e1000_free_rx_resources(struct e1000_adapter *adapter,
2184 struct e1000_rx_ring *rx_ring)
1da177e4 2185{
1da177e4
LT		 2186 struct pci_dev *pdev = adapter->pdev;
2187
581d708e 2188 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 2189
2190 vfree(rx_ring->buffer_info);
2191 rx_ring->buffer_info = NULL;
2d7edb92
MC		 2192 kfree(rx_ring->ps_page);
2193 rx_ring->ps_page = NULL;
2194 kfree(rx_ring->ps_page_dma);
2195 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2196
2197 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2198
2199 rx_ring->desc = NULL;
2200}
2201
2202/**
581d708e 2203 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2204 * @adapter: board private structure
581d708e
MC		 2205 *
2206 * Free all receive software resources
2207 **/
2208
2209void
2210e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2211{
2212 int i;
2213
f56799ea 2214 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2215 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2216}
2217
2218/**
2219 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2220 * @adapter: board private structure
2221 * @rx_ring: ring to free buffers from
1da177e4
LT		 2222 **/
2223
2224static void
581d708e
MC		 2225e1000_clean_rx_ring(struct e1000_adapter *adapter,
2226 struct e1000_rx_ring *rx_ring)
1da177e4 2227{
1da177e4 2228 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2229 struct e1000_ps_page *ps_page;
2230 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2231 struct pci_dev *pdev = adapter->pdev;
2232 unsigned long size;
2d7edb92 2233 unsigned int i, j;
1da177e4
LT		 2234
2235 /* Free all the Rx ring sk_buffs */
96838a40 2236 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2237 buffer_info = &rx_ring->buffer_info[i];
96838a40 2238 if (buffer_info->skb) {
1da177e4
LT		 2239 pci_unmap_single(pdev,
2240 buffer_info->dma,
2241 buffer_info->length,
2242 PCI_DMA_FROMDEVICE);
2243
2244 dev_kfree_skb(buffer_info->skb);
2245 buffer_info->skb = NULL;
997f5cbd
JK		 2246 }
2247 ps_page = &rx_ring->ps_page[i];
2248 ps_page_dma = &rx_ring->ps_page_dma[i];
2249 for (j = 0; j < adapter->rx_ps_pages; j++) {
2250 if (!ps_page->ps_page[j]) break;
2251 pci_unmap_page(pdev,
2252 ps_page_dma->ps_page_dma[j],
2253 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2254 ps_page_dma->ps_page_dma[j] = 0;
2255 put_page(ps_page->ps_page[j]);
2256 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2257 }
2258 }
2259
2260 size = sizeof(struct e1000_buffer) * rx_ring->count;
2261 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2262 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2263 memset(rx_ring->ps_page, 0, size);
2264 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2265 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2266
2267 /* Zero out the descriptor ring */
2268
2269 memset(rx_ring->desc, 0, rx_ring->size);
2270
2271 rx_ring->next_to_clean = 0;
2272 rx_ring->next_to_use = 0;
2273
581d708e
MC		 2274 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2275 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2276}
2277
2278/**
2279 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2280 * @adapter: board private structure
2281 **/
2282
2283static void
2284e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2285{
2286 int i;
2287
f56799ea 2288 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2289 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2290}
2291
2292/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2293 * and memory write and invalidate disabled for certain operations
2294 */
2295static void
2296e1000_enter_82542_rst(struct e1000_adapter *adapter)
2297{
2298 struct net_device *netdev = adapter->netdev;
2299 uint32_t rctl;
2300
2301 e1000_pci_clear_mwi(&adapter->hw);
2302
2303 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2304 rctl |= E1000_RCTL_RST;
2305 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2306 E1000_WRITE_FLUSH(&adapter->hw);
2307 mdelay(5);
2308
96838a40 2309 if (netif_running(netdev))
581d708e 2310 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2311}
2312
2313static void
2314e1000_leave_82542_rst(struct e1000_adapter *adapter)
2315{
2316 struct net_device *netdev = adapter->netdev;
2317 uint32_t rctl;
2318
2319 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2320 rctl &= ~E1000_RCTL_RST;
2321 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2322 E1000_WRITE_FLUSH(&adapter->hw);
2323 mdelay(5);
2324
96838a40 2325 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2326 e1000_pci_set_mwi(&adapter->hw);
2327
96838a40 2328 if (netif_running(netdev)) {
72d64a43
JK		 2329 /* No need to loop, because 82542 supports only 1 queue */
2330 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2331 e1000_configure_rx(adapter);
72d64a43 2332 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2333 }
2334}
2335
2336/**
2337 * e1000_set_mac - Change the Ethernet Address of the NIC
2338 * @netdev: network interface device structure
2339 * @p: pointer to an address structure
2340 *
2341 * Returns 0 on success, negative on failure
2342 **/
2343
2344static int
2345e1000_set_mac(struct net_device *netdev, void *p)
2346{
60490fe0 2347 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2348 struct sockaddr *addr = p;
2349
96838a40 2350 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2351 return -EADDRNOTAVAIL;
2352
2353 /* 82542 2.0 needs to be in reset to write receive address registers */
2354
96838a40 2355 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2356 e1000_enter_82542_rst(adapter);
2357
2358 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2359 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2360
2361 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2362
868d5309
MC		 2363 /* With 82571 controllers, LAA may be overwritten (with the default)
2364 * due to controller reset from the other port. */
2365 if (adapter->hw.mac_type == e1000_82571) {
2366 /* activate the work around */
2367 adapter->hw.laa_is_present = 1;
2368
96838a40
JB		 2369 /* Hold a copy of the LAA in RAR[14] This is done so that
2370 * between the time RAR[0] gets clobbered and the time it
2371 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2372 * of the RARs and no incoming packets directed to this port
96838a40 2373 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2374 * RAR[14] */
96838a40 2375 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2376 E1000_RAR_ENTRIES - 1);
2377 }
2378
96838a40 2379 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2380 e1000_leave_82542_rst(adapter);
2381
2382 return 0;
2383}
2384
2385/**
db0ce50d 2386 * e1000_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
1da177e4
LT		 2387 * @netdev: network interface device structure
2388 *
db0ce50d
PM		 2389 * The set_rx_mode entry point is called whenever the unicast or multicast
2390 * address lists or the network interface flags are updated. This routine is
2391 * responsible for configuring the hardware for proper unicast, multicast,
1da177e4
LT		 2392 * promiscuous mode, and all-multi behavior.
2393 **/
2394
2395static void
db0ce50d 2396e1000_set_rx_mode(struct net_device *netdev)
1da177e4 2397{
60490fe0 2398 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 2399 struct e1000_hw *hw = &adapter->hw;
db0ce50d
PM		 2400 struct dev_addr_list *uc_ptr;
2401 struct dev_addr_list *mc_ptr;
1da177e4
LT		 2402 uint32_t rctl;
2403 uint32_t hash_value;
868d5309 2404 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2405 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2406 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2407 E1000_NUM_MTA_REGISTERS;
2408
2409 if (adapter->hw.mac_type == e1000_ich8lan)
2410 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2411
868d5309
MC		 2412 /* reserve RAR[14] for LAA over-write work-around */
2413 if (adapter->hw.mac_type == e1000_82571)
2414 rar_entries--;
1da177e4 2415
2648345f
MC		 2416 /* Check for Promiscuous and All Multicast modes */
2417
1da177e4
LT		 2418 rctl = E1000_READ_REG(hw, RCTL);
2419
96838a40 2420 if (netdev->flags & IFF_PROMISC) {
1da177e4 2421 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2422 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4 2423 rctl |= E1000_RCTL_MPE;
1da177e4 2424 } else {
db0ce50d
PM		 2425 rctl &= ~E1000_RCTL_MPE;
2426 }
2427
2428 uc_ptr = NULL;
2429 if (netdev->uc_count > rar_entries - 1) {
2430 rctl |= E1000_RCTL_UPE;
2431 } else if (!(netdev->flags & IFF_PROMISC)) {
2432 rctl &= ~E1000_RCTL_UPE;
2433 uc_ptr = netdev->uc_list;
1da177e4
LT		 2434 }
2435
2436 E1000_WRITE_REG(hw, RCTL, rctl);
2437
2438 /* 82542 2.0 needs to be in reset to write receive address registers */
2439
96838a40 2440 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2441 e1000_enter_82542_rst(adapter);
2442
db0ce50d
PM		 2443 /* load the first 14 addresses into the exact filters 1-14. Unicast
2444 * addresses take precedence to avoid disabling unicast filtering
2445 * when possible.
2446 *
1da177e4
LT		 2447 * RAR 0 is used for the station MAC adddress
2448 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2449 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2450 */
2451 mc_ptr = netdev->mc_list;
2452
96838a40 2453 for (i = 1; i < rar_entries; i++) {
db0ce50d
PM		 2454 if (uc_ptr) {
2455 e1000_rar_set(hw, uc_ptr->da_addr, i);
2456 uc_ptr = uc_ptr->next;
2457 } else if (mc_ptr) {
2458 e1000_rar_set(hw, mc_ptr->da_addr, i);
1da177e4
LT		 2459 mc_ptr = mc_ptr->next;
2460 } else {
2461 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2462 E1000_WRITE_FLUSH(hw);
1da177e4 2463 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2464 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2465 }
2466 }
db0ce50d 2467 WARN_ON(uc_ptr != NULL);
1da177e4
LT		 2468
2469 /* clear the old settings from the multicast hash table */
2470
cd94dd0b 2471 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2472 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2473 E1000_WRITE_FLUSH(hw);
2474 }
1da177e4
LT		 2475
2476 /* load any remaining addresses into the hash table */
2477
96838a40 2478 for (; mc_ptr; mc_ptr = mc_ptr->next) {
db0ce50d 2479 hash_value = e1000_hash_mc_addr(hw, mc_ptr->da_addr);
1da177e4
LT		 2480 e1000_mta_set(hw, hash_value);
2481 }
2482
96838a40 2483 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2484 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2485}
2486
2487/* Need to wait a few seconds after link up to get diagnostic information from
2488 * the phy */
2489
2490static void
2491e1000_update_phy_info(unsigned long data)
2492{
2493 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2494 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2495}
2496
2497/**
2498 * e1000_82547_tx_fifo_stall - Timer Call-back
2499 * @data: pointer to adapter cast into an unsigned long
2500 **/
2501
2502static void
2503e1000_82547_tx_fifo_stall(unsigned long data)
2504{
2505 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2506 struct net_device *netdev = adapter->netdev;
2507 uint32_t tctl;
2508
96838a40
JB		 2509 if (atomic_read(&adapter->tx_fifo_stall)) {
2510 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2511 E1000_READ_REG(&adapter->hw, TDH)) &&
2512 (E1000_READ_REG(&adapter->hw, TDFT) ==
2513 E1000_READ_REG(&adapter->hw, TDFH)) &&
2514 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2515 E1000_READ_REG(&adapter->hw, TDFHS))) {
2516 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2517 E1000_WRITE_REG(&adapter->hw, TCTL,
2518 tctl & ~E1000_TCTL_EN);
2519 E1000_WRITE_REG(&adapter->hw, TDFT,
2520 adapter->tx_head_addr);
2521 E1000_WRITE_REG(&adapter->hw, TDFH,
2522 adapter->tx_head_addr);
2523 E1000_WRITE_REG(&adapter->hw, TDFTS,
2524 adapter->tx_head_addr);
2525 E1000_WRITE_REG(&adapter->hw, TDFHS,
2526 adapter->tx_head_addr);
2527 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2528 E1000_WRITE_FLUSH(&adapter->hw);
2529
2530 adapter->tx_fifo_head = 0;
2531 atomic_set(&adapter->tx_fifo_stall, 0);
2532 netif_wake_queue(netdev);
2533 } else {
2534 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2535 }
2536 }
2537}
2538
2539/**
2540 * e1000_watchdog - Timer Call-back
2541 * @data: pointer to adapter cast into an unsigned long
2542 **/
2543static void
2544e1000_watchdog(unsigned long data)
2545{
2546 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2547 struct net_device *netdev = adapter->netdev;
545c67c0 2548 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2549 uint32_t link, tctl;
cd94dd0b
AK		 2550 int32_t ret_val;
2551
2552 ret_val = e1000_check_for_link(&adapter->hw);
2553 if ((ret_val == E1000_ERR_PHY) &&
2554 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2555 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2556 /* See e1000_kumeran_lock_loss_workaround() */
2557 DPRINTK(LINK, INFO,
2558 "Gigabit has been disabled, downgrading speed\n");
2559 }
90fb5135 2560
2d7edb92
MC		 2561 if (adapter->hw.mac_type == e1000_82573) {
2562 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2563 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2564 e1000_update_mng_vlan(adapter);
96838a40 2565 }
1da177e4 2566
96838a40 2567 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2568 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2569 link = !adapter->hw.serdes_link_down;
2570 else
2571 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2572
96838a40
JB		 2573 if (link) {
2574 if (!netif_carrier_ok(netdev)) {
9669f53b 2575 uint32_t ctrl;
fe7fe28e 2576 boolean_t txb2b = 1;
1da177e4
LT		 2577 e1000_get_speed_and_duplex(&adapter->hw,
2578 &adapter->link_speed,
2579 &adapter->link_duplex);
2580
9669f53b
AK		 2581 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
2582 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s, "
2583 "Flow Control: %s\n",
2584 adapter->link_speed,
2585 adapter->link_duplex == FULL_DUPLEX ?
2586 "Full Duplex" : "Half Duplex",
2587 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2588 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2589 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2590 E1000_CTRL_TFCE) ? "TX" : "None" )));
1da177e4 2591
7e6c9861
JK		 2592 /* tweak tx_queue_len according to speed/duplex
2593 * and adjust the timeout factor */
66a2b0a3
JK		 2594 netdev->tx_queue_len = adapter->tx_queue_len;
2595 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2596 switch (adapter->link_speed) {
2597 case SPEED_10:
fe7fe28e 2598 txb2b = 0;
7e6c9861
JK		 2599 netdev->tx_queue_len = 10;
2600 adapter->tx_timeout_factor = 8;
2601 break;
2602 case SPEED_100:
fe7fe28e 2603 txb2b = 0;
7e6c9861
JK		 2604 netdev->tx_queue_len = 100;
2605 /* maybe add some timeout factor ? */
2606 break;
2607 }
2608
fe7fe28e 2609 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2610 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2611 txb2b == 0) {
7e6c9861
JK		 2612 uint32_t tarc0;
2613 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
90fb5135 2614 tarc0 &= ~(1 << 21);
7e6c9861
JK		 2615 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2616 }
90fb5135 2617
7e6c9861
JK		 2618 /* disable TSO for pcie and 10/100 speeds, to avoid
2619 * some hardware issues */
2620 if (!adapter->tso_force &&
2621 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2622 switch (adapter->link_speed) {
2623 case SPEED_10:
66a2b0a3 2624 case SPEED_100:
7e6c9861
JK		 2625 DPRINTK(PROBE,INFO,
2626 "10/100 speed: disabling TSO\n");
2627 netdev->features &= ~NETIF_F_TSO;
87ca4e5b 2628 netdev->features &= ~NETIF_F_TSO6;
7e6c9861
JK		 2629 break;
2630 case SPEED_1000:
2631 netdev->features |= NETIF_F_TSO;
87ca4e5b 2632 netdev->features |= NETIF_F_TSO6;
7e6c9861
JK		 2633 break;
2634 default:
2635 /* oops */
66a2b0a3
JK		 2636 break;
2637 }
2638 }
7e6c9861
JK		 2639
2640 /* enable transmits in the hardware, need to do this
2641 * after setting TARC0 */
2642 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2643 tctl |= E1000_TCTL_EN;
2644 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2645
1da177e4
LT		 2646 netif_carrier_on(netdev);
2647 netif_wake_queue(netdev);
56e1393f 2648 mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
1da177e4 2649 adapter->smartspeed = 0;
bb8e3311
JG		 2650 } else {
2651 /* make sure the receive unit is started */
2652 if (adapter->hw.rx_needs_kicking) {
2653 struct e1000_hw *hw = &adapter->hw;
2654 uint32_t rctl = E1000_READ_REG(hw, RCTL);
2655 E1000_WRITE_REG(hw, RCTL, rctl | E1000_RCTL_EN);
2656 }
1da177e4
LT		 2657 }
2658 } else {
96838a40 2659 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2660 adapter->link_speed = 0;
2661 adapter->link_duplex = 0;
2662 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2663 netif_carrier_off(netdev);
2664 netif_stop_queue(netdev);
56e1393f 2665 mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
87041639
JK		 2666
2667 /* 80003ES2LAN workaround--
2668 * For packet buffer work-around on link down event;
2669 * disable receives in the ISR and
2670 * reset device here in the watchdog
2671 */
8fc897b0 2672 if (adapter->hw.mac_type == e1000_80003es2lan)
87041639
JK		 2673 /* reset device */
2674 schedule_work(&adapter->reset_task);
1da177e4
LT		 2675 }
2676
2677 e1000_smartspeed(adapter);
2678 }
2679
2680 e1000_update_stats(adapter);
2681
2682 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2683 adapter->tpt_old = adapter->stats.tpt;
2684 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2685 adapter->colc_old = adapter->stats.colc;
2686
2687 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2688 adapter->gorcl_old = adapter->stats.gorcl;
2689 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2690 adapter->gotcl_old = adapter->stats.gotcl;
2691
2692 e1000_update_adaptive(&adapter->hw);
2693
f56799ea 2694 if (!netif_carrier_ok(netdev)) {
581d708e 2695 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2696 /* We've lost link, so the controller stops DMA,
2697 * but we've got queued Tx work that's never going
2698 * to get done, so reset controller to flush Tx.
2699 * (Do the reset outside of interrupt context). */
87041639
JK		 2700 adapter->tx_timeout_count++;
2701 schedule_work(&adapter->reset_task);
1da177e4
LT		 2702 }
2703 }
2704
1da177e4
LT		 2705 /* Cause software interrupt to ensure rx ring is cleaned */
2706 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2707
2648345f 2708 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2709 adapter->detect_tx_hung = TRUE;
2710
96838a40 2711 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2712 * reset from the other port. Set the appropriate LAA in RAR[0] */
2713 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2714 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2715
1da177e4 2716 /* Reset the timer */
56e1393f 2717 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
1da177e4
LT		 2718}
2719
835bb129
JB		 2720enum latency_range {
2721 lowest_latency = 0,
2722 low_latency = 1,
2723 bulk_latency = 2,
2724 latency_invalid = 255
2725};
2726
2727/**
2728 * e1000_update_itr - update the dynamic ITR value based on statistics
2729 * Stores a new ITR value based on packets and byte
2730 * counts during the last interrupt. The advantage of per interrupt
2731 * computation is faster updates and more accurate ITR for the current
2732 * traffic pattern. Constants in this function were computed
2733 * based on theoretical maximum wire speed and thresholds were set based
2734 * on testing data as well as attempting to minimize response time
2735 * while increasing bulk throughput.
2736 * this functionality is controlled by the InterruptThrottleRate module
2737 * parameter (see e1000_param.c)
2738 * @adapter: pointer to adapter
2739 * @itr_setting: current adapter->itr
2740 * @packets: the number of packets during this measurement interval
2741 * @bytes: the number of bytes during this measurement interval
2742 **/
2743static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2744 uint16_t itr_setting,
2745 int packets,
2746 int bytes)
2747{
2748 unsigned int retval = itr_setting;
2749 struct e1000_hw *hw = &adapter->hw;
2750
2751 if (unlikely(hw->mac_type < e1000_82540))
2752 goto update_itr_done;
2753
2754 if (packets == 0)
2755 goto update_itr_done;
2756
835bb129
JB		 2757 switch (itr_setting) {
2758 case lowest_latency:
2b65326e
JB		 2759 /* jumbo frames get bulk treatment*/
2760 if (bytes/packets > 8000)
2761 retval = bulk_latency;
2762 else if ((packets < 5) && (bytes > 512))
835bb129
JB		 2763 retval = low_latency;
2764 break;
2765 case low_latency: /* 50 usec aka 20000 ints/s */
2766 if (bytes > 10000) {
2b65326e
JB		 2767 /* jumbo frames need bulk latency setting */
2768 if (bytes/packets > 8000)
2769 retval = bulk_latency;
2770 else if ((packets < 10) || ((bytes/packets) > 1200))
835bb129
JB		 2771 retval = bulk_latency;
2772 else if ((packets > 35))
2773 retval = lowest_latency;
2b65326e
JB		 2774 } else if (bytes/packets > 2000)
2775 retval = bulk_latency;
2776 else if (packets <= 2 && bytes < 512)
835bb129
JB		 2777 retval = lowest_latency;
2778 break;
2779 case bulk_latency: /* 250 usec aka 4000 ints/s */
2780 if (bytes > 25000) {
2781 if (packets > 35)
2782 retval = low_latency;
2b65326e
JB		 2783 } else if (bytes < 6000) {
2784 retval = low_latency;
835bb129
JB		 2785 }
2786 break;
2787 }
2788
2789update_itr_done:
2790 return retval;
2791}
2792
2793static void e1000_set_itr(struct e1000_adapter *adapter)
2794{
2795 struct e1000_hw *hw = &adapter->hw;
2796 uint16_t current_itr;
2797 uint32_t new_itr = adapter->itr;
2798
2799 if (unlikely(hw->mac_type < e1000_82540))
2800 return;
2801
2802 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2803 if (unlikely(adapter->link_speed != SPEED_1000)) {
2804 current_itr = 0;
2805 new_itr = 4000;
2806 goto set_itr_now;
2807 }
2808
2809 adapter->tx_itr = e1000_update_itr(adapter,
2810 adapter->tx_itr,
2811 adapter->total_tx_packets,
2812 adapter->total_tx_bytes);
2b65326e
JB		 2813 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2814 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2815 adapter->tx_itr = low_latency;
2816
835bb129
JB		 2817 adapter->rx_itr = e1000_update_itr(adapter,
2818 adapter->rx_itr,
2819 adapter->total_rx_packets,
2820 adapter->total_rx_bytes);
2b65326e
JB		 2821 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2822 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2823 adapter->rx_itr = low_latency;
835bb129
JB		 2824
2825 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2826
835bb129
JB		 2827 switch (current_itr) {
2828 /* counts and packets in update_itr are dependent on these numbers */
2829 case lowest_latency:
2830 new_itr = 70000;
2831 break;
2832 case low_latency:
2833 new_itr = 20000; /* aka hwitr = ~200 */
2834 break;
2835 case bulk_latency:
2836 new_itr = 4000;
2837 break;
2838 default:
2839 break;
2840 }
2841
2842set_itr_now:
2843 if (new_itr != adapter->itr) {
2844 /* this attempts to bias the interrupt rate towards Bulk
2845 * by adding intermediate steps when interrupt rate is
2846 * increasing */
2847 new_itr = new_itr > adapter->itr ?
2848 min(adapter->itr + (new_itr >> 2), new_itr) :
2849 new_itr;
2850 adapter->itr = new_itr;
2851 E1000_WRITE_REG(hw, ITR, 1000000000 / (new_itr * 256));
2852 }
2853
2854 return;
2855}
2856
1da177e4
LT		 2857#define E1000_TX_FLAGS_CSUM 0x00000001
2858#define E1000_TX_FLAGS_VLAN 0x00000002
2859#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2860#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2861#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2862#define E1000_TX_FLAGS_VLAN_SHIFT 16
2863
e619d523 2864static int
581d708e
MC		 2865e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2866 struct sk_buff *skb)
1da177e4 2867{
1da177e4 2868 struct e1000_context_desc *context_desc;
545c67c0 2869 struct e1000_buffer *buffer_info;
1da177e4
LT		 2870 unsigned int i;
2871 uint32_t cmd_length = 0;
2d7edb92 2872 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2873 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2874 int err;
2875
89114afd 2876 if (skb_is_gso(skb)) {
1da177e4
LT		 2877 if (skb_header_cloned(skb)) {
2878 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2879 if (err)
2880 return err;
2881 }
2882
ab6a5bb6 2883 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
7967168c 2884 mss = skb_shinfo(skb)->gso_size;
60828236 2885 if (skb->protocol == htons(ETH_P_IP)) {
eddc9ec5
ACM		 2886 struct iphdr *iph = ip_hdr(skb);
2887 iph->tot_len = 0;
2888 iph->check = 0;
aa8223c7
ACM		 2889 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2890 iph->daddr, 0,
2891 IPPROTO_TCP,
2892 0);
2d7edb92 2893 cmd_length = E1000_TXD_CMD_IP;
ea2ae17d 2894 ipcse = skb_transport_offset(skb) - 1;
e15fdd03 2895 } else if (skb->protocol == htons(ETH_P_IPV6)) {
0660e03f 2896 ipv6_hdr(skb)->payload_len = 0;
aa8223c7 2897 tcp_hdr(skb)->check =
0660e03f
ACM		 2898 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2899 &ipv6_hdr(skb)->daddr,
2900 0, IPPROTO_TCP, 0);
2d7edb92 2901 ipcse = 0;
2d7edb92 2902 }
bbe735e4 2903 ipcss = skb_network_offset(skb);
eddc9ec5 2904 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
ea2ae17d 2905 tucss = skb_transport_offset(skb);
aa8223c7 2906 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
1da177e4
LT		 2907 tucse = 0;
2908
2909 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2910 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2911
581d708e
MC		 2912 i = tx_ring->next_to_use;
2913 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2914 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2915
2916 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2917 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2918 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2919 context_desc->upper_setup.tcp_fields.tucss = tucss;
2920 context_desc->upper_setup.tcp_fields.tucso = tucso;
2921 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2922 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2923 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2924 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2925
545c67c0 2926 buffer_info->time_stamp = jiffies;
a9ebadd6 2927 buffer_info->next_to_watch = i;
545c67c0 2928
581d708e
MC		 2929 if (++i == tx_ring->count) i = 0;
2930 tx_ring->next_to_use = i;
1da177e4 2931
8241e35e 2932 return TRUE;
1da177e4 2933 }
8241e35e 2934 return FALSE;
1da177e4
LT		 2935}
2936
e619d523 2937static boolean_t
581d708e
MC		 2938e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2939 struct sk_buff *skb)
1da177e4
LT		 2940{
2941 struct e1000_context_desc *context_desc;
545c67c0 2942 struct e1000_buffer *buffer_info;
1da177e4
LT		 2943 unsigned int i;
2944 uint8_t css;
2945
84fa7933 2946 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2947 css = skb_transport_offset(skb);
1da177e4 2948
581d708e 2949 i = tx_ring->next_to_use;
545c67c0 2950 buffer_info = &tx_ring->buffer_info[i];
581d708e 2951 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4 2952
f6c57baf 2953 context_desc->lower_setup.ip_config = 0;
1da177e4 2954 context_desc->upper_setup.tcp_fields.tucss = css;
628592cc
HX		 2955 context_desc->upper_setup.tcp_fields.tucso =
2956 css + skb->csum_offset;
1da177e4
LT		 2957 context_desc->upper_setup.tcp_fields.tucse = 0;
2958 context_desc->tcp_seg_setup.data = 0;
2959 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2960
545c67c0 2961 buffer_info->time_stamp = jiffies;
a9ebadd6 2962 buffer_info->next_to_watch = i;
545c67c0 2963
581d708e
MC		 2964 if (unlikely(++i == tx_ring->count)) i = 0;
2965 tx_ring->next_to_use = i;
1da177e4
LT		 2966
2967 return TRUE;
2968 }
2969
2970 return FALSE;
2971}
2972
2973#define E1000_MAX_TXD_PWR 12
2974#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2975
e619d523 2976static int
581d708e
MC		 2977e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2978 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2979 unsigned int nr_frags, unsigned int mss)
1da177e4 2980{
1da177e4
LT		 2981 struct e1000_buffer *buffer_info;
2982 unsigned int len = skb->len;
2983 unsigned int offset = 0, size, count = 0, i;
2984 unsigned int f;
2985 len -= skb->data_len;
2986
2987 i = tx_ring->next_to_use;
2988
96838a40 2989 while (len) {
1da177e4
LT		 2990 buffer_info = &tx_ring->buffer_info[i];
2991 size = min(len, max_per_txd);
fd803241
JK		 2992 /* Workaround for Controller erratum --
2993 * descriptor for non-tso packet in a linear SKB that follows a
2994 * tso gets written back prematurely before the data is fully
0f15a8fa 2995 * DMA'd to the controller */
fd803241 2996 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 2997 !skb_is_gso(skb)) {
fd803241
JK		 2998 tx_ring->last_tx_tso = 0;
2999 size -= 4;
3000 }
3001
1da177e4
LT		 3002 /* Workaround for premature desc write-backs
3003 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3004 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4 3005 size -= 4;
97338bde
MC		 3006 /* work-around for errata 10 and it applies
3007 * to all controllers in PCI-X mode
3008 * The fix is to make sure that the first descriptor of a
3009 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
3010 */
96838a40 3011 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3012 (size > 2015) && count == 0))
3013 size = 2015;
96838a40 3014
1da177e4
LT		 3015 /* Workaround for potential 82544 hang in PCI-X. Avoid
3016 * terminating buffers within evenly-aligned dwords. */
96838a40 3017 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3018 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
3019 size > 4))
3020 size -= 4;
3021
3022 buffer_info->length = size;
3023 buffer_info->dma =
3024 pci_map_single(adapter->pdev,
3025 skb->data + offset,
3026 size,
3027 PCI_DMA_TODEVICE);
3028 buffer_info->time_stamp = jiffies;
a9ebadd6 3029 buffer_info->next_to_watch = i;
1da177e4
LT		 3030
3031 len -= size;
3032 offset += size;
3033 count++;
96838a40 3034 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3035 }
3036
96838a40 3037 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 3038 struct skb_frag_struct *frag;
3039
3040 frag = &skb_shinfo(skb)->frags[f];
3041 len = frag->size;
3042 offset = frag->page_offset;
3043
96838a40 3044 while (len) {
1da177e4
LT		 3045 buffer_info = &tx_ring->buffer_info[i];
3046 size = min(len, max_per_txd);
1da177e4
LT		 3047 /* Workaround for premature desc write-backs
3048 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3049 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4 3050 size -= 4;
1da177e4
LT		 3051 /* Workaround for potential 82544 hang in PCI-X.
3052 * Avoid terminating buffers within evenly-aligned
3053 * dwords. */
96838a40 3054 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3055 !((unsigned long)(frag->page+offset+size-1) & 4) &&
3056 size > 4))
3057 size -= 4;
3058
3059 buffer_info->length = size;
3060 buffer_info->dma =
3061 pci_map_page(adapter->pdev,
3062 frag->page,
3063 offset,
3064 size,
3065 PCI_DMA_TODEVICE);
3066 buffer_info->time_stamp = jiffies;
a9ebadd6 3067 buffer_info->next_to_watch = i;
1da177e4
LT		 3068
3069 len -= size;
3070 offset += size;
3071 count++;
96838a40 3072 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3073 }
3074 }
3075
3076 i = (i == 0) ? tx_ring->count - 1 : i - 1;
3077 tx_ring->buffer_info[i].skb = skb;
3078 tx_ring->buffer_info[first].next_to_watch = i;
3079
3080 return count;
3081}
3082
e619d523 3083static void
581d708e
MC		 3084e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3085 int tx_flags, int count)
1da177e4 3086{
1da177e4
LT		 3087 struct e1000_tx_desc *tx_desc = NULL;
3088 struct e1000_buffer *buffer_info;
3089 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
3090 unsigned int i;
3091
96838a40 3092 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 3093 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
3094 E1000_TXD_CMD_TSE;
2d7edb92
MC		 3095 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3096
96838a40 3097 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 3098 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 3099 }
3100
96838a40 3101 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 3102 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
3103 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3104 }
3105
96838a40 3106 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 3107 txd_lower |= E1000_TXD_CMD_VLE;
3108 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
3109 }
3110
3111 i = tx_ring->next_to_use;
3112
96838a40 3113 while (count--) {
1da177e4
LT		 3114 buffer_info = &tx_ring->buffer_info[i];
3115 tx_desc = E1000_TX_DESC(*tx_ring, i);
3116 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3117 tx_desc->lower.data =
3118 cpu_to_le32(txd_lower | buffer_info->length);
3119 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 3120 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3121 }
3122
3123 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
3124
3125 /* Force memory writes to complete before letting h/w
3126 * know there are new descriptors to fetch. (Only
3127 * applicable for weak-ordered memory model archs,
3128 * such as IA-64). */
3129 wmb();
3130
3131 tx_ring->next_to_use = i;
581d708e 3132 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
2ce9047f
JB		 3133 /* we need this if more than one processor can write to our tail
3134 * at a time, it syncronizes IO on IA64/Altix systems */
3135 mmiowb();
1da177e4
LT		 3136}
3137
3138/**
3139 * 82547 workaround to avoid controller hang in half-duplex environment.
3140 * The workaround is to avoid queuing a large packet that would span
3141 * the internal Tx FIFO ring boundary by notifying the stack to resend
3142 * the packet at a later time. This gives the Tx FIFO an opportunity to
3143 * flush all packets. When that occurs, we reset the Tx FIFO pointers
3144 * to the beginning of the Tx FIFO.
3145 **/
3146
3147#define E1000_FIFO_HDR 0x10
3148#define E1000_82547_PAD_LEN 0x3E0
3149
e619d523 3150static int
1da177e4
LT		 3151e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
3152{
3153 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
3154 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
3155
9099cfb9 3156 skb_fifo_len = ALIGN(skb_fifo_len, E1000_FIFO_HDR);
1da177e4 3157
96838a40 3158 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 3159 goto no_fifo_stall_required;
3160
96838a40 3161 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 3162 return 1;
3163
96838a40 3164 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 3165 atomic_set(&adapter->tx_fifo_stall, 1);
3166 return 1;
3167 }
3168
3169no_fifo_stall_required:
3170 adapter->tx_fifo_head += skb_fifo_len;
96838a40 3171 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 3172 adapter->tx_fifo_head -= adapter->tx_fifo_size;
3173 return 0;
3174}
3175
2d7edb92 3176#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 3177static int
2d7edb92
MC		 3178e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
3179{
3180 struct e1000_hw *hw = &adapter->hw;
3181 uint16_t length, offset;
96838a40
JB		 3182 if (vlan_tx_tag_present(skb)) {
3183 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 3184 ( adapter->hw.mng_cookie.status &
3185 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
3186 return 0;
3187 }
20a44028 3188 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 3189 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 3190 if ((htons(ETH_P_IP) == eth->h_proto)) {
3191 const struct iphdr *ip =
2d7edb92 3192 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 3193 if (IPPROTO_UDP == ip->protocol) {
3194 struct udphdr *udp =
3195 (struct udphdr *)((uint8_t *)ip +
2d7edb92 3196 (ip->ihl << 2));
96838a40 3197 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 3198 offset = (uint8_t *)udp + 8 - skb->data;
3199 length = skb->len - offset;
3200
3201 return e1000_mng_write_dhcp_info(hw,
96838a40 3202 (uint8_t *)udp + 8,
2d7edb92
MC		 3203 length);
3204 }
3205 }
3206 }
3207 }
3208 return 0;
3209}
3210
65c7973f
JB		 3211static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
3212{
3213 struct e1000_adapter *adapter = netdev_priv(netdev);
3214 struct e1000_tx_ring *tx_ring = adapter->tx_ring;
3215
3216 netif_stop_queue(netdev);
3217 /* Herbert's original patch had:
3218 * smp_mb__after_netif_stop_queue();
3219 * but since that doesn't exist yet, just open code it. */
3220 smp_mb();
3221
3222 /* We need to check again in a case another CPU has just
3223 * made room available. */
3224 if (likely(E1000_DESC_UNUSED(tx_ring) < size))
3225 return -EBUSY;
3226
3227 /* A reprieve! */
3228 netif_start_queue(netdev);
fcfb1224 3229 ++adapter->restart_queue;
65c7973f
JB		 3230 return 0;
3231}
3232
3233static int e1000_maybe_stop_tx(struct net_device *netdev,
3234 struct e1000_tx_ring *tx_ring, int size)
3235{
3236 if (likely(E1000_DESC_UNUSED(tx_ring) >= size))
3237 return 0;
3238 return __e1000_maybe_stop_tx(netdev, size);
3239}
3240
1da177e4
LT		 3241#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3242static int
3243e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3244{
60490fe0 3245 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 3246 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 3247 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
3248 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
3249 unsigned int tx_flags = 0;
6d1e3aa7 3250 unsigned int len = skb->len - skb->data_len;
1da177e4 3251 unsigned long flags;
6d1e3aa7
KK		 3252 unsigned int nr_frags;
3253 unsigned int mss;
1da177e4 3254 int count = 0;
76c224bc 3255 int tso;
1da177e4 3256 unsigned int f;
1da177e4 3257
65c7973f
JB		 3258 /* This goes back to the question of how to logically map a tx queue
3259 * to a flow. Right now, performance is impacted slightly negatively
3260 * if using multiple tx queues. If the stack breaks away from a
3261 * single qdisc implementation, we can look at this again. */
581d708e 3262 tx_ring = adapter->tx_ring;
24025e4e 3263
581d708e 3264 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 3265 dev_kfree_skb_any(skb);
3266 return NETDEV_TX_OK;
3267 }
3268
032fe6e9
JB		 3269 /* 82571 and newer doesn't need the workaround that limited descriptor
3270 * length to 4kB */
3271 if (adapter->hw.mac_type >= e1000_82571)
3272 max_per_txd = 8192;
3273
7967168c 3274 mss = skb_shinfo(skb)->gso_size;
76c224bc 3275 /* The controller does a simple calculation to
1da177e4
LT		 3276 * make sure there is enough room in the FIFO before
3277 * initiating the DMA for each buffer. The calc is:
3278 * 4 = ceil(buffer len/mss). To make sure we don't
3279 * overrun the FIFO, adjust the max buffer len if mss
3280 * drops. */
96838a40 3281 if (mss) {
9a3056da 3282 uint8_t hdr_len;
1da177e4
LT		 3283 max_per_txd = min(mss << 2, max_per_txd);
3284 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 3285
90fb5135
AK		 3286 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
3287 * points to just header, pull a few bytes of payload from
3288 * frags into skb->data */
ab6a5bb6 3289 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
6d1e3aa7 3290 if (skb->data_len && hdr_len == len) {
9f687888
JK		 3291 switch (adapter->hw.mac_type) {
3292 unsigned int pull_size;
683a2aa3
HX		 3293 case e1000_82544:
3294 /* Make sure we have room to chop off 4 bytes,
3295 * and that the end alignment will work out to
3296 * this hardware's requirements
3297 * NOTE: this is a TSO only workaround
3298 * if end byte alignment not correct move us
3299 * into the next dword */
27a884dc 3300 if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4)
683a2aa3
HX		 3301 break;
3302 /* fall through */
9f687888
JK		 3303 case e1000_82571:
3304 case e1000_82572:
3305 case e1000_82573:
cd94dd0b 3306 case e1000_ich8lan:
9f687888
JK		 3307 pull_size = min((unsigned int)4, skb->data_len);
3308 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 3309 DPRINTK(DRV, ERR,
9f687888
JK		 3310 "__pskb_pull_tail failed.\n");
3311 dev_kfree_skb_any(skb);
749dfc70 3312 return NETDEV_TX_OK;
9f687888
JK		 3313 }
3314 len = skb->len - skb->data_len;
3315 break;
3316 default:
3317 /* do nothing */
3318 break;
d74bbd3b 3319 }
9a3056da 3320 }
1da177e4
LT		 3321 }
3322
9a3056da 3323 /* reserve a descriptor for the offload context */
84fa7933 3324 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
1da177e4 3325 count++;
2648345f 3326 count++;
fd803241 3327
fd803241 3328 /* Controller Erratum workaround */
89114afd 3329 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241 3330 count++;
fd803241 3331
1da177e4
LT		 3332 count += TXD_USE_COUNT(len, max_txd_pwr);
3333
96838a40 3334 if (adapter->pcix_82544)
1da177e4
LT		 3335 count++;
3336
96838a40 3337 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 3338 * in PCI-X mode, so add one more descriptor to the count
3339 */
96838a40 3340 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3341 (len > 2015)))
3342 count++;
3343
1da177e4 3344 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 3345 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 3346 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
3347 max_txd_pwr);
96838a40 3348 if (adapter->pcix_82544)
1da177e4
LT		 3349 count += nr_frags;
3350
0f15a8fa
JK		 3351
3352 if (adapter->hw.tx_pkt_filtering &&
3353 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 3354 e1000_transfer_dhcp_info(adapter, skb);
3355
f50393fe 3356 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags))
581d708e 3357 /* Collision - tell upper layer to requeue */
581d708e 3358 return NETDEV_TX_LOCKED;
1da177e4
LT		 3359
3360 /* need: count + 2 desc gap to keep tail from touching
3361 * head, otherwise try next time */
65c7973f 3362 if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) {
581d708e 3363 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3364 return NETDEV_TX_BUSY;
3365 }
3366
96838a40
JB		 3367 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
3368 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4 3369 netif_stop_queue(netdev);
1314bbf3 3370 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
581d708e 3371 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3372 return NETDEV_TX_BUSY;
3373 }
3374 }
3375
96838a40 3376 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 3377 tx_flags |= E1000_TX_FLAGS_VLAN;
3378 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
3379 }
3380
581d708e 3381 first = tx_ring->next_to_use;
96838a40 3382
581d708e 3383 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 3384 if (tso < 0) {
3385 dev_kfree_skb_any(skb);
581d708e 3386 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3387 return NETDEV_TX_OK;
3388 }
3389
fd803241
JK		 3390 if (likely(tso)) {
3391 tx_ring->last_tx_tso = 1;
1da177e4 3392 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3393 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3394 tx_flags |= E1000_TX_FLAGS_CSUM;
3395
2d7edb92 3396 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3397 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3398 * no longer assume, we must. */
60828236 3399 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3400 tx_flags |= E1000_TX_FLAGS_IPV4;
3401
581d708e
MC		 3402 e1000_tx_queue(adapter, tx_ring, tx_flags,
3403 e1000_tx_map(adapter, tx_ring, skb, first,
3404 max_per_txd, nr_frags, mss));
1da177e4
LT		 3405
3406 netdev->trans_start = jiffies;
3407
3408 /* Make sure there is space in the ring for the next send. */
65c7973f 3409 e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
1da177e4 3410
581d708e 3411 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3412 return NETDEV_TX_OK;
3413}
3414
3415/**
3416 * e1000_tx_timeout - Respond to a Tx Hang
3417 * @netdev: network interface device structure
3418 **/
3419
3420static void
3421e1000_tx_timeout(struct net_device *netdev)
3422{
60490fe0 3423 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3424
3425 /* Do the reset outside of interrupt context */
87041639
JK		 3426 adapter->tx_timeout_count++;
3427 schedule_work(&adapter->reset_task);
1da177e4
LT		 3428}
3429
3430static void
65f27f38 3431e1000_reset_task(struct work_struct *work)
1da177e4 3432{
65f27f38
DH		 3433 struct e1000_adapter *adapter =
3434 container_of(work, struct e1000_adapter, reset_task);
1da177e4 3435
2db10a08 3436 e1000_reinit_locked(adapter);
1da177e4
LT		 3437}
3438
3439/**
3440 * e1000_get_stats - Get System Network Statistics
3441 * @netdev: network interface device structure
3442 *
3443 * Returns the address of the device statistics structure.
3444 * The statistics are actually updated from the timer callback.
3445 **/
3446
3447static struct net_device_stats *
3448e1000_get_stats(struct net_device *netdev)
3449{
60490fe0 3450 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3451
6b7660cd 3452 /* only return the current stats */
1da177e4
LT		 3453 return &adapter->net_stats;
3454}
3455
3456/**
3457 * e1000_change_mtu - Change the Maximum Transfer Unit
3458 * @netdev: network interface device structure
3459 * @new_mtu: new value for maximum frame size
3460 *
3461 * Returns 0 on success, negative on failure
3462 **/
3463
3464static int
3465e1000_change_mtu(struct net_device *netdev, int new_mtu)
3466{
60490fe0 3467 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3468 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 3469 uint16_t eeprom_data = 0;
1da177e4 3470
96838a40
JB		 3471 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3472 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3473 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3474 return -EINVAL;
2d7edb92 3475 }
1da177e4 3476
997f5cbd
JK		 3477 /* Adapter-specific max frame size limits. */
3478 switch (adapter->hw.mac_type) {
9e2feace 3479 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3480 case e1000_ich8lan:
997f5cbd
JK		 3481 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3482 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3483 return -EINVAL;
2d7edb92 3484 }
997f5cbd 3485 break;
85b22eb6 3486 case e1000_82573:
249d71d6
BA		 3487 /* Jumbo Frames not supported if:
3488 * - this is not an 82573L device
3489 * - ASPM is enabled in any way (0x1A bits 3:2) */
85b22eb6
JK		 3490 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3491 &eeprom_data);
249d71d6
BA		 3492 if ((adapter->hw.device_id != E1000_DEV_ID_82573L) ||
3493 (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) {
85b22eb6
JK		 3494 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3495 DPRINTK(PROBE, ERR,
3496 "Jumbo Frames not supported.\n");
3497 return -EINVAL;
3498 }
3499 break;
3500 }
249d71d6
BA		 3501 /* ERT will be enabled later to enable wire speed receives */
3502
85b22eb6 3503 /* fall through to get support */
997f5cbd
JK		 3504 case e1000_82571:
3505 case e1000_82572:
87041639 3506 case e1000_80003es2lan:
997f5cbd
JK		 3507#define MAX_STD_JUMBO_FRAME_SIZE 9234
3508 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3509 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3510 return -EINVAL;
3511 }
3512 break;
3513 default:
3514 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3515 break;
1da177e4
LT		 3516 }
3517
87f5032e 3518 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3519 * means we reserve 2 more, this pushes us to allocate from the next
3520 * larger slab size
3521 * i.e. RXBUFFER_2048 --> size-4096 slab */
3522
3523 if (max_frame <= E1000_RXBUFFER_256)
3524 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3525 else if (max_frame <= E1000_RXBUFFER_512)
3526 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3527 else if (max_frame <= E1000_RXBUFFER_1024)
3528 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3529 else if (max_frame <= E1000_RXBUFFER_2048)
3530 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3531 else if (max_frame <= E1000_RXBUFFER_4096)
3532 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3533 else if (max_frame <= E1000_RXBUFFER_8192)
3534 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3535 else if (max_frame <= E1000_RXBUFFER_16384)
3536 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3537
3538 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3539 if (!adapter->hw.tbi_compatibility_on &&
3540 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3541 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3542 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3543
2d7edb92 3544 netdev->mtu = new_mtu;
83cd8279 3545 adapter->hw.max_frame_size = max_frame;
2d7edb92 3546
2db10a08
AK		 3547 if (netif_running(netdev))
3548 e1000_reinit_locked(adapter);
1da177e4 3549
1da177e4
LT		 3550 return 0;
3551}
3552
3553/**
3554 * e1000_update_stats - Update the board statistics counters
3555 * @adapter: board private structure
3556 **/
3557
3558void
3559e1000_update_stats(struct e1000_adapter *adapter)
3560{
3561 struct e1000_hw *hw = &adapter->hw;
282f33c9 3562 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3563 unsigned long flags;
3564 uint16_t phy_tmp;
3565
3566#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3567
282f33c9
LV		 3568 /*
3569 * Prevent stats update while adapter is being reset, or if the pci
3570 * connection is down.
3571 */
9026729b 3572 if (adapter->link_speed == 0)
282f33c9 3573 return;
81b1955e 3574 if (pci_channel_offline(pdev))
9026729b
AK		 3575 return;
3576
1da177e4
LT		 3577 spin_lock_irqsave(&adapter->stats_lock, flags);
3578
828d055f 3579 /* these counters are modified from e1000_tbi_adjust_stats,
1da177e4
LT		 3580 * called from the interrupt context, so they must only
3581 * be written while holding adapter->stats_lock
3582 */
3583
3584 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3585 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3586 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3587 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3588 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3589 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3590 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3591
3592 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3593 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3594 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3595 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3596 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3597 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3598 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3599 }
1da177e4
LT		 3600
3601 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3602 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3603 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3604 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3605 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3606 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3607 adapter->stats.dc += E1000_READ_REG(hw, DC);
3608 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3609 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3610 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3611 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3612 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3613 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3614 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3615 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3616 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3617 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3618 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3619 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3620 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3621 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3622 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3623 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3624 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3625 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3626 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3627
3628 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3629 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3630 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3631 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3632 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3633 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3634 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3635 }
3636
1da177e4
LT		 3637 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3638 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3639
3640 /* used for adaptive IFS */
3641
3642 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3643 adapter->stats.tpt += hw->tx_packet_delta;
3644 hw->collision_delta = E1000_READ_REG(hw, COLC);
3645 adapter->stats.colc += hw->collision_delta;
3646
96838a40 3647 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3648 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3649 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3650 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3651 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3652 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3653 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3654 }
96838a40 3655 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3656 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3657 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3658
3659 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3660 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3661 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3662 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3663 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3664 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3665 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3666 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3667 }
2d7edb92 3668 }
1da177e4
LT		 3669
3670 /* Fill out the OS statistics structure */
1da177e4
LT		 3671 adapter->net_stats.multicast = adapter->stats.mprc;
3672 adapter->net_stats.collisions = adapter->stats.colc;
3673
3674 /* Rx Errors */
3675
87041639
JK		 3676 /* RLEC on some newer hardware can be incorrect so build
3677 * our own version based on RUC and ROC */
1da177e4
LT		 3678 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3679 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3680 adapter->stats.ruc + adapter->stats.roc +
3681 adapter->stats.cexterr;
49559854
MW		 3682 adapter->stats.rlerrc = adapter->stats.ruc + adapter->stats.roc;
3683 adapter->net_stats.rx_length_errors = adapter->stats.rlerrc;
1da177e4
LT		 3684 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3685 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3686 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3687
3688 /* Tx Errors */
49559854
MW		 3689 adapter->stats.txerrc = adapter->stats.ecol + adapter->stats.latecol;
3690 adapter->net_stats.tx_errors = adapter->stats.txerrc;
1da177e4
LT		 3691 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3692 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3693 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
167fb284
JG		 3694 if (adapter->hw.bad_tx_carr_stats_fd &&
3695 adapter->link_duplex == FULL_DUPLEX) {
3696 adapter->net_stats.tx_carrier_errors = 0;
3697 adapter->stats.tncrs = 0;
3698 }
1da177e4
LT		 3699
3700 /* Tx Dropped needs to be maintained elsewhere */
3701
3702 /* Phy Stats */
96838a40
JB		 3703 if (hw->media_type == e1000_media_type_copper) {
3704 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3705 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3706 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3707 adapter->phy_stats.idle_errors += phy_tmp;
3708 }
3709
96838a40 3710 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3711 (hw->phy_type == e1000_phy_m88) &&
3712 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3713 adapter->phy_stats.receive_errors += phy_tmp;
3714 }
3715
15e376b4
JG		 3716 /* Management Stats */
3717 if (adapter->hw.has_smbus) {
3718 adapter->stats.mgptc += E1000_READ_REG(hw, MGTPTC);
3719 adapter->stats.mgprc += E1000_READ_REG(hw, MGTPRC);
3720 adapter->stats.mgpdc += E1000_READ_REG(hw, MGTPDC);
3721 }
3722
1da177e4
LT		 3723 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3724}
9ac98284
JB		 3725
3726/**
3727 * e1000_intr_msi - Interrupt Handler
3728 * @irq: interrupt number
3729 * @data: pointer to a network interface device structure
3730 **/
3731
b5fc8f0c
JB		 3732static irqreturn_t
3733e1000_intr_msi(int irq, void *data)
9ac98284
JB		 3734{
3735 struct net_device *netdev = data;
3736 struct e1000_adapter *adapter = netdev_priv(netdev);
3737 struct e1000_hw *hw = &adapter->hw;
3738#ifndef CONFIG_E1000_NAPI
3739 int i;
3740#endif
b5fc8f0c 3741 uint32_t icr = E1000_READ_REG(hw, ICR);
9ac98284 3742
9ac98284 3743#ifdef CONFIG_E1000_NAPI
b5fc8f0c
JB		 3744 /* read ICR disables interrupts using IAM, so keep up with our
3745 * enable/disable accounting */
3746 atomic_inc(&adapter->irq_sem);
9ac98284 3747#endif
b5fc8f0c
JB		 3748 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3749 hw->get_link_status = 1;
3750 /* 80003ES2LAN workaround-- For packet buffer work-around on
3751 * link down event; disable receives here in the ISR and reset
3752 * adapter in watchdog */
3753 if (netif_carrier_ok(netdev) &&
3754 (adapter->hw.mac_type == e1000_80003es2lan)) {
3755 /* disable receives */
3756 uint32_t rctl = E1000_READ_REG(hw, RCTL);
3757 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
9ac98284 3758 }
b5fc8f0c
JB		 3759 /* guard against interrupt when we're going down */
3760 if (!test_bit(__E1000_DOWN, &adapter->flags))
3761 mod_timer(&adapter->watchdog_timer, jiffies + 1);
9ac98284
JB		 3762 }
3763
3764#ifdef CONFIG_E1000_NAPI
bea3348e 3765 if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
835bb129
JB		 3766 adapter->total_tx_bytes = 0;
3767 adapter->total_tx_packets = 0;
3768 adapter->total_rx_bytes = 0;
3769 adapter->total_rx_packets = 0;
bea3348e 3770 __netif_rx_schedule(netdev, &adapter->napi);
835bb129 3771 } else
9ac98284
JB		 3772 e1000_irq_enable(adapter);
3773#else
835bb129
JB		 3774 adapter->total_tx_bytes = 0;
3775 adapter->total_rx_bytes = 0;
3776 adapter->total_tx_packets = 0;
3777 adapter->total_rx_packets = 0;
3778
9ac98284
JB		 3779 for (i = 0; i < E1000_MAX_INTR; i++)
3780 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3781 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
9ac98284 3782 break;
835bb129
JB		 3783
3784 if (likely(adapter->itr_setting & 3))
3785 e1000_set_itr(adapter);
9ac98284
JB		 3786#endif
3787
3788 return IRQ_HANDLED;
3789}
1da177e4
LT		 3790
3791/**
3792 * e1000_intr - Interrupt Handler
3793 * @irq: interrupt number
3794 * @data: pointer to a network interface device structure
1da177e4
LT		 3795 **/
3796
3797static irqreturn_t
7d12e780 3798e1000_intr(int irq, void *data)
1da177e4
LT		 3799{
3800 struct net_device *netdev = data;
60490fe0 3801 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3802 struct e1000_hw *hw = &adapter->hw;
87041639 3803 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3804#ifndef CONFIG_E1000_NAPI
581d708e 3805 int i;
835bb129
JB		 3806#endif
3807 if (unlikely(!icr))
3808 return IRQ_NONE; /* Not our interrupt */
3809
3810#ifdef CONFIG_E1000_NAPI
3811 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3812 * not set, then the adapter didn't send an interrupt */
3813 if (unlikely(hw->mac_type >= e1000_82571 &&
3814 !(icr & E1000_ICR_INT_ASSERTED)))
3815 return IRQ_NONE;
3816
1e613fd9
JK		 3817 /* Interrupt Auto-Mask...upon reading ICR,
3818 * interrupts are masked. No need for the
3819 * IMC write, but it does mean we should
3820 * account for it ASAP. */
3821 if (likely(hw->mac_type >= e1000_82571))
3822 atomic_inc(&adapter->irq_sem);
be2b28ed 3823#endif
1da177e4 3824
96838a40 3825 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3826 hw->get_link_status = 1;
87041639
JK		 3827 /* 80003ES2LAN workaround--
3828 * For packet buffer work-around on link down event;
3829 * disable receives here in the ISR and
3830 * reset adapter in watchdog
3831 */
3832 if (netif_carrier_ok(netdev) &&
3833 (adapter->hw.mac_type == e1000_80003es2lan)) {
3834 /* disable receives */
3835 rctl = E1000_READ_REG(hw, RCTL);
3836 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3837 }
1314bbf3
AK		 3838 /* guard against interrupt when we're going down */
3839 if (!test_bit(__E1000_DOWN, &adapter->flags))
3840 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1da177e4
LT		 3841 }
3842
3843#ifdef CONFIG_E1000_NAPI
1e613fd9 3844 if (unlikely(hw->mac_type < e1000_82571)) {
835bb129 3845 /* disable interrupts, without the synchronize_irq bit */
1e613fd9
JK		 3846 atomic_inc(&adapter->irq_sem);
3847 E1000_WRITE_REG(hw, IMC, ~0);
3848 E1000_WRITE_FLUSH(hw);
3849 }
bea3348e 3850 if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
835bb129
JB		 3851 adapter->total_tx_bytes = 0;
3852 adapter->total_tx_packets = 0;
3853 adapter->total_rx_bytes = 0;
3854 adapter->total_rx_packets = 0;
bea3348e 3855 __netif_rx_schedule(netdev, &adapter->napi);
835bb129 3856 } else
90fb5135
AK		 3857 /* this really should not happen! if it does it is basically a
3858 * bug, but not a hard error, so enable ints and continue */
581d708e 3859 e1000_irq_enable(adapter);
c1605eb3 3860#else
1da177e4 3861 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3862 * Due to Hub Link bus being occupied, an interrupt
3863 * de-assertion message is not able to be sent.
3864 * When an interrupt assertion message is generated later,
3865 * two messages are re-ordered and sent out.
3866 * That causes APIC to think 82547 is in de-assertion
3867 * state, while 82547 is in assertion state, resulting
3868 * in dead lock. Writing IMC forces 82547 into
3869 * de-assertion state.
3870 */
3871 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3872 atomic_inc(&adapter->irq_sem);
2648345f 3873 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3874 }
3875
835bb129
JB		 3876 adapter->total_tx_bytes = 0;
3877 adapter->total_rx_bytes = 0;
3878 adapter->total_tx_packets = 0;
3879 adapter->total_rx_packets = 0;
3880
96838a40
JB		 3881 for (i = 0; i < E1000_MAX_INTR; i++)
3882 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3883 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3884 break;
3885
835bb129
JB		 3886 if (likely(adapter->itr_setting & 3))
3887 e1000_set_itr(adapter);
3888
96838a40 3889 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3890 e1000_irq_enable(adapter);
581d708e 3891
c1605eb3 3892#endif
1da177e4
LT		 3893 return IRQ_HANDLED;
3894}
3895
3896#ifdef CONFIG_E1000_NAPI
3897/**
3898 * e1000_clean - NAPI Rx polling callback
3899 * @adapter: board private structure
3900 **/
3901
3902static int
bea3348e 3903e1000_clean(struct napi_struct *napi, int budget)
1da177e4 3904{
bea3348e
SH		 3905 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
3906 struct net_device *poll_dev = adapter->netdev;
d2c7ddd6 3907 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3908
3909 /* Must NOT use netdev_priv macro here. */
3910 adapter = poll_dev->priv;
3911
d3d9e484
AK		 3912 /* e1000_clean is called per-cpu. This lock protects
3913 * tx_ring[0] from being cleaned by multiple cpus
3914 * simultaneously. A failure obtaining the lock means
3915 * tx_ring[0] is currently being cleaned anyway. */
3916 if (spin_trylock(&adapter->tx_queue_lock)) {
d2c7ddd6
DM		 3917 tx_cleaned = e1000_clean_tx_irq(adapter,
3918 &adapter->tx_ring[0]);
d3d9e484 3919 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3920 }
3921
d3d9e484 3922 adapter->clean_rx(adapter, &adapter->rx_ring[0],
bea3348e 3923 &work_done, budget);
96838a40 3924
d2c7ddd6
DM		 3925 if (tx_cleaned)
3926 work_done = budget;
3927
53e52c72
DM		 3928 /* If budget not fully consumed, exit the polling mode */
3929 if (work_done < budget) {
835bb129
JB		 3930 if (likely(adapter->itr_setting & 3))
3931 e1000_set_itr(adapter);
bea3348e 3932 netif_rx_complete(poll_dev, napi);
1da177e4 3933 e1000_irq_enable(adapter);
1da177e4
LT		 3934 }
3935
bea3348e 3936 return work_done;
1da177e4
LT		 3937}
3938
3939#endif
3940/**
3941 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3942 * @adapter: board private structure
3943 **/
3944
3945static boolean_t
581d708e
MC		 3946e1000_clean_tx_irq(struct e1000_adapter *adapter,
3947 struct e1000_tx_ring *tx_ring)
1da177e4 3948{
1da177e4
LT		 3949 struct net_device *netdev = adapter->netdev;
3950 struct e1000_tx_desc *tx_desc, *eop_desc;
3951 struct e1000_buffer *buffer_info;
3952 unsigned int i, eop;
2a1af5d7
JK		 3953#ifdef CONFIG_E1000_NAPI
3954 unsigned int count = 0;
3955#endif
46fcc86d 3956 boolean_t cleaned = FALSE;
835bb129 3957 unsigned int total_tx_bytes=0, total_tx_packets=0;
1da177e4
LT		 3958
3959 i = tx_ring->next_to_clean;
3960 eop = tx_ring->buffer_info[i].next_to_watch;
3961 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3962
581d708e 3963 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3964 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3965 tx_desc = E1000_TX_DESC(*tx_ring, i);
3966 buffer_info = &tx_ring->buffer_info[i];
3967 cleaned = (i == eop);
3968
835bb129 3969 if (cleaned) {
2b65326e 3970 struct sk_buff *skb = buffer_info->skb;
7753b171
JB		 3971 unsigned int segs, bytecount;
3972 segs = skb_shinfo(skb)->gso_segs ?: 1;
3973 /* multiply data chunks by size of headers */
3974 bytecount = ((segs - 1) * skb_headlen(skb)) +
3975 skb->len;
2b65326e 3976 total_tx_packets += segs;
7753b171 3977 total_tx_bytes += bytecount;
835bb129 3978 }
fd803241 3979 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
a9ebadd6 3980 tx_desc->upper.data = 0;
1da177e4 3981
96838a40 3982 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 3983 }
581d708e 3984
1da177e4
LT		 3985 eop = tx_ring->buffer_info[i].next_to_watch;
3986 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 3987#ifdef CONFIG_E1000_NAPI
3988#define E1000_TX_WEIGHT 64
3989 /* weight of a sort for tx, to avoid endless transmit cleanup */
46fcc86d 3990 if (count++ == E1000_TX_WEIGHT) break;
2a1af5d7 3991#endif
1da177e4
LT		 3992 }
3993
3994 tx_ring->next_to_clean = i;
3995
77b2aad5 3996#define TX_WAKE_THRESHOLD 32
65c7973f
JB		 3997 if (unlikely(cleaned && netif_carrier_ok(netdev) &&
3998 E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
3999 /* Make sure that anybody stopping the queue after this
4000 * sees the new next_to_clean.
4001 */
4002 smp_mb();
fcfb1224 4003 if (netif_queue_stopped(netdev)) {
77b2aad5 4004 netif_wake_queue(netdev);
fcfb1224
JB		 4005 ++adapter->restart_queue;
4006 }
77b2aad5 4007 }
2648345f 4008
581d708e 4009 if (adapter->detect_tx_hung) {
2648345f 4010 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 4011 * check with the clearing of time_stamp and movement of i */
4012 adapter->detect_tx_hung = FALSE;
392137fa
JK		 4013 if (tx_ring->buffer_info[eop].dma &&
4014 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 4015 (adapter->tx_timeout_factor * HZ))
70b8f1e1 4016 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 4017 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 4018
4019 /* detected Tx unit hang */
c6963ef5 4020 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 4021 " Tx Queue <%lu>\n"
70b8f1e1
MC		 4022 " TDH <%x>\n"
4023 " TDT <%x>\n"
4024 " next_to_use <%x>\n"
4025 " next_to_clean <%x>\n"
4026 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 4027 " time_stamp <%lx>\n"
4028 " next_to_watch <%x>\n"
4029 " jiffies <%lx>\n"
4030 " next_to_watch.status <%x>\n",
7bfa4816
JK		 4031 (unsigned long)((tx_ring - adapter->tx_ring) /
4032 sizeof(struct e1000_tx_ring)),
581d708e
MC		 4033 readl(adapter->hw.hw_addr + tx_ring->tdh),
4034 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 4035 tx_ring->next_to_use,
392137fa
JK		 4036 tx_ring->next_to_clean,
4037 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 4038 eop,
4039 jiffies,
4040 eop_desc->upper.fields.status);
1da177e4 4041 netif_stop_queue(netdev);
70b8f1e1 4042 }
1da177e4 4043 }
835bb129
JB		 4044 adapter->total_tx_bytes += total_tx_bytes;
4045 adapter->total_tx_packets += total_tx_packets;
ef90e4ec
AK		 4046 adapter->net_stats.tx_bytes += total_tx_bytes;
4047 adapter->net_stats.tx_packets += total_tx_packets;
1da177e4
LT		 4048 return cleaned;
4049}
4050
4051/**
4052 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 4053 * @adapter: board private structure
4054 * @status_err: receive descriptor status and error fields
4055 * @csum: receive descriptor csum field
4056 * @sk_buff: socket buffer with received data
1da177e4
LT		 4057 **/
4058
e619d523 4059static void
1da177e4 4060e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 4061 uint32_t status_err, uint32_t csum,
4062 struct sk_buff *skb)
1da177e4 4063{
2d7edb92
MC		 4064 uint16_t status = (uint16_t)status_err;
4065 uint8_t errors = (uint8_t)(status_err >> 24);
4066 skb->ip_summed = CHECKSUM_NONE;
4067
1da177e4 4068 /* 82543 or newer only */
96838a40 4069 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 4070 /* Ignore Checksum bit is set */
96838a40 4071 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 4072 /* TCP/UDP checksum error bit is set */
96838a40 4073 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 4074 /* let the stack verify checksum errors */
1da177e4 4075 adapter->hw_csum_err++;
2d7edb92
MC		 4076 return;
4077 }
4078 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 4079 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
4080 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 4081 return;
1da177e4 4082 } else {
96838a40 4083 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 4084 return;
4085 }
4086 /* It must be a TCP or UDP packet with a valid checksum */
4087 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 4088 /* TCP checksum is good */
4089 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 4090 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
4091 /* IP fragment with UDP payload */
4092 /* Hardware complements the payload checksum, so we undo it
4093 * and then put the value in host order for further stack use.
4094 */
3e18826c
AV		 4095 __sum16 sum = (__force __sum16)htons(csum);
4096 skb->csum = csum_unfold(~sum);
84fa7933 4097 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 4098 }
2d7edb92 4099 adapter->hw_csum_good++;
1da177e4
LT		 4100}
4101
4102/**
2d7edb92 4103 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 4104 * @adapter: board private structure
4105 **/
4106
4107static boolean_t
4108#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4109e1000_clean_rx_irq(struct e1000_adapter *adapter,
4110 struct e1000_rx_ring *rx_ring,
4111 int *work_done, int work_to_do)
1da177e4 4112#else
581d708e
MC		 4113e1000_clean_rx_irq(struct e1000_adapter *adapter,
4114 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 4115#endif
4116{
1da177e4
LT		 4117 struct net_device *netdev = adapter->netdev;
4118 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 4119 struct e1000_rx_desc *rx_desc, *next_rxd;
4120 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 4121 unsigned long flags;
4122 uint32_t length;
4123 uint8_t last_byte;
4124 unsigned int i;
72d64a43 4125 int cleaned_count = 0;
a1415ee6 4126 boolean_t cleaned = FALSE;
835bb129 4127 unsigned int total_rx_bytes=0, total_rx_packets=0;
1da177e4
LT		 4128
4129 i = rx_ring->next_to_clean;
4130 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 4131 buffer_info = &rx_ring->buffer_info[i];
1da177e4 4132
b92ff8ee 4133 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 4134 struct sk_buff *skb;
a292ca6e 4135 u8 status;
90fb5135 4136
1da177e4 4137#ifdef CONFIG_E1000_NAPI
96838a40 4138 if (*work_done >= work_to_do)
1da177e4
LT		 4139 break;
4140 (*work_done)++;
4141#endif
a292ca6e 4142 status = rx_desc->status;
b92ff8ee 4143 skb = buffer_info->skb;
86c3d59f
JB		 4144 buffer_info->skb = NULL;
4145
30320be8
JK		 4146 prefetch(skb->data - NET_IP_ALIGN);
4147
86c3d59f
JB		 4148 if (++i == rx_ring->count) i = 0;
4149 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 4150 prefetch(next_rxd);
4151
86c3d59f 4152 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4153
72d64a43
JK		 4154 cleaned = TRUE;
4155 cleaned_count++;
a292ca6e
JK		 4156 pci_unmap_single(pdev,
4157 buffer_info->dma,
4158 buffer_info->length,
1da177e4
LT		 4159 PCI_DMA_FROMDEVICE);
4160
1da177e4
LT		 4161 length = le16_to_cpu(rx_desc->length);
4162
a1415ee6
JK		 4163 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
4164 /* All receives must fit into a single buffer */
4165 E1000_DBG("%s: Receive packet consumed multiple"
4166 " buffers\n", netdev->name);
864c4e45 4167 /* recycle */
8fc897b0 4168 buffer_info->skb = skb;
1da177e4
LT		 4169 goto next_desc;
4170 }
4171
96838a40 4172 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 4173 last_byte = *(skb->data + length - 1);
b92ff8ee 4174 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 4175 rx_desc->errors, length, last_byte)) {
4176 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 4177 e1000_tbi_adjust_stats(&adapter->hw,
4178 &adapter->stats,
1da177e4
LT		 4179 length, skb->data);
4180 spin_unlock_irqrestore(&adapter->stats_lock,
4181 flags);
4182 length--;
4183 } else {
9e2feace
AK		 4184 /* recycle */
4185 buffer_info->skb = skb;
1da177e4
LT		 4186 goto next_desc;
4187 }
1cb5821f 4188 }
1da177e4 4189
d2a1e213
JB		 4190 /* adjust length to remove Ethernet CRC, this must be
4191 * done after the TBI_ACCEPT workaround above */
4192 length -= 4;
4193
835bb129
JB		 4194 /* probably a little skewed due to removing CRC */
4195 total_rx_bytes += length;
4196 total_rx_packets++;
4197
a292ca6e
JK		 4198 /* code added for copybreak, this should improve
4199 * performance for small packets with large amounts
4200 * of reassembly being done in the stack */
1f753861 4201 if (length < copybreak) {
a292ca6e 4202 struct sk_buff *new_skb =
87f5032e 4203 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 4204 if (new_skb) {
4205 skb_reserve(new_skb, NET_IP_ALIGN);
27d7ff46
ACM		 4206 skb_copy_to_linear_data_offset(new_skb,
4207 -NET_IP_ALIGN,
4208 (skb->data -
4209 NET_IP_ALIGN),
4210 (length +
4211 NET_IP_ALIGN));
a292ca6e
JK		 4212 /* save the skb in buffer_info as good */
4213 buffer_info->skb = skb;
4214 skb = new_skb;
a292ca6e 4215 }
996695de
AK		 4216 /* else just continue with the old one */
4217 }
a292ca6e 4218 /* end copybreak code */
996695de 4219 skb_put(skb, length);
1da177e4
LT		 4220
4221 /* Receive Checksum Offload */
a292ca6e
JK		 4222 e1000_rx_checksum(adapter,
4223 (uint32_t)(status) |
2d7edb92 4224 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 4225 le16_to_cpu(rx_desc->csum), skb);
96838a40 4226
1da177e4
LT		 4227 skb->protocol = eth_type_trans(skb, netdev);
4228#ifdef CONFIG_E1000_NAPI
96838a40 4229 if (unlikely(adapter->vlgrp &&
a292ca6e 4230 (status & E1000_RXD_STAT_VP))) {
1da177e4 4231 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 4232 le16_to_cpu(rx_desc->special) &
4233 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 4234 } else {
4235 netif_receive_skb(skb);
4236 }
4237#else /* CONFIG_E1000_NAPI */
96838a40 4238 if (unlikely(adapter->vlgrp &&
b92ff8ee 4239 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 4240 vlan_hwaccel_rx(skb, adapter->vlgrp,
4241 le16_to_cpu(rx_desc->special) &
4242 E1000_RXD_SPC_VLAN_MASK);
4243 } else {
4244 netif_rx(skb);
4245 }
4246#endif /* CONFIG_E1000_NAPI */
4247 netdev->last_rx = jiffies;
4248
4249next_desc:
4250 rx_desc->status = 0;
1da177e4 4251
72d64a43
JK		 4252 /* return some buffers to hardware, one at a time is too slow */
4253 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4254 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4255 cleaned_count = 0;
4256 }
4257
30320be8 4258 /* use prefetched values */
86c3d59f
JB		 4259 rx_desc = next_rxd;
4260 buffer_info = next_buffer;
1da177e4 4261 }
1da177e4 4262 rx_ring->next_to_clean = i;
72d64a43
JK		 4263
4264 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4265 if (cleaned_count)
4266 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92 4267
835bb129
JB		 4268 adapter->total_rx_packets += total_rx_packets;
4269 adapter->total_rx_bytes += total_rx_bytes;
ef90e4ec
AK		 4270 adapter->net_stats.rx_bytes += total_rx_bytes;
4271 adapter->net_stats.rx_packets += total_rx_packets;
2d7edb92
MC		 4272 return cleaned;
4273}
4274
4275/**
4276 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
4277 * @adapter: board private structure
4278 **/
4279
4280static boolean_t
4281#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4282e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4283 struct e1000_rx_ring *rx_ring,
4284 int *work_done, int work_to_do)
2d7edb92 4285#else
581d708e
MC		 4286e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4287 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 4288#endif
4289{
86c3d59f 4290 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 4291 struct net_device *netdev = adapter->netdev;
4292 struct pci_dev *pdev = adapter->pdev;
86c3d59f 4293 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 4294 struct e1000_ps_page *ps_page;
4295 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 4296 struct sk_buff *skb;
2d7edb92
MC		 4297 unsigned int i, j;
4298 uint32_t length, staterr;
72d64a43 4299 int cleaned_count = 0;
2d7edb92 4300 boolean_t cleaned = FALSE;
835bb129 4301 unsigned int total_rx_bytes=0, total_rx_packets=0;
2d7edb92
MC		 4302
4303 i = rx_ring->next_to_clean;
4304 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 4305 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 4306 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 4307
96838a40 4308 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 4309 ps_page = &rx_ring->ps_page[i];
4310 ps_page_dma = &rx_ring->ps_page_dma[i];
4311#ifdef CONFIG_E1000_NAPI
96838a40 4312 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 4313 break;
4314 (*work_done)++;
4315#endif
86c3d59f
JB		 4316 skb = buffer_info->skb;
4317
30320be8
JK		 4318 /* in the packet split case this is header only */
4319 prefetch(skb->data - NET_IP_ALIGN);
4320
86c3d59f
JB		 4321 if (++i == rx_ring->count) i = 0;
4322 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 4323 prefetch(next_rxd);
4324
86c3d59f 4325 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4326
2d7edb92 4327 cleaned = TRUE;
72d64a43 4328 cleaned_count++;
2d7edb92
MC		 4329 pci_unmap_single(pdev, buffer_info->dma,
4330 buffer_info->length,
4331 PCI_DMA_FROMDEVICE);
4332
96838a40 4333 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 4334 E1000_DBG("%s: Packet Split buffers didn't pick up"
4335 " the full packet\n", netdev->name);
4336 dev_kfree_skb_irq(skb);
4337 goto next_desc;
4338 }
1da177e4 4339
96838a40 4340 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 4341 dev_kfree_skb_irq(skb);
4342 goto next_desc;
4343 }
4344
4345 length = le16_to_cpu(rx_desc->wb.middle.length0);
4346
96838a40 4347 if (unlikely(!length)) {
2d7edb92
MC		 4348 E1000_DBG("%s: Last part of the packet spanning"
4349 " multiple descriptors\n", netdev->name);
4350 dev_kfree_skb_irq(skb);
4351 goto next_desc;
4352 }
4353
4354 /* Good Receive */
4355 skb_put(skb, length);
4356
dc7c6add
JK		 4357 {
4358 /* this looks ugly, but it seems compiler issues make it
4359 more efficient than reusing j */
4360 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
4361
4362 /* page alloc/put takes too long and effects small packet
4363 * throughput, so unsplit small packets and save the alloc/put*/
1f753861 4364 if (l1 && (l1 <= copybreak) && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 4365 u8 *vaddr;
76c224bc 4366 /* there is no documentation about how to call
dc7c6add
JK		 4367 * kmap_atomic, so we can't hold the mapping
4368 * very long */
4369 pci_dma_sync_single_for_cpu(pdev,
4370 ps_page_dma->ps_page_dma[0],
4371 PAGE_SIZE,
4372 PCI_DMA_FROMDEVICE);
4373 vaddr = kmap_atomic(ps_page->ps_page[0],
4374 KM_SKB_DATA_SOFTIRQ);
27a884dc 4375 memcpy(skb_tail_pointer(skb), vaddr, l1);
dc7c6add
JK		 4376 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
4377 pci_dma_sync_single_for_device(pdev,
4378 ps_page_dma->ps_page_dma[0],
4379 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 4380 /* remove the CRC */
4381 l1 -= 4;
dc7c6add 4382 skb_put(skb, l1);
dc7c6add
JK		 4383 goto copydone;
4384 } /* if */
4385 }
90fb5135 4386
96838a40 4387 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 4388 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 4389 break;
2d7edb92
MC		 4390 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
4391 PAGE_SIZE, PCI_DMA_FROMDEVICE);
4392 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 4393 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
4394 length);
2d7edb92 4395 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 4396 skb->len += length;
4397 skb->data_len += length;
5d51b80f 4398 skb->truesize += length;
2d7edb92
MC		 4399 }
4400
f235a2ab
AK		 4401 /* strip the ethernet crc, problem is we're using pages now so
4402 * this whole operation can get a little cpu intensive */
4403 pskb_trim(skb, skb->len - 4);
4404
dc7c6add 4405copydone:
835bb129
JB		 4406 total_rx_bytes += skb->len;
4407 total_rx_packets++;
4408
2d7edb92 4409 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 4410 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 4411 skb->protocol = eth_type_trans(skb, netdev);
4412
96838a40 4413 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 4414 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 4415 adapter->rx_hdr_split++;
2d7edb92 4416#ifdef CONFIG_E1000_NAPI
96838a40 4417 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4418 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 4419 le16_to_cpu(rx_desc->wb.middle.vlan) &
4420 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4421 } else {
4422 netif_receive_skb(skb);
4423 }
4424#else /* CONFIG_E1000_NAPI */
96838a40 4425 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4426 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 4427 le16_to_cpu(rx_desc->wb.middle.vlan) &
4428 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4429 } else {
4430 netif_rx(skb);
4431 }
4432#endif /* CONFIG_E1000_NAPI */
4433 netdev->last_rx = jiffies;
4434
4435next_desc:
c3d7a3a4 4436 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 4437 buffer_info->skb = NULL;
2d7edb92 4438
72d64a43
JK		 4439 /* return some buffers to hardware, one at a time is too slow */
4440 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4441 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4442 cleaned_count = 0;
4443 }
4444
30320be8 4445 /* use prefetched values */
86c3d59f
JB		 4446 rx_desc = next_rxd;
4447 buffer_info = next_buffer;
4448
683a38f3 4449 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 4450 }
4451 rx_ring->next_to_clean = i;
72d64a43
JK		 4452
4453 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4454 if (cleaned_count)
4455 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4 4456
835bb129
JB		 4457 adapter->total_rx_packets += total_rx_packets;
4458 adapter->total_rx_bytes += total_rx_bytes;
ef90e4ec
AK		 4459 adapter->net_stats.rx_bytes += total_rx_bytes;
4460 adapter->net_stats.rx_packets += total_rx_packets;
1da177e4
LT		 4461 return cleaned;
4462}
4463
4464/**
2d7edb92 4465 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 4466 * @adapter: address of board private structure
4467 **/
4468
4469static void
581d708e 4470e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 4471 struct e1000_rx_ring *rx_ring,
a292ca6e 4472 int cleaned_count)
1da177e4 4473{
1da177e4
LT		 4474 struct net_device *netdev = adapter->netdev;
4475 struct pci_dev *pdev = adapter->pdev;
4476 struct e1000_rx_desc *rx_desc;
4477 struct e1000_buffer *buffer_info;
4478 struct sk_buff *skb;
2648345f
MC		 4479 unsigned int i;
4480 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 4481
4482 i = rx_ring->next_to_use;
4483 buffer_info = &rx_ring->buffer_info[i];
4484
a292ca6e 4485 while (cleaned_count--) {
ca6f7224
CH		 4486 skb = buffer_info->skb;
4487 if (skb) {
a292ca6e
JK		 4488 skb_trim(skb, 0);
4489 goto map_skb;
4490 }
4491
ca6f7224 4492 skb = netdev_alloc_skb(netdev, bufsz);
96838a40 4493 if (unlikely(!skb)) {
1da177e4 4494 /* Better luck next round */
72d64a43 4495 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 4496 break;
4497 }
4498
2648345f 4499 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 4500 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4501 struct sk_buff *oldskb = skb;
2648345f
MC		 4502 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
4503 "at %p\n", bufsz, skb->data);
4504 /* Try again, without freeing the previous */
87f5032e 4505 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 4506 /* Failed allocation, critical failure */
1da177e4
LT		 4507 if (!skb) {
4508 dev_kfree_skb(oldskb);
4509 break;
4510 }
2648345f 4511
1da177e4
LT		 4512 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4513 /* give up */
4514 dev_kfree_skb(skb);
4515 dev_kfree_skb(oldskb);
4516 break; /* while !buffer_info->skb */
1da177e4 4517 }
ca6f7224
CH		 4518
4519 /* Use new allocation */
4520 dev_kfree_skb(oldskb);
1da177e4 4521 }
1da177e4
LT		 4522 /* Make buffer alignment 2 beyond a 16 byte boundary
4523 * this will result in a 16 byte aligned IP header after
4524 * the 14 byte MAC header is removed
4525 */
4526 skb_reserve(skb, NET_IP_ALIGN);
4527
1da177e4
LT		 4528 buffer_info->skb = skb;
4529 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4530map_skb:
1da177e4
LT		 4531 buffer_info->dma = pci_map_single(pdev,
4532 skb->data,
4533 adapter->rx_buffer_len,
4534 PCI_DMA_FROMDEVICE);
4535
2648345f
MC		 4536 /* Fix for errata 23, can't cross 64kB boundary */
4537 if (!e1000_check_64k_bound(adapter,
4538 (void *)(unsigned long)buffer_info->dma,
4539 adapter->rx_buffer_len)) {
4540 DPRINTK(RX_ERR, ERR,
4541 "dma align check failed: %u bytes at %p\n",
4542 adapter->rx_buffer_len,
4543 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4544 dev_kfree_skb(skb);
4545 buffer_info->skb = NULL;
4546
2648345f 4547 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4548 adapter->rx_buffer_len,
4549 PCI_DMA_FROMDEVICE);
4550
4551 break; /* while !buffer_info->skb */
4552 }
1da177e4
LT		 4553 rx_desc = E1000_RX_DESC(*rx_ring, i);
4554 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4555
96838a40
JB		 4556 if (unlikely(++i == rx_ring->count))
4557 i = 0;
1da177e4
LT		 4558 buffer_info = &rx_ring->buffer_info[i];
4559 }
4560
b92ff8ee
JB		 4561 if (likely(rx_ring->next_to_use != i)) {
4562 rx_ring->next_to_use = i;
4563 if (unlikely(i-- == 0))
4564 i = (rx_ring->count - 1);
4565
4566 /* Force memory writes to complete before letting h/w
4567 * know there are new descriptors to fetch. (Only
4568 * applicable for weak-ordered memory model archs,
4569 * such as IA-64). */
4570 wmb();
4571 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4572 }
1da177e4
LT		 4573}
4574
2d7edb92
MC		 4575/**
4576 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4577 * @adapter: address of board private structure
4578 **/
4579
4580static void
581d708e 4581e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4582 struct e1000_rx_ring *rx_ring,
4583 int cleaned_count)
2d7edb92 4584{
2d7edb92
MC		 4585 struct net_device *netdev = adapter->netdev;
4586 struct pci_dev *pdev = adapter->pdev;
4587 union e1000_rx_desc_packet_split *rx_desc;
4588 struct e1000_buffer *buffer_info;
4589 struct e1000_ps_page *ps_page;
4590 struct e1000_ps_page_dma *ps_page_dma;
4591 struct sk_buff *skb;
4592 unsigned int i, j;
4593
4594 i = rx_ring->next_to_use;
4595 buffer_info = &rx_ring->buffer_info[i];
4596 ps_page = &rx_ring->ps_page[i];
4597 ps_page_dma = &rx_ring->ps_page_dma[i];
4598
72d64a43 4599 while (cleaned_count--) {
2d7edb92
MC		 4600 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4601
96838a40 4602 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4603 if (j < adapter->rx_ps_pages) {
4604 if (likely(!ps_page->ps_page[j])) {
4605 ps_page->ps_page[j] =
4606 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4607 if (unlikely(!ps_page->ps_page[j])) {
4608 adapter->alloc_rx_buff_failed++;
e4c811c9 4609 goto no_buffers;
b92ff8ee 4610 }
e4c811c9
MC		 4611 ps_page_dma->ps_page_dma[j] =
4612 pci_map_page(pdev,
4613 ps_page->ps_page[j],
4614 0, PAGE_SIZE,
4615 PCI_DMA_FROMDEVICE);
4616 }
4617 /* Refresh the desc even if buffer_addrs didn't
96838a40 4618 * change because each write-back erases
e4c811c9
MC		 4619 * this info.
4620 */
4621 rx_desc->read.buffer_addr[j+1] =
4622 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4623 } else
3e18826c 4624 rx_desc->read.buffer_addr[j+1] = ~cpu_to_le64(0);
2d7edb92
MC		 4625 }
4626
87f5032e 4627 skb = netdev_alloc_skb(netdev,
90fb5135 4628 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4629
b92ff8ee
JB		 4630 if (unlikely(!skb)) {
4631 adapter->alloc_rx_buff_failed++;
2d7edb92 4632 break;
b92ff8ee 4633 }
2d7edb92
MC		 4634
4635 /* Make buffer alignment 2 beyond a 16 byte boundary
4636 * this will result in a 16 byte aligned IP header after
4637 * the 14 byte MAC header is removed
4638 */
4639 skb_reserve(skb, NET_IP_ALIGN);
4640
2d7edb92
MC		 4641 buffer_info->skb = skb;
4642 buffer_info->length = adapter->rx_ps_bsize0;
4643 buffer_info->dma = pci_map_single(pdev, skb->data,
4644 adapter->rx_ps_bsize0,
4645 PCI_DMA_FROMDEVICE);
4646
4647 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4648
96838a40 4649 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4650 buffer_info = &rx_ring->buffer_info[i];
4651 ps_page = &rx_ring->ps_page[i];
4652 ps_page_dma = &rx_ring->ps_page_dma[i];
4653 }
4654
4655no_buffers:
b92ff8ee
JB		 4656 if (likely(rx_ring->next_to_use != i)) {
4657 rx_ring->next_to_use = i;
4658 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4659
4660 /* Force memory writes to complete before letting h/w
4661 * know there are new descriptors to fetch. (Only
4662 * applicable for weak-ordered memory model archs,
4663 * such as IA-64). */
4664 wmb();
4665 /* Hardware increments by 16 bytes, but packet split
4666 * descriptors are 32 bytes...so we increment tail
4667 * twice as much.
4668 */
4669 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4670 }
2d7edb92
MC		 4671}
4672
1da177e4
LT		 4673/**
4674 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4675 * @adapter:
4676 **/
4677
4678static void
4679e1000_smartspeed(struct e1000_adapter *adapter)
4680{
4681 uint16_t phy_status;
4682 uint16_t phy_ctrl;
4683
96838a40 4684 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4685 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4686 return;
4687
96838a40 4688 if (adapter->smartspeed == 0) {
1da177e4
LT		 4689 /* If Master/Slave config fault is asserted twice,
4690 * we assume back-to-back */
4691 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4692 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4693 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4694 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4695 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4696 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4697 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4698 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4699 phy_ctrl);
4700 adapter->smartspeed++;
96838a40 4701 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4702 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4703 &phy_ctrl)) {
4704 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4705 MII_CR_RESTART_AUTO_NEG);
4706 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4707 phy_ctrl);
4708 }
4709 }
4710 return;
96838a40 4711 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4712 /* If still no link, perhaps using 2/3 pair cable */
4713 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4714 phy_ctrl |= CR_1000T_MS_ENABLE;
4715 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4716 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4717 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4718 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4719 MII_CR_RESTART_AUTO_NEG);
4720 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4721 }
4722 }
4723 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4724 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4725 adapter->smartspeed = 0;
4726}
4727
4728/**
4729 * e1000_ioctl -
4730 * @netdev:
4731 * @ifreq:
4732 * @cmd:
4733 **/
4734
4735static int
4736e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4737{
4738 switch (cmd) {
4739 case SIOCGMIIPHY:
4740 case SIOCGMIIREG:
4741 case SIOCSMIIREG:
4742 return e1000_mii_ioctl(netdev, ifr, cmd);
4743 default:
4744 return -EOPNOTSUPP;
4745 }
4746}
4747
4748/**
4749 * e1000_mii_ioctl -
4750 * @netdev:
4751 * @ifreq:
4752 * @cmd:
4753 **/
4754
4755static int
4756e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4757{
60490fe0 4758 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4759 struct mii_ioctl_data *data = if_mii(ifr);
4760 int retval;
4761 uint16_t mii_reg;
4762 uint16_t spddplx;
97876fc6 4763 unsigned long flags;
1da177e4 4764
96838a40 4765 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4766 return -EOPNOTSUPP;
4767
4768 switch (cmd) {
4769 case SIOCGMIIPHY:
4770 data->phy_id = adapter->hw.phy_addr;
4771 break;
4772 case SIOCGMIIREG:
96838a40 4773 if (!capable(CAP_NET_ADMIN))
1da177e4 4774 return -EPERM;
97876fc6 4775 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4776 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4777 &data->val_out)) {
4778 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4779 return -EIO;
97876fc6
MC		 4780 }
4781 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4782 break;
4783 case SIOCSMIIREG:
96838a40 4784 if (!capable(CAP_NET_ADMIN))
1da177e4 4785 return -EPERM;
96838a40 4786 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4787 return -EFAULT;
4788 mii_reg = data->val_in;
97876fc6 4789 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4790 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4791 mii_reg)) {
4792 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4793 return -EIO;
97876fc6 4794 }
f0163ac4 4795 spin_unlock_irqrestore(&adapter->stats_lock, flags);
dc86d32a 4796 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4797 switch (data->reg_num) {
4798 case PHY_CTRL:
96838a40 4799 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4800 break;
96838a40 4801 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4802 adapter->hw.autoneg = 1;
4803 adapter->hw.autoneg_advertised = 0x2F;
4804 } else {
4805 if (mii_reg & 0x40)
4806 spddplx = SPEED_1000;
4807 else if (mii_reg & 0x2000)
4808 spddplx = SPEED_100;
4809 else
4810 spddplx = SPEED_10;
4811 spddplx += (mii_reg & 0x100)
cb764326
JK		 4812 ? DUPLEX_FULL :
4813 DUPLEX_HALF;
1da177e4
LT		 4814 retval = e1000_set_spd_dplx(adapter,
4815 spddplx);
f0163ac4 4816 if (retval)
1da177e4
LT		 4817 return retval;
4818 }
2db10a08
AK		 4819 if (netif_running(adapter->netdev))
4820 e1000_reinit_locked(adapter);
4821 else
1da177e4
LT		 4822 e1000_reset(adapter);
4823 break;
4824 case M88E1000_PHY_SPEC_CTRL:
4825 case M88E1000_EXT_PHY_SPEC_CTRL:
f0163ac4 4826 if (e1000_phy_reset(&adapter->hw))
1da177e4
LT		 4827 return -EIO;
4828 break;
4829 }
4830 } else {
4831 switch (data->reg_num) {
4832 case PHY_CTRL:
96838a40 4833 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4834 break;
2db10a08
AK		 4835 if (netif_running(adapter->netdev))
4836 e1000_reinit_locked(adapter);
4837 else
1da177e4
LT		 4838 e1000_reset(adapter);
4839 break;
4840 }
4841 }
4842 break;
4843 default:
4844 return -EOPNOTSUPP;
4845 }
4846 return E1000_SUCCESS;
4847}
4848
4849void
4850e1000_pci_set_mwi(struct e1000_hw *hw)
4851{
4852 struct e1000_adapter *adapter = hw->back;
2648345f 4853 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4854
96838a40 4855 if (ret_val)
2648345f 4856 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4857}
4858
4859void
4860e1000_pci_clear_mwi(struct e1000_hw *hw)
4861{
4862 struct e1000_adapter *adapter = hw->back;
4863
4864 pci_clear_mwi(adapter->pdev);
4865}
4866
007755eb
PO		 4867int
4868e1000_pcix_get_mmrbc(struct e1000_hw *hw)
4869{
4870 struct e1000_adapter *adapter = hw->back;
4871 return pcix_get_mmrbc(adapter->pdev);
4872}
4873
4874void
4875e1000_pcix_set_mmrbc(struct e1000_hw *hw, int mmrbc)
4876{
4877 struct e1000_adapter *adapter = hw->back;
4878 pcix_set_mmrbc(adapter->pdev, mmrbc);
4879}
4880
caeccb68
JK		 4881int32_t
4882e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4883{
4884 struct e1000_adapter *adapter = hw->back;
4885 uint16_t cap_offset;
4886
4887 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
4888 if (!cap_offset)
4889 return -E1000_ERR_CONFIG;
4890
4891 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
4892
4893 return E1000_SUCCESS;
4894}
4895
1da177e4
LT		 4896void
4897e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4898{
4899 outl(value, port);
4900}
4901
4902static void
4903e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4904{
60490fe0 4905 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4906 uint32_t ctrl, rctl;
4907
4908 e1000_irq_disable(adapter);
4909 adapter->vlgrp = grp;
4910
96838a40 4911 if (grp) {
1da177e4
LT		 4912 /* enable VLAN tag insert/strip */
4913 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4914 ctrl |= E1000_CTRL_VME;
4915 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4916
cd94dd0b 4917 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4918 /* enable VLAN receive filtering */
4919 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4920 rctl |= E1000_RCTL_VFE;
4921 rctl &= ~E1000_RCTL_CFIEN;
4922 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4923 e1000_update_mng_vlan(adapter);
cd94dd0b 4924 }
1da177e4
LT		 4925 } else {
4926 /* disable VLAN tag insert/strip */
4927 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4928 ctrl &= ~E1000_CTRL_VME;
4929 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4930
cd94dd0b 4931 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4932 /* disable VLAN filtering */
4933 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4934 rctl &= ~E1000_RCTL_VFE;
4935 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4936 if (adapter->mng_vlan_id !=
4937 (uint16_t)E1000_MNG_VLAN_NONE) {
4938 e1000_vlan_rx_kill_vid(netdev,
4939 adapter->mng_vlan_id);
4940 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4941 }
cd94dd0b 4942 }
1da177e4
LT		 4943 }
4944
4945 e1000_irq_enable(adapter);
4946}
4947
4948static void
4949e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4950{
60490fe0 4951 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4952 uint32_t vfta, index;
96838a40
JB		 4953
4954 if ((adapter->hw.mng_cookie.status &
4955 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4956 (vid == adapter->mng_vlan_id))
2d7edb92 4957 return;
1da177e4
LT		 4958 /* add VID to filter table */
4959 index = (vid >> 5) & 0x7F;
4960 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4961 vfta |= (1 << (vid & 0x1F));
4962 e1000_write_vfta(&adapter->hw, index, vfta);
4963}
4964
4965static void
4966e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4967{
60490fe0 4968 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4969 uint32_t vfta, index;
4970
4971 e1000_irq_disable(adapter);
5c15bdec 4972 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1da177e4
LT		 4973 e1000_irq_enable(adapter);
4974
96838a40
JB		 4975 if ((adapter->hw.mng_cookie.status &
4976 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 4977 (vid == adapter->mng_vlan_id)) {
4978 /* release control to f/w */
4979 e1000_release_hw_control(adapter);
2d7edb92 4980 return;
ff147013
JK		 4981 }
4982
1da177e4
LT		 4983 /* remove VID from filter table */
4984 index = (vid >> 5) & 0x7F;
4985 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4986 vfta &= ~(1 << (vid & 0x1F));
4987 e1000_write_vfta(&adapter->hw, index, vfta);
4988}
4989
4990static void
4991e1000_restore_vlan(struct e1000_adapter *adapter)
4992{
4993 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
4994
96838a40 4995 if (adapter->vlgrp) {
1da177e4 4996 uint16_t vid;
96838a40 4997 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5c15bdec 4998 if (!vlan_group_get_device(adapter->vlgrp, vid))
1da177e4
LT		 4999 continue;
5000 e1000_vlan_rx_add_vid(adapter->netdev, vid);
5001 }
5002 }
5003}
5004
5005int
5006e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
5007{
5008 adapter->hw.autoneg = 0;
5009
6921368f 5010 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 5011 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 5012 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5013 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
5014 return -EINVAL;
5015 }
5016
96838a40 5017 switch (spddplx) {
1da177e4
LT		 5018 case SPEED_10 + DUPLEX_HALF:
5019 adapter->hw.forced_speed_duplex = e1000_10_half;
5020 break;
5021 case SPEED_10 + DUPLEX_FULL:
5022 adapter->hw.forced_speed_duplex = e1000_10_full;
5023 break;
5024 case SPEED_100 + DUPLEX_HALF:
5025 adapter->hw.forced_speed_duplex = e1000_100_half;
5026 break;
5027 case SPEED_100 + DUPLEX_FULL:
5028 adapter->hw.forced_speed_duplex = e1000_100_full;
5029 break;
5030 case SPEED_1000 + DUPLEX_FULL:
5031 adapter->hw.autoneg = 1;
5032 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
5033 break;
5034 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5035 default:
2648345f 5036 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 5037 return -EINVAL;
5038 }
5039 return 0;
5040}
5041
1da177e4 5042static int
829ca9a3 5043e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 5044{
5045 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5046 struct e1000_adapter *adapter = netdev_priv(netdev);
0fccd0e9 5047 uint32_t ctrl, ctrl_ext, rctl, status;
1da177e4 5048 uint32_t wufc = adapter->wol;
6fdfef16 5049#ifdef CONFIG_PM
240b1710 5050 int retval = 0;
6fdfef16 5051#endif
1da177e4
LT		 5052
5053 netif_device_detach(netdev);
5054
2db10a08
AK		 5055 if (netif_running(netdev)) {
5056 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 5057 e1000_down(adapter);
2db10a08 5058 }
1da177e4 5059
2f82665f 5060#ifdef CONFIG_PM
1d33e9c6 5061 retval = pci_save_state(pdev);
2f82665f
JB		 5062 if (retval)
5063 return retval;
5064#endif
5065
1da177e4 5066 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 5067 if (status & E1000_STATUS_LU)
1da177e4
LT		 5068 wufc &= ~E1000_WUFC_LNKC;
5069
96838a40 5070 if (wufc) {
1da177e4 5071 e1000_setup_rctl(adapter);
db0ce50d 5072 e1000_set_rx_mode(netdev);
1da177e4
LT		 5073
5074 /* turn on all-multi mode if wake on multicast is enabled */
120cd576 5075 if (wufc & E1000_WUFC_MC) {
1da177e4
LT		 5076 rctl = E1000_READ_REG(&adapter->hw, RCTL);
5077 rctl |= E1000_RCTL_MPE;
5078 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
5079 }
5080
96838a40 5081 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 5082 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
5083 /* advertise wake from D3Cold */
5084 #define E1000_CTRL_ADVD3WUC 0x00100000
5085 /* phy power management enable */
5086 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5087 ctrl |= E1000_CTRL_ADVD3WUC |
5088 E1000_CTRL_EN_PHY_PWR_MGMT;
5089 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
5090 }
5091
96838a40 5092 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 5093 adapter->hw.media_type == e1000_media_type_internal_serdes) {
5094 /* keep the laser running in D3 */
5095 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
5096 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
5097 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
5098 }
5099
2d7edb92
MC		 5100 /* Allow time for pending master requests to run */
5101 e1000_disable_pciex_master(&adapter->hw);
5102
1da177e4
LT		 5103 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
5104 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 5105 pci_enable_wake(pdev, PCI_D3hot, 1);
5106 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5107 } else {
5108 E1000_WRITE_REG(&adapter->hw, WUC, 0);
5109 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 5110 pci_enable_wake(pdev, PCI_D3hot, 0);
5111 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 5112 }
5113
0fccd0e9
JG		 5114 e1000_release_manageability(adapter);
5115
5116 /* make sure adapter isn't asleep if manageability is enabled */
5117 if (adapter->en_mng_pt) {
5118 pci_enable_wake(pdev, PCI_D3hot, 1);
5119 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5120 }
5121
cd94dd0b
AK		 5122 if (adapter->hw.phy_type == e1000_phy_igp_3)
5123 e1000_phy_powerdown_workaround(&adapter->hw);
5124
edd106fc
AK		 5125 if (netif_running(netdev))
5126 e1000_free_irq(adapter);
5127
b55ccb35
JK		 5128 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5129 * would have already happened in close and is redundant. */
5130 e1000_release_hw_control(adapter);
2d7edb92 5131
1da177e4 5132 pci_disable_device(pdev);
240b1710 5133
d0e027db 5134 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 5135
5136 return 0;
5137}
5138
2f82665f 5139#ifdef CONFIG_PM
1da177e4
LT		 5140static int
5141e1000_resume(struct pci_dev *pdev)
5142{
5143 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5144 struct e1000_adapter *adapter = netdev_priv(netdev);
0fccd0e9 5145 uint32_t err;
1da177e4 5146
d0e027db 5147 pci_set_power_state(pdev, PCI_D0);
1d33e9c6 5148 pci_restore_state(pdev);
3d1dd8cb
AK		 5149 if ((err = pci_enable_device(pdev))) {
5150 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
5151 return err;
5152 }
a4cb847d 5153 pci_set_master(pdev);
1da177e4 5154
d0e027db
AK		 5155 pci_enable_wake(pdev, PCI_D3hot, 0);
5156 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4 5157
edd106fc
AK		 5158 if (netif_running(netdev) && (err = e1000_request_irq(adapter)))
5159 return err;
5160
5161 e1000_power_up_phy(adapter);
1da177e4
LT		 5162 e1000_reset(adapter);
5163 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5164
0fccd0e9
JG		 5165 e1000_init_manageability(adapter);
5166
96838a40 5167 if (netif_running(netdev))
1da177e4
LT		 5168 e1000_up(adapter);
5169
5170 netif_device_attach(netdev);
5171
b55ccb35
JK		 5172 /* If the controller is 82573 and f/w is AMT, do not set
5173 * DRV_LOAD until the interface is up. For all other cases,
5174 * let the f/w know that the h/w is now under the control
5175 * of the driver. */
5176 if (adapter->hw.mac_type != e1000_82573 ||
5177 !e1000_check_mng_mode(&adapter->hw))
5178 e1000_get_hw_control(adapter);
2d7edb92 5179
1da177e4
LT		 5180 return 0;
5181}
5182#endif
c653e635
AK		 5183
5184static void e1000_shutdown(struct pci_dev *pdev)
5185{
5186 e1000_suspend(pdev, PMSG_SUSPEND);
5187}
5188
1da177e4
LT		 5189#ifdef CONFIG_NET_POLL_CONTROLLER
5190/*
5191 * Polling 'interrupt' - used by things like netconsole to send skbs
5192 * without having to re-enable interrupts. It's not called while
5193 * the interrupt routine is executing.
5194 */
5195static void
2648345f 5196e1000_netpoll(struct net_device *netdev)
1da177e4 5197{
60490fe0 5198 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 5199
1da177e4 5200 disable_irq(adapter->pdev->irq);
7d12e780 5201 e1000_intr(adapter->pdev->irq, netdev);
c4cfe567 5202 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 5203#ifndef CONFIG_E1000_NAPI
5204 adapter->clean_rx(adapter, adapter->rx_ring);
5205#endif
1da177e4
LT		 5206 enable_irq(adapter->pdev->irq);
5207}
5208#endif
5209
9026729b
AK		 5210/**
5211 * e1000_io_error_detected - called when PCI error is detected
5212 * @pdev: Pointer to PCI device
5213 * @state: The current pci conneection state
5214 *
5215 * This function is called after a PCI bus error affecting
5216 * this device has been detected.
5217 */
5218static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5219{
5220 struct net_device *netdev = pci_get_drvdata(pdev);
5221 struct e1000_adapter *adapter = netdev->priv;
5222
5223 netif_device_detach(netdev);
5224
5225 if (netif_running(netdev))
5226 e1000_down(adapter);
72e8d6bb 5227 pci_disable_device(pdev);
9026729b
AK		 5228
5229 /* Request a slot slot reset. */
5230 return PCI_ERS_RESULT_NEED_RESET;
5231}
5232
5233/**
5234 * e1000_io_slot_reset - called after the pci bus has been reset.
5235 * @pdev: Pointer to PCI device
5236 *
5237 * Restart the card from scratch, as if from a cold-boot. Implementation
5238 * resembles the first-half of the e1000_resume routine.
5239 */
5240static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5241{
5242 struct net_device *netdev = pci_get_drvdata(pdev);
5243 struct e1000_adapter *adapter = netdev->priv;
5244
5245 if (pci_enable_device(pdev)) {
5246 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
5247 return PCI_ERS_RESULT_DISCONNECT;
5248 }
5249 pci_set_master(pdev);
5250
dbf38c94
LV		 5251 pci_enable_wake(pdev, PCI_D3hot, 0);
5252 pci_enable_wake(pdev, PCI_D3cold, 0);
9026729b 5253
9026729b
AK		 5254 e1000_reset(adapter);
5255 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5256
5257 return PCI_ERS_RESULT_RECOVERED;
5258}
5259
5260/**
5261 * e1000_io_resume - called when traffic can start flowing again.
5262 * @pdev: Pointer to PCI device
5263 *
5264 * This callback is called when the error recovery driver tells us that
5265 * its OK to resume normal operation. Implementation resembles the
5266 * second-half of the e1000_resume routine.
5267 */
5268static void e1000_io_resume(struct pci_dev *pdev)
5269{
5270 struct net_device *netdev = pci_get_drvdata(pdev);
5271 struct e1000_adapter *adapter = netdev->priv;
0fccd0e9
JG		 5272
5273 e1000_init_manageability(adapter);
9026729b
AK		 5274
5275 if (netif_running(netdev)) {
5276 if (e1000_up(adapter)) {
5277 printk("e1000: can't bring device back up after reset\n");
5278 return;
5279 }
5280 }
5281
5282 netif_device_attach(netdev);
5283
0fccd0e9
JG		 5284 /* If the controller is 82573 and f/w is AMT, do not set
5285 * DRV_LOAD until the interface is up. For all other cases,
5286 * let the f/w know that the h/w is now under the control
5287 * of the driver. */
5288 if (adapter->hw.mac_type != e1000_82573 ||
5289 !e1000_check_mng_mode(&adapter->hw))
5290 e1000_get_hw_control(adapter);
9026729b 5291
9026729b
AK		 5292}
5293
1da177e4 5294/* e1000_main.c */
Linux kernel - Deliverables
This page took 0.825604 seconds and 5 git commands to generate.