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[RT2x00]: add driver for Ralink wireless hardware
[deliverable/linux.git] / drivers / net / e1000 / e1000_main.c
CommitLineData
1da177e4
LT		 1/*******************************************************************************
2
0abb6eb1
AK		 3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
1da177e4 13 more details.
0abb6eb1 14
1da177e4 15 You should have received a copy of the GNU General Public License along with
0abb6eb1
AK		 16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
1da177e4
LT		 22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
3d41e30a 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
1da177e4
LT		 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include "e1000.h"
d0bb53e1 30#include <net/ip6_checksum.h>
1da177e4 31
1da177e4 32char e1000_driver_name[] = "e1000";
3ad2cc67 33static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
1da177e4
LT		 34#ifndef CONFIG_E1000_NAPI
35#define DRIVERNAPI
36#else
37#define DRIVERNAPI "-NAPI"
38#endif
7e721579 39#define DRV_VERSION "7.3.20-k2"DRIVERNAPI
1da177e4 40char e1000_driver_version[] = DRV_VERSION;
3d41e30a 41static char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation.";
1da177e4
LT		 42
43/* e1000_pci_tbl - PCI Device ID Table
44 *
45 * Last entry must be all 0s
46 *
47 * Macro expands to...
48 * {PCI_DEVICE(PCI_VENDOR_ID_INTEL, device_id)}
49 */
50static struct pci_device_id e1000_pci_tbl[] = {
51 INTEL_E1000_ETHERNET_DEVICE(0x1000),
52 INTEL_E1000_ETHERNET_DEVICE(0x1001),
53 INTEL_E1000_ETHERNET_DEVICE(0x1004),
54 INTEL_E1000_ETHERNET_DEVICE(0x1008),
55 INTEL_E1000_ETHERNET_DEVICE(0x1009),
56 INTEL_E1000_ETHERNET_DEVICE(0x100C),
57 INTEL_E1000_ETHERNET_DEVICE(0x100D),
58 INTEL_E1000_ETHERNET_DEVICE(0x100E),
59 INTEL_E1000_ETHERNET_DEVICE(0x100F),
60 INTEL_E1000_ETHERNET_DEVICE(0x1010),
61 INTEL_E1000_ETHERNET_DEVICE(0x1011),
62 INTEL_E1000_ETHERNET_DEVICE(0x1012),
63 INTEL_E1000_ETHERNET_DEVICE(0x1013),
64 INTEL_E1000_ETHERNET_DEVICE(0x1014),
65 INTEL_E1000_ETHERNET_DEVICE(0x1015),
66 INTEL_E1000_ETHERNET_DEVICE(0x1016),
67 INTEL_E1000_ETHERNET_DEVICE(0x1017),
68 INTEL_E1000_ETHERNET_DEVICE(0x1018),
69 INTEL_E1000_ETHERNET_DEVICE(0x1019),
2648345f 70 INTEL_E1000_ETHERNET_DEVICE(0x101A),
1da177e4
LT		 71 INTEL_E1000_ETHERNET_DEVICE(0x101D),
72 INTEL_E1000_ETHERNET_DEVICE(0x101E),
73 INTEL_E1000_ETHERNET_DEVICE(0x1026),
74 INTEL_E1000_ETHERNET_DEVICE(0x1027),
75 INTEL_E1000_ETHERNET_DEVICE(0x1028),
ae2c3860
AK		 76 INTEL_E1000_ETHERNET_DEVICE(0x1049),
77 INTEL_E1000_ETHERNET_DEVICE(0x104A),
78 INTEL_E1000_ETHERNET_DEVICE(0x104B),
79 INTEL_E1000_ETHERNET_DEVICE(0x104C),
80 INTEL_E1000_ETHERNET_DEVICE(0x104D),
07b8fede
MC		 81 INTEL_E1000_ETHERNET_DEVICE(0x105E),
82 INTEL_E1000_ETHERNET_DEVICE(0x105F),
83 INTEL_E1000_ETHERNET_DEVICE(0x1060),
1da177e4
LT		 84 INTEL_E1000_ETHERNET_DEVICE(0x1075),
85 INTEL_E1000_ETHERNET_DEVICE(0x1076),
86 INTEL_E1000_ETHERNET_DEVICE(0x1077),
87 INTEL_E1000_ETHERNET_DEVICE(0x1078),
88 INTEL_E1000_ETHERNET_DEVICE(0x1079),
89 INTEL_E1000_ETHERNET_DEVICE(0x107A),
90 INTEL_E1000_ETHERNET_DEVICE(0x107B),
91 INTEL_E1000_ETHERNET_DEVICE(0x107C),
07b8fede
MC		 92 INTEL_E1000_ETHERNET_DEVICE(0x107D),
93 INTEL_E1000_ETHERNET_DEVICE(0x107E),
94 INTEL_E1000_ETHERNET_DEVICE(0x107F),
1da177e4 95 INTEL_E1000_ETHERNET_DEVICE(0x108A),
2648345f
MC		 96 INTEL_E1000_ETHERNET_DEVICE(0x108B),
97 INTEL_E1000_ETHERNET_DEVICE(0x108C),
6418ecc6
JK		 98 INTEL_E1000_ETHERNET_DEVICE(0x1096),
99 INTEL_E1000_ETHERNET_DEVICE(0x1098),
b7ee49db 100 INTEL_E1000_ETHERNET_DEVICE(0x1099),
07b8fede 101 INTEL_E1000_ETHERNET_DEVICE(0x109A),
5881cde8 102 INTEL_E1000_ETHERNET_DEVICE(0x10A4),
ce57a02c 103 INTEL_E1000_ETHERNET_DEVICE(0x10A5),
b7ee49db 104 INTEL_E1000_ETHERNET_DEVICE(0x10B5),
6418ecc6 105 INTEL_E1000_ETHERNET_DEVICE(0x10B9),
ae2c3860
AK		 106 INTEL_E1000_ETHERNET_DEVICE(0x10BA),
107 INTEL_E1000_ETHERNET_DEVICE(0x10BB),
fc2307d0
AK		 108 INTEL_E1000_ETHERNET_DEVICE(0x10BC),
109 INTEL_E1000_ETHERNET_DEVICE(0x10C4),
110 INTEL_E1000_ETHERNET_DEVICE(0x10C5),
f4ec7f98 111 INTEL_E1000_ETHERNET_DEVICE(0x10D5),
ce57a02c
AK		 112 INTEL_E1000_ETHERNET_DEVICE(0x10D9),
113 INTEL_E1000_ETHERNET_DEVICE(0x10DA),
1da177e4
LT		 114 /* required last entry */
115 {0,}
116};
117
118MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
119
35574764
NN		 120int e1000_up(struct e1000_adapter *adapter);
121void e1000_down(struct e1000_adapter *adapter);
122void e1000_reinit_locked(struct e1000_adapter *adapter);
123void e1000_reset(struct e1000_adapter *adapter);
124int e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx);
125int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
126int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
127void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
128void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
3ad2cc67 129static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
35574764 130 struct e1000_tx_ring *txdr);
3ad2cc67 131static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
35574764 132 struct e1000_rx_ring *rxdr);
3ad2cc67 133static void e1000_free_tx_resources(struct e1000_adapter *adapter,
35574764 134 struct e1000_tx_ring *tx_ring);
3ad2cc67 135static void e1000_free_rx_resources(struct e1000_adapter *adapter,
35574764
NN		 136 struct e1000_rx_ring *rx_ring);
137void e1000_update_stats(struct e1000_adapter *adapter);
1da177e4
LT		 138
139static int e1000_init_module(void);
140static void e1000_exit_module(void);
141static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
142static void __devexit e1000_remove(struct pci_dev *pdev);
581d708e 143static int e1000_alloc_queues(struct e1000_adapter *adapter);
1da177e4
LT		 144static int e1000_sw_init(struct e1000_adapter *adapter);
145static int e1000_open(struct net_device *netdev);
146static int e1000_close(struct net_device *netdev);
147static void e1000_configure_tx(struct e1000_adapter *adapter);
148static void e1000_configure_rx(struct e1000_adapter *adapter);
149static void e1000_setup_rctl(struct e1000_adapter *adapter);
581d708e
MC		 150static void e1000_clean_all_tx_rings(struct e1000_adapter *adapter);
151static void e1000_clean_all_rx_rings(struct e1000_adapter *adapter);
152static void e1000_clean_tx_ring(struct e1000_adapter *adapter,
153 struct e1000_tx_ring *tx_ring);
154static void e1000_clean_rx_ring(struct e1000_adapter *adapter,
155 struct e1000_rx_ring *rx_ring);
1da177e4
LT		 156static void e1000_set_multi(struct net_device *netdev);
157static void e1000_update_phy_info(unsigned long data);
158static void e1000_watchdog(unsigned long data);
1da177e4
LT		 159static void e1000_82547_tx_fifo_stall(unsigned long data);
160static int e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
161static struct net_device_stats * e1000_get_stats(struct net_device *netdev);
162static int e1000_change_mtu(struct net_device *netdev, int new_mtu);
163static int e1000_set_mac(struct net_device *netdev, void *p);
7d12e780 164static irqreturn_t e1000_intr(int irq, void *data);
9ac98284 165static irqreturn_t e1000_intr_msi(int irq, void *data);
581d708e
MC		 166static boolean_t e1000_clean_tx_irq(struct e1000_adapter *adapter,
167 struct e1000_tx_ring *tx_ring);
1da177e4 168#ifdef CONFIG_E1000_NAPI
bea3348e 169static int e1000_clean(struct napi_struct *napi, int budget);
1da177e4 170static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
581d708e 171 struct e1000_rx_ring *rx_ring,
1da177e4 172 int *work_done, int work_to_do);
2d7edb92 173static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
581d708e 174 struct e1000_rx_ring *rx_ring,
2d7edb92 175 int *work_done, int work_to_do);
1da177e4 176#else
581d708e
MC		 177static boolean_t e1000_clean_rx_irq(struct e1000_adapter *adapter,
178 struct e1000_rx_ring *rx_ring);
179static boolean_t e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
180 struct e1000_rx_ring *rx_ring);
1da177e4 181#endif
581d708e 182static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43
JK		 183 struct e1000_rx_ring *rx_ring,
184 int cleaned_count);
581d708e 185static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 186 struct e1000_rx_ring *rx_ring,
187 int cleaned_count);
1da177e4
LT		 188static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
189static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
190 int cmd);
35574764 191void e1000_set_ethtool_ops(struct net_device *netdev);
1da177e4
LT		 192static void e1000_enter_82542_rst(struct e1000_adapter *adapter);
193static void e1000_leave_82542_rst(struct e1000_adapter *adapter);
194static void e1000_tx_timeout(struct net_device *dev);
65f27f38 195static void e1000_reset_task(struct work_struct *work);
1da177e4 196static void e1000_smartspeed(struct e1000_adapter *adapter);
e619d523
AK		 197static int e1000_82547_fifo_workaround(struct e1000_adapter *adapter,
198 struct sk_buff *skb);
1da177e4
LT		 199
200static void e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
201static void e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
202static void e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
203static void e1000_restore_vlan(struct e1000_adapter *adapter);
204
977e74b5 205static int e1000_suspend(struct pci_dev *pdev, pm_message_t state);
6fdfef16 206#ifdef CONFIG_PM
1da177e4
LT		 207static int e1000_resume(struct pci_dev *pdev);
208#endif
c653e635 209static void e1000_shutdown(struct pci_dev *pdev);
1da177e4
LT		 210
211#ifdef CONFIG_NET_POLL_CONTROLLER
212/* for netdump / net console */
213static void e1000_netpoll (struct net_device *netdev);
214#endif
215
35574764
NN		 216extern void e1000_check_options(struct e1000_adapter *adapter);
217
1f753861
JB		 218#define COPYBREAK_DEFAULT 256
219static unsigned int copybreak __read_mostly = COPYBREAK_DEFAULT;
220module_param(copybreak, uint, 0644);
221MODULE_PARM_DESC(copybreak,
222 "Maximum size of packet that is copied to a new buffer on receive");
223
9026729b
AK		 224static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
225 pci_channel_state_t state);
226static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev);
227static void e1000_io_resume(struct pci_dev *pdev);
228
229static struct pci_error_handlers e1000_err_handler = {
230 .error_detected = e1000_io_error_detected,
231 .slot_reset = e1000_io_slot_reset,
232 .resume = e1000_io_resume,
233};
24025e4e 234
1da177e4
LT		 235static struct pci_driver e1000_driver = {
236 .name = e1000_driver_name,
237 .id_table = e1000_pci_tbl,
238 .probe = e1000_probe,
239 .remove = __devexit_p(e1000_remove),
c4e24f01 240#ifdef CONFIG_PM
1da177e4 241 /* Power Managment Hooks */
1da177e4 242 .suspend = e1000_suspend,
c653e635 243 .resume = e1000_resume,
1da177e4 244#endif
9026729b
AK		 245 .shutdown = e1000_shutdown,
246 .err_handler = &e1000_err_handler
1da177e4
LT		 247};
248
249MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
250MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
251MODULE_LICENSE("GPL");
252MODULE_VERSION(DRV_VERSION);
253
254static int debug = NETIF_MSG_DRV | NETIF_MSG_PROBE;
255module_param(debug, int, 0);
256MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
257
258/**
259 * e1000_init_module - Driver Registration Routine
260 *
261 * e1000_init_module is the first routine called when the driver is
262 * loaded. All it does is register with the PCI subsystem.
263 **/
264
265static int __init
266e1000_init_module(void)
267{
268 int ret;
269 printk(KERN_INFO "%s - version %s\n",
270 e1000_driver_string, e1000_driver_version);
271
272 printk(KERN_INFO "%s\n", e1000_copyright);
273
29917620 274 ret = pci_register_driver(&e1000_driver);
1f753861
JB		 275 if (copybreak != COPYBREAK_DEFAULT) {
276 if (copybreak == 0)
277 printk(KERN_INFO "e1000: copybreak disabled\n");
278 else
279 printk(KERN_INFO "e1000: copybreak enabled for "
280 "packets <= %u bytes\n", copybreak);
281 }
1da177e4
LT		 282 return ret;
283}
284
285module_init(e1000_init_module);
286
287/**
288 * e1000_exit_module - Driver Exit Cleanup Routine
289 *
290 * e1000_exit_module is called just before the driver is removed
291 * from memory.
292 **/
293
294static void __exit
295e1000_exit_module(void)
296{
1da177e4
LT		 297 pci_unregister_driver(&e1000_driver);
298}
299
300module_exit(e1000_exit_module);
301
2db10a08
AK		 302static int e1000_request_irq(struct e1000_adapter *adapter)
303{
304 struct net_device *netdev = adapter->netdev;
e94bd23f
AK		 305 void (*handler) = &e1000_intr;
306 int irq_flags = IRQF_SHARED;
307 int err;
2db10a08 308
9ac98284 309 if (adapter->hw.mac_type >= e1000_82571) {
e94bd23f
AK		 310 adapter->have_msi = !pci_enable_msi(adapter->pdev);
311 if (adapter->have_msi) {
312 handler = &e1000_intr_msi;
313 irq_flags = 0;
2db10a08
AK		 314 }
315 }
e94bd23f
AK		 316
317 err = request_irq(adapter->pdev->irq, handler, irq_flags, netdev->name,
318 netdev);
319 if (err) {
320 if (adapter->have_msi)
321 pci_disable_msi(adapter->pdev);
2db10a08
AK		 322 DPRINTK(PROBE, ERR,
323 "Unable to allocate interrupt Error: %d\n", err);
e94bd23f 324 }
2db10a08
AK		 325
326 return err;
327}
328
329static void e1000_free_irq(struct e1000_adapter *adapter)
330{
331 struct net_device *netdev = adapter->netdev;
332
333 free_irq(adapter->pdev->irq, netdev);
334
2db10a08
AK		 335 if (adapter->have_msi)
336 pci_disable_msi(adapter->pdev);
2db10a08
AK		 337}
338
1da177e4
LT		 339/**
340 * e1000_irq_disable - Mask off interrupt generation on the NIC
341 * @adapter: board private structure
342 **/
343
e619d523 344static void
1da177e4
LT		 345e1000_irq_disable(struct e1000_adapter *adapter)
346{
347 atomic_inc(&adapter->irq_sem);
348 E1000_WRITE_REG(&adapter->hw, IMC, ~0);
349 E1000_WRITE_FLUSH(&adapter->hw);
350 synchronize_irq(adapter->pdev->irq);
351}
352
353/**
354 * e1000_irq_enable - Enable default interrupt generation settings
355 * @adapter: board private structure
356 **/
357
e619d523 358static void
1da177e4
LT		 359e1000_irq_enable(struct e1000_adapter *adapter)
360{
96838a40 361 if (likely(atomic_dec_and_test(&adapter->irq_sem))) {
1da177e4
LT		 362 E1000_WRITE_REG(&adapter->hw, IMS, IMS_ENABLE_MASK);
363 E1000_WRITE_FLUSH(&adapter->hw);
364 }
365}
3ad2cc67
AB		 366
367static void
2d7edb92
MC		 368e1000_update_mng_vlan(struct e1000_adapter *adapter)
369{
370 struct net_device *netdev = adapter->netdev;
371 uint16_t vid = adapter->hw.mng_cookie.vlan_id;
372 uint16_t old_vid = adapter->mng_vlan_id;
96838a40 373 if (adapter->vlgrp) {
5c15bdec 374 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
96838a40 375 if (adapter->hw.mng_cookie.status &
2d7edb92
MC		 376 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) {
377 e1000_vlan_rx_add_vid(netdev, vid);
378 adapter->mng_vlan_id = vid;
379 } else
380 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40
JB		 381
382 if ((old_vid != (uint16_t)E1000_MNG_VLAN_NONE) &&
383 (vid != old_vid) &&
5c15bdec 384 !vlan_group_get_device(adapter->vlgrp, old_vid))
2d7edb92 385 e1000_vlan_rx_kill_vid(netdev, old_vid);
c5f226fe
JK		 386 } else
387 adapter->mng_vlan_id = vid;
2d7edb92
MC		 388 }
389}
b55ccb35
JK		 390
391/**
392 * e1000_release_hw_control - release control of the h/w to f/w
393 * @adapter: address of board private structure
394 *
395 * e1000_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
396 * For ASF and Pass Through versions of f/w this means that the
397 * driver is no longer loaded. For AMT version (only with 82573) i
90fb5135 398 * of the f/w this means that the network i/f is closed.
76c224bc 399 *
b55ccb35
JK		 400 **/
401
e619d523 402static void
b55ccb35
JK		 403e1000_release_hw_control(struct e1000_adapter *adapter)
404{
405 uint32_t ctrl_ext;
406 uint32_t swsm;
407
408 /* Let firmware taken over control of h/w */
409 switch (adapter->hw.mac_type) {
b55ccb35
JK		 410 case e1000_82573:
411 swsm = E1000_READ_REG(&adapter->hw, SWSM);
412 E1000_WRITE_REG(&adapter->hw, SWSM,
413 swsm & ~E1000_SWSM_DRV_LOAD);
31d76442
BA		 414 break;
415 case e1000_82571:
416 case e1000_82572:
417 case e1000_80003es2lan:
cd94dd0b 418 case e1000_ich8lan:
31d76442 419 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
cd94dd0b 420 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
31d76442 421 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 422 break;
b55ccb35
JK		 423 default:
424 break;
425 }
426}
427
428/**
429 * e1000_get_hw_control - get control of the h/w from f/w
430 * @adapter: address of board private structure
431 *
432 * e1000_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
76c224bc
AK		 433 * For ASF and Pass Through versions of f/w this means that
434 * the driver is loaded. For AMT version (only with 82573)
90fb5135 435 * of the f/w this means that the network i/f is open.
76c224bc 436 *
b55ccb35
JK		 437 **/
438
e619d523 439static void
b55ccb35
JK		 440e1000_get_hw_control(struct e1000_adapter *adapter)
441{
442 uint32_t ctrl_ext;
443 uint32_t swsm;
90fb5135 444
b55ccb35
JK		 445 /* Let firmware know the driver has taken over */
446 switch (adapter->hw.mac_type) {
b55ccb35
JK		 447 case e1000_82573:
448 swsm = E1000_READ_REG(&adapter->hw, SWSM);
449 E1000_WRITE_REG(&adapter->hw, SWSM,
450 swsm | E1000_SWSM_DRV_LOAD);
451 break;
31d76442
BA		 452 case e1000_82571:
453 case e1000_82572:
454 case e1000_80003es2lan:
cd94dd0b 455 case e1000_ich8lan:
31d76442
BA		 456 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
457 E1000_WRITE_REG(&adapter->hw, CTRL_EXT,
458 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
cd94dd0b 459 break;
b55ccb35
JK		 460 default:
461 break;
462 }
463}
464
0fccd0e9
JG		 465static void
466e1000_init_manageability(struct e1000_adapter *adapter)
467{
468 if (adapter->en_mng_pt) {
469 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
470
471 /* disable hardware interception of ARP */
472 manc &= ~(E1000_MANC_ARP_EN);
473
474 /* enable receiving management packets to the host */
475 /* this will probably generate destination unreachable messages
476 * from the host OS, but the packets will be handled on SMBUS */
477 if (adapter->hw.has_manc2h) {
478 uint32_t manc2h = E1000_READ_REG(&adapter->hw, MANC2H);
479
480 manc |= E1000_MANC_EN_MNG2HOST;
481#define E1000_MNG2HOST_PORT_623 (1 << 5)
482#define E1000_MNG2HOST_PORT_664 (1 << 6)
483 manc2h |= E1000_MNG2HOST_PORT_623;
484 manc2h |= E1000_MNG2HOST_PORT_664;
485 E1000_WRITE_REG(&adapter->hw, MANC2H, manc2h);
486 }
487
488 E1000_WRITE_REG(&adapter->hw, MANC, manc);
489 }
490}
491
492static void
493e1000_release_manageability(struct e1000_adapter *adapter)
494{
495 if (adapter->en_mng_pt) {
496 uint32_t manc = E1000_READ_REG(&adapter->hw, MANC);
497
498 /* re-enable hardware interception of ARP */
499 manc |= E1000_MANC_ARP_EN;
500
501 if (adapter->hw.has_manc2h)
502 manc &= ~E1000_MANC_EN_MNG2HOST;
503
504 /* don't explicitly have to mess with MANC2H since
505 * MANC has an enable disable that gates MANC2H */
506
507 E1000_WRITE_REG(&adapter->hw, MANC, manc);
508 }
509}
510
e0aac5a2
AK		 511/**
512 * e1000_configure - configure the hardware for RX and TX
513 * @adapter = private board structure
514 **/
515static void e1000_configure(struct e1000_adapter *adapter)
1da177e4
LT		 516{
517 struct net_device *netdev = adapter->netdev;
2db10a08 518 int i;
1da177e4 519
1da177e4
LT		 520 e1000_set_multi(netdev);
521
522 e1000_restore_vlan(adapter);
0fccd0e9 523 e1000_init_manageability(adapter);
1da177e4
LT		 524
525 e1000_configure_tx(adapter);
526 e1000_setup_rctl(adapter);
527 e1000_configure_rx(adapter);
72d64a43
JK		 528 /* call E1000_DESC_UNUSED which always leaves
529 * at least 1 descriptor unused to make sure
530 * next_to_use != next_to_clean */
f56799ea 531 for (i = 0; i < adapter->num_rx_queues; i++) {
72d64a43 532 struct e1000_rx_ring *ring = &adapter->rx_ring[i];
a292ca6e
JK		 533 adapter->alloc_rx_buf(adapter, ring,
534 E1000_DESC_UNUSED(ring));
f56799ea 535 }
1da177e4 536
7bfa4816 537 adapter->tx_queue_len = netdev->tx_queue_len;
e0aac5a2
AK		 538}
539
540int e1000_up(struct e1000_adapter *adapter)
541{
542 /* hardware has been reset, we need to reload some things */
543 e1000_configure(adapter);
544
545 clear_bit(__E1000_DOWN, &adapter->flags);
7bfa4816 546
1da177e4 547#ifdef CONFIG_E1000_NAPI
bea3348e 548 napi_enable(&adapter->napi);
1da177e4 549#endif
5de55624
MC		 550 e1000_irq_enable(adapter);
551
79f3d399
JB		 552 /* fire a link change interrupt to start the watchdog */
553 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1da177e4
LT		 554 return 0;
555}
556
79f05bf0
AK		 557/**
558 * e1000_power_up_phy - restore link in case the phy was powered down
559 * @adapter: address of board private structure
560 *
561 * The phy may be powered down to save power and turn off link when the
562 * driver is unloaded and wake on lan is not enabled (among others)
563 * *** this routine MUST be followed by a call to e1000_reset ***
564 *
565 **/
566
d658266e 567void e1000_power_up_phy(struct e1000_adapter *adapter)
79f05bf0
AK		 568{
569 uint16_t mii_reg = 0;
570
571 /* Just clear the power down bit to wake the phy back up */
572 if (adapter->hw.media_type == e1000_media_type_copper) {
573 /* according to the manual, the phy will retain its
574 * settings across a power-down/up cycle */
575 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
576 mii_reg &= ~MII_CR_POWER_DOWN;
577 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
578 }
579}
580
581static void e1000_power_down_phy(struct e1000_adapter *adapter)
582{
61c2505f
BA		 583 /* Power down the PHY so no link is implied when interface is down *
584 * The PHY cannot be powered down if any of the following is TRUE *
79f05bf0
AK		 585 * (a) WoL is enabled
586 * (b) AMT is active
587 * (c) SoL/IDER session is active */
588 if (!adapter->wol && adapter->hw.mac_type >= e1000_82540 &&
61c2505f 589 adapter->hw.media_type == e1000_media_type_copper) {
79f05bf0 590 uint16_t mii_reg = 0;
61c2505f
BA		 591
592 switch (adapter->hw.mac_type) {
593 case e1000_82540:
594 case e1000_82545:
595 case e1000_82545_rev_3:
596 case e1000_82546:
597 case e1000_82546_rev_3:
598 case e1000_82541:
599 case e1000_82541_rev_2:
600 case e1000_82547:
601 case e1000_82547_rev_2:
602 if (E1000_READ_REG(&adapter->hw, MANC) &
603 E1000_MANC_SMBUS_EN)
604 goto out;
605 break;
606 case e1000_82571:
607 case e1000_82572:
608 case e1000_82573:
609 case e1000_80003es2lan:
610 case e1000_ich8lan:
611 if (e1000_check_mng_mode(&adapter->hw) ||
612 e1000_check_phy_reset_block(&adapter->hw))
613 goto out;
614 break;
615 default:
616 goto out;
617 }
79f05bf0
AK		 618 e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &mii_reg);
619 mii_reg |= MII_CR_POWER_DOWN;
620 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, mii_reg);
621 mdelay(1);
622 }
61c2505f
BA		 623out:
624 return;
79f05bf0
AK		 625}
626
1da177e4
LT		 627void
628e1000_down(struct e1000_adapter *adapter)
629{
630 struct net_device *netdev = adapter->netdev;
631
1314bbf3
AK		 632 /* signal that we're down so the interrupt handler does not
633 * reschedule our watchdog timer */
634 set_bit(__E1000_DOWN, &adapter->flags);
635
e0aac5a2 636#ifdef CONFIG_E1000_NAPI
bea3348e 637 napi_disable(&adapter->napi);
e0aac5a2 638#endif
1da177e4 639 e1000_irq_disable(adapter);
c1605eb3 640
1da177e4
LT		 641 del_timer_sync(&adapter->tx_fifo_stall_timer);
642 del_timer_sync(&adapter->watchdog_timer);
643 del_timer_sync(&adapter->phy_info_timer);
644
7bfa4816 645 netdev->tx_queue_len = adapter->tx_queue_len;
1da177e4
LT		 646 adapter->link_speed = 0;
647 adapter->link_duplex = 0;
648 netif_carrier_off(netdev);
649 netif_stop_queue(netdev);
650
651 e1000_reset(adapter);
581d708e
MC		 652 e1000_clean_all_tx_rings(adapter);
653 e1000_clean_all_rx_rings(adapter);
1da177e4 654}
1da177e4 655
2db10a08
AK		 656void
657e1000_reinit_locked(struct e1000_adapter *adapter)
658{
659 WARN_ON(in_interrupt());
660 while (test_and_set_bit(__E1000_RESETTING, &adapter->flags))
661 msleep(1);
662 e1000_down(adapter);
663 e1000_up(adapter);
664 clear_bit(__E1000_RESETTING, &adapter->flags);
1da177e4
LT		 665}
666
667void
668e1000_reset(struct e1000_adapter *adapter)
669{
018ea44e 670 uint32_t pba = 0, tx_space, min_tx_space, min_rx_space;
1125ecbc 671 uint16_t fc_high_water_mark = E1000_FC_HIGH_DIFF;
018ea44e 672 boolean_t legacy_pba_adjust = FALSE;
1da177e4
LT		 673
674 /* Repartition Pba for greater than 9k mtu
675 * To take effect CTRL.RST is required.
676 */
677
2d7edb92 678 switch (adapter->hw.mac_type) {
018ea44e
BA		 679 case e1000_82542_rev2_0:
680 case e1000_82542_rev2_1:
681 case e1000_82543:
682 case e1000_82544:
683 case e1000_82540:
684 case e1000_82541:
685 case e1000_82541_rev_2:
686 legacy_pba_adjust = TRUE;
687 pba = E1000_PBA_48K;
688 break;
689 case e1000_82545:
690 case e1000_82545_rev_3:
691 case e1000_82546:
692 case e1000_82546_rev_3:
693 pba = E1000_PBA_48K;
694 break;
2d7edb92 695 case e1000_82547:
0e6ef3e0 696 case e1000_82547_rev_2:
018ea44e 697 legacy_pba_adjust = TRUE;
2d7edb92
MC		 698 pba = E1000_PBA_30K;
699 break;
868d5309
MC		 700 case e1000_82571:
701 case e1000_82572:
6418ecc6 702 case e1000_80003es2lan:
868d5309
MC		 703 pba = E1000_PBA_38K;
704 break;
2d7edb92 705 case e1000_82573:
018ea44e 706 pba = E1000_PBA_20K;
2d7edb92 707 break;
cd94dd0b
AK		 708 case e1000_ich8lan:
709 pba = E1000_PBA_8K;
018ea44e
BA		 710 case e1000_undefined:
711 case e1000_num_macs:
2d7edb92
MC		 712 break;
713 }
714
018ea44e
BA		 715 if (legacy_pba_adjust == TRUE) {
716 if (adapter->netdev->mtu > E1000_RXBUFFER_8192)
717 pba -= 8; /* allocate more FIFO for Tx */
2d7edb92 718
018ea44e
BA		 719 if (adapter->hw.mac_type == e1000_82547) {
720 adapter->tx_fifo_head = 0;
721 adapter->tx_head_addr = pba << E1000_TX_HEAD_ADDR_SHIFT;
722 adapter->tx_fifo_size =
723 (E1000_PBA_40K - pba) << E1000_PBA_BYTES_SHIFT;
724 atomic_set(&adapter->tx_fifo_stall, 0);
725 }
726 } else if (adapter->hw.max_frame_size > MAXIMUM_ETHERNET_FRAME_SIZE) {
727 /* adjust PBA for jumbo frames */
728 E1000_WRITE_REG(&adapter->hw, PBA, pba);
729
730 /* To maintain wire speed transmits, the Tx FIFO should be
731 * large enough to accomodate two full transmit packets,
732 * rounded up to the next 1KB and expressed in KB. Likewise,
733 * the Rx FIFO should be large enough to accomodate at least
734 * one full receive packet and is similarly rounded up and
735 * expressed in KB. */
736 pba = E1000_READ_REG(&adapter->hw, PBA);
737 /* upper 16 bits has Tx packet buffer allocation size in KB */
738 tx_space = pba >> 16;
739 /* lower 16 bits has Rx packet buffer allocation size in KB */
740 pba &= 0xffff;
741 /* don't include ethernet FCS because hardware appends/strips */
742 min_rx_space = adapter->netdev->mtu + ENET_HEADER_SIZE +
743 VLAN_TAG_SIZE;
744 min_tx_space = min_rx_space;
745 min_tx_space *= 2;
9099cfb9 746 min_tx_space = ALIGN(min_tx_space, 1024);
018ea44e 747 min_tx_space >>= 10;
9099cfb9 748 min_rx_space = ALIGN(min_rx_space, 1024);
018ea44e
BA		 749 min_rx_space >>= 10;
750
751 /* If current Tx allocation is less than the min Tx FIFO size,
752 * and the min Tx FIFO size is less than the current Rx FIFO
753 * allocation, take space away from current Rx allocation */
754 if (tx_space < min_tx_space &&
755 ((min_tx_space - tx_space) < pba)) {
756 pba = pba - (min_tx_space - tx_space);
757
758 /* PCI/PCIx hardware has PBA alignment constraints */
759 switch (adapter->hw.mac_type) {
760 case e1000_82545 ... e1000_82546_rev_3:
761 pba &= ~(E1000_PBA_8K - 1);
762 break;
763 default:
764 break;
765 }
766
767 /* if short on rx space, rx wins and must trump tx
768 * adjustment or use Early Receive if available */
769 if (pba < min_rx_space) {
770 switch (adapter->hw.mac_type) {
771 case e1000_82573:
772 /* ERT enabled in e1000_configure_rx */
773 break;
774 default:
775 pba = min_rx_space;
776 break;
777 }
778 }
779 }
1da177e4 780 }
2d7edb92 781
1da177e4
LT		 782 E1000_WRITE_REG(&adapter->hw, PBA, pba);
783
784 /* flow control settings */
f11b7f85
JK		 785 /* Set the FC high water mark to 90% of the FIFO size.
786 * Required to clear last 3 LSB */
787 fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
cd94dd0b
AK		 788 /* We can't use 90% on small FIFOs because the remainder
789 * would be less than 1 full frame. In this case, we size
790 * it to allow at least a full frame above the high water
791 * mark. */
792 if (pba < E1000_PBA_16K)
793 fc_high_water_mark = (pba * 1024) - 1600;
f11b7f85
JK		 794
795 adapter->hw.fc_high_water = fc_high_water_mark;
796 adapter->hw.fc_low_water = fc_high_water_mark - 8;
87041639
JK		 797 if (adapter->hw.mac_type == e1000_80003es2lan)
798 adapter->hw.fc_pause_time = 0xFFFF;
799 else
800 adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
1da177e4
LT		 801 adapter->hw.fc_send_xon = 1;
802 adapter->hw.fc = adapter->hw.original_fc;
803
2d7edb92 804 /* Allow time for pending master requests to run */
1da177e4 805 e1000_reset_hw(&adapter->hw);
96838a40 806 if (adapter->hw.mac_type >= e1000_82544)
1da177e4 807 E1000_WRITE_REG(&adapter->hw, WUC, 0);
09ae3e88 808
96838a40 809 if (e1000_init_hw(&adapter->hw))
1da177e4 810 DPRINTK(PROBE, ERR, "Hardware Error\n");
2d7edb92 811 e1000_update_mng_vlan(adapter);
3d5460a0
JB		 812
813 /* if (adapter->hwflags & HWFLAGS_PHY_PWR_BIT) { */
814 if (adapter->hw.mac_type >= e1000_82544 &&
815 adapter->hw.mac_type <= e1000_82547_rev_2 &&
816 adapter->hw.autoneg == 1 &&
817 adapter->hw.autoneg_advertised == ADVERTISE_1000_FULL) {
818 uint32_t ctrl = E1000_READ_REG(&adapter->hw, CTRL);
819 /* clear phy power management bit if we are in gig only mode,
820 * which if enabled will attempt negotiation to 100Mb, which
821 * can cause a loss of link at power off or driver unload */
822 ctrl &= ~E1000_CTRL_SWDPIN3;
823 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
824 }
825
1da177e4
LT		 826 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
827 E1000_WRITE_REG(&adapter->hw, VET, ETHERNET_IEEE_VLAN_TYPE);
828
829 e1000_reset_adaptive(&adapter->hw);
830 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
9a53a202
AK		 831
832 if (!adapter->smart_power_down &&
833 (adapter->hw.mac_type == e1000_82571 ||
834 adapter->hw.mac_type == e1000_82572)) {
835 uint16_t phy_data = 0;
836 /* speed up time to link by disabling smart power down, ignore
837 * the return value of this function because there is nothing
838 * different we would do if it failed */
839 e1000_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
840 &phy_data);
841 phy_data &= ~IGP02E1000_PM_SPD;
842 e1000_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
843 phy_data);
844 }
845
0fccd0e9 846 e1000_release_manageability(adapter);
1da177e4
LT		 847}
848
849/**
850 * e1000_probe - Device Initialization Routine
851 * @pdev: PCI device information struct
852 * @ent: entry in e1000_pci_tbl
853 *
854 * Returns 0 on success, negative on failure
855 *
856 * e1000_probe initializes an adapter identified by a pci_dev structure.
857 * The OS initialization, configuring of the adapter private structure,
858 * and a hardware reset occur.
859 **/
860
861static int __devinit
862e1000_probe(struct pci_dev *pdev,
863 const struct pci_device_id *ent)
864{
865 struct net_device *netdev;
866 struct e1000_adapter *adapter;
2d7edb92 867 unsigned long mmio_start, mmio_len;
cd94dd0b 868 unsigned long flash_start, flash_len;
2d7edb92 869
1da177e4 870 static int cards_found = 0;
120cd576 871 static int global_quad_port_a = 0; /* global ksp3 port a indication */
2d7edb92 872 int i, err, pci_using_dac;
120cd576 873 uint16_t eeprom_data = 0;
1da177e4 874 uint16_t eeprom_apme_mask = E1000_EEPROM_APME;
96838a40 875 if ((err = pci_enable_device(pdev)))
1da177e4
LT		 876 return err;
877
cd94dd0b
AK		 878 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)) &&
879 !(err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))) {
1da177e4
LT		 880 pci_using_dac = 1;
881 } else {
cd94dd0b
AK		 882 if ((err = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) &&
883 (err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))) {
1da177e4 884 E1000_ERR("No usable DMA configuration, aborting\n");
6dd62ab0 885 goto err_dma;
1da177e4
LT		 886 }
887 pci_using_dac = 0;
888 }
889
96838a40 890 if ((err = pci_request_regions(pdev, e1000_driver_name)))
6dd62ab0 891 goto err_pci_reg;
1da177e4
LT		 892
893 pci_set_master(pdev);
894
6dd62ab0 895 err = -ENOMEM;
1da177e4 896 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6dd62ab0 897 if (!netdev)
1da177e4 898 goto err_alloc_etherdev;
1da177e4 899
1da177e4
LT		 900 SET_NETDEV_DEV(netdev, &pdev->dev);
901
902 pci_set_drvdata(pdev, netdev);
60490fe0 903 adapter = netdev_priv(netdev);
1da177e4
LT		 904 adapter->netdev = netdev;
905 adapter->pdev = pdev;
906 adapter->hw.back = adapter;
907 adapter->msg_enable = (1 << debug) - 1;
908
909 mmio_start = pci_resource_start(pdev, BAR_0);
910 mmio_len = pci_resource_len(pdev, BAR_0);
911
6dd62ab0 912 err = -EIO;
1da177e4 913 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6dd62ab0 914 if (!adapter->hw.hw_addr)
1da177e4 915 goto err_ioremap;
1da177e4 916
96838a40
JB		 917 for (i = BAR_1; i <= BAR_5; i++) {
918 if (pci_resource_len(pdev, i) == 0)
1da177e4 919 continue;
96838a40 920 if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
1da177e4
LT		 921 adapter->hw.io_base = pci_resource_start(pdev, i);
922 break;
923 }
924 }
925
926 netdev->open = &e1000_open;
927 netdev->stop = &e1000_close;
928 netdev->hard_start_xmit = &e1000_xmit_frame;
929 netdev->get_stats = &e1000_get_stats;
930 netdev->set_multicast_list = &e1000_set_multi;
931 netdev->set_mac_address = &e1000_set_mac;
932 netdev->change_mtu = &e1000_change_mtu;
933 netdev->do_ioctl = &e1000_ioctl;
934 e1000_set_ethtool_ops(netdev);
935 netdev->tx_timeout = &e1000_tx_timeout;
936 netdev->watchdog_timeo = 5 * HZ;
937#ifdef CONFIG_E1000_NAPI
bea3348e 938 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
1da177e4
LT		 939#endif
940 netdev->vlan_rx_register = e1000_vlan_rx_register;
941 netdev->vlan_rx_add_vid = e1000_vlan_rx_add_vid;
942 netdev->vlan_rx_kill_vid = e1000_vlan_rx_kill_vid;
943#ifdef CONFIG_NET_POLL_CONTROLLER
944 netdev->poll_controller = e1000_netpoll;
945#endif
0eb5a34c 946 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1da177e4
LT		 947
948 netdev->mem_start = mmio_start;
949 netdev->mem_end = mmio_start + mmio_len;
950 netdev->base_addr = adapter->hw.io_base;
951
952 adapter->bd_number = cards_found;
953
954 /* setup the private structure */
955
96838a40 956 if ((err = e1000_sw_init(adapter)))
1da177e4
LT		 957 goto err_sw_init;
958
6dd62ab0 959 err = -EIO;
cd94dd0b
AK		 960 /* Flash BAR mapping must happen after e1000_sw_init
961 * because it depends on mac_type */
962 if ((adapter->hw.mac_type == e1000_ich8lan) &&
963 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
964 flash_start = pci_resource_start(pdev, 1);
965 flash_len = pci_resource_len(pdev, 1);
966 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6dd62ab0 967 if (!adapter->hw.flash_address)
cd94dd0b 968 goto err_flashmap;
cd94dd0b
AK		 969 }
970
6dd62ab0 971 if (e1000_check_phy_reset_block(&adapter->hw))
2d7edb92
MC		 972 DPRINTK(PROBE, INFO, "PHY reset is blocked due to SOL/IDER session.\n");
973
96838a40 974 if (adapter->hw.mac_type >= e1000_82543) {
1da177e4
LT		 975 netdev->features = NETIF_F_SG |
976 NETIF_F_HW_CSUM |
977 NETIF_F_HW_VLAN_TX |
978 NETIF_F_HW_VLAN_RX |
979 NETIF_F_HW_VLAN_FILTER;
cd94dd0b
AK		 980 if (adapter->hw.mac_type == e1000_ich8lan)
981 netdev->features &= ~NETIF_F_HW_VLAN_FILTER;
1da177e4
LT		 982 }
983
96838a40 984 if ((adapter->hw.mac_type >= e1000_82544) &&
1da177e4
LT		 985 (adapter->hw.mac_type != e1000_82547))
986 netdev->features |= NETIF_F_TSO;
2d7edb92 987
96838a40 988 if (adapter->hw.mac_type > e1000_82547_rev_2)
87ca4e5b 989 netdev->features |= NETIF_F_TSO6;
96838a40 990 if (pci_using_dac)
1da177e4
LT		 991 netdev->features |= NETIF_F_HIGHDMA;
992
76c224bc
AK		 993 netdev->features |= NETIF_F_LLTX;
994
2d7edb92
MC		 995 adapter->en_mng_pt = e1000_enable_mng_pass_thru(&adapter->hw);
996
cd94dd0b
AK		 997 /* initialize eeprom parameters */
998
999 if (e1000_init_eeprom_params(&adapter->hw)) {
1000 E1000_ERR("EEPROM initialization failed\n");
6dd62ab0 1001 goto err_eeprom;
cd94dd0b
AK		 1002 }
1003
96838a40 1004 /* before reading the EEPROM, reset the controller to
1da177e4 1005 * put the device in a known good starting state */
96838a40 1006
1da177e4
LT		 1007 e1000_reset_hw(&adapter->hw);
1008
1009 /* make sure the EEPROM is good */
1010
96838a40 1011 if (e1000_validate_eeprom_checksum(&adapter->hw) < 0) {
1da177e4 1012 DPRINTK(PROBE, ERR, "The EEPROM Checksum Is Not Valid\n");
1da177e4
LT		 1013 goto err_eeprom;
1014 }
1015
1016 /* copy the MAC address out of the EEPROM */
1017
96838a40 1018 if (e1000_read_mac_addr(&adapter->hw))
1da177e4
LT		 1019 DPRINTK(PROBE, ERR, "EEPROM Read Error\n");
1020 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
9beb0ac1 1021 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1da177e4 1022
96838a40 1023 if (!is_valid_ether_addr(netdev->perm_addr)) {
1da177e4 1024 DPRINTK(PROBE, ERR, "Invalid MAC Address\n");
1da177e4
LT		 1025 goto err_eeprom;
1026 }
1027
1da177e4
LT		 1028 e1000_get_bus_info(&adapter->hw);
1029
1030 init_timer(&adapter->tx_fifo_stall_timer);
1031 adapter->tx_fifo_stall_timer.function = &e1000_82547_tx_fifo_stall;
1032 adapter->tx_fifo_stall_timer.data = (unsigned long) adapter;
1033
1034 init_timer(&adapter->watchdog_timer);
1035 adapter->watchdog_timer.function = &e1000_watchdog;
1036 adapter->watchdog_timer.data = (unsigned long) adapter;
1037
1da177e4
LT		 1038 init_timer(&adapter->phy_info_timer);
1039 adapter->phy_info_timer.function = &e1000_update_phy_info;
1040 adapter->phy_info_timer.data = (unsigned long) adapter;
1041
65f27f38 1042 INIT_WORK(&adapter->reset_task, e1000_reset_task);
1da177e4 1043
1da177e4
LT		 1044 e1000_check_options(adapter);
1045
1046 /* Initial Wake on LAN setting
1047 * If APM wake is enabled in the EEPROM,
1048 * enable the ACPI Magic Packet filter
1049 */
1050
96838a40 1051 switch (adapter->hw.mac_type) {
1da177e4
LT		 1052 case e1000_82542_rev2_0:
1053 case e1000_82542_rev2_1:
1054 case e1000_82543:
1055 break;
1056 case e1000_82544:
1057 e1000_read_eeprom(&adapter->hw,
1058 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1059 eeprom_apme_mask = E1000_EEPROM_82544_APM;
1060 break;
cd94dd0b
AK		 1061 case e1000_ich8lan:
1062 e1000_read_eeprom(&adapter->hw,
1063 EEPROM_INIT_CONTROL1_REG, 1, &eeprom_data);
1064 eeprom_apme_mask = E1000_EEPROM_ICH8_APME;
1065 break;
1da177e4
LT		 1066 case e1000_82546:
1067 case e1000_82546_rev_3:
fd803241 1068 case e1000_82571:
6418ecc6 1069 case e1000_80003es2lan:
96838a40 1070 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1){
1da177e4
LT		 1071 e1000_read_eeprom(&adapter->hw,
1072 EEPROM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
1073 break;
1074 }
1075 /* Fall Through */
1076 default:
1077 e1000_read_eeprom(&adapter->hw,
1078 EEPROM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
1079 break;
1080 }
96838a40 1081 if (eeprom_data & eeprom_apme_mask)
120cd576
JB		 1082 adapter->eeprom_wol |= E1000_WUFC_MAG;
1083
1084 /* now that we have the eeprom settings, apply the special cases
1085 * where the eeprom may be wrong or the board simply won't support
1086 * wake on lan on a particular port */
1087 switch (pdev->device) {
1088 case E1000_DEV_ID_82546GB_PCIE:
1089 adapter->eeprom_wol = 0;
1090 break;
1091 case E1000_DEV_ID_82546EB_FIBER:
1092 case E1000_DEV_ID_82546GB_FIBER:
1093 case E1000_DEV_ID_82571EB_FIBER:
1094 /* Wake events only supported on port A for dual fiber
1095 * regardless of eeprom setting */
1096 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_FUNC_1)
1097 adapter->eeprom_wol = 0;
1098 break;
1099 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
5881cde8 1100 case E1000_DEV_ID_82571EB_QUAD_COPPER:
ce57a02c 1101 case E1000_DEV_ID_82571EB_QUAD_FIBER:
fc2307d0 1102 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
f4ec7f98 1103 case E1000_DEV_ID_82571PT_QUAD_COPPER:
120cd576
JB		 1104 /* if quad port adapter, disable WoL on all but port A */
1105 if (global_quad_port_a != 0)
1106 adapter->eeprom_wol = 0;
1107 else
1108 adapter->quad_port_a = 1;
1109 /* Reset for multiple quad port adapters */
1110 if (++global_quad_port_a == 4)
1111 global_quad_port_a = 0;
1112 break;
1113 }
1114
1115 /* initialize the wol settings based on the eeprom settings */
1116 adapter->wol = adapter->eeprom_wol;
1da177e4 1117
fb3d47d4
JK		 1118 /* print bus type/speed/width info */
1119 {
1120 struct e1000_hw *hw = &adapter->hw;
1121 DPRINTK(PROBE, INFO, "(PCI%s:%s:%s) ",
1122 ((hw->bus_type == e1000_bus_type_pcix) ? "-X" :
1123 (hw->bus_type == e1000_bus_type_pci_express ? " Express":"")),
1124 ((hw->bus_speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
1125 (hw->bus_speed == e1000_bus_speed_133) ? "133MHz" :
1126 (hw->bus_speed == e1000_bus_speed_120) ? "120MHz" :
1127 (hw->bus_speed == e1000_bus_speed_100) ? "100MHz" :
1128 (hw->bus_speed == e1000_bus_speed_66) ? "66MHz" : "33MHz"),
1129 ((hw->bus_width == e1000_bus_width_64) ? "64-bit" :
1130 (hw->bus_width == e1000_bus_width_pciex_4) ? "Width x4" :
1131 (hw->bus_width == e1000_bus_width_pciex_1) ? "Width x1" :
1132 "32-bit"));
1133 }
1134
1135 for (i = 0; i < 6; i++)
1136 printk("%2.2x%c", netdev->dev_addr[i], i == 5 ? '\n' : ':');
1137
1da177e4
LT		 1138 /* reset the hardware with the new settings */
1139 e1000_reset(adapter);
1140
b55ccb35
JK		 1141 /* If the controller is 82573 and f/w is AMT, do not set
1142 * DRV_LOAD until the interface is up. For all other cases,
1143 * let the f/w know that the h/w is now under the control
1144 * of the driver. */
1145 if (adapter->hw.mac_type != e1000_82573 ||
1146 !e1000_check_mng_mode(&adapter->hw))
1147 e1000_get_hw_control(adapter);
2d7edb92 1148
1314bbf3
AK		 1149 /* tell the stack to leave us alone until e1000_open() is called */
1150 netif_carrier_off(netdev);
1151 netif_stop_queue(netdev);
416b5d10
AK		 1152
1153 strcpy(netdev->name, "eth%d");
1154 if ((err = register_netdev(netdev)))
1155 goto err_register;
1314bbf3 1156
1da177e4
LT		 1157 DPRINTK(PROBE, INFO, "Intel(R) PRO/1000 Network Connection\n");
1158
1159 cards_found++;
1160 return 0;
1161
1162err_register:
6dd62ab0
VA		 1163 e1000_release_hw_control(adapter);
1164err_eeprom:
1165 if (!e1000_check_phy_reset_block(&adapter->hw))
1166 e1000_phy_hw_reset(&adapter->hw);
1167
cd94dd0b
AK		 1168 if (adapter->hw.flash_address)
1169 iounmap(adapter->hw.flash_address);
1170err_flashmap:
6dd62ab0
VA		 1171#ifdef CONFIG_E1000_NAPI
1172 for (i = 0; i < adapter->num_rx_queues; i++)
1173 dev_put(&adapter->polling_netdev[i]);
1174#endif
1175
1176 kfree(adapter->tx_ring);
1177 kfree(adapter->rx_ring);
1178#ifdef CONFIG_E1000_NAPI
1179 kfree(adapter->polling_netdev);
1180#endif
1da177e4 1181err_sw_init:
1da177e4
LT		 1182 iounmap(adapter->hw.hw_addr);
1183err_ioremap:
1184 free_netdev(netdev);
1185err_alloc_etherdev:
1186 pci_release_regions(pdev);
6dd62ab0
VA		 1187err_pci_reg:
1188err_dma:
1189 pci_disable_device(pdev);
1da177e4
LT		 1190 return err;
1191}
1192
1193/**
1194 * e1000_remove - Device Removal Routine
1195 * @pdev: PCI device information struct
1196 *
1197 * e1000_remove is called by the PCI subsystem to alert the driver
1198 * that it should release a PCI device. The could be caused by a
1199 * Hot-Plug event, or because the driver is going to be removed from
1200 * memory.
1201 **/
1202
1203static void __devexit
1204e1000_remove(struct pci_dev *pdev)
1205{
1206 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 1207 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e
MC		 1208#ifdef CONFIG_E1000_NAPI
1209 int i;
1210#endif
1da177e4 1211
28e53bdd 1212 cancel_work_sync(&adapter->reset_task);
be2b28ed 1213
0fccd0e9 1214 e1000_release_manageability(adapter);
1da177e4 1215
b55ccb35
JK		 1216 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1217 * would have already happened in close and is redundant. */
1218 e1000_release_hw_control(adapter);
2d7edb92 1219
581d708e 1220#ifdef CONFIG_E1000_NAPI
f56799ea 1221 for (i = 0; i < adapter->num_rx_queues; i++)
15333061 1222 dev_put(&adapter->polling_netdev[i]);
581d708e 1223#endif
1da177e4 1224
bea3348e
SH		 1225 unregister_netdev(netdev);
1226
96838a40 1227 if (!e1000_check_phy_reset_block(&adapter->hw))
2d7edb92 1228 e1000_phy_hw_reset(&adapter->hw);
1da177e4 1229
24025e4e
MC		 1230 kfree(adapter->tx_ring);
1231 kfree(adapter->rx_ring);
1232#ifdef CONFIG_E1000_NAPI
1233 kfree(adapter->polling_netdev);
1234#endif
1235
1da177e4 1236 iounmap(adapter->hw.hw_addr);
cd94dd0b
AK		 1237 if (adapter->hw.flash_address)
1238 iounmap(adapter->hw.flash_address);
1da177e4
LT		 1239 pci_release_regions(pdev);
1240
1241 free_netdev(netdev);
1242
1243 pci_disable_device(pdev);
1244}
1245
1246/**
1247 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
1248 * @adapter: board private structure to initialize
1249 *
1250 * e1000_sw_init initializes the Adapter private data structure.
1251 * Fields are initialized based on PCI device information and
1252 * OS network device settings (MTU size).
1253 **/
1254
1255static int __devinit
1256e1000_sw_init(struct e1000_adapter *adapter)
1257{
1258 struct e1000_hw *hw = &adapter->hw;
1259 struct net_device *netdev = adapter->netdev;
1260 struct pci_dev *pdev = adapter->pdev;
581d708e
MC		 1261#ifdef CONFIG_E1000_NAPI
1262 int i;
1263#endif
1da177e4
LT		 1264
1265 /* PCI config space info */
1266
1267 hw->vendor_id = pdev->vendor;
1268 hw->device_id = pdev->device;
1269 hw->subsystem_vendor_id = pdev->subsystem_vendor;
1270 hw->subsystem_id = pdev->subsystem_device;
44c10138 1271 hw->revision_id = pdev->revision;
1da177e4
LT		 1272
1273 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
1274
eb0f8054 1275 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
9e2feace 1276 adapter->rx_ps_bsize0 = E1000_RXBUFFER_128;
1da177e4
LT		 1277 hw->max_frame_size = netdev->mtu +
1278 ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
1279 hw->min_frame_size = MINIMUM_ETHERNET_FRAME_SIZE;
1280
1281 /* identify the MAC */
1282
96838a40 1283 if (e1000_set_mac_type(hw)) {
1da177e4
LT		 1284 DPRINTK(PROBE, ERR, "Unknown MAC Type\n");
1285 return -EIO;
1286 }
1287
96838a40 1288 switch (hw->mac_type) {
1da177e4
LT		 1289 default:
1290 break;
1291 case e1000_82541:
1292 case e1000_82547:
1293 case e1000_82541_rev_2:
1294 case e1000_82547_rev_2:
1295 hw->phy_init_script = 1;
1296 break;
1297 }
1298
1299 e1000_set_media_type(hw);
1300
1301 hw->wait_autoneg_complete = FALSE;
1302 hw->tbi_compatibility_en = TRUE;
1303 hw->adaptive_ifs = TRUE;
1304
1305 /* Copper options */
1306
96838a40 1307 if (hw->media_type == e1000_media_type_copper) {
1da177e4
LT		 1308 hw->mdix = AUTO_ALL_MODES;
1309 hw->disable_polarity_correction = FALSE;
1310 hw->master_slave = E1000_MASTER_SLAVE;
1311 }
1312
f56799ea
JK		 1313 adapter->num_tx_queues = 1;
1314 adapter->num_rx_queues = 1;
581d708e
MC		 1315
1316 if (e1000_alloc_queues(adapter)) {
1317 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
1318 return -ENOMEM;
1319 }
1320
1321#ifdef CONFIG_E1000_NAPI
f56799ea 1322 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e 1323 adapter->polling_netdev[i].priv = adapter;
581d708e
MC		 1324 dev_hold(&adapter->polling_netdev[i]);
1325 set_bit(__LINK_STATE_START, &adapter->polling_netdev[i].state);
1326 }
7bfa4816 1327 spin_lock_init(&adapter->tx_queue_lock);
24025e4e
MC		 1328#endif
1329
47313054
HX		 1330 /* Explicitly disable IRQ since the NIC can be in any state. */
1331 atomic_set(&adapter->irq_sem, 0);
1332 e1000_irq_disable(adapter);
1333
1da177e4 1334 spin_lock_init(&adapter->stats_lock);
1da177e4 1335
1314bbf3
AK		 1336 set_bit(__E1000_DOWN, &adapter->flags);
1337
1da177e4
LT		 1338 return 0;
1339}
1340
581d708e
MC		 1341/**
1342 * e1000_alloc_queues - Allocate memory for all rings
1343 * @adapter: board private structure to initialize
1344 *
1345 * We allocate one ring per queue at run-time since we don't know the
1346 * number of queues at compile-time. The polling_netdev array is
1347 * intended for Multiqueue, but should work fine with a single queue.
1348 **/
1349
1350static int __devinit
1351e1000_alloc_queues(struct e1000_adapter *adapter)
1352{
1c7e5b12
YB		 1353 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
1354 sizeof(struct e1000_tx_ring), GFP_KERNEL);
581d708e
MC		 1355 if (!adapter->tx_ring)
1356 return -ENOMEM;
581d708e 1357
1c7e5b12
YB		 1358 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
1359 sizeof(struct e1000_rx_ring), GFP_KERNEL);
581d708e
MC		 1360 if (!adapter->rx_ring) {
1361 kfree(adapter->tx_ring);
1362 return -ENOMEM;
1363 }
581d708e
MC		 1364
1365#ifdef CONFIG_E1000_NAPI
1c7e5b12
YB		 1366 adapter->polling_netdev = kcalloc(adapter->num_rx_queues,
1367 sizeof(struct net_device),
1368 GFP_KERNEL);
581d708e
MC		 1369 if (!adapter->polling_netdev) {
1370 kfree(adapter->tx_ring);
1371 kfree(adapter->rx_ring);
1372 return -ENOMEM;
1373 }
581d708e
MC		 1374#endif
1375
1376 return E1000_SUCCESS;
1377}
1378
1da177e4
LT		 1379/**
1380 * e1000_open - Called when a network interface is made active
1381 * @netdev: network interface device structure
1382 *
1383 * Returns 0 on success, negative value on failure
1384 *
1385 * The open entry point is called when a network interface is made
1386 * active by the system (IFF_UP). At this point all resources needed
1387 * for transmit and receive operations are allocated, the interrupt
1388 * handler is registered with the OS, the watchdog timer is started,
1389 * and the stack is notified that the interface is ready.
1390 **/
1391
1392static int
1393e1000_open(struct net_device *netdev)
1394{
60490fe0 1395 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 1396 int err;
1397
2db10a08 1398 /* disallow open during test */
1314bbf3 1399 if (test_bit(__E1000_TESTING, &adapter->flags))
2db10a08
AK		 1400 return -EBUSY;
1401
1da177e4 1402 /* allocate transmit descriptors */
e0aac5a2
AK		 1403 err = e1000_setup_all_tx_resources(adapter);
1404 if (err)
1da177e4
LT		 1405 goto err_setup_tx;
1406
1407 /* allocate receive descriptors */
e0aac5a2 1408 err = e1000_setup_all_rx_resources(adapter);
b5bf28cd 1409 if (err)
e0aac5a2 1410 goto err_setup_rx;
b5bf28cd 1411
79f05bf0
AK		 1412 e1000_power_up_phy(adapter);
1413
2d7edb92 1414 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
96838a40 1415 if ((adapter->hw.mng_cookie.status &
2d7edb92
MC		 1416 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) {
1417 e1000_update_mng_vlan(adapter);
1418 }
1da177e4 1419
b55ccb35
JK		 1420 /* If AMT is enabled, let the firmware know that the network
1421 * interface is now open */
1422 if (adapter->hw.mac_type == e1000_82573 &&
1423 e1000_check_mng_mode(&adapter->hw))
1424 e1000_get_hw_control(adapter);
1425
e0aac5a2
AK		 1426 /* before we allocate an interrupt, we must be ready to handle it.
1427 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1428 * as soon as we call pci_request_irq, so we have to setup our
1429 * clean_rx handler before we do so. */
1430 e1000_configure(adapter);
1431
1432 err = e1000_request_irq(adapter);
1433 if (err)
1434 goto err_req_irq;
1435
1436 /* From here on the code is the same as e1000_up() */
1437 clear_bit(__E1000_DOWN, &adapter->flags);
1438
47313054 1439#ifdef CONFIG_E1000_NAPI
bea3348e 1440 napi_enable(&adapter->napi);
47313054
HX		 1441#endif
1442
e0aac5a2
AK		 1443 e1000_irq_enable(adapter);
1444
1445 /* fire a link status change interrupt to start the watchdog */
1446 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_LSC);
1447
1da177e4
LT		 1448 return E1000_SUCCESS;
1449
b5bf28cd 1450err_req_irq:
e0aac5a2
AK		 1451 e1000_release_hw_control(adapter);
1452 e1000_power_down_phy(adapter);
581d708e 1453 e1000_free_all_rx_resources(adapter);
1da177e4 1454err_setup_rx:
581d708e 1455 e1000_free_all_tx_resources(adapter);
1da177e4
LT		 1456err_setup_tx:
1457 e1000_reset(adapter);
1458
1459 return err;
1460}
1461
1462/**
1463 * e1000_close - Disables a network interface
1464 * @netdev: network interface device structure
1465 *
1466 * Returns 0, this is not allowed to fail
1467 *
1468 * The close entry point is called when an interface is de-activated
1469 * by the OS. The hardware is still under the drivers control, but
1470 * needs to be disabled. A global MAC reset is issued to stop the
1471 * hardware, and all transmit and receive resources are freed.
1472 **/
1473
1474static int
1475e1000_close(struct net_device *netdev)
1476{
60490fe0 1477 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 1478
2db10a08 1479 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 1480 e1000_down(adapter);
79f05bf0 1481 e1000_power_down_phy(adapter);
2db10a08 1482 e1000_free_irq(adapter);
1da177e4 1483
581d708e
MC		 1484 e1000_free_all_tx_resources(adapter);
1485 e1000_free_all_rx_resources(adapter);
1da177e4 1486
4666560a
BA		 1487 /* kill manageability vlan ID if supported, but not if a vlan with
1488 * the same ID is registered on the host OS (let 8021q kill it) */
96838a40 1489 if ((adapter->hw.mng_cookie.status &
4666560a
BA		 1490 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
1491 !(adapter->vlgrp &&
5c15bdec 1492 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id))) {
2d7edb92
MC		 1493 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1494 }
b55ccb35
JK		 1495
1496 /* If AMT is enabled, let the firmware know that the network
1497 * interface is now closed */
1498 if (adapter->hw.mac_type == e1000_82573 &&
1499 e1000_check_mng_mode(&adapter->hw))
1500 e1000_release_hw_control(adapter);
1501
1da177e4
LT		 1502 return 0;
1503}
1504
1505/**
1506 * e1000_check_64k_bound - check that memory doesn't cross 64kB boundary
1507 * @adapter: address of board private structure
2d7edb92
MC		 1508 * @start: address of beginning of memory
1509 * @len: length of memory
1da177e4 1510 **/
e619d523 1511static boolean_t
1da177e4
LT		 1512e1000_check_64k_bound(struct e1000_adapter *adapter,
1513 void *start, unsigned long len)
1514{
1515 unsigned long begin = (unsigned long) start;
1516 unsigned long end = begin + len;
1517
2648345f
MC		 1518 /* First rev 82545 and 82546 need to not allow any memory
1519 * write location to cross 64k boundary due to errata 23 */
1da177e4 1520 if (adapter->hw.mac_type == e1000_82545 ||
2648345f 1521 adapter->hw.mac_type == e1000_82546) {
1da177e4
LT		 1522 return ((begin ^ (end - 1)) >> 16) != 0 ? FALSE : TRUE;
1523 }
1524
1525 return TRUE;
1526}
1527
1528/**
1529 * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
1530 * @adapter: board private structure
581d708e 1531 * @txdr: tx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1532 *
1533 * Return 0 on success, negative on failure
1534 **/
1535
3ad2cc67 1536static int
581d708e
MC		 1537e1000_setup_tx_resources(struct e1000_adapter *adapter,
1538 struct e1000_tx_ring *txdr)
1da177e4 1539{
1da177e4
LT		 1540 struct pci_dev *pdev = adapter->pdev;
1541 int size;
1542
1543 size = sizeof(struct e1000_buffer) * txdr->count;
cd94dd0b 1544 txdr->buffer_info = vmalloc(size);
96838a40 1545 if (!txdr->buffer_info) {
2648345f
MC		 1546 DPRINTK(PROBE, ERR,
1547 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1548 return -ENOMEM;
1549 }
1550 memset(txdr->buffer_info, 0, size);
1551
1552 /* round up to nearest 4K */
1553
1554 txdr->size = txdr->count * sizeof(struct e1000_tx_desc);
9099cfb9 1555 txdr->size = ALIGN(txdr->size, 4096);
1da177e4
LT		 1556
1557 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
96838a40 1558 if (!txdr->desc) {
1da177e4 1559setup_tx_desc_die:
1da177e4 1560 vfree(txdr->buffer_info);
2648345f
MC		 1561 DPRINTK(PROBE, ERR,
1562 "Unable to allocate memory for the transmit descriptor ring\n");
1da177e4
LT		 1563 return -ENOMEM;
1564 }
1565
2648345f 1566 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1567 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1568 void *olddesc = txdr->desc;
1569 dma_addr_t olddma = txdr->dma;
2648345f
MC		 1570 DPRINTK(TX_ERR, ERR, "txdr align check failed: %u bytes "
1571 "at %p\n", txdr->size, txdr->desc);
1572 /* Try again, without freeing the previous */
1da177e4 1573 txdr->desc = pci_alloc_consistent(pdev, txdr->size, &txdr->dma);
2648345f 1574 /* Failed allocation, critical failure */
96838a40 1575 if (!txdr->desc) {
1da177e4
LT		 1576 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1577 goto setup_tx_desc_die;
1578 }
1579
1580 if (!e1000_check_64k_bound(adapter, txdr->desc, txdr->size)) {
1581 /* give up */
2648345f
MC		 1582 pci_free_consistent(pdev, txdr->size, txdr->desc,
1583 txdr->dma);
1da177e4
LT		 1584 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1585 DPRINTK(PROBE, ERR,
2648345f
MC		 1586 "Unable to allocate aligned memory "
1587 "for the transmit descriptor ring\n");
1da177e4
LT		 1588 vfree(txdr->buffer_info);
1589 return -ENOMEM;
1590 } else {
2648345f 1591 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1592 pci_free_consistent(pdev, txdr->size, olddesc, olddma);
1593 }
1594 }
1595 memset(txdr->desc, 0, txdr->size);
1596
1597 txdr->next_to_use = 0;
1598 txdr->next_to_clean = 0;
2ae76d98 1599 spin_lock_init(&txdr->tx_lock);
1da177e4
LT		 1600
1601 return 0;
1602}
1603
581d708e
MC		 1604/**
1605 * e1000_setup_all_tx_resources - wrapper to allocate Tx resources
1606 * (Descriptors) for all queues
1607 * @adapter: board private structure
1608 *
581d708e
MC		 1609 * Return 0 on success, negative on failure
1610 **/
1611
1612int
1613e1000_setup_all_tx_resources(struct e1000_adapter *adapter)
1614{
1615 int i, err = 0;
1616
f56799ea 1617 for (i = 0; i < adapter->num_tx_queues; i++) {
581d708e
MC		 1618 err = e1000_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1619 if (err) {
1620 DPRINTK(PROBE, ERR,
1621 "Allocation for Tx Queue %u failed\n", i);
3fbbc72e
VA		 1622 for (i-- ; i >= 0; i--)
1623 e1000_free_tx_resources(adapter,
1624 &adapter->tx_ring[i]);
581d708e
MC		 1625 break;
1626 }
1627 }
1628
1629 return err;
1630}
1631
1da177e4
LT		 1632/**
1633 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
1634 * @adapter: board private structure
1635 *
1636 * Configure the Tx unit of the MAC after a reset.
1637 **/
1638
1639static void
1640e1000_configure_tx(struct e1000_adapter *adapter)
1641{
581d708e
MC		 1642 uint64_t tdba;
1643 struct e1000_hw *hw = &adapter->hw;
1644 uint32_t tdlen, tctl, tipg, tarc;
0fadb059 1645 uint32_t ipgr1, ipgr2;
1da177e4
LT		 1646
1647 /* Setup the HW Tx Head and Tail descriptor pointers */
1648
f56799ea 1649 switch (adapter->num_tx_queues) {
24025e4e
MC		 1650 case 1:
1651 default:
581d708e
MC		 1652 tdba = adapter->tx_ring[0].dma;
1653 tdlen = adapter->tx_ring[0].count *
1654 sizeof(struct e1000_tx_desc);
581d708e 1655 E1000_WRITE_REG(hw, TDLEN, tdlen);
4ca213a6
AK		 1656 E1000_WRITE_REG(hw, TDBAH, (tdba >> 32));
1657 E1000_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL));
581d708e 1658 E1000_WRITE_REG(hw, TDT, 0);
4ca213a6 1659 E1000_WRITE_REG(hw, TDH, 0);
6a951698
AK		 1660 adapter->tx_ring[0].tdh = ((hw->mac_type >= e1000_82543) ? E1000_TDH : E1000_82542_TDH);
1661 adapter->tx_ring[0].tdt = ((hw->mac_type >= e1000_82543) ? E1000_TDT : E1000_82542_TDT);
24025e4e
MC		 1662 break;
1663 }
1da177e4
LT		 1664
1665 /* Set the default values for the Tx Inter Packet Gap timer */
d89b6c67
JB		 1666 if (adapter->hw.mac_type <= e1000_82547_rev_2 &&
1667 (hw->media_type == e1000_media_type_fiber ||
1668 hw->media_type == e1000_media_type_internal_serdes))
0fadb059
JK		 1669 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
1670 else
1671 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
1672
581d708e 1673 switch (hw->mac_type) {
1da177e4
LT		 1674 case e1000_82542_rev2_0:
1675 case e1000_82542_rev2_1:
1676 tipg = DEFAULT_82542_TIPG_IPGT;
0fadb059
JK		 1677 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
1678 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
1da177e4 1679 break;
87041639
JK		 1680 case e1000_80003es2lan:
1681 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1682 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
1683 break;
1da177e4 1684 default:
0fadb059
JK		 1685 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
1686 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
1687 break;
1da177e4 1688 }
0fadb059
JK		 1689 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
1690 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
581d708e 1691 E1000_WRITE_REG(hw, TIPG, tipg);
1da177e4
LT		 1692
1693 /* Set the Tx Interrupt Delay register */
1694
581d708e
MC		 1695 E1000_WRITE_REG(hw, TIDV, adapter->tx_int_delay);
1696 if (hw->mac_type >= e1000_82540)
1697 E1000_WRITE_REG(hw, TADV, adapter->tx_abs_int_delay);
1da177e4
LT		 1698
1699 /* Program the Transmit Control Register */
1700
581d708e 1701 tctl = E1000_READ_REG(hw, TCTL);
1da177e4 1702 tctl &= ~E1000_TCTL_CT;
7e6c9861 1703 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1da177e4
LT		 1704 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1705
2ae76d98
MC		 1706 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
1707 tarc = E1000_READ_REG(hw, TARC0);
90fb5135
AK		 1708 /* set the speed mode bit, we'll clear it if we're not at
1709 * gigabit link later */
09ae3e88 1710 tarc |= (1 << 21);
2ae76d98 1711 E1000_WRITE_REG(hw, TARC0, tarc);
87041639
JK		 1712 } else if (hw->mac_type == e1000_80003es2lan) {
1713 tarc = E1000_READ_REG(hw, TARC0);
1714 tarc |= 1;
87041639
JK		 1715 E1000_WRITE_REG(hw, TARC0, tarc);
1716 tarc = E1000_READ_REG(hw, TARC1);
1717 tarc |= 1;
1718 E1000_WRITE_REG(hw, TARC1, tarc);
2ae76d98
MC		 1719 }
1720
581d708e 1721 e1000_config_collision_dist(hw);
1da177e4
LT		 1722
1723 /* Setup Transmit Descriptor Settings for eop descriptor */
6a042dab
JB		 1724 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
1725
1726 /* only set IDE if we are delaying interrupts using the timers */
1727 if (adapter->tx_int_delay)
1728 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
1da177e4 1729
581d708e 1730 if (hw->mac_type < e1000_82543)
1da177e4
LT		 1731 adapter->txd_cmd |= E1000_TXD_CMD_RPS;
1732 else
1733 adapter->txd_cmd |= E1000_TXD_CMD_RS;
1734
1735 /* Cache if we're 82544 running in PCI-X because we'll
1736 * need this to apply a workaround later in the send path. */
581d708e
MC		 1737 if (hw->mac_type == e1000_82544 &&
1738 hw->bus_type == e1000_bus_type_pcix)
1da177e4 1739 adapter->pcix_82544 = 1;
7e6c9861
JK		 1740
1741 E1000_WRITE_REG(hw, TCTL, tctl);
1742
1da177e4
LT		 1743}
1744
1745/**
1746 * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
1747 * @adapter: board private structure
581d708e 1748 * @rxdr: rx descriptor ring (for a specific queue) to setup
1da177e4
LT		 1749 *
1750 * Returns 0 on success, negative on failure
1751 **/
1752
3ad2cc67 1753static int
581d708e
MC		 1754e1000_setup_rx_resources(struct e1000_adapter *adapter,
1755 struct e1000_rx_ring *rxdr)
1da177e4 1756{
1da177e4 1757 struct pci_dev *pdev = adapter->pdev;
2d7edb92 1758 int size, desc_len;
1da177e4
LT		 1759
1760 size = sizeof(struct e1000_buffer) * rxdr->count;
cd94dd0b 1761 rxdr->buffer_info = vmalloc(size);
581d708e 1762 if (!rxdr->buffer_info) {
2648345f
MC		 1763 DPRINTK(PROBE, ERR,
1764 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4
LT		 1765 return -ENOMEM;
1766 }
1767 memset(rxdr->buffer_info, 0, size);
1768
1c7e5b12
YB		 1769 rxdr->ps_page = kcalloc(rxdr->count, sizeof(struct e1000_ps_page),
1770 GFP_KERNEL);
96838a40 1771 if (!rxdr->ps_page) {
2d7edb92
MC		 1772 vfree(rxdr->buffer_info);
1773 DPRINTK(PROBE, ERR,
1774 "Unable to allocate memory for the receive descriptor ring\n");
1775 return -ENOMEM;
1776 }
2d7edb92 1777
1c7e5b12
YB		 1778 rxdr->ps_page_dma = kcalloc(rxdr->count,
1779 sizeof(struct e1000_ps_page_dma),
1780 GFP_KERNEL);
96838a40 1781 if (!rxdr->ps_page_dma) {
2d7edb92
MC		 1782 vfree(rxdr->buffer_info);
1783 kfree(rxdr->ps_page);
1784 DPRINTK(PROBE, ERR,
1785 "Unable to allocate memory for the receive descriptor ring\n");
1786 return -ENOMEM;
1787 }
2d7edb92 1788
96838a40 1789 if (adapter->hw.mac_type <= e1000_82547_rev_2)
2d7edb92
MC		 1790 desc_len = sizeof(struct e1000_rx_desc);
1791 else
1792 desc_len = sizeof(union e1000_rx_desc_packet_split);
1793
1da177e4
LT		 1794 /* Round up to nearest 4K */
1795
2d7edb92 1796 rxdr->size = rxdr->count * desc_len;
9099cfb9 1797 rxdr->size = ALIGN(rxdr->size, 4096);
1da177e4
LT		 1798
1799 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
1800
581d708e
MC		 1801 if (!rxdr->desc) {
1802 DPRINTK(PROBE, ERR,
1803 "Unable to allocate memory for the receive descriptor ring\n");
1da177e4 1804setup_rx_desc_die:
1da177e4 1805 vfree(rxdr->buffer_info);
2d7edb92
MC		 1806 kfree(rxdr->ps_page);
1807 kfree(rxdr->ps_page_dma);
1da177e4
LT		 1808 return -ENOMEM;
1809 }
1810
2648345f 1811 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 1812 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1813 void *olddesc = rxdr->desc;
1814 dma_addr_t olddma = rxdr->dma;
2648345f
MC		 1815 DPRINTK(RX_ERR, ERR, "rxdr align check failed: %u bytes "
1816 "at %p\n", rxdr->size, rxdr->desc);
1817 /* Try again, without freeing the previous */
1da177e4 1818 rxdr->desc = pci_alloc_consistent(pdev, rxdr->size, &rxdr->dma);
2648345f 1819 /* Failed allocation, critical failure */
581d708e 1820 if (!rxdr->desc) {
1da177e4 1821 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
581d708e
MC		 1822 DPRINTK(PROBE, ERR,
1823 "Unable to allocate memory "
1824 "for the receive descriptor ring\n");
1da177e4
LT		 1825 goto setup_rx_desc_die;
1826 }
1827
1828 if (!e1000_check_64k_bound(adapter, rxdr->desc, rxdr->size)) {
1829 /* give up */
2648345f
MC		 1830 pci_free_consistent(pdev, rxdr->size, rxdr->desc,
1831 rxdr->dma);
1da177e4 1832 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
2648345f
MC		 1833 DPRINTK(PROBE, ERR,
1834 "Unable to allocate aligned memory "
1835 "for the receive descriptor ring\n");
581d708e 1836 goto setup_rx_desc_die;
1da177e4 1837 } else {
2648345f 1838 /* Free old allocation, new allocation was successful */
1da177e4
LT		 1839 pci_free_consistent(pdev, rxdr->size, olddesc, olddma);
1840 }
1841 }
1842 memset(rxdr->desc, 0, rxdr->size);
1843
1844 rxdr->next_to_clean = 0;
1845 rxdr->next_to_use = 0;
1846
1847 return 0;
1848}
1849
581d708e
MC		 1850/**
1851 * e1000_setup_all_rx_resources - wrapper to allocate Rx resources
1852 * (Descriptors) for all queues
1853 * @adapter: board private structure
1854 *
581d708e
MC		 1855 * Return 0 on success, negative on failure
1856 **/
1857
1858int
1859e1000_setup_all_rx_resources(struct e1000_adapter *adapter)
1860{
1861 int i, err = 0;
1862
f56799ea 1863 for (i = 0; i < adapter->num_rx_queues; i++) {
581d708e
MC		 1864 err = e1000_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1865 if (err) {
1866 DPRINTK(PROBE, ERR,
1867 "Allocation for Rx Queue %u failed\n", i);
3fbbc72e
VA		 1868 for (i-- ; i >= 0; i--)
1869 e1000_free_rx_resources(adapter,
1870 &adapter->rx_ring[i]);
581d708e
MC		 1871 break;
1872 }
1873 }
1874
1875 return err;
1876}
1877
1da177e4 1878/**
2648345f 1879 * e1000_setup_rctl - configure the receive control registers
1da177e4
LT		 1880 * @adapter: Board private structure
1881 **/
e4c811c9
MC		 1882#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1883 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1da177e4
LT		 1884static void
1885e1000_setup_rctl(struct e1000_adapter *adapter)
1886{
2d7edb92
MC		 1887 uint32_t rctl, rfctl;
1888 uint32_t psrctl = 0;
35ec56bb 1889#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
e4c811c9
MC		 1890 uint32_t pages = 0;
1891#endif
1da177e4
LT		 1892
1893 rctl = E1000_READ_REG(&adapter->hw, RCTL);
1894
1895 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1896
1897 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1898 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1899 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
1900
0fadb059 1901 if (adapter->hw.tbi_compatibility_on == 1)
1da177e4
LT		 1902 rctl |= E1000_RCTL_SBP;
1903 else
1904 rctl &= ~E1000_RCTL_SBP;
1905
2d7edb92
MC		 1906 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1907 rctl &= ~E1000_RCTL_LPE;
1908 else
1909 rctl |= E1000_RCTL_LPE;
1910
1da177e4 1911 /* Setup buffer sizes */
9e2feace
AK		 1912 rctl &= ~E1000_RCTL_SZ_4096;
1913 rctl |= E1000_RCTL_BSEX;
1914 switch (adapter->rx_buffer_len) {
1915 case E1000_RXBUFFER_256:
1916 rctl |= E1000_RCTL_SZ_256;
1917 rctl &= ~E1000_RCTL_BSEX;
1918 break;
1919 case E1000_RXBUFFER_512:
1920 rctl |= E1000_RCTL_SZ_512;
1921 rctl &= ~E1000_RCTL_BSEX;
1922 break;
1923 case E1000_RXBUFFER_1024:
1924 rctl |= E1000_RCTL_SZ_1024;
1925 rctl &= ~E1000_RCTL_BSEX;
1926 break;
a1415ee6
JK		 1927 case E1000_RXBUFFER_2048:
1928 default:
1929 rctl |= E1000_RCTL_SZ_2048;
1930 rctl &= ~E1000_RCTL_BSEX;
1931 break;
1932 case E1000_RXBUFFER_4096:
1933 rctl |= E1000_RCTL_SZ_4096;
1934 break;
1935 case E1000_RXBUFFER_8192:
1936 rctl |= E1000_RCTL_SZ_8192;
1937 break;
1938 case E1000_RXBUFFER_16384:
1939 rctl |= E1000_RCTL_SZ_16384;
1940 break;
2d7edb92
MC		 1941 }
1942
35ec56bb 1943#ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT
2d7edb92
MC		 1944 /* 82571 and greater support packet-split where the protocol
1945 * header is placed in skb->data and the packet data is
1946 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1947 * In the case of a non-split, skb->data is linearly filled,
1948 * followed by the page buffers. Therefore, skb->data is
1949 * sized to hold the largest protocol header.
1950 */
e64d7d02
JB		 1951 /* allocations using alloc_page take too long for regular MTU
1952 * so only enable packet split for jumbo frames */
e4c811c9 1953 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
e64d7d02
JB		 1954 if ((adapter->hw.mac_type >= e1000_82571) && (pages <= 3) &&
1955 PAGE_SIZE <= 16384 && (rctl & E1000_RCTL_LPE))
e4c811c9
MC		 1956 adapter->rx_ps_pages = pages;
1957 else
1958 adapter->rx_ps_pages = 0;
2d7edb92 1959#endif
e4c811c9 1960 if (adapter->rx_ps_pages) {
2d7edb92
MC		 1961 /* Configure extra packet-split registers */
1962 rfctl = E1000_READ_REG(&adapter->hw, RFCTL);
1963 rfctl |= E1000_RFCTL_EXTEN;
87ca4e5b
AK		 1964 /* disable packet split support for IPv6 extension headers,
1965 * because some malformed IPv6 headers can hang the RX */
1966 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
1967 E1000_RFCTL_NEW_IPV6_EXT_DIS);
1968
2d7edb92
MC		 1969 E1000_WRITE_REG(&adapter->hw, RFCTL, rfctl);
1970
7dfee0cb 1971 rctl |= E1000_RCTL_DTYP_PS;
96838a40 1972
2d7edb92
MC		 1973 psrctl |= adapter->rx_ps_bsize0 >>
1974 E1000_PSRCTL_BSIZE0_SHIFT;
e4c811c9
MC		 1975
1976 switch (adapter->rx_ps_pages) {
1977 case 3:
1978 psrctl |= PAGE_SIZE <<
1979 E1000_PSRCTL_BSIZE3_SHIFT;
1980 case 2:
1981 psrctl |= PAGE_SIZE <<
1982 E1000_PSRCTL_BSIZE2_SHIFT;
1983 case 1:
1984 psrctl |= PAGE_SIZE >>
1985 E1000_PSRCTL_BSIZE1_SHIFT;
1986 break;
1987 }
2d7edb92
MC		 1988
1989 E1000_WRITE_REG(&adapter->hw, PSRCTL, psrctl);
1da177e4
LT		 1990 }
1991
1992 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
1993}
1994
1995/**
1996 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
1997 * @adapter: board private structure
1998 *
1999 * Configure the Rx unit of the MAC after a reset.
2000 **/
2001
2002static void
2003e1000_configure_rx(struct e1000_adapter *adapter)
2004{
581d708e
MC		 2005 uint64_t rdba;
2006 struct e1000_hw *hw = &adapter->hw;
2007 uint32_t rdlen, rctl, rxcsum, ctrl_ext;
2d7edb92 2008
e4c811c9 2009 if (adapter->rx_ps_pages) {
0f15a8fa 2010 /* this is a 32 byte descriptor */
581d708e 2011 rdlen = adapter->rx_ring[0].count *
2d7edb92
MC		 2012 sizeof(union e1000_rx_desc_packet_split);
2013 adapter->clean_rx = e1000_clean_rx_irq_ps;
2014 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
2015 } else {
581d708e
MC		 2016 rdlen = adapter->rx_ring[0].count *
2017 sizeof(struct e1000_rx_desc);
2d7edb92
MC		 2018 adapter->clean_rx = e1000_clean_rx_irq;
2019 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
2020 }
1da177e4
LT		 2021
2022 /* disable receives while setting up the descriptors */
581d708e
MC		 2023 rctl = E1000_READ_REG(hw, RCTL);
2024 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
1da177e4
LT		 2025
2026 /* set the Receive Delay Timer Register */
581d708e 2027 E1000_WRITE_REG(hw, RDTR, adapter->rx_int_delay);
1da177e4 2028
581d708e
MC		 2029 if (hw->mac_type >= e1000_82540) {
2030 E1000_WRITE_REG(hw, RADV, adapter->rx_abs_int_delay);
835bb129 2031 if (adapter->itr_setting != 0)
581d708e 2032 E1000_WRITE_REG(hw, ITR,
1da177e4
LT		 2033 1000000000 / (adapter->itr * 256));
2034 }
2035
2ae76d98 2036 if (hw->mac_type >= e1000_82571) {
2ae76d98 2037 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1e613fd9 2038 /* Reset delay timers after every interrupt */
6fc7a7ec 2039 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
1e613fd9 2040#ifdef CONFIG_E1000_NAPI
835bb129 2041 /* Auto-Mask interrupts upon ICR access */
1e613fd9 2042 ctrl_ext |= E1000_CTRL_EXT_IAME;
835bb129 2043 E1000_WRITE_REG(hw, IAM, 0xffffffff);
1e613fd9 2044#endif
2ae76d98
MC		 2045 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2046 E1000_WRITE_FLUSH(hw);
2047 }
2048
581d708e
MC		 2049 /* Setup the HW Rx Head and Tail Descriptor Pointers and
2050 * the Base and Length of the Rx Descriptor Ring */
f56799ea 2051 switch (adapter->num_rx_queues) {
24025e4e
MC		 2052 case 1:
2053 default:
581d708e 2054 rdba = adapter->rx_ring[0].dma;
581d708e 2055 E1000_WRITE_REG(hw, RDLEN, rdlen);
4ca213a6
AK		 2056 E1000_WRITE_REG(hw, RDBAH, (rdba >> 32));
2057 E1000_WRITE_REG(hw, RDBAL, (rdba & 0x00000000ffffffffULL));
581d708e 2058 E1000_WRITE_REG(hw, RDT, 0);
4ca213a6 2059 E1000_WRITE_REG(hw, RDH, 0);
6a951698
AK		 2060 adapter->rx_ring[0].rdh = ((hw->mac_type >= e1000_82543) ? E1000_RDH : E1000_82542_RDH);
2061 adapter->rx_ring[0].rdt = ((hw->mac_type >= e1000_82543) ? E1000_RDT : E1000_82542_RDT);
581d708e 2062 break;
24025e4e
MC		 2063 }
2064
1da177e4 2065 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
581d708e
MC		 2066 if (hw->mac_type >= e1000_82543) {
2067 rxcsum = E1000_READ_REG(hw, RXCSUM);
96838a40 2068 if (adapter->rx_csum == TRUE) {
2d7edb92
MC		 2069 rxcsum |= E1000_RXCSUM_TUOFL;
2070
868d5309 2071 /* Enable 82571 IPv4 payload checksum for UDP fragments
2d7edb92 2072 * Must be used in conjunction with packet-split. */
96838a40
JB		 2073 if ((hw->mac_type >= e1000_82571) &&
2074 (adapter->rx_ps_pages)) {
2d7edb92
MC		 2075 rxcsum |= E1000_RXCSUM_IPPCSE;
2076 }
2077 } else {
2078 rxcsum &= ~E1000_RXCSUM_TUOFL;
2079 /* don't need to clear IPPCSE as it defaults to 0 */
2080 }
581d708e 2081 E1000_WRITE_REG(hw, RXCSUM, rxcsum);
1da177e4
LT		 2082 }
2083
21c4d5e0
AK		 2084 /* enable early receives on 82573, only takes effect if using > 2048
2085 * byte total frame size. for example only for jumbo frames */
2086#define E1000_ERT_2048 0x100
2087 if (hw->mac_type == e1000_82573)
2088 E1000_WRITE_REG(hw, ERT, E1000_ERT_2048);
2089
1da177e4 2090 /* Enable Receives */
581d708e 2091 E1000_WRITE_REG(hw, RCTL, rctl);
1da177e4
LT		 2092}
2093
2094/**
581d708e 2095 * e1000_free_tx_resources - Free Tx Resources per Queue
1da177e4 2096 * @adapter: board private structure
581d708e 2097 * @tx_ring: Tx descriptor ring for a specific queue
1da177e4
LT		 2098 *
2099 * Free all transmit software resources
2100 **/
2101
3ad2cc67 2102static void
581d708e
MC		 2103e1000_free_tx_resources(struct e1000_adapter *adapter,
2104 struct e1000_tx_ring *tx_ring)
1da177e4
LT		 2105{
2106 struct pci_dev *pdev = adapter->pdev;
2107
581d708e 2108 e1000_clean_tx_ring(adapter, tx_ring);
1da177e4 2109
581d708e
MC		 2110 vfree(tx_ring->buffer_info);
2111 tx_ring->buffer_info = NULL;
1da177e4 2112
581d708e 2113 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1da177e4 2114
581d708e
MC		 2115 tx_ring->desc = NULL;
2116}
2117
2118/**
2119 * e1000_free_all_tx_resources - Free Tx Resources for All Queues
2120 * @adapter: board private structure
2121 *
2122 * Free all transmit software resources
2123 **/
2124
2125void
2126e1000_free_all_tx_resources(struct e1000_adapter *adapter)
2127{
2128 int i;
2129
f56799ea 2130 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2131 e1000_free_tx_resources(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2132}
2133
e619d523 2134static void
1da177e4
LT		 2135e1000_unmap_and_free_tx_resource(struct e1000_adapter *adapter,
2136 struct e1000_buffer *buffer_info)
2137{
96838a40 2138 if (buffer_info->dma) {
2648345f
MC		 2139 pci_unmap_page(adapter->pdev,
2140 buffer_info->dma,
2141 buffer_info->length,
2142 PCI_DMA_TODEVICE);
a9ebadd6 2143 buffer_info->dma = 0;
1da177e4 2144 }
a9ebadd6 2145 if (buffer_info->skb) {
1da177e4 2146 dev_kfree_skb_any(buffer_info->skb);
a9ebadd6
JB		 2147 buffer_info->skb = NULL;
2148 }
2149 /* buffer_info must be completely set up in the transmit path */
1da177e4
LT		 2150}
2151
2152/**
2153 * e1000_clean_tx_ring - Free Tx Buffers
2154 * @adapter: board private structure
581d708e 2155 * @tx_ring: ring to be cleaned
1da177e4
LT		 2156 **/
2157
2158static void
581d708e
MC		 2159e1000_clean_tx_ring(struct e1000_adapter *adapter,
2160 struct e1000_tx_ring *tx_ring)
1da177e4 2161{
1da177e4
LT		 2162 struct e1000_buffer *buffer_info;
2163 unsigned long size;
2164 unsigned int i;
2165
2166 /* Free all the Tx ring sk_buffs */
2167
96838a40 2168 for (i = 0; i < tx_ring->count; i++) {
1da177e4
LT		 2169 buffer_info = &tx_ring->buffer_info[i];
2170 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
2171 }
2172
2173 size = sizeof(struct e1000_buffer) * tx_ring->count;
2174 memset(tx_ring->buffer_info, 0, size);
2175
2176 /* Zero out the descriptor ring */
2177
2178 memset(tx_ring->desc, 0, tx_ring->size);
2179
2180 tx_ring->next_to_use = 0;
2181 tx_ring->next_to_clean = 0;
fd803241 2182 tx_ring->last_tx_tso = 0;
1da177e4 2183
581d708e
MC		 2184 writel(0, adapter->hw.hw_addr + tx_ring->tdh);
2185 writel(0, adapter->hw.hw_addr + tx_ring->tdt);
2186}
2187
2188/**
2189 * e1000_clean_all_tx_rings - Free Tx Buffers for all queues
2190 * @adapter: board private structure
2191 **/
2192
2193static void
2194e1000_clean_all_tx_rings(struct e1000_adapter *adapter)
2195{
2196 int i;
2197
f56799ea 2198 for (i = 0; i < adapter->num_tx_queues; i++)
581d708e 2199 e1000_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1da177e4
LT		 2200}
2201
2202/**
2203 * e1000_free_rx_resources - Free Rx Resources
2204 * @adapter: board private structure
581d708e 2205 * @rx_ring: ring to clean the resources from
1da177e4
LT		 2206 *
2207 * Free all receive software resources
2208 **/
2209
3ad2cc67 2210static void
581d708e
MC		 2211e1000_free_rx_resources(struct e1000_adapter *adapter,
2212 struct e1000_rx_ring *rx_ring)
1da177e4 2213{
1da177e4
LT		 2214 struct pci_dev *pdev = adapter->pdev;
2215
581d708e 2216 e1000_clean_rx_ring(adapter, rx_ring);
1da177e4
LT		 2217
2218 vfree(rx_ring->buffer_info);
2219 rx_ring->buffer_info = NULL;
2d7edb92
MC		 2220 kfree(rx_ring->ps_page);
2221 rx_ring->ps_page = NULL;
2222 kfree(rx_ring->ps_page_dma);
2223 rx_ring->ps_page_dma = NULL;
1da177e4
LT		 2224
2225 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2226
2227 rx_ring->desc = NULL;
2228}
2229
2230/**
581d708e 2231 * e1000_free_all_rx_resources - Free Rx Resources for All Queues
1da177e4 2232 * @adapter: board private structure
581d708e
MC		 2233 *
2234 * Free all receive software resources
2235 **/
2236
2237void
2238e1000_free_all_rx_resources(struct e1000_adapter *adapter)
2239{
2240 int i;
2241
f56799ea 2242 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e
MC		 2243 e1000_free_rx_resources(adapter, &adapter->rx_ring[i]);
2244}
2245
2246/**
2247 * e1000_clean_rx_ring - Free Rx Buffers per Queue
2248 * @adapter: board private structure
2249 * @rx_ring: ring to free buffers from
1da177e4
LT		 2250 **/
2251
2252static void
581d708e
MC		 2253e1000_clean_rx_ring(struct e1000_adapter *adapter,
2254 struct e1000_rx_ring *rx_ring)
1da177e4 2255{
1da177e4 2256 struct e1000_buffer *buffer_info;
2d7edb92
MC		 2257 struct e1000_ps_page *ps_page;
2258 struct e1000_ps_page_dma *ps_page_dma;
1da177e4
LT		 2259 struct pci_dev *pdev = adapter->pdev;
2260 unsigned long size;
2d7edb92 2261 unsigned int i, j;
1da177e4
LT		 2262
2263 /* Free all the Rx ring sk_buffs */
96838a40 2264 for (i = 0; i < rx_ring->count; i++) {
1da177e4 2265 buffer_info = &rx_ring->buffer_info[i];
96838a40 2266 if (buffer_info->skb) {
1da177e4
LT		 2267 pci_unmap_single(pdev,
2268 buffer_info->dma,
2269 buffer_info->length,
2270 PCI_DMA_FROMDEVICE);
2271
2272 dev_kfree_skb(buffer_info->skb);
2273 buffer_info->skb = NULL;
997f5cbd
JK		 2274 }
2275 ps_page = &rx_ring->ps_page[i];
2276 ps_page_dma = &rx_ring->ps_page_dma[i];
2277 for (j = 0; j < adapter->rx_ps_pages; j++) {
2278 if (!ps_page->ps_page[j]) break;
2279 pci_unmap_page(pdev,
2280 ps_page_dma->ps_page_dma[j],
2281 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2282 ps_page_dma->ps_page_dma[j] = 0;
2283 put_page(ps_page->ps_page[j]);
2284 ps_page->ps_page[j] = NULL;
1da177e4
LT		 2285 }
2286 }
2287
2288 size = sizeof(struct e1000_buffer) * rx_ring->count;
2289 memset(rx_ring->buffer_info, 0, size);
2d7edb92
MC		 2290 size = sizeof(struct e1000_ps_page) * rx_ring->count;
2291 memset(rx_ring->ps_page, 0, size);
2292 size = sizeof(struct e1000_ps_page_dma) * rx_ring->count;
2293 memset(rx_ring->ps_page_dma, 0, size);
1da177e4
LT		 2294
2295 /* Zero out the descriptor ring */
2296
2297 memset(rx_ring->desc, 0, rx_ring->size);
2298
2299 rx_ring->next_to_clean = 0;
2300 rx_ring->next_to_use = 0;
2301
581d708e
MC		 2302 writel(0, adapter->hw.hw_addr + rx_ring->rdh);
2303 writel(0, adapter->hw.hw_addr + rx_ring->rdt);
2304}
2305
2306/**
2307 * e1000_clean_all_rx_rings - Free Rx Buffers for all queues
2308 * @adapter: board private structure
2309 **/
2310
2311static void
2312e1000_clean_all_rx_rings(struct e1000_adapter *adapter)
2313{
2314 int i;
2315
f56799ea 2316 for (i = 0; i < adapter->num_rx_queues; i++)
581d708e 2317 e1000_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1da177e4
LT		 2318}
2319
2320/* The 82542 2.0 (revision 2) needs to have the receive unit in reset
2321 * and memory write and invalidate disabled for certain operations
2322 */
2323static void
2324e1000_enter_82542_rst(struct e1000_adapter *adapter)
2325{
2326 struct net_device *netdev = adapter->netdev;
2327 uint32_t rctl;
2328
2329 e1000_pci_clear_mwi(&adapter->hw);
2330
2331 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2332 rctl |= E1000_RCTL_RST;
2333 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2334 E1000_WRITE_FLUSH(&adapter->hw);
2335 mdelay(5);
2336
96838a40 2337 if (netif_running(netdev))
581d708e 2338 e1000_clean_all_rx_rings(adapter);
1da177e4
LT		 2339}
2340
2341static void
2342e1000_leave_82542_rst(struct e1000_adapter *adapter)
2343{
2344 struct net_device *netdev = adapter->netdev;
2345 uint32_t rctl;
2346
2347 rctl = E1000_READ_REG(&adapter->hw, RCTL);
2348 rctl &= ~E1000_RCTL_RST;
2349 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
2350 E1000_WRITE_FLUSH(&adapter->hw);
2351 mdelay(5);
2352
96838a40 2353 if (adapter->hw.pci_cmd_word & PCI_COMMAND_INVALIDATE)
1da177e4
LT		 2354 e1000_pci_set_mwi(&adapter->hw);
2355
96838a40 2356 if (netif_running(netdev)) {
72d64a43
JK		 2357 /* No need to loop, because 82542 supports only 1 queue */
2358 struct e1000_rx_ring *ring = &adapter->rx_ring[0];
7c4d3367 2359 e1000_configure_rx(adapter);
72d64a43 2360 adapter->alloc_rx_buf(adapter, ring, E1000_DESC_UNUSED(ring));
1da177e4
LT		 2361 }
2362}
2363
2364/**
2365 * e1000_set_mac - Change the Ethernet Address of the NIC
2366 * @netdev: network interface device structure
2367 * @p: pointer to an address structure
2368 *
2369 * Returns 0 on success, negative on failure
2370 **/
2371
2372static int
2373e1000_set_mac(struct net_device *netdev, void *p)
2374{
60490fe0 2375 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2376 struct sockaddr *addr = p;
2377
96838a40 2378 if (!is_valid_ether_addr(addr->sa_data))
1da177e4
LT		 2379 return -EADDRNOTAVAIL;
2380
2381 /* 82542 2.0 needs to be in reset to write receive address registers */
2382
96838a40 2383 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2384 e1000_enter_82542_rst(adapter);
2385
2386 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2387 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
2388
2389 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2390
868d5309
MC		 2391 /* With 82571 controllers, LAA may be overwritten (with the default)
2392 * due to controller reset from the other port. */
2393 if (adapter->hw.mac_type == e1000_82571) {
2394 /* activate the work around */
2395 adapter->hw.laa_is_present = 1;
2396
96838a40
JB		 2397 /* Hold a copy of the LAA in RAR[14] This is done so that
2398 * between the time RAR[0] gets clobbered and the time it
2399 * gets fixed (in e1000_watchdog), the actual LAA is in one
868d5309 2400 * of the RARs and no incoming packets directed to this port
96838a40 2401 * are dropped. Eventaully the LAA will be in RAR[0] and
868d5309 2402 * RAR[14] */
96838a40 2403 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr,
868d5309
MC		 2404 E1000_RAR_ENTRIES - 1);
2405 }
2406
96838a40 2407 if (adapter->hw.mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2408 e1000_leave_82542_rst(adapter);
2409
2410 return 0;
2411}
2412
2413/**
2414 * e1000_set_multi - Multicast and Promiscuous mode set
2415 * @netdev: network interface device structure
2416 *
2417 * The set_multi entry point is called whenever the multicast address
2418 * list or the network interface flags are updated. This routine is
2419 * responsible for configuring the hardware for proper multicast,
2420 * promiscuous mode, and all-multi behavior.
2421 **/
2422
2423static void
2424e1000_set_multi(struct net_device *netdev)
2425{
60490fe0 2426 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 2427 struct e1000_hw *hw = &adapter->hw;
2428 struct dev_mc_list *mc_ptr;
2429 uint32_t rctl;
2430 uint32_t hash_value;
868d5309 2431 int i, rar_entries = E1000_RAR_ENTRIES;
cd94dd0b
AK		 2432 int mta_reg_count = (hw->mac_type == e1000_ich8lan) ?
2433 E1000_NUM_MTA_REGISTERS_ICH8LAN :
2434 E1000_NUM_MTA_REGISTERS;
2435
2436 if (adapter->hw.mac_type == e1000_ich8lan)
2437 rar_entries = E1000_RAR_ENTRIES_ICH8LAN;
1da177e4 2438
868d5309
MC		 2439 /* reserve RAR[14] for LAA over-write work-around */
2440 if (adapter->hw.mac_type == e1000_82571)
2441 rar_entries--;
1da177e4 2442
2648345f
MC		 2443 /* Check for Promiscuous and All Multicast modes */
2444
1da177e4
LT		 2445 rctl = E1000_READ_REG(hw, RCTL);
2446
96838a40 2447 if (netdev->flags & IFF_PROMISC) {
1da177e4 2448 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
96838a40 2449 } else if (netdev->flags & IFF_ALLMULTI) {
1da177e4
LT		 2450 rctl |= E1000_RCTL_MPE;
2451 rctl &= ~E1000_RCTL_UPE;
2452 } else {
2453 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2454 }
2455
2456 E1000_WRITE_REG(hw, RCTL, rctl);
2457
2458 /* 82542 2.0 needs to be in reset to write receive address registers */
2459
96838a40 2460 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4
LT		 2461 e1000_enter_82542_rst(adapter);
2462
2463 /* load the first 14 multicast address into the exact filters 1-14
2464 * RAR 0 is used for the station MAC adddress
2465 * if there are not 14 addresses, go ahead and clear the filters
868d5309 2466 * -- with 82571 controllers only 0-13 entries are filled here
1da177e4
LT		 2467 */
2468 mc_ptr = netdev->mc_list;
2469
96838a40 2470 for (i = 1; i < rar_entries; i++) {
868d5309 2471 if (mc_ptr) {
1da177e4
LT		 2472 e1000_rar_set(hw, mc_ptr->dmi_addr, i);
2473 mc_ptr = mc_ptr->next;
2474 } else {
2475 E1000_WRITE_REG_ARRAY(hw, RA, i << 1, 0);
4ca213a6 2476 E1000_WRITE_FLUSH(hw);
1da177e4 2477 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1) + 1, 0);
4ca213a6 2478 E1000_WRITE_FLUSH(hw);
1da177e4
LT		 2479 }
2480 }
2481
2482 /* clear the old settings from the multicast hash table */
2483
cd94dd0b 2484 for (i = 0; i < mta_reg_count; i++) {
1da177e4 2485 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
4ca213a6
AK		 2486 E1000_WRITE_FLUSH(hw);
2487 }
1da177e4
LT		 2488
2489 /* load any remaining addresses into the hash table */
2490
96838a40 2491 for (; mc_ptr; mc_ptr = mc_ptr->next) {
1da177e4
LT		 2492 hash_value = e1000_hash_mc_addr(hw, mc_ptr->dmi_addr);
2493 e1000_mta_set(hw, hash_value);
2494 }
2495
96838a40 2496 if (hw->mac_type == e1000_82542_rev2_0)
1da177e4 2497 e1000_leave_82542_rst(adapter);
1da177e4
LT		 2498}
2499
2500/* Need to wait a few seconds after link up to get diagnostic information from
2501 * the phy */
2502
2503static void
2504e1000_update_phy_info(unsigned long data)
2505{
2506 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2507 e1000_phy_get_info(&adapter->hw, &adapter->phy_info);
2508}
2509
2510/**
2511 * e1000_82547_tx_fifo_stall - Timer Call-back
2512 * @data: pointer to adapter cast into an unsigned long
2513 **/
2514
2515static void
2516e1000_82547_tx_fifo_stall(unsigned long data)
2517{
2518 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
2519 struct net_device *netdev = adapter->netdev;
2520 uint32_t tctl;
2521
96838a40
JB		 2522 if (atomic_read(&adapter->tx_fifo_stall)) {
2523 if ((E1000_READ_REG(&adapter->hw, TDT) ==
1da177e4
LT		 2524 E1000_READ_REG(&adapter->hw, TDH)) &&
2525 (E1000_READ_REG(&adapter->hw, TDFT) ==
2526 E1000_READ_REG(&adapter->hw, TDFH)) &&
2527 (E1000_READ_REG(&adapter->hw, TDFTS) ==
2528 E1000_READ_REG(&adapter->hw, TDFHS))) {
2529 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2530 E1000_WRITE_REG(&adapter->hw, TCTL,
2531 tctl & ~E1000_TCTL_EN);
2532 E1000_WRITE_REG(&adapter->hw, TDFT,
2533 adapter->tx_head_addr);
2534 E1000_WRITE_REG(&adapter->hw, TDFH,
2535 adapter->tx_head_addr);
2536 E1000_WRITE_REG(&adapter->hw, TDFTS,
2537 adapter->tx_head_addr);
2538 E1000_WRITE_REG(&adapter->hw, TDFHS,
2539 adapter->tx_head_addr);
2540 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
2541 E1000_WRITE_FLUSH(&adapter->hw);
2542
2543 adapter->tx_fifo_head = 0;
2544 atomic_set(&adapter->tx_fifo_stall, 0);
2545 netif_wake_queue(netdev);
2546 } else {
2547 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
2548 }
2549 }
2550}
2551
2552/**
2553 * e1000_watchdog - Timer Call-back
2554 * @data: pointer to adapter cast into an unsigned long
2555 **/
2556static void
2557e1000_watchdog(unsigned long data)
2558{
2559 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
1da177e4 2560 struct net_device *netdev = adapter->netdev;
545c67c0 2561 struct e1000_tx_ring *txdr = adapter->tx_ring;
7e6c9861 2562 uint32_t link, tctl;
cd94dd0b
AK		 2563 int32_t ret_val;
2564
2565 ret_val = e1000_check_for_link(&adapter->hw);
2566 if ((ret_val == E1000_ERR_PHY) &&
2567 (adapter->hw.phy_type == e1000_phy_igp_3) &&
2568 (E1000_READ_REG(&adapter->hw, CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
2569 /* See e1000_kumeran_lock_loss_workaround() */
2570 DPRINTK(LINK, INFO,
2571 "Gigabit has been disabled, downgrading speed\n");
2572 }
90fb5135 2573
2d7edb92
MC		 2574 if (adapter->hw.mac_type == e1000_82573) {
2575 e1000_enable_tx_pkt_filtering(&adapter->hw);
96838a40 2576 if (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)
2d7edb92 2577 e1000_update_mng_vlan(adapter);
96838a40 2578 }
1da177e4 2579
96838a40 2580 if ((adapter->hw.media_type == e1000_media_type_internal_serdes) &&
1da177e4
LT		 2581 !(E1000_READ_REG(&adapter->hw, TXCW) & E1000_TXCW_ANE))
2582 link = !adapter->hw.serdes_link_down;
2583 else
2584 link = E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU;
2585
96838a40
JB		 2586 if (link) {
2587 if (!netif_carrier_ok(netdev)) {
9669f53b 2588 uint32_t ctrl;
fe7fe28e 2589 boolean_t txb2b = 1;
1da177e4
LT		 2590 e1000_get_speed_and_duplex(&adapter->hw,
2591 &adapter->link_speed,
2592 &adapter->link_duplex);
2593
9669f53b
AK		 2594 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
2595 DPRINTK(LINK, INFO, "NIC Link is Up %d Mbps %s, "
2596 "Flow Control: %s\n",
2597 adapter->link_speed,
2598 adapter->link_duplex == FULL_DUPLEX ?
2599 "Full Duplex" : "Half Duplex",
2600 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2601 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2602 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2603 E1000_CTRL_TFCE) ? "TX" : "None" )));
1da177e4 2604
7e6c9861
JK		 2605 /* tweak tx_queue_len according to speed/duplex
2606 * and adjust the timeout factor */
66a2b0a3
JK		 2607 netdev->tx_queue_len = adapter->tx_queue_len;
2608 adapter->tx_timeout_factor = 1;
7e6c9861
JK		 2609 switch (adapter->link_speed) {
2610 case SPEED_10:
fe7fe28e 2611 txb2b = 0;
7e6c9861
JK		 2612 netdev->tx_queue_len = 10;
2613 adapter->tx_timeout_factor = 8;
2614 break;
2615 case SPEED_100:
fe7fe28e 2616 txb2b = 0;
7e6c9861
JK		 2617 netdev->tx_queue_len = 100;
2618 /* maybe add some timeout factor ? */
2619 break;
2620 }
2621
fe7fe28e 2622 if ((adapter->hw.mac_type == e1000_82571 ||
7e6c9861 2623 adapter->hw.mac_type == e1000_82572) &&
fe7fe28e 2624 txb2b == 0) {
7e6c9861
JK		 2625 uint32_t tarc0;
2626 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
90fb5135 2627 tarc0 &= ~(1 << 21);
7e6c9861
JK		 2628 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
2629 }
90fb5135 2630
7e6c9861
JK		 2631 /* disable TSO for pcie and 10/100 speeds, to avoid
2632 * some hardware issues */
2633 if (!adapter->tso_force &&
2634 adapter->hw.bus_type == e1000_bus_type_pci_express){
66a2b0a3
JK		 2635 switch (adapter->link_speed) {
2636 case SPEED_10:
66a2b0a3 2637 case SPEED_100:
7e6c9861
JK		 2638 DPRINTK(PROBE,INFO,
2639 "10/100 speed: disabling TSO\n");
2640 netdev->features &= ~NETIF_F_TSO;
87ca4e5b 2641 netdev->features &= ~NETIF_F_TSO6;
7e6c9861
JK		 2642 break;
2643 case SPEED_1000:
2644 netdev->features |= NETIF_F_TSO;
87ca4e5b 2645 netdev->features |= NETIF_F_TSO6;
7e6c9861
JK		 2646 break;
2647 default:
2648 /* oops */
66a2b0a3
JK		 2649 break;
2650 }
2651 }
7e6c9861
JK		 2652
2653 /* enable transmits in the hardware, need to do this
2654 * after setting TARC0 */
2655 tctl = E1000_READ_REG(&adapter->hw, TCTL);
2656 tctl |= E1000_TCTL_EN;
2657 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
66a2b0a3 2658
1da177e4
LT		 2659 netif_carrier_on(netdev);
2660 netif_wake_queue(netdev);
56e1393f 2661 mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
1da177e4 2662 adapter->smartspeed = 0;
bb8e3311
JG		 2663 } else {
2664 /* make sure the receive unit is started */
2665 if (adapter->hw.rx_needs_kicking) {
2666 struct e1000_hw *hw = &adapter->hw;
2667 uint32_t rctl = E1000_READ_REG(hw, RCTL);
2668 E1000_WRITE_REG(hw, RCTL, rctl | E1000_RCTL_EN);
2669 }
1da177e4
LT		 2670 }
2671 } else {
96838a40 2672 if (netif_carrier_ok(netdev)) {
1da177e4
LT		 2673 adapter->link_speed = 0;
2674 adapter->link_duplex = 0;
2675 DPRINTK(LINK, INFO, "NIC Link is Down\n");
2676 netif_carrier_off(netdev);
2677 netif_stop_queue(netdev);
56e1393f 2678 mod_timer(&adapter->phy_info_timer, round_jiffies(jiffies + 2 * HZ));
87041639
JK		 2679
2680 /* 80003ES2LAN workaround--
2681 * For packet buffer work-around on link down event;
2682 * disable receives in the ISR and
2683 * reset device here in the watchdog
2684 */
8fc897b0 2685 if (adapter->hw.mac_type == e1000_80003es2lan)
87041639
JK		 2686 /* reset device */
2687 schedule_work(&adapter->reset_task);
1da177e4
LT		 2688 }
2689
2690 e1000_smartspeed(adapter);
2691 }
2692
2693 e1000_update_stats(adapter);
2694
2695 adapter->hw.tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2696 adapter->tpt_old = adapter->stats.tpt;
2697 adapter->hw.collision_delta = adapter->stats.colc - adapter->colc_old;
2698 adapter->colc_old = adapter->stats.colc;
2699
2700 adapter->gorcl = adapter->stats.gorcl - adapter->gorcl_old;
2701 adapter->gorcl_old = adapter->stats.gorcl;
2702 adapter->gotcl = adapter->stats.gotcl - adapter->gotcl_old;
2703 adapter->gotcl_old = adapter->stats.gotcl;
2704
2705 e1000_update_adaptive(&adapter->hw);
2706
f56799ea 2707 if (!netif_carrier_ok(netdev)) {
581d708e 2708 if (E1000_DESC_UNUSED(txdr) + 1 < txdr->count) {
1da177e4
LT		 2709 /* We've lost link, so the controller stops DMA,
2710 * but we've got queued Tx work that's never going
2711 * to get done, so reset controller to flush Tx.
2712 * (Do the reset outside of interrupt context). */
87041639
JK		 2713 adapter->tx_timeout_count++;
2714 schedule_work(&adapter->reset_task);
1da177e4
LT		 2715 }
2716 }
2717
1da177e4
LT		 2718 /* Cause software interrupt to ensure rx ring is cleaned */
2719 E1000_WRITE_REG(&adapter->hw, ICS, E1000_ICS_RXDMT0);
2720
2648345f 2721 /* Force detection of hung controller every watchdog period */
1da177e4
LT		 2722 adapter->detect_tx_hung = TRUE;
2723
96838a40 2724 /* With 82571 controllers, LAA may be overwritten due to controller
868d5309
MC		 2725 * reset from the other port. Set the appropriate LAA in RAR[0] */
2726 if (adapter->hw.mac_type == e1000_82571 && adapter->hw.laa_is_present)
2727 e1000_rar_set(&adapter->hw, adapter->hw.mac_addr, 0);
2728
1da177e4 2729 /* Reset the timer */
56e1393f 2730 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
1da177e4
LT		 2731}
2732
835bb129
JB		 2733enum latency_range {
2734 lowest_latency = 0,
2735 low_latency = 1,
2736 bulk_latency = 2,
2737 latency_invalid = 255
2738};
2739
2740/**
2741 * e1000_update_itr - update the dynamic ITR value based on statistics
2742 * Stores a new ITR value based on packets and byte
2743 * counts during the last interrupt. The advantage of per interrupt
2744 * computation is faster updates and more accurate ITR for the current
2745 * traffic pattern. Constants in this function were computed
2746 * based on theoretical maximum wire speed and thresholds were set based
2747 * on testing data as well as attempting to minimize response time
2748 * while increasing bulk throughput.
2749 * this functionality is controlled by the InterruptThrottleRate module
2750 * parameter (see e1000_param.c)
2751 * @adapter: pointer to adapter
2752 * @itr_setting: current adapter->itr
2753 * @packets: the number of packets during this measurement interval
2754 * @bytes: the number of bytes during this measurement interval
2755 **/
2756static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2757 uint16_t itr_setting,
2758 int packets,
2759 int bytes)
2760{
2761 unsigned int retval = itr_setting;
2762 struct e1000_hw *hw = &adapter->hw;
2763
2764 if (unlikely(hw->mac_type < e1000_82540))
2765 goto update_itr_done;
2766
2767 if (packets == 0)
2768 goto update_itr_done;
2769
835bb129
JB		 2770 switch (itr_setting) {
2771 case lowest_latency:
2b65326e
JB		 2772 /* jumbo frames get bulk treatment*/
2773 if (bytes/packets > 8000)
2774 retval = bulk_latency;
2775 else if ((packets < 5) && (bytes > 512))
835bb129
JB		 2776 retval = low_latency;
2777 break;
2778 case low_latency: /* 50 usec aka 20000 ints/s */
2779 if (bytes > 10000) {
2b65326e
JB		 2780 /* jumbo frames need bulk latency setting */
2781 if (bytes/packets > 8000)
2782 retval = bulk_latency;
2783 else if ((packets < 10) || ((bytes/packets) > 1200))
835bb129
JB		 2784 retval = bulk_latency;
2785 else if ((packets > 35))
2786 retval = lowest_latency;
2b65326e
JB		 2787 } else if (bytes/packets > 2000)
2788 retval = bulk_latency;
2789 else if (packets <= 2 && bytes < 512)
835bb129
JB		 2790 retval = lowest_latency;
2791 break;
2792 case bulk_latency: /* 250 usec aka 4000 ints/s */
2793 if (bytes > 25000) {
2794 if (packets > 35)
2795 retval = low_latency;
2b65326e
JB		 2796 } else if (bytes < 6000) {
2797 retval = low_latency;
835bb129
JB		 2798 }
2799 break;
2800 }
2801
2802update_itr_done:
2803 return retval;
2804}
2805
2806static void e1000_set_itr(struct e1000_adapter *adapter)
2807{
2808 struct e1000_hw *hw = &adapter->hw;
2809 uint16_t current_itr;
2810 uint32_t new_itr = adapter->itr;
2811
2812 if (unlikely(hw->mac_type < e1000_82540))
2813 return;
2814
2815 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2816 if (unlikely(adapter->link_speed != SPEED_1000)) {
2817 current_itr = 0;
2818 new_itr = 4000;
2819 goto set_itr_now;
2820 }
2821
2822 adapter->tx_itr = e1000_update_itr(adapter,
2823 adapter->tx_itr,
2824 adapter->total_tx_packets,
2825 adapter->total_tx_bytes);
2b65326e
JB		 2826 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2827 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2828 adapter->tx_itr = low_latency;
2829
835bb129
JB		 2830 adapter->rx_itr = e1000_update_itr(adapter,
2831 adapter->rx_itr,
2832 adapter->total_rx_packets,
2833 adapter->total_rx_bytes);
2b65326e
JB		 2834 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2835 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2836 adapter->rx_itr = low_latency;
835bb129
JB		 2837
2838 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2839
835bb129
JB		 2840 switch (current_itr) {
2841 /* counts and packets in update_itr are dependent on these numbers */
2842 case lowest_latency:
2843 new_itr = 70000;
2844 break;
2845 case low_latency:
2846 new_itr = 20000; /* aka hwitr = ~200 */
2847 break;
2848 case bulk_latency:
2849 new_itr = 4000;
2850 break;
2851 default:
2852 break;
2853 }
2854
2855set_itr_now:
2856 if (new_itr != adapter->itr) {
2857 /* this attempts to bias the interrupt rate towards Bulk
2858 * by adding intermediate steps when interrupt rate is
2859 * increasing */
2860 new_itr = new_itr > adapter->itr ?
2861 min(adapter->itr + (new_itr >> 2), new_itr) :
2862 new_itr;
2863 adapter->itr = new_itr;
2864 E1000_WRITE_REG(hw, ITR, 1000000000 / (new_itr * 256));
2865 }
2866
2867 return;
2868}
2869
1da177e4
LT		 2870#define E1000_TX_FLAGS_CSUM 0x00000001
2871#define E1000_TX_FLAGS_VLAN 0x00000002
2872#define E1000_TX_FLAGS_TSO 0x00000004
2d7edb92 2873#define E1000_TX_FLAGS_IPV4 0x00000008
1da177e4
LT		 2874#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
2875#define E1000_TX_FLAGS_VLAN_SHIFT 16
2876
e619d523 2877static int
581d708e
MC		 2878e1000_tso(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2879 struct sk_buff *skb)
1da177e4 2880{
1da177e4 2881 struct e1000_context_desc *context_desc;
545c67c0 2882 struct e1000_buffer *buffer_info;
1da177e4
LT		 2883 unsigned int i;
2884 uint32_t cmd_length = 0;
2d7edb92 2885 uint16_t ipcse = 0, tucse, mss;
1da177e4
LT		 2886 uint8_t ipcss, ipcso, tucss, tucso, hdr_len;
2887 int err;
2888
89114afd 2889 if (skb_is_gso(skb)) {
1da177e4
LT		 2890 if (skb_header_cloned(skb)) {
2891 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2892 if (err)
2893 return err;
2894 }
2895
ab6a5bb6 2896 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
7967168c 2897 mss = skb_shinfo(skb)->gso_size;
60828236 2898 if (skb->protocol == htons(ETH_P_IP)) {
eddc9ec5
ACM		 2899 struct iphdr *iph = ip_hdr(skb);
2900 iph->tot_len = 0;
2901 iph->check = 0;
aa8223c7
ACM		 2902 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2903 iph->daddr, 0,
2904 IPPROTO_TCP,
2905 0);
2d7edb92 2906 cmd_length = E1000_TXD_CMD_IP;
ea2ae17d 2907 ipcse = skb_transport_offset(skb) - 1;
e15fdd03 2908 } else if (skb->protocol == htons(ETH_P_IPV6)) {
0660e03f 2909 ipv6_hdr(skb)->payload_len = 0;
aa8223c7 2910 tcp_hdr(skb)->check =
0660e03f
ACM		 2911 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2912 &ipv6_hdr(skb)->daddr,
2913 0, IPPROTO_TCP, 0);
2d7edb92 2914 ipcse = 0;
2d7edb92 2915 }
bbe735e4 2916 ipcss = skb_network_offset(skb);
eddc9ec5 2917 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
ea2ae17d 2918 tucss = skb_transport_offset(skb);
aa8223c7 2919 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
1da177e4
LT		 2920 tucse = 0;
2921
2922 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
2d7edb92 2923 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
1da177e4 2924
581d708e
MC		 2925 i = tx_ring->next_to_use;
2926 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
545c67c0 2927 buffer_info = &tx_ring->buffer_info[i];
1da177e4
LT		 2928
2929 context_desc->lower_setup.ip_fields.ipcss = ipcss;
2930 context_desc->lower_setup.ip_fields.ipcso = ipcso;
2931 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
2932 context_desc->upper_setup.tcp_fields.tucss = tucss;
2933 context_desc->upper_setup.tcp_fields.tucso = tucso;
2934 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
2935 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
2936 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
2937 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
2938
545c67c0 2939 buffer_info->time_stamp = jiffies;
a9ebadd6 2940 buffer_info->next_to_watch = i;
545c67c0 2941
581d708e
MC		 2942 if (++i == tx_ring->count) i = 0;
2943 tx_ring->next_to_use = i;
1da177e4 2944
8241e35e 2945 return TRUE;
1da177e4 2946 }
8241e35e 2947 return FALSE;
1da177e4
LT		 2948}
2949
e619d523 2950static boolean_t
581d708e
MC		 2951e1000_tx_csum(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2952 struct sk_buff *skb)
1da177e4
LT		 2953{
2954 struct e1000_context_desc *context_desc;
545c67c0 2955 struct e1000_buffer *buffer_info;
1da177e4
LT		 2956 unsigned int i;
2957 uint8_t css;
2958
84fa7933 2959 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
ea2ae17d 2960 css = skb_transport_offset(skb);
1da177e4 2961
581d708e 2962 i = tx_ring->next_to_use;
545c67c0 2963 buffer_info = &tx_ring->buffer_info[i];
581d708e 2964 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
1da177e4 2965
f6c57baf 2966 context_desc->lower_setup.ip_config = 0;
1da177e4 2967 context_desc->upper_setup.tcp_fields.tucss = css;
628592cc
HX		 2968 context_desc->upper_setup.tcp_fields.tucso =
2969 css + skb->csum_offset;
1da177e4
LT		 2970 context_desc->upper_setup.tcp_fields.tucse = 0;
2971 context_desc->tcp_seg_setup.data = 0;
2972 context_desc->cmd_and_length = cpu_to_le32(E1000_TXD_CMD_DEXT);
2973
545c67c0 2974 buffer_info->time_stamp = jiffies;
a9ebadd6 2975 buffer_info->next_to_watch = i;
545c67c0 2976
581d708e
MC		 2977 if (unlikely(++i == tx_ring->count)) i = 0;
2978 tx_ring->next_to_use = i;
1da177e4
LT		 2979
2980 return TRUE;
2981 }
2982
2983 return FALSE;
2984}
2985
2986#define E1000_MAX_TXD_PWR 12
2987#define E1000_MAX_DATA_PER_TXD (1<<E1000_MAX_TXD_PWR)
2988
e619d523 2989static int
581d708e
MC		 2990e1000_tx_map(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
2991 struct sk_buff *skb, unsigned int first, unsigned int max_per_txd,
2992 unsigned int nr_frags, unsigned int mss)
1da177e4 2993{
1da177e4
LT		 2994 struct e1000_buffer *buffer_info;
2995 unsigned int len = skb->len;
2996 unsigned int offset = 0, size, count = 0, i;
2997 unsigned int f;
2998 len -= skb->data_len;
2999
3000 i = tx_ring->next_to_use;
3001
96838a40 3002 while (len) {
1da177e4
LT		 3003 buffer_info = &tx_ring->buffer_info[i];
3004 size = min(len, max_per_txd);
fd803241
JK		 3005 /* Workaround for Controller erratum --
3006 * descriptor for non-tso packet in a linear SKB that follows a
3007 * tso gets written back prematurely before the data is fully
0f15a8fa 3008 * DMA'd to the controller */
fd803241 3009 if (!skb->data_len && tx_ring->last_tx_tso &&
89114afd 3010 !skb_is_gso(skb)) {
fd803241
JK		 3011 tx_ring->last_tx_tso = 0;
3012 size -= 4;
3013 }
3014
1da177e4
LT		 3015 /* Workaround for premature desc write-backs
3016 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3017 if (unlikely(mss && !nr_frags && size == len && size > 8))
1da177e4 3018 size -= 4;
97338bde
MC		 3019 /* work-around for errata 10 and it applies
3020 * to all controllers in PCI-X mode
3021 * The fix is to make sure that the first descriptor of a
3022 * packet is smaller than 2048 - 16 - 16 (or 2016) bytes
3023 */
96838a40 3024 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3025 (size > 2015) && count == 0))
3026 size = 2015;
96838a40 3027
1da177e4
LT		 3028 /* Workaround for potential 82544 hang in PCI-X. Avoid
3029 * terminating buffers within evenly-aligned dwords. */
96838a40 3030 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3031 !((unsigned long)(skb->data + offset + size - 1) & 4) &&
3032 size > 4))
3033 size -= 4;
3034
3035 buffer_info->length = size;
3036 buffer_info->dma =
3037 pci_map_single(adapter->pdev,
3038 skb->data + offset,
3039 size,
3040 PCI_DMA_TODEVICE);
3041 buffer_info->time_stamp = jiffies;
a9ebadd6 3042 buffer_info->next_to_watch = i;
1da177e4
LT		 3043
3044 len -= size;
3045 offset += size;
3046 count++;
96838a40 3047 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3048 }
3049
96838a40 3050 for (f = 0; f < nr_frags; f++) {
1da177e4
LT		 3051 struct skb_frag_struct *frag;
3052
3053 frag = &skb_shinfo(skb)->frags[f];
3054 len = frag->size;
3055 offset = frag->page_offset;
3056
96838a40 3057 while (len) {
1da177e4
LT		 3058 buffer_info = &tx_ring->buffer_info[i];
3059 size = min(len, max_per_txd);
1da177e4
LT		 3060 /* Workaround for premature desc write-backs
3061 * in TSO mode. Append 4-byte sentinel desc */
96838a40 3062 if (unlikely(mss && f == (nr_frags-1) && size == len && size > 8))
1da177e4 3063 size -= 4;
1da177e4
LT		 3064 /* Workaround for potential 82544 hang in PCI-X.
3065 * Avoid terminating buffers within evenly-aligned
3066 * dwords. */
96838a40 3067 if (unlikely(adapter->pcix_82544 &&
1da177e4
LT		 3068 !((unsigned long)(frag->page+offset+size-1) & 4) &&
3069 size > 4))
3070 size -= 4;
3071
3072 buffer_info->length = size;
3073 buffer_info->dma =
3074 pci_map_page(adapter->pdev,
3075 frag->page,
3076 offset,
3077 size,
3078 PCI_DMA_TODEVICE);
3079 buffer_info->time_stamp = jiffies;
a9ebadd6 3080 buffer_info->next_to_watch = i;
1da177e4
LT		 3081
3082 len -= size;
3083 offset += size;
3084 count++;
96838a40 3085 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3086 }
3087 }
3088
3089 i = (i == 0) ? tx_ring->count - 1 : i - 1;
3090 tx_ring->buffer_info[i].skb = skb;
3091 tx_ring->buffer_info[first].next_to_watch = i;
3092
3093 return count;
3094}
3095
e619d523 3096static void
581d708e
MC		 3097e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
3098 int tx_flags, int count)
1da177e4 3099{
1da177e4
LT		 3100 struct e1000_tx_desc *tx_desc = NULL;
3101 struct e1000_buffer *buffer_info;
3102 uint32_t txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
3103 unsigned int i;
3104
96838a40 3105 if (likely(tx_flags & E1000_TX_FLAGS_TSO)) {
1da177e4
LT		 3106 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
3107 E1000_TXD_CMD_TSE;
2d7edb92
MC		 3108 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3109
96838a40 3110 if (likely(tx_flags & E1000_TX_FLAGS_IPV4))
2d7edb92 3111 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
1da177e4
LT		 3112 }
3113
96838a40 3114 if (likely(tx_flags & E1000_TX_FLAGS_CSUM)) {
1da177e4
LT		 3115 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
3116 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
3117 }
3118
96838a40 3119 if (unlikely(tx_flags & E1000_TX_FLAGS_VLAN)) {
1da177e4
LT		 3120 txd_lower |= E1000_TXD_CMD_VLE;
3121 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
3122 }
3123
3124 i = tx_ring->next_to_use;
3125
96838a40 3126 while (count--) {
1da177e4
LT		 3127 buffer_info = &tx_ring->buffer_info[i];
3128 tx_desc = E1000_TX_DESC(*tx_ring, i);
3129 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
3130 tx_desc->lower.data =
3131 cpu_to_le32(txd_lower | buffer_info->length);
3132 tx_desc->upper.data = cpu_to_le32(txd_upper);
96838a40 3133 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4
LT		 3134 }
3135
3136 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
3137
3138 /* Force memory writes to complete before letting h/w
3139 * know there are new descriptors to fetch. (Only
3140 * applicable for weak-ordered memory model archs,
3141 * such as IA-64). */
3142 wmb();
3143
3144 tx_ring->next_to_use = i;
581d708e 3145 writel(i, adapter->hw.hw_addr + tx_ring->tdt);
2ce9047f
JB		 3146 /* we need this if more than one processor can write to our tail
3147 * at a time, it syncronizes IO on IA64/Altix systems */
3148 mmiowb();
1da177e4
LT		 3149}
3150
3151/**
3152 * 82547 workaround to avoid controller hang in half-duplex environment.
3153 * The workaround is to avoid queuing a large packet that would span
3154 * the internal Tx FIFO ring boundary by notifying the stack to resend
3155 * the packet at a later time. This gives the Tx FIFO an opportunity to
3156 * flush all packets. When that occurs, we reset the Tx FIFO pointers
3157 * to the beginning of the Tx FIFO.
3158 **/
3159
3160#define E1000_FIFO_HDR 0x10
3161#define E1000_82547_PAD_LEN 0x3E0
3162
e619d523 3163static int
1da177e4
LT		 3164e1000_82547_fifo_workaround(struct e1000_adapter *adapter, struct sk_buff *skb)
3165{
3166 uint32_t fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
3167 uint32_t skb_fifo_len = skb->len + E1000_FIFO_HDR;
3168
9099cfb9 3169 skb_fifo_len = ALIGN(skb_fifo_len, E1000_FIFO_HDR);
1da177e4 3170
96838a40 3171 if (adapter->link_duplex != HALF_DUPLEX)
1da177e4
LT		 3172 goto no_fifo_stall_required;
3173
96838a40 3174 if (atomic_read(&adapter->tx_fifo_stall))
1da177e4
LT		 3175 return 1;
3176
96838a40 3177 if (skb_fifo_len >= (E1000_82547_PAD_LEN + fifo_space)) {
1da177e4
LT		 3178 atomic_set(&adapter->tx_fifo_stall, 1);
3179 return 1;
3180 }
3181
3182no_fifo_stall_required:
3183 adapter->tx_fifo_head += skb_fifo_len;
96838a40 3184 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1da177e4
LT		 3185 adapter->tx_fifo_head -= adapter->tx_fifo_size;
3186 return 0;
3187}
3188
2d7edb92 3189#define MINIMUM_DHCP_PACKET_SIZE 282
e619d523 3190static int
2d7edb92
MC		 3191e1000_transfer_dhcp_info(struct e1000_adapter *adapter, struct sk_buff *skb)
3192{
3193 struct e1000_hw *hw = &adapter->hw;
3194 uint16_t length, offset;
96838a40
JB		 3195 if (vlan_tx_tag_present(skb)) {
3196 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
2d7edb92
MC		 3197 ( adapter->hw.mng_cookie.status &
3198 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT)) )
3199 return 0;
3200 }
20a44028 3201 if (skb->len > MINIMUM_DHCP_PACKET_SIZE) {
2d7edb92 3202 struct ethhdr *eth = (struct ethhdr *) skb->data;
96838a40
JB		 3203 if ((htons(ETH_P_IP) == eth->h_proto)) {
3204 const struct iphdr *ip =
2d7edb92 3205 (struct iphdr *)((uint8_t *)skb->data+14);
96838a40
JB		 3206 if (IPPROTO_UDP == ip->protocol) {
3207 struct udphdr *udp =
3208 (struct udphdr *)((uint8_t *)ip +
2d7edb92 3209 (ip->ihl << 2));
96838a40 3210 if (ntohs(udp->dest) == 67) {
2d7edb92
MC		 3211 offset = (uint8_t *)udp + 8 - skb->data;
3212 length = skb->len - offset;
3213
3214 return e1000_mng_write_dhcp_info(hw,
96838a40 3215 (uint8_t *)udp + 8,
2d7edb92
MC		 3216 length);
3217 }
3218 }
3219 }
3220 }
3221 return 0;
3222}
3223
65c7973f
JB		 3224static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
3225{
3226 struct e1000_adapter *adapter = netdev_priv(netdev);
3227 struct e1000_tx_ring *tx_ring = adapter->tx_ring;
3228
3229 netif_stop_queue(netdev);
3230 /* Herbert's original patch had:
3231 * smp_mb__after_netif_stop_queue();
3232 * but since that doesn't exist yet, just open code it. */
3233 smp_mb();
3234
3235 /* We need to check again in a case another CPU has just
3236 * made room available. */
3237 if (likely(E1000_DESC_UNUSED(tx_ring) < size))
3238 return -EBUSY;
3239
3240 /* A reprieve! */
3241 netif_start_queue(netdev);
fcfb1224 3242 ++adapter->restart_queue;
65c7973f
JB		 3243 return 0;
3244}
3245
3246static int e1000_maybe_stop_tx(struct net_device *netdev,
3247 struct e1000_tx_ring *tx_ring, int size)
3248{
3249 if (likely(E1000_DESC_UNUSED(tx_ring) >= size))
3250 return 0;
3251 return __e1000_maybe_stop_tx(netdev, size);
3252}
3253
1da177e4
LT		 3254#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3255static int
3256e1000_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3257{
60490fe0 3258 struct e1000_adapter *adapter = netdev_priv(netdev);
581d708e 3259 struct e1000_tx_ring *tx_ring;
1da177e4
LT		 3260 unsigned int first, max_per_txd = E1000_MAX_DATA_PER_TXD;
3261 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
3262 unsigned int tx_flags = 0;
3263 unsigned int len = skb->len;
3264 unsigned long flags;
3265 unsigned int nr_frags = 0;
3266 unsigned int mss = 0;
3267 int count = 0;
76c224bc 3268 int tso;
1da177e4
LT		 3269 unsigned int f;
3270 len -= skb->data_len;
3271
65c7973f
JB		 3272 /* This goes back to the question of how to logically map a tx queue
3273 * to a flow. Right now, performance is impacted slightly negatively
3274 * if using multiple tx queues. If the stack breaks away from a
3275 * single qdisc implementation, we can look at this again. */
581d708e 3276 tx_ring = adapter->tx_ring;
24025e4e 3277
581d708e 3278 if (unlikely(skb->len <= 0)) {
1da177e4
LT		 3279 dev_kfree_skb_any(skb);
3280 return NETDEV_TX_OK;
3281 }
3282
032fe6e9
JB		 3283 /* 82571 and newer doesn't need the workaround that limited descriptor
3284 * length to 4kB */
3285 if (adapter->hw.mac_type >= e1000_82571)
3286 max_per_txd = 8192;
3287
7967168c 3288 mss = skb_shinfo(skb)->gso_size;
76c224bc 3289 /* The controller does a simple calculation to
1da177e4
LT		 3290 * make sure there is enough room in the FIFO before
3291 * initiating the DMA for each buffer. The calc is:
3292 * 4 = ceil(buffer len/mss). To make sure we don't
3293 * overrun the FIFO, adjust the max buffer len if mss
3294 * drops. */
96838a40 3295 if (mss) {
9a3056da 3296 uint8_t hdr_len;
1da177e4
LT		 3297 max_per_txd = min(mss << 2, max_per_txd);
3298 max_txd_pwr = fls(max_per_txd) - 1;
9a3056da 3299
90fb5135
AK		 3300 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
3301 * points to just header, pull a few bytes of payload from
3302 * frags into skb->data */
ab6a5bb6 3303 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
9f687888
JK		 3304 if (skb->data_len && (hdr_len == (skb->len - skb->data_len))) {
3305 switch (adapter->hw.mac_type) {
3306 unsigned int pull_size;
683a2aa3
HX		 3307 case e1000_82544:
3308 /* Make sure we have room to chop off 4 bytes,
3309 * and that the end alignment will work out to
3310 * this hardware's requirements
3311 * NOTE: this is a TSO only workaround
3312 * if end byte alignment not correct move us
3313 * into the next dword */
27a884dc 3314 if ((unsigned long)(skb_tail_pointer(skb) - 1) & 4)
683a2aa3
HX		 3315 break;
3316 /* fall through */
9f687888
JK		 3317 case e1000_82571:
3318 case e1000_82572:
3319 case e1000_82573:
cd94dd0b 3320 case e1000_ich8lan:
9f687888
JK		 3321 pull_size = min((unsigned int)4, skb->data_len);
3322 if (!__pskb_pull_tail(skb, pull_size)) {
a5eafce2 3323 DPRINTK(DRV, ERR,
9f687888
JK		 3324 "__pskb_pull_tail failed.\n");
3325 dev_kfree_skb_any(skb);
749dfc70 3326 return NETDEV_TX_OK;
9f687888
JK		 3327 }
3328 len = skb->len - skb->data_len;
3329 break;
3330 default:
3331 /* do nothing */
3332 break;
d74bbd3b 3333 }
9a3056da 3334 }
1da177e4
LT		 3335 }
3336
9a3056da 3337 /* reserve a descriptor for the offload context */
84fa7933 3338 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
1da177e4 3339 count++;
2648345f 3340 count++;
fd803241 3341
fd803241 3342 /* Controller Erratum workaround */
89114afd 3343 if (!skb->data_len && tx_ring->last_tx_tso && !skb_is_gso(skb))
fd803241 3344 count++;
fd803241 3345
1da177e4
LT		 3346 count += TXD_USE_COUNT(len, max_txd_pwr);
3347
96838a40 3348 if (adapter->pcix_82544)
1da177e4
LT		 3349 count++;
3350
96838a40 3351 /* work-around for errata 10 and it applies to all controllers
97338bde
MC		 3352 * in PCI-X mode, so add one more descriptor to the count
3353 */
96838a40 3354 if (unlikely((adapter->hw.bus_type == e1000_bus_type_pcix) &&
97338bde
MC		 3355 (len > 2015)))
3356 count++;
3357
1da177e4 3358 nr_frags = skb_shinfo(skb)->nr_frags;
96838a40 3359 for (f = 0; f < nr_frags; f++)
1da177e4
LT		 3360 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size,
3361 max_txd_pwr);
96838a40 3362 if (adapter->pcix_82544)
1da177e4
LT		 3363 count += nr_frags;
3364
0f15a8fa
JK		 3365
3366 if (adapter->hw.tx_pkt_filtering &&
3367 (adapter->hw.mac_type == e1000_82573))
2d7edb92
MC		 3368 e1000_transfer_dhcp_info(adapter, skb);
3369
f50393fe 3370 if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags))
581d708e 3371 /* Collision - tell upper layer to requeue */
581d708e 3372 return NETDEV_TX_LOCKED;
1da177e4
LT		 3373
3374 /* need: count + 2 desc gap to keep tail from touching
3375 * head, otherwise try next time */
65c7973f 3376 if (unlikely(e1000_maybe_stop_tx(netdev, tx_ring, count + 2))) {
581d708e 3377 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3378 return NETDEV_TX_BUSY;
3379 }
3380
96838a40
JB		 3381 if (unlikely(adapter->hw.mac_type == e1000_82547)) {
3382 if (unlikely(e1000_82547_fifo_workaround(adapter, skb))) {
1da177e4 3383 netif_stop_queue(netdev);
1314bbf3 3384 mod_timer(&adapter->tx_fifo_stall_timer, jiffies + 1);
581d708e 3385 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3386 return NETDEV_TX_BUSY;
3387 }
3388 }
3389
96838a40 3390 if (unlikely(adapter->vlgrp && vlan_tx_tag_present(skb))) {
1da177e4
LT		 3391 tx_flags |= E1000_TX_FLAGS_VLAN;
3392 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
3393 }
3394
581d708e 3395 first = tx_ring->next_to_use;
96838a40 3396
581d708e 3397 tso = e1000_tso(adapter, tx_ring, skb);
1da177e4
LT		 3398 if (tso < 0) {
3399 dev_kfree_skb_any(skb);
581d708e 3400 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3401 return NETDEV_TX_OK;
3402 }
3403
fd803241
JK		 3404 if (likely(tso)) {
3405 tx_ring->last_tx_tso = 1;
1da177e4 3406 tx_flags |= E1000_TX_FLAGS_TSO;
fd803241 3407 } else if (likely(e1000_tx_csum(adapter, tx_ring, skb)))
1da177e4
LT		 3408 tx_flags |= E1000_TX_FLAGS_CSUM;
3409
2d7edb92 3410 /* Old method was to assume IPv4 packet by default if TSO was enabled.
868d5309 3411 * 82571 hardware supports TSO capabilities for IPv6 as well...
2d7edb92 3412 * no longer assume, we must. */
60828236 3413 if (likely(skb->protocol == htons(ETH_P_IP)))
2d7edb92
MC		 3414 tx_flags |= E1000_TX_FLAGS_IPV4;
3415
581d708e
MC		 3416 e1000_tx_queue(adapter, tx_ring, tx_flags,
3417 e1000_tx_map(adapter, tx_ring, skb, first,
3418 max_per_txd, nr_frags, mss));
1da177e4
LT		 3419
3420 netdev->trans_start = jiffies;
3421
3422 /* Make sure there is space in the ring for the next send. */
65c7973f 3423 e1000_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 2);
1da177e4 3424
581d708e 3425 spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
1da177e4
LT		 3426 return NETDEV_TX_OK;
3427}
3428
3429/**
3430 * e1000_tx_timeout - Respond to a Tx Hang
3431 * @netdev: network interface device structure
3432 **/
3433
3434static void
3435e1000_tx_timeout(struct net_device *netdev)
3436{
60490fe0 3437 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 3438
3439 /* Do the reset outside of interrupt context */
87041639
JK		 3440 adapter->tx_timeout_count++;
3441 schedule_work(&adapter->reset_task);
1da177e4
LT		 3442}
3443
3444static void
65f27f38 3445e1000_reset_task(struct work_struct *work)
1da177e4 3446{
65f27f38
DH		 3447 struct e1000_adapter *adapter =
3448 container_of(work, struct e1000_adapter, reset_task);
1da177e4 3449
2db10a08 3450 e1000_reinit_locked(adapter);
1da177e4
LT		 3451}
3452
3453/**
3454 * e1000_get_stats - Get System Network Statistics
3455 * @netdev: network interface device structure
3456 *
3457 * Returns the address of the device statistics structure.
3458 * The statistics are actually updated from the timer callback.
3459 **/
3460
3461static struct net_device_stats *
3462e1000_get_stats(struct net_device *netdev)
3463{
60490fe0 3464 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3465
6b7660cd 3466 /* only return the current stats */
1da177e4
LT		 3467 return &adapter->net_stats;
3468}
3469
3470/**
3471 * e1000_change_mtu - Change the Maximum Transfer Unit
3472 * @netdev: network interface device structure
3473 * @new_mtu: new value for maximum frame size
3474 *
3475 * Returns 0 on success, negative on failure
3476 **/
3477
3478static int
3479e1000_change_mtu(struct net_device *netdev, int new_mtu)
3480{
60490fe0 3481 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3482 int max_frame = new_mtu + ENET_HEADER_SIZE + ETHERNET_FCS_SIZE;
85b22eb6 3483 uint16_t eeprom_data = 0;
1da177e4 3484
96838a40
JB		 3485 if ((max_frame < MINIMUM_ETHERNET_FRAME_SIZE) ||
3486 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
3487 DPRINTK(PROBE, ERR, "Invalid MTU setting\n");
1da177e4 3488 return -EINVAL;
2d7edb92 3489 }
1da177e4 3490
997f5cbd
JK		 3491 /* Adapter-specific max frame size limits. */
3492 switch (adapter->hw.mac_type) {
9e2feace 3493 case e1000_undefined ... e1000_82542_rev2_1:
cd94dd0b 3494 case e1000_ich8lan:
997f5cbd
JK		 3495 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3496 DPRINTK(PROBE, ERR, "Jumbo Frames not supported.\n");
2d7edb92 3497 return -EINVAL;
2d7edb92 3498 }
997f5cbd 3499 break;
85b22eb6 3500 case e1000_82573:
249d71d6
BA		 3501 /* Jumbo Frames not supported if:
3502 * - this is not an 82573L device
3503 * - ASPM is enabled in any way (0x1A bits 3:2) */
85b22eb6
JK		 3504 e1000_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3, 1,
3505 &eeprom_data);
249d71d6
BA		 3506 if ((adapter->hw.device_id != E1000_DEV_ID_82573L) ||
3507 (eeprom_data & EEPROM_WORD1A_ASPM_MASK)) {
85b22eb6
JK		 3508 if (max_frame > MAXIMUM_ETHERNET_FRAME_SIZE) {
3509 DPRINTK(PROBE, ERR,
3510 "Jumbo Frames not supported.\n");
3511 return -EINVAL;
3512 }
3513 break;
3514 }
249d71d6
BA		 3515 /* ERT will be enabled later to enable wire speed receives */
3516
85b22eb6 3517 /* fall through to get support */
997f5cbd
JK		 3518 case e1000_82571:
3519 case e1000_82572:
87041639 3520 case e1000_80003es2lan:
997f5cbd
JK		 3521#define MAX_STD_JUMBO_FRAME_SIZE 9234
3522 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
3523 DPRINTK(PROBE, ERR, "MTU > 9216 not supported.\n");
3524 return -EINVAL;
3525 }
3526 break;
3527 default:
3528 /* Capable of supporting up to MAX_JUMBO_FRAME_SIZE limit. */
3529 break;
1da177e4
LT		 3530 }
3531
87f5032e 3532 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
9e2feace
AK		 3533 * means we reserve 2 more, this pushes us to allocate from the next
3534 * larger slab size
3535 * i.e. RXBUFFER_2048 --> size-4096 slab */
3536
3537 if (max_frame <= E1000_RXBUFFER_256)
3538 adapter->rx_buffer_len = E1000_RXBUFFER_256;
3539 else if (max_frame <= E1000_RXBUFFER_512)
3540 adapter->rx_buffer_len = E1000_RXBUFFER_512;
3541 else if (max_frame <= E1000_RXBUFFER_1024)
3542 adapter->rx_buffer_len = E1000_RXBUFFER_1024;
3543 else if (max_frame <= E1000_RXBUFFER_2048)
3544 adapter->rx_buffer_len = E1000_RXBUFFER_2048;
3545 else if (max_frame <= E1000_RXBUFFER_4096)
3546 adapter->rx_buffer_len = E1000_RXBUFFER_4096;
3547 else if (max_frame <= E1000_RXBUFFER_8192)
3548 adapter->rx_buffer_len = E1000_RXBUFFER_8192;
3549 else if (max_frame <= E1000_RXBUFFER_16384)
3550 adapter->rx_buffer_len = E1000_RXBUFFER_16384;
3551
3552 /* adjust allocation if LPE protects us, and we aren't using SBP */
9e2feace
AK		 3553 if (!adapter->hw.tbi_compatibility_on &&
3554 ((max_frame == MAXIMUM_ETHERNET_FRAME_SIZE) ||
3555 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE)))
3556 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
997f5cbd 3557
2d7edb92 3558 netdev->mtu = new_mtu;
83cd8279 3559 adapter->hw.max_frame_size = max_frame;
2d7edb92 3560
2db10a08
AK		 3561 if (netif_running(netdev))
3562 e1000_reinit_locked(adapter);
1da177e4 3563
1da177e4
LT		 3564 return 0;
3565}
3566
3567/**
3568 * e1000_update_stats - Update the board statistics counters
3569 * @adapter: board private structure
3570 **/
3571
3572void
3573e1000_update_stats(struct e1000_adapter *adapter)
3574{
3575 struct e1000_hw *hw = &adapter->hw;
282f33c9 3576 struct pci_dev *pdev = adapter->pdev;
1da177e4
LT		 3577 unsigned long flags;
3578 uint16_t phy_tmp;
3579
3580#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
3581
282f33c9
LV		 3582 /*
3583 * Prevent stats update while adapter is being reset, or if the pci
3584 * connection is down.
3585 */
9026729b 3586 if (adapter->link_speed == 0)
282f33c9 3587 return;
81b1955e 3588 if (pci_channel_offline(pdev))
9026729b
AK		 3589 return;
3590
1da177e4
LT		 3591 spin_lock_irqsave(&adapter->stats_lock, flags);
3592
3593 /* these counters are modified from e1000_adjust_tbi_stats,
3594 * called from the interrupt context, so they must only
3595 * be written while holding adapter->stats_lock
3596 */
3597
3598 adapter->stats.crcerrs += E1000_READ_REG(hw, CRCERRS);
3599 adapter->stats.gprc += E1000_READ_REG(hw, GPRC);
3600 adapter->stats.gorcl += E1000_READ_REG(hw, GORCL);
3601 adapter->stats.gorch += E1000_READ_REG(hw, GORCH);
3602 adapter->stats.bprc += E1000_READ_REG(hw, BPRC);
3603 adapter->stats.mprc += E1000_READ_REG(hw, MPRC);
3604 adapter->stats.roc += E1000_READ_REG(hw, ROC);
cd94dd0b
AK		 3605
3606 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3607 adapter->stats.prc64 += E1000_READ_REG(hw, PRC64);
3608 adapter->stats.prc127 += E1000_READ_REG(hw, PRC127);
3609 adapter->stats.prc255 += E1000_READ_REG(hw, PRC255);
3610 adapter->stats.prc511 += E1000_READ_REG(hw, PRC511);
3611 adapter->stats.prc1023 += E1000_READ_REG(hw, PRC1023);
3612 adapter->stats.prc1522 += E1000_READ_REG(hw, PRC1522);
cd94dd0b 3613 }
1da177e4
LT		 3614
3615 adapter->stats.symerrs += E1000_READ_REG(hw, SYMERRS);
3616 adapter->stats.mpc += E1000_READ_REG(hw, MPC);
3617 adapter->stats.scc += E1000_READ_REG(hw, SCC);
3618 adapter->stats.ecol += E1000_READ_REG(hw, ECOL);
3619 adapter->stats.mcc += E1000_READ_REG(hw, MCC);
3620 adapter->stats.latecol += E1000_READ_REG(hw, LATECOL);
3621 adapter->stats.dc += E1000_READ_REG(hw, DC);
3622 adapter->stats.sec += E1000_READ_REG(hw, SEC);
3623 adapter->stats.rlec += E1000_READ_REG(hw, RLEC);
3624 adapter->stats.xonrxc += E1000_READ_REG(hw, XONRXC);
3625 adapter->stats.xontxc += E1000_READ_REG(hw, XONTXC);
3626 adapter->stats.xoffrxc += E1000_READ_REG(hw, XOFFRXC);
3627 adapter->stats.xofftxc += E1000_READ_REG(hw, XOFFTXC);
3628 adapter->stats.fcruc += E1000_READ_REG(hw, FCRUC);
3629 adapter->stats.gptc += E1000_READ_REG(hw, GPTC);
3630 adapter->stats.gotcl += E1000_READ_REG(hw, GOTCL);
3631 adapter->stats.gotch += E1000_READ_REG(hw, GOTCH);
3632 adapter->stats.rnbc += E1000_READ_REG(hw, RNBC);
3633 adapter->stats.ruc += E1000_READ_REG(hw, RUC);
3634 adapter->stats.rfc += E1000_READ_REG(hw, RFC);
3635 adapter->stats.rjc += E1000_READ_REG(hw, RJC);
3636 adapter->stats.torl += E1000_READ_REG(hw, TORL);
3637 adapter->stats.torh += E1000_READ_REG(hw, TORH);
3638 adapter->stats.totl += E1000_READ_REG(hw, TOTL);
3639 adapter->stats.toth += E1000_READ_REG(hw, TOTH);
3640 adapter->stats.tpr += E1000_READ_REG(hw, TPR);
cd94dd0b
AK		 3641
3642 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3643 adapter->stats.ptc64 += E1000_READ_REG(hw, PTC64);
3644 adapter->stats.ptc127 += E1000_READ_REG(hw, PTC127);
3645 adapter->stats.ptc255 += E1000_READ_REG(hw, PTC255);
3646 adapter->stats.ptc511 += E1000_READ_REG(hw, PTC511);
3647 adapter->stats.ptc1023 += E1000_READ_REG(hw, PTC1023);
3648 adapter->stats.ptc1522 += E1000_READ_REG(hw, PTC1522);
cd94dd0b
AK		 3649 }
3650
1da177e4
LT		 3651 adapter->stats.mptc += E1000_READ_REG(hw, MPTC);
3652 adapter->stats.bptc += E1000_READ_REG(hw, BPTC);
3653
3654 /* used for adaptive IFS */
3655
3656 hw->tx_packet_delta = E1000_READ_REG(hw, TPT);
3657 adapter->stats.tpt += hw->tx_packet_delta;
3658 hw->collision_delta = E1000_READ_REG(hw, COLC);
3659 adapter->stats.colc += hw->collision_delta;
3660
96838a40 3661 if (hw->mac_type >= e1000_82543) {
1da177e4
LT		 3662 adapter->stats.algnerrc += E1000_READ_REG(hw, ALGNERRC);
3663 adapter->stats.rxerrc += E1000_READ_REG(hw, RXERRC);
3664 adapter->stats.tncrs += E1000_READ_REG(hw, TNCRS);
3665 adapter->stats.cexterr += E1000_READ_REG(hw, CEXTERR);
3666 adapter->stats.tsctc += E1000_READ_REG(hw, TSCTC);
3667 adapter->stats.tsctfc += E1000_READ_REG(hw, TSCTFC);
3668 }
96838a40 3669 if (hw->mac_type > e1000_82547_rev_2) {
2d7edb92
MC		 3670 adapter->stats.iac += E1000_READ_REG(hw, IAC);
3671 adapter->stats.icrxoc += E1000_READ_REG(hw, ICRXOC);
cd94dd0b
AK		 3672
3673 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 3674 adapter->stats.icrxptc += E1000_READ_REG(hw, ICRXPTC);
3675 adapter->stats.icrxatc += E1000_READ_REG(hw, ICRXATC);
3676 adapter->stats.ictxptc += E1000_READ_REG(hw, ICTXPTC);
3677 adapter->stats.ictxatc += E1000_READ_REG(hw, ICTXATC);
3678 adapter->stats.ictxqec += E1000_READ_REG(hw, ICTXQEC);
3679 adapter->stats.ictxqmtc += E1000_READ_REG(hw, ICTXQMTC);
3680 adapter->stats.icrxdmtc += E1000_READ_REG(hw, ICRXDMTC);
cd94dd0b 3681 }
2d7edb92 3682 }
1da177e4
LT		 3683
3684 /* Fill out the OS statistics structure */
1da177e4
LT		 3685 adapter->net_stats.rx_packets = adapter->stats.gprc;
3686 adapter->net_stats.tx_packets = adapter->stats.gptc;
3687 adapter->net_stats.rx_bytes = adapter->stats.gorcl;
3688 adapter->net_stats.tx_bytes = adapter->stats.gotcl;
3689 adapter->net_stats.multicast = adapter->stats.mprc;
3690 adapter->net_stats.collisions = adapter->stats.colc;
3691
3692 /* Rx Errors */
3693
87041639
JK		 3694 /* RLEC on some newer hardware can be incorrect so build
3695 * our own version based on RUC and ROC */
1da177e4
LT		 3696 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
3697 adapter->stats.crcerrs + adapter->stats.algnerrc +
87041639
JK		 3698 adapter->stats.ruc + adapter->stats.roc +
3699 adapter->stats.cexterr;
49559854
MW		 3700 adapter->stats.rlerrc = adapter->stats.ruc + adapter->stats.roc;
3701 adapter->net_stats.rx_length_errors = adapter->stats.rlerrc;
1da177e4
LT		 3702 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3703 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
1da177e4
LT		 3704 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
3705
3706 /* Tx Errors */
49559854
MW		 3707 adapter->stats.txerrc = adapter->stats.ecol + adapter->stats.latecol;
3708 adapter->net_stats.tx_errors = adapter->stats.txerrc;
1da177e4
LT		 3709 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3710 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3711 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
167fb284
JG		 3712 if (adapter->hw.bad_tx_carr_stats_fd &&
3713 adapter->link_duplex == FULL_DUPLEX) {
3714 adapter->net_stats.tx_carrier_errors = 0;
3715 adapter->stats.tncrs = 0;
3716 }
1da177e4
LT		 3717
3718 /* Tx Dropped needs to be maintained elsewhere */
3719
3720 /* Phy Stats */
96838a40
JB		 3721 if (hw->media_type == e1000_media_type_copper) {
3722 if ((adapter->link_speed == SPEED_1000) &&
1da177e4
LT		 3723 (!e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
3724 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3725 adapter->phy_stats.idle_errors += phy_tmp;
3726 }
3727
96838a40 3728 if ((hw->mac_type <= e1000_82546) &&
1da177e4
LT		 3729 (hw->phy_type == e1000_phy_m88) &&
3730 !e1000_read_phy_reg(hw, M88E1000_RX_ERR_CNTR, &phy_tmp))
3731 adapter->phy_stats.receive_errors += phy_tmp;
3732 }
3733
15e376b4
JG		 3734 /* Management Stats */
3735 if (adapter->hw.has_smbus) {
3736 adapter->stats.mgptc += E1000_READ_REG(hw, MGTPTC);
3737 adapter->stats.mgprc += E1000_READ_REG(hw, MGTPRC);
3738 adapter->stats.mgpdc += E1000_READ_REG(hw, MGTPDC);
3739 }
3740
1da177e4
LT		 3741 spin_unlock_irqrestore(&adapter->stats_lock, flags);
3742}
9ac98284
JB		 3743
3744/**
3745 * e1000_intr_msi - Interrupt Handler
3746 * @irq: interrupt number
3747 * @data: pointer to a network interface device structure
3748 **/
3749
b5fc8f0c
JB		 3750static irqreturn_t
3751e1000_intr_msi(int irq, void *data)
9ac98284
JB		 3752{
3753 struct net_device *netdev = data;
3754 struct e1000_adapter *adapter = netdev_priv(netdev);
3755 struct e1000_hw *hw = &adapter->hw;
3756#ifndef CONFIG_E1000_NAPI
3757 int i;
3758#endif
b5fc8f0c 3759 uint32_t icr = E1000_READ_REG(hw, ICR);
9ac98284 3760
9ac98284 3761#ifdef CONFIG_E1000_NAPI
b5fc8f0c
JB		 3762 /* read ICR disables interrupts using IAM, so keep up with our
3763 * enable/disable accounting */
3764 atomic_inc(&adapter->irq_sem);
9ac98284 3765#endif
b5fc8f0c
JB		 3766 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3767 hw->get_link_status = 1;
3768 /* 80003ES2LAN workaround-- For packet buffer work-around on
3769 * link down event; disable receives here in the ISR and reset
3770 * adapter in watchdog */
3771 if (netif_carrier_ok(netdev) &&
3772 (adapter->hw.mac_type == e1000_80003es2lan)) {
3773 /* disable receives */
3774 uint32_t rctl = E1000_READ_REG(hw, RCTL);
3775 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
9ac98284 3776 }
b5fc8f0c
JB		 3777 /* guard against interrupt when we're going down */
3778 if (!test_bit(__E1000_DOWN, &adapter->flags))
3779 mod_timer(&adapter->watchdog_timer, jiffies + 1);
9ac98284
JB		 3780 }
3781
3782#ifdef CONFIG_E1000_NAPI
bea3348e 3783 if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
835bb129
JB		 3784 adapter->total_tx_bytes = 0;
3785 adapter->total_tx_packets = 0;
3786 adapter->total_rx_bytes = 0;
3787 adapter->total_rx_packets = 0;
bea3348e 3788 __netif_rx_schedule(netdev, &adapter->napi);
835bb129 3789 } else
9ac98284
JB		 3790 e1000_irq_enable(adapter);
3791#else
835bb129
JB		 3792 adapter->total_tx_bytes = 0;
3793 adapter->total_rx_bytes = 0;
3794 adapter->total_tx_packets = 0;
3795 adapter->total_rx_packets = 0;
3796
9ac98284
JB		 3797 for (i = 0; i < E1000_MAX_INTR; i++)
3798 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3799 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
9ac98284 3800 break;
835bb129
JB		 3801
3802 if (likely(adapter->itr_setting & 3))
3803 e1000_set_itr(adapter);
9ac98284
JB		 3804#endif
3805
3806 return IRQ_HANDLED;
3807}
1da177e4
LT		 3808
3809/**
3810 * e1000_intr - Interrupt Handler
3811 * @irq: interrupt number
3812 * @data: pointer to a network interface device structure
1da177e4
LT		 3813 **/
3814
3815static irqreturn_t
7d12e780 3816e1000_intr(int irq, void *data)
1da177e4
LT		 3817{
3818 struct net_device *netdev = data;
60490fe0 3819 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 3820 struct e1000_hw *hw = &adapter->hw;
87041639 3821 uint32_t rctl, icr = E1000_READ_REG(hw, ICR);
1e613fd9 3822#ifndef CONFIG_E1000_NAPI
581d708e 3823 int i;
835bb129
JB		 3824#endif
3825 if (unlikely(!icr))
3826 return IRQ_NONE; /* Not our interrupt */
3827
3828#ifdef CONFIG_E1000_NAPI
3829 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3830 * not set, then the adapter didn't send an interrupt */
3831 if (unlikely(hw->mac_type >= e1000_82571 &&
3832 !(icr & E1000_ICR_INT_ASSERTED)))
3833 return IRQ_NONE;
3834
1e613fd9
JK		 3835 /* Interrupt Auto-Mask...upon reading ICR,
3836 * interrupts are masked. No need for the
3837 * IMC write, but it does mean we should
3838 * account for it ASAP. */
3839 if (likely(hw->mac_type >= e1000_82571))
3840 atomic_inc(&adapter->irq_sem);
be2b28ed 3841#endif
1da177e4 3842
96838a40 3843 if (unlikely(icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC))) {
1da177e4 3844 hw->get_link_status = 1;
87041639
JK		 3845 /* 80003ES2LAN workaround--
3846 * For packet buffer work-around on link down event;
3847 * disable receives here in the ISR and
3848 * reset adapter in watchdog
3849 */
3850 if (netif_carrier_ok(netdev) &&
3851 (adapter->hw.mac_type == e1000_80003es2lan)) {
3852 /* disable receives */
3853 rctl = E1000_READ_REG(hw, RCTL);
3854 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
3855 }
1314bbf3
AK		 3856 /* guard against interrupt when we're going down */
3857 if (!test_bit(__E1000_DOWN, &adapter->flags))
3858 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1da177e4
LT		 3859 }
3860
3861#ifdef CONFIG_E1000_NAPI
1e613fd9 3862 if (unlikely(hw->mac_type < e1000_82571)) {
835bb129 3863 /* disable interrupts, without the synchronize_irq bit */
1e613fd9
JK		 3864 atomic_inc(&adapter->irq_sem);
3865 E1000_WRITE_REG(hw, IMC, ~0);
3866 E1000_WRITE_FLUSH(hw);
3867 }
bea3348e 3868 if (likely(netif_rx_schedule_prep(netdev, &adapter->napi))) {
835bb129
JB		 3869 adapter->total_tx_bytes = 0;
3870 adapter->total_tx_packets = 0;
3871 adapter->total_rx_bytes = 0;
3872 adapter->total_rx_packets = 0;
bea3348e 3873 __netif_rx_schedule(netdev, &adapter->napi);
835bb129 3874 } else
90fb5135
AK		 3875 /* this really should not happen! if it does it is basically a
3876 * bug, but not a hard error, so enable ints and continue */
581d708e 3877 e1000_irq_enable(adapter);
c1605eb3 3878#else
1da177e4 3879 /* Writing IMC and IMS is needed for 82547.
96838a40
JB		 3880 * Due to Hub Link bus being occupied, an interrupt
3881 * de-assertion message is not able to be sent.
3882 * When an interrupt assertion message is generated later,
3883 * two messages are re-ordered and sent out.
3884 * That causes APIC to think 82547 is in de-assertion
3885 * state, while 82547 is in assertion state, resulting
3886 * in dead lock. Writing IMC forces 82547 into
3887 * de-assertion state.
3888 */
3889 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2) {
1da177e4 3890 atomic_inc(&adapter->irq_sem);
2648345f 3891 E1000_WRITE_REG(hw, IMC, ~0);
1da177e4
LT		 3892 }
3893
835bb129
JB		 3894 adapter->total_tx_bytes = 0;
3895 adapter->total_rx_bytes = 0;
3896 adapter->total_tx_packets = 0;
3897 adapter->total_rx_packets = 0;
3898
96838a40
JB		 3899 for (i = 0; i < E1000_MAX_INTR; i++)
3900 if (unlikely(!adapter->clean_rx(adapter, adapter->rx_ring) &
46fcc86d 3901 !e1000_clean_tx_irq(adapter, adapter->tx_ring)))
1da177e4
LT		 3902 break;
3903
835bb129
JB		 3904 if (likely(adapter->itr_setting & 3))
3905 e1000_set_itr(adapter);
3906
96838a40 3907 if (hw->mac_type == e1000_82547 || hw->mac_type == e1000_82547_rev_2)
1da177e4 3908 e1000_irq_enable(adapter);
581d708e 3909
c1605eb3 3910#endif
1da177e4
LT		 3911 return IRQ_HANDLED;
3912}
3913
3914#ifdef CONFIG_E1000_NAPI
3915/**
3916 * e1000_clean - NAPI Rx polling callback
3917 * @adapter: board private structure
3918 **/
3919
3920static int
bea3348e 3921e1000_clean(struct napi_struct *napi, int budget)
1da177e4 3922{
bea3348e
SH		 3923 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
3924 struct net_device *poll_dev = adapter->netdev;
d3d9e484 3925 int tx_cleaned = 0, work_done = 0;
581d708e
MC		 3926
3927 /* Must NOT use netdev_priv macro here. */
3928 adapter = poll_dev->priv;
3929
3930 /* Keep link state information with original netdev */
d3d9e484 3931 if (!netif_carrier_ok(poll_dev))
581d708e 3932 goto quit_polling;
2648345f 3933
d3d9e484
AK		 3934 /* e1000_clean is called per-cpu. This lock protects
3935 * tx_ring[0] from being cleaned by multiple cpus
3936 * simultaneously. A failure obtaining the lock means
3937 * tx_ring[0] is currently being cleaned anyway. */
3938 if (spin_trylock(&adapter->tx_queue_lock)) {
3939 tx_cleaned = e1000_clean_tx_irq(adapter,
3940 &adapter->tx_ring[0]);
3941 spin_unlock(&adapter->tx_queue_lock);
581d708e
MC		 3942 }
3943
d3d9e484 3944 adapter->clean_rx(adapter, &adapter->rx_ring[0],
bea3348e 3945 &work_done, budget);
96838a40 3946
2b02893e 3947 /* If no Tx and not enough Rx work done, exit the polling mode */
bea3348e 3948 if ((!tx_cleaned && (work_done < budget)) ||
d3d9e484 3949 !netif_running(poll_dev)) {
581d708e 3950quit_polling:
835bb129
JB		 3951 if (likely(adapter->itr_setting & 3))
3952 e1000_set_itr(adapter);
bea3348e 3953 netif_rx_complete(poll_dev, napi);
1da177e4 3954 e1000_irq_enable(adapter);
1da177e4
LT		 3955 }
3956
bea3348e 3957 return work_done;
1da177e4
LT		 3958}
3959
3960#endif
3961/**
3962 * e1000_clean_tx_irq - Reclaim resources after transmit completes
3963 * @adapter: board private structure
3964 **/
3965
3966static boolean_t
581d708e
MC		 3967e1000_clean_tx_irq(struct e1000_adapter *adapter,
3968 struct e1000_tx_ring *tx_ring)
1da177e4 3969{
1da177e4
LT		 3970 struct net_device *netdev = adapter->netdev;
3971 struct e1000_tx_desc *tx_desc, *eop_desc;
3972 struct e1000_buffer *buffer_info;
3973 unsigned int i, eop;
2a1af5d7
JK		 3974#ifdef CONFIG_E1000_NAPI
3975 unsigned int count = 0;
3976#endif
46fcc86d 3977 boolean_t cleaned = FALSE;
835bb129 3978 unsigned int total_tx_bytes=0, total_tx_packets=0;
1da177e4
LT		 3979
3980 i = tx_ring->next_to_clean;
3981 eop = tx_ring->buffer_info[i].next_to_watch;
3982 eop_desc = E1000_TX_DESC(*tx_ring, eop);
3983
581d708e 3984 while (eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) {
96838a40 3985 for (cleaned = FALSE; !cleaned; ) {
1da177e4
LT		 3986 tx_desc = E1000_TX_DESC(*tx_ring, i);
3987 buffer_info = &tx_ring->buffer_info[i];
3988 cleaned = (i == eop);
3989
835bb129 3990 if (cleaned) {
2b65326e 3991 struct sk_buff *skb = buffer_info->skb;
7753b171
JB		 3992 unsigned int segs, bytecount;
3993 segs = skb_shinfo(skb)->gso_segs ?: 1;
3994 /* multiply data chunks by size of headers */
3995 bytecount = ((segs - 1) * skb_headlen(skb)) +
3996 skb->len;
2b65326e 3997 total_tx_packets += segs;
7753b171 3998 total_tx_bytes += bytecount;
835bb129 3999 }
fd803241 4000 e1000_unmap_and_free_tx_resource(adapter, buffer_info);
a9ebadd6 4001 tx_desc->upper.data = 0;
1da177e4 4002
96838a40 4003 if (unlikely(++i == tx_ring->count)) i = 0;
1da177e4 4004 }
581d708e 4005
1da177e4
LT		 4006 eop = tx_ring->buffer_info[i].next_to_watch;
4007 eop_desc = E1000_TX_DESC(*tx_ring, eop);
2a1af5d7
JK		 4008#ifdef CONFIG_E1000_NAPI
4009#define E1000_TX_WEIGHT 64
4010 /* weight of a sort for tx, to avoid endless transmit cleanup */
46fcc86d 4011 if (count++ == E1000_TX_WEIGHT) break;
2a1af5d7 4012#endif
1da177e4
LT		 4013 }
4014
4015 tx_ring->next_to_clean = i;
4016
77b2aad5 4017#define TX_WAKE_THRESHOLD 32
65c7973f
JB		 4018 if (unlikely(cleaned && netif_carrier_ok(netdev) &&
4019 E1000_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD)) {
4020 /* Make sure that anybody stopping the queue after this
4021 * sees the new next_to_clean.
4022 */
4023 smp_mb();
fcfb1224 4024 if (netif_queue_stopped(netdev)) {
77b2aad5 4025 netif_wake_queue(netdev);
fcfb1224
JB		 4026 ++adapter->restart_queue;
4027 }
77b2aad5 4028 }
2648345f 4029
581d708e 4030 if (adapter->detect_tx_hung) {
2648345f 4031 /* Detect a transmit hang in hardware, this serializes the
1da177e4
LT		 4032 * check with the clearing of time_stamp and movement of i */
4033 adapter->detect_tx_hung = FALSE;
392137fa
JK		 4034 if (tx_ring->buffer_info[eop].dma &&
4035 time_after(jiffies, tx_ring->buffer_info[eop].time_stamp +
7e6c9861 4036 (adapter->tx_timeout_factor * HZ))
70b8f1e1 4037 && !(E1000_READ_REG(&adapter->hw, STATUS) &
392137fa 4038 E1000_STATUS_TXOFF)) {
70b8f1e1
MC		 4039
4040 /* detected Tx unit hang */
c6963ef5 4041 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
7bfa4816 4042 " Tx Queue <%lu>\n"
70b8f1e1
MC		 4043 " TDH <%x>\n"
4044 " TDT <%x>\n"
4045 " next_to_use <%x>\n"
4046 " next_to_clean <%x>\n"
4047 "buffer_info[next_to_clean]\n"
70b8f1e1
MC		 4048 " time_stamp <%lx>\n"
4049 " next_to_watch <%x>\n"
4050 " jiffies <%lx>\n"
4051 " next_to_watch.status <%x>\n",
7bfa4816
JK		 4052 (unsigned long)((tx_ring - adapter->tx_ring) /
4053 sizeof(struct e1000_tx_ring)),
581d708e
MC		 4054 readl(adapter->hw.hw_addr + tx_ring->tdh),
4055 readl(adapter->hw.hw_addr + tx_ring->tdt),
70b8f1e1 4056 tx_ring->next_to_use,
392137fa
JK		 4057 tx_ring->next_to_clean,
4058 tx_ring->buffer_info[eop].time_stamp,
70b8f1e1
MC		 4059 eop,
4060 jiffies,
4061 eop_desc->upper.fields.status);
1da177e4 4062 netif_stop_queue(netdev);
70b8f1e1 4063 }
1da177e4 4064 }
835bb129
JB		 4065 adapter->total_tx_bytes += total_tx_bytes;
4066 adapter->total_tx_packets += total_tx_packets;
1da177e4
LT		 4067 return cleaned;
4068}
4069
4070/**
4071 * e1000_rx_checksum - Receive Checksum Offload for 82543
2d7edb92
MC		 4072 * @adapter: board private structure
4073 * @status_err: receive descriptor status and error fields
4074 * @csum: receive descriptor csum field
4075 * @sk_buff: socket buffer with received data
1da177e4
LT		 4076 **/
4077
e619d523 4078static void
1da177e4 4079e1000_rx_checksum(struct e1000_adapter *adapter,
2d7edb92
MC		 4080 uint32_t status_err, uint32_t csum,
4081 struct sk_buff *skb)
1da177e4 4082{
2d7edb92
MC		 4083 uint16_t status = (uint16_t)status_err;
4084 uint8_t errors = (uint8_t)(status_err >> 24);
4085 skb->ip_summed = CHECKSUM_NONE;
4086
1da177e4 4087 /* 82543 or newer only */
96838a40 4088 if (unlikely(adapter->hw.mac_type < e1000_82543)) return;
1da177e4 4089 /* Ignore Checksum bit is set */
96838a40 4090 if (unlikely(status & E1000_RXD_STAT_IXSM)) return;
2d7edb92 4091 /* TCP/UDP checksum error bit is set */
96838a40 4092 if (unlikely(errors & E1000_RXD_ERR_TCPE)) {
1da177e4 4093 /* let the stack verify checksum errors */
1da177e4 4094 adapter->hw_csum_err++;
2d7edb92
MC		 4095 return;
4096 }
4097 /* TCP/UDP Checksum has not been calculated */
96838a40
JB		 4098 if (adapter->hw.mac_type <= e1000_82547_rev_2) {
4099 if (!(status & E1000_RXD_STAT_TCPCS))
2d7edb92 4100 return;
1da177e4 4101 } else {
96838a40 4102 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
2d7edb92
MC		 4103 return;
4104 }
4105 /* It must be a TCP or UDP packet with a valid checksum */
4106 if (likely(status & E1000_RXD_STAT_TCPCS)) {
1da177e4
LT		 4107 /* TCP checksum is good */
4108 skb->ip_summed = CHECKSUM_UNNECESSARY;
2d7edb92
MC		 4109 } else if (adapter->hw.mac_type > e1000_82547_rev_2) {
4110 /* IP fragment with UDP payload */
4111 /* Hardware complements the payload checksum, so we undo it
4112 * and then put the value in host order for further stack use.
4113 */
4114 csum = ntohl(csum ^ 0xFFFF);
4115 skb->csum = csum;
84fa7933 4116 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 4117 }
2d7edb92 4118 adapter->hw_csum_good++;
1da177e4
LT		 4119}
4120
4121/**
2d7edb92 4122 * e1000_clean_rx_irq - Send received data up the network stack; legacy
1da177e4
LT		 4123 * @adapter: board private structure
4124 **/
4125
4126static boolean_t
4127#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4128e1000_clean_rx_irq(struct e1000_adapter *adapter,
4129 struct e1000_rx_ring *rx_ring,
4130 int *work_done, int work_to_do)
1da177e4 4131#else
581d708e
MC		 4132e1000_clean_rx_irq(struct e1000_adapter *adapter,
4133 struct e1000_rx_ring *rx_ring)
1da177e4
LT		 4134#endif
4135{
1da177e4
LT		 4136 struct net_device *netdev = adapter->netdev;
4137 struct pci_dev *pdev = adapter->pdev;
86c3d59f
JB		 4138 struct e1000_rx_desc *rx_desc, *next_rxd;
4139 struct e1000_buffer *buffer_info, *next_buffer;
1da177e4
LT		 4140 unsigned long flags;
4141 uint32_t length;
4142 uint8_t last_byte;
4143 unsigned int i;
72d64a43 4144 int cleaned_count = 0;
a1415ee6 4145 boolean_t cleaned = FALSE;
835bb129 4146 unsigned int total_rx_bytes=0, total_rx_packets=0;
1da177e4
LT		 4147
4148 i = rx_ring->next_to_clean;
4149 rx_desc = E1000_RX_DESC(*rx_ring, i);
b92ff8ee 4150 buffer_info = &rx_ring->buffer_info[i];
1da177e4 4151
b92ff8ee 4152 while (rx_desc->status & E1000_RXD_STAT_DD) {
24f476ee 4153 struct sk_buff *skb;
a292ca6e 4154 u8 status;
90fb5135 4155
1da177e4 4156#ifdef CONFIG_E1000_NAPI
96838a40 4157 if (*work_done >= work_to_do)
1da177e4
LT		 4158 break;
4159 (*work_done)++;
4160#endif
a292ca6e 4161 status = rx_desc->status;
b92ff8ee 4162 skb = buffer_info->skb;
86c3d59f
JB		 4163 buffer_info->skb = NULL;
4164
30320be8
JK		 4165 prefetch(skb->data - NET_IP_ALIGN);
4166
86c3d59f
JB		 4167 if (++i == rx_ring->count) i = 0;
4168 next_rxd = E1000_RX_DESC(*rx_ring, i);
30320be8
JK		 4169 prefetch(next_rxd);
4170
86c3d59f 4171 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4172
72d64a43
JK		 4173 cleaned = TRUE;
4174 cleaned_count++;
a292ca6e
JK		 4175 pci_unmap_single(pdev,
4176 buffer_info->dma,
4177 buffer_info->length,
1da177e4
LT		 4178 PCI_DMA_FROMDEVICE);
4179
1da177e4
LT		 4180 length = le16_to_cpu(rx_desc->length);
4181
a1415ee6
JK		 4182 if (unlikely(!(status & E1000_RXD_STAT_EOP))) {
4183 /* All receives must fit into a single buffer */
4184 E1000_DBG("%s: Receive packet consumed multiple"
4185 " buffers\n", netdev->name);
864c4e45 4186 /* recycle */
8fc897b0 4187 buffer_info->skb = skb;
1da177e4
LT		 4188 goto next_desc;
4189 }
4190
96838a40 4191 if (unlikely(rx_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK)) {
1da177e4 4192 last_byte = *(skb->data + length - 1);
b92ff8ee 4193 if (TBI_ACCEPT(&adapter->hw, status,
1da177e4
LT		 4194 rx_desc->errors, length, last_byte)) {
4195 spin_lock_irqsave(&adapter->stats_lock, flags);
a292ca6e
JK		 4196 e1000_tbi_adjust_stats(&adapter->hw,
4197 &adapter->stats,
1da177e4
LT		 4198 length, skb->data);
4199 spin_unlock_irqrestore(&adapter->stats_lock,
4200 flags);
4201 length--;
4202 } else {
9e2feace
AK		 4203 /* recycle */
4204 buffer_info->skb = skb;
1da177e4
LT		 4205 goto next_desc;
4206 }
1cb5821f 4207 }
1da177e4 4208
d2a1e213
JB		 4209 /* adjust length to remove Ethernet CRC, this must be
4210 * done after the TBI_ACCEPT workaround above */
4211 length -= 4;
4212
835bb129
JB		 4213 /* probably a little skewed due to removing CRC */
4214 total_rx_bytes += length;
4215 total_rx_packets++;
4216
a292ca6e
JK		 4217 /* code added for copybreak, this should improve
4218 * performance for small packets with large amounts
4219 * of reassembly being done in the stack */
1f753861 4220 if (length < copybreak) {
a292ca6e 4221 struct sk_buff *new_skb =
87f5032e 4222 netdev_alloc_skb(netdev, length + NET_IP_ALIGN);
a292ca6e
JK		 4223 if (new_skb) {
4224 skb_reserve(new_skb, NET_IP_ALIGN);
27d7ff46
ACM		 4225 skb_copy_to_linear_data_offset(new_skb,
4226 -NET_IP_ALIGN,
4227 (skb->data -
4228 NET_IP_ALIGN),
4229 (length +
4230 NET_IP_ALIGN));
a292ca6e
JK		 4231 /* save the skb in buffer_info as good */
4232 buffer_info->skb = skb;
4233 skb = new_skb;
a292ca6e 4234 }
996695de
AK		 4235 /* else just continue with the old one */
4236 }
a292ca6e 4237 /* end copybreak code */
996695de 4238 skb_put(skb, length);
1da177e4
LT		 4239
4240 /* Receive Checksum Offload */
a292ca6e
JK		 4241 e1000_rx_checksum(adapter,
4242 (uint32_t)(status) |
2d7edb92 4243 ((uint32_t)(rx_desc->errors) << 24),
c3d7a3a4 4244 le16_to_cpu(rx_desc->csum), skb);
96838a40 4245
1da177e4
LT		 4246 skb->protocol = eth_type_trans(skb, netdev);
4247#ifdef CONFIG_E1000_NAPI
96838a40 4248 if (unlikely(adapter->vlgrp &&
a292ca6e 4249 (status & E1000_RXD_STAT_VP))) {
1da177e4 4250 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
2d7edb92
MC		 4251 le16_to_cpu(rx_desc->special) &
4252 E1000_RXD_SPC_VLAN_MASK);
1da177e4
LT		 4253 } else {
4254 netif_receive_skb(skb);
4255 }
4256#else /* CONFIG_E1000_NAPI */
96838a40 4257 if (unlikely(adapter->vlgrp &&
b92ff8ee 4258 (status & E1000_RXD_STAT_VP))) {
1da177e4
LT		 4259 vlan_hwaccel_rx(skb, adapter->vlgrp,
4260 le16_to_cpu(rx_desc->special) &
4261 E1000_RXD_SPC_VLAN_MASK);
4262 } else {
4263 netif_rx(skb);
4264 }
4265#endif /* CONFIG_E1000_NAPI */
4266 netdev->last_rx = jiffies;
4267
4268next_desc:
4269 rx_desc->status = 0;
1da177e4 4270
72d64a43
JK		 4271 /* return some buffers to hardware, one at a time is too slow */
4272 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4273 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4274 cleaned_count = 0;
4275 }
4276
30320be8 4277 /* use prefetched values */
86c3d59f
JB		 4278 rx_desc = next_rxd;
4279 buffer_info = next_buffer;
1da177e4 4280 }
1da177e4 4281 rx_ring->next_to_clean = i;
72d64a43
JK		 4282
4283 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4284 if (cleaned_count)
4285 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
2d7edb92 4286
835bb129
JB		 4287 adapter->total_rx_packets += total_rx_packets;
4288 adapter->total_rx_bytes += total_rx_bytes;
2d7edb92
MC		 4289 return cleaned;
4290}
4291
4292/**
4293 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
4294 * @adapter: board private structure
4295 **/
4296
4297static boolean_t
4298#ifdef CONFIG_E1000_NAPI
581d708e
MC		 4299e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4300 struct e1000_rx_ring *rx_ring,
4301 int *work_done, int work_to_do)
2d7edb92 4302#else
581d708e
MC		 4303e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
4304 struct e1000_rx_ring *rx_ring)
2d7edb92
MC		 4305#endif
4306{
86c3d59f 4307 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
2d7edb92
MC		 4308 struct net_device *netdev = adapter->netdev;
4309 struct pci_dev *pdev = adapter->pdev;
86c3d59f 4310 struct e1000_buffer *buffer_info, *next_buffer;
2d7edb92
MC		 4311 struct e1000_ps_page *ps_page;
4312 struct e1000_ps_page_dma *ps_page_dma;
24f476ee 4313 struct sk_buff *skb;
2d7edb92
MC		 4314 unsigned int i, j;
4315 uint32_t length, staterr;
72d64a43 4316 int cleaned_count = 0;
2d7edb92 4317 boolean_t cleaned = FALSE;
835bb129 4318 unsigned int total_rx_bytes=0, total_rx_packets=0;
2d7edb92
MC		 4319
4320 i = rx_ring->next_to_clean;
4321 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
683a38f3 4322 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
9e2feace 4323 buffer_info = &rx_ring->buffer_info[i];
2d7edb92 4324
96838a40 4325 while (staterr & E1000_RXD_STAT_DD) {
2d7edb92
MC		 4326 ps_page = &rx_ring->ps_page[i];
4327 ps_page_dma = &rx_ring->ps_page_dma[i];
4328#ifdef CONFIG_E1000_NAPI
96838a40 4329 if (unlikely(*work_done >= work_to_do))
2d7edb92
MC		 4330 break;
4331 (*work_done)++;
4332#endif
86c3d59f
JB		 4333 skb = buffer_info->skb;
4334
30320be8
JK		 4335 /* in the packet split case this is header only */
4336 prefetch(skb->data - NET_IP_ALIGN);
4337
86c3d59f
JB		 4338 if (++i == rx_ring->count) i = 0;
4339 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
30320be8
JK		 4340 prefetch(next_rxd);
4341
86c3d59f 4342 next_buffer = &rx_ring->buffer_info[i];
86c3d59f 4343
2d7edb92 4344 cleaned = TRUE;
72d64a43 4345 cleaned_count++;
2d7edb92
MC		 4346 pci_unmap_single(pdev, buffer_info->dma,
4347 buffer_info->length,
4348 PCI_DMA_FROMDEVICE);
4349
96838a40 4350 if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) {
2d7edb92
MC		 4351 E1000_DBG("%s: Packet Split buffers didn't pick up"
4352 " the full packet\n", netdev->name);
4353 dev_kfree_skb_irq(skb);
4354 goto next_desc;
4355 }
1da177e4 4356
96838a40 4357 if (unlikely(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2d7edb92
MC		 4358 dev_kfree_skb_irq(skb);
4359 goto next_desc;
4360 }
4361
4362 length = le16_to_cpu(rx_desc->wb.middle.length0);
4363
96838a40 4364 if (unlikely(!length)) {
2d7edb92
MC		 4365 E1000_DBG("%s: Last part of the packet spanning"
4366 " multiple descriptors\n", netdev->name);
4367 dev_kfree_skb_irq(skb);
4368 goto next_desc;
4369 }
4370
4371 /* Good Receive */
4372 skb_put(skb, length);
4373
dc7c6add
JK		 4374 {
4375 /* this looks ugly, but it seems compiler issues make it
4376 more efficient than reusing j */
4377 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
4378
4379 /* page alloc/put takes too long and effects small packet
4380 * throughput, so unsplit small packets and save the alloc/put*/
1f753861 4381 if (l1 && (l1 <= copybreak) && ((length + l1) <= adapter->rx_ps_bsize0)) {
dc7c6add 4382 u8 *vaddr;
76c224bc 4383 /* there is no documentation about how to call
dc7c6add
JK		 4384 * kmap_atomic, so we can't hold the mapping
4385 * very long */
4386 pci_dma_sync_single_for_cpu(pdev,
4387 ps_page_dma->ps_page_dma[0],
4388 PAGE_SIZE,
4389 PCI_DMA_FROMDEVICE);
4390 vaddr = kmap_atomic(ps_page->ps_page[0],
4391 KM_SKB_DATA_SOFTIRQ);
27a884dc 4392 memcpy(skb_tail_pointer(skb), vaddr, l1);
dc7c6add
JK		 4393 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
4394 pci_dma_sync_single_for_device(pdev,
4395 ps_page_dma->ps_page_dma[0],
4396 PAGE_SIZE, PCI_DMA_FROMDEVICE);
f235a2ab
AK		 4397 /* remove the CRC */
4398 l1 -= 4;
dc7c6add 4399 skb_put(skb, l1);
dc7c6add
JK		 4400 goto copydone;
4401 } /* if */
4402 }
90fb5135 4403
96838a40 4404 for (j = 0; j < adapter->rx_ps_pages; j++) {
30320be8 4405 if (!(length= le16_to_cpu(rx_desc->wb.upper.length[j])))
2d7edb92 4406 break;
2d7edb92
MC		 4407 pci_unmap_page(pdev, ps_page_dma->ps_page_dma[j],
4408 PAGE_SIZE, PCI_DMA_FROMDEVICE);
4409 ps_page_dma->ps_page_dma[j] = 0;
329bfd0b
JK		 4410 skb_fill_page_desc(skb, j, ps_page->ps_page[j], 0,
4411 length);
2d7edb92 4412 ps_page->ps_page[j] = NULL;
2d7edb92
MC		 4413 skb->len += length;
4414 skb->data_len += length;
5d51b80f 4415 skb->truesize += length;
2d7edb92
MC		 4416 }
4417
f235a2ab
AK		 4418 /* strip the ethernet crc, problem is we're using pages now so
4419 * this whole operation can get a little cpu intensive */
4420 pskb_trim(skb, skb->len - 4);
4421
dc7c6add 4422copydone:
835bb129
JB		 4423 total_rx_bytes += skb->len;
4424 total_rx_packets++;
4425
2d7edb92 4426 e1000_rx_checksum(adapter, staterr,
c3d7a3a4 4427 le16_to_cpu(rx_desc->wb.lower.hi_dword.csum_ip.csum), skb);
2d7edb92
MC		 4428 skb->protocol = eth_type_trans(skb, netdev);
4429
96838a40 4430 if (likely(rx_desc->wb.upper.header_status &
c3d7a3a4 4431 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)))
e4c811c9 4432 adapter->rx_hdr_split++;
2d7edb92 4433#ifdef CONFIG_E1000_NAPI
96838a40 4434 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4435 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
683a38f3
MC		 4436 le16_to_cpu(rx_desc->wb.middle.vlan) &
4437 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4438 } else {
4439 netif_receive_skb(skb);
4440 }
4441#else /* CONFIG_E1000_NAPI */
96838a40 4442 if (unlikely(adapter->vlgrp && (staterr & E1000_RXD_STAT_VP))) {
2d7edb92 4443 vlan_hwaccel_rx(skb, adapter->vlgrp,
683a38f3
MC		 4444 le16_to_cpu(rx_desc->wb.middle.vlan) &
4445 E1000_RXD_SPC_VLAN_MASK);
2d7edb92
MC		 4446 } else {
4447 netif_rx(skb);
4448 }
4449#endif /* CONFIG_E1000_NAPI */
4450 netdev->last_rx = jiffies;
4451
4452next_desc:
c3d7a3a4 4453 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
2d7edb92 4454 buffer_info->skb = NULL;
2d7edb92 4455
72d64a43
JK		 4456 /* return some buffers to hardware, one at a time is too slow */
4457 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
4458 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
4459 cleaned_count = 0;
4460 }
4461
30320be8 4462 /* use prefetched values */
86c3d59f
JB		 4463 rx_desc = next_rxd;
4464 buffer_info = next_buffer;
4465
683a38f3 4466 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
2d7edb92
MC		 4467 }
4468 rx_ring->next_to_clean = i;
72d64a43
JK		 4469
4470 cleaned_count = E1000_DESC_UNUSED(rx_ring);
4471 if (cleaned_count)
4472 adapter->alloc_rx_buf(adapter, rx_ring, cleaned_count);
1da177e4 4473
835bb129
JB		 4474 adapter->total_rx_packets += total_rx_packets;
4475 adapter->total_rx_bytes += total_rx_bytes;
1da177e4
LT		 4476 return cleaned;
4477}
4478
4479/**
2d7edb92 4480 * e1000_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1da177e4
LT		 4481 * @adapter: address of board private structure
4482 **/
4483
4484static void
581d708e 4485e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
72d64a43 4486 struct e1000_rx_ring *rx_ring,
a292ca6e 4487 int cleaned_count)
1da177e4 4488{
1da177e4
LT		 4489 struct net_device *netdev = adapter->netdev;
4490 struct pci_dev *pdev = adapter->pdev;
4491 struct e1000_rx_desc *rx_desc;
4492 struct e1000_buffer *buffer_info;
4493 struct sk_buff *skb;
2648345f
MC		 4494 unsigned int i;
4495 unsigned int bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1da177e4
LT		 4496
4497 i = rx_ring->next_to_use;
4498 buffer_info = &rx_ring->buffer_info[i];
4499
a292ca6e 4500 while (cleaned_count--) {
ca6f7224
CH		 4501 skb = buffer_info->skb;
4502 if (skb) {
a292ca6e
JK		 4503 skb_trim(skb, 0);
4504 goto map_skb;
4505 }
4506
ca6f7224 4507 skb = netdev_alloc_skb(netdev, bufsz);
96838a40 4508 if (unlikely(!skb)) {
1da177e4 4509 /* Better luck next round */
72d64a43 4510 adapter->alloc_rx_buff_failed++;
1da177e4
LT		 4511 break;
4512 }
4513
2648345f 4514 /* Fix for errata 23, can't cross 64kB boundary */
1da177e4
LT		 4515 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4516 struct sk_buff *oldskb = skb;
2648345f
MC		 4517 DPRINTK(RX_ERR, ERR, "skb align check failed: %u bytes "
4518 "at %p\n", bufsz, skb->data);
4519 /* Try again, without freeing the previous */
87f5032e 4520 skb = netdev_alloc_skb(netdev, bufsz);
2648345f 4521 /* Failed allocation, critical failure */
1da177e4
LT		 4522 if (!skb) {
4523 dev_kfree_skb(oldskb);
4524 break;
4525 }
2648345f 4526
1da177e4
LT		 4527 if (!e1000_check_64k_bound(adapter, skb->data, bufsz)) {
4528 /* give up */
4529 dev_kfree_skb(skb);
4530 dev_kfree_skb(oldskb);
4531 break; /* while !buffer_info->skb */
1da177e4 4532 }
ca6f7224
CH		 4533
4534 /* Use new allocation */
4535 dev_kfree_skb(oldskb);
1da177e4 4536 }
1da177e4
LT		 4537 /* Make buffer alignment 2 beyond a 16 byte boundary
4538 * this will result in a 16 byte aligned IP header after
4539 * the 14 byte MAC header is removed
4540 */
4541 skb_reserve(skb, NET_IP_ALIGN);
4542
1da177e4
LT		 4543 buffer_info->skb = skb;
4544 buffer_info->length = adapter->rx_buffer_len;
a292ca6e 4545map_skb:
1da177e4
LT		 4546 buffer_info->dma = pci_map_single(pdev,
4547 skb->data,
4548 adapter->rx_buffer_len,
4549 PCI_DMA_FROMDEVICE);
4550
2648345f
MC		 4551 /* Fix for errata 23, can't cross 64kB boundary */
4552 if (!e1000_check_64k_bound(adapter,
4553 (void *)(unsigned long)buffer_info->dma,
4554 adapter->rx_buffer_len)) {
4555 DPRINTK(RX_ERR, ERR,
4556 "dma align check failed: %u bytes at %p\n",
4557 adapter->rx_buffer_len,
4558 (void *)(unsigned long)buffer_info->dma);
1da177e4
LT		 4559 dev_kfree_skb(skb);
4560 buffer_info->skb = NULL;
4561
2648345f 4562 pci_unmap_single(pdev, buffer_info->dma,
1da177e4
LT		 4563 adapter->rx_buffer_len,
4564 PCI_DMA_FROMDEVICE);
4565
4566 break; /* while !buffer_info->skb */
4567 }
1da177e4
LT		 4568 rx_desc = E1000_RX_DESC(*rx_ring, i);
4569 rx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4570
96838a40
JB		 4571 if (unlikely(++i == rx_ring->count))
4572 i = 0;
1da177e4
LT		 4573 buffer_info = &rx_ring->buffer_info[i];
4574 }
4575
b92ff8ee
JB		 4576 if (likely(rx_ring->next_to_use != i)) {
4577 rx_ring->next_to_use = i;
4578 if (unlikely(i-- == 0))
4579 i = (rx_ring->count - 1);
4580
4581 /* Force memory writes to complete before letting h/w
4582 * know there are new descriptors to fetch. (Only
4583 * applicable for weak-ordered memory model archs,
4584 * such as IA-64). */
4585 wmb();
4586 writel(i, adapter->hw.hw_addr + rx_ring->rdt);
4587 }
1da177e4
LT		 4588}
4589
2d7edb92
MC		 4590/**
4591 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
4592 * @adapter: address of board private structure
4593 **/
4594
4595static void
581d708e 4596e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
72d64a43
JK		 4597 struct e1000_rx_ring *rx_ring,
4598 int cleaned_count)
2d7edb92 4599{
2d7edb92
MC		 4600 struct net_device *netdev = adapter->netdev;
4601 struct pci_dev *pdev = adapter->pdev;
4602 union e1000_rx_desc_packet_split *rx_desc;
4603 struct e1000_buffer *buffer_info;
4604 struct e1000_ps_page *ps_page;
4605 struct e1000_ps_page_dma *ps_page_dma;
4606 struct sk_buff *skb;
4607 unsigned int i, j;
4608
4609 i = rx_ring->next_to_use;
4610 buffer_info = &rx_ring->buffer_info[i];
4611 ps_page = &rx_ring->ps_page[i];
4612 ps_page_dma = &rx_ring->ps_page_dma[i];
4613
72d64a43 4614 while (cleaned_count--) {
2d7edb92
MC		 4615 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
4616
96838a40 4617 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
e4c811c9
MC		 4618 if (j < adapter->rx_ps_pages) {
4619 if (likely(!ps_page->ps_page[j])) {
4620 ps_page->ps_page[j] =
4621 alloc_page(GFP_ATOMIC);
b92ff8ee
JB		 4622 if (unlikely(!ps_page->ps_page[j])) {
4623 adapter->alloc_rx_buff_failed++;
e4c811c9 4624 goto no_buffers;
b92ff8ee 4625 }
e4c811c9
MC		 4626 ps_page_dma->ps_page_dma[j] =
4627 pci_map_page(pdev,
4628 ps_page->ps_page[j],
4629 0, PAGE_SIZE,
4630 PCI_DMA_FROMDEVICE);
4631 }
4632 /* Refresh the desc even if buffer_addrs didn't
96838a40 4633 * change because each write-back erases
e4c811c9
MC		 4634 * this info.
4635 */
4636 rx_desc->read.buffer_addr[j+1] =
4637 cpu_to_le64(ps_page_dma->ps_page_dma[j]);
4638 } else
4639 rx_desc->read.buffer_addr[j+1] = ~0;
2d7edb92
MC		 4640 }
4641
87f5032e 4642 skb = netdev_alloc_skb(netdev,
90fb5135 4643 adapter->rx_ps_bsize0 + NET_IP_ALIGN);
2d7edb92 4644
b92ff8ee
JB		 4645 if (unlikely(!skb)) {
4646 adapter->alloc_rx_buff_failed++;
2d7edb92 4647 break;
b92ff8ee 4648 }
2d7edb92
MC		 4649
4650 /* Make buffer alignment 2 beyond a 16 byte boundary
4651 * this will result in a 16 byte aligned IP header after
4652 * the 14 byte MAC header is removed
4653 */
4654 skb_reserve(skb, NET_IP_ALIGN);
4655
2d7edb92
MC		 4656 buffer_info->skb = skb;
4657 buffer_info->length = adapter->rx_ps_bsize0;
4658 buffer_info->dma = pci_map_single(pdev, skb->data,
4659 adapter->rx_ps_bsize0,
4660 PCI_DMA_FROMDEVICE);
4661
4662 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
4663
96838a40 4664 if (unlikely(++i == rx_ring->count)) i = 0;
2d7edb92
MC		 4665 buffer_info = &rx_ring->buffer_info[i];
4666 ps_page = &rx_ring->ps_page[i];
4667 ps_page_dma = &rx_ring->ps_page_dma[i];
4668 }
4669
4670no_buffers:
b92ff8ee
JB		 4671 if (likely(rx_ring->next_to_use != i)) {
4672 rx_ring->next_to_use = i;
4673 if (unlikely(i-- == 0)) i = (rx_ring->count - 1);
4674
4675 /* Force memory writes to complete before letting h/w
4676 * know there are new descriptors to fetch. (Only
4677 * applicable for weak-ordered memory model archs,
4678 * such as IA-64). */
4679 wmb();
4680 /* Hardware increments by 16 bytes, but packet split
4681 * descriptors are 32 bytes...so we increment tail
4682 * twice as much.
4683 */
4684 writel(i<<1, adapter->hw.hw_addr + rx_ring->rdt);
4685 }
2d7edb92
MC		 4686}
4687
1da177e4
LT		 4688/**
4689 * e1000_smartspeed - Workaround for SmartSpeed on 82541 and 82547 controllers.
4690 * @adapter:
4691 **/
4692
4693static void
4694e1000_smartspeed(struct e1000_adapter *adapter)
4695{
4696 uint16_t phy_status;
4697 uint16_t phy_ctrl;
4698
96838a40 4699 if ((adapter->hw.phy_type != e1000_phy_igp) || !adapter->hw.autoneg ||
1da177e4
LT		 4700 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
4701 return;
4702
96838a40 4703 if (adapter->smartspeed == 0) {
1da177e4
LT		 4704 /* If Master/Slave config fault is asserted twice,
4705 * we assume back-to-back */
4706 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4707 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4708 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_status);
96838a40 4709 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) return;
1da177e4 4710 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
96838a40 4711 if (phy_ctrl & CR_1000T_MS_ENABLE) {
1da177e4
LT		 4712 phy_ctrl &= ~CR_1000T_MS_ENABLE;
4713 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL,
4714 phy_ctrl);
4715 adapter->smartspeed++;
96838a40 4716 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4717 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL,
4718 &phy_ctrl)) {
4719 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4720 MII_CR_RESTART_AUTO_NEG);
4721 e1000_write_phy_reg(&adapter->hw, PHY_CTRL,
4722 phy_ctrl);
4723 }
4724 }
4725 return;
96838a40 4726 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) {
1da177e4
LT		 4727 /* If still no link, perhaps using 2/3 pair cable */
4728 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_ctrl);
4729 phy_ctrl |= CR_1000T_MS_ENABLE;
4730 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_ctrl);
96838a40 4731 if (!e1000_phy_setup_autoneg(&adapter->hw) &&
1da177e4
LT		 4732 !e1000_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_ctrl)) {
4733 phy_ctrl |= (MII_CR_AUTO_NEG_EN |
4734 MII_CR_RESTART_AUTO_NEG);
4735 e1000_write_phy_reg(&adapter->hw, PHY_CTRL, phy_ctrl);
4736 }
4737 }
4738 /* Restart process after E1000_SMARTSPEED_MAX iterations */
96838a40 4739 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX)
1da177e4
LT		 4740 adapter->smartspeed = 0;
4741}
4742
4743/**
4744 * e1000_ioctl -
4745 * @netdev:
4746 * @ifreq:
4747 * @cmd:
4748 **/
4749
4750static int
4751e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4752{
4753 switch (cmd) {
4754 case SIOCGMIIPHY:
4755 case SIOCGMIIREG:
4756 case SIOCSMIIREG:
4757 return e1000_mii_ioctl(netdev, ifr, cmd);
4758 default:
4759 return -EOPNOTSUPP;
4760 }
4761}
4762
4763/**
4764 * e1000_mii_ioctl -
4765 * @netdev:
4766 * @ifreq:
4767 * @cmd:
4768 **/
4769
4770static int
4771e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
4772{
60490fe0 4773 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4774 struct mii_ioctl_data *data = if_mii(ifr);
4775 int retval;
4776 uint16_t mii_reg;
4777 uint16_t spddplx;
97876fc6 4778 unsigned long flags;
1da177e4 4779
96838a40 4780 if (adapter->hw.media_type != e1000_media_type_copper)
1da177e4
LT		 4781 return -EOPNOTSUPP;
4782
4783 switch (cmd) {
4784 case SIOCGMIIPHY:
4785 data->phy_id = adapter->hw.phy_addr;
4786 break;
4787 case SIOCGMIIREG:
96838a40 4788 if (!capable(CAP_NET_ADMIN))
1da177e4 4789 return -EPERM;
97876fc6 4790 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4791 if (e1000_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
97876fc6
MC		 4792 &data->val_out)) {
4793 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4794 return -EIO;
97876fc6
MC		 4795 }
4796 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4797 break;
4798 case SIOCSMIIREG:
96838a40 4799 if (!capable(CAP_NET_ADMIN))
1da177e4 4800 return -EPERM;
96838a40 4801 if (data->reg_num & ~(0x1F))
1da177e4
LT		 4802 return -EFAULT;
4803 mii_reg = data->val_in;
97876fc6 4804 spin_lock_irqsave(&adapter->stats_lock, flags);
96838a40 4805 if (e1000_write_phy_reg(&adapter->hw, data->reg_num,
97876fc6
MC		 4806 mii_reg)) {
4807 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4 4808 return -EIO;
97876fc6 4809 }
dc86d32a 4810 if (adapter->hw.media_type == e1000_media_type_copper) {
1da177e4
LT		 4811 switch (data->reg_num) {
4812 case PHY_CTRL:
96838a40 4813 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4814 break;
96838a40 4815 if (mii_reg & MII_CR_AUTO_NEG_EN) {
1da177e4
LT		 4816 adapter->hw.autoneg = 1;
4817 adapter->hw.autoneg_advertised = 0x2F;
4818 } else {
4819 if (mii_reg & 0x40)
4820 spddplx = SPEED_1000;
4821 else if (mii_reg & 0x2000)
4822 spddplx = SPEED_100;
4823 else
4824 spddplx = SPEED_10;
4825 spddplx += (mii_reg & 0x100)
cb764326
JK		 4826 ? DUPLEX_FULL :
4827 DUPLEX_HALF;
1da177e4
LT		 4828 retval = e1000_set_spd_dplx(adapter,
4829 spddplx);
96838a40 4830 if (retval) {
97876fc6 4831 spin_unlock_irqrestore(
96838a40 4832 &adapter->stats_lock,
97876fc6 4833 flags);
1da177e4 4834 return retval;
97876fc6 4835 }
1da177e4 4836 }
2db10a08
AK		 4837 if (netif_running(adapter->netdev))
4838 e1000_reinit_locked(adapter);
4839 else
1da177e4
LT		 4840 e1000_reset(adapter);
4841 break;
4842 case M88E1000_PHY_SPEC_CTRL:
4843 case M88E1000_EXT_PHY_SPEC_CTRL:
96838a40 4844 if (e1000_phy_reset(&adapter->hw)) {
97876fc6
MC		 4845 spin_unlock_irqrestore(
4846 &adapter->stats_lock, flags);
1da177e4 4847 return -EIO;
97876fc6 4848 }
1da177e4
LT		 4849 break;
4850 }
4851 } else {
4852 switch (data->reg_num) {
4853 case PHY_CTRL:
96838a40 4854 if (mii_reg & MII_CR_POWER_DOWN)
1da177e4 4855 break;
2db10a08
AK		 4856 if (netif_running(adapter->netdev))
4857 e1000_reinit_locked(adapter);
4858 else
1da177e4
LT		 4859 e1000_reset(adapter);
4860 break;
4861 }
4862 }
97876fc6 4863 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1da177e4
LT		 4864 break;
4865 default:
4866 return -EOPNOTSUPP;
4867 }
4868 return E1000_SUCCESS;
4869}
4870
4871void
4872e1000_pci_set_mwi(struct e1000_hw *hw)
4873{
4874 struct e1000_adapter *adapter = hw->back;
2648345f 4875 int ret_val = pci_set_mwi(adapter->pdev);
1da177e4 4876
96838a40 4877 if (ret_val)
2648345f 4878 DPRINTK(PROBE, ERR, "Error in setting MWI\n");
1da177e4
LT		 4879}
4880
4881void
4882e1000_pci_clear_mwi(struct e1000_hw *hw)
4883{
4884 struct e1000_adapter *adapter = hw->back;
4885
4886 pci_clear_mwi(adapter->pdev);
4887}
4888
4889void
4890e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4891{
4892 struct e1000_adapter *adapter = hw->back;
4893
4894 pci_read_config_word(adapter->pdev, reg, value);
4895}
4896
4897void
4898e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4899{
4900 struct e1000_adapter *adapter = hw->back;
4901
4902 pci_write_config_word(adapter->pdev, reg, *value);
4903}
4904
caeccb68
JK		 4905int32_t
4906e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
4907{
4908 struct e1000_adapter *adapter = hw->back;
4909 uint16_t cap_offset;
4910
4911 cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
4912 if (!cap_offset)
4913 return -E1000_ERR_CONFIG;
4914
4915 pci_read_config_word(adapter->pdev, cap_offset + reg, value);
4916
4917 return E1000_SUCCESS;
4918}
4919
1da177e4
LT		 4920void
4921e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value)
4922{
4923 outl(value, port);
4924}
4925
4926static void
4927e1000_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
4928{
60490fe0 4929 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4930 uint32_t ctrl, rctl;
4931
4932 e1000_irq_disable(adapter);
4933 adapter->vlgrp = grp;
4934
96838a40 4935 if (grp) {
1da177e4
LT		 4936 /* enable VLAN tag insert/strip */
4937 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4938 ctrl |= E1000_CTRL_VME;
4939 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4940
cd94dd0b 4941 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4942 /* enable VLAN receive filtering */
4943 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4944 rctl |= E1000_RCTL_VFE;
4945 rctl &= ~E1000_RCTL_CFIEN;
4946 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4947 e1000_update_mng_vlan(adapter);
cd94dd0b 4948 }
1da177e4
LT		 4949 } else {
4950 /* disable VLAN tag insert/strip */
4951 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
4952 ctrl &= ~E1000_CTRL_VME;
4953 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
4954
cd94dd0b 4955 if (adapter->hw.mac_type != e1000_ich8lan) {
90fb5135
AK		 4956 /* disable VLAN filtering */
4957 rctl = E1000_READ_REG(&adapter->hw, RCTL);
4958 rctl &= ~E1000_RCTL_VFE;
4959 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
4960 if (adapter->mng_vlan_id !=
4961 (uint16_t)E1000_MNG_VLAN_NONE) {
4962 e1000_vlan_rx_kill_vid(netdev,
4963 adapter->mng_vlan_id);
4964 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4965 }
cd94dd0b 4966 }
1da177e4
LT		 4967 }
4968
4969 e1000_irq_enable(adapter);
4970}
4971
4972static void
4973e1000_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid)
4974{
60490fe0 4975 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4 4976 uint32_t vfta, index;
96838a40
JB		 4977
4978 if ((adapter->hw.mng_cookie.status &
4979 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
4980 (vid == adapter->mng_vlan_id))
2d7edb92 4981 return;
1da177e4
LT		 4982 /* add VID to filter table */
4983 index = (vid >> 5) & 0x7F;
4984 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
4985 vfta |= (1 << (vid & 0x1F));
4986 e1000_write_vfta(&adapter->hw, index, vfta);
4987}
4988
4989static void
4990e1000_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid)
4991{
60490fe0 4992 struct e1000_adapter *adapter = netdev_priv(netdev);
1da177e4
LT		 4993 uint32_t vfta, index;
4994
4995 e1000_irq_disable(adapter);
5c15bdec 4996 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1da177e4
LT		 4997 e1000_irq_enable(adapter);
4998
96838a40
JB		 4999 if ((adapter->hw.mng_cookie.status &
5000 E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT) &&
ff147013
JK		 5001 (vid == adapter->mng_vlan_id)) {
5002 /* release control to f/w */
5003 e1000_release_hw_control(adapter);
2d7edb92 5004 return;
ff147013
JK		 5005 }
5006
1da177e4
LT		 5007 /* remove VID from filter table */
5008 index = (vid >> 5) & 0x7F;
5009 vfta = E1000_READ_REG_ARRAY(&adapter->hw, VFTA, index);
5010 vfta &= ~(1 << (vid & 0x1F));
5011 e1000_write_vfta(&adapter->hw, index, vfta);
5012}
5013
5014static void
5015e1000_restore_vlan(struct e1000_adapter *adapter)
5016{
5017 e1000_vlan_rx_register(adapter->netdev, adapter->vlgrp);
5018
96838a40 5019 if (adapter->vlgrp) {
1da177e4 5020 uint16_t vid;
96838a40 5021 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
5c15bdec 5022 if (!vlan_group_get_device(adapter->vlgrp, vid))
1da177e4
LT		 5023 continue;
5024 e1000_vlan_rx_add_vid(adapter->netdev, vid);
5025 }
5026 }
5027}
5028
5029int
5030e1000_set_spd_dplx(struct e1000_adapter *adapter, uint16_t spddplx)
5031{
5032 adapter->hw.autoneg = 0;
5033
6921368f 5034 /* Fiber NICs only allow 1000 gbps Full duplex */
96838a40 5035 if ((adapter->hw.media_type == e1000_media_type_fiber) &&
6921368f
MC		 5036 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
5037 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
5038 return -EINVAL;
5039 }
5040
96838a40 5041 switch (spddplx) {
1da177e4
LT		 5042 case SPEED_10 + DUPLEX_HALF:
5043 adapter->hw.forced_speed_duplex = e1000_10_half;
5044 break;
5045 case SPEED_10 + DUPLEX_FULL:
5046 adapter->hw.forced_speed_duplex = e1000_10_full;
5047 break;
5048 case SPEED_100 + DUPLEX_HALF:
5049 adapter->hw.forced_speed_duplex = e1000_100_half;
5050 break;
5051 case SPEED_100 + DUPLEX_FULL:
5052 adapter->hw.forced_speed_duplex = e1000_100_full;
5053 break;
5054 case SPEED_1000 + DUPLEX_FULL:
5055 adapter->hw.autoneg = 1;
5056 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
5057 break;
5058 case SPEED_1000 + DUPLEX_HALF: /* not supported */
5059 default:
2648345f 5060 DPRINTK(PROBE, ERR, "Unsupported Speed/Duplex configuration\n");
1da177e4
LT		 5061 return -EINVAL;
5062 }
5063 return 0;
5064}
5065
1da177e4 5066static int
829ca9a3 5067e1000_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 5068{
5069 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5070 struct e1000_adapter *adapter = netdev_priv(netdev);
0fccd0e9 5071 uint32_t ctrl, ctrl_ext, rctl, status;
1da177e4 5072 uint32_t wufc = adapter->wol;
6fdfef16 5073#ifdef CONFIG_PM
240b1710 5074 int retval = 0;
6fdfef16 5075#endif
1da177e4
LT		 5076
5077 netif_device_detach(netdev);
5078
2db10a08
AK		 5079 if (netif_running(netdev)) {
5080 WARN_ON(test_bit(__E1000_RESETTING, &adapter->flags));
1da177e4 5081 e1000_down(adapter);
2db10a08 5082 }
1da177e4 5083
2f82665f 5084#ifdef CONFIG_PM
1d33e9c6 5085 retval = pci_save_state(pdev);
2f82665f
JB		 5086 if (retval)
5087 return retval;
5088#endif
5089
1da177e4 5090 status = E1000_READ_REG(&adapter->hw, STATUS);
96838a40 5091 if (status & E1000_STATUS_LU)
1da177e4
LT		 5092 wufc &= ~E1000_WUFC_LNKC;
5093
96838a40 5094 if (wufc) {
1da177e4
LT		 5095 e1000_setup_rctl(adapter);
5096 e1000_set_multi(netdev);
5097
5098 /* turn on all-multi mode if wake on multicast is enabled */
120cd576 5099 if (wufc & E1000_WUFC_MC) {
1da177e4
LT		 5100 rctl = E1000_READ_REG(&adapter->hw, RCTL);
5101 rctl |= E1000_RCTL_MPE;
5102 E1000_WRITE_REG(&adapter->hw, RCTL, rctl);
5103 }
5104
96838a40 5105 if (adapter->hw.mac_type >= e1000_82540) {
1da177e4
LT		 5106 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
5107 /* advertise wake from D3Cold */
5108 #define E1000_CTRL_ADVD3WUC 0x00100000
5109 /* phy power management enable */
5110 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
5111 ctrl |= E1000_CTRL_ADVD3WUC |
5112 E1000_CTRL_EN_PHY_PWR_MGMT;
5113 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
5114 }
5115
96838a40 5116 if (adapter->hw.media_type == e1000_media_type_fiber ||
1da177e4
LT		 5117 adapter->hw.media_type == e1000_media_type_internal_serdes) {
5118 /* keep the laser running in D3 */
5119 ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
5120 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
5121 E1000_WRITE_REG(&adapter->hw, CTRL_EXT, ctrl_ext);
5122 }
5123
2d7edb92
MC		 5124 /* Allow time for pending master requests to run */
5125 e1000_disable_pciex_master(&adapter->hw);
5126
1da177e4
LT		 5127 E1000_WRITE_REG(&adapter->hw, WUC, E1000_WUC_PME_EN);
5128 E1000_WRITE_REG(&adapter->hw, WUFC, wufc);
d0e027db
AK		 5129 pci_enable_wake(pdev, PCI_D3hot, 1);
5130 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5131 } else {
5132 E1000_WRITE_REG(&adapter->hw, WUC, 0);
5133 E1000_WRITE_REG(&adapter->hw, WUFC, 0);
d0e027db
AK		 5134 pci_enable_wake(pdev, PCI_D3hot, 0);
5135 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4
LT		 5136 }
5137
0fccd0e9
JG		 5138 e1000_release_manageability(adapter);
5139
5140 /* make sure adapter isn't asleep if manageability is enabled */
5141 if (adapter->en_mng_pt) {
5142 pci_enable_wake(pdev, PCI_D3hot, 1);
5143 pci_enable_wake(pdev, PCI_D3cold, 1);
1da177e4
LT		 5144 }
5145
cd94dd0b
AK		 5146 if (adapter->hw.phy_type == e1000_phy_igp_3)
5147 e1000_phy_powerdown_workaround(&adapter->hw);
5148
edd106fc
AK		 5149 if (netif_running(netdev))
5150 e1000_free_irq(adapter);
5151
b55ccb35
JK		 5152 /* Release control of h/w to f/w. If f/w is AMT enabled, this
5153 * would have already happened in close and is redundant. */
5154 e1000_release_hw_control(adapter);
2d7edb92 5155
1da177e4 5156 pci_disable_device(pdev);
240b1710 5157
d0e027db 5158 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1da177e4
LT		 5159
5160 return 0;
5161}
5162
2f82665f 5163#ifdef CONFIG_PM
1da177e4
LT		 5164static int
5165e1000_resume(struct pci_dev *pdev)
5166{
5167 struct net_device *netdev = pci_get_drvdata(pdev);
60490fe0 5168 struct e1000_adapter *adapter = netdev_priv(netdev);
0fccd0e9 5169 uint32_t err;
1da177e4 5170
d0e027db 5171 pci_set_power_state(pdev, PCI_D0);
1d33e9c6 5172 pci_restore_state(pdev);
3d1dd8cb
AK		 5173 if ((err = pci_enable_device(pdev))) {
5174 printk(KERN_ERR "e1000: Cannot enable PCI device from suspend\n");
5175 return err;
5176 }
a4cb847d 5177 pci_set_master(pdev);
1da177e4 5178
d0e027db
AK		 5179 pci_enable_wake(pdev, PCI_D3hot, 0);
5180 pci_enable_wake(pdev, PCI_D3cold, 0);
1da177e4 5181
edd106fc
AK		 5182 if (netif_running(netdev) && (err = e1000_request_irq(adapter)))
5183 return err;
5184
5185 e1000_power_up_phy(adapter);
1da177e4
LT		 5186 e1000_reset(adapter);
5187 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5188
0fccd0e9
JG		 5189 e1000_init_manageability(adapter);
5190
96838a40 5191 if (netif_running(netdev))
1da177e4
LT		 5192 e1000_up(adapter);
5193
5194 netif_device_attach(netdev);
5195
b55ccb35
JK		 5196 /* If the controller is 82573 and f/w is AMT, do not set
5197 * DRV_LOAD until the interface is up. For all other cases,
5198 * let the f/w know that the h/w is now under the control
5199 * of the driver. */
5200 if (adapter->hw.mac_type != e1000_82573 ||
5201 !e1000_check_mng_mode(&adapter->hw))
5202 e1000_get_hw_control(adapter);
2d7edb92 5203
1da177e4
LT		 5204 return 0;
5205}
5206#endif
c653e635
AK		 5207
5208static void e1000_shutdown(struct pci_dev *pdev)
5209{
5210 e1000_suspend(pdev, PMSG_SUSPEND);
5211}
5212
1da177e4
LT		 5213#ifdef CONFIG_NET_POLL_CONTROLLER
5214/*
5215 * Polling 'interrupt' - used by things like netconsole to send skbs
5216 * without having to re-enable interrupts. It's not called while
5217 * the interrupt routine is executing.
5218 */
5219static void
2648345f 5220e1000_netpoll(struct net_device *netdev)
1da177e4 5221{
60490fe0 5222 struct e1000_adapter *adapter = netdev_priv(netdev);
d3d9e484 5223
1da177e4 5224 disable_irq(adapter->pdev->irq);
7d12e780 5225 e1000_intr(adapter->pdev->irq, netdev);
c4cfe567 5226 e1000_clean_tx_irq(adapter, adapter->tx_ring);
e8da8be1
JK		 5227#ifndef CONFIG_E1000_NAPI
5228 adapter->clean_rx(adapter, adapter->rx_ring);
5229#endif
1da177e4
LT		 5230 enable_irq(adapter->pdev->irq);
5231}
5232#endif
5233
9026729b
AK		 5234/**
5235 * e1000_io_error_detected - called when PCI error is detected
5236 * @pdev: Pointer to PCI device
5237 * @state: The current pci conneection state
5238 *
5239 * This function is called after a PCI bus error affecting
5240 * this device has been detected.
5241 */
5242static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
5243{
5244 struct net_device *netdev = pci_get_drvdata(pdev);
5245 struct e1000_adapter *adapter = netdev->priv;
5246
5247 netif_device_detach(netdev);
5248
5249 if (netif_running(netdev))
5250 e1000_down(adapter);
72e8d6bb 5251 pci_disable_device(pdev);
9026729b
AK		 5252
5253 /* Request a slot slot reset. */
5254 return PCI_ERS_RESULT_NEED_RESET;
5255}
5256
5257/**
5258 * e1000_io_slot_reset - called after the pci bus has been reset.
5259 * @pdev: Pointer to PCI device
5260 *
5261 * Restart the card from scratch, as if from a cold-boot. Implementation
5262 * resembles the first-half of the e1000_resume routine.
5263 */
5264static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5265{
5266 struct net_device *netdev = pci_get_drvdata(pdev);
5267 struct e1000_adapter *adapter = netdev->priv;
5268
5269 if (pci_enable_device(pdev)) {
5270 printk(KERN_ERR "e1000: Cannot re-enable PCI device after reset.\n");
5271 return PCI_ERS_RESULT_DISCONNECT;
5272 }
5273 pci_set_master(pdev);
5274
dbf38c94
LV		 5275 pci_enable_wake(pdev, PCI_D3hot, 0);
5276 pci_enable_wake(pdev, PCI_D3cold, 0);
9026729b 5277
9026729b
AK		 5278 e1000_reset(adapter);
5279 E1000_WRITE_REG(&adapter->hw, WUS, ~0);
5280
5281 return PCI_ERS_RESULT_RECOVERED;
5282}
5283
5284/**
5285 * e1000_io_resume - called when traffic can start flowing again.
5286 * @pdev: Pointer to PCI device
5287 *
5288 * This callback is called when the error recovery driver tells us that
5289 * its OK to resume normal operation. Implementation resembles the
5290 * second-half of the e1000_resume routine.
5291 */
5292static void e1000_io_resume(struct pci_dev *pdev)
5293{
5294 struct net_device *netdev = pci_get_drvdata(pdev);
5295 struct e1000_adapter *adapter = netdev->priv;
0fccd0e9
JG		 5296
5297 e1000_init_manageability(adapter);
9026729b
AK		 5298
5299 if (netif_running(netdev)) {
5300 if (e1000_up(adapter)) {
5301 printk("e1000: can't bring device back up after reset\n");
5302 return;
5303 }
5304 }
5305
5306 netif_device_attach(netdev);
5307
0fccd0e9
JG		 5308 /* If the controller is 82573 and f/w is AMT, do not set
5309 * DRV_LOAD until the interface is up. For all other cases,
5310 * let the f/w know that the h/w is now under the control
5311 * of the driver. */
5312 if (adapter->hw.mac_type != e1000_82573 ||
5313 !e1000_check_mng_mode(&adapter->hw))
5314 e1000_get_hw_control(adapter);
9026729b 5315
9026729b
AK		 5316}
5317
1da177e4 5318/* e1000_main.c */
Linux kernel - Deliverables
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