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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
451152d9 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
d9c76f99 | 55 | #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */ |
ff10e13c CW |
56 | #define E1000_BASE1000T_STATUS 10 |
57 | #define E1000_IDLE_ERROR_COUNT_MASK 0xFF | |
58 | #define E1000_RECEIVE_ERROR_COUNTER 21 | |
59 | #define E1000_RECEIVE_ERROR_MAX 0xFFFF | |
bc7f75fa | 60 | |
4662e82b BA |
61 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
62 | ||
bc7f75fa AK |
63 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
64 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
65 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 66 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
67 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
68 | u16 words, u16 *data); | |
69 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
70 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
71 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
72 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
caaddaf8 | 73 | static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
4662e82b BA |
74 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
75 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 76 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
17f208de | 77 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); |
1b98c2bb BA |
78 | static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); |
79 | static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); | |
80 | static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); | |
bc7f75fa AK |
81 | |
82 | /** | |
83 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
84 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
85 | **/ |
86 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
87 | { | |
88 | struct e1000_phy_info *phy = &hw->phy; | |
89 | s32 ret_val; | |
90 | ||
318a94d6 | 91 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
92 | phy->type = e1000_phy_none; |
93 | return 0; | |
94 | } | |
95 | ||
96 | phy->addr = 1; | |
97 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
98 | phy->reset_delay_us = 100; | |
99 | ||
17f208de BA |
100 | phy->ops.power_up = e1000_power_up_phy_copper; |
101 | phy->ops.power_down = e1000_power_down_phy_copper_82571; | |
102 | ||
bc7f75fa AK |
103 | switch (hw->mac.type) { |
104 | case e1000_82571: | |
105 | case e1000_82572: | |
106 | phy->type = e1000_phy_igp_2; | |
107 | break; | |
108 | case e1000_82573: | |
109 | phy->type = e1000_phy_m88; | |
110 | break; | |
4662e82b | 111 | case e1000_82574: |
8c81c9c3 | 112 | case e1000_82583: |
4662e82b | 113 | phy->type = e1000_phy_bm; |
1b98c2bb BA |
114 | phy->ops.acquire = e1000_get_hw_semaphore_82574; |
115 | phy->ops.release = e1000_put_hw_semaphore_82574; | |
4662e82b | 116 | break; |
bc7f75fa AK |
117 | default: |
118 | return -E1000_ERR_PHY; | |
119 | break; | |
120 | } | |
121 | ||
122 | /* This can only be done after all function pointers are setup. */ | |
123 | ret_val = e1000_get_phy_id_82571(hw); | |
124 | ||
125 | /* Verify phy id */ | |
126 | switch (hw->mac.type) { | |
127 | case e1000_82571: | |
128 | case e1000_82572: | |
129 | if (phy->id != IGP01E1000_I_PHY_ID) | |
130 | return -E1000_ERR_PHY; | |
131 | break; | |
132 | case e1000_82573: | |
133 | if (phy->id != M88E1111_I_PHY_ID) | |
134 | return -E1000_ERR_PHY; | |
135 | break; | |
4662e82b | 136 | case e1000_82574: |
8c81c9c3 | 137 | case e1000_82583: |
4662e82b BA |
138 | if (phy->id != BME1000_E_PHY_ID_R2) |
139 | return -E1000_ERR_PHY; | |
140 | break; | |
bc7f75fa AK |
141 | default: |
142 | return -E1000_ERR_PHY; | |
143 | break; | |
144 | } | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | /** | |
150 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
151 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
152 | **/ |
153 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
154 | { | |
155 | struct e1000_nvm_info *nvm = &hw->nvm; | |
156 | u32 eecd = er32(EECD); | |
157 | u16 size; | |
158 | ||
159 | nvm->opcode_bits = 8; | |
160 | nvm->delay_usec = 1; | |
161 | switch (nvm->override) { | |
162 | case e1000_nvm_override_spi_large: | |
163 | nvm->page_size = 32; | |
164 | nvm->address_bits = 16; | |
165 | break; | |
166 | case e1000_nvm_override_spi_small: | |
167 | nvm->page_size = 8; | |
168 | nvm->address_bits = 8; | |
169 | break; | |
170 | default: | |
171 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
172 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
173 | break; | |
174 | } | |
175 | ||
176 | switch (hw->mac.type) { | |
177 | case e1000_82573: | |
4662e82b | 178 | case e1000_82574: |
8c81c9c3 | 179 | case e1000_82583: |
bc7f75fa AK |
180 | if (((eecd >> 15) & 0x3) == 0x3) { |
181 | nvm->type = e1000_nvm_flash_hw; | |
182 | nvm->word_size = 2048; | |
ad68076e BA |
183 | /* |
184 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
185 | * to Flash update issue. |
186 | */ | |
187 | eecd &= ~E1000_EECD_AUPDEN; | |
188 | ew32(EECD, eecd); | |
189 | break; | |
190 | } | |
191 | /* Fall Through */ | |
192 | default: | |
ad68076e | 193 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
194 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
195 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
196 | /* |
197 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
198 | * for setting word_size. |
199 | */ | |
200 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
201 | |
202 | /* EEPROM access above 16k is unsupported */ | |
203 | if (size > 14) | |
204 | size = 14; | |
bc7f75fa AK |
205 | nvm->word_size = 1 << size; |
206 | break; | |
207 | } | |
208 | ||
1b98c2bb BA |
209 | /* Function Pointers */ |
210 | switch (hw->mac.type) { | |
211 | case e1000_82574: | |
212 | case e1000_82583: | |
213 | nvm->ops.acquire = e1000_get_hw_semaphore_82574; | |
214 | nvm->ops.release = e1000_put_hw_semaphore_82574; | |
215 | break; | |
216 | default: | |
217 | break; | |
218 | } | |
219 | ||
bc7f75fa AK |
220 | return 0; |
221 | } | |
222 | ||
223 | /** | |
224 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
225 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
226 | **/ |
227 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
228 | { | |
229 | struct e1000_hw *hw = &adapter->hw; | |
230 | struct e1000_mac_info *mac = &hw->mac; | |
231 | struct e1000_mac_operations *func = &mac->ops; | |
23a2d1b2 DG |
232 | u32 swsm = 0; |
233 | u32 swsm2 = 0; | |
234 | bool force_clear_smbi = false; | |
bc7f75fa AK |
235 | |
236 | /* Set media type */ | |
237 | switch (adapter->pdev->device) { | |
238 | case E1000_DEV_ID_82571EB_FIBER: | |
239 | case E1000_DEV_ID_82572EI_FIBER: | |
240 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 241 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
242 | break; |
243 | case E1000_DEV_ID_82571EB_SERDES: | |
244 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
245 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
246 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 247 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
248 | break; |
249 | default: | |
318a94d6 | 250 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
251 | break; |
252 | } | |
253 | ||
254 | /* Set mta register count */ | |
255 | mac->mta_reg_count = 128; | |
256 | /* Set rar entry count */ | |
257 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
f464ba87 BA |
258 | /* Adaptive IFS supported */ |
259 | mac->adaptive_ifs = true; | |
bc7f75fa AK |
260 | |
261 | /* check for link */ | |
318a94d6 | 262 | switch (hw->phy.media_type) { |
bc7f75fa AK |
263 | case e1000_media_type_copper: |
264 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
265 | func->check_for_link = e1000e_check_for_copper_link; | |
266 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
267 | break; | |
268 | case e1000_media_type_fiber: | |
ad68076e BA |
269 | func->setup_physical_interface = |
270 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 271 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
272 | func->get_link_up_info = |
273 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
274 | break; |
275 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
276 | func->setup_physical_interface = |
277 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 278 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
279 | func->get_link_up_info = |
280 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
281 | break; |
282 | default: | |
283 | return -E1000_ERR_CONFIG; | |
284 | break; | |
285 | } | |
286 | ||
4662e82b | 287 | switch (hw->mac.type) { |
f4d2dd4c BA |
288 | case e1000_82573: |
289 | func->set_lan_id = e1000_set_lan_id_single_port; | |
290 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
291 | func->led_on = e1000e_led_on_generic; | |
a65a4a0d BA |
292 | |
293 | /* FWSM register */ | |
294 | mac->has_fwsm = true; | |
295 | /* | |
296 | * ARC supported; valid only if manageability features are | |
297 | * enabled. | |
298 | */ | |
299 | mac->arc_subsystem_valid = | |
300 | (er32(FWSM) & E1000_FWSM_MODE_MASK) | |
301 | ? true : false; | |
f4d2dd4c | 302 | break; |
4662e82b | 303 | case e1000_82574: |
8c81c9c3 | 304 | case e1000_82583: |
f4d2dd4c | 305 | func->set_lan_id = e1000_set_lan_id_single_port; |
4662e82b BA |
306 | func->check_mng_mode = e1000_check_mng_mode_82574; |
307 | func->led_on = e1000_led_on_82574; | |
308 | break; | |
309 | default: | |
310 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
311 | func->led_on = e1000e_led_on_generic; | |
a65a4a0d BA |
312 | |
313 | /* FWSM register */ | |
314 | mac->has_fwsm = true; | |
4662e82b BA |
315 | break; |
316 | } | |
317 | ||
23a2d1b2 DG |
318 | /* |
319 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
320 | * first NVM or PHY acess. This should be done for single-port | |
321 | * devices, and for one port only on dual-port devices so that | |
322 | * for those devices we can still use the SMBI lock to synchronize | |
323 | * inter-port accesses to the PHY & NVM. | |
324 | */ | |
325 | switch (hw->mac.type) { | |
326 | case e1000_82571: | |
327 | case e1000_82572: | |
328 | swsm2 = er32(SWSM2); | |
329 | ||
330 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
331 | /* Only do this for the first interface on this card */ | |
332 | ew32(SWSM2, | |
333 | swsm2 | E1000_SWSM2_LOCK); | |
334 | force_clear_smbi = true; | |
335 | } else | |
336 | force_clear_smbi = false; | |
337 | break; | |
338 | default: | |
339 | force_clear_smbi = true; | |
340 | break; | |
341 | } | |
342 | ||
343 | if (force_clear_smbi) { | |
344 | /* Make sure SWSM.SMBI is clear */ | |
345 | swsm = er32(SWSM); | |
346 | if (swsm & E1000_SWSM_SMBI) { | |
347 | /* This bit should not be set on a first interface, and | |
348 | * indicates that the bootagent or EFI code has | |
349 | * improperly left this bit enabled | |
350 | */ | |
3bb99fe2 | 351 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
352 | } |
353 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
354 | } | |
355 | ||
356 | /* | |
2c73e1fe | 357 | * Initialize device specific counter of SMBI acquisition |
23a2d1b2 DG |
358 | * timeouts. |
359 | */ | |
360 | hw->dev_spec.e82571.smb_counter = 0; | |
361 | ||
bc7f75fa AK |
362 | return 0; |
363 | } | |
364 | ||
69e3fd8c | 365 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
366 | { |
367 | struct e1000_hw *hw = &adapter->hw; | |
368 | static int global_quad_port_a; /* global port a indication */ | |
369 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
370 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; |
371 | s32 rc; | |
372 | ||
373 | rc = e1000_init_mac_params_82571(adapter); | |
374 | if (rc) | |
375 | return rc; | |
376 | ||
377 | rc = e1000_init_nvm_params_82571(hw); | |
378 | if (rc) | |
379 | return rc; | |
380 | ||
381 | rc = e1000_init_phy_params_82571(hw); | |
382 | if (rc) | |
383 | return rc; | |
384 | ||
385 | /* tag quad port adapters first, it's used below */ | |
386 | switch (pdev->device) { | |
387 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
388 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
389 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 390 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
391 | adapter->flags |= FLAG_IS_QUAD_PORT; |
392 | /* mark the first port */ | |
393 | if (global_quad_port_a == 0) | |
394 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
395 | /* Reset for multiple quad port adapters */ | |
396 | global_quad_port_a++; | |
397 | if (global_quad_port_a == 4) | |
398 | global_quad_port_a = 0; | |
399 | break; | |
400 | default: | |
401 | break; | |
402 | } | |
403 | ||
404 | switch (adapter->hw.mac.type) { | |
405 | case e1000_82571: | |
406 | /* these dual ports don't have WoL on port B at all */ | |
407 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
408 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
409 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
410 | (is_port_b)) | |
411 | adapter->flags &= ~FLAG_HAS_WOL; | |
412 | /* quad ports only support WoL on port A */ | |
413 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 414 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 415 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
416 | /* Does not support WoL on any port */ |
417 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
418 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa | 419 | break; |
bc7f75fa | 420 | case e1000_82573: |
6f461f6c BA |
421 | case e1000_82574: |
422 | case e1000_82583: | |
423 | /* Disable ASPM L0s due to hardware errata */ | |
424 | e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S); | |
425 | ||
bc7f75fa | 426 | if (pdev->device == E1000_DEV_ID_82573L) { |
6f461f6c BA |
427 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; |
428 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
bc7f75fa AK |
429 | } |
430 | break; | |
431 | default: | |
432 | break; | |
433 | } | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | /** | |
439 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
440 | * @hw: pointer to the HW structure | |
441 | * | |
442 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
443 | * revision in the hardware structure. | |
444 | **/ | |
445 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
446 | { | |
447 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
448 | s32 ret_val; |
449 | u16 phy_id = 0; | |
bc7f75fa AK |
450 | |
451 | switch (hw->mac.type) { | |
452 | case e1000_82571: | |
453 | case e1000_82572: | |
ad68076e BA |
454 | /* |
455 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
456 | * In this case, we cannot access the PHY until the |
457 | * configuration is done. So we explicitly set the | |
ad68076e BA |
458 | * PHY ID. |
459 | */ | |
bc7f75fa AK |
460 | phy->id = IGP01E1000_I_PHY_ID; |
461 | break; | |
462 | case e1000_82573: | |
463 | return e1000e_get_phy_id(hw); | |
464 | break; | |
4662e82b | 465 | case e1000_82574: |
8c81c9c3 | 466 | case e1000_82583: |
4662e82b BA |
467 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
468 | if (ret_val) | |
469 | return ret_val; | |
470 | ||
471 | phy->id = (u32)(phy_id << 16); | |
472 | udelay(20); | |
473 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
474 | if (ret_val) | |
475 | return ret_val; | |
476 | ||
477 | phy->id |= (u32)(phy_id); | |
478 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
479 | break; | |
bc7f75fa AK |
480 | default: |
481 | return -E1000_ERR_PHY; | |
482 | break; | |
483 | } | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | /** | |
489 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
490 | * @hw: pointer to the HW structure | |
491 | * | |
492 | * Acquire the HW semaphore to access the PHY or NVM | |
493 | **/ | |
494 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
495 | { | |
496 | u32 swsm; | |
23a2d1b2 DG |
497 | s32 sw_timeout = hw->nvm.word_size + 1; |
498 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
499 | s32 i = 0; |
500 | ||
23a2d1b2 DG |
501 | /* |
502 | * If we have timedout 3 times on trying to acquire | |
503 | * the inter-port SMBI semaphore, there is old code | |
504 | * operating on the other port, and it is not | |
505 | * releasing SMBI. Modify the number of times that | |
506 | * we try for the semaphore to interwork with this | |
507 | * older code. | |
508 | */ | |
509 | if (hw->dev_spec.e82571.smb_counter > 2) | |
510 | sw_timeout = 1; | |
511 | ||
512 | /* Get the SW semaphore */ | |
513 | while (i < sw_timeout) { | |
514 | swsm = er32(SWSM); | |
515 | if (!(swsm & E1000_SWSM_SMBI)) | |
516 | break; | |
517 | ||
518 | udelay(50); | |
519 | i++; | |
520 | } | |
521 | ||
522 | if (i == sw_timeout) { | |
3bb99fe2 | 523 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
524 | hw->dev_spec.e82571.smb_counter++; |
525 | } | |
bc7f75fa | 526 | /* Get the FW semaphore. */ |
23a2d1b2 | 527 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
528 | swsm = er32(SWSM); |
529 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
530 | ||
531 | /* Semaphore acquired if bit latched */ | |
532 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
533 | break; | |
534 | ||
535 | udelay(50); | |
536 | } | |
537 | ||
23a2d1b2 | 538 | if (i == fw_timeout) { |
bc7f75fa | 539 | /* Release semaphores */ |
23a2d1b2 | 540 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 541 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
542 | return -E1000_ERR_NVM; |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | /** | |
549 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
550 | * @hw: pointer to the HW structure | |
551 | * | |
552 | * Release hardware semaphore used to access the PHY or NVM | |
553 | **/ | |
554 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
555 | { | |
556 | u32 swsm; | |
557 | ||
558 | swsm = er32(SWSM); | |
23a2d1b2 | 559 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
560 | ew32(SWSM, swsm); |
561 | } | |
1b98c2bb BA |
562 | /** |
563 | * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore | |
564 | * @hw: pointer to the HW structure | |
565 | * | |
566 | * Acquire the HW semaphore during reset. | |
567 | * | |
568 | **/ | |
569 | static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) | |
570 | { | |
571 | u32 extcnf_ctrl; | |
572 | s32 ret_val = 0; | |
573 | s32 i = 0; | |
574 | ||
575 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
576 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
577 | do { | |
578 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
579 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
580 | ||
581 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
582 | break; | |
583 | ||
584 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
585 | ||
586 | msleep(2); | |
587 | i++; | |
588 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
589 | ||
590 | if (i == MDIO_OWNERSHIP_TIMEOUT) { | |
591 | /* Release semaphores */ | |
592 | e1000_put_hw_semaphore_82573(hw); | |
593 | e_dbg("Driver can't access the PHY\n"); | |
594 | ret_val = -E1000_ERR_PHY; | |
595 | goto out; | |
596 | } | |
597 | ||
598 | out: | |
599 | return ret_val; | |
600 | } | |
601 | ||
602 | /** | |
603 | * e1000_put_hw_semaphore_82573 - Release hardware semaphore | |
604 | * @hw: pointer to the HW structure | |
605 | * | |
606 | * Release hardware semaphore used during reset. | |
607 | * | |
608 | **/ | |
609 | static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) | |
610 | { | |
611 | u32 extcnf_ctrl; | |
612 | ||
613 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
614 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
615 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
616 | } | |
617 | ||
618 | static DEFINE_MUTEX(swflag_mutex); | |
619 | ||
620 | /** | |
621 | * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore | |
622 | * @hw: pointer to the HW structure | |
623 | * | |
624 | * Acquire the HW semaphore to access the PHY or NVM. | |
625 | * | |
626 | **/ | |
627 | static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) | |
628 | { | |
629 | s32 ret_val; | |
630 | ||
631 | mutex_lock(&swflag_mutex); | |
632 | ret_val = e1000_get_hw_semaphore_82573(hw); | |
633 | if (ret_val) | |
634 | mutex_unlock(&swflag_mutex); | |
635 | return ret_val; | |
636 | } | |
637 | ||
638 | /** | |
639 | * e1000_put_hw_semaphore_82574 - Release hardware semaphore | |
640 | * @hw: pointer to the HW structure | |
641 | * | |
642 | * Release hardware semaphore used to access the PHY or NVM | |
643 | * | |
644 | **/ | |
645 | static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) | |
646 | { | |
647 | e1000_put_hw_semaphore_82573(hw); | |
648 | mutex_unlock(&swflag_mutex); | |
649 | } | |
bc7f75fa AK |
650 | |
651 | /** | |
652 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
653 | * @hw: pointer to the HW structure | |
654 | * | |
655 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
656 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
657 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
658 | * hardware semaphore. | |
659 | **/ | |
660 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
661 | { | |
662 | s32 ret_val; | |
663 | ||
664 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
665 | if (ret_val) | |
666 | return ret_val; | |
667 | ||
8c81c9c3 AD |
668 | switch (hw->mac.type) { |
669 | case e1000_82573: | |
8c81c9c3 AD |
670 | break; |
671 | default: | |
bc7f75fa | 672 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
673 | break; |
674 | } | |
bc7f75fa AK |
675 | |
676 | if (ret_val) | |
677 | e1000_put_hw_semaphore_82571(hw); | |
678 | ||
679 | return ret_val; | |
680 | } | |
681 | ||
682 | /** | |
683 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
684 | * @hw: pointer to the HW structure | |
685 | * | |
686 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
687 | **/ | |
688 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
689 | { | |
690 | e1000e_release_nvm(hw); | |
691 | e1000_put_hw_semaphore_82571(hw); | |
692 | } | |
693 | ||
694 | /** | |
695 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
696 | * @hw: pointer to the HW structure | |
697 | * @offset: offset within the EEPROM to be written to | |
698 | * @words: number of words to write | |
699 | * @data: 16 bit word(s) to be written to the EEPROM | |
700 | * | |
701 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
702 | * | |
703 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 704 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
705 | **/ |
706 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
707 | u16 *data) | |
708 | { | |
709 | s32 ret_val; | |
710 | ||
711 | switch (hw->mac.type) { | |
712 | case e1000_82573: | |
4662e82b | 713 | case e1000_82574: |
8c81c9c3 | 714 | case e1000_82583: |
bc7f75fa AK |
715 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
716 | break; | |
717 | case e1000_82571: | |
718 | case e1000_82572: | |
719 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
720 | break; | |
721 | default: | |
722 | ret_val = -E1000_ERR_NVM; | |
723 | break; | |
724 | } | |
725 | ||
726 | return ret_val; | |
727 | } | |
728 | ||
729 | /** | |
730 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
731 | * @hw: pointer to the HW structure | |
732 | * | |
733 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
734 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
735 | * value to the EEPROM. | |
736 | **/ | |
737 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
738 | { | |
739 | u32 eecd; | |
740 | s32 ret_val; | |
741 | u16 i; | |
742 | ||
743 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
744 | if (ret_val) | |
745 | return ret_val; | |
746 | ||
ad68076e BA |
747 | /* |
748 | * If our nvm is an EEPROM, then we're done | |
749 | * otherwise, commit the checksum to the flash NVM. | |
750 | */ | |
bc7f75fa AK |
751 | if (hw->nvm.type != e1000_nvm_flash_hw) |
752 | return ret_val; | |
753 | ||
754 | /* Check for pending operations. */ | |
755 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
756 | msleep(1); | |
757 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
758 | break; | |
759 | } | |
760 | ||
761 | if (i == E1000_FLASH_UPDATES) | |
762 | return -E1000_ERR_NVM; | |
763 | ||
764 | /* Reset the firmware if using STM opcode. */ | |
765 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
766 | /* |
767 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
768 | * in two write cycles. |
769 | */ | |
770 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
771 | e1e_flush(); | |
772 | ew32(HICR, E1000_HICR_FW_RESET); | |
773 | } | |
774 | ||
775 | /* Commit the write to flash */ | |
776 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
777 | ew32(EECD, eecd); | |
778 | ||
779 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
780 | msleep(1); | |
781 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
782 | break; | |
783 | } | |
784 | ||
785 | if (i == E1000_FLASH_UPDATES) | |
786 | return -E1000_ERR_NVM; | |
787 | ||
788 | return 0; | |
789 | } | |
790 | ||
791 | /** | |
792 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
793 | * @hw: pointer to the HW structure | |
794 | * | |
795 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
796 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
797 | **/ | |
798 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
799 | { | |
800 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
801 | e1000_fix_nvm_checksum_82571(hw); | |
802 | ||
803 | return e1000e_validate_nvm_checksum_generic(hw); | |
804 | } | |
805 | ||
806 | /** | |
807 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
808 | * @hw: pointer to the HW structure | |
809 | * @offset: offset within the EEPROM to be written to | |
810 | * @words: number of words to write | |
811 | * @data: 16 bit word(s) to be written to the EEPROM | |
812 | * | |
813 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
814 | * command has completed before trying to write the next word. After write | |
815 | * poll for completion. | |
816 | * | |
817 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 818 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
819 | **/ |
820 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
821 | u16 words, u16 *data) | |
822 | { | |
823 | struct e1000_nvm_info *nvm = &hw->nvm; | |
a708dd88 | 824 | u32 i, eewr = 0; |
bc7f75fa AK |
825 | s32 ret_val = 0; |
826 | ||
ad68076e BA |
827 | /* |
828 | * A check for invalid values: offset too large, too many words, | |
829 | * and not enough words. | |
830 | */ | |
bc7f75fa AK |
831 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
832 | (words == 0)) { | |
3bb99fe2 | 833 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
834 | return -E1000_ERR_NVM; |
835 | } | |
836 | ||
837 | for (i = 0; i < words; i++) { | |
838 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
839 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
840 | E1000_NVM_RW_REG_START; | |
841 | ||
842 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
843 | if (ret_val) | |
844 | break; | |
845 | ||
846 | ew32(EEWR, eewr); | |
847 | ||
848 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
849 | if (ret_val) | |
850 | break; | |
851 | } | |
852 | ||
853 | return ret_val; | |
854 | } | |
855 | ||
856 | /** | |
857 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
858 | * @hw: pointer to the HW structure | |
859 | * | |
860 | * Reads the management control register for the config done bit to be set. | |
861 | **/ | |
862 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
863 | { | |
864 | s32 timeout = PHY_CFG_TIMEOUT; | |
865 | ||
866 | while (timeout) { | |
867 | if (er32(EEMNGCTL) & | |
868 | E1000_NVM_CFG_DONE_PORT_0) | |
869 | break; | |
870 | msleep(1); | |
871 | timeout--; | |
872 | } | |
873 | if (!timeout) { | |
3bb99fe2 | 874 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
875 | return -E1000_ERR_RESET; |
876 | } | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | /** | |
882 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
883 | * @hw: pointer to the HW structure | |
564ea9bb | 884 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
885 | * |
886 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
887 | * this function also disables smart speed and vice versa. LPLU will not be | |
888 | * activated unless the device autonegotiation advertisement meets standards | |
889 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
890 | * pointer entry point only called by PHY setup routines. | |
891 | **/ | |
892 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
893 | { | |
894 | struct e1000_phy_info *phy = &hw->phy; | |
895 | s32 ret_val; | |
896 | u16 data; | |
897 | ||
898 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
899 | if (ret_val) | |
900 | return ret_val; | |
901 | ||
902 | if (active) { | |
903 | data |= IGP02E1000_PM_D0_LPLU; | |
904 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
905 | if (ret_val) | |
906 | return ret_val; | |
907 | ||
908 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
909 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
910 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
911 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
912 | if (ret_val) | |
913 | return ret_val; | |
914 | } else { | |
915 | data &= ~IGP02E1000_PM_D0_LPLU; | |
916 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
917 | /* |
918 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
919 | * during Dx states where the power conservation is most |
920 | * important. During driver activity we should enable | |
ad68076e BA |
921 | * SmartSpeed, so performance is maintained. |
922 | */ | |
bc7f75fa AK |
923 | if (phy->smart_speed == e1000_smart_speed_on) { |
924 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 925 | &data); |
bc7f75fa AK |
926 | if (ret_val) |
927 | return ret_val; | |
928 | ||
929 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
930 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 931 | data); |
bc7f75fa AK |
932 | if (ret_val) |
933 | return ret_val; | |
934 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
935 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 936 | &data); |
bc7f75fa AK |
937 | if (ret_val) |
938 | return ret_val; | |
939 | ||
940 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
941 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 942 | data); |
bc7f75fa AK |
943 | if (ret_val) |
944 | return ret_val; | |
945 | } | |
946 | } | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
951 | /** | |
952 | * e1000_reset_hw_82571 - Reset hardware | |
953 | * @hw: pointer to the HW structure | |
954 | * | |
fe401674 | 955 | * This resets the hardware into a known state. |
bc7f75fa AK |
956 | **/ |
957 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
958 | { | |
1b98c2bb | 959 | u32 ctrl, ctrl_ext, icr; |
bc7f75fa | 960 | s32 ret_val; |
bc7f75fa | 961 | |
ad68076e BA |
962 | /* |
963 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
964 | * on the last TLP read/write transaction when MAC is reset. |
965 | */ | |
966 | ret_val = e1000e_disable_pcie_master(hw); | |
967 | if (ret_val) | |
3bb99fe2 | 968 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 969 | |
3bb99fe2 | 970 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
971 | ew32(IMC, 0xffffffff); |
972 | ||
973 | ew32(RCTL, 0); | |
974 | ew32(TCTL, E1000_TCTL_PSP); | |
975 | e1e_flush(); | |
976 | ||
977 | msleep(10); | |
978 | ||
ad68076e BA |
979 | /* |
980 | * Must acquire the MDIO ownership before MAC reset. | |
981 | * Ownership defaults to firmware after a reset. | |
982 | */ | |
8c81c9c3 AD |
983 | switch (hw->mac.type) { |
984 | case e1000_82573: | |
1b98c2bb BA |
985 | ret_val = e1000_get_hw_semaphore_82573(hw); |
986 | break; | |
8c81c9c3 AD |
987 | case e1000_82574: |
988 | case e1000_82583: | |
1b98c2bb | 989 | ret_val = e1000_get_hw_semaphore_82574(hw); |
8c81c9c3 AD |
990 | break; |
991 | default: | |
992 | break; | |
bc7f75fa | 993 | } |
1b98c2bb BA |
994 | if (ret_val) |
995 | e_dbg("Cannot acquire MDIO ownership\n"); | |
bc7f75fa AK |
996 | |
997 | ctrl = er32(CTRL); | |
998 | ||
3bb99fe2 | 999 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
1000 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
1001 | ||
1b98c2bb BA |
1002 | /* Must release MDIO ownership and mutex after MAC reset. */ |
1003 | switch (hw->mac.type) { | |
1004 | case e1000_82574: | |
1005 | case e1000_82583: | |
1006 | e1000_put_hw_semaphore_82574(hw); | |
1007 | break; | |
1008 | default: | |
1009 | break; | |
1010 | } | |
1011 | ||
bc7f75fa AK |
1012 | if (hw->nvm.type == e1000_nvm_flash_hw) { |
1013 | udelay(10); | |
1014 | ctrl_ext = er32(CTRL_EXT); | |
1015 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
1016 | ew32(CTRL_EXT, ctrl_ext); | |
1017 | e1e_flush(); | |
1018 | } | |
1019 | ||
1020 | ret_val = e1000e_get_auto_rd_done(hw); | |
1021 | if (ret_val) | |
1022 | /* We don't want to continue accessing MAC registers. */ | |
1023 | return ret_val; | |
1024 | ||
ad68076e BA |
1025 | /* |
1026 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
1027 | * Need to wait for Phy configuration completion before accessing |
1028 | * NVM and Phy. | |
1029 | */ | |
8c81c9c3 AD |
1030 | |
1031 | switch (hw->mac.type) { | |
1032 | case e1000_82573: | |
1033 | case e1000_82574: | |
1034 | case e1000_82583: | |
bc7f75fa | 1035 | msleep(25); |
8c81c9c3 AD |
1036 | break; |
1037 | default: | |
1038 | break; | |
1039 | } | |
bc7f75fa AK |
1040 | |
1041 | /* Clear any pending interrupt events. */ | |
1042 | ew32(IMC, 0xffffffff); | |
1043 | icr = er32(ICR); | |
1044 | ||
1aef70ef BA |
1045 | if (hw->mac.type == e1000_82571) { |
1046 | /* Install any alternate MAC address into RAR0 */ | |
1047 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1048 | if (ret_val) | |
1049 | return ret_val; | |
608f8a0d | 1050 | |
1aef70ef BA |
1051 | e1000e_set_laa_state_82571(hw, true); |
1052 | } | |
93ca1610 | 1053 | |
c9523379 | 1054 | /* Reinitialize the 82571 serdes link state machine */ |
1055 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
1056 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
1057 | ||
bc7f75fa AK |
1058 | return 0; |
1059 | } | |
1060 | ||
1061 | /** | |
1062 | * e1000_init_hw_82571 - Initialize hardware | |
1063 | * @hw: pointer to the HW structure | |
1064 | * | |
1065 | * This inits the hardware readying it for operation. | |
1066 | **/ | |
1067 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
1068 | { | |
1069 | struct e1000_mac_info *mac = &hw->mac; | |
1070 | u32 reg_data; | |
1071 | s32 ret_val; | |
a708dd88 | 1072 | u16 i, rar_count = mac->rar_entry_count; |
bc7f75fa AK |
1073 | |
1074 | e1000_initialize_hw_bits_82571(hw); | |
1075 | ||
1076 | /* Initialize identification LED */ | |
1077 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 1078 | if (ret_val) |
3bb99fe2 | 1079 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 1080 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
1081 | |
1082 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 1083 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 1084 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
1085 | |
1086 | /* Setup the receive address. */ | |
ad68076e BA |
1087 | /* |
1088 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
1089 | * 82571, we must reserve a RAR for it to work around an issue where |
1090 | * resetting one port will reload the MAC on the other port. | |
1091 | */ | |
1092 | if (e1000e_get_laa_state_82571(hw)) | |
1093 | rar_count--; | |
1094 | e1000e_init_rx_addrs(hw, rar_count); | |
1095 | ||
1096 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 1097 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
1098 | for (i = 0; i < mac->mta_reg_count; i++) |
1099 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
1100 | ||
1101 | /* Setup link and flow control */ | |
1102 | ret_val = e1000_setup_link_82571(hw); | |
1103 | ||
1104 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 1105 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
1106 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1107 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1108 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1109 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
1110 | |
1111 | /* ...for both queues. */ | |
8c81c9c3 AD |
1112 | switch (mac->type) { |
1113 | case e1000_82573: | |
a65a4a0d BA |
1114 | e1000e_enable_tx_pkt_filtering(hw); |
1115 | /* fall through */ | |
8c81c9c3 AD |
1116 | case e1000_82574: |
1117 | case e1000_82583: | |
8c81c9c3 AD |
1118 | reg_data = er32(GCR); |
1119 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
1120 | ew32(GCR, reg_data); | |
1121 | break; | |
1122 | default: | |
e9ec2c0f | 1123 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
1124 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1125 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1126 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1127 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 1128 | break; |
bc7f75fa AK |
1129 | } |
1130 | ||
ad68076e BA |
1131 | /* |
1132 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1133 | * important that we do this after we have tried to establish link |
1134 | * because the symbol error count will increment wildly if there | |
1135 | * is no link. | |
1136 | */ | |
1137 | e1000_clear_hw_cntrs_82571(hw); | |
1138 | ||
1139 | return ret_val; | |
1140 | } | |
1141 | ||
1142 | /** | |
1143 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1144 | * @hw: pointer to the HW structure | |
1145 | * | |
1146 | * Initializes required hardware-dependent bits needed for normal operation. | |
1147 | **/ | |
1148 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1149 | { | |
1150 | u32 reg; | |
1151 | ||
1152 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1153 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1154 | reg |= (1 << 22); |
e9ec2c0f | 1155 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1156 | |
1157 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1158 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1159 | reg |= (1 << 22); |
e9ec2c0f | 1160 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1161 | |
1162 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1163 | reg = er32(TARC(0)); |
bc7f75fa AK |
1164 | reg &= ~(0xF << 27); /* 30:27 */ |
1165 | switch (hw->mac.type) { | |
1166 | case e1000_82571: | |
1167 | case e1000_82572: | |
1168 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1169 | break; | |
1170 | default: | |
1171 | break; | |
1172 | } | |
e9ec2c0f | 1173 | ew32(TARC(0), reg); |
bc7f75fa AK |
1174 | |
1175 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1176 | reg = er32(TARC(1)); |
bc7f75fa AK |
1177 | switch (hw->mac.type) { |
1178 | case e1000_82571: | |
1179 | case e1000_82572: | |
1180 | reg &= ~((1 << 29) | (1 << 30)); | |
1181 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1182 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1183 | reg &= ~(1 << 28); | |
1184 | else | |
1185 | reg |= (1 << 28); | |
e9ec2c0f | 1186 | ew32(TARC(1), reg); |
bc7f75fa AK |
1187 | break; |
1188 | default: | |
1189 | break; | |
1190 | } | |
1191 | ||
1192 | /* Device Control */ | |
8c81c9c3 AD |
1193 | switch (hw->mac.type) { |
1194 | case e1000_82573: | |
1195 | case e1000_82574: | |
1196 | case e1000_82583: | |
bc7f75fa AK |
1197 | reg = er32(CTRL); |
1198 | reg &= ~(1 << 29); | |
1199 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1200 | break; |
1201 | default: | |
1202 | break; | |
bc7f75fa AK |
1203 | } |
1204 | ||
1205 | /* Extended Device Control */ | |
8c81c9c3 AD |
1206 | switch (hw->mac.type) { |
1207 | case e1000_82573: | |
1208 | case e1000_82574: | |
1209 | case e1000_82583: | |
bc7f75fa AK |
1210 | reg = er32(CTRL_EXT); |
1211 | reg &= ~(1 << 23); | |
1212 | reg |= (1 << 22); | |
1213 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1214 | break; |
1215 | default: | |
1216 | break; | |
bc7f75fa | 1217 | } |
4662e82b | 1218 | |
6ea7ae1d AD |
1219 | if (hw->mac.type == e1000_82571) { |
1220 | reg = er32(PBA_ECC); | |
1221 | reg |= E1000_PBA_ECC_CORR_EN; | |
1222 | ew32(PBA_ECC, reg); | |
1223 | } | |
5df3f0ea | 1224 | /* |
1225 | * Workaround for hardware errata. | |
1226 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1227 | */ | |
1228 | ||
1229 | if ((hw->mac.type == e1000_82571) || | |
1230 | (hw->mac.type == e1000_82572)) { | |
1231 | reg = er32(CTRL_EXT); | |
1232 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1233 | ew32(CTRL_EXT, reg); | |
1234 | } | |
1235 | ||
6ea7ae1d | 1236 | |
78272bba | 1237 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1238 | switch (hw->mac.type) { |
1239 | case e1000_82574: | |
1240 | case e1000_82583: | |
4662e82b BA |
1241 | reg = er32(GCR); |
1242 | reg |= (1 << 22); | |
1243 | ew32(GCR, reg); | |
78272bba | 1244 | |
84efb7b9 BA |
1245 | /* |
1246 | * Workaround for hardware errata. | |
1247 | * apply workaround for hardware errata documented in errata | |
1248 | * docs Fixes issue where some error prone or unreliable PCIe | |
1249 | * completions are occurring, particularly with ASPM enabled. | |
1250 | * Without fix, issue can cause tx timeouts. | |
1251 | */ | |
78272bba JB |
1252 | reg = er32(GCR2); |
1253 | reg |= 1; | |
1254 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1255 | break; |
1256 | default: | |
1257 | break; | |
4662e82b | 1258 | } |
bc7f75fa AK |
1259 | } |
1260 | ||
1261 | /** | |
caaddaf8 | 1262 | * e1000_clear_vfta_82571 - Clear VLAN filter table |
bc7f75fa AK |
1263 | * @hw: pointer to the HW structure |
1264 | * | |
1265 | * Clears the register array which contains the VLAN filter table by | |
1266 | * setting all the values to 0. | |
1267 | **/ | |
caaddaf8 | 1268 | static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
bc7f75fa AK |
1269 | { |
1270 | u32 offset; | |
1271 | u32 vfta_value = 0; | |
1272 | u32 vfta_offset = 0; | |
1273 | u32 vfta_bit_in_reg = 0; | |
1274 | ||
8c81c9c3 AD |
1275 | switch (hw->mac.type) { |
1276 | case e1000_82573: | |
1277 | case e1000_82574: | |
1278 | case e1000_82583: | |
bc7f75fa | 1279 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1280 | /* |
1281 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1282 | * a single VLAN ID. The following operations |
1283 | * determine which 32b entry (i.e. offset) into the | |
1284 | * array we want to set the VLAN ID (i.e. bit) of | |
1285 | * the manageability unit. | |
1286 | */ | |
1287 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1288 | E1000_VFTA_ENTRY_SHIFT) & | |
1289 | E1000_VFTA_ENTRY_MASK; | |
1290 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1291 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1292 | } | |
8c81c9c3 AD |
1293 | break; |
1294 | default: | |
1295 | break; | |
bc7f75fa AK |
1296 | } |
1297 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1298 | /* |
1299 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1300 | * manageability VLAN ID, then clear all bits except that of |
1301 | * the manageability unit. | |
1302 | */ | |
1303 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1304 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1305 | e1e_flush(); | |
1306 | } | |
1307 | } | |
1308 | ||
4662e82b BA |
1309 | /** |
1310 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1311 | * @hw: pointer to the HW structure | |
1312 | * | |
1313 | * Reads the NVM Initialization Control Word 2 and returns true | |
1314 | * (>0) if any manageability is enabled, else false (0). | |
1315 | **/ | |
1316 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1317 | { | |
1318 | u16 data; | |
1319 | ||
1320 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1321 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1322 | } | |
1323 | ||
1324 | /** | |
1325 | * e1000_led_on_82574 - Turn LED on | |
1326 | * @hw: pointer to the HW structure | |
1327 | * | |
1328 | * Turn LED on. | |
1329 | **/ | |
1330 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1331 | { | |
1332 | u32 ctrl; | |
1333 | u32 i; | |
1334 | ||
1335 | ctrl = hw->mac.ledctl_mode2; | |
1336 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1337 | /* | |
1338 | * If no link, then turn LED on by setting the invert bit | |
1339 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1340 | */ | |
1341 | for (i = 0; i < 4; i++) | |
1342 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1343 | E1000_LEDCTL_MODE_LED_ON) | |
1344 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1345 | } | |
1346 | ew32(LEDCTL, ctrl); | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | ||
ff10e13c CW |
1351 | /** |
1352 | * e1000_check_phy_82574 - check 82574 phy hung state | |
1353 | * @hw: pointer to the HW structure | |
1354 | * | |
1355 | * Returns whether phy is hung or not | |
1356 | **/ | |
1357 | bool e1000_check_phy_82574(struct e1000_hw *hw) | |
1358 | { | |
1359 | u16 status_1kbt = 0; | |
1360 | u16 receive_errors = 0; | |
1361 | bool phy_hung = false; | |
1362 | s32 ret_val = 0; | |
1363 | ||
1364 | /* | |
1365 | * Read PHY Receive Error counter first, if its is max - all F's then | |
1366 | * read the Base1000T status register If both are max then PHY is hung. | |
1367 | */ | |
1368 | ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); | |
1369 | ||
1370 | if (ret_val) | |
1371 | goto out; | |
1372 | if (receive_errors == E1000_RECEIVE_ERROR_MAX) { | |
1373 | ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); | |
1374 | if (ret_val) | |
1375 | goto out; | |
1376 | if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == | |
1377 | E1000_IDLE_ERROR_COUNT_MASK) | |
1378 | phy_hung = true; | |
1379 | } | |
1380 | out: | |
1381 | return phy_hung; | |
1382 | } | |
1383 | ||
bc7f75fa AK |
1384 | /** |
1385 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1386 | * @hw: pointer to the HW structure | |
1387 | * | |
1388 | * Determines which flow control settings to use, then configures flow | |
1389 | * control. Calls the appropriate media-specific link configuration | |
1390 | * function. Assuming the adapter has a valid link partner, a valid link | |
1391 | * should be established. Assumes the hardware has previously been reset | |
1392 | * and the transmitter and receiver are not enabled. | |
1393 | **/ | |
1394 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1395 | { | |
ad68076e BA |
1396 | /* |
1397 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1398 | * the default flow control setting, so we explicitly |
1399 | * set it to full. | |
1400 | */ | |
8c81c9c3 AD |
1401 | switch (hw->mac.type) { |
1402 | case e1000_82573: | |
1403 | case e1000_82574: | |
1404 | case e1000_82583: | |
1405 | if (hw->fc.requested_mode == e1000_fc_default) | |
1406 | hw->fc.requested_mode = e1000_fc_full; | |
1407 | break; | |
1408 | default: | |
1409 | break; | |
1410 | } | |
bc7f75fa AK |
1411 | |
1412 | return e1000e_setup_link(hw); | |
1413 | } | |
1414 | ||
1415 | /** | |
1416 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1417 | * @hw: pointer to the HW structure | |
1418 | * | |
1419 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1420 | * for link, once link is established calls to configure collision distance | |
1421 | * and flow control are called. | |
1422 | **/ | |
1423 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1424 | { | |
1425 | u32 ctrl; | |
bc7f75fa AK |
1426 | s32 ret_val; |
1427 | ||
1428 | ctrl = er32(CTRL); | |
1429 | ctrl |= E1000_CTRL_SLU; | |
1430 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1431 | ew32(CTRL, ctrl); | |
1432 | ||
1433 | switch (hw->phy.type) { | |
1434 | case e1000_phy_m88: | |
4662e82b | 1435 | case e1000_phy_bm: |
bc7f75fa AK |
1436 | ret_val = e1000e_copper_link_setup_m88(hw); |
1437 | break; | |
1438 | case e1000_phy_igp_2: | |
1439 | ret_val = e1000e_copper_link_setup_igp(hw); | |
bc7f75fa AK |
1440 | break; |
1441 | default: | |
1442 | return -E1000_ERR_PHY; | |
1443 | break; | |
1444 | } | |
1445 | ||
1446 | if (ret_val) | |
1447 | return ret_val; | |
1448 | ||
1449 | ret_val = e1000e_setup_copper_link(hw); | |
1450 | ||
1451 | return ret_val; | |
1452 | } | |
1453 | ||
1454 | /** | |
1455 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1456 | * @hw: pointer to the HW structure | |
1457 | * | |
1458 | * Configures collision distance and flow control for fiber and serdes links. | |
1459 | * Upon successful setup, poll for link. | |
1460 | **/ | |
1461 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1462 | { | |
1463 | switch (hw->mac.type) { | |
1464 | case e1000_82571: | |
1465 | case e1000_82572: | |
ad68076e BA |
1466 | /* |
1467 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1468 | * of reset to take the adapter out of that mode. So we |
1469 | * have to explicitly take the adapter out of loopback | |
489815ce | 1470 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1471 | * if another tool failed to take it out of loopback mode. |
1472 | */ | |
ad68076e | 1473 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1474 | break; |
1475 | default: | |
1476 | break; | |
1477 | } | |
1478 | ||
1479 | return e1000e_setup_fiber_serdes_link(hw); | |
1480 | } | |
1481 | ||
c9523379 | 1482 | /** |
1483 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1484 | * @hw: pointer to the HW structure | |
1485 | * | |
1a40d5c1 BA |
1486 | * Reports the link state as up or down. |
1487 | * | |
1488 | * If autonegotiation is supported by the link partner, the link state is | |
1489 | * determined by the result of autonegotiation. This is the most likely case. | |
1490 | * If autonegotiation is not supported by the link partner, and the link | |
1491 | * has a valid signal, force the link up. | |
1492 | * | |
1493 | * The link state is represented internally here by 4 states: | |
1494 | * | |
1495 | * 1) down | |
1496 | * 2) autoneg_progress | |
3ad2f3fb | 1497 | * 3) autoneg_complete (the link successfully autonegotiated) |
1a40d5c1 BA |
1498 | * 4) forced_up (the link has been forced up, it did not autonegotiate) |
1499 | * | |
c9523379 | 1500 | **/ |
f6370117 | 1501 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1502 | { |
1503 | struct e1000_mac_info *mac = &hw->mac; | |
1504 | u32 rxcw; | |
1505 | u32 ctrl; | |
1506 | u32 status; | |
d9c76f99 BA |
1507 | u32 txcw; |
1508 | u32 i; | |
c9523379 | 1509 | s32 ret_val = 0; |
1510 | ||
1511 | ctrl = er32(CTRL); | |
1512 | status = er32(STATUS); | |
1513 | rxcw = er32(RXCW); | |
1514 | ||
1515 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1516 | ||
1517 | /* Receiver is synchronized with no invalid bits. */ | |
1518 | switch (mac->serdes_link_state) { | |
1519 | case e1000_serdes_link_autoneg_complete: | |
1520 | if (!(status & E1000_STATUS_LU)) { | |
1521 | /* | |
1522 | * We have lost link, retry autoneg before | |
1523 | * reporting link failure | |
1524 | */ | |
1525 | mac->serdes_link_state = | |
1526 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1527 | mac->serdes_has_link = false; |
3bb99fe2 | 1528 | e_dbg("AN_UP -> AN_PROG\n"); |
a82a14f4 BA |
1529 | } else { |
1530 | mac->serdes_has_link = true; | |
c9523379 | 1531 | } |
a82a14f4 | 1532 | break; |
c9523379 | 1533 | |
1534 | case e1000_serdes_link_forced_up: | |
1535 | /* | |
1536 | * If we are receiving /C/ ordered sets, re-enable | |
1537 | * auto-negotiation in the TXCW register and disable | |
1538 | * forced link in the Device Control register in an | |
1539 | * attempt to auto-negotiate with our link partner. | |
d478eb44 BA |
1540 | * If the partner code word is null, stop forcing |
1541 | * and restart auto negotiation. | |
c9523379 | 1542 | */ |
d478eb44 | 1543 | if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { |
c9523379 | 1544 | /* Enable autoneg, and unforce link up */ |
1545 | ew32(TXCW, mac->txcw); | |
1a40d5c1 | 1546 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1547 | mac->serdes_link_state = |
1548 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1549 | mac->serdes_has_link = false; |
3bb99fe2 | 1550 | e_dbg("FORCED_UP -> AN_PROG\n"); |
a82a14f4 BA |
1551 | } else { |
1552 | mac->serdes_has_link = true; | |
c9523379 | 1553 | } |
1554 | break; | |
1555 | ||
1556 | case e1000_serdes_link_autoneg_progress: | |
1a40d5c1 BA |
1557 | if (rxcw & E1000_RXCW_C) { |
1558 | /* | |
1559 | * We received /C/ ordered sets, meaning the | |
1560 | * link partner has autonegotiated, and we can | |
1561 | * trust the Link Up (LU) status bit. | |
1562 | */ | |
1563 | if (status & E1000_STATUS_LU) { | |
1564 | mac->serdes_link_state = | |
1565 | e1000_serdes_link_autoneg_complete; | |
1566 | e_dbg("AN_PROG -> AN_UP\n"); | |
1567 | mac->serdes_has_link = true; | |
1568 | } else { | |
1569 | /* Autoneg completed, but failed. */ | |
1570 | mac->serdes_link_state = | |
1571 | e1000_serdes_link_down; | |
1572 | e_dbg("AN_PROG -> DOWN\n"); | |
1573 | } | |
c9523379 | 1574 | } else { |
1575 | /* | |
1a40d5c1 BA |
1576 | * The link partner did not autoneg. |
1577 | * Force link up and full duplex, and change | |
1578 | * state to forced. | |
c9523379 | 1579 | */ |
1a40d5c1 | 1580 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
c9523379 | 1581 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
1582 | ew32(CTRL, ctrl); | |
1583 | ||
1584 | /* Configure Flow Control after link up. */ | |
1a40d5c1 | 1585 | ret_val = e1000e_config_fc_after_link_up(hw); |
c9523379 | 1586 | if (ret_val) { |
3bb99fe2 | 1587 | e_dbg("Error config flow control\n"); |
c9523379 | 1588 | break; |
1589 | } | |
1590 | mac->serdes_link_state = | |
1591 | e1000_serdes_link_forced_up; | |
1a40d5c1 | 1592 | mac->serdes_has_link = true; |
3bb99fe2 | 1593 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1594 | } |
c9523379 | 1595 | break; |
1596 | ||
1597 | case e1000_serdes_link_down: | |
1598 | default: | |
1a40d5c1 BA |
1599 | /* |
1600 | * The link was down but the receiver has now gained | |
c9523379 | 1601 | * valid sync, so lets see if we can bring the link |
1a40d5c1 BA |
1602 | * up. |
1603 | */ | |
c9523379 | 1604 | ew32(TXCW, mac->txcw); |
1a40d5c1 | 1605 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1606 | mac->serdes_link_state = |
1607 | e1000_serdes_link_autoneg_progress; | |
a82a14f4 | 1608 | mac->serdes_has_link = false; |
3bb99fe2 | 1609 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1610 | break; |
1611 | } | |
1612 | } else { | |
1613 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1614 | mac->serdes_has_link = false; | |
1615 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1616 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1617 | } else { |
1618 | /* | |
d9c76f99 BA |
1619 | * Check several times, if Sync and Config |
1620 | * both are consistently 1 then simply ignore | |
1621 | * the Invalid bit and restart Autoneg | |
c9523379 | 1622 | */ |
d9c76f99 BA |
1623 | for (i = 0; i < AN_RETRY_COUNT; i++) { |
1624 | udelay(10); | |
1625 | rxcw = er32(RXCW); | |
1626 | if ((rxcw & E1000_RXCW_IV) && | |
1627 | !((rxcw & E1000_RXCW_SYNCH) && | |
1628 | (rxcw & E1000_RXCW_C))) { | |
1629 | mac->serdes_has_link = false; | |
1630 | mac->serdes_link_state = | |
1631 | e1000_serdes_link_down; | |
1632 | e_dbg("ANYSTATE -> DOWN\n"); | |
1633 | break; | |
1634 | } | |
1635 | } | |
1636 | ||
1637 | if (i == AN_RETRY_COUNT) { | |
1638 | txcw = er32(TXCW); | |
1639 | txcw |= E1000_TXCW_ANE; | |
1640 | ew32(TXCW, txcw); | |
1641 | mac->serdes_link_state = | |
1642 | e1000_serdes_link_autoneg_progress; | |
c9523379 | 1643 | mac->serdes_has_link = false; |
d9c76f99 | 1644 | e_dbg("ANYSTATE -> AN_PROG\n"); |
c9523379 | 1645 | } |
1646 | } | |
1647 | } | |
1648 | ||
1649 | return ret_val; | |
1650 | } | |
1651 | ||
bc7f75fa AK |
1652 | /** |
1653 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1654 | * @hw: pointer to the HW structure | |
1655 | * @data: pointer to the NVM (EEPROM) | |
1656 | * | |
1657 | * Read the EEPROM for the current default LED configuration. If the | |
1658 | * LED configuration is not valid, set to a valid LED configuration. | |
1659 | **/ | |
1660 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1661 | { | |
1662 | s32 ret_val; | |
1663 | ||
1664 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1665 | if (ret_val) { | |
3bb99fe2 | 1666 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1667 | return ret_val; |
1668 | } | |
1669 | ||
8c81c9c3 AD |
1670 | switch (hw->mac.type) { |
1671 | case e1000_82573: | |
1672 | case e1000_82574: | |
1673 | case e1000_82583: | |
1674 | if (*data == ID_LED_RESERVED_F746) | |
1675 | *data = ID_LED_DEFAULT_82573; | |
1676 | break; | |
1677 | default: | |
1678 | if (*data == ID_LED_RESERVED_0000 || | |
1679 | *data == ID_LED_RESERVED_FFFF) | |
1680 | *data = ID_LED_DEFAULT; | |
1681 | break; | |
1682 | } | |
bc7f75fa AK |
1683 | |
1684 | return 0; | |
1685 | } | |
1686 | ||
1687 | /** | |
1688 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1689 | * @hw: pointer to the HW structure | |
1690 | * | |
489815ce | 1691 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1692 | **/ |
1693 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1694 | { | |
1695 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1696 | return false; |
bc7f75fa AK |
1697 | |
1698 | return hw->dev_spec.e82571.laa_is_present; | |
1699 | } | |
1700 | ||
1701 | /** | |
1702 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1703 | * @hw: pointer to the HW structure | |
1704 | * @state: enable/disable locally administered address | |
1705 | * | |
5ff5b664 | 1706 | * Enable/Disable the current locally administered address state. |
bc7f75fa AK |
1707 | **/ |
1708 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1709 | { | |
1710 | if (hw->mac.type != e1000_82571) | |
1711 | return; | |
1712 | ||
1713 | hw->dev_spec.e82571.laa_is_present = state; | |
1714 | ||
1715 | /* If workaround is activated... */ | |
1716 | if (state) | |
ad68076e BA |
1717 | /* |
1718 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1719 | * between the time RAR[0] gets clobbered and the time it |
1720 | * gets fixed, the actual LAA is in one of the RARs and no | |
1721 | * incoming packets directed to this port are dropped. | |
1722 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1723 | */ | |
1724 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1725 | } | |
1726 | ||
1727 | /** | |
1728 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1729 | * @hw: pointer to the HW structure | |
1730 | * | |
1731 | * Verifies that the EEPROM has completed the update. After updating the | |
1732 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1733 | * the checksum fix is not implemented, we need to set the bit and update | |
1734 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1735 | * we need to return bad checksum. | |
1736 | **/ | |
1737 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1738 | { | |
1739 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1740 | s32 ret_val; | |
1741 | u16 data; | |
1742 | ||
1743 | if (nvm->type != e1000_nvm_flash_hw) | |
1744 | return 0; | |
1745 | ||
ad68076e BA |
1746 | /* |
1747 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1748 | * 10h-12h. Checksum may need to be fixed. |
1749 | */ | |
1750 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1751 | if (ret_val) | |
1752 | return ret_val; | |
1753 | ||
1754 | if (!(data & 0x10)) { | |
ad68076e BA |
1755 | /* |
1756 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1757 | * when the checksum has already been fixed. If |
1758 | * the checksum is still wrong and this bit is a | |
1759 | * 1, we need to return bad checksum. Otherwise, | |
1760 | * we need to set this bit to a 1 and update the | |
1761 | * checksum. | |
1762 | */ | |
1763 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1764 | if (ret_val) | |
1765 | return ret_val; | |
1766 | ||
1767 | if (!(data & 0x8000)) { | |
1768 | data |= 0x8000; | |
1769 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1770 | if (ret_val) | |
1771 | return ret_val; | |
1772 | ret_val = e1000e_update_nvm_checksum(hw); | |
1773 | } | |
1774 | } | |
1775 | ||
1776 | return 0; | |
1777 | } | |
1778 | ||
608f8a0d BA |
1779 | /** |
1780 | * e1000_read_mac_addr_82571 - Read device MAC address | |
1781 | * @hw: pointer to the HW structure | |
1782 | **/ | |
1783 | static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) | |
1784 | { | |
1785 | s32 ret_val = 0; | |
1786 | ||
1aef70ef BA |
1787 | if (hw->mac.type == e1000_82571) { |
1788 | /* | |
1789 | * If there's an alternate MAC address place it in RAR0 | |
1790 | * so that it will override the Si installed default perm | |
1791 | * address. | |
1792 | */ | |
1793 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1794 | if (ret_val) | |
1795 | goto out; | |
1796 | } | |
608f8a0d BA |
1797 | |
1798 | ret_val = e1000_read_mac_addr_generic(hw); | |
1799 | ||
1800 | out: | |
1801 | return ret_val; | |
1802 | } | |
1803 | ||
17f208de BA |
1804 | /** |
1805 | * e1000_power_down_phy_copper_82571 - Remove link during PHY power down | |
1806 | * @hw: pointer to the HW structure | |
1807 | * | |
1808 | * In the case of a PHY power down to save power, or to turn off link during a | |
1809 | * driver unload, or wake on lan is not enabled, remove the link. | |
1810 | **/ | |
1811 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) | |
1812 | { | |
1813 | struct e1000_phy_info *phy = &hw->phy; | |
1814 | struct e1000_mac_info *mac = &hw->mac; | |
1815 | ||
1816 | if (!(phy->ops.check_reset_block)) | |
1817 | return; | |
1818 | ||
1819 | /* If the management interface is not enabled, then power down */ | |
1820 | if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) | |
1821 | e1000_power_down_phy_copper(hw); | |
17f208de BA |
1822 | } |
1823 | ||
bc7f75fa AK |
1824 | /** |
1825 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1826 | * @hw: pointer to the HW structure | |
1827 | * | |
1828 | * Clears the hardware counters by reading the counter registers. | |
1829 | **/ | |
1830 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1831 | { | |
bc7f75fa AK |
1832 | e1000e_clear_hw_cntrs_base(hw); |
1833 | ||
99673d9b BA |
1834 | er32(PRC64); |
1835 | er32(PRC127); | |
1836 | er32(PRC255); | |
1837 | er32(PRC511); | |
1838 | er32(PRC1023); | |
1839 | er32(PRC1522); | |
1840 | er32(PTC64); | |
1841 | er32(PTC127); | |
1842 | er32(PTC255); | |
1843 | er32(PTC511); | |
1844 | er32(PTC1023); | |
1845 | er32(PTC1522); | |
1846 | ||
1847 | er32(ALGNERRC); | |
1848 | er32(RXERRC); | |
1849 | er32(TNCRS); | |
1850 | er32(CEXTERR); | |
1851 | er32(TSCTC); | |
1852 | er32(TSCTFC); | |
1853 | ||
1854 | er32(MGTPRC); | |
1855 | er32(MGTPDC); | |
1856 | er32(MGTPTC); | |
1857 | ||
1858 | er32(IAC); | |
1859 | er32(ICRXOC); | |
1860 | ||
1861 | er32(ICRXPTC); | |
1862 | er32(ICRXATC); | |
1863 | er32(ICTXPTC); | |
1864 | er32(ICTXATC); | |
1865 | er32(ICTXQEC); | |
1866 | er32(ICTXQMTC); | |
1867 | er32(ICRXDMTC); | |
bc7f75fa AK |
1868 | } |
1869 | ||
1870 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1871 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1872 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1873 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1874 | .cleanup_led = e1000e_cleanup_led_generic, |
1875 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1876 | .get_bus_info = e1000e_get_bus_info_pcie, | |
f4d2dd4c | 1877 | .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
bc7f75fa | 1878 | /* .get_link_up_info: media type dependent */ |
4662e82b | 1879 | /* .led_on: mac type dependent */ |
bc7f75fa | 1880 | .led_off = e1000e_led_off_generic, |
ab8932f3 | 1881 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1882 | .write_vfta = e1000_write_vfta_generic, |
1883 | .clear_vfta = e1000_clear_vfta_82571, | |
bc7f75fa AK |
1884 | .reset_hw = e1000_reset_hw_82571, |
1885 | .init_hw = e1000_init_hw_82571, | |
1886 | .setup_link = e1000_setup_link_82571, | |
1887 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1888 | .setup_led = e1000e_setup_led_generic, |
608f8a0d | 1889 | .read_mac_addr = e1000_read_mac_addr_82571, |
bc7f75fa AK |
1890 | }; |
1891 | ||
1892 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
94d8186a | 1893 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1894 | .check_polarity = e1000_check_polarity_igp, |
bc7f75fa | 1895 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1896 | .commit = NULL, |
bc7f75fa AK |
1897 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1898 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1899 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1900 | .get_info = e1000e_get_phy_info_igp, |
1901 | .read_reg = e1000e_read_phy_reg_igp, | |
1902 | .release = e1000_put_hw_semaphore_82571, | |
1903 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1904 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1905 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1906 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1907 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1908 | }; |
1909 | ||
1910 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
94d8186a | 1911 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1912 | .check_polarity = e1000_check_polarity_m88, |
bc7f75fa | 1913 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1914 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1915 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1916 | .get_cfg_done = e1000e_get_cfg_done, | |
1917 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1918 | .get_info = e1000e_get_phy_info_m88, |
1919 | .read_reg = e1000e_read_phy_reg_m88, | |
1920 | .release = e1000_put_hw_semaphore_82571, | |
1921 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1922 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1923 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1924 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1925 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1926 | }; |
1927 | ||
4662e82b | 1928 | static struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1929 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1930 | .check_polarity = e1000_check_polarity_m88, |
4662e82b | 1931 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1932 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1933 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1934 | .get_cfg_done = e1000e_get_cfg_done, | |
1935 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1936 | .get_info = e1000e_get_phy_info_m88, |
1937 | .read_reg = e1000e_read_phy_reg_bm2, | |
1938 | .release = e1000_put_hw_semaphore_82571, | |
1939 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1940 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1941 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1942 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1943 | .cfg_on_link_up = NULL, |
4662e82b BA |
1944 | }; |
1945 | ||
bc7f75fa | 1946 | static struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1947 | .acquire = e1000_acquire_nvm_82571, |
1948 | .read = e1000e_read_nvm_eerd, | |
1949 | .release = e1000_release_nvm_82571, | |
1950 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1951 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1952 | .validate = e1000_validate_nvm_checksum_82571, |
1953 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1954 | }; |
1955 | ||
1956 | struct e1000_info e1000_82571_info = { | |
1957 | .mac = e1000_82571, | |
1958 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1959 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1960 | | FLAG_HAS_WOL |
1961 | | FLAG_APME_IN_CTRL3 | |
1962 | | FLAG_RX_CSUM_ENABLED | |
1963 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1964 | | FLAG_HAS_SMART_POWER_DOWN |
1965 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1966 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1967 | | FLAG_APME_CHECK_PORT_B, | |
3a3b7586 JB |
1968 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
1969 | | FLAG2_DMA_BURST, | |
bc7f75fa | 1970 | .pba = 38, |
2adc55c9 | 1971 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1972 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1973 | .mac_ops = &e82571_mac_ops, |
1974 | .phy_ops = &e82_phy_ops_igp, | |
1975 | .nvm_ops = &e82571_nvm_ops, | |
1976 | }; | |
1977 | ||
1978 | struct e1000_info e1000_82572_info = { | |
1979 | .mac = e1000_82572, | |
1980 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1981 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1982 | | FLAG_HAS_WOL |
1983 | | FLAG_APME_IN_CTRL3 | |
1984 | | FLAG_RX_CSUM_ENABLED | |
1985 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa | 1986 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
3a3b7586 JB |
1987 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
1988 | | FLAG2_DMA_BURST, | |
bc7f75fa | 1989 | .pba = 38, |
2adc55c9 | 1990 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1991 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1992 | .mac_ops = &e82571_mac_ops, |
1993 | .phy_ops = &e82_phy_ops_igp, | |
1994 | .nvm_ops = &e82571_nvm_ops, | |
1995 | }; | |
1996 | ||
1997 | struct e1000_info e1000_82573_info = { | |
1998 | .mac = e1000_82573, | |
1999 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
bc7f75fa AK |
2000 | | FLAG_HAS_WOL |
2001 | | FLAG_APME_IN_CTRL3 | |
2002 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
2003 | | FLAG_HAS_SMART_POWER_DOWN |
2004 | | FLAG_HAS_AMT | |
bc7f75fa | 2005 | | FLAG_HAS_SWSM_ON_LOAD, |
19833b5d | 2006 | .flags2 = FLAG2_DISABLE_ASPM_L1, |
bc7f75fa | 2007 | .pba = 20, |
2adc55c9 | 2008 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 2009 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
2010 | .mac_ops = &e82571_mac_ops, |
2011 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 2012 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
2013 | }; |
2014 | ||
4662e82b BA |
2015 | struct e1000_info e1000_82574_info = { |
2016 | .mac = e1000_82574, | |
2017 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2018 | | FLAG_HAS_MSIX | |
2019 | | FLAG_HAS_JUMBO_FRAMES | |
2020 | | FLAG_HAS_WOL | |
2021 | | FLAG_APME_IN_CTRL3 | |
2022 | | FLAG_RX_CSUM_ENABLED | |
2023 | | FLAG_HAS_SMART_POWER_DOWN | |
2024 | | FLAG_HAS_AMT | |
2025 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
ff10e13c | 2026 | .flags2 = FLAG2_CHECK_PHY_HANG, |
ed5c2b0b | 2027 | .pba = 32, |
a825e00c | 2028 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
2029 | .get_variants = e1000_get_variants_82571, |
2030 | .mac_ops = &e82571_mac_ops, | |
2031 | .phy_ops = &e82_phy_ops_bm, | |
2032 | .nvm_ops = &e82571_nvm_ops, | |
2033 | }; | |
2034 | ||
8c81c9c3 AD |
2035 | struct e1000_info e1000_82583_info = { |
2036 | .mac = e1000_82583, | |
2037 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2038 | | FLAG_HAS_WOL | |
2039 | | FLAG_APME_IN_CTRL3 | |
2040 | | FLAG_RX_CSUM_ENABLED | |
2041 | | FLAG_HAS_SMART_POWER_DOWN | |
2042 | | FLAG_HAS_AMT | |
2043 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
ed5c2b0b | 2044 | .pba = 32, |
a825e00c | 2045 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
8c81c9c3 AD |
2046 | .get_variants = e1000_get_variants_82571, |
2047 | .mac_ops = &e82571_mac_ops, | |
2048 | .phy_ops = &e82_phy_ops_bm, | |
2049 | .nvm_ops = &e82571_nvm_ops, | |
2050 | }; | |
2051 |