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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
bc7f75fa AK |
43 | */ |
44 | ||
45 | #include <linux/netdevice.h> | |
46 | #include <linux/delay.h> | |
47 | #include <linux/pci.h> | |
48 | ||
49 | #include "e1000.h" | |
50 | ||
51 | #define ID_LED_RESERVED_F746 0xF746 | |
52 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
53 | (ID_LED_OFF1_ON2 << 8) | \ | |
54 | (ID_LED_DEF1_DEF2 << 4) | \ | |
55 | (ID_LED_DEF1_DEF2)) | |
56 | ||
57 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
58 | ||
4662e82b BA |
59 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
60 | ||
bc7f75fa AK |
61 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
62 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
63 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
64 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
65 | u16 words, u16 *data); | |
66 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
67 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
68 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
69 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
4662e82b BA |
70 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
71 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
bc7f75fa AK |
72 | |
73 | /** | |
74 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
75 | * @hw: pointer to the HW structure | |
76 | * | |
77 | * This is a function pointer entry point called by the api module. | |
78 | **/ | |
79 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
80 | { | |
81 | struct e1000_phy_info *phy = &hw->phy; | |
82 | s32 ret_val; | |
83 | ||
318a94d6 | 84 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
85 | phy->type = e1000_phy_none; |
86 | return 0; | |
87 | } | |
88 | ||
89 | phy->addr = 1; | |
90 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
91 | phy->reset_delay_us = 100; | |
92 | ||
93 | switch (hw->mac.type) { | |
94 | case e1000_82571: | |
95 | case e1000_82572: | |
96 | phy->type = e1000_phy_igp_2; | |
97 | break; | |
98 | case e1000_82573: | |
99 | phy->type = e1000_phy_m88; | |
100 | break; | |
4662e82b BA |
101 | case e1000_82574: |
102 | phy->type = e1000_phy_bm; | |
103 | break; | |
bc7f75fa AK |
104 | default: |
105 | return -E1000_ERR_PHY; | |
106 | break; | |
107 | } | |
108 | ||
109 | /* This can only be done after all function pointers are setup. */ | |
110 | ret_val = e1000_get_phy_id_82571(hw); | |
111 | ||
112 | /* Verify phy id */ | |
113 | switch (hw->mac.type) { | |
114 | case e1000_82571: | |
115 | case e1000_82572: | |
116 | if (phy->id != IGP01E1000_I_PHY_ID) | |
117 | return -E1000_ERR_PHY; | |
118 | break; | |
119 | case e1000_82573: | |
120 | if (phy->id != M88E1111_I_PHY_ID) | |
121 | return -E1000_ERR_PHY; | |
122 | break; | |
4662e82b BA |
123 | case e1000_82574: |
124 | if (phy->id != BME1000_E_PHY_ID_R2) | |
125 | return -E1000_ERR_PHY; | |
126 | break; | |
bc7f75fa AK |
127 | default: |
128 | return -E1000_ERR_PHY; | |
129 | break; | |
130 | } | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | /** | |
136 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
137 | * @hw: pointer to the HW structure | |
138 | * | |
139 | * This is a function pointer entry point called by the api module. | |
140 | **/ | |
141 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
142 | { | |
143 | struct e1000_nvm_info *nvm = &hw->nvm; | |
144 | u32 eecd = er32(EECD); | |
145 | u16 size; | |
146 | ||
147 | nvm->opcode_bits = 8; | |
148 | nvm->delay_usec = 1; | |
149 | switch (nvm->override) { | |
150 | case e1000_nvm_override_spi_large: | |
151 | nvm->page_size = 32; | |
152 | nvm->address_bits = 16; | |
153 | break; | |
154 | case e1000_nvm_override_spi_small: | |
155 | nvm->page_size = 8; | |
156 | nvm->address_bits = 8; | |
157 | break; | |
158 | default: | |
159 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
160 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
161 | break; | |
162 | } | |
163 | ||
164 | switch (hw->mac.type) { | |
165 | case e1000_82573: | |
4662e82b | 166 | case e1000_82574: |
bc7f75fa AK |
167 | if (((eecd >> 15) & 0x3) == 0x3) { |
168 | nvm->type = e1000_nvm_flash_hw; | |
169 | nvm->word_size = 2048; | |
ad68076e BA |
170 | /* |
171 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
172 | * to Flash update issue. |
173 | */ | |
174 | eecd &= ~E1000_EECD_AUPDEN; | |
175 | ew32(EECD, eecd); | |
176 | break; | |
177 | } | |
178 | /* Fall Through */ | |
179 | default: | |
ad68076e | 180 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
181 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
182 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
183 | /* |
184 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
185 | * for setting word_size. |
186 | */ | |
187 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
188 | |
189 | /* EEPROM access above 16k is unsupported */ | |
190 | if (size > 14) | |
191 | size = 14; | |
bc7f75fa AK |
192 | nvm->word_size = 1 << size; |
193 | break; | |
194 | } | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | /** | |
200 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
201 | * @hw: pointer to the HW structure | |
202 | * | |
203 | * This is a function pointer entry point called by the api module. | |
204 | **/ | |
205 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
206 | { | |
207 | struct e1000_hw *hw = &adapter->hw; | |
208 | struct e1000_mac_info *mac = &hw->mac; | |
209 | struct e1000_mac_operations *func = &mac->ops; | |
210 | ||
211 | /* Set media type */ | |
212 | switch (adapter->pdev->device) { | |
213 | case E1000_DEV_ID_82571EB_FIBER: | |
214 | case E1000_DEV_ID_82572EI_FIBER: | |
215 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 216 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
217 | break; |
218 | case E1000_DEV_ID_82571EB_SERDES: | |
219 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
220 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
221 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 222 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
223 | break; |
224 | default: | |
318a94d6 | 225 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
226 | break; |
227 | } | |
228 | ||
229 | /* Set mta register count */ | |
230 | mac->mta_reg_count = 128; | |
231 | /* Set rar entry count */ | |
232 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
233 | /* Set if manageability features are enabled. */ | |
ad68076e | 234 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; |
bc7f75fa AK |
235 | |
236 | /* check for link */ | |
318a94d6 | 237 | switch (hw->phy.media_type) { |
bc7f75fa AK |
238 | case e1000_media_type_copper: |
239 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
240 | func->check_for_link = e1000e_check_for_copper_link; | |
241 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
242 | break; | |
243 | case e1000_media_type_fiber: | |
ad68076e BA |
244 | func->setup_physical_interface = |
245 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 246 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
247 | func->get_link_up_info = |
248 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
249 | break; |
250 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
251 | func->setup_physical_interface = |
252 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 253 | func->check_for_link = e1000e_check_for_serdes_link; |
ad68076e BA |
254 | func->get_link_up_info = |
255 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
256 | break; |
257 | default: | |
258 | return -E1000_ERR_CONFIG; | |
259 | break; | |
260 | } | |
261 | ||
4662e82b BA |
262 | switch (hw->mac.type) { |
263 | case e1000_82574: | |
264 | func->check_mng_mode = e1000_check_mng_mode_82574; | |
265 | func->led_on = e1000_led_on_82574; | |
266 | break; | |
267 | default: | |
268 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
269 | func->led_on = e1000e_led_on_generic; | |
270 | break; | |
271 | } | |
272 | ||
bc7f75fa AK |
273 | return 0; |
274 | } | |
275 | ||
69e3fd8c | 276 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
277 | { |
278 | struct e1000_hw *hw = &adapter->hw; | |
279 | static int global_quad_port_a; /* global port a indication */ | |
280 | struct pci_dev *pdev = adapter->pdev; | |
281 | u16 eeprom_data = 0; | |
282 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; | |
283 | s32 rc; | |
284 | ||
285 | rc = e1000_init_mac_params_82571(adapter); | |
286 | if (rc) | |
287 | return rc; | |
288 | ||
289 | rc = e1000_init_nvm_params_82571(hw); | |
290 | if (rc) | |
291 | return rc; | |
292 | ||
293 | rc = e1000_init_phy_params_82571(hw); | |
294 | if (rc) | |
295 | return rc; | |
296 | ||
297 | /* tag quad port adapters first, it's used below */ | |
298 | switch (pdev->device) { | |
299 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
300 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
301 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 302 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
303 | adapter->flags |= FLAG_IS_QUAD_PORT; |
304 | /* mark the first port */ | |
305 | if (global_quad_port_a == 0) | |
306 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
307 | /* Reset for multiple quad port adapters */ | |
308 | global_quad_port_a++; | |
309 | if (global_quad_port_a == 4) | |
310 | global_quad_port_a = 0; | |
311 | break; | |
312 | default: | |
313 | break; | |
314 | } | |
315 | ||
316 | switch (adapter->hw.mac.type) { | |
317 | case e1000_82571: | |
318 | /* these dual ports don't have WoL on port B at all */ | |
319 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
320 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
321 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
322 | (is_port_b)) | |
323 | adapter->flags &= ~FLAG_HAS_WOL; | |
324 | /* quad ports only support WoL on port A */ | |
325 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 326 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 327 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
328 | /* Does not support WoL on any port */ |
329 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
330 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa AK |
331 | break; |
332 | ||
333 | case e1000_82573: | |
334 | if (pdev->device == E1000_DEV_ID_82573L) { | |
e243455d BA |
335 | if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, |
336 | &eeprom_data) < 0) | |
337 | break; | |
bc7f75fa AK |
338 | if (eeprom_data & NVM_WORD1A_ASPM_MASK) |
339 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; | |
340 | } | |
341 | break; | |
342 | default: | |
343 | break; | |
344 | } | |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
349 | /** | |
350 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
351 | * @hw: pointer to the HW structure | |
352 | * | |
353 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
354 | * revision in the hardware structure. | |
355 | **/ | |
356 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
357 | { | |
358 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
359 | s32 ret_val; |
360 | u16 phy_id = 0; | |
bc7f75fa AK |
361 | |
362 | switch (hw->mac.type) { | |
363 | case e1000_82571: | |
364 | case e1000_82572: | |
ad68076e BA |
365 | /* |
366 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
367 | * In this case, we cannot access the PHY until the |
368 | * configuration is done. So we explicitly set the | |
ad68076e BA |
369 | * PHY ID. |
370 | */ | |
bc7f75fa AK |
371 | phy->id = IGP01E1000_I_PHY_ID; |
372 | break; | |
373 | case e1000_82573: | |
374 | return e1000e_get_phy_id(hw); | |
375 | break; | |
4662e82b BA |
376 | case e1000_82574: |
377 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); | |
378 | if (ret_val) | |
379 | return ret_val; | |
380 | ||
381 | phy->id = (u32)(phy_id << 16); | |
382 | udelay(20); | |
383 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
384 | if (ret_val) | |
385 | return ret_val; | |
386 | ||
387 | phy->id |= (u32)(phy_id); | |
388 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
389 | break; | |
bc7f75fa AK |
390 | default: |
391 | return -E1000_ERR_PHY; | |
392 | break; | |
393 | } | |
394 | ||
395 | return 0; | |
396 | } | |
397 | ||
398 | /** | |
399 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
400 | * @hw: pointer to the HW structure | |
401 | * | |
402 | * Acquire the HW semaphore to access the PHY or NVM | |
403 | **/ | |
404 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
405 | { | |
406 | u32 swsm; | |
407 | s32 timeout = hw->nvm.word_size + 1; | |
408 | s32 i = 0; | |
409 | ||
410 | /* Get the FW semaphore. */ | |
411 | for (i = 0; i < timeout; i++) { | |
412 | swsm = er32(SWSM); | |
413 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
414 | ||
415 | /* Semaphore acquired if bit latched */ | |
416 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
417 | break; | |
418 | ||
419 | udelay(50); | |
420 | } | |
421 | ||
422 | if (i == timeout) { | |
423 | /* Release semaphores */ | |
424 | e1000e_put_hw_semaphore(hw); | |
425 | hw_dbg(hw, "Driver can't access the NVM\n"); | |
426 | return -E1000_ERR_NVM; | |
427 | } | |
428 | ||
429 | return 0; | |
430 | } | |
431 | ||
432 | /** | |
433 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
434 | * @hw: pointer to the HW structure | |
435 | * | |
436 | * Release hardware semaphore used to access the PHY or NVM | |
437 | **/ | |
438 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
439 | { | |
440 | u32 swsm; | |
441 | ||
442 | swsm = er32(SWSM); | |
443 | ||
444 | swsm &= ~E1000_SWSM_SWESMBI; | |
445 | ||
446 | ew32(SWSM, swsm); | |
447 | } | |
448 | ||
449 | /** | |
450 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
451 | * @hw: pointer to the HW structure | |
452 | * | |
453 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
454 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
455 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
456 | * hardware semaphore. | |
457 | **/ | |
458 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
459 | { | |
460 | s32 ret_val; | |
461 | ||
462 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
463 | if (ret_val) | |
464 | return ret_val; | |
465 | ||
4662e82b | 466 | if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574) |
bc7f75fa AK |
467 | ret_val = e1000e_acquire_nvm(hw); |
468 | ||
469 | if (ret_val) | |
470 | e1000_put_hw_semaphore_82571(hw); | |
471 | ||
472 | return ret_val; | |
473 | } | |
474 | ||
475 | /** | |
476 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
477 | * @hw: pointer to the HW structure | |
478 | * | |
479 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
480 | **/ | |
481 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
482 | { | |
483 | e1000e_release_nvm(hw); | |
484 | e1000_put_hw_semaphore_82571(hw); | |
485 | } | |
486 | ||
487 | /** | |
488 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
489 | * @hw: pointer to the HW structure | |
490 | * @offset: offset within the EEPROM to be written to | |
491 | * @words: number of words to write | |
492 | * @data: 16 bit word(s) to be written to the EEPROM | |
493 | * | |
494 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
495 | * | |
496 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 497 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
498 | **/ |
499 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
500 | u16 *data) | |
501 | { | |
502 | s32 ret_val; | |
503 | ||
504 | switch (hw->mac.type) { | |
505 | case e1000_82573: | |
4662e82b | 506 | case e1000_82574: |
bc7f75fa AK |
507 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
508 | break; | |
509 | case e1000_82571: | |
510 | case e1000_82572: | |
511 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
512 | break; | |
513 | default: | |
514 | ret_val = -E1000_ERR_NVM; | |
515 | break; | |
516 | } | |
517 | ||
518 | return ret_val; | |
519 | } | |
520 | ||
521 | /** | |
522 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
523 | * @hw: pointer to the HW structure | |
524 | * | |
525 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
526 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
527 | * value to the EEPROM. | |
528 | **/ | |
529 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
530 | { | |
531 | u32 eecd; | |
532 | s32 ret_val; | |
533 | u16 i; | |
534 | ||
535 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
536 | if (ret_val) | |
537 | return ret_val; | |
538 | ||
ad68076e BA |
539 | /* |
540 | * If our nvm is an EEPROM, then we're done | |
541 | * otherwise, commit the checksum to the flash NVM. | |
542 | */ | |
bc7f75fa AK |
543 | if (hw->nvm.type != e1000_nvm_flash_hw) |
544 | return ret_val; | |
545 | ||
546 | /* Check for pending operations. */ | |
547 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
548 | msleep(1); | |
549 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
550 | break; | |
551 | } | |
552 | ||
553 | if (i == E1000_FLASH_UPDATES) | |
554 | return -E1000_ERR_NVM; | |
555 | ||
556 | /* Reset the firmware if using STM opcode. */ | |
557 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
558 | /* |
559 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
560 | * in two write cycles. |
561 | */ | |
562 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
563 | e1e_flush(); | |
564 | ew32(HICR, E1000_HICR_FW_RESET); | |
565 | } | |
566 | ||
567 | /* Commit the write to flash */ | |
568 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
569 | ew32(EECD, eecd); | |
570 | ||
571 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
572 | msleep(1); | |
573 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
574 | break; | |
575 | } | |
576 | ||
577 | if (i == E1000_FLASH_UPDATES) | |
578 | return -E1000_ERR_NVM; | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
583 | /** | |
584 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
585 | * @hw: pointer to the HW structure | |
586 | * | |
587 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
588 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
589 | **/ | |
590 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
591 | { | |
592 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
593 | e1000_fix_nvm_checksum_82571(hw); | |
594 | ||
595 | return e1000e_validate_nvm_checksum_generic(hw); | |
596 | } | |
597 | ||
598 | /** | |
599 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
600 | * @hw: pointer to the HW structure | |
601 | * @offset: offset within the EEPROM to be written to | |
602 | * @words: number of words to write | |
603 | * @data: 16 bit word(s) to be written to the EEPROM | |
604 | * | |
605 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
606 | * command has completed before trying to write the next word. After write | |
607 | * poll for completion. | |
608 | * | |
609 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 610 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
611 | **/ |
612 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
613 | u16 words, u16 *data) | |
614 | { | |
615 | struct e1000_nvm_info *nvm = &hw->nvm; | |
616 | u32 i; | |
617 | u32 eewr = 0; | |
618 | s32 ret_val = 0; | |
619 | ||
ad68076e BA |
620 | /* |
621 | * A check for invalid values: offset too large, too many words, | |
622 | * and not enough words. | |
623 | */ | |
bc7f75fa AK |
624 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
625 | (words == 0)) { | |
626 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
627 | return -E1000_ERR_NVM; | |
628 | } | |
629 | ||
630 | for (i = 0; i < words; i++) { | |
631 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
632 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
633 | E1000_NVM_RW_REG_START; | |
634 | ||
635 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
636 | if (ret_val) | |
637 | break; | |
638 | ||
639 | ew32(EEWR, eewr); | |
640 | ||
641 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
642 | if (ret_val) | |
643 | break; | |
644 | } | |
645 | ||
646 | return ret_val; | |
647 | } | |
648 | ||
649 | /** | |
650 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
651 | * @hw: pointer to the HW structure | |
652 | * | |
653 | * Reads the management control register for the config done bit to be set. | |
654 | **/ | |
655 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
656 | { | |
657 | s32 timeout = PHY_CFG_TIMEOUT; | |
658 | ||
659 | while (timeout) { | |
660 | if (er32(EEMNGCTL) & | |
661 | E1000_NVM_CFG_DONE_PORT_0) | |
662 | break; | |
663 | msleep(1); | |
664 | timeout--; | |
665 | } | |
666 | if (!timeout) { | |
667 | hw_dbg(hw, "MNG configuration cycle has not completed.\n"); | |
668 | return -E1000_ERR_RESET; | |
669 | } | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | /** | |
675 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
676 | * @hw: pointer to the HW structure | |
677 | * @active: TRUE to enable LPLU, FALSE to disable | |
678 | * | |
679 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
680 | * this function also disables smart speed and vice versa. LPLU will not be | |
681 | * activated unless the device autonegotiation advertisement meets standards | |
682 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
683 | * pointer entry point only called by PHY setup routines. | |
684 | **/ | |
685 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
686 | { | |
687 | struct e1000_phy_info *phy = &hw->phy; | |
688 | s32 ret_val; | |
689 | u16 data; | |
690 | ||
691 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
692 | if (ret_val) | |
693 | return ret_val; | |
694 | ||
695 | if (active) { | |
696 | data |= IGP02E1000_PM_D0_LPLU; | |
697 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
698 | if (ret_val) | |
699 | return ret_val; | |
700 | ||
701 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
702 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
703 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
704 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
705 | if (ret_val) | |
706 | return ret_val; | |
707 | } else { | |
708 | data &= ~IGP02E1000_PM_D0_LPLU; | |
709 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
710 | /* |
711 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
712 | * during Dx states where the power conservation is most |
713 | * important. During driver activity we should enable | |
ad68076e BA |
714 | * SmartSpeed, so performance is maintained. |
715 | */ | |
bc7f75fa AK |
716 | if (phy->smart_speed == e1000_smart_speed_on) { |
717 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 718 | &data); |
bc7f75fa AK |
719 | if (ret_val) |
720 | return ret_val; | |
721 | ||
722 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
723 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 724 | data); |
bc7f75fa AK |
725 | if (ret_val) |
726 | return ret_val; | |
727 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
728 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 729 | &data); |
bc7f75fa AK |
730 | if (ret_val) |
731 | return ret_val; | |
732 | ||
733 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
734 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 735 | data); |
bc7f75fa AK |
736 | if (ret_val) |
737 | return ret_val; | |
738 | } | |
739 | } | |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
744 | /** | |
745 | * e1000_reset_hw_82571 - Reset hardware | |
746 | * @hw: pointer to the HW structure | |
747 | * | |
748 | * This resets the hardware into a known state. This is a | |
749 | * function pointer entry point called by the api module. | |
750 | **/ | |
751 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
752 | { | |
753 | u32 ctrl; | |
754 | u32 extcnf_ctrl; | |
755 | u32 ctrl_ext; | |
756 | u32 icr; | |
757 | s32 ret_val; | |
758 | u16 i = 0; | |
759 | ||
ad68076e BA |
760 | /* |
761 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
762 | * on the last TLP read/write transaction when MAC is reset. |
763 | */ | |
764 | ret_val = e1000e_disable_pcie_master(hw); | |
765 | if (ret_val) | |
766 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
767 | ||
768 | hw_dbg(hw, "Masking off all interrupts\n"); | |
769 | ew32(IMC, 0xffffffff); | |
770 | ||
771 | ew32(RCTL, 0); | |
772 | ew32(TCTL, E1000_TCTL_PSP); | |
773 | e1e_flush(); | |
774 | ||
775 | msleep(10); | |
776 | ||
ad68076e BA |
777 | /* |
778 | * Must acquire the MDIO ownership before MAC reset. | |
779 | * Ownership defaults to firmware after a reset. | |
780 | */ | |
4662e82b | 781 | if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { |
bc7f75fa AK |
782 | extcnf_ctrl = er32(EXTCNF_CTRL); |
783 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
784 | ||
785 | do { | |
786 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
787 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
788 | ||
789 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
790 | break; | |
791 | ||
792 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
793 | ||
794 | msleep(2); | |
795 | i++; | |
796 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
797 | } | |
798 | ||
799 | ctrl = er32(CTRL); | |
800 | ||
801 | hw_dbg(hw, "Issuing a global reset to MAC\n"); | |
802 | ew32(CTRL, ctrl | E1000_CTRL_RST); | |
803 | ||
804 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
805 | udelay(10); | |
806 | ctrl_ext = er32(CTRL_EXT); | |
807 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
808 | ew32(CTRL_EXT, ctrl_ext); | |
809 | e1e_flush(); | |
810 | } | |
811 | ||
812 | ret_val = e1000e_get_auto_rd_done(hw); | |
813 | if (ret_val) | |
814 | /* We don't want to continue accessing MAC registers. */ | |
815 | return ret_val; | |
816 | ||
ad68076e BA |
817 | /* |
818 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
819 | * Need to wait for Phy configuration completion before accessing |
820 | * NVM and Phy. | |
821 | */ | |
4662e82b | 822 | if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) |
bc7f75fa AK |
823 | msleep(25); |
824 | ||
825 | /* Clear any pending interrupt events. */ | |
826 | ew32(IMC, 0xffffffff); | |
827 | icr = er32(ICR); | |
828 | ||
93ca1610 BH |
829 | if (hw->mac.type == e1000_82571 && |
830 | hw->dev_spec.e82571.alt_mac_addr_is_present) | |
831 | e1000e_set_laa_state_82571(hw, true); | |
832 | ||
bc7f75fa AK |
833 | return 0; |
834 | } | |
835 | ||
836 | /** | |
837 | * e1000_init_hw_82571 - Initialize hardware | |
838 | * @hw: pointer to the HW structure | |
839 | * | |
840 | * This inits the hardware readying it for operation. | |
841 | **/ | |
842 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
843 | { | |
844 | struct e1000_mac_info *mac = &hw->mac; | |
845 | u32 reg_data; | |
846 | s32 ret_val; | |
847 | u16 i; | |
848 | u16 rar_count = mac->rar_entry_count; | |
849 | ||
850 | e1000_initialize_hw_bits_82571(hw); | |
851 | ||
852 | /* Initialize identification LED */ | |
853 | ret_val = e1000e_id_led_init(hw); | |
854 | if (ret_val) { | |
855 | hw_dbg(hw, "Error initializing identification LED\n"); | |
856 | return ret_val; | |
857 | } | |
858 | ||
859 | /* Disabling VLAN filtering */ | |
860 | hw_dbg(hw, "Initializing the IEEE VLAN\n"); | |
861 | e1000e_clear_vfta(hw); | |
862 | ||
863 | /* Setup the receive address. */ | |
ad68076e BA |
864 | /* |
865 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
866 | * 82571, we must reserve a RAR for it to work around an issue where |
867 | * resetting one port will reload the MAC on the other port. | |
868 | */ | |
869 | if (e1000e_get_laa_state_82571(hw)) | |
870 | rar_count--; | |
871 | e1000e_init_rx_addrs(hw, rar_count); | |
872 | ||
873 | /* Zero out the Multicast HASH table */ | |
874 | hw_dbg(hw, "Zeroing the MTA\n"); | |
875 | for (i = 0; i < mac->mta_reg_count; i++) | |
876 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
877 | ||
878 | /* Setup link and flow control */ | |
879 | ret_val = e1000_setup_link_82571(hw); | |
880 | ||
881 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 882 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
883 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
884 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
885 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 886 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
887 | |
888 | /* ...for both queues. */ | |
4662e82b | 889 | if (mac->type != e1000_82573 && mac->type != e1000_82574) { |
e9ec2c0f | 890 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
891 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
892 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
893 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 894 | ew32(TXDCTL(1), reg_data); |
bc7f75fa AK |
895 | } else { |
896 | e1000e_enable_tx_pkt_filtering(hw); | |
897 | reg_data = er32(GCR); | |
898 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
899 | ew32(GCR, reg_data); | |
900 | } | |
901 | ||
ad68076e BA |
902 | /* |
903 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
904 | * important that we do this after we have tried to establish link |
905 | * because the symbol error count will increment wildly if there | |
906 | * is no link. | |
907 | */ | |
908 | e1000_clear_hw_cntrs_82571(hw); | |
909 | ||
910 | return ret_val; | |
911 | } | |
912 | ||
913 | /** | |
914 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
915 | * @hw: pointer to the HW structure | |
916 | * | |
917 | * Initializes required hardware-dependent bits needed for normal operation. | |
918 | **/ | |
919 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
920 | { | |
921 | u32 reg; | |
922 | ||
923 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 924 | reg = er32(TXDCTL(0)); |
bc7f75fa | 925 | reg |= (1 << 22); |
e9ec2c0f | 926 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
927 | |
928 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 929 | reg = er32(TXDCTL(1)); |
bc7f75fa | 930 | reg |= (1 << 22); |
e9ec2c0f | 931 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
932 | |
933 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 934 | reg = er32(TARC(0)); |
bc7f75fa AK |
935 | reg &= ~(0xF << 27); /* 30:27 */ |
936 | switch (hw->mac.type) { | |
937 | case e1000_82571: | |
938 | case e1000_82572: | |
939 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
940 | break; | |
941 | default: | |
942 | break; | |
943 | } | |
e9ec2c0f | 944 | ew32(TARC(0), reg); |
bc7f75fa AK |
945 | |
946 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 947 | reg = er32(TARC(1)); |
bc7f75fa AK |
948 | switch (hw->mac.type) { |
949 | case e1000_82571: | |
950 | case e1000_82572: | |
951 | reg &= ~((1 << 29) | (1 << 30)); | |
952 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
953 | if (er32(TCTL) & E1000_TCTL_MULR) | |
954 | reg &= ~(1 << 28); | |
955 | else | |
956 | reg |= (1 << 28); | |
e9ec2c0f | 957 | ew32(TARC(1), reg); |
bc7f75fa AK |
958 | break; |
959 | default: | |
960 | break; | |
961 | } | |
962 | ||
963 | /* Device Control */ | |
4662e82b | 964 | if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { |
bc7f75fa AK |
965 | reg = er32(CTRL); |
966 | reg &= ~(1 << 29); | |
967 | ew32(CTRL, reg); | |
968 | } | |
969 | ||
970 | /* Extended Device Control */ | |
4662e82b | 971 | if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { |
bc7f75fa AK |
972 | reg = er32(CTRL_EXT); |
973 | reg &= ~(1 << 23); | |
974 | reg |= (1 << 22); | |
975 | ew32(CTRL_EXT, reg); | |
976 | } | |
4662e82b | 977 | |
6ea7ae1d AD |
978 | if (hw->mac.type == e1000_82571) { |
979 | reg = er32(PBA_ECC); | |
980 | reg |= E1000_PBA_ECC_CORR_EN; | |
981 | ew32(PBA_ECC, reg); | |
982 | } | |
983 | ||
78272bba | 984 | /* PCI-Ex Control Registers */ |
4662e82b BA |
985 | if (hw->mac.type == e1000_82574) { |
986 | reg = er32(GCR); | |
987 | reg |= (1 << 22); | |
988 | ew32(GCR, reg); | |
78272bba JB |
989 | |
990 | reg = er32(GCR2); | |
991 | reg |= 1; | |
992 | ew32(GCR2, reg); | |
4662e82b BA |
993 | } |
994 | ||
995 | return; | |
bc7f75fa AK |
996 | } |
997 | ||
998 | /** | |
999 | * e1000e_clear_vfta - Clear VLAN filter table | |
1000 | * @hw: pointer to the HW structure | |
1001 | * | |
1002 | * Clears the register array which contains the VLAN filter table by | |
1003 | * setting all the values to 0. | |
1004 | **/ | |
1005 | void e1000e_clear_vfta(struct e1000_hw *hw) | |
1006 | { | |
1007 | u32 offset; | |
1008 | u32 vfta_value = 0; | |
1009 | u32 vfta_offset = 0; | |
1010 | u32 vfta_bit_in_reg = 0; | |
1011 | ||
4662e82b | 1012 | if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) { |
bc7f75fa | 1013 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1014 | /* |
1015 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1016 | * a single VLAN ID. The following operations |
1017 | * determine which 32b entry (i.e. offset) into the | |
1018 | * array we want to set the VLAN ID (i.e. bit) of | |
1019 | * the manageability unit. | |
1020 | */ | |
1021 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1022 | E1000_VFTA_ENTRY_SHIFT) & | |
1023 | E1000_VFTA_ENTRY_MASK; | |
1024 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1025 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1026 | } | |
1027 | } | |
1028 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1029 | /* |
1030 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1031 | * manageability VLAN ID, then clear all bits except that of |
1032 | * the manageability unit. | |
1033 | */ | |
1034 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1035 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1036 | e1e_flush(); | |
1037 | } | |
1038 | } | |
1039 | ||
4662e82b BA |
1040 | /** |
1041 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1042 | * @hw: pointer to the HW structure | |
1043 | * | |
1044 | * Reads the NVM Initialization Control Word 2 and returns true | |
1045 | * (>0) if any manageability is enabled, else false (0). | |
1046 | **/ | |
1047 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1048 | { | |
1049 | u16 data; | |
1050 | ||
1051 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1052 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1053 | } | |
1054 | ||
1055 | /** | |
1056 | * e1000_led_on_82574 - Turn LED on | |
1057 | * @hw: pointer to the HW structure | |
1058 | * | |
1059 | * Turn LED on. | |
1060 | **/ | |
1061 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1062 | { | |
1063 | u32 ctrl; | |
1064 | u32 i; | |
1065 | ||
1066 | ctrl = hw->mac.ledctl_mode2; | |
1067 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1068 | /* | |
1069 | * If no link, then turn LED on by setting the invert bit | |
1070 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1071 | */ | |
1072 | for (i = 0; i < 4; i++) | |
1073 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1074 | E1000_LEDCTL_MODE_LED_ON) | |
1075 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1076 | } | |
1077 | ew32(LEDCTL, ctrl); | |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
bc7f75fa | 1082 | /** |
e2de3eb6 | 1083 | * e1000_update_mc_addr_list_82571 - Update Multicast addresses |
bc7f75fa AK |
1084 | * @hw: pointer to the HW structure |
1085 | * @mc_addr_list: array of multicast addresses to program | |
1086 | * @mc_addr_count: number of multicast addresses to program | |
1087 | * @rar_used_count: the first RAR register free to program | |
1088 | * @rar_count: total number of supported Receive Address Registers | |
1089 | * | |
1090 | * Updates the Receive Address Registers and Multicast Table Array. | |
1091 | * The caller must have a packed mc_addr_list of multicast addresses. | |
1092 | * The parameter rar_count will usually be hw->mac.rar_entry_count | |
1093 | * unless there are workarounds that change this. | |
1094 | **/ | |
e2de3eb6 | 1095 | static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, |
bc7f75fa AK |
1096 | u8 *mc_addr_list, |
1097 | u32 mc_addr_count, | |
1098 | u32 rar_used_count, | |
1099 | u32 rar_count) | |
1100 | { | |
1101 | if (e1000e_get_laa_state_82571(hw)) | |
1102 | rar_count--; | |
1103 | ||
e2de3eb6 JK |
1104 | e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, |
1105 | rar_used_count, rar_count); | |
bc7f75fa AK |
1106 | } |
1107 | ||
1108 | /** | |
1109 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1110 | * @hw: pointer to the HW structure | |
1111 | * | |
1112 | * Determines which flow control settings to use, then configures flow | |
1113 | * control. Calls the appropriate media-specific link configuration | |
1114 | * function. Assuming the adapter has a valid link partner, a valid link | |
1115 | * should be established. Assumes the hardware has previously been reset | |
1116 | * and the transmitter and receiver are not enabled. | |
1117 | **/ | |
1118 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1119 | { | |
ad68076e BA |
1120 | /* |
1121 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1122 | * the default flow control setting, so we explicitly |
1123 | * set it to full. | |
1124 | */ | |
4662e82b | 1125 | if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) && |
5c48ef3e BA |
1126 | hw->fc.requested_mode == e1000_fc_default) |
1127 | hw->fc.requested_mode = e1000_fc_full; | |
bc7f75fa AK |
1128 | |
1129 | return e1000e_setup_link(hw); | |
1130 | } | |
1131 | ||
1132 | /** | |
1133 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1134 | * @hw: pointer to the HW structure | |
1135 | * | |
1136 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1137 | * for link, once link is established calls to configure collision distance | |
1138 | * and flow control are called. | |
1139 | **/ | |
1140 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1141 | { | |
1142 | u32 ctrl; | |
1143 | u32 led_ctrl; | |
1144 | s32 ret_val; | |
1145 | ||
1146 | ctrl = er32(CTRL); | |
1147 | ctrl |= E1000_CTRL_SLU; | |
1148 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1149 | ew32(CTRL, ctrl); | |
1150 | ||
1151 | switch (hw->phy.type) { | |
1152 | case e1000_phy_m88: | |
4662e82b | 1153 | case e1000_phy_bm: |
bc7f75fa AK |
1154 | ret_val = e1000e_copper_link_setup_m88(hw); |
1155 | break; | |
1156 | case e1000_phy_igp_2: | |
1157 | ret_val = e1000e_copper_link_setup_igp(hw); | |
1158 | /* Setup activity LED */ | |
1159 | led_ctrl = er32(LEDCTL); | |
1160 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1161 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1162 | ew32(LEDCTL, led_ctrl); | |
1163 | break; | |
1164 | default: | |
1165 | return -E1000_ERR_PHY; | |
1166 | break; | |
1167 | } | |
1168 | ||
1169 | if (ret_val) | |
1170 | return ret_val; | |
1171 | ||
1172 | ret_val = e1000e_setup_copper_link(hw); | |
1173 | ||
1174 | return ret_val; | |
1175 | } | |
1176 | ||
1177 | /** | |
1178 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1179 | * @hw: pointer to the HW structure | |
1180 | * | |
1181 | * Configures collision distance and flow control for fiber and serdes links. | |
1182 | * Upon successful setup, poll for link. | |
1183 | **/ | |
1184 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1185 | { | |
1186 | switch (hw->mac.type) { | |
1187 | case e1000_82571: | |
1188 | case e1000_82572: | |
ad68076e BA |
1189 | /* |
1190 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1191 | * of reset to take the adapter out of that mode. So we |
1192 | * have to explicitly take the adapter out of loopback | |
489815ce | 1193 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1194 | * if another tool failed to take it out of loopback mode. |
1195 | */ | |
ad68076e | 1196 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1197 | break; |
1198 | default: | |
1199 | break; | |
1200 | } | |
1201 | ||
1202 | return e1000e_setup_fiber_serdes_link(hw); | |
1203 | } | |
1204 | ||
1205 | /** | |
1206 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1207 | * @hw: pointer to the HW structure | |
1208 | * @data: pointer to the NVM (EEPROM) | |
1209 | * | |
1210 | * Read the EEPROM for the current default LED configuration. If the | |
1211 | * LED configuration is not valid, set to a valid LED configuration. | |
1212 | **/ | |
1213 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1214 | { | |
1215 | s32 ret_val; | |
1216 | ||
1217 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1218 | if (ret_val) { | |
1219 | hw_dbg(hw, "NVM Read Error\n"); | |
1220 | return ret_val; | |
1221 | } | |
1222 | ||
4662e82b | 1223 | if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) && |
bc7f75fa AK |
1224 | *data == ID_LED_RESERVED_F746) |
1225 | *data = ID_LED_DEFAULT_82573; | |
4662e82b | 1226 | else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) |
bc7f75fa AK |
1227 | *data = ID_LED_DEFAULT; |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | /** | |
1233 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1234 | * @hw: pointer to the HW structure | |
1235 | * | |
489815ce | 1236 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1237 | **/ |
1238 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1239 | { | |
1240 | if (hw->mac.type != e1000_82571) | |
1241 | return 0; | |
1242 | ||
1243 | return hw->dev_spec.e82571.laa_is_present; | |
1244 | } | |
1245 | ||
1246 | /** | |
1247 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1248 | * @hw: pointer to the HW structure | |
1249 | * @state: enable/disable locally administered address | |
1250 | * | |
489815ce | 1251 | * Enable/Disable the current locally administers address state. |
bc7f75fa AK |
1252 | **/ |
1253 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1254 | { | |
1255 | if (hw->mac.type != e1000_82571) | |
1256 | return; | |
1257 | ||
1258 | hw->dev_spec.e82571.laa_is_present = state; | |
1259 | ||
1260 | /* If workaround is activated... */ | |
1261 | if (state) | |
ad68076e BA |
1262 | /* |
1263 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1264 | * between the time RAR[0] gets clobbered and the time it |
1265 | * gets fixed, the actual LAA is in one of the RARs and no | |
1266 | * incoming packets directed to this port are dropped. | |
1267 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1268 | */ | |
1269 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1270 | } | |
1271 | ||
1272 | /** | |
1273 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1274 | * @hw: pointer to the HW structure | |
1275 | * | |
1276 | * Verifies that the EEPROM has completed the update. After updating the | |
1277 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1278 | * the checksum fix is not implemented, we need to set the bit and update | |
1279 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1280 | * we need to return bad checksum. | |
1281 | **/ | |
1282 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1283 | { | |
1284 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1285 | s32 ret_val; | |
1286 | u16 data; | |
1287 | ||
1288 | if (nvm->type != e1000_nvm_flash_hw) | |
1289 | return 0; | |
1290 | ||
ad68076e BA |
1291 | /* |
1292 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1293 | * 10h-12h. Checksum may need to be fixed. |
1294 | */ | |
1295 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1296 | if (ret_val) | |
1297 | return ret_val; | |
1298 | ||
1299 | if (!(data & 0x10)) { | |
ad68076e BA |
1300 | /* |
1301 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1302 | * when the checksum has already been fixed. If |
1303 | * the checksum is still wrong and this bit is a | |
1304 | * 1, we need to return bad checksum. Otherwise, | |
1305 | * we need to set this bit to a 1 and update the | |
1306 | * checksum. | |
1307 | */ | |
1308 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1309 | if (ret_val) | |
1310 | return ret_val; | |
1311 | ||
1312 | if (!(data & 0x8000)) { | |
1313 | data |= 0x8000; | |
1314 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1315 | if (ret_val) | |
1316 | return ret_val; | |
1317 | ret_val = e1000e_update_nvm_checksum(hw); | |
1318 | } | |
1319 | } | |
1320 | ||
1321 | return 0; | |
1322 | } | |
1323 | ||
1324 | /** | |
1325 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1326 | * @hw: pointer to the HW structure | |
1327 | * | |
1328 | * Clears the hardware counters by reading the counter registers. | |
1329 | **/ | |
1330 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1331 | { | |
1332 | u32 temp; | |
1333 | ||
1334 | e1000e_clear_hw_cntrs_base(hw); | |
1335 | ||
1336 | temp = er32(PRC64); | |
1337 | temp = er32(PRC127); | |
1338 | temp = er32(PRC255); | |
1339 | temp = er32(PRC511); | |
1340 | temp = er32(PRC1023); | |
1341 | temp = er32(PRC1522); | |
1342 | temp = er32(PTC64); | |
1343 | temp = er32(PTC127); | |
1344 | temp = er32(PTC255); | |
1345 | temp = er32(PTC511); | |
1346 | temp = er32(PTC1023); | |
1347 | temp = er32(PTC1522); | |
1348 | ||
1349 | temp = er32(ALGNERRC); | |
1350 | temp = er32(RXERRC); | |
1351 | temp = er32(TNCRS); | |
1352 | temp = er32(CEXTERR); | |
1353 | temp = er32(TSCTC); | |
1354 | temp = er32(TSCTFC); | |
1355 | ||
1356 | temp = er32(MGTPRC); | |
1357 | temp = er32(MGTPDC); | |
1358 | temp = er32(MGTPTC); | |
1359 | ||
1360 | temp = er32(IAC); | |
1361 | temp = er32(ICRXOC); | |
1362 | ||
1363 | temp = er32(ICRXPTC); | |
1364 | temp = er32(ICRXATC); | |
1365 | temp = er32(ICTXPTC); | |
1366 | temp = er32(ICTXATC); | |
1367 | temp = er32(ICTXQEC); | |
1368 | temp = er32(ICTXQMTC); | |
1369 | temp = er32(ICRXDMTC); | |
1370 | } | |
1371 | ||
1372 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1373 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa AK |
1374 | /* .check_for_link: media type dependent */ |
1375 | .cleanup_led = e1000e_cleanup_led_generic, | |
1376 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1377 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1378 | /* .get_link_up_info: media type dependent */ | |
4662e82b | 1379 | /* .led_on: mac type dependent */ |
bc7f75fa | 1380 | .led_off = e1000e_led_off_generic, |
e2de3eb6 | 1381 | .update_mc_addr_list = e1000_update_mc_addr_list_82571, |
bc7f75fa AK |
1382 | .reset_hw = e1000_reset_hw_82571, |
1383 | .init_hw = e1000_init_hw_82571, | |
1384 | .setup_link = e1000_setup_link_82571, | |
1385 | /* .setup_physical_interface: media type dependent */ | |
1386 | }; | |
1387 | ||
1388 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
1389 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1390 | .check_reset_block = e1000e_check_reset_block_generic, | |
1391 | .commit_phy = NULL, | |
1392 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, | |
1393 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1394 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
1395 | .get_phy_info = e1000e_get_phy_info_igp, | |
1396 | .read_phy_reg = e1000e_read_phy_reg_igp, | |
1397 | .release_phy = e1000_put_hw_semaphore_82571, | |
1398 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1399 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1400 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1401 | .write_phy_reg = e1000e_write_phy_reg_igp, | |
75eb0fad | 1402 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1403 | }; |
1404 | ||
1405 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
1406 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1407 | .check_reset_block = e1000e_check_reset_block_generic, | |
1408 | .commit_phy = e1000e_phy_sw_reset, | |
1409 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, | |
1410 | .get_cfg_done = e1000e_get_cfg_done, | |
1411 | .get_cable_length = e1000e_get_cable_length_m88, | |
1412 | .get_phy_info = e1000e_get_phy_info_m88, | |
1413 | .read_phy_reg = e1000e_read_phy_reg_m88, | |
1414 | .release_phy = e1000_put_hw_semaphore_82571, | |
1415 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1416 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1417 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1418 | .write_phy_reg = e1000e_write_phy_reg_m88, | |
75eb0fad | 1419 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1420 | }; |
1421 | ||
4662e82b BA |
1422 | static struct e1000_phy_operations e82_phy_ops_bm = { |
1423 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1424 | .check_reset_block = e1000e_check_reset_block_generic, | |
1425 | .commit_phy = e1000e_phy_sw_reset, | |
1426 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, | |
1427 | .get_cfg_done = e1000e_get_cfg_done, | |
1428 | .get_cable_length = e1000e_get_cable_length_m88, | |
1429 | .get_phy_info = e1000e_get_phy_info_m88, | |
1430 | .read_phy_reg = e1000e_read_phy_reg_bm2, | |
1431 | .release_phy = e1000_put_hw_semaphore_82571, | |
1432 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1433 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1434 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1435 | .write_phy_reg = e1000e_write_phy_reg_bm2, | |
75eb0fad | 1436 | .cfg_on_link_up = NULL, |
4662e82b BA |
1437 | }; |
1438 | ||
bc7f75fa | 1439 | static struct e1000_nvm_operations e82571_nvm_ops = { |
bc7f75fa AK |
1440 | .acquire_nvm = e1000_acquire_nvm_82571, |
1441 | .read_nvm = e1000e_read_nvm_eerd, | |
1442 | .release_nvm = e1000_release_nvm_82571, | |
1443 | .update_nvm = e1000_update_nvm_checksum_82571, | |
1444 | .valid_led_default = e1000_valid_led_default_82571, | |
1445 | .validate_nvm = e1000_validate_nvm_checksum_82571, | |
1446 | .write_nvm = e1000_write_nvm_82571, | |
1447 | }; | |
1448 | ||
1449 | struct e1000_info e1000_82571_info = { | |
1450 | .mac = e1000_82571, | |
1451 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1452 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1453 | | FLAG_HAS_WOL |
1454 | | FLAG_APME_IN_CTRL3 | |
1455 | | FLAG_RX_CSUM_ENABLED | |
1456 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1457 | | FLAG_HAS_SMART_POWER_DOWN |
1458 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1459 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1460 | | FLAG_APME_CHECK_PORT_B, | |
1461 | .pba = 38, | |
69e3fd8c | 1462 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1463 | .mac_ops = &e82571_mac_ops, |
1464 | .phy_ops = &e82_phy_ops_igp, | |
1465 | .nvm_ops = &e82571_nvm_ops, | |
1466 | }; | |
1467 | ||
1468 | struct e1000_info e1000_82572_info = { | |
1469 | .mac = e1000_82572, | |
1470 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1471 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1472 | | FLAG_HAS_WOL |
1473 | | FLAG_APME_IN_CTRL3 | |
1474 | | FLAG_RX_CSUM_ENABLED | |
1475 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1476 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
1477 | .pba = 38, | |
69e3fd8c | 1478 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1479 | .mac_ops = &e82571_mac_ops, |
1480 | .phy_ops = &e82_phy_ops_igp, | |
1481 | .nvm_ops = &e82571_nvm_ops, | |
1482 | }; | |
1483 | ||
1484 | struct e1000_info e1000_82573_info = { | |
1485 | .mac = e1000_82573, | |
1486 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1487 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1488 | | FLAG_HAS_WOL |
1489 | | FLAG_APME_IN_CTRL3 | |
1490 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
1491 | | FLAG_HAS_SMART_POWER_DOWN |
1492 | | FLAG_HAS_AMT | |
bc7f75fa AK |
1493 | | FLAG_HAS_ERT |
1494 | | FLAG_HAS_SWSM_ON_LOAD, | |
1495 | .pba = 20, | |
69e3fd8c | 1496 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1497 | .mac_ops = &e82571_mac_ops, |
1498 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1499 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1500 | }; |
1501 | ||
4662e82b BA |
1502 | struct e1000_info e1000_82574_info = { |
1503 | .mac = e1000_82574, | |
1504 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1505 | | FLAG_HAS_MSIX | |
1506 | | FLAG_HAS_JUMBO_FRAMES | |
1507 | | FLAG_HAS_WOL | |
1508 | | FLAG_APME_IN_CTRL3 | |
1509 | | FLAG_RX_CSUM_ENABLED | |
1510 | | FLAG_HAS_SMART_POWER_DOWN | |
1511 | | FLAG_HAS_AMT | |
1512 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1513 | .pba = 20, | |
1514 | .get_variants = e1000_get_variants_82571, | |
1515 | .mac_ops = &e82571_mac_ops, | |
1516 | .phy_ops = &e82_phy_ops_bm, | |
1517 | .nvm_ops = &e82571_nvm_ops, | |
1518 | }; | |
1519 |