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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
451152d9 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
bc7f75fa AK |
46 | #include "e1000.h" |
47 | ||
48 | #define ID_LED_RESERVED_F746 0xF746 | |
49 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
50 | (ID_LED_OFF1_ON2 << 8) | \ | |
51 | (ID_LED_DEF1_DEF2 << 4) | \ | |
52 | (ID_LED_DEF1_DEF2)) | |
53 | ||
54 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
d9c76f99 | 55 | #define AN_RETRY_COUNT 5 /* Autoneg Retry Count value */ |
ff10e13c CW |
56 | #define E1000_BASE1000T_STATUS 10 |
57 | #define E1000_IDLE_ERROR_COUNT_MASK 0xFF | |
58 | #define E1000_RECEIVE_ERROR_COUNTER 21 | |
59 | #define E1000_RECEIVE_ERROR_MAX 0xFFFF | |
bc7f75fa | 60 | |
4662e82b BA |
61 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
62 | ||
bc7f75fa AK |
63 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
64 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
65 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 66 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
67 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
68 | u16 words, u16 *data); | |
69 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
70 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
71 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
72 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
caaddaf8 | 73 | static void e1000_clear_vfta_82571(struct e1000_hw *hw); |
4662e82b BA |
74 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
75 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
23a2d1b2 | 76 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); |
17f208de | 77 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw); |
1b98c2bb BA |
78 | static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw); |
79 | static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw); | |
80 | static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw); | |
bc7f75fa AK |
81 | |
82 | /** | |
83 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
84 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
85 | **/ |
86 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
87 | { | |
88 | struct e1000_phy_info *phy = &hw->phy; | |
89 | s32 ret_val; | |
90 | ||
318a94d6 | 91 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
92 | phy->type = e1000_phy_none; |
93 | return 0; | |
94 | } | |
95 | ||
96 | phy->addr = 1; | |
97 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
98 | phy->reset_delay_us = 100; | |
99 | ||
17f208de BA |
100 | phy->ops.power_up = e1000_power_up_phy_copper; |
101 | phy->ops.power_down = e1000_power_down_phy_copper_82571; | |
102 | ||
bc7f75fa AK |
103 | switch (hw->mac.type) { |
104 | case e1000_82571: | |
105 | case e1000_82572: | |
106 | phy->type = e1000_phy_igp_2; | |
107 | break; | |
108 | case e1000_82573: | |
109 | phy->type = e1000_phy_m88; | |
110 | break; | |
4662e82b | 111 | case e1000_82574: |
8c81c9c3 | 112 | case e1000_82583: |
4662e82b | 113 | phy->type = e1000_phy_bm; |
1b98c2bb BA |
114 | phy->ops.acquire = e1000_get_hw_semaphore_82574; |
115 | phy->ops.release = e1000_put_hw_semaphore_82574; | |
4662e82b | 116 | break; |
bc7f75fa AK |
117 | default: |
118 | return -E1000_ERR_PHY; | |
119 | break; | |
120 | } | |
121 | ||
122 | /* This can only be done after all function pointers are setup. */ | |
123 | ret_val = e1000_get_phy_id_82571(hw); | |
dd93f95e BA |
124 | if (ret_val) { |
125 | e_dbg("Error getting PHY ID\n"); | |
126 | return ret_val; | |
127 | } | |
bc7f75fa AK |
128 | |
129 | /* Verify phy id */ | |
130 | switch (hw->mac.type) { | |
131 | case e1000_82571: | |
132 | case e1000_82572: | |
133 | if (phy->id != IGP01E1000_I_PHY_ID) | |
dd93f95e | 134 | ret_val = -E1000_ERR_PHY; |
bc7f75fa AK |
135 | break; |
136 | case e1000_82573: | |
137 | if (phy->id != M88E1111_I_PHY_ID) | |
dd93f95e | 138 | ret_val = -E1000_ERR_PHY; |
bc7f75fa | 139 | break; |
4662e82b | 140 | case e1000_82574: |
8c81c9c3 | 141 | case e1000_82583: |
4662e82b | 142 | if (phy->id != BME1000_E_PHY_ID_R2) |
dd93f95e | 143 | ret_val = -E1000_ERR_PHY; |
4662e82b | 144 | break; |
bc7f75fa | 145 | default: |
dd93f95e | 146 | ret_val = -E1000_ERR_PHY; |
bc7f75fa AK |
147 | break; |
148 | } | |
149 | ||
dd93f95e BA |
150 | if (ret_val) |
151 | e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id); | |
152 | ||
153 | return ret_val; | |
bc7f75fa AK |
154 | } |
155 | ||
156 | /** | |
157 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
158 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
159 | **/ |
160 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
161 | { | |
162 | struct e1000_nvm_info *nvm = &hw->nvm; | |
163 | u32 eecd = er32(EECD); | |
164 | u16 size; | |
165 | ||
166 | nvm->opcode_bits = 8; | |
167 | nvm->delay_usec = 1; | |
168 | switch (nvm->override) { | |
169 | case e1000_nvm_override_spi_large: | |
170 | nvm->page_size = 32; | |
171 | nvm->address_bits = 16; | |
172 | break; | |
173 | case e1000_nvm_override_spi_small: | |
174 | nvm->page_size = 8; | |
175 | nvm->address_bits = 8; | |
176 | break; | |
177 | default: | |
178 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
179 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
180 | break; | |
181 | } | |
182 | ||
183 | switch (hw->mac.type) { | |
184 | case e1000_82573: | |
4662e82b | 185 | case e1000_82574: |
8c81c9c3 | 186 | case e1000_82583: |
bc7f75fa AK |
187 | if (((eecd >> 15) & 0x3) == 0x3) { |
188 | nvm->type = e1000_nvm_flash_hw; | |
189 | nvm->word_size = 2048; | |
ad68076e BA |
190 | /* |
191 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
192 | * to Flash update issue. |
193 | */ | |
194 | eecd &= ~E1000_EECD_AUPDEN; | |
195 | ew32(EECD, eecd); | |
196 | break; | |
197 | } | |
198 | /* Fall Through */ | |
199 | default: | |
ad68076e | 200 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
201 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
202 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
203 | /* |
204 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
205 | * for setting word_size. |
206 | */ | |
207 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
208 | |
209 | /* EEPROM access above 16k is unsupported */ | |
210 | if (size > 14) | |
211 | size = 14; | |
bc7f75fa AK |
212 | nvm->word_size = 1 << size; |
213 | break; | |
214 | } | |
215 | ||
1b98c2bb BA |
216 | /* Function Pointers */ |
217 | switch (hw->mac.type) { | |
218 | case e1000_82574: | |
219 | case e1000_82583: | |
220 | nvm->ops.acquire = e1000_get_hw_semaphore_82574; | |
221 | nvm->ops.release = e1000_put_hw_semaphore_82574; | |
222 | break; | |
223 | default: | |
224 | break; | |
225 | } | |
226 | ||
bc7f75fa AK |
227 | return 0; |
228 | } | |
229 | ||
230 | /** | |
231 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
232 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
233 | **/ |
234 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
235 | { | |
236 | struct e1000_hw *hw = &adapter->hw; | |
237 | struct e1000_mac_info *mac = &hw->mac; | |
238 | struct e1000_mac_operations *func = &mac->ops; | |
23a2d1b2 DG |
239 | u32 swsm = 0; |
240 | u32 swsm2 = 0; | |
241 | bool force_clear_smbi = false; | |
bc7f75fa AK |
242 | |
243 | /* Set media type */ | |
244 | switch (adapter->pdev->device) { | |
245 | case E1000_DEV_ID_82571EB_FIBER: | |
246 | case E1000_DEV_ID_82572EI_FIBER: | |
247 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 248 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
249 | break; |
250 | case E1000_DEV_ID_82571EB_SERDES: | |
251 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
252 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
253 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 254 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
255 | break; |
256 | default: | |
318a94d6 | 257 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
258 | break; |
259 | } | |
260 | ||
261 | /* Set mta register count */ | |
262 | mac->mta_reg_count = 128; | |
263 | /* Set rar entry count */ | |
264 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
f464ba87 BA |
265 | /* Adaptive IFS supported */ |
266 | mac->adaptive_ifs = true; | |
bc7f75fa AK |
267 | |
268 | /* check for link */ | |
318a94d6 | 269 | switch (hw->phy.media_type) { |
bc7f75fa AK |
270 | case e1000_media_type_copper: |
271 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
272 | func->check_for_link = e1000e_check_for_copper_link; | |
273 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
274 | break; | |
275 | case e1000_media_type_fiber: | |
ad68076e BA |
276 | func->setup_physical_interface = |
277 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 278 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
279 | func->get_link_up_info = |
280 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
281 | break; |
282 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
283 | func->setup_physical_interface = |
284 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 285 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
286 | func->get_link_up_info = |
287 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
288 | break; |
289 | default: | |
290 | return -E1000_ERR_CONFIG; | |
291 | break; | |
292 | } | |
293 | ||
4662e82b | 294 | switch (hw->mac.type) { |
f4d2dd4c BA |
295 | case e1000_82573: |
296 | func->set_lan_id = e1000_set_lan_id_single_port; | |
297 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
298 | func->led_on = e1000e_led_on_generic; | |
a65a4a0d BA |
299 | |
300 | /* FWSM register */ | |
301 | mac->has_fwsm = true; | |
302 | /* | |
303 | * ARC supported; valid only if manageability features are | |
304 | * enabled. | |
305 | */ | |
306 | mac->arc_subsystem_valid = | |
307 | (er32(FWSM) & E1000_FWSM_MODE_MASK) | |
308 | ? true : false; | |
f4d2dd4c | 309 | break; |
4662e82b | 310 | case e1000_82574: |
8c81c9c3 | 311 | case e1000_82583: |
f4d2dd4c | 312 | func->set_lan_id = e1000_set_lan_id_single_port; |
4662e82b BA |
313 | func->check_mng_mode = e1000_check_mng_mode_82574; |
314 | func->led_on = e1000_led_on_82574; | |
315 | break; | |
316 | default: | |
317 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
318 | func->led_on = e1000e_led_on_generic; | |
a65a4a0d BA |
319 | |
320 | /* FWSM register */ | |
321 | mac->has_fwsm = true; | |
4662e82b BA |
322 | break; |
323 | } | |
324 | ||
23a2d1b2 DG |
325 | /* |
326 | * Ensure that the inter-port SWSM.SMBI lock bit is clear before | |
327 | * first NVM or PHY acess. This should be done for single-port | |
328 | * devices, and for one port only on dual-port devices so that | |
329 | * for those devices we can still use the SMBI lock to synchronize | |
330 | * inter-port accesses to the PHY & NVM. | |
331 | */ | |
332 | switch (hw->mac.type) { | |
333 | case e1000_82571: | |
334 | case e1000_82572: | |
335 | swsm2 = er32(SWSM2); | |
336 | ||
337 | if (!(swsm2 & E1000_SWSM2_LOCK)) { | |
338 | /* Only do this for the first interface on this card */ | |
339 | ew32(SWSM2, | |
340 | swsm2 | E1000_SWSM2_LOCK); | |
341 | force_clear_smbi = true; | |
342 | } else | |
343 | force_clear_smbi = false; | |
344 | break; | |
345 | default: | |
346 | force_clear_smbi = true; | |
347 | break; | |
348 | } | |
349 | ||
350 | if (force_clear_smbi) { | |
351 | /* Make sure SWSM.SMBI is clear */ | |
352 | swsm = er32(SWSM); | |
353 | if (swsm & E1000_SWSM_SMBI) { | |
354 | /* This bit should not be set on a first interface, and | |
355 | * indicates that the bootagent or EFI code has | |
356 | * improperly left this bit enabled | |
357 | */ | |
3bb99fe2 | 358 | e_dbg("Please update your 82571 Bootagent\n"); |
23a2d1b2 DG |
359 | } |
360 | ew32(SWSM, swsm & ~E1000_SWSM_SMBI); | |
361 | } | |
362 | ||
363 | /* | |
2c73e1fe | 364 | * Initialize device specific counter of SMBI acquisition |
23a2d1b2 DG |
365 | * timeouts. |
366 | */ | |
367 | hw->dev_spec.e82571.smb_counter = 0; | |
368 | ||
bc7f75fa AK |
369 | return 0; |
370 | } | |
371 | ||
69e3fd8c | 372 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
373 | { |
374 | struct e1000_hw *hw = &adapter->hw; | |
375 | static int global_quad_port_a; /* global port a indication */ | |
376 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
377 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; |
378 | s32 rc; | |
379 | ||
380 | rc = e1000_init_mac_params_82571(adapter); | |
381 | if (rc) | |
382 | return rc; | |
383 | ||
384 | rc = e1000_init_nvm_params_82571(hw); | |
385 | if (rc) | |
386 | return rc; | |
387 | ||
388 | rc = e1000_init_phy_params_82571(hw); | |
389 | if (rc) | |
390 | return rc; | |
391 | ||
392 | /* tag quad port adapters first, it's used below */ | |
393 | switch (pdev->device) { | |
394 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
395 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
396 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 397 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
398 | adapter->flags |= FLAG_IS_QUAD_PORT; |
399 | /* mark the first port */ | |
400 | if (global_quad_port_a == 0) | |
401 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
402 | /* Reset for multiple quad port adapters */ | |
403 | global_quad_port_a++; | |
404 | if (global_quad_port_a == 4) | |
405 | global_quad_port_a = 0; | |
406 | break; | |
407 | default: | |
408 | break; | |
409 | } | |
410 | ||
411 | switch (adapter->hw.mac.type) { | |
412 | case e1000_82571: | |
413 | /* these dual ports don't have WoL on port B at all */ | |
414 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
415 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
416 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
417 | (is_port_b)) | |
418 | adapter->flags &= ~FLAG_HAS_WOL; | |
419 | /* quad ports only support WoL on port A */ | |
420 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 421 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 422 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
423 | /* Does not support WoL on any port */ |
424 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
425 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa | 426 | break; |
bc7f75fa | 427 | case e1000_82573: |
6f461f6c BA |
428 | case e1000_82574: |
429 | case e1000_82583: | |
430 | /* Disable ASPM L0s due to hardware errata */ | |
431 | e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S); | |
432 | ||
bc7f75fa | 433 | if (pdev->device == E1000_DEV_ID_82573L) { |
6f461f6c BA |
434 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; |
435 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
bc7f75fa AK |
436 | } |
437 | break; | |
438 | default: | |
439 | break; | |
440 | } | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | /** | |
446 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
447 | * @hw: pointer to the HW structure | |
448 | * | |
449 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
450 | * revision in the hardware structure. | |
451 | **/ | |
452 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
453 | { | |
454 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
455 | s32 ret_val; |
456 | u16 phy_id = 0; | |
bc7f75fa AK |
457 | |
458 | switch (hw->mac.type) { | |
459 | case e1000_82571: | |
460 | case e1000_82572: | |
ad68076e BA |
461 | /* |
462 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
463 | * In this case, we cannot access the PHY until the |
464 | * configuration is done. So we explicitly set the | |
ad68076e BA |
465 | * PHY ID. |
466 | */ | |
bc7f75fa AK |
467 | phy->id = IGP01E1000_I_PHY_ID; |
468 | break; | |
469 | case e1000_82573: | |
470 | return e1000e_get_phy_id(hw); | |
471 | break; | |
4662e82b | 472 | case e1000_82574: |
8c81c9c3 | 473 | case e1000_82583: |
4662e82b BA |
474 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
475 | if (ret_val) | |
476 | return ret_val; | |
477 | ||
478 | phy->id = (u32)(phy_id << 16); | |
479 | udelay(20); | |
480 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
481 | if (ret_val) | |
482 | return ret_val; | |
483 | ||
484 | phy->id |= (u32)(phy_id); | |
485 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
486 | break; | |
bc7f75fa AK |
487 | default: |
488 | return -E1000_ERR_PHY; | |
489 | break; | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | /** | |
496 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
497 | * @hw: pointer to the HW structure | |
498 | * | |
499 | * Acquire the HW semaphore to access the PHY or NVM | |
500 | **/ | |
501 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
502 | { | |
503 | u32 swsm; | |
23a2d1b2 DG |
504 | s32 sw_timeout = hw->nvm.word_size + 1; |
505 | s32 fw_timeout = hw->nvm.word_size + 1; | |
bc7f75fa AK |
506 | s32 i = 0; |
507 | ||
23a2d1b2 DG |
508 | /* |
509 | * If we have timedout 3 times on trying to acquire | |
510 | * the inter-port SMBI semaphore, there is old code | |
511 | * operating on the other port, and it is not | |
512 | * releasing SMBI. Modify the number of times that | |
513 | * we try for the semaphore to interwork with this | |
514 | * older code. | |
515 | */ | |
516 | if (hw->dev_spec.e82571.smb_counter > 2) | |
517 | sw_timeout = 1; | |
518 | ||
519 | /* Get the SW semaphore */ | |
520 | while (i < sw_timeout) { | |
521 | swsm = er32(SWSM); | |
522 | if (!(swsm & E1000_SWSM_SMBI)) | |
523 | break; | |
524 | ||
525 | udelay(50); | |
526 | i++; | |
527 | } | |
528 | ||
529 | if (i == sw_timeout) { | |
3bb99fe2 | 530 | e_dbg("Driver can't access device - SMBI bit is set.\n"); |
23a2d1b2 DG |
531 | hw->dev_spec.e82571.smb_counter++; |
532 | } | |
bc7f75fa | 533 | /* Get the FW semaphore. */ |
23a2d1b2 | 534 | for (i = 0; i < fw_timeout; i++) { |
bc7f75fa AK |
535 | swsm = er32(SWSM); |
536 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
537 | ||
538 | /* Semaphore acquired if bit latched */ | |
539 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
540 | break; | |
541 | ||
542 | udelay(50); | |
543 | } | |
544 | ||
23a2d1b2 | 545 | if (i == fw_timeout) { |
bc7f75fa | 546 | /* Release semaphores */ |
23a2d1b2 | 547 | e1000_put_hw_semaphore_82571(hw); |
3bb99fe2 | 548 | e_dbg("Driver can't access the NVM\n"); |
bc7f75fa AK |
549 | return -E1000_ERR_NVM; |
550 | } | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | /** | |
556 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
557 | * @hw: pointer to the HW structure | |
558 | * | |
559 | * Release hardware semaphore used to access the PHY or NVM | |
560 | **/ | |
561 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
562 | { | |
563 | u32 swsm; | |
564 | ||
565 | swsm = er32(SWSM); | |
23a2d1b2 | 566 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
bc7f75fa AK |
567 | ew32(SWSM, swsm); |
568 | } | |
1b98c2bb BA |
569 | /** |
570 | * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore | |
571 | * @hw: pointer to the HW structure | |
572 | * | |
573 | * Acquire the HW semaphore during reset. | |
574 | * | |
575 | **/ | |
576 | static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw) | |
577 | { | |
578 | u32 extcnf_ctrl; | |
579 | s32 ret_val = 0; | |
580 | s32 i = 0; | |
581 | ||
582 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
583 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
584 | do { | |
585 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
586 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
587 | ||
588 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
589 | break; | |
590 | ||
591 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
592 | ||
593 | msleep(2); | |
594 | i++; | |
595 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
596 | ||
597 | if (i == MDIO_OWNERSHIP_TIMEOUT) { | |
598 | /* Release semaphores */ | |
599 | e1000_put_hw_semaphore_82573(hw); | |
600 | e_dbg("Driver can't access the PHY\n"); | |
601 | ret_val = -E1000_ERR_PHY; | |
602 | goto out; | |
603 | } | |
604 | ||
605 | out: | |
606 | return ret_val; | |
607 | } | |
608 | ||
609 | /** | |
610 | * e1000_put_hw_semaphore_82573 - Release hardware semaphore | |
611 | * @hw: pointer to the HW structure | |
612 | * | |
613 | * Release hardware semaphore used during reset. | |
614 | * | |
615 | **/ | |
616 | static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw) | |
617 | { | |
618 | u32 extcnf_ctrl; | |
619 | ||
620 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
621 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
622 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
623 | } | |
624 | ||
625 | static DEFINE_MUTEX(swflag_mutex); | |
626 | ||
627 | /** | |
628 | * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore | |
629 | * @hw: pointer to the HW structure | |
630 | * | |
631 | * Acquire the HW semaphore to access the PHY or NVM. | |
632 | * | |
633 | **/ | |
634 | static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw) | |
635 | { | |
636 | s32 ret_val; | |
637 | ||
638 | mutex_lock(&swflag_mutex); | |
639 | ret_val = e1000_get_hw_semaphore_82573(hw); | |
640 | if (ret_val) | |
641 | mutex_unlock(&swflag_mutex); | |
642 | return ret_val; | |
643 | } | |
644 | ||
645 | /** | |
646 | * e1000_put_hw_semaphore_82574 - Release hardware semaphore | |
647 | * @hw: pointer to the HW structure | |
648 | * | |
649 | * Release hardware semaphore used to access the PHY or NVM | |
650 | * | |
651 | **/ | |
652 | static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw) | |
653 | { | |
654 | e1000_put_hw_semaphore_82573(hw); | |
655 | mutex_unlock(&swflag_mutex); | |
656 | } | |
bc7f75fa AK |
657 | |
658 | /** | |
659 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
660 | * @hw: pointer to the HW structure | |
661 | * | |
662 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
663 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
664 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
665 | * hardware semaphore. | |
666 | **/ | |
667 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
668 | { | |
669 | s32 ret_val; | |
670 | ||
671 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
672 | if (ret_val) | |
673 | return ret_val; | |
674 | ||
8c81c9c3 AD |
675 | switch (hw->mac.type) { |
676 | case e1000_82573: | |
8c81c9c3 AD |
677 | break; |
678 | default: | |
bc7f75fa | 679 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
680 | break; |
681 | } | |
bc7f75fa AK |
682 | |
683 | if (ret_val) | |
684 | e1000_put_hw_semaphore_82571(hw); | |
685 | ||
686 | return ret_val; | |
687 | } | |
688 | ||
689 | /** | |
690 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
691 | * @hw: pointer to the HW structure | |
692 | * | |
693 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
694 | **/ | |
695 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
696 | { | |
697 | e1000e_release_nvm(hw); | |
698 | e1000_put_hw_semaphore_82571(hw); | |
699 | } | |
700 | ||
701 | /** | |
702 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
703 | * @hw: pointer to the HW structure | |
704 | * @offset: offset within the EEPROM to be written to | |
705 | * @words: number of words to write | |
706 | * @data: 16 bit word(s) to be written to the EEPROM | |
707 | * | |
708 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
709 | * | |
710 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 711 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
712 | **/ |
713 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
714 | u16 *data) | |
715 | { | |
716 | s32 ret_val; | |
717 | ||
718 | switch (hw->mac.type) { | |
719 | case e1000_82573: | |
4662e82b | 720 | case e1000_82574: |
8c81c9c3 | 721 | case e1000_82583: |
bc7f75fa AK |
722 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
723 | break; | |
724 | case e1000_82571: | |
725 | case e1000_82572: | |
726 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
727 | break; | |
728 | default: | |
729 | ret_val = -E1000_ERR_NVM; | |
730 | break; | |
731 | } | |
732 | ||
733 | return ret_val; | |
734 | } | |
735 | ||
736 | /** | |
737 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
738 | * @hw: pointer to the HW structure | |
739 | * | |
740 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
741 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
742 | * value to the EEPROM. | |
743 | **/ | |
744 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
745 | { | |
746 | u32 eecd; | |
747 | s32 ret_val; | |
748 | u16 i; | |
749 | ||
750 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
751 | if (ret_val) | |
752 | return ret_val; | |
753 | ||
ad68076e BA |
754 | /* |
755 | * If our nvm is an EEPROM, then we're done | |
756 | * otherwise, commit the checksum to the flash NVM. | |
757 | */ | |
bc7f75fa AK |
758 | if (hw->nvm.type != e1000_nvm_flash_hw) |
759 | return ret_val; | |
760 | ||
761 | /* Check for pending operations. */ | |
762 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
763 | msleep(1); | |
764 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
765 | break; | |
766 | } | |
767 | ||
768 | if (i == E1000_FLASH_UPDATES) | |
769 | return -E1000_ERR_NVM; | |
770 | ||
771 | /* Reset the firmware if using STM opcode. */ | |
772 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
773 | /* |
774 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
775 | * in two write cycles. |
776 | */ | |
777 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
778 | e1e_flush(); | |
779 | ew32(HICR, E1000_HICR_FW_RESET); | |
780 | } | |
781 | ||
782 | /* Commit the write to flash */ | |
783 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
784 | ew32(EECD, eecd); | |
785 | ||
786 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
787 | msleep(1); | |
788 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
789 | break; | |
790 | } | |
791 | ||
792 | if (i == E1000_FLASH_UPDATES) | |
793 | return -E1000_ERR_NVM; | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
798 | /** | |
799 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
800 | * @hw: pointer to the HW structure | |
801 | * | |
802 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
803 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
804 | **/ | |
805 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
806 | { | |
807 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
808 | e1000_fix_nvm_checksum_82571(hw); | |
809 | ||
810 | return e1000e_validate_nvm_checksum_generic(hw); | |
811 | } | |
812 | ||
813 | /** | |
814 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
815 | * @hw: pointer to the HW structure | |
816 | * @offset: offset within the EEPROM to be written to | |
817 | * @words: number of words to write | |
818 | * @data: 16 bit word(s) to be written to the EEPROM | |
819 | * | |
820 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
821 | * command has completed before trying to write the next word. After write | |
822 | * poll for completion. | |
823 | * | |
824 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 825 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
826 | **/ |
827 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
828 | u16 words, u16 *data) | |
829 | { | |
830 | struct e1000_nvm_info *nvm = &hw->nvm; | |
a708dd88 | 831 | u32 i, eewr = 0; |
bc7f75fa AK |
832 | s32 ret_val = 0; |
833 | ||
ad68076e BA |
834 | /* |
835 | * A check for invalid values: offset too large, too many words, | |
836 | * and not enough words. | |
837 | */ | |
bc7f75fa AK |
838 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
839 | (words == 0)) { | |
3bb99fe2 | 840 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
841 | return -E1000_ERR_NVM; |
842 | } | |
843 | ||
844 | for (i = 0; i < words; i++) { | |
845 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
846 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
847 | E1000_NVM_RW_REG_START; | |
848 | ||
849 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
850 | if (ret_val) | |
851 | break; | |
852 | ||
853 | ew32(EEWR, eewr); | |
854 | ||
855 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
856 | if (ret_val) | |
857 | break; | |
858 | } | |
859 | ||
860 | return ret_val; | |
861 | } | |
862 | ||
863 | /** | |
864 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
865 | * @hw: pointer to the HW structure | |
866 | * | |
867 | * Reads the management control register for the config done bit to be set. | |
868 | **/ | |
869 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
870 | { | |
871 | s32 timeout = PHY_CFG_TIMEOUT; | |
872 | ||
873 | while (timeout) { | |
874 | if (er32(EEMNGCTL) & | |
875 | E1000_NVM_CFG_DONE_PORT_0) | |
876 | break; | |
877 | msleep(1); | |
878 | timeout--; | |
879 | } | |
880 | if (!timeout) { | |
3bb99fe2 | 881 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
882 | return -E1000_ERR_RESET; |
883 | } | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
888 | /** | |
889 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
890 | * @hw: pointer to the HW structure | |
564ea9bb | 891 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
892 | * |
893 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
894 | * this function also disables smart speed and vice versa. LPLU will not be | |
895 | * activated unless the device autonegotiation advertisement meets standards | |
896 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
897 | * pointer entry point only called by PHY setup routines. | |
898 | **/ | |
899 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
900 | { | |
901 | struct e1000_phy_info *phy = &hw->phy; | |
902 | s32 ret_val; | |
903 | u16 data; | |
904 | ||
905 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
906 | if (ret_val) | |
907 | return ret_val; | |
908 | ||
909 | if (active) { | |
910 | data |= IGP02E1000_PM_D0_LPLU; | |
911 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
912 | if (ret_val) | |
913 | return ret_val; | |
914 | ||
915 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
916 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
917 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
918 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
919 | if (ret_val) | |
920 | return ret_val; | |
921 | } else { | |
922 | data &= ~IGP02E1000_PM_D0_LPLU; | |
923 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
924 | /* |
925 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
926 | * during Dx states where the power conservation is most |
927 | * important. During driver activity we should enable | |
ad68076e BA |
928 | * SmartSpeed, so performance is maintained. |
929 | */ | |
bc7f75fa AK |
930 | if (phy->smart_speed == e1000_smart_speed_on) { |
931 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 932 | &data); |
bc7f75fa AK |
933 | if (ret_val) |
934 | return ret_val; | |
935 | ||
936 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
937 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 938 | data); |
bc7f75fa AK |
939 | if (ret_val) |
940 | return ret_val; | |
941 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
942 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 943 | &data); |
bc7f75fa AK |
944 | if (ret_val) |
945 | return ret_val; | |
946 | ||
947 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
948 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 949 | data); |
bc7f75fa AK |
950 | if (ret_val) |
951 | return ret_val; | |
952 | } | |
953 | } | |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
958 | /** | |
959 | * e1000_reset_hw_82571 - Reset hardware | |
960 | * @hw: pointer to the HW structure | |
961 | * | |
fe401674 | 962 | * This resets the hardware into a known state. |
bc7f75fa AK |
963 | **/ |
964 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
965 | { | |
dd93f95e | 966 | u32 ctrl, ctrl_ext; |
bc7f75fa | 967 | s32 ret_val; |
bc7f75fa | 968 | |
ad68076e BA |
969 | /* |
970 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
971 | * on the last TLP read/write transaction when MAC is reset. |
972 | */ | |
973 | ret_val = e1000e_disable_pcie_master(hw); | |
974 | if (ret_val) | |
3bb99fe2 | 975 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 976 | |
3bb99fe2 | 977 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
978 | ew32(IMC, 0xffffffff); |
979 | ||
980 | ew32(RCTL, 0); | |
981 | ew32(TCTL, E1000_TCTL_PSP); | |
982 | e1e_flush(); | |
983 | ||
984 | msleep(10); | |
985 | ||
ad68076e BA |
986 | /* |
987 | * Must acquire the MDIO ownership before MAC reset. | |
988 | * Ownership defaults to firmware after a reset. | |
989 | */ | |
8c81c9c3 AD |
990 | switch (hw->mac.type) { |
991 | case e1000_82573: | |
1b98c2bb BA |
992 | ret_val = e1000_get_hw_semaphore_82573(hw); |
993 | break; | |
8c81c9c3 AD |
994 | case e1000_82574: |
995 | case e1000_82583: | |
1b98c2bb | 996 | ret_val = e1000_get_hw_semaphore_82574(hw); |
8c81c9c3 AD |
997 | break; |
998 | default: | |
999 | break; | |
bc7f75fa | 1000 | } |
1b98c2bb BA |
1001 | if (ret_val) |
1002 | e_dbg("Cannot acquire MDIO ownership\n"); | |
bc7f75fa AK |
1003 | |
1004 | ctrl = er32(CTRL); | |
1005 | ||
3bb99fe2 | 1006 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa AK |
1007 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
1008 | ||
1b98c2bb BA |
1009 | /* Must release MDIO ownership and mutex after MAC reset. */ |
1010 | switch (hw->mac.type) { | |
1011 | case e1000_82574: | |
1012 | case e1000_82583: | |
1013 | e1000_put_hw_semaphore_82574(hw); | |
1014 | break; | |
1015 | default: | |
1016 | break; | |
1017 | } | |
1018 | ||
bc7f75fa AK |
1019 | if (hw->nvm.type == e1000_nvm_flash_hw) { |
1020 | udelay(10); | |
1021 | ctrl_ext = er32(CTRL_EXT); | |
1022 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
1023 | ew32(CTRL_EXT, ctrl_ext); | |
1024 | e1e_flush(); | |
1025 | } | |
1026 | ||
1027 | ret_val = e1000e_get_auto_rd_done(hw); | |
1028 | if (ret_val) | |
1029 | /* We don't want to continue accessing MAC registers. */ | |
1030 | return ret_val; | |
1031 | ||
ad68076e BA |
1032 | /* |
1033 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
1034 | * Need to wait for Phy configuration completion before accessing |
1035 | * NVM and Phy. | |
1036 | */ | |
8c81c9c3 AD |
1037 | |
1038 | switch (hw->mac.type) { | |
1039 | case e1000_82573: | |
1040 | case e1000_82574: | |
1041 | case e1000_82583: | |
bc7f75fa | 1042 | msleep(25); |
8c81c9c3 AD |
1043 | break; |
1044 | default: | |
1045 | break; | |
1046 | } | |
bc7f75fa AK |
1047 | |
1048 | /* Clear any pending interrupt events. */ | |
1049 | ew32(IMC, 0xffffffff); | |
dd93f95e | 1050 | er32(ICR); |
bc7f75fa | 1051 | |
1aef70ef BA |
1052 | if (hw->mac.type == e1000_82571) { |
1053 | /* Install any alternate MAC address into RAR0 */ | |
1054 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1055 | if (ret_val) | |
1056 | return ret_val; | |
608f8a0d | 1057 | |
1aef70ef BA |
1058 | e1000e_set_laa_state_82571(hw, true); |
1059 | } | |
93ca1610 | 1060 | |
c9523379 | 1061 | /* Reinitialize the 82571 serdes link state machine */ |
1062 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
1063 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
1064 | ||
bc7f75fa AK |
1065 | return 0; |
1066 | } | |
1067 | ||
1068 | /** | |
1069 | * e1000_init_hw_82571 - Initialize hardware | |
1070 | * @hw: pointer to the HW structure | |
1071 | * | |
1072 | * This inits the hardware readying it for operation. | |
1073 | **/ | |
1074 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
1075 | { | |
1076 | struct e1000_mac_info *mac = &hw->mac; | |
1077 | u32 reg_data; | |
1078 | s32 ret_val; | |
a708dd88 | 1079 | u16 i, rar_count = mac->rar_entry_count; |
bc7f75fa AK |
1080 | |
1081 | e1000_initialize_hw_bits_82571(hw); | |
1082 | ||
1083 | /* Initialize identification LED */ | |
1084 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 1085 | if (ret_val) |
3bb99fe2 | 1086 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 1087 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
1088 | |
1089 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 1090 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 1091 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
1092 | |
1093 | /* Setup the receive address. */ | |
ad68076e BA |
1094 | /* |
1095 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
1096 | * 82571, we must reserve a RAR for it to work around an issue where |
1097 | * resetting one port will reload the MAC on the other port. | |
1098 | */ | |
1099 | if (e1000e_get_laa_state_82571(hw)) | |
1100 | rar_count--; | |
1101 | e1000e_init_rx_addrs(hw, rar_count); | |
1102 | ||
1103 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 1104 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
1105 | for (i = 0; i < mac->mta_reg_count; i++) |
1106 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
1107 | ||
1108 | /* Setup link and flow control */ | |
1109 | ret_val = e1000_setup_link_82571(hw); | |
1110 | ||
1111 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 1112 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
1113 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1114 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1115 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1116 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
1117 | |
1118 | /* ...for both queues. */ | |
8c81c9c3 AD |
1119 | switch (mac->type) { |
1120 | case e1000_82573: | |
a65a4a0d BA |
1121 | e1000e_enable_tx_pkt_filtering(hw); |
1122 | /* fall through */ | |
8c81c9c3 AD |
1123 | case e1000_82574: |
1124 | case e1000_82583: | |
8c81c9c3 AD |
1125 | reg_data = er32(GCR); |
1126 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
1127 | ew32(GCR, reg_data); | |
1128 | break; | |
1129 | default: | |
e9ec2c0f | 1130 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
1131 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
1132 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
1133 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 1134 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 1135 | break; |
bc7f75fa AK |
1136 | } |
1137 | ||
ad68076e BA |
1138 | /* |
1139 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
1140 | * important that we do this after we have tried to establish link |
1141 | * because the symbol error count will increment wildly if there | |
1142 | * is no link. | |
1143 | */ | |
1144 | e1000_clear_hw_cntrs_82571(hw); | |
1145 | ||
1146 | return ret_val; | |
1147 | } | |
1148 | ||
1149 | /** | |
1150 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
1151 | * @hw: pointer to the HW structure | |
1152 | * | |
1153 | * Initializes required hardware-dependent bits needed for normal operation. | |
1154 | **/ | |
1155 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
1156 | { | |
1157 | u32 reg; | |
1158 | ||
1159 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 1160 | reg = er32(TXDCTL(0)); |
bc7f75fa | 1161 | reg |= (1 << 22); |
e9ec2c0f | 1162 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
1163 | |
1164 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 1165 | reg = er32(TXDCTL(1)); |
bc7f75fa | 1166 | reg |= (1 << 22); |
e9ec2c0f | 1167 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
1168 | |
1169 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 1170 | reg = er32(TARC(0)); |
bc7f75fa AK |
1171 | reg &= ~(0xF << 27); /* 30:27 */ |
1172 | switch (hw->mac.type) { | |
1173 | case e1000_82571: | |
1174 | case e1000_82572: | |
1175 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
1176 | break; | |
1177 | default: | |
1178 | break; | |
1179 | } | |
e9ec2c0f | 1180 | ew32(TARC(0), reg); |
bc7f75fa AK |
1181 | |
1182 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 1183 | reg = er32(TARC(1)); |
bc7f75fa AK |
1184 | switch (hw->mac.type) { |
1185 | case e1000_82571: | |
1186 | case e1000_82572: | |
1187 | reg &= ~((1 << 29) | (1 << 30)); | |
1188 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
1189 | if (er32(TCTL) & E1000_TCTL_MULR) | |
1190 | reg &= ~(1 << 28); | |
1191 | else | |
1192 | reg |= (1 << 28); | |
e9ec2c0f | 1193 | ew32(TARC(1), reg); |
bc7f75fa AK |
1194 | break; |
1195 | default: | |
1196 | break; | |
1197 | } | |
1198 | ||
1199 | /* Device Control */ | |
8c81c9c3 AD |
1200 | switch (hw->mac.type) { |
1201 | case e1000_82573: | |
1202 | case e1000_82574: | |
1203 | case e1000_82583: | |
bc7f75fa AK |
1204 | reg = er32(CTRL); |
1205 | reg &= ~(1 << 29); | |
1206 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1207 | break; |
1208 | default: | |
1209 | break; | |
bc7f75fa AK |
1210 | } |
1211 | ||
1212 | /* Extended Device Control */ | |
8c81c9c3 AD |
1213 | switch (hw->mac.type) { |
1214 | case e1000_82573: | |
1215 | case e1000_82574: | |
1216 | case e1000_82583: | |
bc7f75fa AK |
1217 | reg = er32(CTRL_EXT); |
1218 | reg &= ~(1 << 23); | |
1219 | reg |= (1 << 22); | |
1220 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1221 | break; |
1222 | default: | |
1223 | break; | |
bc7f75fa | 1224 | } |
4662e82b | 1225 | |
6ea7ae1d AD |
1226 | if (hw->mac.type == e1000_82571) { |
1227 | reg = er32(PBA_ECC); | |
1228 | reg |= E1000_PBA_ECC_CORR_EN; | |
1229 | ew32(PBA_ECC, reg); | |
1230 | } | |
5df3f0ea | 1231 | /* |
1232 | * Workaround for hardware errata. | |
1233 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1234 | */ | |
1235 | ||
1236 | if ((hw->mac.type == e1000_82571) || | |
1237 | (hw->mac.type == e1000_82572)) { | |
1238 | reg = er32(CTRL_EXT); | |
1239 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1240 | ew32(CTRL_EXT, reg); | |
1241 | } | |
1242 | ||
6ea7ae1d | 1243 | |
78272bba | 1244 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1245 | switch (hw->mac.type) { |
1246 | case e1000_82574: | |
1247 | case e1000_82583: | |
4662e82b BA |
1248 | reg = er32(GCR); |
1249 | reg |= (1 << 22); | |
1250 | ew32(GCR, reg); | |
78272bba | 1251 | |
84efb7b9 BA |
1252 | /* |
1253 | * Workaround for hardware errata. | |
1254 | * apply workaround for hardware errata documented in errata | |
1255 | * docs Fixes issue where some error prone or unreliable PCIe | |
1256 | * completions are occurring, particularly with ASPM enabled. | |
1257 | * Without fix, issue can cause tx timeouts. | |
1258 | */ | |
78272bba JB |
1259 | reg = er32(GCR2); |
1260 | reg |= 1; | |
1261 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1262 | break; |
1263 | default: | |
1264 | break; | |
4662e82b | 1265 | } |
bc7f75fa AK |
1266 | } |
1267 | ||
1268 | /** | |
caaddaf8 | 1269 | * e1000_clear_vfta_82571 - Clear VLAN filter table |
bc7f75fa AK |
1270 | * @hw: pointer to the HW structure |
1271 | * | |
1272 | * Clears the register array which contains the VLAN filter table by | |
1273 | * setting all the values to 0. | |
1274 | **/ | |
caaddaf8 | 1275 | static void e1000_clear_vfta_82571(struct e1000_hw *hw) |
bc7f75fa AK |
1276 | { |
1277 | u32 offset; | |
1278 | u32 vfta_value = 0; | |
1279 | u32 vfta_offset = 0; | |
1280 | u32 vfta_bit_in_reg = 0; | |
1281 | ||
8c81c9c3 AD |
1282 | switch (hw->mac.type) { |
1283 | case e1000_82573: | |
1284 | case e1000_82574: | |
1285 | case e1000_82583: | |
bc7f75fa | 1286 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1287 | /* |
1288 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1289 | * a single VLAN ID. The following operations |
1290 | * determine which 32b entry (i.e. offset) into the | |
1291 | * array we want to set the VLAN ID (i.e. bit) of | |
1292 | * the manageability unit. | |
1293 | */ | |
1294 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1295 | E1000_VFTA_ENTRY_SHIFT) & | |
1296 | E1000_VFTA_ENTRY_MASK; | |
1297 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1298 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1299 | } | |
8c81c9c3 AD |
1300 | break; |
1301 | default: | |
1302 | break; | |
bc7f75fa AK |
1303 | } |
1304 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1305 | /* |
1306 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1307 | * manageability VLAN ID, then clear all bits except that of |
1308 | * the manageability unit. | |
1309 | */ | |
1310 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1311 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1312 | e1e_flush(); | |
1313 | } | |
1314 | } | |
1315 | ||
4662e82b BA |
1316 | /** |
1317 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1318 | * @hw: pointer to the HW structure | |
1319 | * | |
1320 | * Reads the NVM Initialization Control Word 2 and returns true | |
1321 | * (>0) if any manageability is enabled, else false (0). | |
1322 | **/ | |
1323 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1324 | { | |
1325 | u16 data; | |
1326 | ||
1327 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1328 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1329 | } | |
1330 | ||
1331 | /** | |
1332 | * e1000_led_on_82574 - Turn LED on | |
1333 | * @hw: pointer to the HW structure | |
1334 | * | |
1335 | * Turn LED on. | |
1336 | **/ | |
1337 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1338 | { | |
1339 | u32 ctrl; | |
1340 | u32 i; | |
1341 | ||
1342 | ctrl = hw->mac.ledctl_mode2; | |
1343 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1344 | /* | |
1345 | * If no link, then turn LED on by setting the invert bit | |
1346 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1347 | */ | |
1348 | for (i = 0; i < 4; i++) | |
1349 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1350 | E1000_LEDCTL_MODE_LED_ON) | |
1351 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1352 | } | |
1353 | ew32(LEDCTL, ctrl); | |
1354 | ||
1355 | return 0; | |
1356 | } | |
1357 | ||
ff10e13c CW |
1358 | /** |
1359 | * e1000_check_phy_82574 - check 82574 phy hung state | |
1360 | * @hw: pointer to the HW structure | |
1361 | * | |
1362 | * Returns whether phy is hung or not | |
1363 | **/ | |
1364 | bool e1000_check_phy_82574(struct e1000_hw *hw) | |
1365 | { | |
1366 | u16 status_1kbt = 0; | |
1367 | u16 receive_errors = 0; | |
1368 | bool phy_hung = false; | |
1369 | s32 ret_val = 0; | |
1370 | ||
1371 | /* | |
1372 | * Read PHY Receive Error counter first, if its is max - all F's then | |
1373 | * read the Base1000T status register If both are max then PHY is hung. | |
1374 | */ | |
1375 | ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors); | |
1376 | ||
1377 | if (ret_val) | |
1378 | goto out; | |
1379 | if (receive_errors == E1000_RECEIVE_ERROR_MAX) { | |
1380 | ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt); | |
1381 | if (ret_val) | |
1382 | goto out; | |
1383 | if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) == | |
1384 | E1000_IDLE_ERROR_COUNT_MASK) | |
1385 | phy_hung = true; | |
1386 | } | |
1387 | out: | |
1388 | return phy_hung; | |
1389 | } | |
1390 | ||
bc7f75fa AK |
1391 | /** |
1392 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1393 | * @hw: pointer to the HW structure | |
1394 | * | |
1395 | * Determines which flow control settings to use, then configures flow | |
1396 | * control. Calls the appropriate media-specific link configuration | |
1397 | * function. Assuming the adapter has a valid link partner, a valid link | |
1398 | * should be established. Assumes the hardware has previously been reset | |
1399 | * and the transmitter and receiver are not enabled. | |
1400 | **/ | |
1401 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1402 | { | |
ad68076e BA |
1403 | /* |
1404 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1405 | * the default flow control setting, so we explicitly |
1406 | * set it to full. | |
1407 | */ | |
8c81c9c3 AD |
1408 | switch (hw->mac.type) { |
1409 | case e1000_82573: | |
1410 | case e1000_82574: | |
1411 | case e1000_82583: | |
1412 | if (hw->fc.requested_mode == e1000_fc_default) | |
1413 | hw->fc.requested_mode = e1000_fc_full; | |
1414 | break; | |
1415 | default: | |
1416 | break; | |
1417 | } | |
bc7f75fa AK |
1418 | |
1419 | return e1000e_setup_link(hw); | |
1420 | } | |
1421 | ||
1422 | /** | |
1423 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1424 | * @hw: pointer to the HW structure | |
1425 | * | |
1426 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1427 | * for link, once link is established calls to configure collision distance | |
1428 | * and flow control are called. | |
1429 | **/ | |
1430 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1431 | { | |
1432 | u32 ctrl; | |
bc7f75fa AK |
1433 | s32 ret_val; |
1434 | ||
1435 | ctrl = er32(CTRL); | |
1436 | ctrl |= E1000_CTRL_SLU; | |
1437 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1438 | ew32(CTRL, ctrl); | |
1439 | ||
1440 | switch (hw->phy.type) { | |
1441 | case e1000_phy_m88: | |
4662e82b | 1442 | case e1000_phy_bm: |
bc7f75fa AK |
1443 | ret_val = e1000e_copper_link_setup_m88(hw); |
1444 | break; | |
1445 | case e1000_phy_igp_2: | |
1446 | ret_val = e1000e_copper_link_setup_igp(hw); | |
bc7f75fa AK |
1447 | break; |
1448 | default: | |
1449 | return -E1000_ERR_PHY; | |
1450 | break; | |
1451 | } | |
1452 | ||
1453 | if (ret_val) | |
1454 | return ret_val; | |
1455 | ||
1456 | ret_val = e1000e_setup_copper_link(hw); | |
1457 | ||
1458 | return ret_val; | |
1459 | } | |
1460 | ||
1461 | /** | |
1462 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1463 | * @hw: pointer to the HW structure | |
1464 | * | |
1465 | * Configures collision distance and flow control for fiber and serdes links. | |
1466 | * Upon successful setup, poll for link. | |
1467 | **/ | |
1468 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1469 | { | |
1470 | switch (hw->mac.type) { | |
1471 | case e1000_82571: | |
1472 | case e1000_82572: | |
ad68076e BA |
1473 | /* |
1474 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1475 | * of reset to take the adapter out of that mode. So we |
1476 | * have to explicitly take the adapter out of loopback | |
489815ce | 1477 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1478 | * if another tool failed to take it out of loopback mode. |
1479 | */ | |
ad68076e | 1480 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1481 | break; |
1482 | default: | |
1483 | break; | |
1484 | } | |
1485 | ||
1486 | return e1000e_setup_fiber_serdes_link(hw); | |
1487 | } | |
1488 | ||
c9523379 | 1489 | /** |
1490 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1491 | * @hw: pointer to the HW structure | |
1492 | * | |
1a40d5c1 BA |
1493 | * Reports the link state as up or down. |
1494 | * | |
1495 | * If autonegotiation is supported by the link partner, the link state is | |
1496 | * determined by the result of autonegotiation. This is the most likely case. | |
1497 | * If autonegotiation is not supported by the link partner, and the link | |
1498 | * has a valid signal, force the link up. | |
1499 | * | |
1500 | * The link state is represented internally here by 4 states: | |
1501 | * | |
1502 | * 1) down | |
1503 | * 2) autoneg_progress | |
3ad2f3fb | 1504 | * 3) autoneg_complete (the link successfully autonegotiated) |
1a40d5c1 BA |
1505 | * 4) forced_up (the link has been forced up, it did not autonegotiate) |
1506 | * | |
c9523379 | 1507 | **/ |
f6370117 | 1508 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1509 | { |
1510 | struct e1000_mac_info *mac = &hw->mac; | |
1511 | u32 rxcw; | |
1512 | u32 ctrl; | |
1513 | u32 status; | |
d9c76f99 BA |
1514 | u32 txcw; |
1515 | u32 i; | |
c9523379 | 1516 | s32 ret_val = 0; |
1517 | ||
1518 | ctrl = er32(CTRL); | |
1519 | status = er32(STATUS); | |
1520 | rxcw = er32(RXCW); | |
1521 | ||
1522 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1523 | ||
1524 | /* Receiver is synchronized with no invalid bits. */ | |
1525 | switch (mac->serdes_link_state) { | |
1526 | case e1000_serdes_link_autoneg_complete: | |
1527 | if (!(status & E1000_STATUS_LU)) { | |
1528 | /* | |
1529 | * We have lost link, retry autoneg before | |
1530 | * reporting link failure | |
1531 | */ | |
1532 | mac->serdes_link_state = | |
1533 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1534 | mac->serdes_has_link = false; |
3bb99fe2 | 1535 | e_dbg("AN_UP -> AN_PROG\n"); |
a82a14f4 BA |
1536 | } else { |
1537 | mac->serdes_has_link = true; | |
c9523379 | 1538 | } |
a82a14f4 | 1539 | break; |
c9523379 | 1540 | |
1541 | case e1000_serdes_link_forced_up: | |
1542 | /* | |
1543 | * If we are receiving /C/ ordered sets, re-enable | |
1544 | * auto-negotiation in the TXCW register and disable | |
1545 | * forced link in the Device Control register in an | |
1546 | * attempt to auto-negotiate with our link partner. | |
d478eb44 BA |
1547 | * If the partner code word is null, stop forcing |
1548 | * and restart auto negotiation. | |
c9523379 | 1549 | */ |
d478eb44 | 1550 | if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW)) { |
c9523379 | 1551 | /* Enable autoneg, and unforce link up */ |
1552 | ew32(TXCW, mac->txcw); | |
1a40d5c1 | 1553 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1554 | mac->serdes_link_state = |
1555 | e1000_serdes_link_autoneg_progress; | |
1a40d5c1 | 1556 | mac->serdes_has_link = false; |
3bb99fe2 | 1557 | e_dbg("FORCED_UP -> AN_PROG\n"); |
a82a14f4 BA |
1558 | } else { |
1559 | mac->serdes_has_link = true; | |
c9523379 | 1560 | } |
1561 | break; | |
1562 | ||
1563 | case e1000_serdes_link_autoneg_progress: | |
1a40d5c1 BA |
1564 | if (rxcw & E1000_RXCW_C) { |
1565 | /* | |
1566 | * We received /C/ ordered sets, meaning the | |
1567 | * link partner has autonegotiated, and we can | |
1568 | * trust the Link Up (LU) status bit. | |
1569 | */ | |
1570 | if (status & E1000_STATUS_LU) { | |
1571 | mac->serdes_link_state = | |
1572 | e1000_serdes_link_autoneg_complete; | |
1573 | e_dbg("AN_PROG -> AN_UP\n"); | |
1574 | mac->serdes_has_link = true; | |
1575 | } else { | |
1576 | /* Autoneg completed, but failed. */ | |
1577 | mac->serdes_link_state = | |
1578 | e1000_serdes_link_down; | |
1579 | e_dbg("AN_PROG -> DOWN\n"); | |
1580 | } | |
c9523379 | 1581 | } else { |
1582 | /* | |
1a40d5c1 BA |
1583 | * The link partner did not autoneg. |
1584 | * Force link up and full duplex, and change | |
1585 | * state to forced. | |
c9523379 | 1586 | */ |
1a40d5c1 | 1587 | ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); |
c9523379 | 1588 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
1589 | ew32(CTRL, ctrl); | |
1590 | ||
1591 | /* Configure Flow Control after link up. */ | |
1a40d5c1 | 1592 | ret_val = e1000e_config_fc_after_link_up(hw); |
c9523379 | 1593 | if (ret_val) { |
3bb99fe2 | 1594 | e_dbg("Error config flow control\n"); |
c9523379 | 1595 | break; |
1596 | } | |
1597 | mac->serdes_link_state = | |
1598 | e1000_serdes_link_forced_up; | |
1a40d5c1 | 1599 | mac->serdes_has_link = true; |
3bb99fe2 | 1600 | e_dbg("AN_PROG -> FORCED_UP\n"); |
c9523379 | 1601 | } |
c9523379 | 1602 | break; |
1603 | ||
1604 | case e1000_serdes_link_down: | |
1605 | default: | |
1a40d5c1 BA |
1606 | /* |
1607 | * The link was down but the receiver has now gained | |
c9523379 | 1608 | * valid sync, so lets see if we can bring the link |
1a40d5c1 BA |
1609 | * up. |
1610 | */ | |
c9523379 | 1611 | ew32(TXCW, mac->txcw); |
1a40d5c1 | 1612 | ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); |
c9523379 | 1613 | mac->serdes_link_state = |
1614 | e1000_serdes_link_autoneg_progress; | |
a82a14f4 | 1615 | mac->serdes_has_link = false; |
3bb99fe2 | 1616 | e_dbg("DOWN -> AN_PROG\n"); |
c9523379 | 1617 | break; |
1618 | } | |
1619 | } else { | |
1620 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1621 | mac->serdes_has_link = false; | |
1622 | mac->serdes_link_state = e1000_serdes_link_down; | |
3bb99fe2 | 1623 | e_dbg("ANYSTATE -> DOWN\n"); |
c9523379 | 1624 | } else { |
1625 | /* | |
d9c76f99 BA |
1626 | * Check several times, if Sync and Config |
1627 | * both are consistently 1 then simply ignore | |
1628 | * the Invalid bit and restart Autoneg | |
c9523379 | 1629 | */ |
d9c76f99 BA |
1630 | for (i = 0; i < AN_RETRY_COUNT; i++) { |
1631 | udelay(10); | |
1632 | rxcw = er32(RXCW); | |
1633 | if ((rxcw & E1000_RXCW_IV) && | |
1634 | !((rxcw & E1000_RXCW_SYNCH) && | |
1635 | (rxcw & E1000_RXCW_C))) { | |
1636 | mac->serdes_has_link = false; | |
1637 | mac->serdes_link_state = | |
1638 | e1000_serdes_link_down; | |
1639 | e_dbg("ANYSTATE -> DOWN\n"); | |
1640 | break; | |
1641 | } | |
1642 | } | |
1643 | ||
1644 | if (i == AN_RETRY_COUNT) { | |
1645 | txcw = er32(TXCW); | |
1646 | txcw |= E1000_TXCW_ANE; | |
1647 | ew32(TXCW, txcw); | |
1648 | mac->serdes_link_state = | |
1649 | e1000_serdes_link_autoneg_progress; | |
c9523379 | 1650 | mac->serdes_has_link = false; |
d9c76f99 | 1651 | e_dbg("ANYSTATE -> AN_PROG\n"); |
c9523379 | 1652 | } |
1653 | } | |
1654 | } | |
1655 | ||
1656 | return ret_val; | |
1657 | } | |
1658 | ||
bc7f75fa AK |
1659 | /** |
1660 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1661 | * @hw: pointer to the HW structure | |
1662 | * @data: pointer to the NVM (EEPROM) | |
1663 | * | |
1664 | * Read the EEPROM for the current default LED configuration. If the | |
1665 | * LED configuration is not valid, set to a valid LED configuration. | |
1666 | **/ | |
1667 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1668 | { | |
1669 | s32 ret_val; | |
1670 | ||
1671 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1672 | if (ret_val) { | |
3bb99fe2 | 1673 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
1674 | return ret_val; |
1675 | } | |
1676 | ||
8c81c9c3 AD |
1677 | switch (hw->mac.type) { |
1678 | case e1000_82573: | |
1679 | case e1000_82574: | |
1680 | case e1000_82583: | |
1681 | if (*data == ID_LED_RESERVED_F746) | |
1682 | *data = ID_LED_DEFAULT_82573; | |
1683 | break; | |
1684 | default: | |
1685 | if (*data == ID_LED_RESERVED_0000 || | |
1686 | *data == ID_LED_RESERVED_FFFF) | |
1687 | *data = ID_LED_DEFAULT; | |
1688 | break; | |
1689 | } | |
bc7f75fa AK |
1690 | |
1691 | return 0; | |
1692 | } | |
1693 | ||
1694 | /** | |
1695 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1696 | * @hw: pointer to the HW structure | |
1697 | * | |
489815ce | 1698 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1699 | **/ |
1700 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1701 | { | |
1702 | if (hw->mac.type != e1000_82571) | |
564ea9bb | 1703 | return false; |
bc7f75fa AK |
1704 | |
1705 | return hw->dev_spec.e82571.laa_is_present; | |
1706 | } | |
1707 | ||
1708 | /** | |
1709 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1710 | * @hw: pointer to the HW structure | |
1711 | * @state: enable/disable locally administered address | |
1712 | * | |
5ff5b664 | 1713 | * Enable/Disable the current locally administered address state. |
bc7f75fa AK |
1714 | **/ |
1715 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1716 | { | |
1717 | if (hw->mac.type != e1000_82571) | |
1718 | return; | |
1719 | ||
1720 | hw->dev_spec.e82571.laa_is_present = state; | |
1721 | ||
1722 | /* If workaround is activated... */ | |
1723 | if (state) | |
ad68076e BA |
1724 | /* |
1725 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1726 | * between the time RAR[0] gets clobbered and the time it |
1727 | * gets fixed, the actual LAA is in one of the RARs and no | |
1728 | * incoming packets directed to this port are dropped. | |
1729 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1730 | */ | |
1731 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1732 | } | |
1733 | ||
1734 | /** | |
1735 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1736 | * @hw: pointer to the HW structure | |
1737 | * | |
1738 | * Verifies that the EEPROM has completed the update. After updating the | |
1739 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1740 | * the checksum fix is not implemented, we need to set the bit and update | |
1741 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1742 | * we need to return bad checksum. | |
1743 | **/ | |
1744 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1745 | { | |
1746 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1747 | s32 ret_val; | |
1748 | u16 data; | |
1749 | ||
1750 | if (nvm->type != e1000_nvm_flash_hw) | |
1751 | return 0; | |
1752 | ||
ad68076e BA |
1753 | /* |
1754 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1755 | * 10h-12h. Checksum may need to be fixed. |
1756 | */ | |
1757 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1758 | if (ret_val) | |
1759 | return ret_val; | |
1760 | ||
1761 | if (!(data & 0x10)) { | |
ad68076e BA |
1762 | /* |
1763 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1764 | * when the checksum has already been fixed. If |
1765 | * the checksum is still wrong and this bit is a | |
1766 | * 1, we need to return bad checksum. Otherwise, | |
1767 | * we need to set this bit to a 1 and update the | |
1768 | * checksum. | |
1769 | */ | |
1770 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1771 | if (ret_val) | |
1772 | return ret_val; | |
1773 | ||
1774 | if (!(data & 0x8000)) { | |
1775 | data |= 0x8000; | |
1776 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1777 | if (ret_val) | |
1778 | return ret_val; | |
1779 | ret_val = e1000e_update_nvm_checksum(hw); | |
1780 | } | |
1781 | } | |
1782 | ||
1783 | return 0; | |
1784 | } | |
1785 | ||
608f8a0d BA |
1786 | /** |
1787 | * e1000_read_mac_addr_82571 - Read device MAC address | |
1788 | * @hw: pointer to the HW structure | |
1789 | **/ | |
1790 | static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) | |
1791 | { | |
1792 | s32 ret_val = 0; | |
1793 | ||
1aef70ef BA |
1794 | if (hw->mac.type == e1000_82571) { |
1795 | /* | |
1796 | * If there's an alternate MAC address place it in RAR0 | |
1797 | * so that it will override the Si installed default perm | |
1798 | * address. | |
1799 | */ | |
1800 | ret_val = e1000_check_alt_mac_addr_generic(hw); | |
1801 | if (ret_val) | |
1802 | goto out; | |
1803 | } | |
608f8a0d BA |
1804 | |
1805 | ret_val = e1000_read_mac_addr_generic(hw); | |
1806 | ||
1807 | out: | |
1808 | return ret_val; | |
1809 | } | |
1810 | ||
17f208de BA |
1811 | /** |
1812 | * e1000_power_down_phy_copper_82571 - Remove link during PHY power down | |
1813 | * @hw: pointer to the HW structure | |
1814 | * | |
1815 | * In the case of a PHY power down to save power, or to turn off link during a | |
1816 | * driver unload, or wake on lan is not enabled, remove the link. | |
1817 | **/ | |
1818 | static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw) | |
1819 | { | |
1820 | struct e1000_phy_info *phy = &hw->phy; | |
1821 | struct e1000_mac_info *mac = &hw->mac; | |
1822 | ||
1823 | if (!(phy->ops.check_reset_block)) | |
1824 | return; | |
1825 | ||
1826 | /* If the management interface is not enabled, then power down */ | |
1827 | if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw))) | |
1828 | e1000_power_down_phy_copper(hw); | |
17f208de BA |
1829 | } |
1830 | ||
bc7f75fa AK |
1831 | /** |
1832 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1833 | * @hw: pointer to the HW structure | |
1834 | * | |
1835 | * Clears the hardware counters by reading the counter registers. | |
1836 | **/ | |
1837 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1838 | { | |
bc7f75fa AK |
1839 | e1000e_clear_hw_cntrs_base(hw); |
1840 | ||
99673d9b BA |
1841 | er32(PRC64); |
1842 | er32(PRC127); | |
1843 | er32(PRC255); | |
1844 | er32(PRC511); | |
1845 | er32(PRC1023); | |
1846 | er32(PRC1522); | |
1847 | er32(PTC64); | |
1848 | er32(PTC127); | |
1849 | er32(PTC255); | |
1850 | er32(PTC511); | |
1851 | er32(PTC1023); | |
1852 | er32(PTC1522); | |
1853 | ||
1854 | er32(ALGNERRC); | |
1855 | er32(RXERRC); | |
1856 | er32(TNCRS); | |
1857 | er32(CEXTERR); | |
1858 | er32(TSCTC); | |
1859 | er32(TSCTFC); | |
1860 | ||
1861 | er32(MGTPRC); | |
1862 | er32(MGTPDC); | |
1863 | er32(MGTPTC); | |
1864 | ||
1865 | er32(IAC); | |
1866 | er32(ICRXOC); | |
1867 | ||
1868 | er32(ICRXPTC); | |
1869 | er32(ICRXATC); | |
1870 | er32(ICTXPTC); | |
1871 | er32(ICTXATC); | |
1872 | er32(ICTXQEC); | |
1873 | er32(ICTXQMTC); | |
1874 | er32(ICRXDMTC); | |
bc7f75fa AK |
1875 | } |
1876 | ||
1877 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1878 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1879 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1880 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1881 | .cleanup_led = e1000e_cleanup_led_generic, |
1882 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1883 | .get_bus_info = e1000e_get_bus_info_pcie, | |
f4d2dd4c | 1884 | .set_lan_id = e1000_set_lan_id_multi_port_pcie, |
bc7f75fa | 1885 | /* .get_link_up_info: media type dependent */ |
4662e82b | 1886 | /* .led_on: mac type dependent */ |
bc7f75fa | 1887 | .led_off = e1000e_led_off_generic, |
ab8932f3 | 1888 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1889 | .write_vfta = e1000_write_vfta_generic, |
1890 | .clear_vfta = e1000_clear_vfta_82571, | |
bc7f75fa AK |
1891 | .reset_hw = e1000_reset_hw_82571, |
1892 | .init_hw = e1000_init_hw_82571, | |
1893 | .setup_link = e1000_setup_link_82571, | |
1894 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1895 | .setup_led = e1000e_setup_led_generic, |
608f8a0d | 1896 | .read_mac_addr = e1000_read_mac_addr_82571, |
bc7f75fa AK |
1897 | }; |
1898 | ||
1899 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
94d8186a | 1900 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1901 | .check_polarity = e1000_check_polarity_igp, |
bc7f75fa | 1902 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1903 | .commit = NULL, |
bc7f75fa AK |
1904 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, |
1905 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1906 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
94d8186a BA |
1907 | .get_info = e1000e_get_phy_info_igp, |
1908 | .read_reg = e1000e_read_phy_reg_igp, | |
1909 | .release = e1000_put_hw_semaphore_82571, | |
1910 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1911 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1912 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1913 | .write_reg = e1000e_write_phy_reg_igp, |
75eb0fad | 1914 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1915 | }; |
1916 | ||
1917 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
94d8186a | 1918 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1919 | .check_polarity = e1000_check_polarity_m88, |
bc7f75fa | 1920 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1921 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1922 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1923 | .get_cfg_done = e1000e_get_cfg_done, | |
1924 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1925 | .get_info = e1000e_get_phy_info_m88, |
1926 | .read_reg = e1000e_read_phy_reg_m88, | |
1927 | .release = e1000_put_hw_semaphore_82571, | |
1928 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1929 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1930 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1931 | .write_reg = e1000e_write_phy_reg_m88, |
75eb0fad | 1932 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1933 | }; |
1934 | ||
4662e82b | 1935 | static struct e1000_phy_operations e82_phy_ops_bm = { |
94d8186a | 1936 | .acquire = e1000_get_hw_semaphore_82571, |
94e5b651 | 1937 | .check_polarity = e1000_check_polarity_m88, |
4662e82b | 1938 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1939 | .commit = e1000e_phy_sw_reset, |
4662e82b BA |
1940 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, |
1941 | .get_cfg_done = e1000e_get_cfg_done, | |
1942 | .get_cable_length = e1000e_get_cable_length_m88, | |
94d8186a BA |
1943 | .get_info = e1000e_get_phy_info_m88, |
1944 | .read_reg = e1000e_read_phy_reg_bm2, | |
1945 | .release = e1000_put_hw_semaphore_82571, | |
1946 | .reset = e1000e_phy_hw_reset_generic, | |
4662e82b BA |
1947 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, |
1948 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1949 | .write_reg = e1000e_write_phy_reg_bm2, |
75eb0fad | 1950 | .cfg_on_link_up = NULL, |
4662e82b BA |
1951 | }; |
1952 | ||
bc7f75fa | 1953 | static struct e1000_nvm_operations e82571_nvm_ops = { |
94d8186a BA |
1954 | .acquire = e1000_acquire_nvm_82571, |
1955 | .read = e1000e_read_nvm_eerd, | |
1956 | .release = e1000_release_nvm_82571, | |
1957 | .update = e1000_update_nvm_checksum_82571, | |
bc7f75fa | 1958 | .valid_led_default = e1000_valid_led_default_82571, |
94d8186a BA |
1959 | .validate = e1000_validate_nvm_checksum_82571, |
1960 | .write = e1000_write_nvm_82571, | |
bc7f75fa AK |
1961 | }; |
1962 | ||
1963 | struct e1000_info e1000_82571_info = { | |
1964 | .mac = e1000_82571, | |
1965 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1966 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1967 | | FLAG_HAS_WOL |
1968 | | FLAG_APME_IN_CTRL3 | |
1969 | | FLAG_RX_CSUM_ENABLED | |
1970 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1971 | | FLAG_HAS_SMART_POWER_DOWN |
1972 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1973 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1974 | | FLAG_APME_CHECK_PORT_B, | |
3a3b7586 JB |
1975 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
1976 | | FLAG2_DMA_BURST, | |
bc7f75fa | 1977 | .pba = 38, |
2adc55c9 | 1978 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1979 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1980 | .mac_ops = &e82571_mac_ops, |
1981 | .phy_ops = &e82_phy_ops_igp, | |
1982 | .nvm_ops = &e82571_nvm_ops, | |
1983 | }; | |
1984 | ||
1985 | struct e1000_info e1000_82572_info = { | |
1986 | .mac = e1000_82572, | |
1987 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1988 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1989 | | FLAG_HAS_WOL |
1990 | | FLAG_APME_IN_CTRL3 | |
1991 | | FLAG_RX_CSUM_ENABLED | |
1992 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa | 1993 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
3a3b7586 JB |
1994 | .flags2 = FLAG2_DISABLE_ASPM_L1 /* errata 13 */ |
1995 | | FLAG2_DMA_BURST, | |
bc7f75fa | 1996 | .pba = 38, |
2adc55c9 | 1997 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1998 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1999 | .mac_ops = &e82571_mac_ops, |
2000 | .phy_ops = &e82_phy_ops_igp, | |
2001 | .nvm_ops = &e82571_nvm_ops, | |
2002 | }; | |
2003 | ||
2004 | struct e1000_info e1000_82573_info = { | |
2005 | .mac = e1000_82573, | |
2006 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
bc7f75fa AK |
2007 | | FLAG_HAS_WOL |
2008 | | FLAG_APME_IN_CTRL3 | |
2009 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
2010 | | FLAG_HAS_SMART_POWER_DOWN |
2011 | | FLAG_HAS_AMT | |
bc7f75fa | 2012 | | FLAG_HAS_SWSM_ON_LOAD, |
19833b5d | 2013 | .flags2 = FLAG2_DISABLE_ASPM_L1, |
bc7f75fa | 2014 | .pba = 20, |
2adc55c9 | 2015 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 2016 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
2017 | .mac_ops = &e82571_mac_ops, |
2018 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 2019 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
2020 | }; |
2021 | ||
4662e82b BA |
2022 | struct e1000_info e1000_82574_info = { |
2023 | .mac = e1000_82574, | |
2024 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2025 | | FLAG_HAS_MSIX | |
2026 | | FLAG_HAS_JUMBO_FRAMES | |
2027 | | FLAG_HAS_WOL | |
2028 | | FLAG_APME_IN_CTRL3 | |
2029 | | FLAG_RX_CSUM_ENABLED | |
2030 | | FLAG_HAS_SMART_POWER_DOWN | |
2031 | | FLAG_HAS_AMT | |
2032 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
ff10e13c | 2033 | .flags2 = FLAG2_CHECK_PHY_HANG, |
ed5c2b0b | 2034 | .pba = 32, |
a825e00c | 2035 | .max_hw_frame_size = DEFAULT_JUMBO, |
4662e82b BA |
2036 | .get_variants = e1000_get_variants_82571, |
2037 | .mac_ops = &e82571_mac_ops, | |
2038 | .phy_ops = &e82_phy_ops_bm, | |
2039 | .nvm_ops = &e82571_nvm_ops, | |
2040 | }; | |
2041 | ||
8c81c9c3 AD |
2042 | struct e1000_info e1000_82583_info = { |
2043 | .mac = e1000_82583, | |
2044 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
2045 | | FLAG_HAS_WOL | |
2046 | | FLAG_APME_IN_CTRL3 | |
2047 | | FLAG_RX_CSUM_ENABLED | |
2048 | | FLAG_HAS_SMART_POWER_DOWN | |
2049 | | FLAG_HAS_AMT | |
2050 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
ed5c2b0b | 2051 | .pba = 32, |
a825e00c | 2052 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
8c81c9c3 AD |
2053 | .get_variants = e1000_get_variants_82571, |
2054 | .mac_ops = &e82571_mac_ops, | |
2055 | .phy_ops = &e82_phy_ops_bm, | |
2056 | .nvm_ops = &e82571_nvm_ops, | |
2057 | }; | |
2058 |