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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
ad68076e | 4 | Copyright(c) 1999 - 2008 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 82571EB Gigabit Ethernet Controller | |
1605927f | 31 | * 82571EB Gigabit Ethernet Controller (Copper) |
bc7f75fa | 32 | * 82571EB Gigabit Ethernet Controller (Fiber) |
ad68076e BA |
33 | * 82571EB Dual Port Gigabit Mezzanine Adapter |
34 | * 82571EB Quad Port Gigabit Mezzanine Adapter | |
35 | * 82571PT Gigabit PT Quad Port Server ExpressModule | |
bc7f75fa AK |
36 | * 82572EI Gigabit Ethernet Controller (Copper) |
37 | * 82572EI Gigabit Ethernet Controller (Fiber) | |
38 | * 82572EI Gigabit Ethernet Controller | |
39 | * 82573V Gigabit Ethernet Controller (Copper) | |
40 | * 82573E Gigabit Ethernet Controller (Copper) | |
41 | * 82573L Gigabit Ethernet Controller | |
4662e82b | 42 | * 82574L Gigabit Network Connection |
8c81c9c3 | 43 | * 82583V Gigabit Network Connection |
bc7f75fa AK |
44 | */ |
45 | ||
46 | #include <linux/netdevice.h> | |
47 | #include <linux/delay.h> | |
48 | #include <linux/pci.h> | |
49 | ||
50 | #include "e1000.h" | |
51 | ||
52 | #define ID_LED_RESERVED_F746 0xF746 | |
53 | #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ | |
54 | (ID_LED_OFF1_ON2 << 8) | \ | |
55 | (ID_LED_DEF1_DEF2 << 4) | \ | |
56 | (ID_LED_DEF1_DEF2)) | |
57 | ||
58 | #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 | |
59 | ||
4662e82b BA |
60 | #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ |
61 | ||
bc7f75fa AK |
62 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); |
63 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); | |
64 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); | |
c9523379 | 65 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw); |
bc7f75fa AK |
66 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, |
67 | u16 words, u16 *data); | |
68 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); | |
69 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); | |
70 | static s32 e1000_setup_link_82571(struct e1000_hw *hw); | |
71 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); | |
4662e82b BA |
72 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw); |
73 | static s32 e1000_led_on_82574(struct e1000_hw *hw); | |
bc7f75fa AK |
74 | |
75 | /** | |
76 | * e1000_init_phy_params_82571 - Init PHY func ptrs. | |
77 | * @hw: pointer to the HW structure | |
78 | * | |
79 | * This is a function pointer entry point called by the api module. | |
80 | **/ | |
81 | static s32 e1000_init_phy_params_82571(struct e1000_hw *hw) | |
82 | { | |
83 | struct e1000_phy_info *phy = &hw->phy; | |
84 | s32 ret_val; | |
85 | ||
318a94d6 | 86 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
87 | phy->type = e1000_phy_none; |
88 | return 0; | |
89 | } | |
90 | ||
91 | phy->addr = 1; | |
92 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
93 | phy->reset_delay_us = 100; | |
94 | ||
95 | switch (hw->mac.type) { | |
96 | case e1000_82571: | |
97 | case e1000_82572: | |
98 | phy->type = e1000_phy_igp_2; | |
99 | break; | |
100 | case e1000_82573: | |
101 | phy->type = e1000_phy_m88; | |
102 | break; | |
4662e82b | 103 | case e1000_82574: |
8c81c9c3 | 104 | case e1000_82583: |
4662e82b BA |
105 | phy->type = e1000_phy_bm; |
106 | break; | |
bc7f75fa AK |
107 | default: |
108 | return -E1000_ERR_PHY; | |
109 | break; | |
110 | } | |
111 | ||
112 | /* This can only be done after all function pointers are setup. */ | |
113 | ret_val = e1000_get_phy_id_82571(hw); | |
114 | ||
115 | /* Verify phy id */ | |
116 | switch (hw->mac.type) { | |
117 | case e1000_82571: | |
118 | case e1000_82572: | |
119 | if (phy->id != IGP01E1000_I_PHY_ID) | |
120 | return -E1000_ERR_PHY; | |
121 | break; | |
122 | case e1000_82573: | |
123 | if (phy->id != M88E1111_I_PHY_ID) | |
124 | return -E1000_ERR_PHY; | |
125 | break; | |
4662e82b | 126 | case e1000_82574: |
8c81c9c3 | 127 | case e1000_82583: |
4662e82b BA |
128 | if (phy->id != BME1000_E_PHY_ID_R2) |
129 | return -E1000_ERR_PHY; | |
130 | break; | |
bc7f75fa AK |
131 | default: |
132 | return -E1000_ERR_PHY; | |
133 | break; | |
134 | } | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | /** | |
140 | * e1000_init_nvm_params_82571 - Init NVM func ptrs. | |
141 | * @hw: pointer to the HW structure | |
142 | * | |
143 | * This is a function pointer entry point called by the api module. | |
144 | **/ | |
145 | static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) | |
146 | { | |
147 | struct e1000_nvm_info *nvm = &hw->nvm; | |
148 | u32 eecd = er32(EECD); | |
149 | u16 size; | |
150 | ||
151 | nvm->opcode_bits = 8; | |
152 | nvm->delay_usec = 1; | |
153 | switch (nvm->override) { | |
154 | case e1000_nvm_override_spi_large: | |
155 | nvm->page_size = 32; | |
156 | nvm->address_bits = 16; | |
157 | break; | |
158 | case e1000_nvm_override_spi_small: | |
159 | nvm->page_size = 8; | |
160 | nvm->address_bits = 8; | |
161 | break; | |
162 | default: | |
163 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
164 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
165 | break; | |
166 | } | |
167 | ||
168 | switch (hw->mac.type) { | |
169 | case e1000_82573: | |
4662e82b | 170 | case e1000_82574: |
8c81c9c3 | 171 | case e1000_82583: |
bc7f75fa AK |
172 | if (((eecd >> 15) & 0x3) == 0x3) { |
173 | nvm->type = e1000_nvm_flash_hw; | |
174 | nvm->word_size = 2048; | |
ad68076e BA |
175 | /* |
176 | * Autonomous Flash update bit must be cleared due | |
bc7f75fa AK |
177 | * to Flash update issue. |
178 | */ | |
179 | eecd &= ~E1000_EECD_AUPDEN; | |
180 | ew32(EECD, eecd); | |
181 | break; | |
182 | } | |
183 | /* Fall Through */ | |
184 | default: | |
ad68076e | 185 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
186 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
187 | E1000_EECD_SIZE_EX_SHIFT); | |
ad68076e BA |
188 | /* |
189 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
190 | * for setting word_size. |
191 | */ | |
192 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
193 | |
194 | /* EEPROM access above 16k is unsupported */ | |
195 | if (size > 14) | |
196 | size = 14; | |
bc7f75fa AK |
197 | nvm->word_size = 1 << size; |
198 | break; | |
199 | } | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | /** | |
205 | * e1000_init_mac_params_82571 - Init MAC func ptrs. | |
206 | * @hw: pointer to the HW structure | |
207 | * | |
208 | * This is a function pointer entry point called by the api module. | |
209 | **/ | |
210 | static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter) | |
211 | { | |
212 | struct e1000_hw *hw = &adapter->hw; | |
213 | struct e1000_mac_info *mac = &hw->mac; | |
214 | struct e1000_mac_operations *func = &mac->ops; | |
215 | ||
216 | /* Set media type */ | |
217 | switch (adapter->pdev->device) { | |
218 | case E1000_DEV_ID_82571EB_FIBER: | |
219 | case E1000_DEV_ID_82572EI_FIBER: | |
220 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
318a94d6 | 221 | hw->phy.media_type = e1000_media_type_fiber; |
bc7f75fa AK |
222 | break; |
223 | case E1000_DEV_ID_82571EB_SERDES: | |
224 | case E1000_DEV_ID_82572EI_SERDES: | |
040babf9 AK |
225 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
226 | case E1000_DEV_ID_82571EB_SERDES_QUAD: | |
318a94d6 | 227 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
228 | break; |
229 | default: | |
318a94d6 | 230 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
231 | break; |
232 | } | |
233 | ||
234 | /* Set mta register count */ | |
235 | mac->mta_reg_count = 128; | |
236 | /* Set rar entry count */ | |
237 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
238 | /* Set if manageability features are enabled. */ | |
ad68076e | 239 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0; |
bc7f75fa AK |
240 | |
241 | /* check for link */ | |
318a94d6 | 242 | switch (hw->phy.media_type) { |
bc7f75fa AK |
243 | case e1000_media_type_copper: |
244 | func->setup_physical_interface = e1000_setup_copper_link_82571; | |
245 | func->check_for_link = e1000e_check_for_copper_link; | |
246 | func->get_link_up_info = e1000e_get_speed_and_duplex_copper; | |
247 | break; | |
248 | case e1000_media_type_fiber: | |
ad68076e BA |
249 | func->setup_physical_interface = |
250 | e1000_setup_fiber_serdes_link_82571; | |
bc7f75fa | 251 | func->check_for_link = e1000e_check_for_fiber_link; |
ad68076e BA |
252 | func->get_link_up_info = |
253 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
254 | break; |
255 | case e1000_media_type_internal_serdes: | |
ad68076e BA |
256 | func->setup_physical_interface = |
257 | e1000_setup_fiber_serdes_link_82571; | |
c9523379 | 258 | func->check_for_link = e1000_check_for_serdes_link_82571; |
ad68076e BA |
259 | func->get_link_up_info = |
260 | e1000e_get_speed_and_duplex_fiber_serdes; | |
bc7f75fa AK |
261 | break; |
262 | default: | |
263 | return -E1000_ERR_CONFIG; | |
264 | break; | |
265 | } | |
266 | ||
4662e82b BA |
267 | switch (hw->mac.type) { |
268 | case e1000_82574: | |
8c81c9c3 | 269 | case e1000_82583: |
4662e82b BA |
270 | func->check_mng_mode = e1000_check_mng_mode_82574; |
271 | func->led_on = e1000_led_on_82574; | |
272 | break; | |
273 | default: | |
274 | func->check_mng_mode = e1000e_check_mng_mode_generic; | |
275 | func->led_on = e1000e_led_on_generic; | |
276 | break; | |
277 | } | |
278 | ||
bc7f75fa AK |
279 | return 0; |
280 | } | |
281 | ||
69e3fd8c | 282 | static s32 e1000_get_variants_82571(struct e1000_adapter *adapter) |
bc7f75fa AK |
283 | { |
284 | struct e1000_hw *hw = &adapter->hw; | |
285 | static int global_quad_port_a; /* global port a indication */ | |
286 | struct pci_dev *pdev = adapter->pdev; | |
287 | u16 eeprom_data = 0; | |
288 | int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1; | |
289 | s32 rc; | |
290 | ||
291 | rc = e1000_init_mac_params_82571(adapter); | |
292 | if (rc) | |
293 | return rc; | |
294 | ||
295 | rc = e1000_init_nvm_params_82571(hw); | |
296 | if (rc) | |
297 | return rc; | |
298 | ||
299 | rc = e1000_init_phy_params_82571(hw); | |
300 | if (rc) | |
301 | return rc; | |
302 | ||
303 | /* tag quad port adapters first, it's used below */ | |
304 | switch (pdev->device) { | |
305 | case E1000_DEV_ID_82571EB_QUAD_COPPER: | |
306 | case E1000_DEV_ID_82571EB_QUAD_FIBER: | |
307 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: | |
040babf9 | 308 | case E1000_DEV_ID_82571PT_QUAD_COPPER: |
bc7f75fa AK |
309 | adapter->flags |= FLAG_IS_QUAD_PORT; |
310 | /* mark the first port */ | |
311 | if (global_quad_port_a == 0) | |
312 | adapter->flags |= FLAG_IS_QUAD_PORT_A; | |
313 | /* Reset for multiple quad port adapters */ | |
314 | global_quad_port_a++; | |
315 | if (global_quad_port_a == 4) | |
316 | global_quad_port_a = 0; | |
317 | break; | |
318 | default: | |
319 | break; | |
320 | } | |
321 | ||
322 | switch (adapter->hw.mac.type) { | |
323 | case e1000_82571: | |
324 | /* these dual ports don't have WoL on port B at all */ | |
325 | if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) || | |
326 | (pdev->device == E1000_DEV_ID_82571EB_SERDES) || | |
327 | (pdev->device == E1000_DEV_ID_82571EB_COPPER)) && | |
328 | (is_port_b)) | |
329 | adapter->flags &= ~FLAG_HAS_WOL; | |
330 | /* quad ports only support WoL on port A */ | |
331 | if (adapter->flags & FLAG_IS_QUAD_PORT && | |
6e4ca80d | 332 | (!(adapter->flags & FLAG_IS_QUAD_PORT_A))) |
bc7f75fa | 333 | adapter->flags &= ~FLAG_HAS_WOL; |
040babf9 AK |
334 | /* Does not support WoL on any port */ |
335 | if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD) | |
336 | adapter->flags &= ~FLAG_HAS_WOL; | |
bc7f75fa AK |
337 | break; |
338 | ||
339 | case e1000_82573: | |
340 | if (pdev->device == E1000_DEV_ID_82573L) { | |
e243455d BA |
341 | if (e1000_read_nvm(&adapter->hw, NVM_INIT_3GIO_3, 1, |
342 | &eeprom_data) < 0) | |
343 | break; | |
2adc55c9 BA |
344 | if (!(eeprom_data & NVM_WORD1A_ASPM_MASK)) { |
345 | adapter->flags |= FLAG_HAS_JUMBO_FRAMES; | |
346 | adapter->max_hw_frame_size = DEFAULT_JUMBO; | |
347 | } | |
bc7f75fa AK |
348 | } |
349 | break; | |
350 | default: | |
351 | break; | |
352 | } | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | /** | |
358 | * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision | |
359 | * @hw: pointer to the HW structure | |
360 | * | |
361 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
362 | * revision in the hardware structure. | |
363 | **/ | |
364 | static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) | |
365 | { | |
366 | struct e1000_phy_info *phy = &hw->phy; | |
4662e82b BA |
367 | s32 ret_val; |
368 | u16 phy_id = 0; | |
bc7f75fa AK |
369 | |
370 | switch (hw->mac.type) { | |
371 | case e1000_82571: | |
372 | case e1000_82572: | |
ad68076e BA |
373 | /* |
374 | * The 82571 firmware may still be configuring the PHY. | |
bc7f75fa AK |
375 | * In this case, we cannot access the PHY until the |
376 | * configuration is done. So we explicitly set the | |
ad68076e BA |
377 | * PHY ID. |
378 | */ | |
bc7f75fa AK |
379 | phy->id = IGP01E1000_I_PHY_ID; |
380 | break; | |
381 | case e1000_82573: | |
382 | return e1000e_get_phy_id(hw); | |
383 | break; | |
4662e82b | 384 | case e1000_82574: |
8c81c9c3 | 385 | case e1000_82583: |
4662e82b BA |
386 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); |
387 | if (ret_val) | |
388 | return ret_val; | |
389 | ||
390 | phy->id = (u32)(phy_id << 16); | |
391 | udelay(20); | |
392 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
393 | if (ret_val) | |
394 | return ret_val; | |
395 | ||
396 | phy->id |= (u32)(phy_id); | |
397 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
398 | break; | |
bc7f75fa AK |
399 | default: |
400 | return -E1000_ERR_PHY; | |
401 | break; | |
402 | } | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | /** | |
408 | * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore | |
409 | * @hw: pointer to the HW structure | |
410 | * | |
411 | * Acquire the HW semaphore to access the PHY or NVM | |
412 | **/ | |
413 | static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) | |
414 | { | |
415 | u32 swsm; | |
416 | s32 timeout = hw->nvm.word_size + 1; | |
417 | s32 i = 0; | |
418 | ||
419 | /* Get the FW semaphore. */ | |
420 | for (i = 0; i < timeout; i++) { | |
421 | swsm = er32(SWSM); | |
422 | ew32(SWSM, swsm | E1000_SWSM_SWESMBI); | |
423 | ||
424 | /* Semaphore acquired if bit latched */ | |
425 | if (er32(SWSM) & E1000_SWSM_SWESMBI) | |
426 | break; | |
427 | ||
428 | udelay(50); | |
429 | } | |
430 | ||
431 | if (i == timeout) { | |
432 | /* Release semaphores */ | |
433 | e1000e_put_hw_semaphore(hw); | |
434 | hw_dbg(hw, "Driver can't access the NVM\n"); | |
435 | return -E1000_ERR_NVM; | |
436 | } | |
437 | ||
438 | return 0; | |
439 | } | |
440 | ||
441 | /** | |
442 | * e1000_put_hw_semaphore_82571 - Release hardware semaphore | |
443 | * @hw: pointer to the HW structure | |
444 | * | |
445 | * Release hardware semaphore used to access the PHY or NVM | |
446 | **/ | |
447 | static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) | |
448 | { | |
449 | u32 swsm; | |
450 | ||
451 | swsm = er32(SWSM); | |
452 | ||
453 | swsm &= ~E1000_SWSM_SWESMBI; | |
454 | ||
455 | ew32(SWSM, swsm); | |
456 | } | |
457 | ||
458 | /** | |
459 | * e1000_acquire_nvm_82571 - Request for access to the EEPROM | |
460 | * @hw: pointer to the HW structure | |
461 | * | |
462 | * To gain access to the EEPROM, first we must obtain a hardware semaphore. | |
463 | * Then for non-82573 hardware, set the EEPROM access request bit and wait | |
464 | * for EEPROM access grant bit. If the access grant bit is not set, release | |
465 | * hardware semaphore. | |
466 | **/ | |
467 | static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) | |
468 | { | |
469 | s32 ret_val; | |
470 | ||
471 | ret_val = e1000_get_hw_semaphore_82571(hw); | |
472 | if (ret_val) | |
473 | return ret_val; | |
474 | ||
8c81c9c3 AD |
475 | switch (hw->mac.type) { |
476 | case e1000_82573: | |
477 | case e1000_82574: | |
478 | case e1000_82583: | |
479 | break; | |
480 | default: | |
bc7f75fa | 481 | ret_val = e1000e_acquire_nvm(hw); |
8c81c9c3 AD |
482 | break; |
483 | } | |
bc7f75fa AK |
484 | |
485 | if (ret_val) | |
486 | e1000_put_hw_semaphore_82571(hw); | |
487 | ||
488 | return ret_val; | |
489 | } | |
490 | ||
491 | /** | |
492 | * e1000_release_nvm_82571 - Release exclusive access to EEPROM | |
493 | * @hw: pointer to the HW structure | |
494 | * | |
495 | * Stop any current commands to the EEPROM and clear the EEPROM request bit. | |
496 | **/ | |
497 | static void e1000_release_nvm_82571(struct e1000_hw *hw) | |
498 | { | |
499 | e1000e_release_nvm(hw); | |
500 | e1000_put_hw_semaphore_82571(hw); | |
501 | } | |
502 | ||
503 | /** | |
504 | * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface | |
505 | * @hw: pointer to the HW structure | |
506 | * @offset: offset within the EEPROM to be written to | |
507 | * @words: number of words to write | |
508 | * @data: 16 bit word(s) to be written to the EEPROM | |
509 | * | |
510 | * For non-82573 silicon, write data to EEPROM at offset using SPI interface. | |
511 | * | |
512 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 513 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
514 | **/ |
515 | static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, | |
516 | u16 *data) | |
517 | { | |
518 | s32 ret_val; | |
519 | ||
520 | switch (hw->mac.type) { | |
521 | case e1000_82573: | |
4662e82b | 522 | case e1000_82574: |
8c81c9c3 | 523 | case e1000_82583: |
bc7f75fa AK |
524 | ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); |
525 | break; | |
526 | case e1000_82571: | |
527 | case e1000_82572: | |
528 | ret_val = e1000e_write_nvm_spi(hw, offset, words, data); | |
529 | break; | |
530 | default: | |
531 | ret_val = -E1000_ERR_NVM; | |
532 | break; | |
533 | } | |
534 | ||
535 | return ret_val; | |
536 | } | |
537 | ||
538 | /** | |
539 | * e1000_update_nvm_checksum_82571 - Update EEPROM checksum | |
540 | * @hw: pointer to the HW structure | |
541 | * | |
542 | * Updates the EEPROM checksum by reading/adding each word of the EEPROM | |
543 | * up to the checksum. Then calculates the EEPROM checksum and writes the | |
544 | * value to the EEPROM. | |
545 | **/ | |
546 | static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) | |
547 | { | |
548 | u32 eecd; | |
549 | s32 ret_val; | |
550 | u16 i; | |
551 | ||
552 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
553 | if (ret_val) | |
554 | return ret_val; | |
555 | ||
ad68076e BA |
556 | /* |
557 | * If our nvm is an EEPROM, then we're done | |
558 | * otherwise, commit the checksum to the flash NVM. | |
559 | */ | |
bc7f75fa AK |
560 | if (hw->nvm.type != e1000_nvm_flash_hw) |
561 | return ret_val; | |
562 | ||
563 | /* Check for pending operations. */ | |
564 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
565 | msleep(1); | |
566 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
567 | break; | |
568 | } | |
569 | ||
570 | if (i == E1000_FLASH_UPDATES) | |
571 | return -E1000_ERR_NVM; | |
572 | ||
573 | /* Reset the firmware if using STM opcode. */ | |
574 | if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) { | |
ad68076e BA |
575 | /* |
576 | * The enabling of and the actual reset must be done | |
bc7f75fa AK |
577 | * in two write cycles. |
578 | */ | |
579 | ew32(HICR, E1000_HICR_FW_RESET_ENABLE); | |
580 | e1e_flush(); | |
581 | ew32(HICR, E1000_HICR_FW_RESET); | |
582 | } | |
583 | ||
584 | /* Commit the write to flash */ | |
585 | eecd = er32(EECD) | E1000_EECD_FLUPD; | |
586 | ew32(EECD, eecd); | |
587 | ||
588 | for (i = 0; i < E1000_FLASH_UPDATES; i++) { | |
589 | msleep(1); | |
590 | if ((er32(EECD) & E1000_EECD_FLUPD) == 0) | |
591 | break; | |
592 | } | |
593 | ||
594 | if (i == E1000_FLASH_UPDATES) | |
595 | return -E1000_ERR_NVM; | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | /** | |
601 | * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum | |
602 | * @hw: pointer to the HW structure | |
603 | * | |
604 | * Calculates the EEPROM checksum by reading/adding each word of the EEPROM | |
605 | * and then verifies that the sum of the EEPROM is equal to 0xBABA. | |
606 | **/ | |
607 | static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) | |
608 | { | |
609 | if (hw->nvm.type == e1000_nvm_flash_hw) | |
610 | e1000_fix_nvm_checksum_82571(hw); | |
611 | ||
612 | return e1000e_validate_nvm_checksum_generic(hw); | |
613 | } | |
614 | ||
615 | /** | |
616 | * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon | |
617 | * @hw: pointer to the HW structure | |
618 | * @offset: offset within the EEPROM to be written to | |
619 | * @words: number of words to write | |
620 | * @data: 16 bit word(s) to be written to the EEPROM | |
621 | * | |
622 | * After checking for invalid values, poll the EEPROM to ensure the previous | |
623 | * command has completed before trying to write the next word. After write | |
624 | * poll for completion. | |
625 | * | |
626 | * If e1000e_update_nvm_checksum is not called after this function, the | |
489815ce | 627 | * EEPROM will most likely contain an invalid checksum. |
bc7f75fa AK |
628 | **/ |
629 | static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, | |
630 | u16 words, u16 *data) | |
631 | { | |
632 | struct e1000_nvm_info *nvm = &hw->nvm; | |
633 | u32 i; | |
634 | u32 eewr = 0; | |
635 | s32 ret_val = 0; | |
636 | ||
ad68076e BA |
637 | /* |
638 | * A check for invalid values: offset too large, too many words, | |
639 | * and not enough words. | |
640 | */ | |
bc7f75fa AK |
641 | if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || |
642 | (words == 0)) { | |
643 | hw_dbg(hw, "nvm parameter(s) out of bounds\n"); | |
644 | return -E1000_ERR_NVM; | |
645 | } | |
646 | ||
647 | for (i = 0; i < words; i++) { | |
648 | eewr = (data[i] << E1000_NVM_RW_REG_DATA) | | |
649 | ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | | |
650 | E1000_NVM_RW_REG_START; | |
651 | ||
652 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
653 | if (ret_val) | |
654 | break; | |
655 | ||
656 | ew32(EEWR, eewr); | |
657 | ||
658 | ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); | |
659 | if (ret_val) | |
660 | break; | |
661 | } | |
662 | ||
663 | return ret_val; | |
664 | } | |
665 | ||
666 | /** | |
667 | * e1000_get_cfg_done_82571 - Poll for configuration done | |
668 | * @hw: pointer to the HW structure | |
669 | * | |
670 | * Reads the management control register for the config done bit to be set. | |
671 | **/ | |
672 | static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) | |
673 | { | |
674 | s32 timeout = PHY_CFG_TIMEOUT; | |
675 | ||
676 | while (timeout) { | |
677 | if (er32(EEMNGCTL) & | |
678 | E1000_NVM_CFG_DONE_PORT_0) | |
679 | break; | |
680 | msleep(1); | |
681 | timeout--; | |
682 | } | |
683 | if (!timeout) { | |
684 | hw_dbg(hw, "MNG configuration cycle has not completed.\n"); | |
685 | return -E1000_ERR_RESET; | |
686 | } | |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | /** | |
692 | * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state | |
693 | * @hw: pointer to the HW structure | |
694 | * @active: TRUE to enable LPLU, FALSE to disable | |
695 | * | |
696 | * Sets the LPLU D0 state according to the active flag. When activating LPLU | |
697 | * this function also disables smart speed and vice versa. LPLU will not be | |
698 | * activated unless the device autonegotiation advertisement meets standards | |
699 | * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function | |
700 | * pointer entry point only called by PHY setup routines. | |
701 | **/ | |
702 | static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) | |
703 | { | |
704 | struct e1000_phy_info *phy = &hw->phy; | |
705 | s32 ret_val; | |
706 | u16 data; | |
707 | ||
708 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
709 | if (ret_val) | |
710 | return ret_val; | |
711 | ||
712 | if (active) { | |
713 | data |= IGP02E1000_PM_D0_LPLU; | |
714 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
715 | if (ret_val) | |
716 | return ret_val; | |
717 | ||
718 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
719 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
720 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
721 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
722 | if (ret_val) | |
723 | return ret_val; | |
724 | } else { | |
725 | data &= ~IGP02E1000_PM_D0_LPLU; | |
726 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
ad68076e BA |
727 | /* |
728 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
729 | * during Dx states where the power conservation is most |
730 | * important. During driver activity we should enable | |
ad68076e BA |
731 | * SmartSpeed, so performance is maintained. |
732 | */ | |
bc7f75fa AK |
733 | if (phy->smart_speed == e1000_smart_speed_on) { |
734 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 735 | &data); |
bc7f75fa AK |
736 | if (ret_val) |
737 | return ret_val; | |
738 | ||
739 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
740 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 741 | data); |
bc7f75fa AK |
742 | if (ret_val) |
743 | return ret_val; | |
744 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
745 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 746 | &data); |
bc7f75fa AK |
747 | if (ret_val) |
748 | return ret_val; | |
749 | ||
750 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
751 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 752 | data); |
bc7f75fa AK |
753 | if (ret_val) |
754 | return ret_val; | |
755 | } | |
756 | } | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | /** | |
762 | * e1000_reset_hw_82571 - Reset hardware | |
763 | * @hw: pointer to the HW structure | |
764 | * | |
765 | * This resets the hardware into a known state. This is a | |
766 | * function pointer entry point called by the api module. | |
767 | **/ | |
768 | static s32 e1000_reset_hw_82571(struct e1000_hw *hw) | |
769 | { | |
770 | u32 ctrl; | |
771 | u32 extcnf_ctrl; | |
772 | u32 ctrl_ext; | |
773 | u32 icr; | |
774 | s32 ret_val; | |
775 | u16 i = 0; | |
776 | ||
ad68076e BA |
777 | /* |
778 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
779 | * on the last TLP read/write transaction when MAC is reset. |
780 | */ | |
781 | ret_val = e1000e_disable_pcie_master(hw); | |
782 | if (ret_val) | |
783 | hw_dbg(hw, "PCI-E Master disable polling has failed.\n"); | |
784 | ||
785 | hw_dbg(hw, "Masking off all interrupts\n"); | |
786 | ew32(IMC, 0xffffffff); | |
787 | ||
788 | ew32(RCTL, 0); | |
789 | ew32(TCTL, E1000_TCTL_PSP); | |
790 | e1e_flush(); | |
791 | ||
792 | msleep(10); | |
793 | ||
ad68076e BA |
794 | /* |
795 | * Must acquire the MDIO ownership before MAC reset. | |
796 | * Ownership defaults to firmware after a reset. | |
797 | */ | |
8c81c9c3 AD |
798 | switch (hw->mac.type) { |
799 | case e1000_82573: | |
800 | case e1000_82574: | |
801 | case e1000_82583: | |
bc7f75fa AK |
802 | extcnf_ctrl = er32(EXTCNF_CTRL); |
803 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
804 | ||
805 | do { | |
806 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
807 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
808 | ||
809 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) | |
810 | break; | |
811 | ||
812 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; | |
813 | ||
814 | msleep(2); | |
815 | i++; | |
816 | } while (i < MDIO_OWNERSHIP_TIMEOUT); | |
8c81c9c3 AD |
817 | break; |
818 | default: | |
819 | break; | |
bc7f75fa AK |
820 | } |
821 | ||
822 | ctrl = er32(CTRL); | |
823 | ||
824 | hw_dbg(hw, "Issuing a global reset to MAC\n"); | |
825 | ew32(CTRL, ctrl | E1000_CTRL_RST); | |
826 | ||
827 | if (hw->nvm.type == e1000_nvm_flash_hw) { | |
828 | udelay(10); | |
829 | ctrl_ext = er32(CTRL_EXT); | |
830 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; | |
831 | ew32(CTRL_EXT, ctrl_ext); | |
832 | e1e_flush(); | |
833 | } | |
834 | ||
835 | ret_val = e1000e_get_auto_rd_done(hw); | |
836 | if (ret_val) | |
837 | /* We don't want to continue accessing MAC registers. */ | |
838 | return ret_val; | |
839 | ||
ad68076e BA |
840 | /* |
841 | * Phy configuration from NVM just starts after EECD_AUTO_RD is set. | |
bc7f75fa AK |
842 | * Need to wait for Phy configuration completion before accessing |
843 | * NVM and Phy. | |
844 | */ | |
8c81c9c3 AD |
845 | |
846 | switch (hw->mac.type) { | |
847 | case e1000_82573: | |
848 | case e1000_82574: | |
849 | case e1000_82583: | |
bc7f75fa | 850 | msleep(25); |
8c81c9c3 AD |
851 | break; |
852 | default: | |
853 | break; | |
854 | } | |
bc7f75fa AK |
855 | |
856 | /* Clear any pending interrupt events. */ | |
857 | ew32(IMC, 0xffffffff); | |
858 | icr = er32(ICR); | |
859 | ||
93ca1610 BH |
860 | if (hw->mac.type == e1000_82571 && |
861 | hw->dev_spec.e82571.alt_mac_addr_is_present) | |
862 | e1000e_set_laa_state_82571(hw, true); | |
863 | ||
c9523379 | 864 | /* Reinitialize the 82571 serdes link state machine */ |
865 | if (hw->phy.media_type == e1000_media_type_internal_serdes) | |
866 | hw->mac.serdes_link_state = e1000_serdes_link_down; | |
867 | ||
bc7f75fa AK |
868 | return 0; |
869 | } | |
870 | ||
871 | /** | |
872 | * e1000_init_hw_82571 - Initialize hardware | |
873 | * @hw: pointer to the HW structure | |
874 | * | |
875 | * This inits the hardware readying it for operation. | |
876 | **/ | |
877 | static s32 e1000_init_hw_82571(struct e1000_hw *hw) | |
878 | { | |
879 | struct e1000_mac_info *mac = &hw->mac; | |
880 | u32 reg_data; | |
881 | s32 ret_val; | |
882 | u16 i; | |
883 | u16 rar_count = mac->rar_entry_count; | |
884 | ||
885 | e1000_initialize_hw_bits_82571(hw); | |
886 | ||
887 | /* Initialize identification LED */ | |
888 | ret_val = e1000e_id_led_init(hw); | |
889 | if (ret_val) { | |
890 | hw_dbg(hw, "Error initializing identification LED\n"); | |
891 | return ret_val; | |
892 | } | |
893 | ||
894 | /* Disabling VLAN filtering */ | |
895 | hw_dbg(hw, "Initializing the IEEE VLAN\n"); | |
896 | e1000e_clear_vfta(hw); | |
897 | ||
898 | /* Setup the receive address. */ | |
ad68076e BA |
899 | /* |
900 | * If, however, a locally administered address was assigned to the | |
bc7f75fa AK |
901 | * 82571, we must reserve a RAR for it to work around an issue where |
902 | * resetting one port will reload the MAC on the other port. | |
903 | */ | |
904 | if (e1000e_get_laa_state_82571(hw)) | |
905 | rar_count--; | |
906 | e1000e_init_rx_addrs(hw, rar_count); | |
907 | ||
908 | /* Zero out the Multicast HASH table */ | |
909 | hw_dbg(hw, "Zeroing the MTA\n"); | |
910 | for (i = 0; i < mac->mta_reg_count; i++) | |
911 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
912 | ||
913 | /* Setup link and flow control */ | |
914 | ret_val = e1000_setup_link_82571(hw); | |
915 | ||
916 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 917 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
918 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
919 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
920 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 921 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
922 | |
923 | /* ...for both queues. */ | |
8c81c9c3 AD |
924 | switch (mac->type) { |
925 | case e1000_82573: | |
926 | case e1000_82574: | |
927 | case e1000_82583: | |
928 | e1000e_enable_tx_pkt_filtering(hw); | |
929 | reg_data = er32(GCR); | |
930 | reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; | |
931 | ew32(GCR, reg_data); | |
932 | break; | |
933 | default: | |
e9ec2c0f | 934 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
935 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
936 | E1000_TXDCTL_FULL_TX_DESC_WB | | |
937 | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 938 | ew32(TXDCTL(1), reg_data); |
8c81c9c3 | 939 | break; |
bc7f75fa AK |
940 | } |
941 | ||
ad68076e BA |
942 | /* |
943 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
944 | * important that we do this after we have tried to establish link |
945 | * because the symbol error count will increment wildly if there | |
946 | * is no link. | |
947 | */ | |
948 | e1000_clear_hw_cntrs_82571(hw); | |
949 | ||
950 | return ret_val; | |
951 | } | |
952 | ||
953 | /** | |
954 | * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits | |
955 | * @hw: pointer to the HW structure | |
956 | * | |
957 | * Initializes required hardware-dependent bits needed for normal operation. | |
958 | **/ | |
959 | static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) | |
960 | { | |
961 | u32 reg; | |
962 | ||
963 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 964 | reg = er32(TXDCTL(0)); |
bc7f75fa | 965 | reg |= (1 << 22); |
e9ec2c0f | 966 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
967 | |
968 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 969 | reg = er32(TXDCTL(1)); |
bc7f75fa | 970 | reg |= (1 << 22); |
e9ec2c0f | 971 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
972 | |
973 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 974 | reg = er32(TARC(0)); |
bc7f75fa AK |
975 | reg &= ~(0xF << 27); /* 30:27 */ |
976 | switch (hw->mac.type) { | |
977 | case e1000_82571: | |
978 | case e1000_82572: | |
979 | reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); | |
980 | break; | |
981 | default: | |
982 | break; | |
983 | } | |
e9ec2c0f | 984 | ew32(TARC(0), reg); |
bc7f75fa AK |
985 | |
986 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 987 | reg = er32(TARC(1)); |
bc7f75fa AK |
988 | switch (hw->mac.type) { |
989 | case e1000_82571: | |
990 | case e1000_82572: | |
991 | reg &= ~((1 << 29) | (1 << 30)); | |
992 | reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); | |
993 | if (er32(TCTL) & E1000_TCTL_MULR) | |
994 | reg &= ~(1 << 28); | |
995 | else | |
996 | reg |= (1 << 28); | |
e9ec2c0f | 997 | ew32(TARC(1), reg); |
bc7f75fa AK |
998 | break; |
999 | default: | |
1000 | break; | |
1001 | } | |
1002 | ||
1003 | /* Device Control */ | |
8c81c9c3 AD |
1004 | switch (hw->mac.type) { |
1005 | case e1000_82573: | |
1006 | case e1000_82574: | |
1007 | case e1000_82583: | |
bc7f75fa AK |
1008 | reg = er32(CTRL); |
1009 | reg &= ~(1 << 29); | |
1010 | ew32(CTRL, reg); | |
8c81c9c3 AD |
1011 | break; |
1012 | default: | |
1013 | break; | |
bc7f75fa AK |
1014 | } |
1015 | ||
1016 | /* Extended Device Control */ | |
8c81c9c3 AD |
1017 | switch (hw->mac.type) { |
1018 | case e1000_82573: | |
1019 | case e1000_82574: | |
1020 | case e1000_82583: | |
bc7f75fa AK |
1021 | reg = er32(CTRL_EXT); |
1022 | reg &= ~(1 << 23); | |
1023 | reg |= (1 << 22); | |
1024 | ew32(CTRL_EXT, reg); | |
8c81c9c3 AD |
1025 | break; |
1026 | default: | |
1027 | break; | |
bc7f75fa | 1028 | } |
4662e82b | 1029 | |
6ea7ae1d AD |
1030 | if (hw->mac.type == e1000_82571) { |
1031 | reg = er32(PBA_ECC); | |
1032 | reg |= E1000_PBA_ECC_CORR_EN; | |
1033 | ew32(PBA_ECC, reg); | |
1034 | } | |
5df3f0ea | 1035 | /* |
1036 | * Workaround for hardware errata. | |
1037 | * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572 | |
1038 | */ | |
1039 | ||
1040 | if ((hw->mac.type == e1000_82571) || | |
1041 | (hw->mac.type == e1000_82572)) { | |
1042 | reg = er32(CTRL_EXT); | |
1043 | reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN; | |
1044 | ew32(CTRL_EXT, reg); | |
1045 | } | |
1046 | ||
6ea7ae1d | 1047 | |
78272bba | 1048 | /* PCI-Ex Control Registers */ |
8c81c9c3 AD |
1049 | switch (hw->mac.type) { |
1050 | case e1000_82574: | |
1051 | case e1000_82583: | |
4662e82b BA |
1052 | reg = er32(GCR); |
1053 | reg |= (1 << 22); | |
1054 | ew32(GCR, reg); | |
78272bba JB |
1055 | |
1056 | reg = er32(GCR2); | |
1057 | reg |= 1; | |
1058 | ew32(GCR2, reg); | |
8c81c9c3 AD |
1059 | break; |
1060 | default: | |
1061 | break; | |
4662e82b BA |
1062 | } |
1063 | ||
1064 | return; | |
bc7f75fa AK |
1065 | } |
1066 | ||
1067 | /** | |
1068 | * e1000e_clear_vfta - Clear VLAN filter table | |
1069 | * @hw: pointer to the HW structure | |
1070 | * | |
1071 | * Clears the register array which contains the VLAN filter table by | |
1072 | * setting all the values to 0. | |
1073 | **/ | |
1074 | void e1000e_clear_vfta(struct e1000_hw *hw) | |
1075 | { | |
1076 | u32 offset; | |
1077 | u32 vfta_value = 0; | |
1078 | u32 vfta_offset = 0; | |
1079 | u32 vfta_bit_in_reg = 0; | |
1080 | ||
8c81c9c3 AD |
1081 | switch (hw->mac.type) { |
1082 | case e1000_82573: | |
1083 | case e1000_82574: | |
1084 | case e1000_82583: | |
bc7f75fa | 1085 | if (hw->mng_cookie.vlan_id != 0) { |
ad68076e BA |
1086 | /* |
1087 | * The VFTA is a 4096b bit-field, each identifying | |
bc7f75fa AK |
1088 | * a single VLAN ID. The following operations |
1089 | * determine which 32b entry (i.e. offset) into the | |
1090 | * array we want to set the VLAN ID (i.e. bit) of | |
1091 | * the manageability unit. | |
1092 | */ | |
1093 | vfta_offset = (hw->mng_cookie.vlan_id >> | |
1094 | E1000_VFTA_ENTRY_SHIFT) & | |
1095 | E1000_VFTA_ENTRY_MASK; | |
1096 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & | |
1097 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); | |
1098 | } | |
8c81c9c3 AD |
1099 | break; |
1100 | default: | |
1101 | break; | |
bc7f75fa AK |
1102 | } |
1103 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { | |
ad68076e BA |
1104 | /* |
1105 | * If the offset we want to clear is the same offset of the | |
bc7f75fa AK |
1106 | * manageability VLAN ID, then clear all bits except that of |
1107 | * the manageability unit. | |
1108 | */ | |
1109 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; | |
1110 | E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); | |
1111 | e1e_flush(); | |
1112 | } | |
1113 | } | |
1114 | ||
4662e82b BA |
1115 | /** |
1116 | * e1000_check_mng_mode_82574 - Check manageability is enabled | |
1117 | * @hw: pointer to the HW structure | |
1118 | * | |
1119 | * Reads the NVM Initialization Control Word 2 and returns true | |
1120 | * (>0) if any manageability is enabled, else false (0). | |
1121 | **/ | |
1122 | static bool e1000_check_mng_mode_82574(struct e1000_hw *hw) | |
1123 | { | |
1124 | u16 data; | |
1125 | ||
1126 | e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data); | |
1127 | return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0; | |
1128 | } | |
1129 | ||
1130 | /** | |
1131 | * e1000_led_on_82574 - Turn LED on | |
1132 | * @hw: pointer to the HW structure | |
1133 | * | |
1134 | * Turn LED on. | |
1135 | **/ | |
1136 | static s32 e1000_led_on_82574(struct e1000_hw *hw) | |
1137 | { | |
1138 | u32 ctrl; | |
1139 | u32 i; | |
1140 | ||
1141 | ctrl = hw->mac.ledctl_mode2; | |
1142 | if (!(E1000_STATUS_LU & er32(STATUS))) { | |
1143 | /* | |
1144 | * If no link, then turn LED on by setting the invert bit | |
1145 | * for each LED that's "on" (0x0E) in ledctl_mode2. | |
1146 | */ | |
1147 | for (i = 0; i < 4; i++) | |
1148 | if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == | |
1149 | E1000_LEDCTL_MODE_LED_ON) | |
1150 | ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8)); | |
1151 | } | |
1152 | ew32(LEDCTL, ctrl); | |
1153 | ||
1154 | return 0; | |
1155 | } | |
1156 | ||
bc7f75fa | 1157 | /** |
e2de3eb6 | 1158 | * e1000_update_mc_addr_list_82571 - Update Multicast addresses |
bc7f75fa AK |
1159 | * @hw: pointer to the HW structure |
1160 | * @mc_addr_list: array of multicast addresses to program | |
1161 | * @mc_addr_count: number of multicast addresses to program | |
1162 | * @rar_used_count: the first RAR register free to program | |
1163 | * @rar_count: total number of supported Receive Address Registers | |
1164 | * | |
1165 | * Updates the Receive Address Registers and Multicast Table Array. | |
1166 | * The caller must have a packed mc_addr_list of multicast addresses. | |
1167 | * The parameter rar_count will usually be hw->mac.rar_entry_count | |
1168 | * unless there are workarounds that change this. | |
1169 | **/ | |
e2de3eb6 | 1170 | static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, |
bc7f75fa AK |
1171 | u8 *mc_addr_list, |
1172 | u32 mc_addr_count, | |
1173 | u32 rar_used_count, | |
1174 | u32 rar_count) | |
1175 | { | |
1176 | if (e1000e_get_laa_state_82571(hw)) | |
1177 | rar_count--; | |
1178 | ||
e2de3eb6 JK |
1179 | e1000e_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, |
1180 | rar_used_count, rar_count); | |
bc7f75fa AK |
1181 | } |
1182 | ||
1183 | /** | |
1184 | * e1000_setup_link_82571 - Setup flow control and link settings | |
1185 | * @hw: pointer to the HW structure | |
1186 | * | |
1187 | * Determines which flow control settings to use, then configures flow | |
1188 | * control. Calls the appropriate media-specific link configuration | |
1189 | * function. Assuming the adapter has a valid link partner, a valid link | |
1190 | * should be established. Assumes the hardware has previously been reset | |
1191 | * and the transmitter and receiver are not enabled. | |
1192 | **/ | |
1193 | static s32 e1000_setup_link_82571(struct e1000_hw *hw) | |
1194 | { | |
ad68076e BA |
1195 | /* |
1196 | * 82573 does not have a word in the NVM to determine | |
bc7f75fa AK |
1197 | * the default flow control setting, so we explicitly |
1198 | * set it to full. | |
1199 | */ | |
8c81c9c3 AD |
1200 | switch (hw->mac.type) { |
1201 | case e1000_82573: | |
1202 | case e1000_82574: | |
1203 | case e1000_82583: | |
1204 | if (hw->fc.requested_mode == e1000_fc_default) | |
1205 | hw->fc.requested_mode = e1000_fc_full; | |
1206 | break; | |
1207 | default: | |
1208 | break; | |
1209 | } | |
bc7f75fa AK |
1210 | |
1211 | return e1000e_setup_link(hw); | |
1212 | } | |
1213 | ||
1214 | /** | |
1215 | * e1000_setup_copper_link_82571 - Configure copper link settings | |
1216 | * @hw: pointer to the HW structure | |
1217 | * | |
1218 | * Configures the link for auto-neg or forced speed and duplex. Then we check | |
1219 | * for link, once link is established calls to configure collision distance | |
1220 | * and flow control are called. | |
1221 | **/ | |
1222 | static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) | |
1223 | { | |
1224 | u32 ctrl; | |
1225 | u32 led_ctrl; | |
1226 | s32 ret_val; | |
1227 | ||
1228 | ctrl = er32(CTRL); | |
1229 | ctrl |= E1000_CTRL_SLU; | |
1230 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1231 | ew32(CTRL, ctrl); | |
1232 | ||
1233 | switch (hw->phy.type) { | |
1234 | case e1000_phy_m88: | |
4662e82b | 1235 | case e1000_phy_bm: |
bc7f75fa AK |
1236 | ret_val = e1000e_copper_link_setup_m88(hw); |
1237 | break; | |
1238 | case e1000_phy_igp_2: | |
1239 | ret_val = e1000e_copper_link_setup_igp(hw); | |
1240 | /* Setup activity LED */ | |
1241 | led_ctrl = er32(LEDCTL); | |
1242 | led_ctrl &= IGP_ACTIVITY_LED_MASK; | |
1243 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); | |
1244 | ew32(LEDCTL, led_ctrl); | |
1245 | break; | |
1246 | default: | |
1247 | return -E1000_ERR_PHY; | |
1248 | break; | |
1249 | } | |
1250 | ||
1251 | if (ret_val) | |
1252 | return ret_val; | |
1253 | ||
1254 | ret_val = e1000e_setup_copper_link(hw); | |
1255 | ||
1256 | return ret_val; | |
1257 | } | |
1258 | ||
1259 | /** | |
1260 | * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes | |
1261 | * @hw: pointer to the HW structure | |
1262 | * | |
1263 | * Configures collision distance and flow control for fiber and serdes links. | |
1264 | * Upon successful setup, poll for link. | |
1265 | **/ | |
1266 | static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) | |
1267 | { | |
1268 | switch (hw->mac.type) { | |
1269 | case e1000_82571: | |
1270 | case e1000_82572: | |
ad68076e BA |
1271 | /* |
1272 | * If SerDes loopback mode is entered, there is no form | |
bc7f75fa AK |
1273 | * of reset to take the adapter out of that mode. So we |
1274 | * have to explicitly take the adapter out of loopback | |
489815ce | 1275 | * mode. This prevents drivers from twiddling their thumbs |
bc7f75fa AK |
1276 | * if another tool failed to take it out of loopback mode. |
1277 | */ | |
ad68076e | 1278 | ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); |
bc7f75fa AK |
1279 | break; |
1280 | default: | |
1281 | break; | |
1282 | } | |
1283 | ||
1284 | return e1000e_setup_fiber_serdes_link(hw); | |
1285 | } | |
1286 | ||
c9523379 | 1287 | /** |
1288 | * e1000_check_for_serdes_link_82571 - Check for link (Serdes) | |
1289 | * @hw: pointer to the HW structure | |
1290 | * | |
1291 | * Checks for link up on the hardware. If link is not up and we have | |
1292 | * a signal, then we need to force link up. | |
1293 | **/ | |
f6370117 | 1294 | static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw) |
c9523379 | 1295 | { |
1296 | struct e1000_mac_info *mac = &hw->mac; | |
1297 | u32 rxcw; | |
1298 | u32 ctrl; | |
1299 | u32 status; | |
1300 | s32 ret_val = 0; | |
1301 | ||
1302 | ctrl = er32(CTRL); | |
1303 | status = er32(STATUS); | |
1304 | rxcw = er32(RXCW); | |
1305 | ||
1306 | if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) { | |
1307 | ||
1308 | /* Receiver is synchronized with no invalid bits. */ | |
1309 | switch (mac->serdes_link_state) { | |
1310 | case e1000_serdes_link_autoneg_complete: | |
1311 | if (!(status & E1000_STATUS_LU)) { | |
1312 | /* | |
1313 | * We have lost link, retry autoneg before | |
1314 | * reporting link failure | |
1315 | */ | |
1316 | mac->serdes_link_state = | |
1317 | e1000_serdes_link_autoneg_progress; | |
1318 | hw_dbg(hw, "AN_UP -> AN_PROG\n"); | |
1319 | } | |
1320 | break; | |
1321 | ||
1322 | case e1000_serdes_link_forced_up: | |
1323 | /* | |
1324 | * If we are receiving /C/ ordered sets, re-enable | |
1325 | * auto-negotiation in the TXCW register and disable | |
1326 | * forced link in the Device Control register in an | |
1327 | * attempt to auto-negotiate with our link partner. | |
1328 | */ | |
1329 | if (rxcw & E1000_RXCW_C) { | |
1330 | /* Enable autoneg, and unforce link up */ | |
1331 | ew32(TXCW, mac->txcw); | |
1332 | ew32(CTRL, | |
1333 | (ctrl & ~E1000_CTRL_SLU)); | |
1334 | mac->serdes_link_state = | |
1335 | e1000_serdes_link_autoneg_progress; | |
1336 | hw_dbg(hw, "FORCED_UP -> AN_PROG\n"); | |
1337 | } | |
1338 | break; | |
1339 | ||
1340 | case e1000_serdes_link_autoneg_progress: | |
1341 | /* | |
1342 | * If the LU bit is set in the STATUS register, | |
1343 | * autoneg has completed sucessfully. If not, | |
1344 | * try foring the link because the far end may be | |
1345 | * available but not capable of autonegotiation. | |
1346 | */ | |
1347 | if (status & E1000_STATUS_LU) { | |
1348 | mac->serdes_link_state = | |
1349 | e1000_serdes_link_autoneg_complete; | |
1350 | hw_dbg(hw, "AN_PROG -> AN_UP\n"); | |
1351 | } else { | |
1352 | /* | |
1353 | * Disable autoneg, force link up and | |
1354 | * full duplex, and change state to forced | |
1355 | */ | |
1356 | ew32(TXCW, | |
1357 | (mac->txcw & ~E1000_TXCW_ANE)); | |
1358 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); | |
1359 | ew32(CTRL, ctrl); | |
1360 | ||
1361 | /* Configure Flow Control after link up. */ | |
1362 | ret_val = | |
1363 | e1000e_config_fc_after_link_up(hw); | |
1364 | if (ret_val) { | |
1365 | hw_dbg(hw, "Error config flow control\n"); | |
1366 | break; | |
1367 | } | |
1368 | mac->serdes_link_state = | |
1369 | e1000_serdes_link_forced_up; | |
1370 | hw_dbg(hw, "AN_PROG -> FORCED_UP\n"); | |
1371 | } | |
1372 | mac->serdes_has_link = true; | |
1373 | break; | |
1374 | ||
1375 | case e1000_serdes_link_down: | |
1376 | default: | |
1377 | /* The link was down but the receiver has now gained | |
1378 | * valid sync, so lets see if we can bring the link | |
1379 | * up. */ | |
1380 | ew32(TXCW, mac->txcw); | |
1381 | ew32(CTRL, | |
1382 | (ctrl & ~E1000_CTRL_SLU)); | |
1383 | mac->serdes_link_state = | |
1384 | e1000_serdes_link_autoneg_progress; | |
1385 | hw_dbg(hw, "DOWN -> AN_PROG\n"); | |
1386 | break; | |
1387 | } | |
1388 | } else { | |
1389 | if (!(rxcw & E1000_RXCW_SYNCH)) { | |
1390 | mac->serdes_has_link = false; | |
1391 | mac->serdes_link_state = e1000_serdes_link_down; | |
1392 | hw_dbg(hw, "ANYSTATE -> DOWN\n"); | |
1393 | } else { | |
1394 | /* | |
1395 | * We have sync, and can tolerate one | |
1396 | * invalid (IV) codeword before declaring | |
1397 | * link down, so reread to look again | |
1398 | */ | |
1399 | udelay(10); | |
1400 | rxcw = er32(RXCW); | |
1401 | if (rxcw & E1000_RXCW_IV) { | |
1402 | mac->serdes_link_state = e1000_serdes_link_down; | |
1403 | mac->serdes_has_link = false; | |
1404 | hw_dbg(hw, "ANYSTATE -> DOWN\n"); | |
1405 | } | |
1406 | } | |
1407 | } | |
1408 | ||
1409 | return ret_val; | |
1410 | } | |
1411 | ||
bc7f75fa AK |
1412 | /** |
1413 | * e1000_valid_led_default_82571 - Verify a valid default LED config | |
1414 | * @hw: pointer to the HW structure | |
1415 | * @data: pointer to the NVM (EEPROM) | |
1416 | * | |
1417 | * Read the EEPROM for the current default LED configuration. If the | |
1418 | * LED configuration is not valid, set to a valid LED configuration. | |
1419 | **/ | |
1420 | static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) | |
1421 | { | |
1422 | s32 ret_val; | |
1423 | ||
1424 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
1425 | if (ret_val) { | |
1426 | hw_dbg(hw, "NVM Read Error\n"); | |
1427 | return ret_val; | |
1428 | } | |
1429 | ||
8c81c9c3 AD |
1430 | switch (hw->mac.type) { |
1431 | case e1000_82573: | |
1432 | case e1000_82574: | |
1433 | case e1000_82583: | |
1434 | if (*data == ID_LED_RESERVED_F746) | |
1435 | *data = ID_LED_DEFAULT_82573; | |
1436 | break; | |
1437 | default: | |
1438 | if (*data == ID_LED_RESERVED_0000 || | |
1439 | *data == ID_LED_RESERVED_FFFF) | |
1440 | *data = ID_LED_DEFAULT; | |
1441 | break; | |
1442 | } | |
bc7f75fa AK |
1443 | |
1444 | return 0; | |
1445 | } | |
1446 | ||
1447 | /** | |
1448 | * e1000e_get_laa_state_82571 - Get locally administered address state | |
1449 | * @hw: pointer to the HW structure | |
1450 | * | |
489815ce | 1451 | * Retrieve and return the current locally administered address state. |
bc7f75fa AK |
1452 | **/ |
1453 | bool e1000e_get_laa_state_82571(struct e1000_hw *hw) | |
1454 | { | |
1455 | if (hw->mac.type != e1000_82571) | |
1456 | return 0; | |
1457 | ||
1458 | return hw->dev_spec.e82571.laa_is_present; | |
1459 | } | |
1460 | ||
1461 | /** | |
1462 | * e1000e_set_laa_state_82571 - Set locally administered address state | |
1463 | * @hw: pointer to the HW structure | |
1464 | * @state: enable/disable locally administered address | |
1465 | * | |
489815ce | 1466 | * Enable/Disable the current locally administers address state. |
bc7f75fa AK |
1467 | **/ |
1468 | void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state) | |
1469 | { | |
1470 | if (hw->mac.type != e1000_82571) | |
1471 | return; | |
1472 | ||
1473 | hw->dev_spec.e82571.laa_is_present = state; | |
1474 | ||
1475 | /* If workaround is activated... */ | |
1476 | if (state) | |
ad68076e BA |
1477 | /* |
1478 | * Hold a copy of the LAA in RAR[14] This is done so that | |
bc7f75fa AK |
1479 | * between the time RAR[0] gets clobbered and the time it |
1480 | * gets fixed, the actual LAA is in one of the RARs and no | |
1481 | * incoming packets directed to this port are dropped. | |
1482 | * Eventually the LAA will be in RAR[0] and RAR[14]. | |
1483 | */ | |
1484 | e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1); | |
1485 | } | |
1486 | ||
1487 | /** | |
1488 | * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum | |
1489 | * @hw: pointer to the HW structure | |
1490 | * | |
1491 | * Verifies that the EEPROM has completed the update. After updating the | |
1492 | * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If | |
1493 | * the checksum fix is not implemented, we need to set the bit and update | |
1494 | * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, | |
1495 | * we need to return bad checksum. | |
1496 | **/ | |
1497 | static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) | |
1498 | { | |
1499 | struct e1000_nvm_info *nvm = &hw->nvm; | |
1500 | s32 ret_val; | |
1501 | u16 data; | |
1502 | ||
1503 | if (nvm->type != e1000_nvm_flash_hw) | |
1504 | return 0; | |
1505 | ||
ad68076e BA |
1506 | /* |
1507 | * Check bit 4 of word 10h. If it is 0, firmware is done updating | |
bc7f75fa AK |
1508 | * 10h-12h. Checksum may need to be fixed. |
1509 | */ | |
1510 | ret_val = e1000_read_nvm(hw, 0x10, 1, &data); | |
1511 | if (ret_val) | |
1512 | return ret_val; | |
1513 | ||
1514 | if (!(data & 0x10)) { | |
ad68076e BA |
1515 | /* |
1516 | * Read 0x23 and check bit 15. This bit is a 1 | |
bc7f75fa AK |
1517 | * when the checksum has already been fixed. If |
1518 | * the checksum is still wrong and this bit is a | |
1519 | * 1, we need to return bad checksum. Otherwise, | |
1520 | * we need to set this bit to a 1 and update the | |
1521 | * checksum. | |
1522 | */ | |
1523 | ret_val = e1000_read_nvm(hw, 0x23, 1, &data); | |
1524 | if (ret_val) | |
1525 | return ret_val; | |
1526 | ||
1527 | if (!(data & 0x8000)) { | |
1528 | data |= 0x8000; | |
1529 | ret_val = e1000_write_nvm(hw, 0x23, 1, &data); | |
1530 | if (ret_val) | |
1531 | return ret_val; | |
1532 | ret_val = e1000e_update_nvm_checksum(hw); | |
1533 | } | |
1534 | } | |
1535 | ||
1536 | return 0; | |
1537 | } | |
1538 | ||
1539 | /** | |
1540 | * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters | |
1541 | * @hw: pointer to the HW structure | |
1542 | * | |
1543 | * Clears the hardware counters by reading the counter registers. | |
1544 | **/ | |
1545 | static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) | |
1546 | { | |
1547 | u32 temp; | |
1548 | ||
1549 | e1000e_clear_hw_cntrs_base(hw); | |
1550 | ||
1551 | temp = er32(PRC64); | |
1552 | temp = er32(PRC127); | |
1553 | temp = er32(PRC255); | |
1554 | temp = er32(PRC511); | |
1555 | temp = er32(PRC1023); | |
1556 | temp = er32(PRC1522); | |
1557 | temp = er32(PTC64); | |
1558 | temp = er32(PTC127); | |
1559 | temp = er32(PTC255); | |
1560 | temp = er32(PTC511); | |
1561 | temp = er32(PTC1023); | |
1562 | temp = er32(PTC1522); | |
1563 | ||
1564 | temp = er32(ALGNERRC); | |
1565 | temp = er32(RXERRC); | |
1566 | temp = er32(TNCRS); | |
1567 | temp = er32(CEXTERR); | |
1568 | temp = er32(TSCTC); | |
1569 | temp = er32(TSCTFC); | |
1570 | ||
1571 | temp = er32(MGTPRC); | |
1572 | temp = er32(MGTPDC); | |
1573 | temp = er32(MGTPTC); | |
1574 | ||
1575 | temp = er32(IAC); | |
1576 | temp = er32(ICRXOC); | |
1577 | ||
1578 | temp = er32(ICRXPTC); | |
1579 | temp = er32(ICRXATC); | |
1580 | temp = er32(ICTXPTC); | |
1581 | temp = er32(ICTXATC); | |
1582 | temp = er32(ICTXQEC); | |
1583 | temp = er32(ICTXQMTC); | |
1584 | temp = er32(ICRXDMTC); | |
1585 | } | |
1586 | ||
1587 | static struct e1000_mac_operations e82571_mac_ops = { | |
4662e82b | 1588 | /* .check_mng_mode: mac type dependent */ |
bc7f75fa | 1589 | /* .check_for_link: media type dependent */ |
a4f58f54 | 1590 | .id_led_init = e1000e_id_led_init, |
bc7f75fa AK |
1591 | .cleanup_led = e1000e_cleanup_led_generic, |
1592 | .clear_hw_cntrs = e1000_clear_hw_cntrs_82571, | |
1593 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1594 | /* .get_link_up_info: media type dependent */ | |
4662e82b | 1595 | /* .led_on: mac type dependent */ |
bc7f75fa | 1596 | .led_off = e1000e_led_off_generic, |
e2de3eb6 | 1597 | .update_mc_addr_list = e1000_update_mc_addr_list_82571, |
bc7f75fa AK |
1598 | .reset_hw = e1000_reset_hw_82571, |
1599 | .init_hw = e1000_init_hw_82571, | |
1600 | .setup_link = e1000_setup_link_82571, | |
1601 | /* .setup_physical_interface: media type dependent */ | |
a4f58f54 | 1602 | .setup_led = e1000e_setup_led_generic, |
bc7f75fa AK |
1603 | }; |
1604 | ||
1605 | static struct e1000_phy_operations e82_phy_ops_igp = { | |
1606 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1607 | .check_reset_block = e1000e_check_reset_block_generic, | |
1608 | .commit_phy = NULL, | |
1609 | .force_speed_duplex = e1000e_phy_force_speed_duplex_igp, | |
1610 | .get_cfg_done = e1000_get_cfg_done_82571, | |
1611 | .get_cable_length = e1000e_get_cable_length_igp_2, | |
1612 | .get_phy_info = e1000e_get_phy_info_igp, | |
1613 | .read_phy_reg = e1000e_read_phy_reg_igp, | |
1614 | .release_phy = e1000_put_hw_semaphore_82571, | |
1615 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1616 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1617 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1618 | .write_phy_reg = e1000e_write_phy_reg_igp, | |
75eb0fad | 1619 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1620 | }; |
1621 | ||
1622 | static struct e1000_phy_operations e82_phy_ops_m88 = { | |
1623 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1624 | .check_reset_block = e1000e_check_reset_block_generic, | |
1625 | .commit_phy = e1000e_phy_sw_reset, | |
1626 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, | |
1627 | .get_cfg_done = e1000e_get_cfg_done, | |
1628 | .get_cable_length = e1000e_get_cable_length_m88, | |
1629 | .get_phy_info = e1000e_get_phy_info_m88, | |
1630 | .read_phy_reg = e1000e_read_phy_reg_m88, | |
1631 | .release_phy = e1000_put_hw_semaphore_82571, | |
1632 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1633 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1634 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1635 | .write_phy_reg = e1000e_write_phy_reg_m88, | |
75eb0fad | 1636 | .cfg_on_link_up = NULL, |
bc7f75fa AK |
1637 | }; |
1638 | ||
4662e82b BA |
1639 | static struct e1000_phy_operations e82_phy_ops_bm = { |
1640 | .acquire_phy = e1000_get_hw_semaphore_82571, | |
1641 | .check_reset_block = e1000e_check_reset_block_generic, | |
1642 | .commit_phy = e1000e_phy_sw_reset, | |
1643 | .force_speed_duplex = e1000e_phy_force_speed_duplex_m88, | |
1644 | .get_cfg_done = e1000e_get_cfg_done, | |
1645 | .get_cable_length = e1000e_get_cable_length_m88, | |
1646 | .get_phy_info = e1000e_get_phy_info_m88, | |
1647 | .read_phy_reg = e1000e_read_phy_reg_bm2, | |
1648 | .release_phy = e1000_put_hw_semaphore_82571, | |
1649 | .reset_phy = e1000e_phy_hw_reset_generic, | |
1650 | .set_d0_lplu_state = e1000_set_d0_lplu_state_82571, | |
1651 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
1652 | .write_phy_reg = e1000e_write_phy_reg_bm2, | |
75eb0fad | 1653 | .cfg_on_link_up = NULL, |
4662e82b BA |
1654 | }; |
1655 | ||
bc7f75fa | 1656 | static struct e1000_nvm_operations e82571_nvm_ops = { |
bc7f75fa AK |
1657 | .acquire_nvm = e1000_acquire_nvm_82571, |
1658 | .read_nvm = e1000e_read_nvm_eerd, | |
1659 | .release_nvm = e1000_release_nvm_82571, | |
1660 | .update_nvm = e1000_update_nvm_checksum_82571, | |
1661 | .valid_led_default = e1000_valid_led_default_82571, | |
1662 | .validate_nvm = e1000_validate_nvm_checksum_82571, | |
1663 | .write_nvm = e1000_write_nvm_82571, | |
1664 | }; | |
1665 | ||
1666 | struct e1000_info e1000_82571_info = { | |
1667 | .mac = e1000_82571, | |
1668 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1669 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1670 | | FLAG_HAS_WOL |
1671 | | FLAG_APME_IN_CTRL3 | |
1672 | | FLAG_RX_CSUM_ENABLED | |
1673 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1674 | | FLAG_HAS_SMART_POWER_DOWN |
1675 | | FLAG_RESET_OVERWRITES_LAA /* errata */ | |
1676 | | FLAG_TARC_SPEED_MODE_BIT /* errata */ | |
1677 | | FLAG_APME_CHECK_PORT_B, | |
1678 | .pba = 38, | |
2adc55c9 | 1679 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1680 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1681 | .mac_ops = &e82571_mac_ops, |
1682 | .phy_ops = &e82_phy_ops_igp, | |
1683 | .nvm_ops = &e82571_nvm_ops, | |
1684 | }; | |
1685 | ||
1686 | struct e1000_info e1000_82572_info = { | |
1687 | .mac = e1000_82572, | |
1688 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1689 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1690 | | FLAG_HAS_WOL |
1691 | | FLAG_APME_IN_CTRL3 | |
1692 | | FLAG_RX_CSUM_ENABLED | |
1693 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1694 | | FLAG_TARC_SPEED_MODE_BIT, /* errata */ |
1695 | .pba = 38, | |
2adc55c9 | 1696 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1697 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1698 | .mac_ops = &e82571_mac_ops, |
1699 | .phy_ops = &e82_phy_ops_igp, | |
1700 | .nvm_ops = &e82571_nvm_ops, | |
1701 | }; | |
1702 | ||
1703 | struct e1000_info e1000_82573_info = { | |
1704 | .mac = e1000_82573, | |
1705 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1706 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1707 | | FLAG_HAS_WOL |
1708 | | FLAG_APME_IN_CTRL3 | |
1709 | | FLAG_RX_CSUM_ENABLED | |
bc7f75fa AK |
1710 | | FLAG_HAS_SMART_POWER_DOWN |
1711 | | FLAG_HAS_AMT | |
bc7f75fa AK |
1712 | | FLAG_HAS_ERT |
1713 | | FLAG_HAS_SWSM_ON_LOAD, | |
1714 | .pba = 20, | |
2adc55c9 | 1715 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 1716 | .get_variants = e1000_get_variants_82571, |
bc7f75fa AK |
1717 | .mac_ops = &e82571_mac_ops, |
1718 | .phy_ops = &e82_phy_ops_m88, | |
31f8c4fe | 1719 | .nvm_ops = &e82571_nvm_ops, |
bc7f75fa AK |
1720 | }; |
1721 | ||
4662e82b BA |
1722 | struct e1000_info e1000_82574_info = { |
1723 | .mac = e1000_82574, | |
1724 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1725 | | FLAG_HAS_MSIX | |
1726 | | FLAG_HAS_JUMBO_FRAMES | |
1727 | | FLAG_HAS_WOL | |
1728 | | FLAG_APME_IN_CTRL3 | |
1729 | | FLAG_RX_CSUM_ENABLED | |
1730 | | FLAG_HAS_SMART_POWER_DOWN | |
1731 | | FLAG_HAS_AMT | |
1732 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1733 | .pba = 20, | |
2adc55c9 | 1734 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
4662e82b BA |
1735 | .get_variants = e1000_get_variants_82571, |
1736 | .mac_ops = &e82571_mac_ops, | |
1737 | .phy_ops = &e82_phy_ops_bm, | |
1738 | .nvm_ops = &e82571_nvm_ops, | |
1739 | }; | |
1740 | ||
8c81c9c3 AD |
1741 | struct e1000_info e1000_82583_info = { |
1742 | .mac = e1000_82583, | |
1743 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1744 | | FLAG_HAS_WOL | |
1745 | | FLAG_APME_IN_CTRL3 | |
1746 | | FLAG_RX_CSUM_ENABLED | |
1747 | | FLAG_HAS_SMART_POWER_DOWN | |
1748 | | FLAG_HAS_AMT | |
1749 | | FLAG_HAS_CTRLEXT_ON_LOAD, | |
1750 | .pba = 20, | |
2adc55c9 | 1751 | .max_hw_frame_size = DEFAULT_JUMBO, |
8c81c9c3 AD |
1752 | .get_variants = e1000_get_variants_82571, |
1753 | .mac_ops = &e82571_mac_ops, | |
1754 | .phy_ops = &e82_phy_ops_bm, | |
1755 | .nvm_ops = &e82571_nvm_ops, | |
1756 | }; | |
1757 |