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e1000e: disable far-end loopback mode on ESB2
[deliverable/linux.git] / drivers / net / e1000e / e1000.h
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
0d6057e4 4 Copyright(c) 1999 - 2011 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _E1000_H_
32#define _E1000_H_
33
86d70e53 34#include <linux/bitops.h>
bc7f75fa
AK		 35#include <linux/types.h>
36#include <linux/timer.h>
37#include <linux/workqueue.h>
38#include <linux/io.h>
39#include <linux/netdevice.h>
d8014dbc 40#include <linux/pci.h>
6f461f6c 41#include <linux/pci-aspm.h>
fe46f58f 42#include <linux/crc32.h>
86d70e53 43#include <linux/if_vlan.h>
bc7f75fa
AK		 44
45#include "hw.h"
46
47struct e1000_info;
48
44defeb3 49#define e_dbg(format, arg...) \
8544b9f7 50 netdev_dbg(hw->adapter->netdev, format, ## arg)
44defeb3 51#define e_err(format, arg...) \
8544b9f7 52 netdev_err(adapter->netdev, format, ## arg)
44defeb3 53#define e_info(format, arg...) \
8544b9f7 54 netdev_info(adapter->netdev, format, ## arg)
44defeb3 55#define e_warn(format, arg...) \
8544b9f7 56 netdev_warn(adapter->netdev, format, ## arg)
44defeb3 57#define e_notice(format, arg...) \
8544b9f7 58 netdev_notice(adapter->netdev, format, ## arg)
bc7f75fa
AK		 59
60
98a1708d 61/* Interrupt modes, as used by the IntMode parameter */
4662e82b
BA		 62#define E1000E_INT_MODE_LEGACY 0
63#define E1000E_INT_MODE_MSI 1
64#define E1000E_INT_MODE_MSIX 2
65
ad68076e 66/* Tx/Rx descriptor defines */
bc7f75fa
AK		 67#define E1000_DEFAULT_TXD 256
68#define E1000_MAX_TXD 4096
7b1be198 69#define E1000_MIN_TXD 64
bc7f75fa
AK		 70
71#define E1000_DEFAULT_RXD 256
72#define E1000_MAX_RXD 4096
7b1be198 73#define E1000_MIN_RXD 64
bc7f75fa 74
de5b3077
AK		 75#define E1000_MIN_ITR_USECS 10 /* 100000 irq/sec */
76#define E1000_MAX_ITR_USECS 10000 /* 100 irq/sec */
77
bc7f75fa
AK		 78/* Early Receive defines */
79#define E1000_ERT_2048 0x100
80
81#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
82
83/* How many Tx Descriptors do we need to call netif_wake_queue ? */
84/* How many Rx Buffers do we bundle into one write to the hardware ? */
85#define E1000_RX_BUFFER_WRITE 16 /* Must be power of 2 */
86
87#define AUTO_ALL_MODES 0
88#define E1000_EEPROM_APME 0x0400
89
90#define E1000_MNG_VLAN_NONE (-1)
91
92/* Number of packet split data buffers (not including the header buffer) */
93#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
94
2adc55c9
BA		 95#define DEFAULT_JUMBO 9234
96
a4f58f54
BA		 97/* BM/HV Specific Registers */
98#define BM_PORT_CTRL_PAGE 769
99
100#define PHY_UPPER_SHIFT 21
101#define BM_PHY_REG(page, reg) \
102 (((reg) & MAX_PHY_REG_ADDRESS) |\
103 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
104 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
105
106/* PHY Wakeup Registers and defines */
107#define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
108#define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
109#define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
110#define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
111#define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
112#define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
113#define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
114#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
115#define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
116
117#define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
118#define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
119#define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
120#define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
121#define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
122#define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
123#define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
124
125#define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
126#define HV_SCC_LOWER PHY_REG(778, 17)
127#define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
128#define HV_ECOL_LOWER PHY_REG(778, 19)
129#define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
130#define HV_MCC_LOWER PHY_REG(778, 21)
131#define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
132#define HV_LATECOL_LOWER PHY_REG(778, 24)
133#define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
134#define HV_COLC_LOWER PHY_REG(778, 26)
135#define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
136#define HV_DC_LOWER PHY_REG(778, 28)
137#define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
138#define HV_TNCRS_LOWER PHY_REG(778, 30)
139
38eb394e
BA		 140#define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */
141
1d5846b9
BA		 142/* BM PHY Copper Specific Status */
143#define BM_CS_STATUS 17
144#define BM_CS_STATUS_LINK_UP 0x0400
145#define BM_CS_STATUS_RESOLVED 0x0800
146#define BM_CS_STATUS_SPEED_MASK 0xC000
147#define BM_CS_STATUS_SPEED_1000 0x8000
148
149/* 82577 Mobile Phy Status Register */
150#define HV_M_STATUS 26
151#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000
152#define HV_M_STATUS_SPEED_MASK 0x0300
153#define HV_M_STATUS_SPEED_1000 0x0200
154#define HV_M_STATUS_LINK_UP 0x0040
155
23606cf5
RW		 156/* Time to wait before putting the device into D3 if there's no link (in ms). */
157#define LINK_TIMEOUT 100
158
3a3b7586
JB		 159#define DEFAULT_RDTR 0
160#define DEFAULT_RADV 8
161#define BURST_RDTR 0x20
162#define BURST_RADV 0x20
163
164/*
165 * in the case of WTHRESH, it appears at least the 82571/2 hardware
166 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
167 * WTHRESH=4, and since we want 64 bytes at a time written back, set
168 * it to 5
169 */
170#define E1000_TXDCTL_DMA_BURST_ENABLE \
171 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
172 E1000_TXDCTL_COUNT_DESC | \
173 (5 << 16) | /* wthresh must be +1 more than desired */\
174 (1 << 8) | /* hthresh */ \
175 0x1f) /* pthresh */
176
177#define E1000_RXDCTL_DMA_BURST_ENABLE \
178 (0x01000000 | /* set descriptor granularity */ \
179 (4 << 16) | /* set writeback threshold */ \
180 (4 << 8) | /* set prefetch threshold */ \
181 0x20) /* set hthresh */
182
183#define E1000_TIDV_FPD (1 << 31)
184#define E1000_RDTR_FPD (1 << 31)
185
bc7f75fa
AK		 186enum e1000_boards {
187 board_82571,
188 board_82572,
189 board_82573,
4662e82b 190 board_82574,
8c81c9c3 191 board_82583,
bc7f75fa
AK		 192 board_80003es2lan,
193 board_ich8lan,
194 board_ich9lan,
f4187b56 195 board_ich10lan,
a4f58f54 196 board_pchlan,
d3738bb8 197 board_pch2lan,
bc7f75fa
AK		 198};
199
200struct e1000_queue_stats {
201 u64 packets;
202 u64 bytes;
203};
204
205struct e1000_ps_page {
206 struct page *page;
207 u64 dma; /* must be u64 - written to hw */
208};
209
210/*
211 * wrappers around a pointer to a socket buffer,
212 * so a DMA handle can be stored along with the buffer
213 */
214struct e1000_buffer {
215 dma_addr_t dma;
216 struct sk_buff *skb;
217 union {
ad68076e 218 /* Tx */
bc7f75fa
AK		 219 struct {
220 unsigned long time_stamp;
221 u16 length;
222 u16 next_to_watch;
9ed318d5
TH		 223 unsigned int segs;
224 unsigned int bytecount;
03b1320d 225 u16 mapped_as_page;
bc7f75fa 226 };
ad68076e 227 /* Rx */
03b1320d
AD		 228 struct {
229 /* arrays of page information for packet split */
230 struct e1000_ps_page *ps_pages;
231 struct page *page;
232 };
bc7f75fa 233 };
bc7f75fa
AK		 234};
235
236struct e1000_ring {
237 void *desc; /* pointer to ring memory */
238 dma_addr_t dma; /* phys address of ring */
239 unsigned int size; /* length of ring in bytes */
240 unsigned int count; /* number of desc. in ring */
241
242 u16 next_to_use;
243 u16 next_to_clean;
244
245 u16 head;
246 u16 tail;
247
248 /* array of buffer information structs */
249 struct e1000_buffer *buffer_info;
250
4662e82b
BA		 251 char name[IFNAMSIZ + 5];
252 u32 ims_val;
253 u32 itr_val;
254 u16 itr_register;
255 int set_itr;
256
bc7f75fa
AK		 257 struct sk_buff *rx_skb_top;
258
259 struct e1000_queue_stats stats;
260};
261
7c25769f
BA		 262/* PHY register snapshot values */
263struct e1000_phy_regs {
264 u16 bmcr; /* basic mode control register */
265 u16 bmsr; /* basic mode status register */
266 u16 advertise; /* auto-negotiation advertisement */
267 u16 lpa; /* link partner ability register */
268 u16 expansion; /* auto-negotiation expansion reg */
269 u16 ctrl1000; /* 1000BASE-T control register */
270 u16 stat1000; /* 1000BASE-T status register */
271 u16 estatus; /* extended status register */
272};
273
bc7f75fa
AK		 274/* board specific private data structure */
275struct e1000_adapter {
276 struct timer_list watchdog_timer;
277 struct timer_list phy_info_timer;
278 struct timer_list blink_timer;
279
280 struct work_struct reset_task;
281 struct work_struct watchdog_task;
282
283 const struct e1000_info *ei;
284
86d70e53 285 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
bc7f75fa
AK		 286 u32 bd_number;
287 u32 rx_buffer_len;
288 u16 mng_vlan_id;
289 u16 link_speed;
290 u16 link_duplex;
84527590 291 u16 eeprom_vers;
bc7f75fa 292
bc7f75fa
AK		 293 /* track device up/down/testing state */
294 unsigned long state;
295
296 /* Interrupt Throttle Rate */
297 u32 itr;
298 u32 itr_setting;
299 u16 tx_itr;
300 u16 rx_itr;
301
302 /*
ad68076e 303 * Tx
bc7f75fa
AK		 304 */
305 struct e1000_ring *tx_ring /* One per active queue */
306 ____cacheline_aligned_in_smp;
307
308 struct napi_struct napi;
309
bc7f75fa
AK		 310 unsigned int restart_queue;
311 u32 txd_cmd;
312
313 bool detect_tx_hung;
314 u8 tx_timeout_factor;
315
316 u32 tx_int_delay;
317 u32 tx_abs_int_delay;
318
319 unsigned int total_tx_bytes;
320 unsigned int total_tx_packets;
321 unsigned int total_rx_bytes;
322 unsigned int total_rx_packets;
323
ad68076e 324 /* Tx stats */
bc7f75fa
AK		 325 u64 tpt_old;
326 u64 colc_old;
7c25769f
BA		 327 u32 gotc;
328 u64 gotc_old;
bc7f75fa
AK		 329 u32 tx_timeout_count;
330 u32 tx_fifo_head;
331 u32 tx_head_addr;
332 u32 tx_fifo_size;
333 u32 tx_dma_failed;
334
335 /*
ad68076e 336 * Rx
bc7f75fa
AK		 337 */
338 bool (*clean_rx) (struct e1000_adapter *adapter,
339 int *work_done, int work_to_do)
340 ____cacheline_aligned_in_smp;
341 void (*alloc_rx_buf) (struct e1000_adapter *adapter,
342 int cleaned_count);
343 struct e1000_ring *rx_ring;
344
345 u32 rx_int_delay;
346 u32 rx_abs_int_delay;
347
ad68076e 348 /* Rx stats */
bc7f75fa
AK		 349 u64 hw_csum_err;
350 u64 hw_csum_good;
351 u64 rx_hdr_split;
7c25769f
BA		 352 u32 gorc;
353 u64 gorc_old;
bc7f75fa
AK		 354 u32 alloc_rx_buff_failed;
355 u32 rx_dma_failed;
356
357 unsigned int rx_ps_pages;
358 u16 rx_ps_bsize0;
318a94d6
JK		 359 u32 max_frame_size;
360 u32 min_frame_size;
bc7f75fa
AK		 361
362 /* OS defined structs */
363 struct net_device *netdev;
364 struct pci_dev *pdev;
bc7f75fa
AK		 365
366 /* structs defined in e1000_hw.h */
367 struct e1000_hw hw;
368
67fd4fcb 369 spinlock_t stats64_lock;
bc7f75fa
AK		 370 struct e1000_hw_stats stats;
371 struct e1000_phy_info phy_info;
372 struct e1000_phy_stats phy_stats;
373
7c25769f
BA		 374 /* Snapshot of PHY registers */
375 struct e1000_phy_regs phy_regs;
376
bc7f75fa
AK		 377 struct e1000_ring test_tx_ring;
378 struct e1000_ring test_rx_ring;
379 u32 test_icr;
380
381 u32 msg_enable;
8e86acd7 382 unsigned int num_vectors;
4662e82b
BA		 383 struct msix_entry *msix_entries;
384 int int_mode;
385 u32 eiac_mask;
bc7f75fa
AK		 386
387 u32 eeprom_wol;
388 u32 wol;
389 u32 pba;
2adc55c9 390 u32 max_hw_frame_size;
bc7f75fa 391
318a94d6 392 bool fc_autoneg;
bc7f75fa 393
bc7f75fa 394 unsigned int flags;
eb7c3adb 395 unsigned int flags2;
a8f88ff5
JB		 396 struct work_struct downshift_task;
397 struct work_struct update_phy_task;
41cec6f1 398 struct work_struct print_hang_task;
23606cf5
RW		 399
400 bool idle_check;
ff10e13c 401 int phy_hang_count;
bc7f75fa
AK		 402};
403
404struct e1000_info {
405 enum e1000_mac_type mac;
406 unsigned int flags;
6f461f6c 407 unsigned int flags2;
bc7f75fa 408 u32 pba;
2adc55c9 409 u32 max_hw_frame_size;
69e3fd8c 410 s32 (*get_variants)(struct e1000_adapter *);
bc7f75fa
AK		 411 struct e1000_mac_operations *mac_ops;
412 struct e1000_phy_operations *phy_ops;
413 struct e1000_nvm_operations *nvm_ops;
414};
415
416/* hardware capability, feature, and workaround flags */
417#define FLAG_HAS_AMT (1 << 0)
418#define FLAG_HAS_FLASH (1 << 1)
419#define FLAG_HAS_HW_VLAN_FILTER (1 << 2)
420#define FLAG_HAS_WOL (1 << 3)
421#define FLAG_HAS_ERT (1 << 4)
422#define FLAG_HAS_CTRLEXT_ON_LOAD (1 << 5)
423#define FLAG_HAS_SWSM_ON_LOAD (1 << 6)
424#define FLAG_HAS_JUMBO_FRAMES (1 << 7)
4a770358 425#define FLAG_READ_ONLY_NVM (1 << 8)
97ac8cae 426#define FLAG_IS_ICH (1 << 9)
4662e82b 427#define FLAG_HAS_MSIX (1 << 10)
bc7f75fa
AK		 428#define FLAG_HAS_SMART_POWER_DOWN (1 << 11)
429#define FLAG_IS_QUAD_PORT_A (1 << 12)
430#define FLAG_IS_QUAD_PORT (1 << 13)
431#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14)
432#define FLAG_APME_IN_WUC (1 << 15)
433#define FLAG_APME_IN_CTRL3 (1 << 16)
434#define FLAG_APME_CHECK_PORT_B (1 << 17)
435#define FLAG_DISABLE_FC_PAUSE_TIME (1 << 18)
436#define FLAG_NO_WAKE_UCAST (1 << 19)
437#define FLAG_MNG_PT_ENABLED (1 << 20)
438#define FLAG_RESET_OVERWRITES_LAA (1 << 21)
439#define FLAG_TARC_SPEED_MODE_BIT (1 << 22)
440#define FLAG_TARC_SET_BIT_ZERO (1 << 23)
441#define FLAG_RX_NEEDS_RESTART (1 << 24)
442#define FLAG_LSC_GIG_SPEED_DROP (1 << 25)
443#define FLAG_SMART_POWER_DOWN (1 << 26)
444#define FLAG_MSI_ENABLED (1 << 27)
445#define FLAG_RX_CSUM_ENABLED (1 << 28)
446#define FLAG_TSO_FORCE (1 << 29)
318a94d6 447#define FLAG_RX_RESTART_NOW (1 << 30)
f8d59f78 448#define FLAG_MSI_TEST_FAILED (1 << 31)
bc7f75fa 449
eb7c3adb
JK		 450/* CRC Stripping defines */
451#define FLAG2_CRC_STRIPPING (1 << 0)
a4f58f54 452#define FLAG2_HAS_PHY_WAKEUP (1 << 1)
b94b5028 453#define FLAG2_IS_DISCARDING (1 << 2)
6f461f6c 454#define FLAG2_DISABLE_ASPM_L1 (1 << 3)
8c7bbb92 455#define FLAG2_HAS_PHY_STATS (1 << 4)
e52997f9 456#define FLAG2_HAS_EEE (1 << 5)
3a3b7586 457#define FLAG2_DMA_BURST (1 << 6)
78cd29d5 458#define FLAG2_DISABLE_ASPM_L0S (1 << 7)
828bac87 459#define FLAG2_DISABLE_AIM (1 << 8)
ff10e13c 460#define FLAG2_CHECK_PHY_HANG (1 << 9)
eb7c3adb 461
bc7f75fa
AK		 462#define E1000_RX_DESC_PS(R, i) \
463 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
464#define E1000_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i]))
465#define E1000_RX_DESC(R, i) E1000_GET_DESC(R, i, e1000_rx_desc)
466#define E1000_TX_DESC(R, i) E1000_GET_DESC(R, i, e1000_tx_desc)
467#define E1000_CONTEXT_DESC(R, i) E1000_GET_DESC(R, i, e1000_context_desc)
468
469enum e1000_state_t {
470 __E1000_TESTING,
471 __E1000_RESETTING,
472 __E1000_DOWN
473};
474
475enum latency_range {
476 lowest_latency = 0,
477 low_latency = 1,
478 bulk_latency = 2,
479 latency_invalid = 255
480};
481
482extern char e1000e_driver_name[];
483extern const char e1000e_driver_version[];
484
485extern void e1000e_check_options(struct e1000_adapter *adapter);
486extern void e1000e_set_ethtool_ops(struct net_device *netdev);
487
488extern int e1000e_up(struct e1000_adapter *adapter);
489extern void e1000e_down(struct e1000_adapter *adapter);
490extern void e1000e_reinit_locked(struct e1000_adapter *adapter);
491extern void e1000e_reset(struct e1000_adapter *adapter);
492extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
493extern int e1000e_setup_rx_resources(struct e1000_adapter *adapter);
494extern int e1000e_setup_tx_resources(struct e1000_adapter *adapter);
495extern void e1000e_free_rx_resources(struct e1000_adapter *adapter);
496extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
67fd4fcb
JK		 497extern struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
498 struct rtnl_link_stats64
499 *stats);
4662e82b
BA		 500extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
501extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
31dbe5b4
BA		 502extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
503extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
bc7f75fa
AK		 504
505extern unsigned int copybreak;
506
507extern char *e1000e_get_hw_dev_name(struct e1000_hw *hw);
508
509extern struct e1000_info e1000_82571_info;
510extern struct e1000_info e1000_82572_info;
511extern struct e1000_info e1000_82573_info;
4662e82b 512extern struct e1000_info e1000_82574_info;
8c81c9c3 513extern struct e1000_info e1000_82583_info;
bc7f75fa
AK		 514extern struct e1000_info e1000_ich8_info;
515extern struct e1000_info e1000_ich9_info;
f4187b56 516extern struct e1000_info e1000_ich10_info;
a4f58f54 517extern struct e1000_info e1000_pch_info;
d3738bb8 518extern struct e1000_info e1000_pch2_info;
bc7f75fa
AK		 519extern struct e1000_info e1000_es2_info;
520
073287c0
BA		 521extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
522 u32 pba_num_size);
bc7f75fa
AK		 523
524extern s32 e1000e_commit_phy(struct e1000_hw *hw);
525
526extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
527
528extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
529extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
530
4a770358 531extern void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 532extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
533 bool state);
534extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
535extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
97ac8cae 536extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
bb436b20 537extern s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
d3738bb8
BA		 538extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
539extern void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 540
541extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
542extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
543extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
a4f58f54 544extern s32 e1000e_setup_led_generic(struct e1000_hw *hw);
bc7f75fa
AK		 545extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
546extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
547extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
548extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
f4d2dd4c
BA		 549extern void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
550extern void e1000_set_lan_id_single_port(struct e1000_hw *hw);
bc7f75fa
AK		 551extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
552extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
553extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
554extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
555extern s32 e1000e_id_led_init(struct e1000_hw *hw);
556extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
557extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
558extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
559extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
560extern s32 e1000e_setup_link(struct e1000_hw *hw);
caaddaf8 561extern void e1000_clear_vfta_generic(struct e1000_hw *hw);
bc7f75fa 562extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
e2de3eb6
JK		 563extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
564 u8 *mc_addr_list,
ab8932f3 565 u32 mc_addr_count);
bc7f75fa
AK		 566extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
567extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
568extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
569extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
570extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
571extern void e1000e_config_collision_dist(struct e1000_hw *hw);
572extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
573extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
dbf80dcb 574extern s32 e1000e_blink_led_generic(struct e1000_hw *hw);
caaddaf8 575extern void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
608f8a0d 576extern s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
bc7f75fa
AK		 577extern void e1000e_reset_adaptive(struct e1000_hw *hw);
578extern void e1000e_update_adaptive(struct e1000_hw *hw);
579
580extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
581extern s32 e1000e_get_phy_id(struct e1000_hw *hw);
582extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
583extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
584extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
585extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
586extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
587extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 588extern s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
589 u16 *data);
bc7f75fa
AK		 590extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
591extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
592extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 593extern s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset,
594 u16 data);
bc7f75fa
AK		 595extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
596extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
597extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
598extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
599extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
600extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
601extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
f4187b56 602extern s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw);
bc7f75fa 603extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
97ac8cae
BA		 604extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
605extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
606extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
4662e82b
BA		 607extern s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
608extern s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa
AK		 609extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
610extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 611extern s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
612 u16 data);
bc7f75fa 613extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 614extern s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset,
615 u16 *data);
bc7f75fa
AK		 616extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
617 u32 usec_interval, bool *success);
618extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
17f208de
BA		 619extern void e1000_power_up_phy_copper(struct e1000_hw *hw);
620extern void e1000_power_down_phy_copper(struct e1000_hw *hw);
2d9498f3
DG		 621extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
622extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
bc7f75fa 623extern s32 e1000e_check_downshift(struct e1000_hw *hw);
a4f58f54 624extern s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
5ccdcecb
BA		 625extern s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
626 u16 *data);
a4f58f54 627extern s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
5ccdcecb
BA		 628extern s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset,
629 u16 data);
a4f58f54
BA		 630extern s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw);
631extern s32 e1000_copper_link_setup_82577(struct e1000_hw *hw);
632extern s32 e1000_check_polarity_82577(struct e1000_hw *hw);
633extern s32 e1000_get_phy_info_82577(struct e1000_hw *hw);
634extern s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
635extern s32 e1000_get_cable_length_82577(struct e1000_hw *hw);
bc7f75fa 636
0be84010
BA		 637extern s32 e1000_check_polarity_m88(struct e1000_hw *hw);
638extern s32 e1000_get_phy_info_ife(struct e1000_hw *hw);
639extern s32 e1000_check_polarity_ife(struct e1000_hw *hw);
640extern s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
641extern s32 e1000_check_polarity_igp(struct e1000_hw *hw);
ff10e13c 642extern bool e1000_check_phy_82574(struct e1000_hw *hw);
0be84010 643
bc7f75fa
AK		 644static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw)
645{
94d8186a 646 return hw->phy.ops.reset(hw);
bc7f75fa
AK		 647}
648
649static inline s32 e1000_check_reset_block(struct e1000_hw *hw)
650{
651 return hw->phy.ops.check_reset_block(hw);
652}
653
654static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
655{
94d8186a 656 return hw->phy.ops.read_reg(hw, offset, data);
bc7f75fa
AK		 657}
658
659static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
660{
94d8186a 661 return hw->phy.ops.write_reg(hw, offset, data);
bc7f75fa
AK		 662}
663
664static inline s32 e1000_get_cable_length(struct e1000_hw *hw)
665{
666 return hw->phy.ops.get_cable_length(hw);
667}
668
669extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
670extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
671extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
672extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
bc7f75fa
AK		 673extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
674extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
675extern void e1000e_release_nvm(struct e1000_hw *hw);
676extern void e1000e_reload_nvm(struct e1000_hw *hw);
608f8a0d
BA		 677extern s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
678
679static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
680{
681 if (hw->mac.ops.read_mac_addr)
682 return hw->mac.ops.read_mac_addr(hw);
683
684 return e1000_read_mac_addr_generic(hw);
685}
bc7f75fa
AK		 686
687static inline s32 e1000_validate_nvm_checksum(struct e1000_hw *hw)
688{
94d8186a 689 return hw->nvm.ops.validate(hw);
bc7f75fa
AK		 690}
691
692static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
693{
94d8186a 694 return hw->nvm.ops.update(hw);
bc7f75fa
AK		 695}
696
697static inline s32 e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
698{
94d8186a 699 return hw->nvm.ops.read(hw, offset, words, data);
bc7f75fa
AK		 700}
701
702static inline s32 e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
703{
94d8186a 704 return hw->nvm.ops.write(hw, offset, words, data);
bc7f75fa
AK		 705}
706
707static inline s32 e1000_get_phy_info(struct e1000_hw *hw)
708{
94d8186a 709 return hw->phy.ops.get_info(hw);
bc7f75fa
AK		 710}
711
4662e82b
BA		 712static inline s32 e1000e_check_mng_mode(struct e1000_hw *hw)
713{
714 return hw->mac.ops.check_mng_mode(hw);
715}
716
717extern bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
bc7f75fa
AK		 718extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
719extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
720
721static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
722{
723 return readl(hw->hw_addr + reg);
724}
725
726static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
727{
728 writel(val, hw->hw_addr + reg);
729}
730
731#endif /* _E1000_H_ */
Linux kernel - Deliverables
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