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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 80003ES2LAN Gigabit Ethernet Controller (Copper) | |
31 | * 80003ES2LAN Gigabit Ethernet Controller (Serdes) | |
32 | */ | |
33 | ||
bc7f75fa AK |
34 | #include "e1000.h" |
35 | ||
36 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 | |
37 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 | |
38 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 | |
2d9498f3 | 39 | #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F |
bc7f75fa AK |
40 | |
41 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 | |
42 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 | |
43 | #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 | |
44 | ||
45 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 | |
46 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 | |
2d9498f3 | 47 | #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 |
bc7f75fa AK |
48 | |
49 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ | |
50 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 | |
51 | ||
52 | #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 | |
53 | #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 | |
54 | ||
55 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ | |
56 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */ | |
57 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 | |
58 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ | |
59 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ | |
60 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ | |
61 | ||
62 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ | |
63 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 | |
64 | /* 1=Reverse Auto-Negotiation */ | |
65 | ||
66 | /* MAC Specific Control Register (Page 2, Register 21) */ | |
67 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ | |
68 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 | |
69 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 | |
70 | #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 | |
71 | #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 | |
72 | ||
73 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ | |
74 | ||
75 | /* DSP Distance Register (Page 5, Register 26) */ | |
76 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M | |
77 | 1 = 50-80M | |
78 | 2 = 80-110M | |
79 | 3 = 110-140M | |
80 | 4 = >140M */ | |
81 | ||
82 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | |
83 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 | |
84 | ||
2d9498f3 DG |
85 | /* Max number of times Kumeran read/write should be validated */ |
86 | #define GG82563_MAX_KMRN_RETRY 0x5 | |
87 | ||
bc7f75fa AK |
88 | /* Power Management Control Register (Page 193, Register 20) */ |
89 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 | |
90 | /* 1=Enable SERDES Electrical Idle */ | |
91 | ||
92 | /* In-Band Control Register (Page 194, Register 18) */ | |
93 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ | |
94 | ||
ad68076e BA |
95 | /* |
96 | * A table for the GG82563 cable length where the range is defined | |
bc7f75fa AK |
97 | * with a lower bound at "index" and the upper bound at |
98 | * "index + 5". | |
99 | */ | |
100 | static const u16 e1000_gg82563_cable_length_table[] = | |
101 | { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; | |
eb656d45 BA |
102 | #define GG82563_CABLE_LENGTH_TABLE_SIZE \ |
103 | ARRAY_SIZE(e1000_gg82563_cable_length_table) | |
bc7f75fa AK |
104 | |
105 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); | |
106 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
107 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
108 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); | |
109 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); | |
110 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); | |
111 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); | |
75eb0fad BA |
112 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); |
113 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
114 | u16 *data); | |
115 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
116 | u16 data); | |
17f208de | 117 | static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); |
bc7f75fa AK |
118 | |
119 | /** | |
120 | * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. | |
121 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
122 | **/ |
123 | static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) | |
124 | { | |
125 | struct e1000_phy_info *phy = &hw->phy; | |
126 | s32 ret_val; | |
127 | ||
318a94d6 | 128 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
129 | phy->type = e1000_phy_none; |
130 | return 0; | |
17f208de BA |
131 | } else { |
132 | phy->ops.power_up = e1000_power_up_phy_copper; | |
133 | phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; | |
bc7f75fa AK |
134 | } |
135 | ||
136 | phy->addr = 1; | |
137 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
138 | phy->reset_delay_us = 100; | |
139 | phy->type = e1000_phy_gg82563; | |
140 | ||
141 | /* This can only be done after all function pointers are setup. */ | |
142 | ret_val = e1000e_get_phy_id(hw); | |
143 | ||
144 | /* Verify phy id */ | |
145 | if (phy->id != GG82563_E_PHY_ID) | |
146 | return -E1000_ERR_PHY; | |
147 | ||
148 | return ret_val; | |
149 | } | |
150 | ||
151 | /** | |
152 | * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. | |
153 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
154 | **/ |
155 | static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) | |
156 | { | |
157 | struct e1000_nvm_info *nvm = &hw->nvm; | |
158 | u32 eecd = er32(EECD); | |
159 | u16 size; | |
160 | ||
161 | nvm->opcode_bits = 8; | |
162 | nvm->delay_usec = 1; | |
163 | switch (nvm->override) { | |
164 | case e1000_nvm_override_spi_large: | |
165 | nvm->page_size = 32; | |
166 | nvm->address_bits = 16; | |
167 | break; | |
168 | case e1000_nvm_override_spi_small: | |
169 | nvm->page_size = 8; | |
170 | nvm->address_bits = 8; | |
171 | break; | |
172 | default: | |
173 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
174 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
175 | break; | |
176 | } | |
177 | ||
ad68076e | 178 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
179 | |
180 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
181 | E1000_EECD_SIZE_EX_SHIFT); | |
182 | ||
ad68076e BA |
183 | /* |
184 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
185 | * for setting word_size. |
186 | */ | |
187 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
188 | |
189 | /* EEPROM access above 16k is unsupported */ | |
190 | if (size > 14) | |
191 | size = 14; | |
bc7f75fa AK |
192 | nvm->word_size = 1 << size; |
193 | ||
194 | return 0; | |
195 | } | |
196 | ||
197 | /** | |
198 | * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. | |
199 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
200 | **/ |
201 | static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) | |
202 | { | |
203 | struct e1000_hw *hw = &adapter->hw; | |
204 | struct e1000_mac_info *mac = &hw->mac; | |
205 | struct e1000_mac_operations *func = &mac->ops; | |
206 | ||
207 | /* Set media type */ | |
208 | switch (adapter->pdev->device) { | |
209 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
318a94d6 | 210 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
211 | break; |
212 | default: | |
318a94d6 | 213 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
214 | break; |
215 | } | |
216 | ||
217 | /* Set mta register count */ | |
218 | mac->mta_reg_count = 128; | |
219 | /* Set rar entry count */ | |
220 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
221 | /* Set if manageability features are enabled. */ | |
564ea9bb BA |
222 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) |
223 | ? true : false; | |
bc7f75fa AK |
224 | |
225 | /* check for link */ | |
318a94d6 | 226 | switch (hw->phy.media_type) { |
bc7f75fa AK |
227 | case e1000_media_type_copper: |
228 | func->setup_physical_interface = e1000_setup_copper_link_80003es2lan; | |
229 | func->check_for_link = e1000e_check_for_copper_link; | |
230 | break; | |
231 | case e1000_media_type_fiber: | |
232 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
233 | func->check_for_link = e1000e_check_for_fiber_link; | |
234 | break; | |
235 | case e1000_media_type_internal_serdes: | |
236 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
237 | func->check_for_link = e1000e_check_for_serdes_link; | |
238 | break; | |
239 | default: | |
240 | return -E1000_ERR_CONFIG; | |
241 | break; | |
242 | } | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
69e3fd8c | 247 | static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
248 | { |
249 | struct e1000_hw *hw = &adapter->hw; | |
250 | s32 rc; | |
251 | ||
252 | rc = e1000_init_mac_params_80003es2lan(adapter); | |
253 | if (rc) | |
254 | return rc; | |
255 | ||
256 | rc = e1000_init_nvm_params_80003es2lan(hw); | |
257 | if (rc) | |
258 | return rc; | |
259 | ||
260 | rc = e1000_init_phy_params_80003es2lan(hw); | |
261 | if (rc) | |
262 | return rc; | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | /** | |
268 | * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY | |
269 | * @hw: pointer to the HW structure | |
270 | * | |
fe401674 | 271 | * A wrapper to acquire access rights to the correct PHY. |
bc7f75fa AK |
272 | **/ |
273 | static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) | |
274 | { | |
275 | u16 mask; | |
276 | ||
277 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
bc7f75fa AK |
278 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); |
279 | } | |
280 | ||
281 | /** | |
282 | * e1000_release_phy_80003es2lan - Release rights to access PHY | |
283 | * @hw: pointer to the HW structure | |
284 | * | |
fe401674 | 285 | * A wrapper to release access rights to the correct PHY. |
bc7f75fa AK |
286 | **/ |
287 | static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) | |
288 | { | |
289 | u16 mask; | |
290 | ||
291 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
75eb0fad BA |
292 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
293 | } | |
294 | ||
295 | /** | |
296 | * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register | |
297 | * @hw: pointer to the HW structure | |
298 | * | |
299 | * Acquire the semaphore to access the Kumeran interface. | |
300 | * | |
301 | **/ | |
302 | static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) | |
303 | { | |
304 | u16 mask; | |
305 | ||
306 | mask = E1000_SWFW_CSR_SM; | |
307 | ||
308 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); | |
309 | } | |
310 | ||
311 | /** | |
312 | * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register | |
313 | * @hw: pointer to the HW structure | |
314 | * | |
315 | * Release the semaphore used to access the Kumeran interface | |
316 | **/ | |
317 | static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) | |
318 | { | |
319 | u16 mask; | |
320 | ||
321 | mask = E1000_SWFW_CSR_SM; | |
2d9498f3 | 322 | |
bc7f75fa AK |
323 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
324 | } | |
325 | ||
326 | /** | |
327 | * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM | |
328 | * @hw: pointer to the HW structure | |
329 | * | |
fe401674 | 330 | * Acquire the semaphore to access the EEPROM. |
bc7f75fa AK |
331 | **/ |
332 | static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) | |
333 | { | |
334 | s32 ret_val; | |
335 | ||
336 | ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
337 | if (ret_val) | |
338 | return ret_val; | |
339 | ||
340 | ret_val = e1000e_acquire_nvm(hw); | |
341 | ||
342 | if (ret_val) | |
343 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
344 | ||
345 | return ret_val; | |
346 | } | |
347 | ||
348 | /** | |
349 | * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM | |
350 | * @hw: pointer to the HW structure | |
351 | * | |
fe401674 | 352 | * Release the semaphore used to access the EEPROM. |
bc7f75fa AK |
353 | **/ |
354 | static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) | |
355 | { | |
356 | e1000e_release_nvm(hw); | |
357 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
358 | } | |
359 | ||
360 | /** | |
361 | * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore | |
362 | * @hw: pointer to the HW structure | |
363 | * @mask: specifies which semaphore to acquire | |
364 | * | |
365 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
366 | * will also specify which port we're acquiring the lock for. | |
367 | **/ | |
368 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
369 | { | |
370 | u32 swfw_sync; | |
371 | u32 swmask = mask; | |
372 | u32 fwmask = mask << 16; | |
373 | s32 i = 0; | |
75eb0fad | 374 | s32 timeout = 50; |
bc7f75fa AK |
375 | |
376 | while (i < timeout) { | |
377 | if (e1000e_get_hw_semaphore(hw)) | |
378 | return -E1000_ERR_SWFW_SYNC; | |
379 | ||
380 | swfw_sync = er32(SW_FW_SYNC); | |
381 | if (!(swfw_sync & (fwmask | swmask))) | |
382 | break; | |
383 | ||
ad68076e BA |
384 | /* |
385 | * Firmware currently using resource (fwmask) | |
386 | * or other software thread using resource (swmask) | |
387 | */ | |
bc7f75fa AK |
388 | e1000e_put_hw_semaphore(hw); |
389 | mdelay(5); | |
390 | i++; | |
391 | } | |
392 | ||
393 | if (i == timeout) { | |
3bb99fe2 | 394 | e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
bc7f75fa AK |
395 | return -E1000_ERR_SWFW_SYNC; |
396 | } | |
397 | ||
398 | swfw_sync |= swmask; | |
399 | ew32(SW_FW_SYNC, swfw_sync); | |
400 | ||
401 | e1000e_put_hw_semaphore(hw); | |
402 | ||
403 | return 0; | |
404 | } | |
405 | ||
406 | /** | |
407 | * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore | |
408 | * @hw: pointer to the HW structure | |
409 | * @mask: specifies which semaphore to acquire | |
410 | * | |
411 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
412 | * will also specify which port we're releasing the lock for. | |
413 | **/ | |
414 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
415 | { | |
416 | u32 swfw_sync; | |
417 | ||
418 | while (e1000e_get_hw_semaphore(hw) != 0); | |
419 | /* Empty */ | |
420 | ||
421 | swfw_sync = er32(SW_FW_SYNC); | |
422 | swfw_sync &= ~mask; | |
423 | ew32(SW_FW_SYNC, swfw_sync); | |
424 | ||
425 | e1000e_put_hw_semaphore(hw); | |
426 | } | |
427 | ||
428 | /** | |
429 | * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register | |
430 | * @hw: pointer to the HW structure | |
431 | * @offset: offset of the register to read | |
432 | * @data: pointer to the data returned from the operation | |
433 | * | |
fe401674 | 434 | * Read the GG82563 PHY register. |
bc7f75fa AK |
435 | **/ |
436 | static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
437 | u32 offset, u16 *data) | |
438 | { | |
439 | s32 ret_val; | |
440 | u32 page_select; | |
441 | u16 temp; | |
442 | ||
2d9498f3 DG |
443 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
444 | if (ret_val) | |
445 | return ret_val; | |
446 | ||
bc7f75fa | 447 | /* Select Configuration Page */ |
2d9498f3 | 448 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 449 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 450 | } else { |
ad68076e BA |
451 | /* |
452 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
453 | * registers 30 and 31 |
454 | */ | |
455 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 456 | } |
bc7f75fa AK |
457 | |
458 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
459 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
460 | if (ret_val) { | |
461 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 462 | return ret_val; |
2d9498f3 | 463 | } |
bc7f75fa | 464 | |
ad68076e BA |
465 | /* |
466 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
467 | * before the device has completed the "Page Select" MDI |
468 | * transaction. So we wait 200us after each MDI command... | |
469 | */ | |
470 | udelay(200); | |
471 | ||
472 | /* ...and verify the command was successful. */ | |
2d9498f3 | 473 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa AK |
474 | |
475 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { | |
476 | ret_val = -E1000_ERR_PHY; | |
2d9498f3 | 477 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
478 | return ret_val; |
479 | } | |
480 | ||
481 | udelay(200); | |
482 | ||
2d9498f3 DG |
483 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
484 | data); | |
bc7f75fa AK |
485 | |
486 | udelay(200); | |
2d9498f3 | 487 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
488 | |
489 | return ret_val; | |
490 | } | |
491 | ||
492 | /** | |
493 | * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register | |
494 | * @hw: pointer to the HW structure | |
495 | * @offset: offset of the register to read | |
496 | * @data: value to write to the register | |
497 | * | |
fe401674 | 498 | * Write to the GG82563 PHY register. |
bc7f75fa AK |
499 | **/ |
500 | static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
501 | u32 offset, u16 data) | |
502 | { | |
503 | s32 ret_val; | |
504 | u32 page_select; | |
505 | u16 temp; | |
506 | ||
2d9498f3 DG |
507 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
508 | if (ret_val) | |
509 | return ret_val; | |
510 | ||
bc7f75fa | 511 | /* Select Configuration Page */ |
2d9498f3 | 512 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 513 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 514 | } else { |
ad68076e BA |
515 | /* |
516 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
517 | * registers 30 and 31 |
518 | */ | |
519 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 520 | } |
bc7f75fa AK |
521 | |
522 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
523 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
524 | if (ret_val) { | |
525 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 526 | return ret_val; |
2d9498f3 | 527 | } |
bc7f75fa AK |
528 | |
529 | ||
ad68076e BA |
530 | /* |
531 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
532 | * before the device has completed the "Page Select" MDI |
533 | * transaction. So we wait 200us after each MDI command... | |
534 | */ | |
535 | udelay(200); | |
536 | ||
537 | /* ...and verify the command was successful. */ | |
2d9498f3 | 538 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa | 539 | |
2d9498f3 DG |
540 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
541 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 542 | return -E1000_ERR_PHY; |
2d9498f3 | 543 | } |
bc7f75fa AK |
544 | |
545 | udelay(200); | |
546 | ||
2d9498f3 DG |
547 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
548 | data); | |
bc7f75fa AK |
549 | |
550 | udelay(200); | |
2d9498f3 | 551 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
552 | |
553 | return ret_val; | |
554 | } | |
555 | ||
556 | /** | |
557 | * e1000_write_nvm_80003es2lan - Write to ESB2 NVM | |
558 | * @hw: pointer to the HW structure | |
559 | * @offset: offset of the register to read | |
560 | * @words: number of words to write | |
561 | * @data: buffer of data to write to the NVM | |
562 | * | |
fe401674 | 563 | * Write "words" of data to the ESB2 NVM. |
bc7f75fa AK |
564 | **/ |
565 | static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, | |
566 | u16 words, u16 *data) | |
567 | { | |
568 | return e1000e_write_nvm_spi(hw, offset, words, data); | |
569 | } | |
570 | ||
571 | /** | |
572 | * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete | |
573 | * @hw: pointer to the HW structure | |
574 | * | |
575 | * Wait a specific amount of time for manageability processes to complete. | |
576 | * This is a function pointer entry point called by the phy module. | |
577 | **/ | |
578 | static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) | |
579 | { | |
580 | s32 timeout = PHY_CFG_TIMEOUT; | |
581 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
582 | ||
583 | if (hw->bus.func == 1) | |
584 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
585 | ||
586 | while (timeout) { | |
587 | if (er32(EEMNGCTL) & mask) | |
588 | break; | |
589 | msleep(1); | |
590 | timeout--; | |
591 | } | |
592 | if (!timeout) { | |
3bb99fe2 | 593 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
594 | return -E1000_ERR_RESET; |
595 | } | |
596 | ||
597 | return 0; | |
598 | } | |
599 | ||
600 | /** | |
601 | * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex | |
602 | * @hw: pointer to the HW structure | |
603 | * | |
604 | * Force the speed and duplex settings onto the PHY. This is a | |
605 | * function pointer entry point called by the phy module. | |
606 | **/ | |
607 | static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) | |
608 | { | |
609 | s32 ret_val; | |
610 | u16 phy_data; | |
611 | bool link; | |
612 | ||
ad68076e BA |
613 | /* |
614 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
615 | * forced whenever speed and duplex are forced. |
616 | */ | |
617 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
618 | if (ret_val) | |
619 | return ret_val; | |
620 | ||
621 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
622 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
623 | if (ret_val) | |
624 | return ret_val; | |
625 | ||
3bb99fe2 | 626 | e_dbg("GG82563 PSCR: %X\n", phy_data); |
bc7f75fa AK |
627 | |
628 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
629 | if (ret_val) | |
630 | return ret_val; | |
631 | ||
632 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
633 | ||
634 | /* Reset the phy to commit changes. */ | |
635 | phy_data |= MII_CR_RESET; | |
636 | ||
637 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
638 | if (ret_val) | |
639 | return ret_val; | |
640 | ||
641 | udelay(1); | |
642 | ||
318a94d6 | 643 | if (hw->phy.autoneg_wait_to_complete) { |
3bb99fe2 | 644 | e_dbg("Waiting for forced speed/duplex link " |
bc7f75fa AK |
645 | "on GG82563 phy.\n"); |
646 | ||
647 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
648 | 100000, &link); | |
649 | if (ret_val) | |
650 | return ret_val; | |
651 | ||
652 | if (!link) { | |
ad68076e BA |
653 | /* |
654 | * We didn't get link. | |
bc7f75fa AK |
655 | * Reset the DSP and cross our fingers. |
656 | */ | |
657 | ret_val = e1000e_phy_reset_dsp(hw); | |
658 | if (ret_val) | |
659 | return ret_val; | |
660 | } | |
661 | ||
662 | /* Try once more */ | |
663 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
664 | 100000, &link); | |
665 | if (ret_val) | |
666 | return ret_val; | |
667 | } | |
668 | ||
669 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
670 | if (ret_val) | |
671 | return ret_val; | |
672 | ||
ad68076e BA |
673 | /* |
674 | * Resetting the phy means we need to verify the TX_CLK corresponds | |
bc7f75fa AK |
675 | * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. |
676 | */ | |
677 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
678 | if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) | |
679 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; | |
680 | else | |
681 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; | |
682 | ||
ad68076e BA |
683 | /* |
684 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
685 | * duplex. |
686 | */ | |
687 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
688 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
689 | ||
690 | return ret_val; | |
691 | } | |
692 | ||
693 | /** | |
694 | * e1000_get_cable_length_80003es2lan - Set approximate cable length | |
695 | * @hw: pointer to the HW structure | |
696 | * | |
697 | * Find the approximate cable length as measured by the GG82563 PHY. | |
698 | * This is a function pointer entry point called by the phy module. | |
699 | **/ | |
700 | static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) | |
701 | { | |
702 | struct e1000_phy_info *phy = &hw->phy; | |
eb656d45 | 703 | s32 ret_val = 0; |
a708dd88 | 704 | u16 phy_data, index; |
bc7f75fa AK |
705 | |
706 | ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); | |
707 | if (ret_val) | |
eb656d45 | 708 | goto out; |
bc7f75fa AK |
709 | |
710 | index = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
eb656d45 BA |
711 | |
712 | if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) { | |
713 | ret_val = -E1000_ERR_PHY; | |
714 | goto out; | |
715 | } | |
716 | ||
bc7f75fa | 717 | phy->min_cable_length = e1000_gg82563_cable_length_table[index]; |
eb656d45 | 718 | phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; |
bc7f75fa AK |
719 | |
720 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
721 | ||
eb656d45 BA |
722 | out: |
723 | return ret_val; | |
bc7f75fa AK |
724 | } |
725 | ||
726 | /** | |
727 | * e1000_get_link_up_info_80003es2lan - Report speed and duplex | |
728 | * @hw: pointer to the HW structure | |
729 | * @speed: pointer to speed buffer | |
730 | * @duplex: pointer to duplex buffer | |
731 | * | |
732 | * Retrieve the current speed and duplex configuration. | |
bc7f75fa AK |
733 | **/ |
734 | static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, | |
735 | u16 *duplex) | |
736 | { | |
737 | s32 ret_val; | |
738 | ||
318a94d6 | 739 | if (hw->phy.media_type == e1000_media_type_copper) { |
bc7f75fa AK |
740 | ret_val = e1000e_get_speed_and_duplex_copper(hw, |
741 | speed, | |
742 | duplex); | |
75eb0fad | 743 | hw->phy.ops.cfg_on_link_up(hw); |
bc7f75fa AK |
744 | } else { |
745 | ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, | |
746 | speed, | |
747 | duplex); | |
748 | } | |
749 | ||
750 | return ret_val; | |
751 | } | |
752 | ||
753 | /** | |
754 | * e1000_reset_hw_80003es2lan - Reset the ESB2 controller | |
755 | * @hw: pointer to the HW structure | |
756 | * | |
757 | * Perform a global reset to the ESB2 controller. | |
bc7f75fa AK |
758 | **/ |
759 | static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) | |
760 | { | |
a708dd88 | 761 | u32 ctrl, icr; |
bc7f75fa AK |
762 | s32 ret_val; |
763 | ||
ad68076e BA |
764 | /* |
765 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
766 | * on the last TLP read/write transaction when MAC is reset. |
767 | */ | |
768 | ret_val = e1000e_disable_pcie_master(hw); | |
769 | if (ret_val) | |
3bb99fe2 | 770 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 771 | |
3bb99fe2 | 772 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
773 | ew32(IMC, 0xffffffff); |
774 | ||
775 | ew32(RCTL, 0); | |
776 | ew32(TCTL, E1000_TCTL_PSP); | |
777 | e1e_flush(); | |
778 | ||
779 | msleep(10); | |
780 | ||
781 | ctrl = er32(CTRL); | |
782 | ||
75eb0fad | 783 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
3bb99fe2 | 784 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa | 785 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
75eb0fad | 786 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
787 | |
788 | ret_val = e1000e_get_auto_rd_done(hw); | |
789 | if (ret_val) | |
790 | /* We don't want to continue accessing MAC registers. */ | |
791 | return ret_val; | |
792 | ||
793 | /* Clear any pending interrupt events. */ | |
794 | ew32(IMC, 0xffffffff); | |
795 | icr = er32(ICR); | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
800 | /** | |
801 | * e1000_init_hw_80003es2lan - Initialize the ESB2 controller | |
802 | * @hw: pointer to the HW structure | |
803 | * | |
804 | * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. | |
bc7f75fa AK |
805 | **/ |
806 | static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) | |
807 | { | |
808 | struct e1000_mac_info *mac = &hw->mac; | |
809 | u32 reg_data; | |
810 | s32 ret_val; | |
811 | u16 i; | |
812 | ||
813 | e1000_initialize_hw_bits_80003es2lan(hw); | |
814 | ||
815 | /* Initialize identification LED */ | |
816 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 817 | if (ret_val) |
3bb99fe2 | 818 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 819 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
820 | |
821 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 822 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 823 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
824 | |
825 | /* Setup the receive address. */ | |
826 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
827 | ||
828 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 829 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
830 | for (i = 0; i < mac->mta_reg_count; i++) |
831 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
832 | ||
833 | /* Setup link and flow control */ | |
834 | ret_val = e1000e_setup_link(hw); | |
835 | ||
836 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 837 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
838 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
839 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 840 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
841 | |
842 | /* ...for both queues. */ | |
e9ec2c0f | 843 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
844 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
845 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 846 | ew32(TXDCTL(1), reg_data); |
bc7f75fa AK |
847 | |
848 | /* Enable retransmit on late collisions */ | |
849 | reg_data = er32(TCTL); | |
850 | reg_data |= E1000_TCTL_RTLC; | |
851 | ew32(TCTL, reg_data); | |
852 | ||
853 | /* Configure Gigabit Carry Extend Padding */ | |
854 | reg_data = er32(TCTL_EXT); | |
855 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
856 | reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; | |
857 | ew32(TCTL_EXT, reg_data); | |
858 | ||
859 | /* Configure Transmit Inter-Packet Gap */ | |
860 | reg_data = er32(TIPG); | |
861 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
862 | reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
863 | ew32(TIPG, reg_data); | |
864 | ||
865 | reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); | |
866 | reg_data &= ~0x00100000; | |
867 | E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); | |
868 | ||
ad68076e BA |
869 | /* |
870 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
871 | * important that we do this after we have tried to establish link |
872 | * because the symbol error count will increment wildly if there | |
873 | * is no link. | |
874 | */ | |
875 | e1000_clear_hw_cntrs_80003es2lan(hw); | |
876 | ||
877 | return ret_val; | |
878 | } | |
879 | ||
880 | /** | |
881 | * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 | |
882 | * @hw: pointer to the HW structure | |
883 | * | |
884 | * Initializes required hardware-dependent bits needed for normal operation. | |
885 | **/ | |
886 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) | |
887 | { | |
888 | u32 reg; | |
889 | ||
890 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 891 | reg = er32(TXDCTL(0)); |
bc7f75fa | 892 | reg |= (1 << 22); |
e9ec2c0f | 893 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
894 | |
895 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 896 | reg = er32(TXDCTL(1)); |
bc7f75fa | 897 | reg |= (1 << 22); |
e9ec2c0f | 898 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
899 | |
900 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 901 | reg = er32(TARC(0)); |
bc7f75fa | 902 | reg &= ~(0xF << 27); /* 30:27 */ |
318a94d6 | 903 | if (hw->phy.media_type != e1000_media_type_copper) |
bc7f75fa | 904 | reg &= ~(1 << 20); |
e9ec2c0f | 905 | ew32(TARC(0), reg); |
bc7f75fa AK |
906 | |
907 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 908 | reg = er32(TARC(1)); |
bc7f75fa AK |
909 | if (er32(TCTL) & E1000_TCTL_MULR) |
910 | reg &= ~(1 << 28); | |
911 | else | |
912 | reg |= (1 << 28); | |
e9ec2c0f | 913 | ew32(TARC(1), reg); |
bc7f75fa AK |
914 | } |
915 | ||
916 | /** | |
917 | * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link | |
918 | * @hw: pointer to the HW structure | |
919 | * | |
920 | * Setup some GG82563 PHY registers for obtaining link | |
921 | **/ | |
922 | static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |
923 | { | |
924 | struct e1000_phy_info *phy = &hw->phy; | |
925 | s32 ret_val; | |
926 | u32 ctrl_ext; | |
75eb0fad | 927 | u16 data; |
bc7f75fa | 928 | |
2d9498f3 | 929 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); |
bc7f75fa AK |
930 | if (ret_val) |
931 | return ret_val; | |
932 | ||
933 | data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
934 | /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ | |
935 | data |= GG82563_MSCR_TX_CLK_1000MBPS_25; | |
936 | ||
2d9498f3 | 937 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); |
bc7f75fa AK |
938 | if (ret_val) |
939 | return ret_val; | |
940 | ||
ad68076e BA |
941 | /* |
942 | * Options: | |
bc7f75fa AK |
943 | * MDI/MDI-X = 0 (default) |
944 | * 0 - Auto for all speeds | |
945 | * 1 - MDI mode | |
946 | * 2 - MDI-X mode | |
947 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
948 | */ | |
949 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); | |
950 | if (ret_val) | |
951 | return ret_val; | |
952 | ||
953 | data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
954 | ||
955 | switch (phy->mdix) { | |
956 | case 1: | |
957 | data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
958 | break; | |
959 | case 2: | |
960 | data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
961 | break; | |
962 | case 0: | |
963 | default: | |
964 | data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
965 | break; | |
966 | } | |
967 | ||
ad68076e BA |
968 | /* |
969 | * Options: | |
bc7f75fa AK |
970 | * disable_polarity_correction = 0 (default) |
971 | * Automatic Correction for Reversed Cable Polarity | |
972 | * 0 - Disabled | |
973 | * 1 - Enabled | |
974 | */ | |
975 | data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
976 | if (phy->disable_polarity_correction) | |
977 | data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
978 | ||
979 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); | |
980 | if (ret_val) | |
981 | return ret_val; | |
982 | ||
983 | /* SW Reset the PHY so all changes take effect */ | |
984 | ret_val = e1000e_commit_phy(hw); | |
985 | if (ret_val) { | |
3bb99fe2 | 986 | e_dbg("Error Resetting the PHY\n"); |
bc7f75fa AK |
987 | return ret_val; |
988 | } | |
989 | ||
ad68076e | 990 | /* Bypass Rx and Tx FIFO's */ |
75eb0fad BA |
991 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
992 | E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, | |
ad68076e | 993 | E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | |
bc7f75fa AK |
994 | E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); |
995 | if (ret_val) | |
996 | return ret_val; | |
997 | ||
75eb0fad | 998 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
999 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
1000 | &data); | |
1001 | if (ret_val) | |
1002 | return ret_val; | |
1003 | data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; | |
75eb0fad | 1004 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
1005 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
1006 | data); | |
1007 | if (ret_val) | |
1008 | return ret_val; | |
1009 | ||
bc7f75fa AK |
1010 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); |
1011 | if (ret_val) | |
1012 | return ret_val; | |
1013 | ||
1014 | data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
1015 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); | |
1016 | if (ret_val) | |
1017 | return ret_val; | |
1018 | ||
1019 | ctrl_ext = er32(CTRL_EXT); | |
1020 | ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
1021 | ew32(CTRL_EXT, ctrl_ext); | |
1022 | ||
1023 | ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); | |
1024 | if (ret_val) | |
1025 | return ret_val; | |
1026 | ||
ad68076e BA |
1027 | /* |
1028 | * Do not init these registers when the HW is in IAMT mode, since the | |
bc7f75fa AK |
1029 | * firmware will have already initialized them. We only initialize |
1030 | * them if the HW is not in IAMT mode. | |
1031 | */ | |
1032 | if (!e1000e_check_mng_mode(hw)) { | |
1033 | /* Enable Electrical Idle on the PHY */ | |
1034 | data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
1035 | ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); | |
1036 | if (ret_val) | |
1037 | return ret_val; | |
1038 | ||
75eb0fad BA |
1039 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); |
1040 | if (ret_val) | |
1041 | return ret_val; | |
bc7f75fa AK |
1042 | |
1043 | data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1044 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); | |
1045 | if (ret_val) | |
1046 | return ret_val; | |
1047 | } | |
1048 | ||
ad68076e BA |
1049 | /* |
1050 | * Workaround: Disable padding in Kumeran interface in the MAC | |
bc7f75fa AK |
1051 | * and in the PHY to avoid CRC errors. |
1052 | */ | |
1053 | ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); | |
1054 | if (ret_val) | |
1055 | return ret_val; | |
1056 | ||
1057 | data |= GG82563_ICR_DIS_PADDING; | |
1058 | ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); | |
1059 | if (ret_val) | |
1060 | return ret_val; | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | /** | |
1066 | * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 | |
1067 | * @hw: pointer to the HW structure | |
1068 | * | |
1069 | * Essentially a wrapper for setting up all things "copper" related. | |
1070 | * This is a function pointer entry point called by the mac module. | |
1071 | **/ | |
1072 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) | |
1073 | { | |
1074 | u32 ctrl; | |
1075 | s32 ret_val; | |
1076 | u16 reg_data; | |
1077 | ||
1078 | ctrl = er32(CTRL); | |
1079 | ctrl |= E1000_CTRL_SLU; | |
1080 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1081 | ew32(CTRL, ctrl); | |
1082 | ||
ad68076e BA |
1083 | /* |
1084 | * Set the mac to wait the maximum time between each | |
bc7f75fa | 1085 | * iteration and increase the max iterations when |
ad68076e BA |
1086 | * polling the phy; this fixes erroneous timeouts at 10Mbps. |
1087 | */ | |
75eb0fad BA |
1088 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), |
1089 | 0xFFFF); | |
bc7f75fa AK |
1090 | if (ret_val) |
1091 | return ret_val; | |
75eb0fad BA |
1092 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
1093 | ®_data); | |
bc7f75fa AK |
1094 | if (ret_val) |
1095 | return ret_val; | |
1096 | reg_data |= 0x3F; | |
75eb0fad BA |
1097 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
1098 | reg_data); | |
bc7f75fa AK |
1099 | if (ret_val) |
1100 | return ret_val; | |
75eb0fad | 1101 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
bc7f75fa AK |
1102 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, |
1103 | ®_data); | |
1104 | if (ret_val) | |
1105 | return ret_val; | |
1106 | reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; | |
75eb0fad BA |
1107 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1108 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, | |
ad68076e | 1109 | reg_data); |
bc7f75fa AK |
1110 | if (ret_val) |
1111 | return ret_val; | |
1112 | ||
1113 | ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); | |
1114 | if (ret_val) | |
1115 | return ret_val; | |
1116 | ||
1117 | ret_val = e1000e_setup_copper_link(hw); | |
1118 | ||
1119 | return 0; | |
1120 | } | |
1121 | ||
75eb0fad BA |
1122 | /** |
1123 | * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up | |
1124 | * @hw: pointer to the HW structure | |
1125 | * @duplex: current duplex setting | |
1126 | * | |
1127 | * Configure the KMRN interface by applying last minute quirks for | |
1128 | * 10/100 operation. | |
1129 | **/ | |
1130 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) | |
1131 | { | |
1132 | s32 ret_val = 0; | |
1133 | u16 speed; | |
1134 | u16 duplex; | |
1135 | ||
1136 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1137 | ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, | |
1138 | &duplex); | |
1139 | if (ret_val) | |
1140 | return ret_val; | |
1141 | ||
1142 | if (speed == SPEED_1000) | |
1143 | ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); | |
1144 | else | |
1145 | ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); | |
1146 | } | |
1147 | ||
1148 | return ret_val; | |
1149 | } | |
1150 | ||
bc7f75fa AK |
1151 | /** |
1152 | * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation | |
1153 | * @hw: pointer to the HW structure | |
1154 | * @duplex: current duplex setting | |
1155 | * | |
1156 | * Configure the KMRN interface by applying last minute quirks for | |
1157 | * 10/100 operation. | |
1158 | **/ | |
1159 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |
1160 | { | |
1161 | s32 ret_val; | |
1162 | u32 tipg; | |
2d9498f3 DG |
1163 | u32 i = 0; |
1164 | u16 reg_data, reg_data2; | |
bc7f75fa AK |
1165 | |
1166 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
75eb0fad BA |
1167 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1168 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1169 | reg_data); | |
bc7f75fa AK |
1170 | if (ret_val) |
1171 | return ret_val; | |
1172 | ||
1173 | /* Configure Transmit Inter-Packet Gap */ | |
1174 | tipg = er32(TIPG); | |
1175 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1176 | tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; | |
1177 | ew32(TIPG, tipg); | |
1178 | ||
2d9498f3 DG |
1179 | do { |
1180 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1181 | if (ret_val) | |
1182 | return ret_val; | |
1183 | ||
1184 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1185 | if (ret_val) | |
1186 | return ret_val; | |
1187 | i++; | |
1188 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1189 | |
1190 | if (duplex == HALF_DUPLEX) | |
1191 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
1192 | else | |
1193 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1194 | ||
1195 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | /** | |
1201 | * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation | |
1202 | * @hw: pointer to the HW structure | |
1203 | * | |
1204 | * Configure the KMRN interface by applying last minute quirks for | |
1205 | * gigabit operation. | |
1206 | **/ | |
1207 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) | |
1208 | { | |
1209 | s32 ret_val; | |
2d9498f3 | 1210 | u16 reg_data, reg_data2; |
bc7f75fa | 1211 | u32 tipg; |
2d9498f3 | 1212 | u32 i = 0; |
bc7f75fa AK |
1213 | |
1214 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; | |
75eb0fad BA |
1215 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1216 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1217 | reg_data); | |
bc7f75fa AK |
1218 | if (ret_val) |
1219 | return ret_val; | |
1220 | ||
1221 | /* Configure Transmit Inter-Packet Gap */ | |
1222 | tipg = er32(TIPG); | |
1223 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1224 | tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
1225 | ew32(TIPG, tipg); | |
1226 | ||
2d9498f3 DG |
1227 | do { |
1228 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1229 | if (ret_val) | |
1230 | return ret_val; | |
1231 | ||
1232 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1233 | if (ret_val) | |
1234 | return ret_val; | |
1235 | i++; | |
1236 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1237 | |
1238 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1239 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1240 | ||
1241 | return ret_val; | |
1242 | } | |
1243 | ||
75eb0fad BA |
1244 | /** |
1245 | * e1000_read_kmrn_reg_80003es2lan - Read kumeran register | |
1246 | * @hw: pointer to the HW structure | |
1247 | * @offset: register offset to be read | |
1248 | * @data: pointer to the read data | |
1249 | * | |
1250 | * Acquire semaphore, then read the PHY register at offset | |
1251 | * using the kumeran interface. The information retrieved is stored in data. | |
1252 | * Release the semaphore before exiting. | |
1253 | **/ | |
fa4c16da HE |
1254 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1255 | u16 *data) | |
75eb0fad BA |
1256 | { |
1257 | u32 kmrnctrlsta; | |
1258 | s32 ret_val = 0; | |
1259 | ||
1260 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1261 | if (ret_val) | |
1262 | return ret_val; | |
1263 | ||
1264 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
1265 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
1266 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
1267 | ||
1268 | udelay(2); | |
1269 | ||
1270 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
1271 | *data = (u16)kmrnctrlsta; | |
1272 | ||
1273 | e1000_release_mac_csr_80003es2lan(hw); | |
1274 | ||
1275 | return ret_val; | |
1276 | } | |
1277 | ||
1278 | /** | |
1279 | * e1000_write_kmrn_reg_80003es2lan - Write kumeran register | |
1280 | * @hw: pointer to the HW structure | |
1281 | * @offset: register offset to write to | |
1282 | * @data: data to write at register offset | |
1283 | * | |
1284 | * Acquire semaphore, then write the data to PHY register | |
1285 | * at the offset using the kumeran interface. Release semaphore | |
1286 | * before exiting. | |
1287 | **/ | |
fa4c16da HE |
1288 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1289 | u16 data) | |
75eb0fad BA |
1290 | { |
1291 | u32 kmrnctrlsta; | |
1292 | s32 ret_val = 0; | |
1293 | ||
1294 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1295 | if (ret_val) | |
1296 | return ret_val; | |
1297 | ||
1298 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
1299 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
1300 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
1301 | ||
1302 | udelay(2); | |
1303 | ||
1304 | e1000_release_mac_csr_80003es2lan(hw); | |
1305 | ||
1306 | return ret_val; | |
1307 | } | |
1308 | ||
17f208de BA |
1309 | /** |
1310 | * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down | |
1311 | * @hw: pointer to the HW structure | |
1312 | * | |
1313 | * In the case of a PHY power down to save power, or to turn off link during a | |
1314 | * driver unload, or wake on lan is not enabled, remove the link. | |
1315 | **/ | |
1316 | static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) | |
1317 | { | |
1318 | /* If the management interface is not enabled, then power down */ | |
1319 | if (!(hw->mac.ops.check_mng_mode(hw) || | |
1320 | hw->phy.ops.check_reset_block(hw))) | |
1321 | e1000_power_down_phy_copper(hw); | |
1322 | ||
1323 | return; | |
1324 | } | |
1325 | ||
bc7f75fa AK |
1326 | /** |
1327 | * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters | |
1328 | * @hw: pointer to the HW structure | |
1329 | * | |
1330 | * Clears the hardware counters by reading the counter registers. | |
1331 | **/ | |
1332 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) | |
1333 | { | |
bc7f75fa AK |
1334 | e1000e_clear_hw_cntrs_base(hw); |
1335 | ||
99673d9b BA |
1336 | er32(PRC64); |
1337 | er32(PRC127); | |
1338 | er32(PRC255); | |
1339 | er32(PRC511); | |
1340 | er32(PRC1023); | |
1341 | er32(PRC1522); | |
1342 | er32(PTC64); | |
1343 | er32(PTC127); | |
1344 | er32(PTC255); | |
1345 | er32(PTC511); | |
1346 | er32(PTC1023); | |
1347 | er32(PTC1522); | |
1348 | ||
1349 | er32(ALGNERRC); | |
1350 | er32(RXERRC); | |
1351 | er32(TNCRS); | |
1352 | er32(CEXTERR); | |
1353 | er32(TSCTC); | |
1354 | er32(TSCTFC); | |
1355 | ||
1356 | er32(MGTPRC); | |
1357 | er32(MGTPDC); | |
1358 | er32(MGTPTC); | |
1359 | ||
1360 | er32(IAC); | |
1361 | er32(ICRXOC); | |
1362 | ||
1363 | er32(ICRXPTC); | |
1364 | er32(ICRXATC); | |
1365 | er32(ICTXPTC); | |
1366 | er32(ICTXATC); | |
1367 | er32(ICTXQEC); | |
1368 | er32(ICTXQMTC); | |
1369 | er32(ICRXDMTC); | |
bc7f75fa AK |
1370 | } |
1371 | ||
1372 | static struct e1000_mac_operations es2_mac_ops = { | |
a4f58f54 | 1373 | .id_led_init = e1000e_id_led_init, |
4662e82b | 1374 | .check_mng_mode = e1000e_check_mng_mode_generic, |
bc7f75fa AK |
1375 | /* check_for_link dependent on media type */ |
1376 | .cleanup_led = e1000e_cleanup_led_generic, | |
1377 | .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, | |
1378 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1379 | .get_link_up_info = e1000_get_link_up_info_80003es2lan, | |
1380 | .led_on = e1000e_led_on_generic, | |
1381 | .led_off = e1000e_led_off_generic, | |
e2de3eb6 | 1382 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1383 | .write_vfta = e1000_write_vfta_generic, |
1384 | .clear_vfta = e1000_clear_vfta_generic, | |
bc7f75fa AK |
1385 | .reset_hw = e1000_reset_hw_80003es2lan, |
1386 | .init_hw = e1000_init_hw_80003es2lan, | |
1387 | .setup_link = e1000e_setup_link, | |
1388 | /* setup_physical_interface dependent on media type */ | |
a4f58f54 | 1389 | .setup_led = e1000e_setup_led_generic, |
bc7f75fa AK |
1390 | }; |
1391 | ||
1392 | static struct e1000_phy_operations es2_phy_ops = { | |
94d8186a | 1393 | .acquire = e1000_acquire_phy_80003es2lan, |
94e5b651 | 1394 | .check_polarity = e1000_check_polarity_m88, |
bc7f75fa | 1395 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1396 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1397 | .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, |
1398 | .get_cfg_done = e1000_get_cfg_done_80003es2lan, | |
1399 | .get_cable_length = e1000_get_cable_length_80003es2lan, | |
94d8186a BA |
1400 | .get_info = e1000e_get_phy_info_m88, |
1401 | .read_reg = e1000_read_phy_reg_gg82563_80003es2lan, | |
1402 | .release = e1000_release_phy_80003es2lan, | |
1403 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1404 | .set_d0_lplu_state = NULL, |
1405 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1406 | .write_reg = e1000_write_phy_reg_gg82563_80003es2lan, |
75eb0fad | 1407 | .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, |
bc7f75fa AK |
1408 | }; |
1409 | ||
1410 | static struct e1000_nvm_operations es2_nvm_ops = { | |
94d8186a BA |
1411 | .acquire = e1000_acquire_nvm_80003es2lan, |
1412 | .read = e1000e_read_nvm_eerd, | |
1413 | .release = e1000_release_nvm_80003es2lan, | |
1414 | .update = e1000e_update_nvm_checksum_generic, | |
bc7f75fa | 1415 | .valid_led_default = e1000e_valid_led_default, |
94d8186a BA |
1416 | .validate = e1000e_validate_nvm_checksum_generic, |
1417 | .write = e1000_write_nvm_80003es2lan, | |
bc7f75fa AK |
1418 | }; |
1419 | ||
1420 | struct e1000_info e1000_es2_info = { | |
1421 | .mac = e1000_80003es2lan, | |
1422 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1423 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1424 | | FLAG_HAS_WOL |
1425 | | FLAG_APME_IN_CTRL3 | |
1426 | | FLAG_RX_CSUM_ENABLED | |
1427 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1428 | | FLAG_RX_NEEDS_RESTART /* errata */ |
1429 | | FLAG_TARC_SET_BIT_ZERO /* errata */ | |
1430 | | FLAG_APME_CHECK_PORT_B | |
1431 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | |
1432 | | FLAG_TIPG_MEDIUM_FOR_80003ESLAN, | |
1433 | .pba = 38, | |
2adc55c9 | 1434 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1435 | .get_variants = e1000_get_variants_80003es2lan, |
bc7f75fa AK |
1436 | .mac_ops = &es2_mac_ops, |
1437 | .phy_ops = &es2_phy_ops, | |
1438 | .nvm_ops = &es2_nvm_ops, | |
1439 | }; | |
1440 |