Commit | Line | Data |
---|---|---|
bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 80003ES2LAN Gigabit Ethernet Controller (Copper) | |
31 | * 80003ES2LAN Gigabit Ethernet Controller (Serdes) | |
32 | */ | |
33 | ||
bc7f75fa AK |
34 | #include "e1000.h" |
35 | ||
36 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 | |
37 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 | |
38 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 | |
2d9498f3 | 39 | #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F |
bc7f75fa AK |
40 | |
41 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 | |
42 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 | |
43 | #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 | |
44 | ||
45 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 | |
46 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 | |
2d9498f3 | 47 | #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 |
bc7f75fa AK |
48 | |
49 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ | |
50 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 | |
51 | ||
52 | #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 | |
53 | #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 | |
54 | ||
55 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ | |
56 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */ | |
57 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 | |
58 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ | |
59 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ | |
60 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ | |
61 | ||
62 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ | |
63 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 | |
64 | /* 1=Reverse Auto-Negotiation */ | |
65 | ||
66 | /* MAC Specific Control Register (Page 2, Register 21) */ | |
67 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ | |
68 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 | |
69 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 | |
70 | #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 | |
71 | #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 | |
72 | ||
73 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ | |
74 | ||
75 | /* DSP Distance Register (Page 5, Register 26) */ | |
76 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M | |
77 | 1 = 50-80M | |
78 | 2 = 80-110M | |
79 | 3 = 110-140M | |
80 | 4 = >140M */ | |
81 | ||
82 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | |
83 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 | |
84 | ||
2d9498f3 DG |
85 | /* Max number of times Kumeran read/write should be validated */ |
86 | #define GG82563_MAX_KMRN_RETRY 0x5 | |
87 | ||
bc7f75fa AK |
88 | /* Power Management Control Register (Page 193, Register 20) */ |
89 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 | |
90 | /* 1=Enable SERDES Electrical Idle */ | |
91 | ||
92 | /* In-Band Control Register (Page 194, Register 18) */ | |
93 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ | |
94 | ||
ad68076e BA |
95 | /* |
96 | * A table for the GG82563 cable length where the range is defined | |
bc7f75fa AK |
97 | * with a lower bound at "index" and the upper bound at |
98 | * "index + 5". | |
99 | */ | |
100 | static const u16 e1000_gg82563_cable_length_table[] = | |
101 | { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; | |
102 | ||
103 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); | |
104 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
105 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
106 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); | |
107 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); | |
108 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); | |
109 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); | |
75eb0fad BA |
110 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); |
111 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
112 | u16 *data); | |
113 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
114 | u16 data); | |
bc7f75fa AK |
115 | |
116 | /** | |
117 | * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. | |
118 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
119 | **/ |
120 | static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) | |
121 | { | |
122 | struct e1000_phy_info *phy = &hw->phy; | |
123 | s32 ret_val; | |
124 | ||
318a94d6 | 125 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
126 | phy->type = e1000_phy_none; |
127 | return 0; | |
128 | } | |
129 | ||
130 | phy->addr = 1; | |
131 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
132 | phy->reset_delay_us = 100; | |
133 | phy->type = e1000_phy_gg82563; | |
134 | ||
135 | /* This can only be done after all function pointers are setup. */ | |
136 | ret_val = e1000e_get_phy_id(hw); | |
137 | ||
138 | /* Verify phy id */ | |
139 | if (phy->id != GG82563_E_PHY_ID) | |
140 | return -E1000_ERR_PHY; | |
141 | ||
142 | return ret_val; | |
143 | } | |
144 | ||
145 | /** | |
146 | * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. | |
147 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
148 | **/ |
149 | static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) | |
150 | { | |
151 | struct e1000_nvm_info *nvm = &hw->nvm; | |
152 | u32 eecd = er32(EECD); | |
153 | u16 size; | |
154 | ||
155 | nvm->opcode_bits = 8; | |
156 | nvm->delay_usec = 1; | |
157 | switch (nvm->override) { | |
158 | case e1000_nvm_override_spi_large: | |
159 | nvm->page_size = 32; | |
160 | nvm->address_bits = 16; | |
161 | break; | |
162 | case e1000_nvm_override_spi_small: | |
163 | nvm->page_size = 8; | |
164 | nvm->address_bits = 8; | |
165 | break; | |
166 | default: | |
167 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
168 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
169 | break; | |
170 | } | |
171 | ||
ad68076e | 172 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
173 | |
174 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
175 | E1000_EECD_SIZE_EX_SHIFT); | |
176 | ||
ad68076e BA |
177 | /* |
178 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
179 | * for setting word_size. |
180 | */ | |
181 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
182 | |
183 | /* EEPROM access above 16k is unsupported */ | |
184 | if (size > 14) | |
185 | size = 14; | |
bc7f75fa AK |
186 | nvm->word_size = 1 << size; |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | /** | |
192 | * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. | |
193 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
194 | **/ |
195 | static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) | |
196 | { | |
197 | struct e1000_hw *hw = &adapter->hw; | |
198 | struct e1000_mac_info *mac = &hw->mac; | |
199 | struct e1000_mac_operations *func = &mac->ops; | |
200 | ||
201 | /* Set media type */ | |
202 | switch (adapter->pdev->device) { | |
203 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
318a94d6 | 204 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
205 | break; |
206 | default: | |
318a94d6 | 207 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
208 | break; |
209 | } | |
210 | ||
211 | /* Set mta register count */ | |
212 | mac->mta_reg_count = 128; | |
213 | /* Set rar entry count */ | |
214 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
215 | /* Set if manageability features are enabled. */ | |
564ea9bb BA |
216 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) |
217 | ? true : false; | |
bc7f75fa AK |
218 | |
219 | /* check for link */ | |
318a94d6 | 220 | switch (hw->phy.media_type) { |
bc7f75fa AK |
221 | case e1000_media_type_copper: |
222 | func->setup_physical_interface = e1000_setup_copper_link_80003es2lan; | |
223 | func->check_for_link = e1000e_check_for_copper_link; | |
224 | break; | |
225 | case e1000_media_type_fiber: | |
226 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
227 | func->check_for_link = e1000e_check_for_fiber_link; | |
228 | break; | |
229 | case e1000_media_type_internal_serdes: | |
230 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
231 | func->check_for_link = e1000e_check_for_serdes_link; | |
232 | break; | |
233 | default: | |
234 | return -E1000_ERR_CONFIG; | |
235 | break; | |
236 | } | |
237 | ||
238 | return 0; | |
239 | } | |
240 | ||
69e3fd8c | 241 | static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
242 | { |
243 | struct e1000_hw *hw = &adapter->hw; | |
244 | s32 rc; | |
245 | ||
246 | rc = e1000_init_mac_params_80003es2lan(adapter); | |
247 | if (rc) | |
248 | return rc; | |
249 | ||
250 | rc = e1000_init_nvm_params_80003es2lan(hw); | |
251 | if (rc) | |
252 | return rc; | |
253 | ||
254 | rc = e1000_init_phy_params_80003es2lan(hw); | |
255 | if (rc) | |
256 | return rc; | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | /** | |
262 | * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY | |
263 | * @hw: pointer to the HW structure | |
264 | * | |
fe401674 | 265 | * A wrapper to acquire access rights to the correct PHY. |
bc7f75fa AK |
266 | **/ |
267 | static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) | |
268 | { | |
269 | u16 mask; | |
270 | ||
271 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
bc7f75fa AK |
272 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); |
273 | } | |
274 | ||
275 | /** | |
276 | * e1000_release_phy_80003es2lan - Release rights to access PHY | |
277 | * @hw: pointer to the HW structure | |
278 | * | |
fe401674 | 279 | * A wrapper to release access rights to the correct PHY. |
bc7f75fa AK |
280 | **/ |
281 | static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) | |
282 | { | |
283 | u16 mask; | |
284 | ||
285 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
75eb0fad BA |
286 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
287 | } | |
288 | ||
289 | /** | |
290 | * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register | |
291 | * @hw: pointer to the HW structure | |
292 | * | |
293 | * Acquire the semaphore to access the Kumeran interface. | |
294 | * | |
295 | **/ | |
296 | static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) | |
297 | { | |
298 | u16 mask; | |
299 | ||
300 | mask = E1000_SWFW_CSR_SM; | |
301 | ||
302 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); | |
303 | } | |
304 | ||
305 | /** | |
306 | * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register | |
307 | * @hw: pointer to the HW structure | |
308 | * | |
309 | * Release the semaphore used to access the Kumeran interface | |
310 | **/ | |
311 | static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) | |
312 | { | |
313 | u16 mask; | |
314 | ||
315 | mask = E1000_SWFW_CSR_SM; | |
2d9498f3 | 316 | |
bc7f75fa AK |
317 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
318 | } | |
319 | ||
320 | /** | |
321 | * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM | |
322 | * @hw: pointer to the HW structure | |
323 | * | |
fe401674 | 324 | * Acquire the semaphore to access the EEPROM. |
bc7f75fa AK |
325 | **/ |
326 | static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) | |
327 | { | |
328 | s32 ret_val; | |
329 | ||
330 | ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
331 | if (ret_val) | |
332 | return ret_val; | |
333 | ||
334 | ret_val = e1000e_acquire_nvm(hw); | |
335 | ||
336 | if (ret_val) | |
337 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
338 | ||
339 | return ret_val; | |
340 | } | |
341 | ||
342 | /** | |
343 | * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM | |
344 | * @hw: pointer to the HW structure | |
345 | * | |
fe401674 | 346 | * Release the semaphore used to access the EEPROM. |
bc7f75fa AK |
347 | **/ |
348 | static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) | |
349 | { | |
350 | e1000e_release_nvm(hw); | |
351 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
352 | } | |
353 | ||
354 | /** | |
355 | * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore | |
356 | * @hw: pointer to the HW structure | |
357 | * @mask: specifies which semaphore to acquire | |
358 | * | |
359 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
360 | * will also specify which port we're acquiring the lock for. | |
361 | **/ | |
362 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
363 | { | |
364 | u32 swfw_sync; | |
365 | u32 swmask = mask; | |
366 | u32 fwmask = mask << 16; | |
367 | s32 i = 0; | |
75eb0fad | 368 | s32 timeout = 50; |
bc7f75fa AK |
369 | |
370 | while (i < timeout) { | |
371 | if (e1000e_get_hw_semaphore(hw)) | |
372 | return -E1000_ERR_SWFW_SYNC; | |
373 | ||
374 | swfw_sync = er32(SW_FW_SYNC); | |
375 | if (!(swfw_sync & (fwmask | swmask))) | |
376 | break; | |
377 | ||
ad68076e BA |
378 | /* |
379 | * Firmware currently using resource (fwmask) | |
380 | * or other software thread using resource (swmask) | |
381 | */ | |
bc7f75fa AK |
382 | e1000e_put_hw_semaphore(hw); |
383 | mdelay(5); | |
384 | i++; | |
385 | } | |
386 | ||
387 | if (i == timeout) { | |
3bb99fe2 | 388 | e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
bc7f75fa AK |
389 | return -E1000_ERR_SWFW_SYNC; |
390 | } | |
391 | ||
392 | swfw_sync |= swmask; | |
393 | ew32(SW_FW_SYNC, swfw_sync); | |
394 | ||
395 | e1000e_put_hw_semaphore(hw); | |
396 | ||
397 | return 0; | |
398 | } | |
399 | ||
400 | /** | |
401 | * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore | |
402 | * @hw: pointer to the HW structure | |
403 | * @mask: specifies which semaphore to acquire | |
404 | * | |
405 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
406 | * will also specify which port we're releasing the lock for. | |
407 | **/ | |
408 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
409 | { | |
410 | u32 swfw_sync; | |
411 | ||
412 | while (e1000e_get_hw_semaphore(hw) != 0); | |
413 | /* Empty */ | |
414 | ||
415 | swfw_sync = er32(SW_FW_SYNC); | |
416 | swfw_sync &= ~mask; | |
417 | ew32(SW_FW_SYNC, swfw_sync); | |
418 | ||
419 | e1000e_put_hw_semaphore(hw); | |
420 | } | |
421 | ||
422 | /** | |
423 | * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register | |
424 | * @hw: pointer to the HW structure | |
425 | * @offset: offset of the register to read | |
426 | * @data: pointer to the data returned from the operation | |
427 | * | |
fe401674 | 428 | * Read the GG82563 PHY register. |
bc7f75fa AK |
429 | **/ |
430 | static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
431 | u32 offset, u16 *data) | |
432 | { | |
433 | s32 ret_val; | |
434 | u32 page_select; | |
435 | u16 temp; | |
436 | ||
2d9498f3 DG |
437 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
438 | if (ret_val) | |
439 | return ret_val; | |
440 | ||
bc7f75fa | 441 | /* Select Configuration Page */ |
2d9498f3 | 442 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 443 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 444 | } else { |
ad68076e BA |
445 | /* |
446 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
447 | * registers 30 and 31 |
448 | */ | |
449 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 450 | } |
bc7f75fa AK |
451 | |
452 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
453 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
454 | if (ret_val) { | |
455 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 456 | return ret_val; |
2d9498f3 | 457 | } |
bc7f75fa | 458 | |
ad68076e BA |
459 | /* |
460 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
461 | * before the device has completed the "Page Select" MDI |
462 | * transaction. So we wait 200us after each MDI command... | |
463 | */ | |
464 | udelay(200); | |
465 | ||
466 | /* ...and verify the command was successful. */ | |
2d9498f3 | 467 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa AK |
468 | |
469 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { | |
470 | ret_val = -E1000_ERR_PHY; | |
2d9498f3 | 471 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
472 | return ret_val; |
473 | } | |
474 | ||
475 | udelay(200); | |
476 | ||
2d9498f3 DG |
477 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
478 | data); | |
bc7f75fa AK |
479 | |
480 | udelay(200); | |
2d9498f3 | 481 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
482 | |
483 | return ret_val; | |
484 | } | |
485 | ||
486 | /** | |
487 | * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register | |
488 | * @hw: pointer to the HW structure | |
489 | * @offset: offset of the register to read | |
490 | * @data: value to write to the register | |
491 | * | |
fe401674 | 492 | * Write to the GG82563 PHY register. |
bc7f75fa AK |
493 | **/ |
494 | static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
495 | u32 offset, u16 data) | |
496 | { | |
497 | s32 ret_val; | |
498 | u32 page_select; | |
499 | u16 temp; | |
500 | ||
2d9498f3 DG |
501 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
502 | if (ret_val) | |
503 | return ret_val; | |
504 | ||
bc7f75fa | 505 | /* Select Configuration Page */ |
2d9498f3 | 506 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 507 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 508 | } else { |
ad68076e BA |
509 | /* |
510 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
511 | * registers 30 and 31 |
512 | */ | |
513 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 514 | } |
bc7f75fa AK |
515 | |
516 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
517 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
518 | if (ret_val) { | |
519 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 520 | return ret_val; |
2d9498f3 | 521 | } |
bc7f75fa AK |
522 | |
523 | ||
ad68076e BA |
524 | /* |
525 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
526 | * before the device has completed the "Page Select" MDI |
527 | * transaction. So we wait 200us after each MDI command... | |
528 | */ | |
529 | udelay(200); | |
530 | ||
531 | /* ...and verify the command was successful. */ | |
2d9498f3 | 532 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa | 533 | |
2d9498f3 DG |
534 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
535 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 536 | return -E1000_ERR_PHY; |
2d9498f3 | 537 | } |
bc7f75fa AK |
538 | |
539 | udelay(200); | |
540 | ||
2d9498f3 DG |
541 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
542 | data); | |
bc7f75fa AK |
543 | |
544 | udelay(200); | |
2d9498f3 | 545 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
546 | |
547 | return ret_val; | |
548 | } | |
549 | ||
550 | /** | |
551 | * e1000_write_nvm_80003es2lan - Write to ESB2 NVM | |
552 | * @hw: pointer to the HW structure | |
553 | * @offset: offset of the register to read | |
554 | * @words: number of words to write | |
555 | * @data: buffer of data to write to the NVM | |
556 | * | |
fe401674 | 557 | * Write "words" of data to the ESB2 NVM. |
bc7f75fa AK |
558 | **/ |
559 | static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, | |
560 | u16 words, u16 *data) | |
561 | { | |
562 | return e1000e_write_nvm_spi(hw, offset, words, data); | |
563 | } | |
564 | ||
565 | /** | |
566 | * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete | |
567 | * @hw: pointer to the HW structure | |
568 | * | |
569 | * Wait a specific amount of time for manageability processes to complete. | |
570 | * This is a function pointer entry point called by the phy module. | |
571 | **/ | |
572 | static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) | |
573 | { | |
574 | s32 timeout = PHY_CFG_TIMEOUT; | |
575 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
576 | ||
577 | if (hw->bus.func == 1) | |
578 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
579 | ||
580 | while (timeout) { | |
581 | if (er32(EEMNGCTL) & mask) | |
582 | break; | |
583 | msleep(1); | |
584 | timeout--; | |
585 | } | |
586 | if (!timeout) { | |
3bb99fe2 | 587 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
588 | return -E1000_ERR_RESET; |
589 | } | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
594 | /** | |
595 | * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex | |
596 | * @hw: pointer to the HW structure | |
597 | * | |
598 | * Force the speed and duplex settings onto the PHY. This is a | |
599 | * function pointer entry point called by the phy module. | |
600 | **/ | |
601 | static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) | |
602 | { | |
603 | s32 ret_val; | |
604 | u16 phy_data; | |
605 | bool link; | |
606 | ||
ad68076e BA |
607 | /* |
608 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
609 | * forced whenever speed and duplex are forced. |
610 | */ | |
611 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
612 | if (ret_val) | |
613 | return ret_val; | |
614 | ||
615 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
616 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
617 | if (ret_val) | |
618 | return ret_val; | |
619 | ||
3bb99fe2 | 620 | e_dbg("GG82563 PSCR: %X\n", phy_data); |
bc7f75fa AK |
621 | |
622 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
623 | if (ret_val) | |
624 | return ret_val; | |
625 | ||
626 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
627 | ||
628 | /* Reset the phy to commit changes. */ | |
629 | phy_data |= MII_CR_RESET; | |
630 | ||
631 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
632 | if (ret_val) | |
633 | return ret_val; | |
634 | ||
635 | udelay(1); | |
636 | ||
318a94d6 | 637 | if (hw->phy.autoneg_wait_to_complete) { |
3bb99fe2 | 638 | e_dbg("Waiting for forced speed/duplex link " |
bc7f75fa AK |
639 | "on GG82563 phy.\n"); |
640 | ||
641 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
642 | 100000, &link); | |
643 | if (ret_val) | |
644 | return ret_val; | |
645 | ||
646 | if (!link) { | |
ad68076e BA |
647 | /* |
648 | * We didn't get link. | |
bc7f75fa AK |
649 | * Reset the DSP and cross our fingers. |
650 | */ | |
651 | ret_val = e1000e_phy_reset_dsp(hw); | |
652 | if (ret_val) | |
653 | return ret_val; | |
654 | } | |
655 | ||
656 | /* Try once more */ | |
657 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
658 | 100000, &link); | |
659 | if (ret_val) | |
660 | return ret_val; | |
661 | } | |
662 | ||
663 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
664 | if (ret_val) | |
665 | return ret_val; | |
666 | ||
ad68076e BA |
667 | /* |
668 | * Resetting the phy means we need to verify the TX_CLK corresponds | |
bc7f75fa AK |
669 | * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. |
670 | */ | |
671 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
672 | if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) | |
673 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; | |
674 | else | |
675 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; | |
676 | ||
ad68076e BA |
677 | /* |
678 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
679 | * duplex. |
680 | */ | |
681 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
682 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
683 | ||
684 | return ret_val; | |
685 | } | |
686 | ||
687 | /** | |
688 | * e1000_get_cable_length_80003es2lan - Set approximate cable length | |
689 | * @hw: pointer to the HW structure | |
690 | * | |
691 | * Find the approximate cable length as measured by the GG82563 PHY. | |
692 | * This is a function pointer entry point called by the phy module. | |
693 | **/ | |
694 | static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) | |
695 | { | |
696 | struct e1000_phy_info *phy = &hw->phy; | |
697 | s32 ret_val; | |
a708dd88 | 698 | u16 phy_data, index; |
bc7f75fa AK |
699 | |
700 | ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); | |
701 | if (ret_val) | |
702 | return ret_val; | |
703 | ||
704 | index = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
705 | phy->min_cable_length = e1000_gg82563_cable_length_table[index]; | |
706 | phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; | |
707 | ||
708 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
713 | /** | |
714 | * e1000_get_link_up_info_80003es2lan - Report speed and duplex | |
715 | * @hw: pointer to the HW structure | |
716 | * @speed: pointer to speed buffer | |
717 | * @duplex: pointer to duplex buffer | |
718 | * | |
719 | * Retrieve the current speed and duplex configuration. | |
bc7f75fa AK |
720 | **/ |
721 | static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, | |
722 | u16 *duplex) | |
723 | { | |
724 | s32 ret_val; | |
725 | ||
318a94d6 | 726 | if (hw->phy.media_type == e1000_media_type_copper) { |
bc7f75fa AK |
727 | ret_val = e1000e_get_speed_and_duplex_copper(hw, |
728 | speed, | |
729 | duplex); | |
75eb0fad | 730 | hw->phy.ops.cfg_on_link_up(hw); |
bc7f75fa AK |
731 | } else { |
732 | ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, | |
733 | speed, | |
734 | duplex); | |
735 | } | |
736 | ||
737 | return ret_val; | |
738 | } | |
739 | ||
740 | /** | |
741 | * e1000_reset_hw_80003es2lan - Reset the ESB2 controller | |
742 | * @hw: pointer to the HW structure | |
743 | * | |
744 | * Perform a global reset to the ESB2 controller. | |
bc7f75fa AK |
745 | **/ |
746 | static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) | |
747 | { | |
a708dd88 | 748 | u32 ctrl, icr; |
bc7f75fa AK |
749 | s32 ret_val; |
750 | ||
ad68076e BA |
751 | /* |
752 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
753 | * on the last TLP read/write transaction when MAC is reset. |
754 | */ | |
755 | ret_val = e1000e_disable_pcie_master(hw); | |
756 | if (ret_val) | |
3bb99fe2 | 757 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 758 | |
3bb99fe2 | 759 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
760 | ew32(IMC, 0xffffffff); |
761 | ||
762 | ew32(RCTL, 0); | |
763 | ew32(TCTL, E1000_TCTL_PSP); | |
764 | e1e_flush(); | |
765 | ||
766 | msleep(10); | |
767 | ||
768 | ctrl = er32(CTRL); | |
769 | ||
75eb0fad | 770 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
3bb99fe2 | 771 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa | 772 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
75eb0fad | 773 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
774 | |
775 | ret_val = e1000e_get_auto_rd_done(hw); | |
776 | if (ret_val) | |
777 | /* We don't want to continue accessing MAC registers. */ | |
778 | return ret_val; | |
779 | ||
780 | /* Clear any pending interrupt events. */ | |
781 | ew32(IMC, 0xffffffff); | |
782 | icr = er32(ICR); | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
787 | /** | |
788 | * e1000_init_hw_80003es2lan - Initialize the ESB2 controller | |
789 | * @hw: pointer to the HW structure | |
790 | * | |
791 | * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. | |
bc7f75fa AK |
792 | **/ |
793 | static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) | |
794 | { | |
795 | struct e1000_mac_info *mac = &hw->mac; | |
796 | u32 reg_data; | |
797 | s32 ret_val; | |
798 | u16 i; | |
799 | ||
800 | e1000_initialize_hw_bits_80003es2lan(hw); | |
801 | ||
802 | /* Initialize identification LED */ | |
803 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 804 | if (ret_val) |
3bb99fe2 | 805 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 806 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
807 | |
808 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 809 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 810 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
811 | |
812 | /* Setup the receive address. */ | |
813 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
814 | ||
815 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 816 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
817 | for (i = 0; i < mac->mta_reg_count; i++) |
818 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
819 | ||
820 | /* Setup link and flow control */ | |
821 | ret_val = e1000e_setup_link(hw); | |
822 | ||
823 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 824 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
825 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
826 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 827 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
828 | |
829 | /* ...for both queues. */ | |
e9ec2c0f | 830 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
831 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
832 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 833 | ew32(TXDCTL(1), reg_data); |
bc7f75fa AK |
834 | |
835 | /* Enable retransmit on late collisions */ | |
836 | reg_data = er32(TCTL); | |
837 | reg_data |= E1000_TCTL_RTLC; | |
838 | ew32(TCTL, reg_data); | |
839 | ||
840 | /* Configure Gigabit Carry Extend Padding */ | |
841 | reg_data = er32(TCTL_EXT); | |
842 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
843 | reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; | |
844 | ew32(TCTL_EXT, reg_data); | |
845 | ||
846 | /* Configure Transmit Inter-Packet Gap */ | |
847 | reg_data = er32(TIPG); | |
848 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
849 | reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
850 | ew32(TIPG, reg_data); | |
851 | ||
852 | reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); | |
853 | reg_data &= ~0x00100000; | |
854 | E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); | |
855 | ||
ad68076e BA |
856 | /* |
857 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
858 | * important that we do this after we have tried to establish link |
859 | * because the symbol error count will increment wildly if there | |
860 | * is no link. | |
861 | */ | |
862 | e1000_clear_hw_cntrs_80003es2lan(hw); | |
863 | ||
864 | return ret_val; | |
865 | } | |
866 | ||
867 | /** | |
868 | * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 | |
869 | * @hw: pointer to the HW structure | |
870 | * | |
871 | * Initializes required hardware-dependent bits needed for normal operation. | |
872 | **/ | |
873 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) | |
874 | { | |
875 | u32 reg; | |
876 | ||
877 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 878 | reg = er32(TXDCTL(0)); |
bc7f75fa | 879 | reg |= (1 << 22); |
e9ec2c0f | 880 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
881 | |
882 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 883 | reg = er32(TXDCTL(1)); |
bc7f75fa | 884 | reg |= (1 << 22); |
e9ec2c0f | 885 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
886 | |
887 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 888 | reg = er32(TARC(0)); |
bc7f75fa | 889 | reg &= ~(0xF << 27); /* 30:27 */ |
318a94d6 | 890 | if (hw->phy.media_type != e1000_media_type_copper) |
bc7f75fa | 891 | reg &= ~(1 << 20); |
e9ec2c0f | 892 | ew32(TARC(0), reg); |
bc7f75fa AK |
893 | |
894 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 895 | reg = er32(TARC(1)); |
bc7f75fa AK |
896 | if (er32(TCTL) & E1000_TCTL_MULR) |
897 | reg &= ~(1 << 28); | |
898 | else | |
899 | reg |= (1 << 28); | |
e9ec2c0f | 900 | ew32(TARC(1), reg); |
bc7f75fa AK |
901 | } |
902 | ||
903 | /** | |
904 | * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link | |
905 | * @hw: pointer to the HW structure | |
906 | * | |
907 | * Setup some GG82563 PHY registers for obtaining link | |
908 | **/ | |
909 | static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |
910 | { | |
911 | struct e1000_phy_info *phy = &hw->phy; | |
912 | s32 ret_val; | |
913 | u32 ctrl_ext; | |
75eb0fad | 914 | u16 data; |
bc7f75fa | 915 | |
2d9498f3 | 916 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); |
bc7f75fa AK |
917 | if (ret_val) |
918 | return ret_val; | |
919 | ||
920 | data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
921 | /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ | |
922 | data |= GG82563_MSCR_TX_CLK_1000MBPS_25; | |
923 | ||
2d9498f3 | 924 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); |
bc7f75fa AK |
925 | if (ret_val) |
926 | return ret_val; | |
927 | ||
ad68076e BA |
928 | /* |
929 | * Options: | |
bc7f75fa AK |
930 | * MDI/MDI-X = 0 (default) |
931 | * 0 - Auto for all speeds | |
932 | * 1 - MDI mode | |
933 | * 2 - MDI-X mode | |
934 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
935 | */ | |
936 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); | |
937 | if (ret_val) | |
938 | return ret_val; | |
939 | ||
940 | data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
941 | ||
942 | switch (phy->mdix) { | |
943 | case 1: | |
944 | data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
945 | break; | |
946 | case 2: | |
947 | data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
948 | break; | |
949 | case 0: | |
950 | default: | |
951 | data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
952 | break; | |
953 | } | |
954 | ||
ad68076e BA |
955 | /* |
956 | * Options: | |
bc7f75fa AK |
957 | * disable_polarity_correction = 0 (default) |
958 | * Automatic Correction for Reversed Cable Polarity | |
959 | * 0 - Disabled | |
960 | * 1 - Enabled | |
961 | */ | |
962 | data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
963 | if (phy->disable_polarity_correction) | |
964 | data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
965 | ||
966 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); | |
967 | if (ret_val) | |
968 | return ret_val; | |
969 | ||
970 | /* SW Reset the PHY so all changes take effect */ | |
971 | ret_val = e1000e_commit_phy(hw); | |
972 | if (ret_val) { | |
3bb99fe2 | 973 | e_dbg("Error Resetting the PHY\n"); |
bc7f75fa AK |
974 | return ret_val; |
975 | } | |
976 | ||
ad68076e | 977 | /* Bypass Rx and Tx FIFO's */ |
75eb0fad BA |
978 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
979 | E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, | |
ad68076e | 980 | E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | |
bc7f75fa AK |
981 | E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); |
982 | if (ret_val) | |
983 | return ret_val; | |
984 | ||
75eb0fad | 985 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
986 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
987 | &data); | |
988 | if (ret_val) | |
989 | return ret_val; | |
990 | data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; | |
75eb0fad | 991 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
992 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
993 | data); | |
994 | if (ret_val) | |
995 | return ret_val; | |
996 | ||
bc7f75fa AK |
997 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); |
998 | if (ret_val) | |
999 | return ret_val; | |
1000 | ||
1001 | data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
1002 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); | |
1003 | if (ret_val) | |
1004 | return ret_val; | |
1005 | ||
1006 | ctrl_ext = er32(CTRL_EXT); | |
1007 | ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
1008 | ew32(CTRL_EXT, ctrl_ext); | |
1009 | ||
1010 | ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); | |
1011 | if (ret_val) | |
1012 | return ret_val; | |
1013 | ||
ad68076e BA |
1014 | /* |
1015 | * Do not init these registers when the HW is in IAMT mode, since the | |
bc7f75fa AK |
1016 | * firmware will have already initialized them. We only initialize |
1017 | * them if the HW is not in IAMT mode. | |
1018 | */ | |
1019 | if (!e1000e_check_mng_mode(hw)) { | |
1020 | /* Enable Electrical Idle on the PHY */ | |
1021 | data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
1022 | ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); | |
1023 | if (ret_val) | |
1024 | return ret_val; | |
1025 | ||
75eb0fad BA |
1026 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); |
1027 | if (ret_val) | |
1028 | return ret_val; | |
bc7f75fa AK |
1029 | |
1030 | data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1031 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); | |
1032 | if (ret_val) | |
1033 | return ret_val; | |
1034 | } | |
1035 | ||
ad68076e BA |
1036 | /* |
1037 | * Workaround: Disable padding in Kumeran interface in the MAC | |
bc7f75fa AK |
1038 | * and in the PHY to avoid CRC errors. |
1039 | */ | |
1040 | ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); | |
1041 | if (ret_val) | |
1042 | return ret_val; | |
1043 | ||
1044 | data |= GG82563_ICR_DIS_PADDING; | |
1045 | ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); | |
1046 | if (ret_val) | |
1047 | return ret_val; | |
1048 | ||
1049 | return 0; | |
1050 | } | |
1051 | ||
1052 | /** | |
1053 | * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 | |
1054 | * @hw: pointer to the HW structure | |
1055 | * | |
1056 | * Essentially a wrapper for setting up all things "copper" related. | |
1057 | * This is a function pointer entry point called by the mac module. | |
1058 | **/ | |
1059 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) | |
1060 | { | |
1061 | u32 ctrl; | |
1062 | s32 ret_val; | |
1063 | u16 reg_data; | |
1064 | ||
1065 | ctrl = er32(CTRL); | |
1066 | ctrl |= E1000_CTRL_SLU; | |
1067 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1068 | ew32(CTRL, ctrl); | |
1069 | ||
ad68076e BA |
1070 | /* |
1071 | * Set the mac to wait the maximum time between each | |
bc7f75fa | 1072 | * iteration and increase the max iterations when |
ad68076e BA |
1073 | * polling the phy; this fixes erroneous timeouts at 10Mbps. |
1074 | */ | |
75eb0fad BA |
1075 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), |
1076 | 0xFFFF); | |
bc7f75fa AK |
1077 | if (ret_val) |
1078 | return ret_val; | |
75eb0fad BA |
1079 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
1080 | ®_data); | |
bc7f75fa AK |
1081 | if (ret_val) |
1082 | return ret_val; | |
1083 | reg_data |= 0x3F; | |
75eb0fad BA |
1084 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
1085 | reg_data); | |
bc7f75fa AK |
1086 | if (ret_val) |
1087 | return ret_val; | |
75eb0fad | 1088 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
bc7f75fa AK |
1089 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, |
1090 | ®_data); | |
1091 | if (ret_val) | |
1092 | return ret_val; | |
1093 | reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; | |
75eb0fad BA |
1094 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1095 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, | |
ad68076e | 1096 | reg_data); |
bc7f75fa AK |
1097 | if (ret_val) |
1098 | return ret_val; | |
1099 | ||
1100 | ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); | |
1101 | if (ret_val) | |
1102 | return ret_val; | |
1103 | ||
1104 | ret_val = e1000e_setup_copper_link(hw); | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
75eb0fad BA |
1109 | /** |
1110 | * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up | |
1111 | * @hw: pointer to the HW structure | |
1112 | * @duplex: current duplex setting | |
1113 | * | |
1114 | * Configure the KMRN interface by applying last minute quirks for | |
1115 | * 10/100 operation. | |
1116 | **/ | |
1117 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) | |
1118 | { | |
1119 | s32 ret_val = 0; | |
1120 | u16 speed; | |
1121 | u16 duplex; | |
1122 | ||
1123 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1124 | ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, | |
1125 | &duplex); | |
1126 | if (ret_val) | |
1127 | return ret_val; | |
1128 | ||
1129 | if (speed == SPEED_1000) | |
1130 | ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); | |
1131 | else | |
1132 | ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); | |
1133 | } | |
1134 | ||
1135 | return ret_val; | |
1136 | } | |
1137 | ||
bc7f75fa AK |
1138 | /** |
1139 | * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation | |
1140 | * @hw: pointer to the HW structure | |
1141 | * @duplex: current duplex setting | |
1142 | * | |
1143 | * Configure the KMRN interface by applying last minute quirks for | |
1144 | * 10/100 operation. | |
1145 | **/ | |
1146 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |
1147 | { | |
1148 | s32 ret_val; | |
1149 | u32 tipg; | |
2d9498f3 DG |
1150 | u32 i = 0; |
1151 | u16 reg_data, reg_data2; | |
bc7f75fa AK |
1152 | |
1153 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
75eb0fad BA |
1154 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1155 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1156 | reg_data); | |
bc7f75fa AK |
1157 | if (ret_val) |
1158 | return ret_val; | |
1159 | ||
1160 | /* Configure Transmit Inter-Packet Gap */ | |
1161 | tipg = er32(TIPG); | |
1162 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1163 | tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; | |
1164 | ew32(TIPG, tipg); | |
1165 | ||
2d9498f3 DG |
1166 | do { |
1167 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1168 | if (ret_val) | |
1169 | return ret_val; | |
1170 | ||
1171 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1172 | if (ret_val) | |
1173 | return ret_val; | |
1174 | i++; | |
1175 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1176 | |
1177 | if (duplex == HALF_DUPLEX) | |
1178 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
1179 | else | |
1180 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1181 | ||
1182 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | /** | |
1188 | * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation | |
1189 | * @hw: pointer to the HW structure | |
1190 | * | |
1191 | * Configure the KMRN interface by applying last minute quirks for | |
1192 | * gigabit operation. | |
1193 | **/ | |
1194 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) | |
1195 | { | |
1196 | s32 ret_val; | |
2d9498f3 | 1197 | u16 reg_data, reg_data2; |
bc7f75fa | 1198 | u32 tipg; |
2d9498f3 | 1199 | u32 i = 0; |
bc7f75fa AK |
1200 | |
1201 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; | |
75eb0fad BA |
1202 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1203 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1204 | reg_data); | |
bc7f75fa AK |
1205 | if (ret_val) |
1206 | return ret_val; | |
1207 | ||
1208 | /* Configure Transmit Inter-Packet Gap */ | |
1209 | tipg = er32(TIPG); | |
1210 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1211 | tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
1212 | ew32(TIPG, tipg); | |
1213 | ||
2d9498f3 DG |
1214 | do { |
1215 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1216 | if (ret_val) | |
1217 | return ret_val; | |
1218 | ||
1219 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1220 | if (ret_val) | |
1221 | return ret_val; | |
1222 | i++; | |
1223 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1224 | |
1225 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1226 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1227 | ||
1228 | return ret_val; | |
1229 | } | |
1230 | ||
75eb0fad BA |
1231 | /** |
1232 | * e1000_read_kmrn_reg_80003es2lan - Read kumeran register | |
1233 | * @hw: pointer to the HW structure | |
1234 | * @offset: register offset to be read | |
1235 | * @data: pointer to the read data | |
1236 | * | |
1237 | * Acquire semaphore, then read the PHY register at offset | |
1238 | * using the kumeran interface. The information retrieved is stored in data. | |
1239 | * Release the semaphore before exiting. | |
1240 | **/ | |
fa4c16da HE |
1241 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1242 | u16 *data) | |
75eb0fad BA |
1243 | { |
1244 | u32 kmrnctrlsta; | |
1245 | s32 ret_val = 0; | |
1246 | ||
1247 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1248 | if (ret_val) | |
1249 | return ret_val; | |
1250 | ||
1251 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
1252 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
1253 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
1254 | ||
1255 | udelay(2); | |
1256 | ||
1257 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
1258 | *data = (u16)kmrnctrlsta; | |
1259 | ||
1260 | e1000_release_mac_csr_80003es2lan(hw); | |
1261 | ||
1262 | return ret_val; | |
1263 | } | |
1264 | ||
1265 | /** | |
1266 | * e1000_write_kmrn_reg_80003es2lan - Write kumeran register | |
1267 | * @hw: pointer to the HW structure | |
1268 | * @offset: register offset to write to | |
1269 | * @data: data to write at register offset | |
1270 | * | |
1271 | * Acquire semaphore, then write the data to PHY register | |
1272 | * at the offset using the kumeran interface. Release semaphore | |
1273 | * before exiting. | |
1274 | **/ | |
fa4c16da HE |
1275 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1276 | u16 data) | |
75eb0fad BA |
1277 | { |
1278 | u32 kmrnctrlsta; | |
1279 | s32 ret_val = 0; | |
1280 | ||
1281 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1282 | if (ret_val) | |
1283 | return ret_val; | |
1284 | ||
1285 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
1286 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
1287 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
1288 | ||
1289 | udelay(2); | |
1290 | ||
1291 | e1000_release_mac_csr_80003es2lan(hw); | |
1292 | ||
1293 | return ret_val; | |
1294 | } | |
1295 | ||
bc7f75fa AK |
1296 | /** |
1297 | * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters | |
1298 | * @hw: pointer to the HW structure | |
1299 | * | |
1300 | * Clears the hardware counters by reading the counter registers. | |
1301 | **/ | |
1302 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) | |
1303 | { | |
bc7f75fa AK |
1304 | e1000e_clear_hw_cntrs_base(hw); |
1305 | ||
99673d9b BA |
1306 | er32(PRC64); |
1307 | er32(PRC127); | |
1308 | er32(PRC255); | |
1309 | er32(PRC511); | |
1310 | er32(PRC1023); | |
1311 | er32(PRC1522); | |
1312 | er32(PTC64); | |
1313 | er32(PTC127); | |
1314 | er32(PTC255); | |
1315 | er32(PTC511); | |
1316 | er32(PTC1023); | |
1317 | er32(PTC1522); | |
1318 | ||
1319 | er32(ALGNERRC); | |
1320 | er32(RXERRC); | |
1321 | er32(TNCRS); | |
1322 | er32(CEXTERR); | |
1323 | er32(TSCTC); | |
1324 | er32(TSCTFC); | |
1325 | ||
1326 | er32(MGTPRC); | |
1327 | er32(MGTPDC); | |
1328 | er32(MGTPTC); | |
1329 | ||
1330 | er32(IAC); | |
1331 | er32(ICRXOC); | |
1332 | ||
1333 | er32(ICRXPTC); | |
1334 | er32(ICRXATC); | |
1335 | er32(ICTXPTC); | |
1336 | er32(ICTXATC); | |
1337 | er32(ICTXQEC); | |
1338 | er32(ICTXQMTC); | |
1339 | er32(ICRXDMTC); | |
bc7f75fa AK |
1340 | } |
1341 | ||
1342 | static struct e1000_mac_operations es2_mac_ops = { | |
a4f58f54 | 1343 | .id_led_init = e1000e_id_led_init, |
4662e82b | 1344 | .check_mng_mode = e1000e_check_mng_mode_generic, |
bc7f75fa AK |
1345 | /* check_for_link dependent on media type */ |
1346 | .cleanup_led = e1000e_cleanup_led_generic, | |
1347 | .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, | |
1348 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1349 | .get_link_up_info = e1000_get_link_up_info_80003es2lan, | |
1350 | .led_on = e1000e_led_on_generic, | |
1351 | .led_off = e1000e_led_off_generic, | |
e2de3eb6 | 1352 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1353 | .write_vfta = e1000_write_vfta_generic, |
1354 | .clear_vfta = e1000_clear_vfta_generic, | |
bc7f75fa AK |
1355 | .reset_hw = e1000_reset_hw_80003es2lan, |
1356 | .init_hw = e1000_init_hw_80003es2lan, | |
1357 | .setup_link = e1000e_setup_link, | |
1358 | /* setup_physical_interface dependent on media type */ | |
a4f58f54 | 1359 | .setup_led = e1000e_setup_led_generic, |
bc7f75fa AK |
1360 | }; |
1361 | ||
1362 | static struct e1000_phy_operations es2_phy_ops = { | |
94d8186a | 1363 | .acquire = e1000_acquire_phy_80003es2lan, |
bc7f75fa | 1364 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1365 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1366 | .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, |
1367 | .get_cfg_done = e1000_get_cfg_done_80003es2lan, | |
1368 | .get_cable_length = e1000_get_cable_length_80003es2lan, | |
94d8186a BA |
1369 | .get_info = e1000e_get_phy_info_m88, |
1370 | .read_reg = e1000_read_phy_reg_gg82563_80003es2lan, | |
1371 | .release = e1000_release_phy_80003es2lan, | |
1372 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1373 | .set_d0_lplu_state = NULL, |
1374 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1375 | .write_reg = e1000_write_phy_reg_gg82563_80003es2lan, |
75eb0fad | 1376 | .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, |
bc7f75fa AK |
1377 | }; |
1378 | ||
1379 | static struct e1000_nvm_operations es2_nvm_ops = { | |
94d8186a BA |
1380 | .acquire = e1000_acquire_nvm_80003es2lan, |
1381 | .read = e1000e_read_nvm_eerd, | |
1382 | .release = e1000_release_nvm_80003es2lan, | |
1383 | .update = e1000e_update_nvm_checksum_generic, | |
bc7f75fa | 1384 | .valid_led_default = e1000e_valid_led_default, |
94d8186a BA |
1385 | .validate = e1000e_validate_nvm_checksum_generic, |
1386 | .write = e1000_write_nvm_80003es2lan, | |
bc7f75fa AK |
1387 | }; |
1388 | ||
1389 | struct e1000_info e1000_es2_info = { | |
1390 | .mac = e1000_80003es2lan, | |
1391 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1392 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1393 | | FLAG_HAS_WOL |
1394 | | FLAG_APME_IN_CTRL3 | |
1395 | | FLAG_RX_CSUM_ENABLED | |
1396 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1397 | | FLAG_RX_NEEDS_RESTART /* errata */ |
1398 | | FLAG_TARC_SET_BIT_ZERO /* errata */ | |
1399 | | FLAG_APME_CHECK_PORT_B | |
1400 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | |
1401 | | FLAG_TIPG_MEDIUM_FOR_80003ESLAN, | |
1402 | .pba = 38, | |
2adc55c9 | 1403 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1404 | .get_variants = e1000_get_variants_80003es2lan, |
bc7f75fa AK |
1405 | .mac_ops = &es2_mac_ops, |
1406 | .phy_ops = &es2_phy_ops, | |
1407 | .nvm_ops = &es2_nvm_ops, | |
1408 | }; | |
1409 |