Commit | Line | Data |
---|---|---|
bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | /* | |
30 | * 80003ES2LAN Gigabit Ethernet Controller (Copper) | |
31 | * 80003ES2LAN Gigabit Ethernet Controller (Serdes) | |
32 | */ | |
33 | ||
bc7f75fa AK |
34 | #include "e1000.h" |
35 | ||
36 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 | |
37 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 | |
38 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 | |
2d9498f3 | 39 | #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F |
bc7f75fa AK |
40 | |
41 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 | |
42 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 | |
43 | #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 | |
44 | ||
45 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 | |
46 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 | |
2d9498f3 | 47 | #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 |
bc7f75fa AK |
48 | |
49 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ | |
50 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 | |
51 | ||
52 | #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 | |
53 | #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 | |
54 | ||
55 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ | |
56 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */ | |
57 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 | |
58 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ | |
59 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ | |
60 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ | |
61 | ||
62 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ | |
63 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 | |
64 | /* 1=Reverse Auto-Negotiation */ | |
65 | ||
66 | /* MAC Specific Control Register (Page 2, Register 21) */ | |
67 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ | |
68 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 | |
69 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 | |
70 | #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 | |
71 | #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 | |
72 | ||
73 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ | |
74 | ||
75 | /* DSP Distance Register (Page 5, Register 26) */ | |
76 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M | |
77 | 1 = 50-80M | |
78 | 2 = 80-110M | |
79 | 3 = 110-140M | |
80 | 4 = >140M */ | |
81 | ||
82 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | |
83 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 | |
84 | ||
2d9498f3 DG |
85 | /* Max number of times Kumeran read/write should be validated */ |
86 | #define GG82563_MAX_KMRN_RETRY 0x5 | |
87 | ||
bc7f75fa AK |
88 | /* Power Management Control Register (Page 193, Register 20) */ |
89 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 | |
90 | /* 1=Enable SERDES Electrical Idle */ | |
91 | ||
92 | /* In-Band Control Register (Page 194, Register 18) */ | |
93 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ | |
94 | ||
ad68076e BA |
95 | /* |
96 | * A table for the GG82563 cable length where the range is defined | |
bc7f75fa AK |
97 | * with a lower bound at "index" and the upper bound at |
98 | * "index + 5". | |
99 | */ | |
100 | static const u16 e1000_gg82563_cable_length_table[] = | |
101 | { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; | |
eb656d45 BA |
102 | #define GG82563_CABLE_LENGTH_TABLE_SIZE \ |
103 | ARRAY_SIZE(e1000_gg82563_cable_length_table) | |
bc7f75fa AK |
104 | |
105 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); | |
106 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
107 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); | |
108 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); | |
109 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); | |
110 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); | |
111 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); | |
75eb0fad BA |
112 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); |
113 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
114 | u16 *data); | |
115 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, | |
116 | u16 data); | |
bc7f75fa AK |
117 | |
118 | /** | |
119 | * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. | |
120 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
121 | **/ |
122 | static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) | |
123 | { | |
124 | struct e1000_phy_info *phy = &hw->phy; | |
125 | s32 ret_val; | |
126 | ||
318a94d6 | 127 | if (hw->phy.media_type != e1000_media_type_copper) { |
bc7f75fa AK |
128 | phy->type = e1000_phy_none; |
129 | return 0; | |
130 | } | |
131 | ||
132 | phy->addr = 1; | |
133 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
134 | phy->reset_delay_us = 100; | |
135 | phy->type = e1000_phy_gg82563; | |
136 | ||
137 | /* This can only be done after all function pointers are setup. */ | |
138 | ret_val = e1000e_get_phy_id(hw); | |
139 | ||
140 | /* Verify phy id */ | |
141 | if (phy->id != GG82563_E_PHY_ID) | |
142 | return -E1000_ERR_PHY; | |
143 | ||
144 | return ret_val; | |
145 | } | |
146 | ||
147 | /** | |
148 | * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. | |
149 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
150 | **/ |
151 | static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) | |
152 | { | |
153 | struct e1000_nvm_info *nvm = &hw->nvm; | |
154 | u32 eecd = er32(EECD); | |
155 | u16 size; | |
156 | ||
157 | nvm->opcode_bits = 8; | |
158 | nvm->delay_usec = 1; | |
159 | switch (nvm->override) { | |
160 | case e1000_nvm_override_spi_large: | |
161 | nvm->page_size = 32; | |
162 | nvm->address_bits = 16; | |
163 | break; | |
164 | case e1000_nvm_override_spi_small: | |
165 | nvm->page_size = 8; | |
166 | nvm->address_bits = 8; | |
167 | break; | |
168 | default: | |
169 | nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; | |
170 | nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; | |
171 | break; | |
172 | } | |
173 | ||
ad68076e | 174 | nvm->type = e1000_nvm_eeprom_spi; |
bc7f75fa AK |
175 | |
176 | size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> | |
177 | E1000_EECD_SIZE_EX_SHIFT); | |
178 | ||
ad68076e BA |
179 | /* |
180 | * Added to a constant, "size" becomes the left-shift value | |
bc7f75fa AK |
181 | * for setting word_size. |
182 | */ | |
183 | size += NVM_WORD_SIZE_BASE_SHIFT; | |
8d7c294c JK |
184 | |
185 | /* EEPROM access above 16k is unsupported */ | |
186 | if (size > 14) | |
187 | size = 14; | |
bc7f75fa AK |
188 | nvm->word_size = 1 << size; |
189 | ||
190 | return 0; | |
191 | } | |
192 | ||
193 | /** | |
194 | * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. | |
195 | * @hw: pointer to the HW structure | |
bc7f75fa AK |
196 | **/ |
197 | static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter) | |
198 | { | |
199 | struct e1000_hw *hw = &adapter->hw; | |
200 | struct e1000_mac_info *mac = &hw->mac; | |
201 | struct e1000_mac_operations *func = &mac->ops; | |
202 | ||
203 | /* Set media type */ | |
204 | switch (adapter->pdev->device) { | |
205 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: | |
318a94d6 | 206 | hw->phy.media_type = e1000_media_type_internal_serdes; |
bc7f75fa AK |
207 | break; |
208 | default: | |
318a94d6 | 209 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
210 | break; |
211 | } | |
212 | ||
213 | /* Set mta register count */ | |
214 | mac->mta_reg_count = 128; | |
215 | /* Set rar entry count */ | |
216 | mac->rar_entry_count = E1000_RAR_ENTRIES; | |
217 | /* Set if manageability features are enabled. */ | |
564ea9bb BA |
218 | mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) |
219 | ? true : false; | |
bc7f75fa AK |
220 | |
221 | /* check for link */ | |
318a94d6 | 222 | switch (hw->phy.media_type) { |
bc7f75fa AK |
223 | case e1000_media_type_copper: |
224 | func->setup_physical_interface = e1000_setup_copper_link_80003es2lan; | |
225 | func->check_for_link = e1000e_check_for_copper_link; | |
226 | break; | |
227 | case e1000_media_type_fiber: | |
228 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
229 | func->check_for_link = e1000e_check_for_fiber_link; | |
230 | break; | |
231 | case e1000_media_type_internal_serdes: | |
232 | func->setup_physical_interface = e1000e_setup_fiber_serdes_link; | |
233 | func->check_for_link = e1000e_check_for_serdes_link; | |
234 | break; | |
235 | default: | |
236 | return -E1000_ERR_CONFIG; | |
237 | break; | |
238 | } | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
69e3fd8c | 243 | static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
244 | { |
245 | struct e1000_hw *hw = &adapter->hw; | |
246 | s32 rc; | |
247 | ||
248 | rc = e1000_init_mac_params_80003es2lan(adapter); | |
249 | if (rc) | |
250 | return rc; | |
251 | ||
252 | rc = e1000_init_nvm_params_80003es2lan(hw); | |
253 | if (rc) | |
254 | return rc; | |
255 | ||
256 | rc = e1000_init_phy_params_80003es2lan(hw); | |
257 | if (rc) | |
258 | return rc; | |
259 | ||
260 | return 0; | |
261 | } | |
262 | ||
263 | /** | |
264 | * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY | |
265 | * @hw: pointer to the HW structure | |
266 | * | |
fe401674 | 267 | * A wrapper to acquire access rights to the correct PHY. |
bc7f75fa AK |
268 | **/ |
269 | static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) | |
270 | { | |
271 | u16 mask; | |
272 | ||
273 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
bc7f75fa AK |
274 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); |
275 | } | |
276 | ||
277 | /** | |
278 | * e1000_release_phy_80003es2lan - Release rights to access PHY | |
279 | * @hw: pointer to the HW structure | |
280 | * | |
fe401674 | 281 | * A wrapper to release access rights to the correct PHY. |
bc7f75fa AK |
282 | **/ |
283 | static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) | |
284 | { | |
285 | u16 mask; | |
286 | ||
287 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | |
75eb0fad BA |
288 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
289 | } | |
290 | ||
291 | /** | |
292 | * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register | |
293 | * @hw: pointer to the HW structure | |
294 | * | |
295 | * Acquire the semaphore to access the Kumeran interface. | |
296 | * | |
297 | **/ | |
298 | static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) | |
299 | { | |
300 | u16 mask; | |
301 | ||
302 | mask = E1000_SWFW_CSR_SM; | |
303 | ||
304 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); | |
305 | } | |
306 | ||
307 | /** | |
308 | * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register | |
309 | * @hw: pointer to the HW structure | |
310 | * | |
311 | * Release the semaphore used to access the Kumeran interface | |
312 | **/ | |
313 | static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) | |
314 | { | |
315 | u16 mask; | |
316 | ||
317 | mask = E1000_SWFW_CSR_SM; | |
2d9498f3 | 318 | |
bc7f75fa AK |
319 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
320 | } | |
321 | ||
322 | /** | |
323 | * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM | |
324 | * @hw: pointer to the HW structure | |
325 | * | |
fe401674 | 326 | * Acquire the semaphore to access the EEPROM. |
bc7f75fa AK |
327 | **/ |
328 | static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) | |
329 | { | |
330 | s32 ret_val; | |
331 | ||
332 | ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
333 | if (ret_val) | |
334 | return ret_val; | |
335 | ||
336 | ret_val = e1000e_acquire_nvm(hw); | |
337 | ||
338 | if (ret_val) | |
339 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
340 | ||
341 | return ret_val; | |
342 | } | |
343 | ||
344 | /** | |
345 | * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM | |
346 | * @hw: pointer to the HW structure | |
347 | * | |
fe401674 | 348 | * Release the semaphore used to access the EEPROM. |
bc7f75fa AK |
349 | **/ |
350 | static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) | |
351 | { | |
352 | e1000e_release_nvm(hw); | |
353 | e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); | |
354 | } | |
355 | ||
356 | /** | |
357 | * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore | |
358 | * @hw: pointer to the HW structure | |
359 | * @mask: specifies which semaphore to acquire | |
360 | * | |
361 | * Acquire the SW/FW semaphore to access the PHY or NVM. The mask | |
362 | * will also specify which port we're acquiring the lock for. | |
363 | **/ | |
364 | static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
365 | { | |
366 | u32 swfw_sync; | |
367 | u32 swmask = mask; | |
368 | u32 fwmask = mask << 16; | |
369 | s32 i = 0; | |
75eb0fad | 370 | s32 timeout = 50; |
bc7f75fa AK |
371 | |
372 | while (i < timeout) { | |
373 | if (e1000e_get_hw_semaphore(hw)) | |
374 | return -E1000_ERR_SWFW_SYNC; | |
375 | ||
376 | swfw_sync = er32(SW_FW_SYNC); | |
377 | if (!(swfw_sync & (fwmask | swmask))) | |
378 | break; | |
379 | ||
ad68076e BA |
380 | /* |
381 | * Firmware currently using resource (fwmask) | |
382 | * or other software thread using resource (swmask) | |
383 | */ | |
bc7f75fa AK |
384 | e1000e_put_hw_semaphore(hw); |
385 | mdelay(5); | |
386 | i++; | |
387 | } | |
388 | ||
389 | if (i == timeout) { | |
3bb99fe2 | 390 | e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
bc7f75fa AK |
391 | return -E1000_ERR_SWFW_SYNC; |
392 | } | |
393 | ||
394 | swfw_sync |= swmask; | |
395 | ew32(SW_FW_SYNC, swfw_sync); | |
396 | ||
397 | e1000e_put_hw_semaphore(hw); | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | /** | |
403 | * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore | |
404 | * @hw: pointer to the HW structure | |
405 | * @mask: specifies which semaphore to acquire | |
406 | * | |
407 | * Release the SW/FW semaphore used to access the PHY or NVM. The mask | |
408 | * will also specify which port we're releasing the lock for. | |
409 | **/ | |
410 | static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) | |
411 | { | |
412 | u32 swfw_sync; | |
413 | ||
414 | while (e1000e_get_hw_semaphore(hw) != 0); | |
415 | /* Empty */ | |
416 | ||
417 | swfw_sync = er32(SW_FW_SYNC); | |
418 | swfw_sync &= ~mask; | |
419 | ew32(SW_FW_SYNC, swfw_sync); | |
420 | ||
421 | e1000e_put_hw_semaphore(hw); | |
422 | } | |
423 | ||
424 | /** | |
425 | * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register | |
426 | * @hw: pointer to the HW structure | |
427 | * @offset: offset of the register to read | |
428 | * @data: pointer to the data returned from the operation | |
429 | * | |
fe401674 | 430 | * Read the GG82563 PHY register. |
bc7f75fa AK |
431 | **/ |
432 | static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
433 | u32 offset, u16 *data) | |
434 | { | |
435 | s32 ret_val; | |
436 | u32 page_select; | |
437 | u16 temp; | |
438 | ||
2d9498f3 DG |
439 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
440 | if (ret_val) | |
441 | return ret_val; | |
442 | ||
bc7f75fa | 443 | /* Select Configuration Page */ |
2d9498f3 | 444 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 445 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 446 | } else { |
ad68076e BA |
447 | /* |
448 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
449 | * registers 30 and 31 |
450 | */ | |
451 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 452 | } |
bc7f75fa AK |
453 | |
454 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
455 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
456 | if (ret_val) { | |
457 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 458 | return ret_val; |
2d9498f3 | 459 | } |
bc7f75fa | 460 | |
ad68076e BA |
461 | /* |
462 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
463 | * before the device has completed the "Page Select" MDI |
464 | * transaction. So we wait 200us after each MDI command... | |
465 | */ | |
466 | udelay(200); | |
467 | ||
468 | /* ...and verify the command was successful. */ | |
2d9498f3 | 469 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa AK |
470 | |
471 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { | |
472 | ret_val = -E1000_ERR_PHY; | |
2d9498f3 | 473 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
474 | return ret_val; |
475 | } | |
476 | ||
477 | udelay(200); | |
478 | ||
2d9498f3 DG |
479 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
480 | data); | |
bc7f75fa AK |
481 | |
482 | udelay(200); | |
2d9498f3 | 483 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
484 | |
485 | return ret_val; | |
486 | } | |
487 | ||
488 | /** | |
489 | * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register | |
490 | * @hw: pointer to the HW structure | |
491 | * @offset: offset of the register to read | |
492 | * @data: value to write to the register | |
493 | * | |
fe401674 | 494 | * Write to the GG82563 PHY register. |
bc7f75fa AK |
495 | **/ |
496 | static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |
497 | u32 offset, u16 data) | |
498 | { | |
499 | s32 ret_val; | |
500 | u32 page_select; | |
501 | u16 temp; | |
502 | ||
2d9498f3 DG |
503 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
504 | if (ret_val) | |
505 | return ret_val; | |
506 | ||
bc7f75fa | 507 | /* Select Configuration Page */ |
2d9498f3 | 508 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
bc7f75fa | 509 | page_select = GG82563_PHY_PAGE_SELECT; |
2d9498f3 | 510 | } else { |
ad68076e BA |
511 | /* |
512 | * Use Alternative Page Select register to access | |
bc7f75fa AK |
513 | * registers 30 and 31 |
514 | */ | |
515 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | |
2d9498f3 | 516 | } |
bc7f75fa AK |
517 | |
518 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | |
2d9498f3 DG |
519 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
520 | if (ret_val) { | |
521 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 522 | return ret_val; |
2d9498f3 | 523 | } |
bc7f75fa AK |
524 | |
525 | ||
ad68076e BA |
526 | /* |
527 | * The "ready" bit in the MDIC register may be incorrectly set | |
bc7f75fa AK |
528 | * before the device has completed the "Page Select" MDI |
529 | * transaction. So we wait 200us after each MDI command... | |
530 | */ | |
531 | udelay(200); | |
532 | ||
533 | /* ...and verify the command was successful. */ | |
2d9498f3 | 534 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
bc7f75fa | 535 | |
2d9498f3 DG |
536 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
537 | e1000_release_phy_80003es2lan(hw); | |
bc7f75fa | 538 | return -E1000_ERR_PHY; |
2d9498f3 | 539 | } |
bc7f75fa AK |
540 | |
541 | udelay(200); | |
542 | ||
2d9498f3 DG |
543 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
544 | data); | |
bc7f75fa AK |
545 | |
546 | udelay(200); | |
2d9498f3 | 547 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
548 | |
549 | return ret_val; | |
550 | } | |
551 | ||
552 | /** | |
553 | * e1000_write_nvm_80003es2lan - Write to ESB2 NVM | |
554 | * @hw: pointer to the HW structure | |
555 | * @offset: offset of the register to read | |
556 | * @words: number of words to write | |
557 | * @data: buffer of data to write to the NVM | |
558 | * | |
fe401674 | 559 | * Write "words" of data to the ESB2 NVM. |
bc7f75fa AK |
560 | **/ |
561 | static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, | |
562 | u16 words, u16 *data) | |
563 | { | |
564 | return e1000e_write_nvm_spi(hw, offset, words, data); | |
565 | } | |
566 | ||
567 | /** | |
568 | * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete | |
569 | * @hw: pointer to the HW structure | |
570 | * | |
571 | * Wait a specific amount of time for manageability processes to complete. | |
572 | * This is a function pointer entry point called by the phy module. | |
573 | **/ | |
574 | static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) | |
575 | { | |
576 | s32 timeout = PHY_CFG_TIMEOUT; | |
577 | u32 mask = E1000_NVM_CFG_DONE_PORT_0; | |
578 | ||
579 | if (hw->bus.func == 1) | |
580 | mask = E1000_NVM_CFG_DONE_PORT_1; | |
581 | ||
582 | while (timeout) { | |
583 | if (er32(EEMNGCTL) & mask) | |
584 | break; | |
585 | msleep(1); | |
586 | timeout--; | |
587 | } | |
588 | if (!timeout) { | |
3bb99fe2 | 589 | e_dbg("MNG configuration cycle has not completed.\n"); |
bc7f75fa AK |
590 | return -E1000_ERR_RESET; |
591 | } | |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | /** | |
597 | * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex | |
598 | * @hw: pointer to the HW structure | |
599 | * | |
600 | * Force the speed and duplex settings onto the PHY. This is a | |
601 | * function pointer entry point called by the phy module. | |
602 | **/ | |
603 | static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) | |
604 | { | |
605 | s32 ret_val; | |
606 | u16 phy_data; | |
607 | bool link; | |
608 | ||
ad68076e BA |
609 | /* |
610 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
611 | * forced whenever speed and duplex are forced. |
612 | */ | |
613 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
614 | if (ret_val) | |
615 | return ret_val; | |
616 | ||
617 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
618 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data); | |
619 | if (ret_val) | |
620 | return ret_val; | |
621 | ||
3bb99fe2 | 622 | e_dbg("GG82563 PSCR: %X\n", phy_data); |
bc7f75fa AK |
623 | |
624 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
625 | if (ret_val) | |
626 | return ret_val; | |
627 | ||
628 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
629 | ||
630 | /* Reset the phy to commit changes. */ | |
631 | phy_data |= MII_CR_RESET; | |
632 | ||
633 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
634 | if (ret_val) | |
635 | return ret_val; | |
636 | ||
637 | udelay(1); | |
638 | ||
318a94d6 | 639 | if (hw->phy.autoneg_wait_to_complete) { |
3bb99fe2 | 640 | e_dbg("Waiting for forced speed/duplex link " |
bc7f75fa AK |
641 | "on GG82563 phy.\n"); |
642 | ||
643 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
644 | 100000, &link); | |
645 | if (ret_val) | |
646 | return ret_val; | |
647 | ||
648 | if (!link) { | |
ad68076e BA |
649 | /* |
650 | * We didn't get link. | |
bc7f75fa AK |
651 | * Reset the DSP and cross our fingers. |
652 | */ | |
653 | ret_val = e1000e_phy_reset_dsp(hw); | |
654 | if (ret_val) | |
655 | return ret_val; | |
656 | } | |
657 | ||
658 | /* Try once more */ | |
659 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
660 | 100000, &link); | |
661 | if (ret_val) | |
662 | return ret_val; | |
663 | } | |
664 | ||
665 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); | |
666 | if (ret_val) | |
667 | return ret_val; | |
668 | ||
ad68076e BA |
669 | /* |
670 | * Resetting the phy means we need to verify the TX_CLK corresponds | |
bc7f75fa AK |
671 | * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. |
672 | */ | |
673 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; | |
674 | if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) | |
675 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; | |
676 | else | |
677 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; | |
678 | ||
ad68076e BA |
679 | /* |
680 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
681 | * duplex. |
682 | */ | |
683 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
684 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); | |
685 | ||
686 | return ret_val; | |
687 | } | |
688 | ||
689 | /** | |
690 | * e1000_get_cable_length_80003es2lan - Set approximate cable length | |
691 | * @hw: pointer to the HW structure | |
692 | * | |
693 | * Find the approximate cable length as measured by the GG82563 PHY. | |
694 | * This is a function pointer entry point called by the phy module. | |
695 | **/ | |
696 | static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) | |
697 | { | |
698 | struct e1000_phy_info *phy = &hw->phy; | |
eb656d45 | 699 | s32 ret_val = 0; |
a708dd88 | 700 | u16 phy_data, index; |
bc7f75fa AK |
701 | |
702 | ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); | |
703 | if (ret_val) | |
eb656d45 | 704 | goto out; |
bc7f75fa AK |
705 | |
706 | index = phy_data & GG82563_DSPD_CABLE_LENGTH; | |
eb656d45 BA |
707 | |
708 | if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) { | |
709 | ret_val = -E1000_ERR_PHY; | |
710 | goto out; | |
711 | } | |
712 | ||
bc7f75fa | 713 | phy->min_cable_length = e1000_gg82563_cable_length_table[index]; |
eb656d45 | 714 | phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; |
bc7f75fa AK |
715 | |
716 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
717 | ||
eb656d45 BA |
718 | out: |
719 | return ret_val; | |
bc7f75fa AK |
720 | } |
721 | ||
722 | /** | |
723 | * e1000_get_link_up_info_80003es2lan - Report speed and duplex | |
724 | * @hw: pointer to the HW structure | |
725 | * @speed: pointer to speed buffer | |
726 | * @duplex: pointer to duplex buffer | |
727 | * | |
728 | * Retrieve the current speed and duplex configuration. | |
bc7f75fa AK |
729 | **/ |
730 | static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, | |
731 | u16 *duplex) | |
732 | { | |
733 | s32 ret_val; | |
734 | ||
318a94d6 | 735 | if (hw->phy.media_type == e1000_media_type_copper) { |
bc7f75fa AK |
736 | ret_val = e1000e_get_speed_and_duplex_copper(hw, |
737 | speed, | |
738 | duplex); | |
75eb0fad | 739 | hw->phy.ops.cfg_on_link_up(hw); |
bc7f75fa AK |
740 | } else { |
741 | ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw, | |
742 | speed, | |
743 | duplex); | |
744 | } | |
745 | ||
746 | return ret_val; | |
747 | } | |
748 | ||
749 | /** | |
750 | * e1000_reset_hw_80003es2lan - Reset the ESB2 controller | |
751 | * @hw: pointer to the HW structure | |
752 | * | |
753 | * Perform a global reset to the ESB2 controller. | |
bc7f75fa AK |
754 | **/ |
755 | static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) | |
756 | { | |
a708dd88 | 757 | u32 ctrl, icr; |
bc7f75fa AK |
758 | s32 ret_val; |
759 | ||
ad68076e BA |
760 | /* |
761 | * Prevent the PCI-E bus from sticking if there is no TLP connection | |
bc7f75fa AK |
762 | * on the last TLP read/write transaction when MAC is reset. |
763 | */ | |
764 | ret_val = e1000e_disable_pcie_master(hw); | |
765 | if (ret_val) | |
3bb99fe2 | 766 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 767 | |
3bb99fe2 | 768 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
769 | ew32(IMC, 0xffffffff); |
770 | ||
771 | ew32(RCTL, 0); | |
772 | ew32(TCTL, E1000_TCTL_PSP); | |
773 | e1e_flush(); | |
774 | ||
775 | msleep(10); | |
776 | ||
777 | ctrl = er32(CTRL); | |
778 | ||
75eb0fad | 779 | ret_val = e1000_acquire_phy_80003es2lan(hw); |
3bb99fe2 | 780 | e_dbg("Issuing a global reset to MAC\n"); |
bc7f75fa | 781 | ew32(CTRL, ctrl | E1000_CTRL_RST); |
75eb0fad | 782 | e1000_release_phy_80003es2lan(hw); |
bc7f75fa AK |
783 | |
784 | ret_val = e1000e_get_auto_rd_done(hw); | |
785 | if (ret_val) | |
786 | /* We don't want to continue accessing MAC registers. */ | |
787 | return ret_val; | |
788 | ||
789 | /* Clear any pending interrupt events. */ | |
790 | ew32(IMC, 0xffffffff); | |
791 | icr = er32(ICR); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | /** | |
797 | * e1000_init_hw_80003es2lan - Initialize the ESB2 controller | |
798 | * @hw: pointer to the HW structure | |
799 | * | |
800 | * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. | |
bc7f75fa AK |
801 | **/ |
802 | static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) | |
803 | { | |
804 | struct e1000_mac_info *mac = &hw->mac; | |
805 | u32 reg_data; | |
806 | s32 ret_val; | |
807 | u16 i; | |
808 | ||
809 | e1000_initialize_hw_bits_80003es2lan(hw); | |
810 | ||
811 | /* Initialize identification LED */ | |
812 | ret_val = e1000e_id_led_init(hw); | |
de39b752 | 813 | if (ret_val) |
3bb99fe2 | 814 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 815 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
816 | |
817 | /* Disabling VLAN filtering */ | |
3bb99fe2 | 818 | e_dbg("Initializing the IEEE VLAN\n"); |
caaddaf8 | 819 | mac->ops.clear_vfta(hw); |
bc7f75fa AK |
820 | |
821 | /* Setup the receive address. */ | |
822 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
823 | ||
824 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 825 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
826 | for (i = 0; i < mac->mta_reg_count; i++) |
827 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
828 | ||
829 | /* Setup link and flow control */ | |
830 | ret_val = e1000e_setup_link(hw); | |
831 | ||
832 | /* Set the transmit descriptor write-back policy */ | |
e9ec2c0f | 833 | reg_data = er32(TXDCTL(0)); |
bc7f75fa AK |
834 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
835 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 836 | ew32(TXDCTL(0), reg_data); |
bc7f75fa AK |
837 | |
838 | /* ...for both queues. */ | |
e9ec2c0f | 839 | reg_data = er32(TXDCTL(1)); |
bc7f75fa AK |
840 | reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | |
841 | E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; | |
e9ec2c0f | 842 | ew32(TXDCTL(1), reg_data); |
bc7f75fa AK |
843 | |
844 | /* Enable retransmit on late collisions */ | |
845 | reg_data = er32(TCTL); | |
846 | reg_data |= E1000_TCTL_RTLC; | |
847 | ew32(TCTL, reg_data); | |
848 | ||
849 | /* Configure Gigabit Carry Extend Padding */ | |
850 | reg_data = er32(TCTL_EXT); | |
851 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; | |
852 | reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; | |
853 | ew32(TCTL_EXT, reg_data); | |
854 | ||
855 | /* Configure Transmit Inter-Packet Gap */ | |
856 | reg_data = er32(TIPG); | |
857 | reg_data &= ~E1000_TIPG_IPGT_MASK; | |
858 | reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
859 | ew32(TIPG, reg_data); | |
860 | ||
861 | reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); | |
862 | reg_data &= ~0x00100000; | |
863 | E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); | |
864 | ||
ad68076e BA |
865 | /* |
866 | * Clear all of the statistics registers (clear on read). It is | |
bc7f75fa AK |
867 | * important that we do this after we have tried to establish link |
868 | * because the symbol error count will increment wildly if there | |
869 | * is no link. | |
870 | */ | |
871 | e1000_clear_hw_cntrs_80003es2lan(hw); | |
872 | ||
873 | return ret_val; | |
874 | } | |
875 | ||
876 | /** | |
877 | * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 | |
878 | * @hw: pointer to the HW structure | |
879 | * | |
880 | * Initializes required hardware-dependent bits needed for normal operation. | |
881 | **/ | |
882 | static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) | |
883 | { | |
884 | u32 reg; | |
885 | ||
886 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 887 | reg = er32(TXDCTL(0)); |
bc7f75fa | 888 | reg |= (1 << 22); |
e9ec2c0f | 889 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
890 | |
891 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 892 | reg = er32(TXDCTL(1)); |
bc7f75fa | 893 | reg |= (1 << 22); |
e9ec2c0f | 894 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
895 | |
896 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 897 | reg = er32(TARC(0)); |
bc7f75fa | 898 | reg &= ~(0xF << 27); /* 30:27 */ |
318a94d6 | 899 | if (hw->phy.media_type != e1000_media_type_copper) |
bc7f75fa | 900 | reg &= ~(1 << 20); |
e9ec2c0f | 901 | ew32(TARC(0), reg); |
bc7f75fa AK |
902 | |
903 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 904 | reg = er32(TARC(1)); |
bc7f75fa AK |
905 | if (er32(TCTL) & E1000_TCTL_MULR) |
906 | reg &= ~(1 << 28); | |
907 | else | |
908 | reg |= (1 << 28); | |
e9ec2c0f | 909 | ew32(TARC(1), reg); |
bc7f75fa AK |
910 | } |
911 | ||
912 | /** | |
913 | * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link | |
914 | * @hw: pointer to the HW structure | |
915 | * | |
916 | * Setup some GG82563 PHY registers for obtaining link | |
917 | **/ | |
918 | static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |
919 | { | |
920 | struct e1000_phy_info *phy = &hw->phy; | |
921 | s32 ret_val; | |
922 | u32 ctrl_ext; | |
75eb0fad | 923 | u16 data; |
bc7f75fa | 924 | |
2d9498f3 | 925 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); |
bc7f75fa AK |
926 | if (ret_val) |
927 | return ret_val; | |
928 | ||
929 | data |= GG82563_MSCR_ASSERT_CRS_ON_TX; | |
930 | /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ | |
931 | data |= GG82563_MSCR_TX_CLK_1000MBPS_25; | |
932 | ||
2d9498f3 | 933 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); |
bc7f75fa AK |
934 | if (ret_val) |
935 | return ret_val; | |
936 | ||
ad68076e BA |
937 | /* |
938 | * Options: | |
bc7f75fa AK |
939 | * MDI/MDI-X = 0 (default) |
940 | * 0 - Auto for all speeds | |
941 | * 1 - MDI mode | |
942 | * 2 - MDI-X mode | |
943 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
944 | */ | |
945 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data); | |
946 | if (ret_val) | |
947 | return ret_val; | |
948 | ||
949 | data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; | |
950 | ||
951 | switch (phy->mdix) { | |
952 | case 1: | |
953 | data |= GG82563_PSCR_CROSSOVER_MODE_MDI; | |
954 | break; | |
955 | case 2: | |
956 | data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; | |
957 | break; | |
958 | case 0: | |
959 | default: | |
960 | data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; | |
961 | break; | |
962 | } | |
963 | ||
ad68076e BA |
964 | /* |
965 | * Options: | |
bc7f75fa AK |
966 | * disable_polarity_correction = 0 (default) |
967 | * Automatic Correction for Reversed Cable Polarity | |
968 | * 0 - Disabled | |
969 | * 1 - Enabled | |
970 | */ | |
971 | data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
972 | if (phy->disable_polarity_correction) | |
973 | data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; | |
974 | ||
975 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data); | |
976 | if (ret_val) | |
977 | return ret_val; | |
978 | ||
979 | /* SW Reset the PHY so all changes take effect */ | |
980 | ret_val = e1000e_commit_phy(hw); | |
981 | if (ret_val) { | |
3bb99fe2 | 982 | e_dbg("Error Resetting the PHY\n"); |
bc7f75fa AK |
983 | return ret_val; |
984 | } | |
985 | ||
ad68076e | 986 | /* Bypass Rx and Tx FIFO's */ |
75eb0fad BA |
987 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
988 | E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, | |
ad68076e | 989 | E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | |
bc7f75fa AK |
990 | E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); |
991 | if (ret_val) | |
992 | return ret_val; | |
993 | ||
75eb0fad | 994 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
995 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
996 | &data); | |
997 | if (ret_val) | |
998 | return ret_val; | |
999 | data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; | |
75eb0fad | 1000 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
2d9498f3 DG |
1001 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, |
1002 | data); | |
1003 | if (ret_val) | |
1004 | return ret_val; | |
1005 | ||
bc7f75fa AK |
1006 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); |
1007 | if (ret_val) | |
1008 | return ret_val; | |
1009 | ||
1010 | data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; | |
1011 | ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data); | |
1012 | if (ret_val) | |
1013 | return ret_val; | |
1014 | ||
1015 | ctrl_ext = er32(CTRL_EXT); | |
1016 | ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); | |
1017 | ew32(CTRL_EXT, ctrl_ext); | |
1018 | ||
1019 | ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); | |
1020 | if (ret_val) | |
1021 | return ret_val; | |
1022 | ||
ad68076e BA |
1023 | /* |
1024 | * Do not init these registers when the HW is in IAMT mode, since the | |
bc7f75fa AK |
1025 | * firmware will have already initialized them. We only initialize |
1026 | * them if the HW is not in IAMT mode. | |
1027 | */ | |
1028 | if (!e1000e_check_mng_mode(hw)) { | |
1029 | /* Enable Electrical Idle on the PHY */ | |
1030 | data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; | |
1031 | ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data); | |
1032 | if (ret_val) | |
1033 | return ret_val; | |
1034 | ||
75eb0fad BA |
1035 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); |
1036 | if (ret_val) | |
1037 | return ret_val; | |
bc7f75fa AK |
1038 | |
1039 | data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1040 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); | |
1041 | if (ret_val) | |
1042 | return ret_val; | |
1043 | } | |
1044 | ||
ad68076e BA |
1045 | /* |
1046 | * Workaround: Disable padding in Kumeran interface in the MAC | |
bc7f75fa AK |
1047 | * and in the PHY to avoid CRC errors. |
1048 | */ | |
1049 | ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data); | |
1050 | if (ret_val) | |
1051 | return ret_val; | |
1052 | ||
1053 | data |= GG82563_ICR_DIS_PADDING; | |
1054 | ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data); | |
1055 | if (ret_val) | |
1056 | return ret_val; | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | /** | |
1062 | * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 | |
1063 | * @hw: pointer to the HW structure | |
1064 | * | |
1065 | * Essentially a wrapper for setting up all things "copper" related. | |
1066 | * This is a function pointer entry point called by the mac module. | |
1067 | **/ | |
1068 | static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) | |
1069 | { | |
1070 | u32 ctrl; | |
1071 | s32 ret_val; | |
1072 | u16 reg_data; | |
1073 | ||
1074 | ctrl = er32(CTRL); | |
1075 | ctrl |= E1000_CTRL_SLU; | |
1076 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1077 | ew32(CTRL, ctrl); | |
1078 | ||
ad68076e BA |
1079 | /* |
1080 | * Set the mac to wait the maximum time between each | |
bc7f75fa | 1081 | * iteration and increase the max iterations when |
ad68076e BA |
1082 | * polling the phy; this fixes erroneous timeouts at 10Mbps. |
1083 | */ | |
75eb0fad BA |
1084 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), |
1085 | 0xFFFF); | |
bc7f75fa AK |
1086 | if (ret_val) |
1087 | return ret_val; | |
75eb0fad BA |
1088 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
1089 | ®_data); | |
bc7f75fa AK |
1090 | if (ret_val) |
1091 | return ret_val; | |
1092 | reg_data |= 0x3F; | |
75eb0fad BA |
1093 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), |
1094 | reg_data); | |
bc7f75fa AK |
1095 | if (ret_val) |
1096 | return ret_val; | |
75eb0fad | 1097 | ret_val = e1000_read_kmrn_reg_80003es2lan(hw, |
bc7f75fa AK |
1098 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, |
1099 | ®_data); | |
1100 | if (ret_val) | |
1101 | return ret_val; | |
1102 | reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; | |
75eb0fad BA |
1103 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1104 | E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, | |
ad68076e | 1105 | reg_data); |
bc7f75fa AK |
1106 | if (ret_val) |
1107 | return ret_val; | |
1108 | ||
1109 | ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); | |
1110 | if (ret_val) | |
1111 | return ret_val; | |
1112 | ||
1113 | ret_val = e1000e_setup_copper_link(hw); | |
1114 | ||
1115 | return 0; | |
1116 | } | |
1117 | ||
75eb0fad BA |
1118 | /** |
1119 | * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up | |
1120 | * @hw: pointer to the HW structure | |
1121 | * @duplex: current duplex setting | |
1122 | * | |
1123 | * Configure the KMRN interface by applying last minute quirks for | |
1124 | * 10/100 operation. | |
1125 | **/ | |
1126 | static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) | |
1127 | { | |
1128 | s32 ret_val = 0; | |
1129 | u16 speed; | |
1130 | u16 duplex; | |
1131 | ||
1132 | if (hw->phy.media_type == e1000_media_type_copper) { | |
1133 | ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed, | |
1134 | &duplex); | |
1135 | if (ret_val) | |
1136 | return ret_val; | |
1137 | ||
1138 | if (speed == SPEED_1000) | |
1139 | ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); | |
1140 | else | |
1141 | ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); | |
1142 | } | |
1143 | ||
1144 | return ret_val; | |
1145 | } | |
1146 | ||
bc7f75fa AK |
1147 | /** |
1148 | * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation | |
1149 | * @hw: pointer to the HW structure | |
1150 | * @duplex: current duplex setting | |
1151 | * | |
1152 | * Configure the KMRN interface by applying last minute quirks for | |
1153 | * 10/100 operation. | |
1154 | **/ | |
1155 | static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |
1156 | { | |
1157 | s32 ret_val; | |
1158 | u32 tipg; | |
2d9498f3 DG |
1159 | u32 i = 0; |
1160 | u16 reg_data, reg_data2; | |
bc7f75fa AK |
1161 | |
1162 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; | |
75eb0fad BA |
1163 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1164 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1165 | reg_data); | |
bc7f75fa AK |
1166 | if (ret_val) |
1167 | return ret_val; | |
1168 | ||
1169 | /* Configure Transmit Inter-Packet Gap */ | |
1170 | tipg = er32(TIPG); | |
1171 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1172 | tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; | |
1173 | ew32(TIPG, tipg); | |
1174 | ||
2d9498f3 DG |
1175 | do { |
1176 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1177 | if (ret_val) | |
1178 | return ret_val; | |
1179 | ||
1180 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1181 | if (ret_val) | |
1182 | return ret_val; | |
1183 | i++; | |
1184 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1185 | |
1186 | if (duplex == HALF_DUPLEX) | |
1187 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | |
1188 | else | |
1189 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1190 | ||
1191 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1192 | ||
1193 | return 0; | |
1194 | } | |
1195 | ||
1196 | /** | |
1197 | * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation | |
1198 | * @hw: pointer to the HW structure | |
1199 | * | |
1200 | * Configure the KMRN interface by applying last minute quirks for | |
1201 | * gigabit operation. | |
1202 | **/ | |
1203 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) | |
1204 | { | |
1205 | s32 ret_val; | |
2d9498f3 | 1206 | u16 reg_data, reg_data2; |
bc7f75fa | 1207 | u32 tipg; |
2d9498f3 | 1208 | u32 i = 0; |
bc7f75fa AK |
1209 | |
1210 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; | |
75eb0fad BA |
1211 | ret_val = e1000_write_kmrn_reg_80003es2lan(hw, |
1212 | E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | |
1213 | reg_data); | |
bc7f75fa AK |
1214 | if (ret_val) |
1215 | return ret_val; | |
1216 | ||
1217 | /* Configure Transmit Inter-Packet Gap */ | |
1218 | tipg = er32(TIPG); | |
1219 | tipg &= ~E1000_TIPG_IPGT_MASK; | |
1220 | tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | |
1221 | ew32(TIPG, tipg); | |
1222 | ||
2d9498f3 DG |
1223 | do { |
1224 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | |
1225 | if (ret_val) | |
1226 | return ret_val; | |
1227 | ||
1228 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | |
1229 | if (ret_val) | |
1230 | return ret_val; | |
1231 | i++; | |
1232 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | |
bc7f75fa AK |
1233 | |
1234 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | |
1235 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | |
1236 | ||
1237 | return ret_val; | |
1238 | } | |
1239 | ||
75eb0fad BA |
1240 | /** |
1241 | * e1000_read_kmrn_reg_80003es2lan - Read kumeran register | |
1242 | * @hw: pointer to the HW structure | |
1243 | * @offset: register offset to be read | |
1244 | * @data: pointer to the read data | |
1245 | * | |
1246 | * Acquire semaphore, then read the PHY register at offset | |
1247 | * using the kumeran interface. The information retrieved is stored in data. | |
1248 | * Release the semaphore before exiting. | |
1249 | **/ | |
fa4c16da HE |
1250 | static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1251 | u16 *data) | |
75eb0fad BA |
1252 | { |
1253 | u32 kmrnctrlsta; | |
1254 | s32 ret_val = 0; | |
1255 | ||
1256 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1257 | if (ret_val) | |
1258 | return ret_val; | |
1259 | ||
1260 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
1261 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
1262 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
1263 | ||
1264 | udelay(2); | |
1265 | ||
1266 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
1267 | *data = (u16)kmrnctrlsta; | |
1268 | ||
1269 | e1000_release_mac_csr_80003es2lan(hw); | |
1270 | ||
1271 | return ret_val; | |
1272 | } | |
1273 | ||
1274 | /** | |
1275 | * e1000_write_kmrn_reg_80003es2lan - Write kumeran register | |
1276 | * @hw: pointer to the HW structure | |
1277 | * @offset: register offset to write to | |
1278 | * @data: data to write at register offset | |
1279 | * | |
1280 | * Acquire semaphore, then write the data to PHY register | |
1281 | * at the offset using the kumeran interface. Release semaphore | |
1282 | * before exiting. | |
1283 | **/ | |
fa4c16da HE |
1284 | static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, |
1285 | u16 data) | |
75eb0fad BA |
1286 | { |
1287 | u32 kmrnctrlsta; | |
1288 | s32 ret_val = 0; | |
1289 | ||
1290 | ret_val = e1000_acquire_mac_csr_80003es2lan(hw); | |
1291 | if (ret_val) | |
1292 | return ret_val; | |
1293 | ||
1294 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
1295 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
1296 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
1297 | ||
1298 | udelay(2); | |
1299 | ||
1300 | e1000_release_mac_csr_80003es2lan(hw); | |
1301 | ||
1302 | return ret_val; | |
1303 | } | |
1304 | ||
bc7f75fa AK |
1305 | /** |
1306 | * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters | |
1307 | * @hw: pointer to the HW structure | |
1308 | * | |
1309 | * Clears the hardware counters by reading the counter registers. | |
1310 | **/ | |
1311 | static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) | |
1312 | { | |
bc7f75fa AK |
1313 | e1000e_clear_hw_cntrs_base(hw); |
1314 | ||
99673d9b BA |
1315 | er32(PRC64); |
1316 | er32(PRC127); | |
1317 | er32(PRC255); | |
1318 | er32(PRC511); | |
1319 | er32(PRC1023); | |
1320 | er32(PRC1522); | |
1321 | er32(PTC64); | |
1322 | er32(PTC127); | |
1323 | er32(PTC255); | |
1324 | er32(PTC511); | |
1325 | er32(PTC1023); | |
1326 | er32(PTC1522); | |
1327 | ||
1328 | er32(ALGNERRC); | |
1329 | er32(RXERRC); | |
1330 | er32(TNCRS); | |
1331 | er32(CEXTERR); | |
1332 | er32(TSCTC); | |
1333 | er32(TSCTFC); | |
1334 | ||
1335 | er32(MGTPRC); | |
1336 | er32(MGTPDC); | |
1337 | er32(MGTPTC); | |
1338 | ||
1339 | er32(IAC); | |
1340 | er32(ICRXOC); | |
1341 | ||
1342 | er32(ICRXPTC); | |
1343 | er32(ICRXATC); | |
1344 | er32(ICTXPTC); | |
1345 | er32(ICTXATC); | |
1346 | er32(ICTXQEC); | |
1347 | er32(ICTXQMTC); | |
1348 | er32(ICRXDMTC); | |
bc7f75fa AK |
1349 | } |
1350 | ||
1351 | static struct e1000_mac_operations es2_mac_ops = { | |
a4f58f54 | 1352 | .id_led_init = e1000e_id_led_init, |
4662e82b | 1353 | .check_mng_mode = e1000e_check_mng_mode_generic, |
bc7f75fa AK |
1354 | /* check_for_link dependent on media type */ |
1355 | .cleanup_led = e1000e_cleanup_led_generic, | |
1356 | .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan, | |
1357 | .get_bus_info = e1000e_get_bus_info_pcie, | |
1358 | .get_link_up_info = e1000_get_link_up_info_80003es2lan, | |
1359 | .led_on = e1000e_led_on_generic, | |
1360 | .led_off = e1000e_led_off_generic, | |
e2de3eb6 | 1361 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
caaddaf8 BA |
1362 | .write_vfta = e1000_write_vfta_generic, |
1363 | .clear_vfta = e1000_clear_vfta_generic, | |
bc7f75fa AK |
1364 | .reset_hw = e1000_reset_hw_80003es2lan, |
1365 | .init_hw = e1000_init_hw_80003es2lan, | |
1366 | .setup_link = e1000e_setup_link, | |
1367 | /* setup_physical_interface dependent on media type */ | |
a4f58f54 | 1368 | .setup_led = e1000e_setup_led_generic, |
bc7f75fa AK |
1369 | }; |
1370 | ||
1371 | static struct e1000_phy_operations es2_phy_ops = { | |
94d8186a | 1372 | .acquire = e1000_acquire_phy_80003es2lan, |
bc7f75fa | 1373 | .check_reset_block = e1000e_check_reset_block_generic, |
94d8186a | 1374 | .commit = e1000e_phy_sw_reset, |
bc7f75fa AK |
1375 | .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan, |
1376 | .get_cfg_done = e1000_get_cfg_done_80003es2lan, | |
1377 | .get_cable_length = e1000_get_cable_length_80003es2lan, | |
94d8186a BA |
1378 | .get_info = e1000e_get_phy_info_m88, |
1379 | .read_reg = e1000_read_phy_reg_gg82563_80003es2lan, | |
1380 | .release = e1000_release_phy_80003es2lan, | |
1381 | .reset = e1000e_phy_hw_reset_generic, | |
bc7f75fa AK |
1382 | .set_d0_lplu_state = NULL, |
1383 | .set_d3_lplu_state = e1000e_set_d3_lplu_state, | |
94d8186a | 1384 | .write_reg = e1000_write_phy_reg_gg82563_80003es2lan, |
75eb0fad | 1385 | .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan, |
bc7f75fa AK |
1386 | }; |
1387 | ||
1388 | static struct e1000_nvm_operations es2_nvm_ops = { | |
94d8186a BA |
1389 | .acquire = e1000_acquire_nvm_80003es2lan, |
1390 | .read = e1000e_read_nvm_eerd, | |
1391 | .release = e1000_release_nvm_80003es2lan, | |
1392 | .update = e1000e_update_nvm_checksum_generic, | |
bc7f75fa | 1393 | .valid_led_default = e1000e_valid_led_default, |
94d8186a BA |
1394 | .validate = e1000e_validate_nvm_checksum_generic, |
1395 | .write = e1000_write_nvm_80003es2lan, | |
bc7f75fa AK |
1396 | }; |
1397 | ||
1398 | struct e1000_info e1000_es2_info = { | |
1399 | .mac = e1000_80003es2lan, | |
1400 | .flags = FLAG_HAS_HW_VLAN_FILTER | |
1401 | | FLAG_HAS_JUMBO_FRAMES | |
bc7f75fa AK |
1402 | | FLAG_HAS_WOL |
1403 | | FLAG_APME_IN_CTRL3 | |
1404 | | FLAG_RX_CSUM_ENABLED | |
1405 | | FLAG_HAS_CTRLEXT_ON_LOAD | |
bc7f75fa AK |
1406 | | FLAG_RX_NEEDS_RESTART /* errata */ |
1407 | | FLAG_TARC_SET_BIT_ZERO /* errata */ | |
1408 | | FLAG_APME_CHECK_PORT_B | |
1409 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ | |
1410 | | FLAG_TIPG_MEDIUM_FOR_80003ESLAN, | |
1411 | .pba = 38, | |
2adc55c9 | 1412 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 1413 | .get_variants = e1000_get_variants_80003es2lan, |
bc7f75fa AK |
1414 | .mac_ops = &es2_mac_ops, |
1415 | .phy_ops = &es2_phy_ops, | |
1416 | .nvm_ops = &es2_nvm_ops, | |
1417 | }; | |
1418 |