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e1000e: cleanup e1000_sw_lcd_config_ich8lan()
[deliverable/linux.git] / drivers / net / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
c7e54b1b 4 Copyright(c) 1999 - 2009 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
1605927f 30 * 82562G 10/100 Network Connection
bc7f75fa
AK		 31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
97ac8cae
BA		 42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
1605927f 44 * 82567V Gigabit Network Connection
97ac8cae
BA		 45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
2f15f9d6 50 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
bc7f75fa
AK		 55 */
56
bc7f75fa
AK		 57#include "e1000.h"
58
59#define ICH_FLASH_GFPREG 0x0000
60#define ICH_FLASH_HSFSTS 0x0004
61#define ICH_FLASH_HSFCTL 0x0006
62#define ICH_FLASH_FADDR 0x0008
63#define ICH_FLASH_FDATA0 0x0010
4a770358 64#define ICH_FLASH_PR0 0x0074
bc7f75fa
AK		 65
66#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
67#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
68#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
69#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
70#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
71
72#define ICH_CYCLE_READ 0
73#define ICH_CYCLE_WRITE 2
74#define ICH_CYCLE_ERASE 3
75
76#define FLASH_GFPREG_BASE_MASK 0x1FFF
77#define FLASH_SECTOR_ADDR_SHIFT 12
78
79#define ICH_FLASH_SEG_SIZE_256 256
80#define ICH_FLASH_SEG_SIZE_4K 4096
81#define ICH_FLASH_SEG_SIZE_8K 8192
82#define ICH_FLASH_SEG_SIZE_64K 65536
83
84
85#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
6dfaa769
BA		 86/* FW established a valid mode */
87#define E1000_ICH_FWSM_FW_VALID 0x00008000
bc7f75fa
AK		 88
89#define E1000_ICH_MNG_IAMT_MODE 0x2
90
91#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
92 (ID_LED_DEF1_OFF2 << 8) | \
93 (ID_LED_DEF1_ON2 << 4) | \
94 (ID_LED_DEF1_DEF2))
95
96#define E1000_ICH_NVM_SIG_WORD 0x13
97#define E1000_ICH_NVM_SIG_MASK 0xC000
e243455d
BA		 98#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
99#define E1000_ICH_NVM_SIG_VALUE 0x80
bc7f75fa
AK		 100
101#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
102
103#define E1000_FEXTNVM_SW_CONFIG 1
104#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
105
106#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
107
108#define E1000_ICH_RAR_ENTRIES 7
109
110#define PHY_PAGE_SHIFT 5
111#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
112 ((reg) & MAX_PHY_REG_ADDRESS))
113#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
114#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
115
116#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
117#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
118#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
119
a4f58f54
BA		 120#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
121
53ac5a88
BA		 122#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
123
f523d211
BA		 124/* SMBus Address Phy Register */
125#define HV_SMB_ADDR PHY_REG(768, 26)
126#define HV_SMB_ADDR_PEC_EN 0x0200
127#define HV_SMB_ADDR_VALID 0x0080
128
129/* Strapping Option Register - RO */
130#define E1000_STRAP 0x0000C
131#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
132#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
133
fa2ce13c
BA		 134/* OEM Bits Phy Register */
135#define HV_OEM_BITS PHY_REG(768, 25)
136#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
f523d211 137#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
fa2ce13c
BA		 138#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
139
1d5846b9
BA		 140#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
141#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
142
fddaa1af
BA		 143/* KMRN Mode Control */
144#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
145#define HV_KMRN_MDIO_SLOW 0x0400
146
bc7f75fa
AK		 147/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
148/* Offset 04h HSFSTS */
149union ich8_hws_flash_status {
150 struct ich8_hsfsts {
151 u16 flcdone :1; /* bit 0 Flash Cycle Done */
152 u16 flcerr :1; /* bit 1 Flash Cycle Error */
153 u16 dael :1; /* bit 2 Direct Access error Log */
154 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
155 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
156 u16 reserved1 :2; /* bit 13:6 Reserved */
157 u16 reserved2 :6; /* bit 13:6 Reserved */
158 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
159 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
160 } hsf_status;
161 u16 regval;
162};
163
164/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
165/* Offset 06h FLCTL */
166union ich8_hws_flash_ctrl {
167 struct ich8_hsflctl {
168 u16 flcgo :1; /* 0 Flash Cycle Go */
169 u16 flcycle :2; /* 2:1 Flash Cycle */
170 u16 reserved :5; /* 7:3 Reserved */
171 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
172 u16 flockdn :6; /* 15:10 Reserved */
173 } hsf_ctrl;
174 u16 regval;
175};
176
177/* ICH Flash Region Access Permissions */
178union ich8_hws_flash_regacc {
179 struct ich8_flracc {
180 u32 grra :8; /* 0:7 GbE region Read Access */
181 u32 grwa :8; /* 8:15 GbE region Write Access */
182 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
183 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
184 } hsf_flregacc;
185 u16 regval;
186};
187
4a770358
BA		 188/* ICH Flash Protected Region */
189union ich8_flash_protected_range {
190 struct ich8_pr {
191 u32 base:13; /* 0:12 Protected Range Base */
192 u32 reserved1:2; /* 13:14 Reserved */
193 u32 rpe:1; /* 15 Read Protection Enable */
194 u32 limit:13; /* 16:28 Protected Range Limit */
195 u32 reserved2:2; /* 29:30 Reserved */
196 u32 wpe:1; /* 31 Write Protection Enable */
197 } range;
198 u32 regval;
199};
200
bc7f75fa
AK		 201static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
202static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
203static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 204static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
205static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
206 u32 offset, u8 byte);
f4187b56
BA		 207static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
208 u8 *data);
bc7f75fa
AK		 209static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
210 u16 *data);
211static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
212 u8 size, u16 *data);
213static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
214static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
f4187b56 215static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 216static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
217static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
218static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
219static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
220static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
221static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
222static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
223static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 224static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 225static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 226static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1d5846b9 227static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 228static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
bc7f75fa
AK		 229
230static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
231{
232 return readw(hw->flash_address + reg);
233}
234
235static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
236{
237 return readl(hw->flash_address + reg);
238}
239
240static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
241{
242 writew(val, hw->flash_address + reg);
243}
244
245static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
246{
247 writel(val, hw->flash_address + reg);
248}
249
250#define er16flash(reg) __er16flash(hw, (reg))
251#define er32flash(reg) __er32flash(hw, (reg))
252#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
253#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
254
a4f58f54
BA		 255/**
256 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
257 * @hw: pointer to the HW structure
258 *
259 * Initialize family-specific PHY parameters and function pointers.
260 **/
261static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
262{
263 struct e1000_phy_info *phy = &hw->phy;
6dfaa769 264 u32 ctrl;
a4f58f54
BA		 265 s32 ret_val = 0;
266
267 phy->addr = 1;
268 phy->reset_delay_us = 100;
269
94d8186a
BA		 270 phy->ops.read_reg = e1000_read_phy_reg_hv;
271 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
fa2ce13c
BA		 272 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
273 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
94d8186a
BA		 274 phy->ops.write_reg = e1000_write_phy_reg_hv;
275 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
17f208de
BA		 276 phy->ops.power_up = e1000_power_up_phy_copper;
277 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
a4f58f54
BA		 278 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
279
6dfaa769
BA		 280 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
281 /*
282 * The MAC-PHY interconnect may still be in SMBus mode
283 * after Sx->S0. Toggle the LANPHYPC Value bit to force
284 * the interconnect to PCIe mode, but only if there is no
285 * firmware present otherwise firmware will have done it.
286 */
287 ctrl = er32(CTRL);
288 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
289 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
290 ew32(CTRL, ctrl);
291 udelay(10);
292 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
293 ew32(CTRL, ctrl);
294 msleep(50);
295 }
296
627c8a04
BA		 297 /*
298 * Reset the PHY before any acccess to it. Doing so, ensures that
299 * the PHY is in a known good state before we read/write PHY registers.
300 * The generic reset is sufficient here, because we haven't determined
301 * the PHY type yet.
302 */
303 ret_val = e1000e_phy_hw_reset_generic(hw);
304 if (ret_val)
305 goto out;
306
a4f58f54 307 phy->id = e1000_phy_unknown;
fddaa1af
BA		 308 ret_val = e1000e_get_phy_id(hw);
309 if (ret_val)
310 goto out;
311 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
312 /*
313 * In case the PHY needs to be in mdio slow mode (eg. 82577),
314 * set slow mode and try to get the PHY id again.
315 */
316 ret_val = e1000_set_mdio_slow_mode_hv(hw);
317 if (ret_val)
318 goto out;
319 ret_val = e1000e_get_phy_id(hw);
320 if (ret_val)
321 goto out;
322 }
a4f58f54
BA		 323 phy->type = e1000e_get_phy_type_from_id(phy->id);
324
0be84010
BA		 325 switch (phy->type) {
326 case e1000_phy_82577:
a4f58f54
BA		 327 phy->ops.check_polarity = e1000_check_polarity_82577;
328 phy->ops.force_speed_duplex =
329 e1000_phy_force_speed_duplex_82577;
0be84010 330 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 331 phy->ops.get_info = e1000_get_phy_info_82577;
332 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 333 break;
0be84010
BA		 334 case e1000_phy_82578:
335 phy->ops.check_polarity = e1000_check_polarity_m88;
336 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
337 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
338 phy->ops.get_info = e1000e_get_phy_info_m88;
339 break;
340 default:
341 ret_val = -E1000_ERR_PHY;
342 break;
a4f58f54
BA		 343 }
344
fddaa1af 345out:
a4f58f54
BA		 346 return ret_val;
347}
348
bc7f75fa
AK		 349/**
350 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
351 * @hw: pointer to the HW structure
352 *
353 * Initialize family-specific PHY parameters and function pointers.
354 **/
355static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
356{
357 struct e1000_phy_info *phy = &hw->phy;
358 s32 ret_val;
359 u16 i = 0;
360
361 phy->addr = 1;
362 phy->reset_delay_us = 100;
363
17f208de
BA		 364 phy->ops.power_up = e1000_power_up_phy_copper;
365 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
366
97ac8cae
BA		 367 /*
368 * We may need to do this twice - once for IGP and if that fails,
369 * we'll set BM func pointers and try again
370 */
371 ret_val = e1000e_determine_phy_address(hw);
372 if (ret_val) {
94d8186a
BA		 373 phy->ops.write_reg = e1000e_write_phy_reg_bm;
374 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 375 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 376 if (ret_val) {
377 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 378 return ret_val;
9b71b419 379 }
97ac8cae
BA		 380 }
381
bc7f75fa
AK		 382 phy->id = 0;
383 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
384 (i++ < 100)) {
385 msleep(1);
386 ret_val = e1000e_get_phy_id(hw);
387 if (ret_val)
388 return ret_val;
389 }
390
391 /* Verify phy id */
392 switch (phy->id) {
393 case IGP03E1000_E_PHY_ID:
394 phy->type = e1000_phy_igp_3;
395 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 396 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
397 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 398 phy->ops.get_info = e1000e_get_phy_info_igp;
399 phy->ops.check_polarity = e1000_check_polarity_igp;
400 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 401 break;
402 case IFE_E_PHY_ID:
403 case IFE_PLUS_E_PHY_ID:
404 case IFE_C_E_PHY_ID:
405 phy->type = e1000_phy_ife;
406 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 407 phy->ops.get_info = e1000_get_phy_info_ife;
408 phy->ops.check_polarity = e1000_check_polarity_ife;
409 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 410 break;
97ac8cae
BA		 411 case BME1000_E_PHY_ID:
412 phy->type = e1000_phy_bm;
413 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 414 phy->ops.read_reg = e1000e_read_phy_reg_bm;
415 phy->ops.write_reg = e1000e_write_phy_reg_bm;
416 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 417 phy->ops.get_info = e1000e_get_phy_info_m88;
418 phy->ops.check_polarity = e1000_check_polarity_m88;
419 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 420 break;
bc7f75fa
AK		 421 default:
422 return -E1000_ERR_PHY;
423 break;
424 }
425
426 return 0;
427}
428
429/**
430 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
431 * @hw: pointer to the HW structure
432 *
433 * Initialize family-specific NVM parameters and function
434 * pointers.
435 **/
436static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
437{
438 struct e1000_nvm_info *nvm = &hw->nvm;
439 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 440 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 441 u16 i;
442
ad68076e 443 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 444 if (!hw->flash_address) {
3bb99fe2 445 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 446 return -E1000_ERR_CONFIG;
447 }
448
449 nvm->type = e1000_nvm_flash_sw;
450
451 gfpreg = er32flash(ICH_FLASH_GFPREG);
452
ad68076e
BA		 453 /*
454 * sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 455 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 456 * the overall size.
457 */
bc7f75fa
AK		 458 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
459 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
460
461 /* flash_base_addr is byte-aligned */
462 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
463
ad68076e
BA		 464 /*
465 * find total size of the NVM, then cut in half since the total
466 * size represents two separate NVM banks.
467 */
bc7f75fa
AK		 468 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
469 << FLASH_SECTOR_ADDR_SHIFT;
470 nvm->flash_bank_size /= 2;
471 /* Adjust to word count */
472 nvm->flash_bank_size /= sizeof(u16);
473
474 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
475
476 /* Clear shadow ram */
477 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 478 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 479 dev_spec->shadow_ram[i].value = 0xFFFF;
480 }
481
482 return 0;
483}
484
485/**
486 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
487 * @hw: pointer to the HW structure
488 *
489 * Initialize family-specific MAC parameters and function
490 * pointers.
491 **/
492static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
493{
494 struct e1000_hw *hw = &adapter->hw;
495 struct e1000_mac_info *mac = &hw->mac;
496
497 /* Set media type function pointer */
318a94d6 498 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 499
500 /* Set mta register count */
501 mac->mta_reg_count = 32;
502 /* Set rar entry count */
503 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
504 if (mac->type == e1000_ich8lan)
505 mac->rar_entry_count--;
a65a4a0d
BA		 506 /* FWSM register */
507 mac->has_fwsm = true;
508 /* ARC subsystem not supported */
509 mac->arc_subsystem_valid = false;
f464ba87
BA		 510 /* Adaptive IFS supported */
511 mac->adaptive_ifs = true;
bc7f75fa 512
a4f58f54
BA		 513 /* LED operations */
514 switch (mac->type) {
515 case e1000_ich8lan:
516 case e1000_ich9lan:
517 case e1000_ich10lan:
518 /* ID LED init */
519 mac->ops.id_led_init = e1000e_id_led_init;
520 /* setup LED */
521 mac->ops.setup_led = e1000e_setup_led_generic;
522 /* cleanup LED */
523 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
524 /* turn on/off LED */
525 mac->ops.led_on = e1000_led_on_ich8lan;
526 mac->ops.led_off = e1000_led_off_ich8lan;
527 break;
528 case e1000_pchlan:
529 /* ID LED init */
530 mac->ops.id_led_init = e1000_id_led_init_pchlan;
531 /* setup LED */
532 mac->ops.setup_led = e1000_setup_led_pchlan;
533 /* cleanup LED */
534 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
535 /* turn on/off LED */
536 mac->ops.led_on = e1000_led_on_pchlan;
537 mac->ops.led_off = e1000_led_off_pchlan;
538 break;
539 default:
540 break;
541 }
542
bc7f75fa
AK		 543 /* Enable PCS Lock-loss workaround for ICH8 */
544 if (mac->type == e1000_ich8lan)
564ea9bb 545 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa
AK		 546
547 return 0;
548}
549
7d3cabbc
BA		 550/**
551 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
552 * @hw: pointer to the HW structure
553 *
554 * Checks to see of the link status of the hardware has changed. If a
555 * change in link status has been detected, then we read the PHY registers
556 * to get the current speed/duplex if link exists.
557 **/
558static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
559{
560 struct e1000_mac_info *mac = &hw->mac;
561 s32 ret_val;
562 bool link;
563
564 /*
565 * We only want to go out to the PHY registers to see if Auto-Neg
566 * has completed and/or if our link status has changed. The
567 * get_link_status flag is set upon receiving a Link Status
568 * Change or Rx Sequence Error interrupt.
569 */
570 if (!mac->get_link_status) {
571 ret_val = 0;
572 goto out;
573 }
574
7d3cabbc
BA		 575 /*
576 * First we want to see if the MII Status Register reports
577 * link. If so, then we want to get the current speed/duplex
578 * of the PHY.
579 */
580 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
581 if (ret_val)
582 goto out;
583
1d5846b9
BA		 584 if (hw->mac.type == e1000_pchlan) {
585 ret_val = e1000_k1_gig_workaround_hv(hw, link);
586 if (ret_val)
587 goto out;
588 }
589
7d3cabbc
BA		 590 if (!link)
591 goto out; /* No link detected */
592
593 mac->get_link_status = false;
594
595 if (hw->phy.type == e1000_phy_82578) {
596 ret_val = e1000_link_stall_workaround_hv(hw);
597 if (ret_val)
598 goto out;
599 }
600
601 /*
602 * Check if there was DownShift, must be checked
603 * immediately after link-up
604 */
605 e1000e_check_downshift(hw);
606
607 /*
608 * If we are forcing speed/duplex, then we simply return since
609 * we have already determined whether we have link or not.
610 */
611 if (!mac->autoneg) {
612 ret_val = -E1000_ERR_CONFIG;
613 goto out;
614 }
615
616 /*
617 * Auto-Neg is enabled. Auto Speed Detection takes care
618 * of MAC speed/duplex configuration. So we only need to
619 * configure Collision Distance in the MAC.
620 */
621 e1000e_config_collision_dist(hw);
622
623 /*
624 * Configure Flow Control now that Auto-Neg has completed.
625 * First, we need to restore the desired flow control
626 * settings because we may have had to re-autoneg with a
627 * different link partner.
628 */
629 ret_val = e1000e_config_fc_after_link_up(hw);
630 if (ret_val)
3bb99fe2 631 e_dbg("Error configuring flow control\n");
7d3cabbc
BA		 632
633out:
634 return ret_val;
635}
636
69e3fd8c 637static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 638{
639 struct e1000_hw *hw = &adapter->hw;
640 s32 rc;
641
642 rc = e1000_init_mac_params_ich8lan(adapter);
643 if (rc)
644 return rc;
645
646 rc = e1000_init_nvm_params_ich8lan(hw);
647 if (rc)
648 return rc;
649
a4f58f54
BA		 650 if (hw->mac.type == e1000_pchlan)
651 rc = e1000_init_phy_params_pchlan(hw);
652 else
653 rc = e1000_init_phy_params_ich8lan(hw);
bc7f75fa
AK		 654 if (rc)
655 return rc;
656
2adc55c9
BA		 657 if (adapter->hw.phy.type == e1000_phy_ife) {
658 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
659 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
660 }
661
bc7f75fa
AK		 662 if ((adapter->hw.mac.type == e1000_ich8lan) &&
663 (adapter->hw.phy.type == e1000_phy_igp_3))
664 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
665
666 return 0;
667}
668
717d438d 669static DEFINE_MUTEX(nvm_mutex);
717d438d 670
ca15df58
BA		 671/**
672 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
673 * @hw: pointer to the HW structure
674 *
675 * Acquires the mutex for performing NVM operations.
676 **/
677static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
678{
679 mutex_lock(&nvm_mutex);
680
681 return 0;
682}
683
684/**
685 * e1000_release_nvm_ich8lan - Release NVM mutex
686 * @hw: pointer to the HW structure
687 *
688 * Releases the mutex used while performing NVM operations.
689 **/
690static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
691{
692 mutex_unlock(&nvm_mutex);
ca15df58
BA		 693}
694
695static DEFINE_MUTEX(swflag_mutex);
696
bc7f75fa
AK		 697/**
698 * e1000_acquire_swflag_ich8lan - Acquire software control flag
699 * @hw: pointer to the HW structure
700 *
ca15df58
BA		 701 * Acquires the software control flag for performing PHY and select
702 * MAC CSR accesses.
bc7f75fa
AK		 703 **/
704static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
705{
373a88d7
BA		 706 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
707 s32 ret_val = 0;
bc7f75fa 708
ca15df58 709 mutex_lock(&swflag_mutex);
717d438d 710
bc7f75fa
AK		 711 while (timeout) {
712 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 713 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
714 break;
bc7f75fa 715
373a88d7
BA		 716 mdelay(1);
717 timeout--;
718 }
719
720 if (!timeout) {
3bb99fe2 721 e_dbg("SW/FW/HW has locked the resource for too long.\n");
373a88d7
BA		 722 ret_val = -E1000_ERR_CONFIG;
723 goto out;
724 }
725
53ac5a88 726 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 727
728 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
729 ew32(EXTCNF_CTRL, extcnf_ctrl);
730
731 while (timeout) {
732 extcnf_ctrl = er32(EXTCNF_CTRL);
733 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
734 break;
a4f58f54 735
bc7f75fa
AK		 736 mdelay(1);
737 timeout--;
738 }
739
740 if (!timeout) {
3bb99fe2 741 e_dbg("Failed to acquire the semaphore.\n");
2e2e8d53
BA		 742 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
743 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 744 ret_val = -E1000_ERR_CONFIG;
745 goto out;
bc7f75fa
AK		 746 }
747
373a88d7
BA		 748out:
749 if (ret_val)
ca15df58 750 mutex_unlock(&swflag_mutex);
373a88d7
BA		 751
752 return ret_val;
bc7f75fa
AK		 753}
754
755/**
756 * e1000_release_swflag_ich8lan - Release software control flag
757 * @hw: pointer to the HW structure
758 *
ca15df58
BA		 759 * Releases the software control flag for performing PHY and select
760 * MAC CSR accesses.
bc7f75fa
AK		 761 **/
762static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
763{
764 u32 extcnf_ctrl;
765
766 extcnf_ctrl = er32(EXTCNF_CTRL);
767 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
768 ew32(EXTCNF_CTRL, extcnf_ctrl);
717d438d 769
ca15df58 770 mutex_unlock(&swflag_mutex);
bc7f75fa
AK		 771}
772
4662e82b
BA		 773/**
774 * e1000_check_mng_mode_ich8lan - Checks management mode
775 * @hw: pointer to the HW structure
776 *
777 * This checks if the adapter has manageability enabled.
778 * This is a function pointer entry point only called by read/write
779 * routines for the PHY and NVM parts.
780 **/
781static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
782{
a708dd88
BA		 783 u32 fwsm;
784
785 fwsm = er32(FWSM);
4662e82b
BA		 786
787 return (fwsm & E1000_FWSM_MODE_MASK) ==
788 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
789}
790
bc7f75fa
AK		 791/**
792 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
793 * @hw: pointer to the HW structure
794 *
795 * Checks if firmware is blocking the reset of the PHY.
796 * This is a function pointer entry point only called by
797 * reset routines.
798 **/
799static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
800{
801 u32 fwsm;
802
803 fwsm = er32(FWSM);
804
805 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
806}
807
f523d211
BA		 808/**
809 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
810 * @hw: pointer to the HW structure
811 *
812 * SW should configure the LCD from the NVM extended configuration region
813 * as a workaround for certain parts.
814 **/
815static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
816{
8b802a7e 817 struct e1000_adapter *adapter = hw->adapter;
f523d211
BA		 818 struct e1000_phy_info *phy = &hw->phy;
819 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 820 s32 ret_val = 0;
f523d211
BA		 821 u16 word_addr, reg_data, reg_addr, phy_page = 0;
822
f523d211
BA		 823 /*
824 * Initialize the PHY from the NVM on ICH platforms. This
825 * is needed due to an issue where the NVM configuration is
826 * not properly autoloaded after power transitions.
827 * Therefore, after each PHY reset, we will load the
828 * configuration data out of the NVM manually.
829 */
3f0c16e8
BA		 830 switch (hw->mac.type) {
831 case e1000_ich8lan:
832 if (phy->type != e1000_phy_igp_3)
833 return ret_val;
834
835 if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
836 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
837 break;
838 }
839 /* Fall-thru */
840 case e1000_pchlan:
8b802a7e 841 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 842 break;
843 default:
844 return ret_val;
845 }
846
847 ret_val = hw->phy.ops.acquire(hw);
848 if (ret_val)
849 return ret_val;
8b802a7e
BA		 850
851 data = er32(FEXTNVM);
852 if (!(data & sw_cfg_mask))
853 goto out;
f523d211 854
8b802a7e
BA		 855 /*
856 * Make sure HW does not configure LCD from PHY
857 * extended configuration before SW configuration
858 */
859 data = er32(EXTCNF_CTRL);
860 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
861 goto out;
862
863 cnf_size = er32(EXTCNF_SIZE);
864 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
865 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
866 if (!cnf_size)
867 goto out;
868
869 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
870 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
871
872 if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
873 (hw->mac.type == e1000_pchlan)) {
f523d211 874 /*
8b802a7e
BA		 875 * HW configures the SMBus address and LEDs when the
876 * OEM and LCD Write Enable bits are set in the NVM.
877 * When both NVM bits are cleared, SW will configure
878 * them instead.
f523d211 879 */
8b802a7e
BA		 880 data = er32(STRAP);
881 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
882 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
883 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
884 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
885 reg_data);
886 if (ret_val)
f523d211
BA		 887 goto out;
888
8b802a7e
BA		 889 data = er32(LEDCTL);
890 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
891 (u16)data);
892 if (ret_val)
f523d211 893 goto out;
8b802a7e 894 }
f523d211 895
8b802a7e
BA		 896 /* Configure LCD from extended configuration region. */
897
898 /* cnf_base_addr is in DWORD */
899 word_addr = (u16)(cnf_base_addr << 1);
900
901 for (i = 0; i < cnf_size; i++) {
902 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
903 &reg_data);
904 if (ret_val)
905 goto out;
906
907 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
908 1, &reg_addr);
909 if (ret_val)
910 goto out;
911
912 /* Save off the PHY page for future writes. */
913 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
914 phy_page = reg_data;
915 continue;
f523d211 916 }
8b802a7e
BA		 917
918 reg_addr &= PHY_REG_MASK;
919 reg_addr |= phy_page;
920
921 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
922 reg_data);
923 if (ret_val)
924 goto out;
f523d211
BA		 925 }
926
927out:
94d8186a 928 hw->phy.ops.release(hw);
f523d211
BA		 929 return ret_val;
930}
931
1d5846b9
BA		 932/**
933 * e1000_k1_gig_workaround_hv - K1 Si workaround
934 * @hw: pointer to the HW structure
935 * @link: link up bool flag
936 *
937 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
938 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
939 * If link is down, the function will restore the default K1 setting located
940 * in the NVM.
941 **/
942static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
943{
944 s32 ret_val = 0;
945 u16 status_reg = 0;
946 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
947
948 if (hw->mac.type != e1000_pchlan)
949 goto out;
950
951 /* Wrap the whole flow with the sw flag */
94d8186a 952 ret_val = hw->phy.ops.acquire(hw);
1d5846b9
BA		 953 if (ret_val)
954 goto out;
955
956 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
957 if (link) {
958 if (hw->phy.type == e1000_phy_82578) {
94d8186a 959 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1d5846b9
BA		 960 &status_reg);
961 if (ret_val)
962 goto release;
963
964 status_reg &= BM_CS_STATUS_LINK_UP |
965 BM_CS_STATUS_RESOLVED |
966 BM_CS_STATUS_SPEED_MASK;
967
968 if (status_reg == (BM_CS_STATUS_LINK_UP |
969 BM_CS_STATUS_RESOLVED |
970 BM_CS_STATUS_SPEED_1000))
971 k1_enable = false;
972 }
973
974 if (hw->phy.type == e1000_phy_82577) {
94d8186a 975 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1d5846b9
BA		 976 &status_reg);
977 if (ret_val)
978 goto release;
979
980 status_reg &= HV_M_STATUS_LINK_UP |
981 HV_M_STATUS_AUTONEG_COMPLETE |
982 HV_M_STATUS_SPEED_MASK;
983
984 if (status_reg == (HV_M_STATUS_LINK_UP |
985 HV_M_STATUS_AUTONEG_COMPLETE |
986 HV_M_STATUS_SPEED_1000))
987 k1_enable = false;
988 }
989
990 /* Link stall fix for link up */
94d8186a 991 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 992 0x0100);
993 if (ret_val)
994 goto release;
995
996 } else {
997 /* Link stall fix for link down */
94d8186a 998 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 999 0x4100);
1000 if (ret_val)
1001 goto release;
1002 }
1003
1004 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1005
1006release:
94d8186a 1007 hw->phy.ops.release(hw);
1d5846b9
BA		 1008out:
1009 return ret_val;
1010}
1011
1012/**
1013 * e1000_configure_k1_ich8lan - Configure K1 power state
1014 * @hw: pointer to the HW structure
1015 * @enable: K1 state to configure
1016 *
1017 * Configure the K1 power state based on the provided parameter.
1018 * Assumes semaphore already acquired.
1019 *
1020 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1021 **/
bb436b20 1022s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9
BA		 1023{
1024 s32 ret_val = 0;
1025 u32 ctrl_reg = 0;
1026 u32 ctrl_ext = 0;
1027 u32 reg = 0;
1028 u16 kmrn_reg = 0;
1029
1030 ret_val = e1000e_read_kmrn_reg_locked(hw,
1031 E1000_KMRNCTRLSTA_K1_CONFIG,
1032 &kmrn_reg);
1033 if (ret_val)
1034 goto out;
1035
1036 if (k1_enable)
1037 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1038 else
1039 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1040
1041 ret_val = e1000e_write_kmrn_reg_locked(hw,
1042 E1000_KMRNCTRLSTA_K1_CONFIG,
1043 kmrn_reg);
1044 if (ret_val)
1045 goto out;
1046
1047 udelay(20);
1048 ctrl_ext = er32(CTRL_EXT);
1049 ctrl_reg = er32(CTRL);
1050
1051 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1052 reg |= E1000_CTRL_FRCSPD;
1053 ew32(CTRL, reg);
1054
1055 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1056 udelay(20);
1057 ew32(CTRL, ctrl_reg);
1058 ew32(CTRL_EXT, ctrl_ext);
1059 udelay(20);
1060
1061out:
1062 return ret_val;
1063}
1064
f523d211
BA		 1065/**
1066 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1067 * @hw: pointer to the HW structure
1068 * @d0_state: boolean if entering d0 or d3 device state
1069 *
1070 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1071 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1072 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1073 **/
1074static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1075{
1076 s32 ret_val = 0;
1077 u32 mac_reg;
1078 u16 oem_reg;
1079
1080 if (hw->mac.type != e1000_pchlan)
1081 return ret_val;
1082
94d8186a 1083 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1084 if (ret_val)
1085 return ret_val;
1086
1087 mac_reg = er32(EXTCNF_CTRL);
1088 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1089 goto out;
1090
1091 mac_reg = er32(FEXTNVM);
1092 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1093 goto out;
1094
1095 mac_reg = er32(PHY_CTRL);
1096
94d8186a 1097 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211
BA		 1098 if (ret_val)
1099 goto out;
1100
1101 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1102
1103 if (d0_state) {
1104 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1105 oem_reg |= HV_OEM_BITS_GBE_DIS;
1106
1107 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1108 oem_reg |= HV_OEM_BITS_LPLU;
1109 } else {
1110 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1111 oem_reg |= HV_OEM_BITS_GBE_DIS;
1112
1113 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1114 oem_reg |= HV_OEM_BITS_LPLU;
1115 }
1116 /* Restart auto-neg to activate the bits */
818f3331
BA		 1117 if (!e1000_check_reset_block(hw))
1118 oem_reg |= HV_OEM_BITS_RESTART_AN;
94d8186a 1119 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
f523d211
BA		 1120
1121out:
94d8186a 1122 hw->phy.ops.release(hw);
f523d211
BA		 1123
1124 return ret_val;
1125}
1126
1127
fddaa1af
BA		 1128/**
1129 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1130 * @hw: pointer to the HW structure
1131 **/
1132static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1133{
1134 s32 ret_val;
1135 u16 data;
1136
1137 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1138 if (ret_val)
1139 return ret_val;
1140
1141 data |= HV_KMRN_MDIO_SLOW;
1142
1143 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1144
1145 return ret_val;
1146}
1147
a4f58f54
BA		 1148/**
1149 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1150 * done after every PHY reset.
1151 **/
1152static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1153{
1154 s32 ret_val = 0;
baf86c9d 1155 u16 phy_data;
a4f58f54
BA		 1156
1157 if (hw->mac.type != e1000_pchlan)
1158 return ret_val;
1159
fddaa1af
BA		 1160 /* Set MDIO slow mode before any other MDIO access */
1161 if (hw->phy.type == e1000_phy_82577) {
1162 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1163 if (ret_val)
1164 goto out;
1165 }
1166
a4f58f54
BA		 1167 if (((hw->phy.type == e1000_phy_82577) &&
1168 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1169 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1170 /* Disable generation of early preamble */
1171 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1172 if (ret_val)
1173 return ret_val;
1174
1175 /* Preamble tuning for SSC */
1176 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1177 if (ret_val)
1178 return ret_val;
1179 }
1180
1181 if (hw->phy.type == e1000_phy_82578) {
1182 /*
1183 * Return registers to default by doing a soft reset then
1184 * writing 0x3140 to the control register.
1185 */
1186 if (hw->phy.revision < 2) {
1187 e1000e_phy_sw_reset(hw);
1188 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1189 }
1190 }
1191
1192 /* Select page 0 */
94d8186a 1193 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1194 if (ret_val)
1195 return ret_val;
1d5846b9 1196
a4f58f54 1197 hw->phy.addr = 1;
1d5846b9 1198 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 1199 hw->phy.ops.release(hw);
1d5846b9
BA		 1200 if (ret_val)
1201 goto out;
a4f58f54 1202
1d5846b9
BA		 1203 /*
1204 * Configure the K1 Si workaround during phy reset assuming there is
1205 * link so that it disables K1 if link is in 1Gbps.
1206 */
1207 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d
BA		 1208 if (ret_val)
1209 goto out;
1d5846b9 1210
baf86c9d
BA		 1211 /* Workaround for link disconnects on a busy hub in half duplex */
1212 ret_val = hw->phy.ops.acquire(hw);
1213 if (ret_val)
1214 goto out;
1215 ret_val = hw->phy.ops.read_reg_locked(hw,
1216 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1217 &phy_data);
1218 if (ret_val)
1219 goto release;
1220 ret_val = hw->phy.ops.write_reg_locked(hw,
1221 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1222 phy_data & 0x00FF);
1223release:
1224 hw->phy.ops.release(hw);
1d5846b9 1225out:
a4f58f54
BA		 1226 return ret_val;
1227}
1228
fc0c7760
BA		 1229/**
1230 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1231 * @hw: pointer to the HW structure
1232 *
1233 * Check the appropriate indication the MAC has finished configuring the
1234 * PHY after a software reset.
1235 **/
1236static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1237{
1238 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1239
1240 /* Wait for basic configuration completes before proceeding */
1241 do {
1242 data = er32(STATUS);
1243 data &= E1000_STATUS_LAN_INIT_DONE;
1244 udelay(100);
1245 } while ((!data) && --loop);
1246
1247 /*
1248 * If basic configuration is incomplete before the above loop
1249 * count reaches 0, loading the configuration from NVM will
1250 * leave the PHY in a bad state possibly resulting in no link.
1251 */
1252 if (loop == 0)
3bb99fe2 1253 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 1254
1255 /* Clear the Init Done bit for the next init event */
1256 data = er32(STATUS);
1257 data &= ~E1000_STATUS_LAN_INIT_DONE;
1258 ew32(STATUS, data);
1259}
1260
bc7f75fa 1261/**
e98cac44 1262 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 1263 * @hw: pointer to the HW structure
bc7f75fa 1264 **/
e98cac44 1265static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 1266{
f523d211
BA		 1267 s32 ret_val = 0;
1268 u16 reg;
bc7f75fa 1269
e98cac44
BA		 1270 if (e1000_check_reset_block(hw))
1271 goto out;
fc0c7760 1272
fddaa1af 1273 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 1274 switch (hw->mac.type) {
1275 case e1000_pchlan:
a4f58f54
BA		 1276 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1277 if (ret_val)
e98cac44
BA		 1278 goto out;
1279 break;
1280 default:
1281 break;
a4f58f54
BA		 1282 }
1283
db2932ec
BA		 1284 /* Dummy read to clear the phy wakeup bit after lcd reset */
1285 if (hw->mac.type == e1000_pchlan)
1286 e1e_rphy(hw, BM_WUC, &reg);
1287
f523d211
BA		 1288 /* Configure the LCD with the extended configuration region in NVM */
1289 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1290 if (ret_val)
1291 goto out;
bc7f75fa 1292
f523d211 1293 /* Configure the LCD with the OEM bits in NVM */
e98cac44 1294 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 1295
f523d211 1296out:
e98cac44
BA		 1297 return ret_val;
1298}
1299
1300/**
1301 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1302 * @hw: pointer to the HW structure
1303 *
1304 * Resets the PHY
1305 * This is a function pointer entry point called by drivers
1306 * or other shared routines.
1307 **/
1308static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1309{
1310 s32 ret_val = 0;
1311
1312 ret_val = e1000e_phy_hw_reset_generic(hw);
1313 if (ret_val)
1314 goto out;
1315
1316 ret_val = e1000_post_phy_reset_ich8lan(hw);
1317
1318out:
1319 return ret_val;
bc7f75fa
AK		 1320}
1321
fa2ce13c
BA		 1322/**
1323 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1324 * @hw: pointer to the HW structure
1325 * @active: true to enable LPLU, false to disable
1326 *
1327 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1328 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1329 * the phy speed. This function will manually set the LPLU bit and restart
1330 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1331 * since it configures the same bit.
1332 **/
1333static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1334{
1335 s32 ret_val = 0;
1336 u16 oem_reg;
1337
1338 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1339 if (ret_val)
1340 goto out;
1341
1342 if (active)
1343 oem_reg |= HV_OEM_BITS_LPLU;
1344 else
1345 oem_reg &= ~HV_OEM_BITS_LPLU;
1346
1347 oem_reg |= HV_OEM_BITS_RESTART_AN;
1348 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1349
1350out:
1351 return ret_val;
1352}
1353
bc7f75fa
AK		 1354/**
1355 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1356 * @hw: pointer to the HW structure
564ea9bb 1357 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1358 *
1359 * Sets the LPLU D0 state according to the active flag. When
1360 * activating LPLU this function also disables smart speed
1361 * and vice versa. LPLU will not be activated unless the
1362 * device autonegotiation advertisement meets standards of
1363 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1364 * This is a function pointer entry point only called by
1365 * PHY setup routines.
1366 **/
1367static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1368{
1369 struct e1000_phy_info *phy = &hw->phy;
1370 u32 phy_ctrl;
1371 s32 ret_val = 0;
1372 u16 data;
1373
97ac8cae 1374 if (phy->type == e1000_phy_ife)
bc7f75fa
AK		 1375 return ret_val;
1376
1377 phy_ctrl = er32(PHY_CTRL);
1378
1379 if (active) {
1380 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1381 ew32(PHY_CTRL, phy_ctrl);
1382
60f1292f
BA		 1383 if (phy->type != e1000_phy_igp_3)
1384 return 0;
1385
ad68076e
BA		 1386 /*
1387 * Call gig speed drop workaround on LPLU before accessing
1388 * any PHY registers
1389 */
60f1292f 1390 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1391 e1000e_gig_downshift_workaround_ich8lan(hw);
1392
1393 /* When LPLU is enabled, we should disable SmartSpeed */
1394 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1395 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1396 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1397 if (ret_val)
1398 return ret_val;
1399 } else {
1400 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1401 ew32(PHY_CTRL, phy_ctrl);
1402
60f1292f
BA		 1403 if (phy->type != e1000_phy_igp_3)
1404 return 0;
1405
ad68076e
BA		 1406 /*
1407 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1408 * during Dx states where the power conservation is most
1409 * important. During driver activity we should enable
ad68076e
BA		 1410 * SmartSpeed, so performance is maintained.
1411 */
bc7f75fa
AK		 1412 if (phy->smart_speed == e1000_smart_speed_on) {
1413 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1414 &data);
bc7f75fa
AK		 1415 if (ret_val)
1416 return ret_val;
1417
1418 data |= IGP01E1000_PSCFR_SMART_SPEED;
1419 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1420 data);
bc7f75fa
AK		 1421 if (ret_val)
1422 return ret_val;
1423 } else if (phy->smart_speed == e1000_smart_speed_off) {
1424 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1425 &data);
bc7f75fa
AK		 1426 if (ret_val)
1427 return ret_val;
1428
1429 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1430 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1431 data);
bc7f75fa
AK		 1432 if (ret_val)
1433 return ret_val;
1434 }
1435 }
1436
1437 return 0;
1438}
1439
1440/**
1441 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1442 * @hw: pointer to the HW structure
564ea9bb 1443 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1444 *
1445 * Sets the LPLU D3 state according to the active flag. When
1446 * activating LPLU this function also disables smart speed
1447 * and vice versa. LPLU will not be activated unless the
1448 * device autonegotiation advertisement meets standards of
1449 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1450 * This is a function pointer entry point only called by
1451 * PHY setup routines.
1452 **/
1453static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1454{
1455 struct e1000_phy_info *phy = &hw->phy;
1456 u32 phy_ctrl;
1457 s32 ret_val;
1458 u16 data;
1459
1460 phy_ctrl = er32(PHY_CTRL);
1461
1462 if (!active) {
1463 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1464 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 1465
1466 if (phy->type != e1000_phy_igp_3)
1467 return 0;
1468
ad68076e
BA		 1469 /*
1470 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1471 * during Dx states where the power conservation is most
1472 * important. During driver activity we should enable
ad68076e
BA		 1473 * SmartSpeed, so performance is maintained.
1474 */
bc7f75fa 1475 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 1476 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1477 &data);
bc7f75fa
AK		 1478 if (ret_val)
1479 return ret_val;
1480
1481 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1482 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1483 data);
bc7f75fa
AK		 1484 if (ret_val)
1485 return ret_val;
1486 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 1487 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1488 &data);
bc7f75fa
AK		 1489 if (ret_val)
1490 return ret_val;
1491
1492 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1493 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1494 data);
bc7f75fa
AK		 1495 if (ret_val)
1496 return ret_val;
1497 }
1498 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1499 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1500 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1501 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1502 ew32(PHY_CTRL, phy_ctrl);
1503
60f1292f
BA		 1504 if (phy->type != e1000_phy_igp_3)
1505 return 0;
1506
ad68076e
BA		 1507 /*
1508 * Call gig speed drop workaround on LPLU before accessing
1509 * any PHY registers
1510 */
60f1292f 1511 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1512 e1000e_gig_downshift_workaround_ich8lan(hw);
1513
1514 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 1515 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 1516 if (ret_val)
1517 return ret_val;
1518
1519 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 1520 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 1521 }
1522
1523 return 0;
1524}
1525
f4187b56
BA		 1526/**
1527 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1528 * @hw: pointer to the HW structure
1529 * @bank: pointer to the variable that returns the active bank
1530 *
1531 * Reads signature byte from the NVM using the flash access registers.
e243455d 1532 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 1533 **/
1534static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1535{
e243455d 1536 u32 eecd;
f4187b56 1537 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 1538 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1539 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d
BA		 1540 u8 sig_byte = 0;
1541 s32 ret_val = 0;
f4187b56 1542
e243455d
BA		 1543 switch (hw->mac.type) {
1544 case e1000_ich8lan:
1545 case e1000_ich9lan:
1546 eecd = er32(EECD);
1547 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1548 E1000_EECD_SEC1VAL_VALID_MASK) {
1549 if (eecd & E1000_EECD_SEC1VAL)
1550 *bank = 1;
1551 else
1552 *bank = 0;
1553
1554 return 0;
1555 }
3bb99fe2 1556 e_dbg("Unable to determine valid NVM bank via EEC - "
e243455d
BA		 1557 "reading flash signature\n");
1558 /* fall-thru */
1559 default:
1560 /* set bank to 0 in case flash read fails */
1561 *bank = 0;
1562
1563 /* Check bank 0 */
1564 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1565 &sig_byte);
1566 if (ret_val)
1567 return ret_val;
1568 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1569 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 1570 *bank = 0;
e243455d
BA		 1571 return 0;
1572 }
f4187b56 1573
e243455d
BA		 1574 /* Check bank 1 */
1575 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1576 bank1_offset,
1577 &sig_byte);
1578 if (ret_val)
1579 return ret_val;
1580 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1581 E1000_ICH_NVM_SIG_VALUE) {
1582 *bank = 1;
1583 return 0;
f4187b56 1584 }
e243455d 1585
3bb99fe2 1586 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 1587 return -E1000_ERR_NVM;
f4187b56
BA		 1588 }
1589
1590 return 0;
1591}
1592
bc7f75fa
AK		 1593/**
1594 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1595 * @hw: pointer to the HW structure
1596 * @offset: The offset (in bytes) of the word(s) to read.
1597 * @words: Size of data to read in words
1598 * @data: Pointer to the word(s) to read at offset.
1599 *
1600 * Reads a word(s) from the NVM using the flash access registers.
1601 **/
1602static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1603 u16 *data)
1604{
1605 struct e1000_nvm_info *nvm = &hw->nvm;
1606 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1607 u32 act_offset;
148675a7 1608 s32 ret_val = 0;
f4187b56 1609 u32 bank = 0;
bc7f75fa
AK		 1610 u16 i, word;
1611
1612 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1613 (words == 0)) {
3bb99fe2 1614 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 1615 ret_val = -E1000_ERR_NVM;
1616 goto out;
bc7f75fa
AK		 1617 }
1618
94d8186a 1619 nvm->ops.acquire(hw);
bc7f75fa 1620
f4187b56 1621 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 1622 if (ret_val) {
3bb99fe2 1623 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 1624 bank = 0;
1625 }
f4187b56
BA		 1626
1627 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 1628 act_offset += offset;
1629
148675a7 1630 ret_val = 0;
bc7f75fa
AK		 1631 for (i = 0; i < words; i++) {
1632 if ((dev_spec->shadow_ram) &&
1633 (dev_spec->shadow_ram[offset+i].modified)) {
1634 data[i] = dev_spec->shadow_ram[offset+i].value;
1635 } else {
1636 ret_val = e1000_read_flash_word_ich8lan(hw,
1637 act_offset + i,
1638 &word);
1639 if (ret_val)
1640 break;
1641 data[i] = word;
1642 }
1643 }
1644
94d8186a 1645 nvm->ops.release(hw);
bc7f75fa 1646
e243455d
BA		 1647out:
1648 if (ret_val)
3bb99fe2 1649 e_dbg("NVM read error: %d\n", ret_val);
e243455d 1650
bc7f75fa
AK		 1651 return ret_val;
1652}
1653
1654/**
1655 * e1000_flash_cycle_init_ich8lan - Initialize flash
1656 * @hw: pointer to the HW structure
1657 *
1658 * This function does initial flash setup so that a new read/write/erase cycle
1659 * can be started.
1660 **/
1661static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1662{
1663 union ich8_hws_flash_status hsfsts;
1664 s32 ret_val = -E1000_ERR_NVM;
1665 s32 i = 0;
1666
1667 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1668
1669 /* Check if the flash descriptor is valid */
1670 if (hsfsts.hsf_status.fldesvalid == 0) {
3bb99fe2 1671 e_dbg("Flash descriptor invalid. "
2c73e1fe 1672 "SW Sequencing must be used.\n");
bc7f75fa
AK		 1673 return -E1000_ERR_NVM;
1674 }
1675
1676 /* Clear FCERR and DAEL in hw status by writing 1 */
1677 hsfsts.hsf_status.flcerr = 1;
1678 hsfsts.hsf_status.dael = 1;
1679
1680 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1681
ad68076e
BA		 1682 /*
1683 * Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 1684 * bit to check against, in order to start a new cycle or
1685 * FDONE bit should be changed in the hardware so that it
489815ce 1686 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 1687 * indication whether a cycle is in progress or has been
1688 * completed.
1689 */
1690
1691 if (hsfsts.hsf_status.flcinprog == 0) {
ad68076e
BA		 1692 /*
1693 * There is no cycle running at present,
5ff5b664 1694 * so we can start a cycle.
ad68076e
BA		 1695 * Begin by setting Flash Cycle Done.
1696 */
bc7f75fa
AK		 1697 hsfsts.hsf_status.flcdone = 1;
1698 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1699 ret_val = 0;
1700 } else {
ad68076e 1701 /*
5ff5b664 1702 * Otherwise poll for sometime so the current
ad68076e
BA		 1703 * cycle has a chance to end before giving up.
1704 */
bc7f75fa
AK		 1705 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1706 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1707 if (hsfsts.hsf_status.flcinprog == 0) {
1708 ret_val = 0;
1709 break;
1710 }
1711 udelay(1);
1712 }
1713 if (ret_val == 0) {
ad68076e
BA		 1714 /*
1715 * Successful in waiting for previous cycle to timeout,
1716 * now set the Flash Cycle Done.
1717 */
bc7f75fa
AK		 1718 hsfsts.hsf_status.flcdone = 1;
1719 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1720 } else {
2c73e1fe 1721 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 1722 }
1723 }
1724
1725 return ret_val;
1726}
1727
1728/**
1729 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1730 * @hw: pointer to the HW structure
1731 * @timeout: maximum time to wait for completion
1732 *
1733 * This function starts a flash cycle and waits for its completion.
1734 **/
1735static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1736{
1737 union ich8_hws_flash_ctrl hsflctl;
1738 union ich8_hws_flash_status hsfsts;
1739 s32 ret_val = -E1000_ERR_NVM;
1740 u32 i = 0;
1741
1742 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1743 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1744 hsflctl.hsf_ctrl.flcgo = 1;
1745 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1746
1747 /* wait till FDONE bit is set to 1 */
1748 do {
1749 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1750 if (hsfsts.hsf_status.flcdone == 1)
1751 break;
1752 udelay(1);
1753 } while (i++ < timeout);
1754
1755 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1756 return 0;
1757
1758 return ret_val;
1759}
1760
1761/**
1762 * e1000_read_flash_word_ich8lan - Read word from flash
1763 * @hw: pointer to the HW structure
1764 * @offset: offset to data location
1765 * @data: pointer to the location for storing the data
1766 *
1767 * Reads the flash word at offset into data. Offset is converted
1768 * to bytes before read.
1769 **/
1770static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1771 u16 *data)
1772{
1773 /* Must convert offset into bytes. */
1774 offset <<= 1;
1775
1776 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1777}
1778
f4187b56
BA		 1779/**
1780 * e1000_read_flash_byte_ich8lan - Read byte from flash
1781 * @hw: pointer to the HW structure
1782 * @offset: The offset of the byte to read.
1783 * @data: Pointer to a byte to store the value read.
1784 *
1785 * Reads a single byte from the NVM using the flash access registers.
1786 **/
1787static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1788 u8 *data)
1789{
1790 s32 ret_val;
1791 u16 word = 0;
1792
1793 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1794 if (ret_val)
1795 return ret_val;
1796
1797 *data = (u8)word;
1798
1799 return 0;
1800}
1801
bc7f75fa
AK		 1802/**
1803 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
1804 * @hw: pointer to the HW structure
1805 * @offset: The offset (in bytes) of the byte or word to read.
1806 * @size: Size of data to read, 1=byte 2=word
1807 * @data: Pointer to the word to store the value read.
1808 *
1809 * Reads a byte or word from the NVM using the flash access registers.
1810 **/
1811static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1812 u8 size, u16 *data)
1813{
1814 union ich8_hws_flash_status hsfsts;
1815 union ich8_hws_flash_ctrl hsflctl;
1816 u32 flash_linear_addr;
1817 u32 flash_data = 0;
1818 s32 ret_val = -E1000_ERR_NVM;
1819 u8 count = 0;
1820
1821 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1822 return -E1000_ERR_NVM;
1823
1824 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1825 hw->nvm.flash_base_addr;
1826
1827 do {
1828 udelay(1);
1829 /* Steps */
1830 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1831 if (ret_val != 0)
1832 break;
1833
1834 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1835 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1836 hsflctl.hsf_ctrl.fldbcount = size - 1;
1837 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1838 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1839
1840 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1841
1842 ret_val = e1000_flash_cycle_ich8lan(hw,
1843 ICH_FLASH_READ_COMMAND_TIMEOUT);
1844
ad68076e
BA		 1845 /*
1846 * Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 1847 * and try the whole sequence a few more times, else
1848 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 1849 * least significant byte first msb to lsb
1850 */
bc7f75fa
AK		 1851 if (ret_val == 0) {
1852 flash_data = er32flash(ICH_FLASH_FDATA0);
1853 if (size == 1) {
1854 *data = (u8)(flash_data & 0x000000FF);
1855 } else if (size == 2) {
1856 *data = (u16)(flash_data & 0x0000FFFF);
1857 }
1858 break;
1859 } else {
ad68076e
BA		 1860 /*
1861 * If we've gotten here, then things are probably
bc7f75fa
AK		 1862 * completely hosed, but if the error condition is
1863 * detected, it won't hurt to give it another try...
1864 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1865 */
1866 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1867 if (hsfsts.hsf_status.flcerr == 1) {
1868 /* Repeat for some time before giving up. */
1869 continue;
1870 } else if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 1871 e_dbg("Timeout error - flash cycle "
2c73e1fe 1872 "did not complete.\n");
bc7f75fa
AK		 1873 break;
1874 }
1875 }
1876 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1877
1878 return ret_val;
1879}
1880
1881/**
1882 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
1883 * @hw: pointer to the HW structure
1884 * @offset: The offset (in bytes) of the word(s) to write.
1885 * @words: Size of data to write in words
1886 * @data: Pointer to the word(s) to write at offset.
1887 *
1888 * Writes a byte or word to the NVM using the flash access registers.
1889 **/
1890static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1891 u16 *data)
1892{
1893 struct e1000_nvm_info *nvm = &hw->nvm;
1894 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 1895 u16 i;
1896
1897 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1898 (words == 0)) {
3bb99fe2 1899 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 1900 return -E1000_ERR_NVM;
1901 }
1902
94d8186a 1903 nvm->ops.acquire(hw);
ca15df58 1904
bc7f75fa 1905 for (i = 0; i < words; i++) {
564ea9bb 1906 dev_spec->shadow_ram[offset+i].modified = true;
bc7f75fa
AK		 1907 dev_spec->shadow_ram[offset+i].value = data[i];
1908 }
1909
94d8186a 1910 nvm->ops.release(hw);
ca15df58 1911
bc7f75fa
AK		 1912 return 0;
1913}
1914
1915/**
1916 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1917 * @hw: pointer to the HW structure
1918 *
1919 * The NVM checksum is updated by calling the generic update_nvm_checksum,
1920 * which writes the checksum to the shadow ram. The changes in the shadow
1921 * ram are then committed to the EEPROM by processing each bank at a time
1922 * checking for the modified bit and writing only the pending changes.
489815ce 1923 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 1924 * future writes.
1925 **/
1926static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1927{
1928 struct e1000_nvm_info *nvm = &hw->nvm;
1929 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 1930 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 1931 s32 ret_val;
1932 u16 data;
1933
1934 ret_val = e1000e_update_nvm_checksum_generic(hw);
1935 if (ret_val)
e243455d 1936 goto out;
bc7f75fa
AK		 1937
1938 if (nvm->type != e1000_nvm_flash_sw)
e243455d 1939 goto out;
bc7f75fa 1940
94d8186a 1941 nvm->ops.acquire(hw);
bc7f75fa 1942
ad68076e
BA		 1943 /*
1944 * We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 1945 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 1946 * is going to be written
1947 */
f4187b56 1948 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 1949 if (ret_val) {
3bb99fe2 1950 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 1951 bank = 0;
e243455d 1952 }
f4187b56
BA		 1953
1954 if (bank == 0) {
bc7f75fa
AK		 1955 new_bank_offset = nvm->flash_bank_size;
1956 old_bank_offset = 0;
e243455d 1957 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 1958 if (ret_val)
1959 goto release;
bc7f75fa
AK		 1960 } else {
1961 old_bank_offset = nvm->flash_bank_size;
1962 new_bank_offset = 0;
e243455d 1963 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 1964 if (ret_val)
1965 goto release;
bc7f75fa
AK		 1966 }
1967
1968 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
ad68076e
BA		 1969 /*
1970 * Determine whether to write the value stored
bc7f75fa 1971 * in the other NVM bank or a modified value stored
ad68076e
BA		 1972 * in the shadow RAM
1973 */
bc7f75fa
AK		 1974 if (dev_spec->shadow_ram[i].modified) {
1975 data = dev_spec->shadow_ram[i].value;
1976 } else {
e243455d
BA		 1977 ret_val = e1000_read_flash_word_ich8lan(hw, i +
1978 old_bank_offset,
1979 &data);
1980 if (ret_val)
1981 break;
bc7f75fa
AK		 1982 }
1983
ad68076e
BA		 1984 /*
1985 * If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 1986 * (15:14) are 11b until the commit has completed.
1987 * This will allow us to write 10b which indicates the
1988 * signature is valid. We want to do this after the write
1989 * has completed so that we don't mark the segment valid
ad68076e
BA		 1990 * while the write is still in progress
1991 */
bc7f75fa
AK		 1992 if (i == E1000_ICH_NVM_SIG_WORD)
1993 data |= E1000_ICH_NVM_SIG_MASK;
1994
1995 /* Convert offset to bytes. */
1996 act_offset = (i + new_bank_offset) << 1;
1997
1998 udelay(100);
1999 /* Write the bytes to the new bank. */
2000 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2001 act_offset,
2002 (u8)data);
2003 if (ret_val)
2004 break;
2005
2006 udelay(100);
2007 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2008 act_offset + 1,
2009 (u8)(data >> 8));
2010 if (ret_val)
2011 break;
2012 }
2013
ad68076e
BA		 2014 /*
2015 * Don't bother writing the segment valid bits if sector
2016 * programming failed.
2017 */
bc7f75fa 2018 if (ret_val) {
4a770358 2019 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 2020 e_dbg("Flash commit failed.\n");
9c5e209d 2021 goto release;
bc7f75fa
AK		 2022 }
2023
ad68076e
BA		 2024 /*
2025 * Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 2026 * to 10b in word 0x13 , this can be done without an
2027 * erase as well since these bits are 11 to start with
ad68076e
BA		 2028 * and we need to change bit 14 to 0b
2029 */
bc7f75fa 2030 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 2031 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 2032 if (ret_val)
2033 goto release;
2034
bc7f75fa
AK		 2035 data &= 0xBFFF;
2036 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2037 act_offset * 2 + 1,
2038 (u8)(data >> 8));
9c5e209d
BA		 2039 if (ret_val)
2040 goto release;
bc7f75fa 2041
ad68076e
BA		 2042 /*
2043 * And invalidate the previously valid segment by setting
bc7f75fa
AK		 2044 * its signature word (0x13) high_byte to 0b. This can be
2045 * done without an erase because flash erase sets all bits
ad68076e
BA		 2046 * to 1's. We can write 1's to 0's without an erase
2047 */
bc7f75fa
AK		 2048 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2049 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 2050 if (ret_val)
2051 goto release;
bc7f75fa
AK		 2052
2053 /* Great! Everything worked, we can now clear the cached entries. */
2054 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 2055 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 2056 dev_spec->shadow_ram[i].value = 0xFFFF;
2057 }
2058
9c5e209d 2059release:
94d8186a 2060 nvm->ops.release(hw);
bc7f75fa 2061
ad68076e
BA		 2062 /*
2063 * Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 2064 * until after the next adapter reset.
2065 */
9c5e209d
BA		 2066 if (!ret_val) {
2067 e1000e_reload_nvm(hw);
2068 msleep(10);
2069 }
bc7f75fa 2070
e243455d
BA		 2071out:
2072 if (ret_val)
3bb99fe2 2073 e_dbg("NVM update error: %d\n", ret_val);
e243455d 2074
bc7f75fa
AK		 2075 return ret_val;
2076}
2077
2078/**
2079 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2080 * @hw: pointer to the HW structure
2081 *
2082 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2083 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2084 * calculated, in which case we need to calculate the checksum and set bit 6.
2085 **/
2086static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2087{
2088 s32 ret_val;
2089 u16 data;
2090
ad68076e
BA		 2091 /*
2092 * Read 0x19 and check bit 6. If this bit is 0, the checksum
bc7f75fa
AK		 2093 * needs to be fixed. This bit is an indication that the NVM
2094 * was prepared by OEM software and did not calculate the
2095 * checksum...a likely scenario.
2096 */
2097 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2098 if (ret_val)
2099 return ret_val;
2100
2101 if ((data & 0x40) == 0) {
2102 data |= 0x40;
2103 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2104 if (ret_val)
2105 return ret_val;
2106 ret_val = e1000e_update_nvm_checksum(hw);
2107 if (ret_val)
2108 return ret_val;
2109 }
2110
2111 return e1000e_validate_nvm_checksum_generic(hw);
2112}
2113
4a770358
BA		 2114/**
2115 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2116 * @hw: pointer to the HW structure
2117 *
2118 * To prevent malicious write/erase of the NVM, set it to be read-only
2119 * so that the hardware ignores all write/erase cycles of the NVM via
2120 * the flash control registers. The shadow-ram copy of the NVM will
2121 * still be updated, however any updates to this copy will not stick
2122 * across driver reloads.
2123 **/
2124void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2125{
ca15df58 2126 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 2127 union ich8_flash_protected_range pr0;
2128 union ich8_hws_flash_status hsfsts;
2129 u32 gfpreg;
4a770358 2130
94d8186a 2131 nvm->ops.acquire(hw);
4a770358
BA		 2132
2133 gfpreg = er32flash(ICH_FLASH_GFPREG);
2134
2135 /* Write-protect GbE Sector of NVM */
2136 pr0.regval = er32flash(ICH_FLASH_PR0);
2137 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2138 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2139 pr0.range.wpe = true;
2140 ew32flash(ICH_FLASH_PR0, pr0.regval);
2141
2142 /*
2143 * Lock down a subset of GbE Flash Control Registers, e.g.
2144 * PR0 to prevent the write-protection from being lifted.
2145 * Once FLOCKDN is set, the registers protected by it cannot
2146 * be written until FLOCKDN is cleared by a hardware reset.
2147 */
2148 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2149 hsfsts.hsf_status.flockdn = true;
2150 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2151
94d8186a 2152 nvm->ops.release(hw);
4a770358
BA		 2153}
2154
bc7f75fa
AK		 2155/**
2156 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2157 * @hw: pointer to the HW structure
2158 * @offset: The offset (in bytes) of the byte/word to read.
2159 * @size: Size of data to read, 1=byte 2=word
2160 * @data: The byte(s) to write to the NVM.
2161 *
2162 * Writes one/two bytes to the NVM using the flash access registers.
2163 **/
2164static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2165 u8 size, u16 data)
2166{
2167 union ich8_hws_flash_status hsfsts;
2168 union ich8_hws_flash_ctrl hsflctl;
2169 u32 flash_linear_addr;
2170 u32 flash_data = 0;
2171 s32 ret_val;
2172 u8 count = 0;
2173
2174 if (size < 1 || size > 2 || data > size * 0xff ||
2175 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2176 return -E1000_ERR_NVM;
2177
2178 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2179 hw->nvm.flash_base_addr;
2180
2181 do {
2182 udelay(1);
2183 /* Steps */
2184 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2185 if (ret_val)
2186 break;
2187
2188 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2189 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2190 hsflctl.hsf_ctrl.fldbcount = size -1;
2191 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2192 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2193
2194 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2195
2196 if (size == 1)
2197 flash_data = (u32)data & 0x00FF;
2198 else
2199 flash_data = (u32)data;
2200
2201 ew32flash(ICH_FLASH_FDATA0, flash_data);
2202
ad68076e
BA		 2203 /*
2204 * check if FCERR is set to 1 , if set to 1, clear it
2205 * and try the whole sequence a few more times else done
2206 */
bc7f75fa
AK		 2207 ret_val = e1000_flash_cycle_ich8lan(hw,
2208 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2209 if (!ret_val)
2210 break;
2211
ad68076e
BA		 2212 /*
2213 * If we're here, then things are most likely
bc7f75fa
AK		 2214 * completely hosed, but if the error condition
2215 * is detected, it won't hurt to give it another
2216 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2217 */
2218 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2219 if (hsfsts.hsf_status.flcerr == 1)
2220 /* Repeat for some time before giving up. */
2221 continue;
2222 if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2223 e_dbg("Timeout error - flash cycle "
bc7f75fa
AK		 2224 "did not complete.");
2225 break;
2226 }
2227 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2228
2229 return ret_val;
2230}
2231
2232/**
2233 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2234 * @hw: pointer to the HW structure
2235 * @offset: The index of the byte to read.
2236 * @data: The byte to write to the NVM.
2237 *
2238 * Writes a single byte to the NVM using the flash access registers.
2239 **/
2240static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2241 u8 data)
2242{
2243 u16 word = (u16)data;
2244
2245 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2246}
2247
2248/**
2249 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2250 * @hw: pointer to the HW structure
2251 * @offset: The offset of the byte to write.
2252 * @byte: The byte to write to the NVM.
2253 *
2254 * Writes a single byte to the NVM using the flash access registers.
2255 * Goes through a retry algorithm before giving up.
2256 **/
2257static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2258 u32 offset, u8 byte)
2259{
2260 s32 ret_val;
2261 u16 program_retries;
2262
2263 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2264 if (!ret_val)
2265 return ret_val;
2266
2267 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 2268 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
bc7f75fa
AK		 2269 udelay(100);
2270 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2271 if (!ret_val)
2272 break;
2273 }
2274 if (program_retries == 100)
2275 return -E1000_ERR_NVM;
2276
2277 return 0;
2278}
2279
2280/**
2281 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2282 * @hw: pointer to the HW structure
2283 * @bank: 0 for first bank, 1 for second bank, etc.
2284 *
2285 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2286 * bank N is 4096 * N + flash_reg_addr.
2287 **/
2288static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2289{
2290 struct e1000_nvm_info *nvm = &hw->nvm;
2291 union ich8_hws_flash_status hsfsts;
2292 union ich8_hws_flash_ctrl hsflctl;
2293 u32 flash_linear_addr;
2294 /* bank size is in 16bit words - adjust to bytes */
2295 u32 flash_bank_size = nvm->flash_bank_size * 2;
2296 s32 ret_val;
2297 s32 count = 0;
a708dd88 2298 s32 j, iteration, sector_size;
bc7f75fa
AK		 2299
2300 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2301
ad68076e
BA		 2302 /*
2303 * Determine HW Sector size: Read BERASE bits of hw flash status
2304 * register
2305 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 2306 * consecutive sectors. The start index for the nth Hw sector
2307 * can be calculated as = bank * 4096 + n * 256
2308 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2309 * The start index for the nth Hw sector can be calculated
2310 * as = bank * 4096
2311 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2312 * (ich9 only, otherwise error condition)
2313 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2314 */
2315 switch (hsfsts.hsf_status.berasesz) {
2316 case 0:
2317 /* Hw sector size 256 */
2318 sector_size = ICH_FLASH_SEG_SIZE_256;
2319 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2320 break;
2321 case 1:
2322 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 2323 iteration = 1;
bc7f75fa
AK		 2324 break;
2325 case 2:
148675a7
BA		 2326 sector_size = ICH_FLASH_SEG_SIZE_8K;
2327 iteration = 1;
bc7f75fa
AK		 2328 break;
2329 case 3:
2330 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 2331 iteration = 1;
bc7f75fa
AK		 2332 break;
2333 default:
2334 return -E1000_ERR_NVM;
2335 }
2336
2337 /* Start with the base address, then add the sector offset. */
2338 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 2339 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa
AK		 2340
2341 for (j = 0; j < iteration ; j++) {
2342 do {
2343 /* Steps */
2344 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2345 if (ret_val)
2346 return ret_val;
2347
ad68076e
BA		 2348 /*
2349 * Write a value 11 (block Erase) in Flash
2350 * Cycle field in hw flash control
2351 */
bc7f75fa
AK		 2352 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2353 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2354 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2355
ad68076e
BA		 2356 /*
2357 * Write the last 24 bits of an index within the
bc7f75fa
AK		 2358 * block into Flash Linear address field in Flash
2359 * Address.
2360 */
2361 flash_linear_addr += (j * sector_size);
2362 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2363
2364 ret_val = e1000_flash_cycle_ich8lan(hw,
2365 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2366 if (ret_val == 0)
2367 break;
2368
ad68076e
BA		 2369 /*
2370 * Check if FCERR is set to 1. If 1,
bc7f75fa 2371 * clear it and try the whole sequence
ad68076e
BA		 2372 * a few more times else Done
2373 */
bc7f75fa
AK		 2374 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2375 if (hsfsts.hsf_status.flcerr == 1)
ad68076e 2376 /* repeat for some time before giving up */
bc7f75fa
AK		 2377 continue;
2378 else if (hsfsts.hsf_status.flcdone == 0)
2379 return ret_val;
2380 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2381 }
2382
2383 return 0;
2384}
2385
2386/**
2387 * e1000_valid_led_default_ich8lan - Set the default LED settings
2388 * @hw: pointer to the HW structure
2389 * @data: Pointer to the LED settings
2390 *
2391 * Reads the LED default settings from the NVM to data. If the NVM LED
2392 * settings is all 0's or F's, set the LED default to a valid LED default
2393 * setting.
2394 **/
2395static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2396{
2397 s32 ret_val;
2398
2399 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2400 if (ret_val) {
3bb99fe2 2401 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 2402 return ret_val;
2403 }
2404
2405 if (*data == ID_LED_RESERVED_0000 ||
2406 *data == ID_LED_RESERVED_FFFF)
2407 *data = ID_LED_DEFAULT_ICH8LAN;
2408
2409 return 0;
2410}
2411
a4f58f54
BA		 2412/**
2413 * e1000_id_led_init_pchlan - store LED configurations
2414 * @hw: pointer to the HW structure
2415 *
2416 * PCH does not control LEDs via the LEDCTL register, rather it uses
2417 * the PHY LED configuration register.
2418 *
2419 * PCH also does not have an "always on" or "always off" mode which
2420 * complicates the ID feature. Instead of using the "on" mode to indicate
2421 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2422 * use "link_up" mode. The LEDs will still ID on request if there is no
2423 * link based on logic in e1000_led_[on|off]_pchlan().
2424 **/
2425static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2426{
2427 struct e1000_mac_info *mac = &hw->mac;
2428 s32 ret_val;
2429 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2430 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2431 u16 data, i, temp, shift;
2432
2433 /* Get default ID LED modes */
2434 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2435 if (ret_val)
2436 goto out;
2437
2438 mac->ledctl_default = er32(LEDCTL);
2439 mac->ledctl_mode1 = mac->ledctl_default;
2440 mac->ledctl_mode2 = mac->ledctl_default;
2441
2442 for (i = 0; i < 4; i++) {
2443 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2444 shift = (i * 5);
2445 switch (temp) {
2446 case ID_LED_ON1_DEF2:
2447 case ID_LED_ON1_ON2:
2448 case ID_LED_ON1_OFF2:
2449 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2450 mac->ledctl_mode1 |= (ledctl_on << shift);
2451 break;
2452 case ID_LED_OFF1_DEF2:
2453 case ID_LED_OFF1_ON2:
2454 case ID_LED_OFF1_OFF2:
2455 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2456 mac->ledctl_mode1 |= (ledctl_off << shift);
2457 break;
2458 default:
2459 /* Do nothing */
2460 break;
2461 }
2462 switch (temp) {
2463 case ID_LED_DEF1_ON2:
2464 case ID_LED_ON1_ON2:
2465 case ID_LED_OFF1_ON2:
2466 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2467 mac->ledctl_mode2 |= (ledctl_on << shift);
2468 break;
2469 case ID_LED_DEF1_OFF2:
2470 case ID_LED_ON1_OFF2:
2471 case ID_LED_OFF1_OFF2:
2472 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2473 mac->ledctl_mode2 |= (ledctl_off << shift);
2474 break;
2475 default:
2476 /* Do nothing */
2477 break;
2478 }
2479 }
2480
2481out:
2482 return ret_val;
2483}
2484
bc7f75fa
AK		 2485/**
2486 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2487 * @hw: pointer to the HW structure
2488 *
2489 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2490 * register, so the the bus width is hard coded.
2491 **/
2492static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2493{
2494 struct e1000_bus_info *bus = &hw->bus;
2495 s32 ret_val;
2496
2497 ret_val = e1000e_get_bus_info_pcie(hw);
2498
ad68076e
BA		 2499 /*
2500 * ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 2501 * a configuration space, but do not contain
2502 * PCI Express Capability registers, so bus width
2503 * must be hardcoded.
2504 */
2505 if (bus->width == e1000_bus_width_unknown)
2506 bus->width = e1000_bus_width_pcie_x1;
2507
2508 return ret_val;
2509}
2510
2511/**
2512 * e1000_reset_hw_ich8lan - Reset the hardware
2513 * @hw: pointer to the HW structure
2514 *
2515 * Does a full reset of the hardware which includes a reset of the PHY and
2516 * MAC.
2517 **/
2518static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2519{
1d5846b9 2520 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
db2932ec 2521 u16 reg;
bc7f75fa
AK		 2522 u32 ctrl, icr, kab;
2523 s32 ret_val;
2524
ad68076e
BA		 2525 /*
2526 * Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 2527 * on the last TLP read/write transaction when MAC is reset.
2528 */
2529 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 2530 if (ret_val)
3bb99fe2 2531 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 2532
3bb99fe2 2533 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 2534 ew32(IMC, 0xffffffff);
2535
ad68076e
BA		 2536 /*
2537 * Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 2538 * any pending transactions to complete before we hit the MAC
2539 * with the global reset.
2540 */
2541 ew32(RCTL, 0);
2542 ew32(TCTL, E1000_TCTL_PSP);
2543 e1e_flush();
2544
2545 msleep(10);
2546
2547 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2548 if (hw->mac.type == e1000_ich8lan) {
2549 /* Set Tx and Rx buffer allocation to 8k apiece. */
2550 ew32(PBA, E1000_PBA_8K);
2551 /* Set Packet Buffer Size to 16k. */
2552 ew32(PBS, E1000_PBS_16K);
2553 }
2554
1d5846b9
BA		 2555 if (hw->mac.type == e1000_pchlan) {
2556 /* Save the NVM K1 bit setting*/
2557 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2558 if (ret_val)
2559 return ret_val;
2560
2561 if (reg & E1000_NVM_K1_ENABLE)
2562 dev_spec->nvm_k1_enabled = true;
2563 else
2564 dev_spec->nvm_k1_enabled = false;
2565 }
2566
bc7f75fa
AK		 2567 ctrl = er32(CTRL);
2568
2569 if (!e1000_check_reset_block(hw)) {
ad68076e 2570 /*
e98cac44 2571 * Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 2572 * time to make sure the interface between MAC and the
2573 * external PHY is reset.
2574 */
2575 ctrl |= E1000_CTRL_PHY_RST;
2576 }
2577 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 2578 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa
AK		 2579 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2580 msleep(20);
2581
fc0c7760 2582 if (!ret_val)
30bb0e0d 2583 e1000_release_swflag_ich8lan(hw);
37f40239 2584
e98cac44 2585 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 2586 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44
BA		 2587 if (ret_val)
2588 goto out;
fc0c7760 2589
e98cac44 2590 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211
BA		 2591 if (ret_val)
2592 goto out;
2593 }
e98cac44 2594
7d3cabbc
BA		 2595 /*
2596 * For PCH, this write will make sure that any noise
2597 * will be detected as a CRC error and be dropped rather than show up
2598 * as a bad packet to the DMA engine.
2599 */
2600 if (hw->mac.type == e1000_pchlan)
2601 ew32(CRC_OFFSET, 0x65656565);
2602
bc7f75fa
AK		 2603 ew32(IMC, 0xffffffff);
2604 icr = er32(ICR);
2605
2606 kab = er32(KABGTXD);
2607 kab |= E1000_KABGTXD_BGSQLBIAS;
2608 ew32(KABGTXD, kab);
2609
f523d211 2610out:
bc7f75fa
AK		 2611 return ret_val;
2612}
2613
2614/**
2615 * e1000_init_hw_ich8lan - Initialize the hardware
2616 * @hw: pointer to the HW structure
2617 *
2618 * Prepares the hardware for transmit and receive by doing the following:
2619 * - initialize hardware bits
2620 * - initialize LED identification
2621 * - setup receive address registers
2622 * - setup flow control
489815ce 2623 * - setup transmit descriptors
bc7f75fa
AK		 2624 * - clear statistics
2625 **/
2626static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2627{
2628 struct e1000_mac_info *mac = &hw->mac;
2629 u32 ctrl_ext, txdctl, snoop;
2630 s32 ret_val;
2631 u16 i;
2632
2633 e1000_initialize_hw_bits_ich8lan(hw);
2634
2635 /* Initialize identification LED */
a4f58f54 2636 ret_val = mac->ops.id_led_init(hw);
de39b752 2637 if (ret_val)
3bb99fe2 2638 e_dbg("Error initializing identification LED\n");
de39b752 2639 /* This is not fatal and we should not stop init due to this */
bc7f75fa
AK		 2640
2641 /* Setup the receive address. */
2642 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2643
2644 /* Zero out the Multicast HASH table */
3bb99fe2 2645 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 2646 for (i = 0; i < mac->mta_reg_count; i++)
2647 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2648
fc0c7760
BA		 2649 /*
2650 * The 82578 Rx buffer will stall if wakeup is enabled in host and
2651 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
2652 * Reset the phy after disabling host wakeup to reset the Rx buffer.
2653 */
2654 if (hw->phy.type == e1000_phy_82578) {
94d8186a 2655 hw->phy.ops.read_reg(hw, BM_WUC, &i);
fc0c7760
BA		 2656 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2657 if (ret_val)
2658 return ret_val;
2659 }
2660
bc7f75fa
AK		 2661 /* Setup link and flow control */
2662 ret_val = e1000_setup_link_ich8lan(hw);
2663
2664 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 2665 txdctl = er32(TXDCTL(0));
bc7f75fa
AK		 2666 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2667 E1000_TXDCTL_FULL_TX_DESC_WB;
2668 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2669 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f
JK		 2670 ew32(TXDCTL(0), txdctl);
2671 txdctl = er32(TXDCTL(1));
bc7f75fa
AK		 2672 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2673 E1000_TXDCTL_FULL_TX_DESC_WB;
2674 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2675 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f 2676 ew32(TXDCTL(1), txdctl);
bc7f75fa 2677
ad68076e
BA		 2678 /*
2679 * ICH8 has opposite polarity of no_snoop bits.
2680 * By default, we should use snoop behavior.
2681 */
bc7f75fa
AK		 2682 if (mac->type == e1000_ich8lan)
2683 snoop = PCIE_ICH8_SNOOP_ALL;
2684 else
2685 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2686 e1000e_set_pcie_no_snoop(hw, snoop);
2687
2688 ctrl_ext = er32(CTRL_EXT);
2689 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2690 ew32(CTRL_EXT, ctrl_ext);
2691
ad68076e
BA		 2692 /*
2693 * Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 2694 * important that we do this after we have tried to establish link
2695 * because the symbol error count will increment wildly if there
2696 * is no link.
2697 */
2698 e1000_clear_hw_cntrs_ich8lan(hw);
2699
2700 return 0;
2701}
2702/**
2703 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2704 * @hw: pointer to the HW structure
2705 *
2706 * Sets/Clears required hardware bits necessary for correctly setting up the
2707 * hardware for transmit and receive.
2708 **/
2709static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2710{
2711 u32 reg;
2712
2713 /* Extended Device Control */
2714 reg = er32(CTRL_EXT);
2715 reg |= (1 << 22);
a4f58f54
BA		 2716 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2717 if (hw->mac.type >= e1000_pchlan)
2718 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 2719 ew32(CTRL_EXT, reg);
2720
2721 /* Transmit Descriptor Control 0 */
e9ec2c0f 2722 reg = er32(TXDCTL(0));
bc7f75fa 2723 reg |= (1 << 22);
e9ec2c0f 2724 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 2725
2726 /* Transmit Descriptor Control 1 */
e9ec2c0f 2727 reg = er32(TXDCTL(1));
bc7f75fa 2728 reg |= (1 << 22);
e9ec2c0f 2729 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 2730
2731 /* Transmit Arbitration Control 0 */
e9ec2c0f 2732 reg = er32(TARC(0));
bc7f75fa
AK		 2733 if (hw->mac.type == e1000_ich8lan)
2734 reg |= (1 << 28) | (1 << 29);
2735 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 2736 ew32(TARC(0), reg);
bc7f75fa
AK		 2737
2738 /* Transmit Arbitration Control 1 */
e9ec2c0f 2739 reg = er32(TARC(1));
bc7f75fa
AK		 2740 if (er32(TCTL) & E1000_TCTL_MULR)
2741 reg &= ~(1 << 28);
2742 else
2743 reg |= (1 << 28);
2744 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 2745 ew32(TARC(1), reg);
bc7f75fa
AK		 2746
2747 /* Device Status */
2748 if (hw->mac.type == e1000_ich8lan) {
2749 reg = er32(STATUS);
2750 reg &= ~(1 << 31);
2751 ew32(STATUS, reg);
2752 }
a80483d3
JB		 2753
2754 /*
2755 * work-around descriptor data corruption issue during nfs v2 udp
2756 * traffic, just disable the nfs filtering capability
2757 */
2758 reg = er32(RFCTL);
2759 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
2760 ew32(RFCTL, reg);
bc7f75fa
AK		 2761}
2762
2763/**
2764 * e1000_setup_link_ich8lan - Setup flow control and link settings
2765 * @hw: pointer to the HW structure
2766 *
2767 * Determines which flow control settings to use, then configures flow
2768 * control. Calls the appropriate media-specific link configuration
2769 * function. Assuming the adapter has a valid link partner, a valid link
2770 * should be established. Assumes the hardware has previously been reset
2771 * and the transmitter and receiver are not enabled.
2772 **/
2773static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2774{
bc7f75fa
AK		 2775 s32 ret_val;
2776
2777 if (e1000_check_reset_block(hw))
2778 return 0;
2779
ad68076e
BA		 2780 /*
2781 * ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 2782 * the default flow control setting, so we explicitly
2783 * set it to full.
2784 */
37289d9c
BA		 2785 if (hw->fc.requested_mode == e1000_fc_default) {
2786 /* Workaround h/w hang when Tx flow control enabled */
2787 if (hw->mac.type == e1000_pchlan)
2788 hw->fc.requested_mode = e1000_fc_rx_pause;
2789 else
2790 hw->fc.requested_mode = e1000_fc_full;
2791 }
bc7f75fa 2792
5c48ef3e
BA		 2793 /*
2794 * Save off the requested flow control mode for use later. Depending
2795 * on the link partner's capabilities, we may or may not use this mode.
2796 */
2797 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 2798
3bb99fe2 2799 e_dbg("After fix-ups FlowControl is now = %x\n",
5c48ef3e 2800 hw->fc.current_mode);
bc7f75fa
AK		 2801
2802 /* Continue to configure the copper link. */
2803 ret_val = e1000_setup_copper_link_ich8lan(hw);
2804 if (ret_val)
2805 return ret_val;
2806
318a94d6 2807 ew32(FCTTV, hw->fc.pause_time);
a4f58f54
BA		 2808 if ((hw->phy.type == e1000_phy_82578) ||
2809 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 2810 ew32(FCRTV_PCH, hw->fc.refresh_time);
2811
94d8186a 2812 ret_val = hw->phy.ops.write_reg(hw,
a4f58f54
BA		 2813 PHY_REG(BM_PORT_CTRL_PAGE, 27),
2814 hw->fc.pause_time);
2815 if (ret_val)
2816 return ret_val;
2817 }
bc7f75fa
AK		 2818
2819 return e1000e_set_fc_watermarks(hw);
2820}
2821
2822/**
2823 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2824 * @hw: pointer to the HW structure
2825 *
2826 * Configures the kumeran interface to the PHY to wait the appropriate time
2827 * when polling the PHY, then call the generic setup_copper_link to finish
2828 * configuring the copper link.
2829 **/
2830static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2831{
2832 u32 ctrl;
2833 s32 ret_val;
2834 u16 reg_data;
2835
2836 ctrl = er32(CTRL);
2837 ctrl |= E1000_CTRL_SLU;
2838 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2839 ew32(CTRL, ctrl);
2840
ad68076e
BA		 2841 /*
2842 * Set the mac to wait the maximum time between each iteration
bc7f75fa 2843 * and increase the max iterations when polling the phy;
ad68076e
BA		 2844 * this fixes erroneous timeouts at 10Mbps.
2845 */
07818950 2846 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 2847 if (ret_val)
2848 return ret_val;
07818950
BA		 2849 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2850 &reg_data);
bc7f75fa
AK		 2851 if (ret_val)
2852 return ret_val;
2853 reg_data |= 0x3F;
07818950
BA		 2854 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2855 reg_data);
bc7f75fa
AK		 2856 if (ret_val)
2857 return ret_val;
2858
a4f58f54
BA		 2859 switch (hw->phy.type) {
2860 case e1000_phy_igp_3:
bc7f75fa
AK		 2861 ret_val = e1000e_copper_link_setup_igp(hw);
2862 if (ret_val)
2863 return ret_val;
a4f58f54
BA		 2864 break;
2865 case e1000_phy_bm:
2866 case e1000_phy_82578:
97ac8cae
BA		 2867 ret_val = e1000e_copper_link_setup_m88(hw);
2868 if (ret_val)
2869 return ret_val;
a4f58f54
BA		 2870 break;
2871 case e1000_phy_82577:
2872 ret_val = e1000_copper_link_setup_82577(hw);
2873 if (ret_val)
2874 return ret_val;
2875 break;
2876 case e1000_phy_ife:
94d8186a 2877 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 2878 &reg_data);
97ac8cae
BA		 2879 if (ret_val)
2880 return ret_val;
2881
2882 reg_data &= ~IFE_PMC_AUTO_MDIX;
2883
2884 switch (hw->phy.mdix) {
2885 case 1:
2886 reg_data &= ~IFE_PMC_FORCE_MDIX;
2887 break;
2888 case 2:
2889 reg_data |= IFE_PMC_FORCE_MDIX;
2890 break;
2891 case 0:
2892 default:
2893 reg_data |= IFE_PMC_AUTO_MDIX;
2894 break;
2895 }
94d8186a 2896 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 2897 reg_data);
97ac8cae
BA		 2898 if (ret_val)
2899 return ret_val;
a4f58f54
BA		 2900 break;
2901 default:
2902 break;
97ac8cae 2903 }
bc7f75fa
AK		 2904 return e1000e_setup_copper_link(hw);
2905}
2906
2907/**
2908 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2909 * @hw: pointer to the HW structure
2910 * @speed: pointer to store current link speed
2911 * @duplex: pointer to store the current link duplex
2912 *
ad68076e 2913 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 2914 * information and then calls the Kumeran lock loss workaround for links at
2915 * gigabit speeds.
2916 **/
2917static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2918 u16 *duplex)
2919{
2920 s32 ret_val;
2921
2922 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2923 if (ret_val)
2924 return ret_val;
2925
2926 if ((hw->mac.type == e1000_ich8lan) &&
2927 (hw->phy.type == e1000_phy_igp_3) &&
2928 (*speed == SPEED_1000)) {
2929 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2930 }
2931
2932 return ret_val;
2933}
2934
2935/**
2936 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2937 * @hw: pointer to the HW structure
2938 *
2939 * Work-around for 82566 Kumeran PCS lock loss:
2940 * On link status change (i.e. PCI reset, speed change) and link is up and
2941 * speed is gigabit-
2942 * 0) if workaround is optionally disabled do nothing
2943 * 1) wait 1ms for Kumeran link to come up
2944 * 2) check Kumeran Diagnostic register PCS lock loss bit
2945 * 3) if not set the link is locked (all is good), otherwise...
2946 * 4) reset the PHY
2947 * 5) repeat up to 10 times
2948 * Note: this is only called for IGP3 copper when speed is 1gb.
2949 **/
2950static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2951{
2952 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2953 u32 phy_ctrl;
2954 s32 ret_val;
2955 u16 i, data;
2956 bool link;
2957
2958 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2959 return 0;
2960
ad68076e
BA		 2961 /*
2962 * Make sure link is up before proceeding. If not just return.
bc7f75fa 2963 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 2964 * stability
2965 */
bc7f75fa
AK		 2966 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2967 if (!link)
2968 return 0;
2969
2970 for (i = 0; i < 10; i++) {
2971 /* read once to clear */
2972 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2973 if (ret_val)
2974 return ret_val;
2975 /* and again to get new status */
2976 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2977 if (ret_val)
2978 return ret_val;
2979
2980 /* check for PCS lock */
2981 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2982 return 0;
2983
2984 /* Issue PHY reset */
2985 e1000_phy_hw_reset(hw);
2986 mdelay(5);
2987 }
2988 /* Disable GigE link negotiation */
2989 phy_ctrl = er32(PHY_CTRL);
2990 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2991 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2992 ew32(PHY_CTRL, phy_ctrl);
2993
ad68076e
BA		 2994 /*
2995 * Call gig speed drop workaround on Gig disable before accessing
2996 * any PHY registers
2997 */
bc7f75fa
AK		 2998 e1000e_gig_downshift_workaround_ich8lan(hw);
2999
3000 /* unable to acquire PCS lock */
3001 return -E1000_ERR_PHY;
3002}
3003
3004/**
ad68076e 3005 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 3006 * @hw: pointer to the HW structure
489815ce 3007 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 3008 *
564ea9bb
BA		 3009 * If ICH8, set the current Kumeran workaround state (enabled - true
3010 * /disabled - false).
bc7f75fa
AK		 3011 **/
3012void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3013 bool state)
3014{
3015 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3016
3017 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 3018 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 3019 return;
3020 }
3021
3022 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3023}
3024
3025/**
3026 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3027 * @hw: pointer to the HW structure
3028 *
3029 * Workaround for 82566 power-down on D3 entry:
3030 * 1) disable gigabit link
3031 * 2) write VR power-down enable
3032 * 3) read it back
3033 * Continue if successful, else issue LCD reset and repeat
3034 **/
3035void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3036{
3037 u32 reg;
3038 u16 data;
3039 u8 retry = 0;
3040
3041 if (hw->phy.type != e1000_phy_igp_3)
3042 return;
3043
3044 /* Try the workaround twice (if needed) */
3045 do {
3046 /* Disable link */
3047 reg = er32(PHY_CTRL);
3048 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3049 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3050 ew32(PHY_CTRL, reg);
3051
ad68076e
BA		 3052 /*
3053 * Call gig speed drop workaround on Gig disable before
3054 * accessing any PHY registers
3055 */
bc7f75fa
AK		 3056 if (hw->mac.type == e1000_ich8lan)
3057 e1000e_gig_downshift_workaround_ich8lan(hw);
3058
3059 /* Write VR power-down enable */
3060 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3061 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3062 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3063
3064 /* Read it back and test */
3065 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3066 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3067 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3068 break;
3069
3070 /* Issue PHY reset and repeat at most one more time */
3071 reg = er32(CTRL);
3072 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3073 retry++;
3074 } while (retry);
3075}
3076
3077/**
3078 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3079 * @hw: pointer to the HW structure
3080 *
3081 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 3082 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 3083 * 1) Set Kumeran Near-end loopback
3084 * 2) Clear Kumeran Near-end loopback
3085 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3086 **/
3087void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3088{
3089 s32 ret_val;
3090 u16 reg_data;
3091
3092 if ((hw->mac.type != e1000_ich8lan) ||
3093 (hw->phy.type != e1000_phy_igp_3))
3094 return;
3095
3096 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3097 &reg_data);
3098 if (ret_val)
3099 return;
3100 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3101 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3102 reg_data);
3103 if (ret_val)
3104 return;
3105 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3106 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3107 reg_data);
3108}
3109
97ac8cae
BA		 3110/**
3111 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3112 * @hw: pointer to the HW structure
3113 *
3114 * During S0 to Sx transition, it is possible the link remains at gig
3115 * instead of negotiating to a lower speed. Before going to Sx, set
3116 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3117 * to a lower speed.
3118 *
a4f58f54 3119 * Should only be called for applicable parts.
97ac8cae
BA		 3120 **/
3121void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3122{
3123 u32 phy_ctrl;
3124
a4f58f54 3125 switch (hw->mac.type) {
9e135a2e 3126 case e1000_ich8lan:
a4f58f54
BA		 3127 case e1000_ich9lan:
3128 case e1000_ich10lan:
3129 case e1000_pchlan:
97ac8cae
BA		 3130 phy_ctrl = er32(PHY_CTRL);
3131 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3132 E1000_PHY_CTRL_GBE_DISABLE;
3133 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 3134
a4f58f54 3135 if (hw->mac.type == e1000_pchlan)
74eee2e8 3136 e1000_phy_hw_reset_ich8lan(hw);
a4f58f54
BA		 3137 default:
3138 break;
97ac8cae 3139 }
97ac8cae
BA		 3140}
3141
bc7f75fa
AK		 3142/**
3143 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3144 * @hw: pointer to the HW structure
3145 *
3146 * Return the LED back to the default configuration.
3147 **/
3148static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3149{
3150 if (hw->phy.type == e1000_phy_ife)
3151 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3152
3153 ew32(LEDCTL, hw->mac.ledctl_default);
3154 return 0;
3155}
3156
3157/**
489815ce 3158 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 3159 * @hw: pointer to the HW structure
3160 *
489815ce 3161 * Turn on the LEDs.
bc7f75fa
AK		 3162 **/
3163static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3164{
3165 if (hw->phy.type == e1000_phy_ife)
3166 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3167 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3168
3169 ew32(LEDCTL, hw->mac.ledctl_mode2);
3170 return 0;
3171}
3172
3173/**
489815ce 3174 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 3175 * @hw: pointer to the HW structure
3176 *
489815ce 3177 * Turn off the LEDs.
bc7f75fa
AK		 3178 **/
3179static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3180{
3181 if (hw->phy.type == e1000_phy_ife)
3182 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3183 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3184
3185 ew32(LEDCTL, hw->mac.ledctl_mode1);
3186 return 0;
3187}
3188
a4f58f54
BA		 3189/**
3190 * e1000_setup_led_pchlan - Configures SW controllable LED
3191 * @hw: pointer to the HW structure
3192 *
3193 * This prepares the SW controllable LED for use.
3194 **/
3195static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3196{
94d8186a 3197 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3198 (u16)hw->mac.ledctl_mode1);
3199}
3200
3201/**
3202 * e1000_cleanup_led_pchlan - Restore the default LED operation
3203 * @hw: pointer to the HW structure
3204 *
3205 * Return the LED back to the default configuration.
3206 **/
3207static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3208{
94d8186a 3209 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3210 (u16)hw->mac.ledctl_default);
3211}
3212
3213/**
3214 * e1000_led_on_pchlan - Turn LEDs on
3215 * @hw: pointer to the HW structure
3216 *
3217 * Turn on the LEDs.
3218 **/
3219static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3220{
3221 u16 data = (u16)hw->mac.ledctl_mode2;
3222 u32 i, led;
3223
3224 /*
3225 * If no link, then turn LED on by setting the invert bit
3226 * for each LED that's mode is "link_up" in ledctl_mode2.
3227 */
3228 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3229 for (i = 0; i < 3; i++) {
3230 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3231 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3232 E1000_LEDCTL_MODE_LINK_UP)
3233 continue;
3234 if (led & E1000_PHY_LED0_IVRT)
3235 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3236 else
3237 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3238 }
3239 }
3240
94d8186a 3241 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3242}
3243
3244/**
3245 * e1000_led_off_pchlan - Turn LEDs off
3246 * @hw: pointer to the HW structure
3247 *
3248 * Turn off the LEDs.
3249 **/
3250static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3251{
3252 u16 data = (u16)hw->mac.ledctl_mode1;
3253 u32 i, led;
3254
3255 /*
3256 * If no link, then turn LED off by clearing the invert bit
3257 * for each LED that's mode is "link_up" in ledctl_mode1.
3258 */
3259 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3260 for (i = 0; i < 3; i++) {
3261 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3262 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3263 E1000_LEDCTL_MODE_LINK_UP)
3264 continue;
3265 if (led & E1000_PHY_LED0_IVRT)
3266 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3267 else
3268 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3269 }
3270 }
3271
94d8186a 3272 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3273}
3274
f4187b56 3275/**
e98cac44 3276 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 3277 * @hw: pointer to the HW structure
3278 *
e98cac44
BA		 3279 * Read appropriate register for the config done bit for completion status
3280 * and configure the PHY through s/w for EEPROM-less parts.
3281 *
3282 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3283 * config done bit, so only an error is logged and continues. If we were
3284 * to return with error, EEPROM-less silicon would not be able to be reset
3285 * or change link.
f4187b56
BA		 3286 **/
3287static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3288{
e98cac44 3289 s32 ret_val = 0;
f4187b56 3290 u32 bank = 0;
e98cac44 3291 u32 status;
f4187b56 3292
e98cac44 3293 e1000e_get_cfg_done(hw);
fc0c7760 3294
e98cac44
BA		 3295 /* Wait for indication from h/w that it has completed basic config */
3296 if (hw->mac.type >= e1000_ich10lan) {
3297 e1000_lan_init_done_ich8lan(hw);
3298 } else {
3299 ret_val = e1000e_get_auto_rd_done(hw);
3300 if (ret_val) {
3301 /*
3302 * When auto config read does not complete, do not
3303 * return with an error. This can happen in situations
3304 * where there is no eeprom and prevents getting link.
3305 */
3306 e_dbg("Auto Read Done did not complete\n");
3307 ret_val = 0;
3308 }
fc0c7760
BA		 3309 }
3310
e98cac44
BA		 3311 /* Clear PHY Reset Asserted bit */
3312 status = er32(STATUS);
3313 if (status & E1000_STATUS_PHYRA)
3314 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3315 else
3316 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 3317
3318 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 3319 if (hw->mac.type <= e1000_ich9lan) {
f4187b56
BA		 3320 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3321 (hw->phy.type == e1000_phy_igp_3)) {
3322 e1000e_phy_init_script_igp3(hw);
3323 }
3324 } else {
3325 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3326 /* Maybe we should do a basic PHY config */
3bb99fe2 3327 e_dbg("EEPROM not present\n");
e98cac44 3328 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 3329 }
3330 }
3331
e98cac44 3332 return ret_val;
f4187b56
BA		 3333}
3334
17f208de
BA		 3335/**
3336 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3337 * @hw: pointer to the HW structure
3338 *
3339 * In the case of a PHY power down to save power, or to turn off link during a
3340 * driver unload, or wake on lan is not enabled, remove the link.
3341 **/
3342static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3343{
3344 /* If the management interface is not enabled, then power down */
3345 if (!(hw->mac.ops.check_mng_mode(hw) ||
3346 hw->phy.ops.check_reset_block(hw)))
3347 e1000_power_down_phy_copper(hw);
17f208de
BA		 3348}
3349
bc7f75fa
AK		 3350/**
3351 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3352 * @hw: pointer to the HW structure
3353 *
3354 * Clears hardware counters specific to the silicon family and calls
3355 * clear_hw_cntrs_generic to clear all general purpose counters.
3356 **/
3357static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3358{
a4f58f54 3359 u16 phy_data;
bc7f75fa
AK		 3360
3361 e1000e_clear_hw_cntrs_base(hw);
3362
99673d9b
BA		 3363 er32(ALGNERRC);
3364 er32(RXERRC);
3365 er32(TNCRS);
3366 er32(CEXTERR);
3367 er32(TSCTC);
3368 er32(TSCTFC);
bc7f75fa 3369
99673d9b
BA		 3370 er32(MGTPRC);
3371 er32(MGTPDC);
3372 er32(MGTPTC);
bc7f75fa 3373
99673d9b
BA		 3374 er32(IAC);
3375 er32(ICRXOC);
bc7f75fa 3376
a4f58f54
BA		 3377 /* Clear PHY statistics registers */
3378 if ((hw->phy.type == e1000_phy_82578) ||
3379 (hw->phy.type == e1000_phy_82577)) {
94d8186a
BA		 3380 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3381 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3382 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3383 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3384 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3385 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3386 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3387 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3388 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3389 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3390 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3391 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3392 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3393 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
a4f58f54 3394 }
bc7f75fa
AK		 3395}
3396
3397static struct e1000_mac_operations ich8_mac_ops = {
a4f58f54 3398 .id_led_init = e1000e_id_led_init,
4662e82b 3399 .check_mng_mode = e1000_check_mng_mode_ich8lan,
7d3cabbc 3400 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 3401 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 3402 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3403 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 3404 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 3405 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 3406 /* led_on dependent on mac type */
3407 /* led_off dependent on mac type */
e2de3eb6 3408 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 3409 .reset_hw = e1000_reset_hw_ich8lan,
3410 .init_hw = e1000_init_hw_ich8lan,
3411 .setup_link = e1000_setup_link_ich8lan,
3412 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
a4f58f54 3413 /* id_led_init dependent on mac type */
bc7f75fa
AK		 3414};
3415
3416static struct e1000_phy_operations ich8_phy_ops = {
94d8186a 3417 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 3418 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 3419 .commit = NULL,
f4187b56 3420 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 3421 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 3422 .read_reg = e1000e_read_phy_reg_igp,
3423 .release = e1000_release_swflag_ich8lan,
3424 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 3425 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3426 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 3427 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 3428};
3429
3430static struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a
BA		 3431 .acquire = e1000_acquire_nvm_ich8lan,
3432 .read = e1000_read_nvm_ich8lan,
3433 .release = e1000_release_nvm_ich8lan,
3434 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 3435 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 3436 .validate = e1000_validate_nvm_checksum_ich8lan,
3437 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 3438};
3439
3440struct e1000_info e1000_ich8_info = {
3441 .mac = e1000_ich8lan,
3442 .flags = FLAG_HAS_WOL
97ac8cae 3443 | FLAG_IS_ICH
bc7f75fa
AK		 3444 | FLAG_RX_CSUM_ENABLED
3445 | FLAG_HAS_CTRLEXT_ON_LOAD
3446 | FLAG_HAS_AMT
3447 | FLAG_HAS_FLASH
3448 | FLAG_APME_IN_WUC,
3449 .pba = 8,
2adc55c9 3450 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 3451 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3452 .mac_ops = &ich8_mac_ops,
3453 .phy_ops = &ich8_phy_ops,
3454 .nvm_ops = &ich8_nvm_ops,
3455};
3456
3457struct e1000_info e1000_ich9_info = {
3458 .mac = e1000_ich9lan,
3459 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 3460 | FLAG_IS_ICH
bc7f75fa
AK		 3461 | FLAG_HAS_WOL
3462 | FLAG_RX_CSUM_ENABLED
3463 | FLAG_HAS_CTRLEXT_ON_LOAD
3464 | FLAG_HAS_AMT
3465 | FLAG_HAS_ERT
3466 | FLAG_HAS_FLASH
3467 | FLAG_APME_IN_WUC,
3468 .pba = 10,
2adc55c9 3469 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 3470 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3471 .mac_ops = &ich8_mac_ops,
3472 .phy_ops = &ich8_phy_ops,
3473 .nvm_ops = &ich8_nvm_ops,
3474};
3475
f4187b56
BA		 3476struct e1000_info e1000_ich10_info = {
3477 .mac = e1000_ich10lan,
3478 .flags = FLAG_HAS_JUMBO_FRAMES
3479 | FLAG_IS_ICH
3480 | FLAG_HAS_WOL
3481 | FLAG_RX_CSUM_ENABLED
3482 | FLAG_HAS_CTRLEXT_ON_LOAD
3483 | FLAG_HAS_AMT
3484 | FLAG_HAS_ERT
3485 | FLAG_HAS_FLASH
3486 | FLAG_APME_IN_WUC,
3487 .pba = 10,
2adc55c9 3488 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 3489 .get_variants = e1000_get_variants_ich8lan,
3490 .mac_ops = &ich8_mac_ops,
3491 .phy_ops = &ich8_phy_ops,
3492 .nvm_ops = &ich8_nvm_ops,
3493};
a4f58f54
BA		 3494
3495struct e1000_info e1000_pch_info = {
3496 .mac = e1000_pchlan,
3497 .flags = FLAG_IS_ICH
3498 | FLAG_HAS_WOL
3499 | FLAG_RX_CSUM_ENABLED
3500 | FLAG_HAS_CTRLEXT_ON_LOAD
3501 | FLAG_HAS_AMT
3502 | FLAG_HAS_FLASH
3503 | FLAG_HAS_JUMBO_FRAMES
38eb394e 3504 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54
BA		 3505 | FLAG_APME_IN_WUC,
3506 .pba = 26,
3507 .max_hw_frame_size = 4096,
3508 .get_variants = e1000_get_variants_ich8lan,
3509 .mac_ops = &ich8_mac_ops,
3510 .phy_ops = &ich8_phy_ops,
3511 .nvm_ops = &ich8_nvm_ops,
3512};
Linux kernel - Deliverables
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