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e1000e: 82566DC fails to get link
[deliverable/linux.git] / drivers / net / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
451152d9 4 Copyright(c) 1999 - 2010 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
1605927f 30 * 82562G 10/100 Network Connection
bc7f75fa
AK		 31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
97ac8cae
BA		 42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
1605927f 44 * 82567V Gigabit Network Connection
97ac8cae
BA		 45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
2f15f9d6 50 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
d3738bb8
BA		 55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
bc7f75fa
AK		 57 */
58
bc7f75fa
AK		 59#include "e1000.h"
60
61#define ICH_FLASH_GFPREG 0x0000
62#define ICH_FLASH_HSFSTS 0x0004
63#define ICH_FLASH_HSFCTL 0x0006
64#define ICH_FLASH_FADDR 0x0008
65#define ICH_FLASH_FDATA0 0x0010
4a770358 66#define ICH_FLASH_PR0 0x0074
bc7f75fa
AK		 67
68#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74#define ICH_CYCLE_READ 0
75#define ICH_CYCLE_WRITE 2
76#define ICH_CYCLE_ERASE 3
77
78#define FLASH_GFPREG_BASE_MASK 0x1FFF
79#define FLASH_SECTOR_ADDR_SHIFT 12
80
81#define ICH_FLASH_SEG_SIZE_256 256
82#define ICH_FLASH_SEG_SIZE_4K 4096
83#define ICH_FLASH_SEG_SIZE_8K 8192
84#define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
6dfaa769
BA		 88/* FW established a valid mode */
89#define E1000_ICH_FWSM_FW_VALID 0x00008000
bc7f75fa
AK		 90
91#define E1000_ICH_MNG_IAMT_MODE 0x2
92
93#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98#define E1000_ICH_NVM_SIG_WORD 0x13
99#define E1000_ICH_NVM_SIG_MASK 0xC000
e243455d
BA		 100#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101#define E1000_ICH_NVM_SIG_VALUE 0x80
bc7f75fa
AK		 102
103#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105#define E1000_FEXTNVM_SW_CONFIG 1
106#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
108#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
109
110#define E1000_ICH_RAR_ENTRIES 7
111
112#define PHY_PAGE_SHIFT 5
113#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
114 ((reg) & MAX_PHY_REG_ADDRESS))
115#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
116#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
117
118#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
119#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
120#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
121
a4f58f54
BA		 122#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
123
53ac5a88
BA		 124#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
125
f523d211
BA		 126/* SMBus Address Phy Register */
127#define HV_SMB_ADDR PHY_REG(768, 26)
8395ae83 128#define HV_SMB_ADDR_MASK 0x007F
f523d211
BA		 129#define HV_SMB_ADDR_PEC_EN 0x0200
130#define HV_SMB_ADDR_VALID 0x0080
131
d3738bb8
BA		 132/* PHY Power Management Control */
133#define HV_PM_CTRL PHY_REG(770, 17)
134
e52997f9
BA		 135/* PHY Low Power Idle Control */
136#define I82579_LPI_CTRL PHY_REG(772, 20)
137#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
138
f523d211
BA		 139/* Strapping Option Register - RO */
140#define E1000_STRAP 0x0000C
141#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
142#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
143
fa2ce13c
BA		 144/* OEM Bits Phy Register */
145#define HV_OEM_BITS PHY_REG(768, 25)
146#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
f523d211 147#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
fa2ce13c
BA		 148#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
149
1d5846b9
BA		 150#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
151#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
152
fddaa1af
BA		 153/* KMRN Mode Control */
154#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
155#define HV_KMRN_MDIO_SLOW 0x0400
156
bc7f75fa
AK		 157/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
158/* Offset 04h HSFSTS */
159union ich8_hws_flash_status {
160 struct ich8_hsfsts {
161 u16 flcdone :1; /* bit 0 Flash Cycle Done */
162 u16 flcerr :1; /* bit 1 Flash Cycle Error */
163 u16 dael :1; /* bit 2 Direct Access error Log */
164 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
165 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
166 u16 reserved1 :2; /* bit 13:6 Reserved */
167 u16 reserved2 :6; /* bit 13:6 Reserved */
168 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
169 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
170 } hsf_status;
171 u16 regval;
172};
173
174/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
175/* Offset 06h FLCTL */
176union ich8_hws_flash_ctrl {
177 struct ich8_hsflctl {
178 u16 flcgo :1; /* 0 Flash Cycle Go */
179 u16 flcycle :2; /* 2:1 Flash Cycle */
180 u16 reserved :5; /* 7:3 Reserved */
181 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
182 u16 flockdn :6; /* 15:10 Reserved */
183 } hsf_ctrl;
184 u16 regval;
185};
186
187/* ICH Flash Region Access Permissions */
188union ich8_hws_flash_regacc {
189 struct ich8_flracc {
190 u32 grra :8; /* 0:7 GbE region Read Access */
191 u32 grwa :8; /* 8:15 GbE region Write Access */
192 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
193 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
194 } hsf_flregacc;
195 u16 regval;
196};
197
4a770358
BA		 198/* ICH Flash Protected Region */
199union ich8_flash_protected_range {
200 struct ich8_pr {
201 u32 base:13; /* 0:12 Protected Range Base */
202 u32 reserved1:2; /* 13:14 Reserved */
203 u32 rpe:1; /* 15 Read Protection Enable */
204 u32 limit:13; /* 16:28 Protected Range Limit */
205 u32 reserved2:2; /* 29:30 Reserved */
206 u32 wpe:1; /* 31 Write Protection Enable */
207 } range;
208 u32 regval;
209};
210
bc7f75fa
AK		 211static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
212static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
213static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 214static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
215static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
216 u32 offset, u8 byte);
f4187b56
BA		 217static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
218 u8 *data);
bc7f75fa
AK		 219static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
220 u16 *data);
221static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
222 u8 size, u16 *data);
223static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
224static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
f4187b56 225static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 226static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
227static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
228static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
229static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
230static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
231static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
232static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
233static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 234static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 235static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 236static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1d5846b9 237static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 238static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
eb7700dc
BA		 239static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
240static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
bc7f75fa
AK		 241
242static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
243{
244 return readw(hw->flash_address + reg);
245}
246
247static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
248{
249 return readl(hw->flash_address + reg);
250}
251
252static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
253{
254 writew(val, hw->flash_address + reg);
255}
256
257static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
258{
259 writel(val, hw->flash_address + reg);
260}
261
262#define er16flash(reg) __er16flash(hw, (reg))
263#define er32flash(reg) __er32flash(hw, (reg))
264#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
265#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
266
a4f58f54
BA		 267/**
268 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
269 * @hw: pointer to the HW structure
270 *
271 * Initialize family-specific PHY parameters and function pointers.
272 **/
273static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
274{
275 struct e1000_phy_info *phy = &hw->phy;
6dfaa769 276 u32 ctrl;
a4f58f54
BA		 277 s32 ret_val = 0;
278
279 phy->addr = 1;
280 phy->reset_delay_us = 100;
281
94d8186a
BA		 282 phy->ops.read_reg = e1000_read_phy_reg_hv;
283 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
fa2ce13c
BA		 284 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
285 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
94d8186a
BA		 286 phy->ops.write_reg = e1000_write_phy_reg_hv;
287 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
17f208de
BA		 288 phy->ops.power_up = e1000_power_up_phy_copper;
289 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
a4f58f54
BA		 290 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
291
d3738bb8
BA		 292 /*
293 * The MAC-PHY interconnect may still be in SMBus mode
294 * after Sx->S0. If the manageability engine (ME) is
295 * disabled, then toggle the LANPHYPC Value bit to force
296 * the interconnect to PCIe mode.
297 */
6dfaa769 298 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
6dfaa769
BA		 299 ctrl = er32(CTRL);
300 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
301 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
302 ew32(CTRL, ctrl);
303 udelay(10);
304 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
305 ew32(CTRL, ctrl);
306 msleep(50);
307 }
308
627c8a04
BA		 309 /*
310 * Reset the PHY before any acccess to it. Doing so, ensures that
311 * the PHY is in a known good state before we read/write PHY registers.
312 * The generic reset is sufficient here, because we haven't determined
313 * the PHY type yet.
314 */
315 ret_val = e1000e_phy_hw_reset_generic(hw);
316 if (ret_val)
317 goto out;
318
a4f58f54 319 phy->id = e1000_phy_unknown;
fddaa1af
BA		 320 ret_val = e1000e_get_phy_id(hw);
321 if (ret_val)
322 goto out;
323 if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
324 /*
325 * In case the PHY needs to be in mdio slow mode (eg. 82577),
326 * set slow mode and try to get the PHY id again.
327 */
328 ret_val = e1000_set_mdio_slow_mode_hv(hw);
329 if (ret_val)
330 goto out;
331 ret_val = e1000e_get_phy_id(hw);
332 if (ret_val)
333 goto out;
334 }
a4f58f54
BA		 335 phy->type = e1000e_get_phy_type_from_id(phy->id);
336
0be84010
BA		 337 switch (phy->type) {
338 case e1000_phy_82577:
d3738bb8 339 case e1000_phy_82579:
a4f58f54
BA		 340 phy->ops.check_polarity = e1000_check_polarity_82577;
341 phy->ops.force_speed_duplex =
342 e1000_phy_force_speed_duplex_82577;
0be84010 343 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 344 phy->ops.get_info = e1000_get_phy_info_82577;
345 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 346 break;
0be84010
BA		 347 case e1000_phy_82578:
348 phy->ops.check_polarity = e1000_check_polarity_m88;
349 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
350 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
351 phy->ops.get_info = e1000e_get_phy_info_m88;
352 break;
353 default:
354 ret_val = -E1000_ERR_PHY;
355 break;
a4f58f54
BA		 356 }
357
fddaa1af 358out:
a4f58f54
BA		 359 return ret_val;
360}
361
bc7f75fa
AK		 362/**
363 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
364 * @hw: pointer to the HW structure
365 *
366 * Initialize family-specific PHY parameters and function pointers.
367 **/
368static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
369{
370 struct e1000_phy_info *phy = &hw->phy;
371 s32 ret_val;
372 u16 i = 0;
373
374 phy->addr = 1;
375 phy->reset_delay_us = 100;
376
17f208de
BA		 377 phy->ops.power_up = e1000_power_up_phy_copper;
378 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
379
97ac8cae
BA		 380 /*
381 * We may need to do this twice - once for IGP and if that fails,
382 * we'll set BM func pointers and try again
383 */
384 ret_val = e1000e_determine_phy_address(hw);
385 if (ret_val) {
94d8186a
BA		 386 phy->ops.write_reg = e1000e_write_phy_reg_bm;
387 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 388 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 389 if (ret_val) {
390 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 391 return ret_val;
9b71b419 392 }
97ac8cae
BA		 393 }
394
bc7f75fa
AK		 395 phy->id = 0;
396 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
397 (i++ < 100)) {
398 msleep(1);
399 ret_val = e1000e_get_phy_id(hw);
400 if (ret_val)
401 return ret_val;
402 }
403
404 /* Verify phy id */
405 switch (phy->id) {
406 case IGP03E1000_E_PHY_ID:
407 phy->type = e1000_phy_igp_3;
408 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 409 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
410 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 411 phy->ops.get_info = e1000e_get_phy_info_igp;
412 phy->ops.check_polarity = e1000_check_polarity_igp;
413 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 414 break;
415 case IFE_E_PHY_ID:
416 case IFE_PLUS_E_PHY_ID:
417 case IFE_C_E_PHY_ID:
418 phy->type = e1000_phy_ife;
419 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 420 phy->ops.get_info = e1000_get_phy_info_ife;
421 phy->ops.check_polarity = e1000_check_polarity_ife;
422 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 423 break;
97ac8cae
BA		 424 case BME1000_E_PHY_ID:
425 phy->type = e1000_phy_bm;
426 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 427 phy->ops.read_reg = e1000e_read_phy_reg_bm;
428 phy->ops.write_reg = e1000e_write_phy_reg_bm;
429 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 430 phy->ops.get_info = e1000e_get_phy_info_m88;
431 phy->ops.check_polarity = e1000_check_polarity_m88;
432 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 433 break;
bc7f75fa
AK		 434 default:
435 return -E1000_ERR_PHY;
436 break;
437 }
438
439 return 0;
440}
441
442/**
443 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
444 * @hw: pointer to the HW structure
445 *
446 * Initialize family-specific NVM parameters and function
447 * pointers.
448 **/
449static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
450{
451 struct e1000_nvm_info *nvm = &hw->nvm;
452 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 453 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 454 u16 i;
455
ad68076e 456 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 457 if (!hw->flash_address) {
3bb99fe2 458 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 459 return -E1000_ERR_CONFIG;
460 }
461
462 nvm->type = e1000_nvm_flash_sw;
463
464 gfpreg = er32flash(ICH_FLASH_GFPREG);
465
ad68076e
BA		 466 /*
467 * sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 468 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 469 * the overall size.
470 */
bc7f75fa
AK		 471 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
472 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
473
474 /* flash_base_addr is byte-aligned */
475 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
476
ad68076e
BA		 477 /*
478 * find total size of the NVM, then cut in half since the total
479 * size represents two separate NVM banks.
480 */
bc7f75fa
AK		 481 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
482 << FLASH_SECTOR_ADDR_SHIFT;
483 nvm->flash_bank_size /= 2;
484 /* Adjust to word count */
485 nvm->flash_bank_size /= sizeof(u16);
486
487 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
488
489 /* Clear shadow ram */
490 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 491 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 492 dev_spec->shadow_ram[i].value = 0xFFFF;
493 }
494
495 return 0;
496}
497
498/**
499 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
500 * @hw: pointer to the HW structure
501 *
502 * Initialize family-specific MAC parameters and function
503 * pointers.
504 **/
505static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
506{
507 struct e1000_hw *hw = &adapter->hw;
508 struct e1000_mac_info *mac = &hw->mac;
509
510 /* Set media type function pointer */
318a94d6 511 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 512
513 /* Set mta register count */
514 mac->mta_reg_count = 32;
515 /* Set rar entry count */
516 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
517 if (mac->type == e1000_ich8lan)
518 mac->rar_entry_count--;
a65a4a0d
BA		 519 /* FWSM register */
520 mac->has_fwsm = true;
521 /* ARC subsystem not supported */
522 mac->arc_subsystem_valid = false;
f464ba87
BA		 523 /* Adaptive IFS supported */
524 mac->adaptive_ifs = true;
bc7f75fa 525
a4f58f54
BA		 526 /* LED operations */
527 switch (mac->type) {
528 case e1000_ich8lan:
529 case e1000_ich9lan:
530 case e1000_ich10lan:
eb7700dc
BA		 531 /* check management mode */
532 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
a4f58f54
BA		 533 /* ID LED init */
534 mac->ops.id_led_init = e1000e_id_led_init;
535 /* setup LED */
536 mac->ops.setup_led = e1000e_setup_led_generic;
537 /* cleanup LED */
538 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
539 /* turn on/off LED */
540 mac->ops.led_on = e1000_led_on_ich8lan;
541 mac->ops.led_off = e1000_led_off_ich8lan;
542 break;
543 case e1000_pchlan:
d3738bb8 544 case e1000_pch2lan:
eb7700dc
BA		 545 /* check management mode */
546 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
a4f58f54
BA		 547 /* ID LED init */
548 mac->ops.id_led_init = e1000_id_led_init_pchlan;
549 /* setup LED */
550 mac->ops.setup_led = e1000_setup_led_pchlan;
551 /* cleanup LED */
552 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
553 /* turn on/off LED */
554 mac->ops.led_on = e1000_led_on_pchlan;
555 mac->ops.led_off = e1000_led_off_pchlan;
556 break;
557 default:
558 break;
559 }
560
bc7f75fa
AK		 561 /* Enable PCS Lock-loss workaround for ICH8 */
562 if (mac->type == e1000_ich8lan)
564ea9bb 563 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa 564
d3738bb8
BA		 565 /* Disable PHY configuration by hardware, config by software */
566 if (mac->type == e1000_pch2lan) {
567 u32 extcnf_ctrl = er32(EXTCNF_CTRL);
568
569 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
570 ew32(EXTCNF_CTRL, extcnf_ctrl);
571 }
572
bc7f75fa
AK		 573 return 0;
574}
575
e52997f9
BA		 576/**
577 * e1000_set_eee_pchlan - Enable/disable EEE support
578 * @hw: pointer to the HW structure
579 *
580 * Enable/disable EEE based on setting in dev_spec structure. The bits in
581 * the LPI Control register will remain set only if/when link is up.
582 **/
583static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
584{
585 s32 ret_val = 0;
586 u16 phy_reg;
587
588 if (hw->phy.type != e1000_phy_82579)
589 goto out;
590
591 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
592 if (ret_val)
593 goto out;
594
595 if (hw->dev_spec.ich8lan.eee_disable)
596 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
597 else
598 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
599
600 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
601out:
602 return ret_val;
603}
604
7d3cabbc
BA		 605/**
606 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
607 * @hw: pointer to the HW structure
608 *
609 * Checks to see of the link status of the hardware has changed. If a
610 * change in link status has been detected, then we read the PHY registers
611 * to get the current speed/duplex if link exists.
612 **/
613static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
614{
615 struct e1000_mac_info *mac = &hw->mac;
616 s32 ret_val;
617 bool link;
618
619 /*
620 * We only want to go out to the PHY registers to see if Auto-Neg
621 * has completed and/or if our link status has changed. The
622 * get_link_status flag is set upon receiving a Link Status
623 * Change or Rx Sequence Error interrupt.
624 */
625 if (!mac->get_link_status) {
626 ret_val = 0;
627 goto out;
628 }
629
7d3cabbc
BA		 630 /*
631 * First we want to see if the MII Status Register reports
632 * link. If so, then we want to get the current speed/duplex
633 * of the PHY.
634 */
635 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
636 if (ret_val)
637 goto out;
638
1d5846b9
BA		 639 if (hw->mac.type == e1000_pchlan) {
640 ret_val = e1000_k1_gig_workaround_hv(hw, link);
641 if (ret_val)
642 goto out;
643 }
644
7d3cabbc
BA		 645 if (!link)
646 goto out; /* No link detected */
647
648 mac->get_link_status = false;
649
650 if (hw->phy.type == e1000_phy_82578) {
651 ret_val = e1000_link_stall_workaround_hv(hw);
652 if (ret_val)
653 goto out;
654 }
655
656 /*
657 * Check if there was DownShift, must be checked
658 * immediately after link-up
659 */
660 e1000e_check_downshift(hw);
661
e52997f9
BA		 662 /* Enable/Disable EEE after link up */
663 ret_val = e1000_set_eee_pchlan(hw);
664 if (ret_val)
665 goto out;
666
7d3cabbc
BA		 667 /*
668 * If we are forcing speed/duplex, then we simply return since
669 * we have already determined whether we have link or not.
670 */
671 if (!mac->autoneg) {
672 ret_val = -E1000_ERR_CONFIG;
673 goto out;
674 }
675
676 /*
677 * Auto-Neg is enabled. Auto Speed Detection takes care
678 * of MAC speed/duplex configuration. So we only need to
679 * configure Collision Distance in the MAC.
680 */
681 e1000e_config_collision_dist(hw);
682
683 /*
684 * Configure Flow Control now that Auto-Neg has completed.
685 * First, we need to restore the desired flow control
686 * settings because we may have had to re-autoneg with a
687 * different link partner.
688 */
689 ret_val = e1000e_config_fc_after_link_up(hw);
690 if (ret_val)
3bb99fe2 691 e_dbg("Error configuring flow control\n");
7d3cabbc
BA		 692
693out:
694 return ret_val;
695}
696
69e3fd8c 697static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 698{
699 struct e1000_hw *hw = &adapter->hw;
700 s32 rc;
701
702 rc = e1000_init_mac_params_ich8lan(adapter);
703 if (rc)
704 return rc;
705
706 rc = e1000_init_nvm_params_ich8lan(hw);
707 if (rc)
708 return rc;
709
d3738bb8
BA		 710 switch (hw->mac.type) {
711 case e1000_ich8lan:
712 case e1000_ich9lan:
713 case e1000_ich10lan:
a4f58f54 714 rc = e1000_init_phy_params_ich8lan(hw);
d3738bb8
BA		 715 break;
716 case e1000_pchlan:
717 case e1000_pch2lan:
718 rc = e1000_init_phy_params_pchlan(hw);
719 break;
720 default:
721 break;
722 }
bc7f75fa
AK		 723 if (rc)
724 return rc;
725
2adc55c9
BA		 726 if (adapter->hw.phy.type == e1000_phy_ife) {
727 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
728 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
729 }
730
bc7f75fa
AK		 731 if ((adapter->hw.mac.type == e1000_ich8lan) &&
732 (adapter->hw.phy.type == e1000_phy_igp_3))
733 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
734
5a86f28f
BA		 735 /* Disable EEE by default until IEEE802.3az spec is finalized */
736 if (adapter->flags2 & FLAG2_HAS_EEE)
737 adapter->hw.dev_spec.ich8lan.eee_disable = true;
738
bc7f75fa
AK		 739 return 0;
740}
741
717d438d 742static DEFINE_MUTEX(nvm_mutex);
717d438d 743
ca15df58
BA		 744/**
745 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
746 * @hw: pointer to the HW structure
747 *
748 * Acquires the mutex for performing NVM operations.
749 **/
750static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
751{
752 mutex_lock(&nvm_mutex);
753
754 return 0;
755}
756
757/**
758 * e1000_release_nvm_ich8lan - Release NVM mutex
759 * @hw: pointer to the HW structure
760 *
761 * Releases the mutex used while performing NVM operations.
762 **/
763static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
764{
765 mutex_unlock(&nvm_mutex);
ca15df58
BA		 766}
767
768static DEFINE_MUTEX(swflag_mutex);
769
bc7f75fa
AK		 770/**
771 * e1000_acquire_swflag_ich8lan - Acquire software control flag
772 * @hw: pointer to the HW structure
773 *
ca15df58
BA		 774 * Acquires the software control flag for performing PHY and select
775 * MAC CSR accesses.
bc7f75fa
AK		 776 **/
777static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
778{
373a88d7
BA		 779 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
780 s32 ret_val = 0;
bc7f75fa 781
ca15df58 782 mutex_lock(&swflag_mutex);
717d438d 783
bc7f75fa
AK		 784 while (timeout) {
785 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 786 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
787 break;
bc7f75fa 788
373a88d7
BA		 789 mdelay(1);
790 timeout--;
791 }
792
793 if (!timeout) {
3bb99fe2 794 e_dbg("SW/FW/HW has locked the resource for too long.\n");
373a88d7
BA		 795 ret_val = -E1000_ERR_CONFIG;
796 goto out;
797 }
798
53ac5a88 799 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 800
801 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
802 ew32(EXTCNF_CTRL, extcnf_ctrl);
803
804 while (timeout) {
805 extcnf_ctrl = er32(EXTCNF_CTRL);
806 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
807 break;
a4f58f54 808
bc7f75fa
AK		 809 mdelay(1);
810 timeout--;
811 }
812
813 if (!timeout) {
3bb99fe2 814 e_dbg("Failed to acquire the semaphore.\n");
2e2e8d53
BA		 815 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
816 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 817 ret_val = -E1000_ERR_CONFIG;
818 goto out;
bc7f75fa
AK		 819 }
820
373a88d7
BA		 821out:
822 if (ret_val)
ca15df58 823 mutex_unlock(&swflag_mutex);
373a88d7
BA		 824
825 return ret_val;
bc7f75fa
AK		 826}
827
828/**
829 * e1000_release_swflag_ich8lan - Release software control flag
830 * @hw: pointer to the HW structure
831 *
ca15df58
BA		 832 * Releases the software control flag for performing PHY and select
833 * MAC CSR accesses.
bc7f75fa
AK		 834 **/
835static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
836{
837 u32 extcnf_ctrl;
838
839 extcnf_ctrl = er32(EXTCNF_CTRL);
840 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
841 ew32(EXTCNF_CTRL, extcnf_ctrl);
717d438d 842
ca15df58 843 mutex_unlock(&swflag_mutex);
bc7f75fa
AK		 844}
845
4662e82b
BA		 846/**
847 * e1000_check_mng_mode_ich8lan - Checks management mode
848 * @hw: pointer to the HW structure
849 *
eb7700dc 850 * This checks if the adapter has any manageability enabled.
4662e82b
BA		 851 * This is a function pointer entry point only called by read/write
852 * routines for the PHY and NVM parts.
853 **/
854static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
855{
a708dd88
BA		 856 u32 fwsm;
857
858 fwsm = er32(FWSM);
eb7700dc
BA		 859 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
860 ((fwsm & E1000_FWSM_MODE_MASK) ==
861 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
862}
4662e82b 863
eb7700dc
BA		 864/**
865 * e1000_check_mng_mode_pchlan - Checks management mode
866 * @hw: pointer to the HW structure
867 *
868 * This checks if the adapter has iAMT enabled.
869 * This is a function pointer entry point only called by read/write
870 * routines for the PHY and NVM parts.
871 **/
872static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
873{
874 u32 fwsm;
875
876 fwsm = er32(FWSM);
877 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
878 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
4662e82b
BA		 879}
880
bc7f75fa
AK		 881/**
882 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
883 * @hw: pointer to the HW structure
884 *
885 * Checks if firmware is blocking the reset of the PHY.
886 * This is a function pointer entry point only called by
887 * reset routines.
888 **/
889static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
890{
891 u32 fwsm;
892
893 fwsm = er32(FWSM);
894
895 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
896}
897
8395ae83
BA		 898/**
899 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
900 * @hw: pointer to the HW structure
901 *
902 * Assumes semaphore already acquired.
903 *
904 **/
905static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
906{
907 u16 phy_data;
908 u32 strap = er32(STRAP);
909 s32 ret_val = 0;
910
911 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
912
913 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
914 if (ret_val)
915 goto out;
916
917 phy_data &= ~HV_SMB_ADDR_MASK;
918 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
919 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
920 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
921
922out:
923 return ret_val;
924}
925
f523d211
BA		 926/**
927 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
928 * @hw: pointer to the HW structure
929 *
930 * SW should configure the LCD from the NVM extended configuration region
931 * as a workaround for certain parts.
932 **/
933static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
934{
935 struct e1000_phy_info *phy = &hw->phy;
936 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 937 s32 ret_val = 0;
f523d211
BA		 938 u16 word_addr, reg_data, reg_addr, phy_page = 0;
939
f523d211
BA		 940 /*
941 * Initialize the PHY from the NVM on ICH platforms. This
942 * is needed due to an issue where the NVM configuration is
943 * not properly autoloaded after power transitions.
944 * Therefore, after each PHY reset, we will load the
945 * configuration data out of the NVM manually.
946 */
3f0c16e8
BA		 947 switch (hw->mac.type) {
948 case e1000_ich8lan:
949 if (phy->type != e1000_phy_igp_3)
950 return ret_val;
951
5f3eed6f
BA		 952 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
953 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
3f0c16e8
BA		 954 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
955 break;
956 }
957 /* Fall-thru */
958 case e1000_pchlan:
d3738bb8 959 case e1000_pch2lan:
8b802a7e 960 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 961 break;
962 default:
963 return ret_val;
964 }
965
966 ret_val = hw->phy.ops.acquire(hw);
967 if (ret_val)
968 return ret_val;
8b802a7e
BA		 969
970 data = er32(FEXTNVM);
971 if (!(data & sw_cfg_mask))
972 goto out;
f523d211 973
8b802a7e
BA		 974 /*
975 * Make sure HW does not configure LCD from PHY
976 * extended configuration before SW configuration
977 */
978 data = er32(EXTCNF_CTRL);
d3738bb8
BA		 979 if (!(hw->mac.type == e1000_pch2lan)) {
980 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
981 goto out;
982 }
8b802a7e
BA		 983
984 cnf_size = er32(EXTCNF_SIZE);
985 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
986 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
987 if (!cnf_size)
988 goto out;
989
990 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
991 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
992
87fb7410
BA		 993 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
994 (hw->mac.type == e1000_pchlan)) ||
995 (hw->mac.type == e1000_pch2lan)) {
f523d211 996 /*
8b802a7e
BA		 997 * HW configures the SMBus address and LEDs when the
998 * OEM and LCD Write Enable bits are set in the NVM.
999 * When both NVM bits are cleared, SW will configure
1000 * them instead.
f523d211 1001 */
8395ae83 1002 ret_val = e1000_write_smbus_addr(hw);
8b802a7e 1003 if (ret_val)
f523d211
BA		 1004 goto out;
1005
8b802a7e
BA		 1006 data = er32(LEDCTL);
1007 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1008 (u16)data);
1009 if (ret_val)
f523d211 1010 goto out;
8b802a7e 1011 }
f523d211 1012
8b802a7e
BA		 1013 /* Configure LCD from extended configuration region. */
1014
1015 /* cnf_base_addr is in DWORD */
1016 word_addr = (u16)(cnf_base_addr << 1);
1017
1018 for (i = 0; i < cnf_size; i++) {
1019 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1020 &reg_data);
1021 if (ret_val)
1022 goto out;
1023
1024 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1025 1, &reg_addr);
1026 if (ret_val)
1027 goto out;
1028
1029 /* Save off the PHY page for future writes. */
1030 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1031 phy_page = reg_data;
1032 continue;
f523d211 1033 }
8b802a7e
BA		 1034
1035 reg_addr &= PHY_REG_MASK;
1036 reg_addr |= phy_page;
1037
1038 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1039 reg_data);
1040 if (ret_val)
1041 goto out;
f523d211
BA		 1042 }
1043
1044out:
94d8186a 1045 hw->phy.ops.release(hw);
f523d211
BA		 1046 return ret_val;
1047}
1048
1d5846b9
BA		 1049/**
1050 * e1000_k1_gig_workaround_hv - K1 Si workaround
1051 * @hw: pointer to the HW structure
1052 * @link: link up bool flag
1053 *
1054 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1055 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1056 * If link is down, the function will restore the default K1 setting located
1057 * in the NVM.
1058 **/
1059static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1060{
1061 s32 ret_val = 0;
1062 u16 status_reg = 0;
1063 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1064
1065 if (hw->mac.type != e1000_pchlan)
1066 goto out;
1067
1068 /* Wrap the whole flow with the sw flag */
94d8186a 1069 ret_val = hw->phy.ops.acquire(hw);
1d5846b9
BA		 1070 if (ret_val)
1071 goto out;
1072
1073 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1074 if (link) {
1075 if (hw->phy.type == e1000_phy_82578) {
94d8186a 1076 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1d5846b9
BA		 1077 &status_reg);
1078 if (ret_val)
1079 goto release;
1080
1081 status_reg &= BM_CS_STATUS_LINK_UP |
1082 BM_CS_STATUS_RESOLVED |
1083 BM_CS_STATUS_SPEED_MASK;
1084
1085 if (status_reg == (BM_CS_STATUS_LINK_UP |
1086 BM_CS_STATUS_RESOLVED |
1087 BM_CS_STATUS_SPEED_1000))
1088 k1_enable = false;
1089 }
1090
1091 if (hw->phy.type == e1000_phy_82577) {
94d8186a 1092 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1d5846b9
BA		 1093 &status_reg);
1094 if (ret_val)
1095 goto release;
1096
1097 status_reg &= HV_M_STATUS_LINK_UP |
1098 HV_M_STATUS_AUTONEG_COMPLETE |
1099 HV_M_STATUS_SPEED_MASK;
1100
1101 if (status_reg == (HV_M_STATUS_LINK_UP |
1102 HV_M_STATUS_AUTONEG_COMPLETE |
1103 HV_M_STATUS_SPEED_1000))
1104 k1_enable = false;
1105 }
1106
1107 /* Link stall fix for link up */
94d8186a 1108 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 1109 0x0100);
1110 if (ret_val)
1111 goto release;
1112
1113 } else {
1114 /* Link stall fix for link down */
94d8186a 1115 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 1116 0x4100);
1117 if (ret_val)
1118 goto release;
1119 }
1120
1121 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1122
1123release:
94d8186a 1124 hw->phy.ops.release(hw);
1d5846b9
BA		 1125out:
1126 return ret_val;
1127}
1128
1129/**
1130 * e1000_configure_k1_ich8lan - Configure K1 power state
1131 * @hw: pointer to the HW structure
1132 * @enable: K1 state to configure
1133 *
1134 * Configure the K1 power state based on the provided parameter.
1135 * Assumes semaphore already acquired.
1136 *
1137 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1138 **/
bb436b20 1139s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9
BA		 1140{
1141 s32 ret_val = 0;
1142 u32 ctrl_reg = 0;
1143 u32 ctrl_ext = 0;
1144 u32 reg = 0;
1145 u16 kmrn_reg = 0;
1146
1147 ret_val = e1000e_read_kmrn_reg_locked(hw,
1148 E1000_KMRNCTRLSTA_K1_CONFIG,
1149 &kmrn_reg);
1150 if (ret_val)
1151 goto out;
1152
1153 if (k1_enable)
1154 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1155 else
1156 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1157
1158 ret_val = e1000e_write_kmrn_reg_locked(hw,
1159 E1000_KMRNCTRLSTA_K1_CONFIG,
1160 kmrn_reg);
1161 if (ret_val)
1162 goto out;
1163
1164 udelay(20);
1165 ctrl_ext = er32(CTRL_EXT);
1166 ctrl_reg = er32(CTRL);
1167
1168 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1169 reg |= E1000_CTRL_FRCSPD;
1170 ew32(CTRL, reg);
1171
1172 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1173 udelay(20);
1174 ew32(CTRL, ctrl_reg);
1175 ew32(CTRL_EXT, ctrl_ext);
1176 udelay(20);
1177
1178out:
1179 return ret_val;
1180}
1181
f523d211
BA		 1182/**
1183 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1184 * @hw: pointer to the HW structure
1185 * @d0_state: boolean if entering d0 or d3 device state
1186 *
1187 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1188 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1189 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1190 **/
1191static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1192{
1193 s32 ret_val = 0;
1194 u32 mac_reg;
1195 u16 oem_reg;
1196
d3738bb8 1197 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
f523d211
BA		 1198 return ret_val;
1199
94d8186a 1200 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1201 if (ret_val)
1202 return ret_val;
1203
d3738bb8
BA		 1204 if (!(hw->mac.type == e1000_pch2lan)) {
1205 mac_reg = er32(EXTCNF_CTRL);
1206 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1207 goto out;
1208 }
f523d211
BA		 1209
1210 mac_reg = er32(FEXTNVM);
1211 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1212 goto out;
1213
1214 mac_reg = er32(PHY_CTRL);
1215
94d8186a 1216 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211
BA		 1217 if (ret_val)
1218 goto out;
1219
1220 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1221
1222 if (d0_state) {
1223 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1224 oem_reg |= HV_OEM_BITS_GBE_DIS;
1225
1226 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1227 oem_reg |= HV_OEM_BITS_LPLU;
1228 } else {
1229 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1230 oem_reg |= HV_OEM_BITS_GBE_DIS;
1231
1232 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1233 oem_reg |= HV_OEM_BITS_LPLU;
1234 }
1235 /* Restart auto-neg to activate the bits */
818f3331
BA		 1236 if (!e1000_check_reset_block(hw))
1237 oem_reg |= HV_OEM_BITS_RESTART_AN;
94d8186a 1238 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
f523d211
BA		 1239
1240out:
94d8186a 1241 hw->phy.ops.release(hw);
f523d211
BA		 1242
1243 return ret_val;
1244}
1245
1246
fddaa1af
BA		 1247/**
1248 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1249 * @hw: pointer to the HW structure
1250 **/
1251static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1252{
1253 s32 ret_val;
1254 u16 data;
1255
1256 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1257 if (ret_val)
1258 return ret_val;
1259
1260 data |= HV_KMRN_MDIO_SLOW;
1261
1262 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1263
1264 return ret_val;
1265}
1266
a4f58f54
BA		 1267/**
1268 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1269 * done after every PHY reset.
1270 **/
1271static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1272{
1273 s32 ret_val = 0;
baf86c9d 1274 u16 phy_data;
a4f58f54
BA		 1275
1276 if (hw->mac.type != e1000_pchlan)
1277 return ret_val;
1278
fddaa1af
BA		 1279 /* Set MDIO slow mode before any other MDIO access */
1280 if (hw->phy.type == e1000_phy_82577) {
1281 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1282 if (ret_val)
1283 goto out;
1284 }
1285
a4f58f54
BA		 1286 if (((hw->phy.type == e1000_phy_82577) &&
1287 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1288 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1289 /* Disable generation of early preamble */
1290 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1291 if (ret_val)
1292 return ret_val;
1293
1294 /* Preamble tuning for SSC */
1295 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1296 if (ret_val)
1297 return ret_val;
1298 }
1299
1300 if (hw->phy.type == e1000_phy_82578) {
1301 /*
1302 * Return registers to default by doing a soft reset then
1303 * writing 0x3140 to the control register.
1304 */
1305 if (hw->phy.revision < 2) {
1306 e1000e_phy_sw_reset(hw);
1307 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1308 }
1309 }
1310
1311 /* Select page 0 */
94d8186a 1312 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1313 if (ret_val)
1314 return ret_val;
1d5846b9 1315
a4f58f54 1316 hw->phy.addr = 1;
1d5846b9 1317 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 1318 hw->phy.ops.release(hw);
1d5846b9
BA		 1319 if (ret_val)
1320 goto out;
a4f58f54 1321
1d5846b9
BA		 1322 /*
1323 * Configure the K1 Si workaround during phy reset assuming there is
1324 * link so that it disables K1 if link is in 1Gbps.
1325 */
1326 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d
BA		 1327 if (ret_val)
1328 goto out;
1d5846b9 1329
baf86c9d
BA		 1330 /* Workaround for link disconnects on a busy hub in half duplex */
1331 ret_val = hw->phy.ops.acquire(hw);
1332 if (ret_val)
1333 goto out;
1334 ret_val = hw->phy.ops.read_reg_locked(hw,
1335 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1336 &phy_data);
1337 if (ret_val)
1338 goto release;
1339 ret_val = hw->phy.ops.write_reg_locked(hw,
1340 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1341 phy_data & 0x00FF);
1342release:
1343 hw->phy.ops.release(hw);
1d5846b9 1344out:
a4f58f54
BA		 1345 return ret_val;
1346}
1347
d3738bb8
BA		 1348/**
1349 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1350 * @hw: pointer to the HW structure
1351 **/
1352void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1353{
1354 u32 mac_reg;
1355 u16 i;
1356
1357 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1358 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1359 mac_reg = er32(RAL(i));
1360 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1361 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1362 mac_reg = er32(RAH(i));
1363 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1364 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1365 }
1366}
1367
1368static u32 e1000_calc_rx_da_crc(u8 mac[])
1369{
1370 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
1371 u32 i, j, mask, crc;
1372
1373 crc = 0xffffffff;
1374 for (i = 0; i < 6; i++) {
1375 crc = crc ^ mac[i];
1376 for (j = 8; j > 0; j--) {
1377 mask = (crc & 1) * (-1);
1378 crc = (crc >> 1) ^ (poly & mask);
1379 }
1380 }
1381 return ~crc;
1382}
1383
1384/**
1385 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1386 * with 82579 PHY
1387 * @hw: pointer to the HW structure
1388 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1389 **/
1390s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1391{
1392 s32 ret_val = 0;
1393 u16 phy_reg, data;
1394 u32 mac_reg;
1395 u16 i;
1396
1397 if (hw->mac.type != e1000_pch2lan)
1398 goto out;
1399
1400 /* disable Rx path while enabling/disabling workaround */
1401 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1402 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1403 if (ret_val)
1404 goto out;
1405
1406 if (enable) {
1407 /*
1408 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1409 * SHRAL/H) and initial CRC values to the MAC
1410 */
1411 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1412 u8 mac_addr[ETH_ALEN] = {0};
1413 u32 addr_high, addr_low;
1414
1415 addr_high = er32(RAH(i));
1416 if (!(addr_high & E1000_RAH_AV))
1417 continue;
1418 addr_low = er32(RAL(i));
1419 mac_addr[0] = (addr_low & 0xFF);
1420 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1421 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1422 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1423 mac_addr[4] = (addr_high & 0xFF);
1424 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1425
1426 ew32(PCH_RAICC(i),
1427 e1000_calc_rx_da_crc(mac_addr));
1428 }
1429
1430 /* Write Rx addresses to the PHY */
1431 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1432
1433 /* Enable jumbo frame workaround in the MAC */
1434 mac_reg = er32(FFLT_DBG);
1435 mac_reg &= ~(1 << 14);
1436 mac_reg |= (7 << 15);
1437 ew32(FFLT_DBG, mac_reg);
1438
1439 mac_reg = er32(RCTL);
1440 mac_reg |= E1000_RCTL_SECRC;
1441 ew32(RCTL, mac_reg);
1442
1443 ret_val = e1000e_read_kmrn_reg(hw,
1444 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1445 &data);
1446 if (ret_val)
1447 goto out;
1448 ret_val = e1000e_write_kmrn_reg(hw,
1449 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1450 data | (1 << 0));
1451 if (ret_val)
1452 goto out;
1453 ret_val = e1000e_read_kmrn_reg(hw,
1454 E1000_KMRNCTRLSTA_HD_CTRL,
1455 &data);
1456 if (ret_val)
1457 goto out;
1458 data &= ~(0xF << 8);
1459 data |= (0xB << 8);
1460 ret_val = e1000e_write_kmrn_reg(hw,
1461 E1000_KMRNCTRLSTA_HD_CTRL,
1462 data);
1463 if (ret_val)
1464 goto out;
1465
1466 /* Enable jumbo frame workaround in the PHY */
1467 e1e_rphy(hw, PHY_REG(769, 20), &data);
1468 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1469 if (ret_val)
1470 goto out;
1471 e1e_rphy(hw, PHY_REG(769, 23), &data);
1472 data &= ~(0x7F << 5);
1473 data |= (0x37 << 5);
1474 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1475 if (ret_val)
1476 goto out;
1477 e1e_rphy(hw, PHY_REG(769, 16), &data);
1478 data &= ~(1 << 13);
1479 data |= (1 << 12);
1480 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1481 if (ret_val)
1482 goto out;
1483 e1e_rphy(hw, PHY_REG(776, 20), &data);
1484 data &= ~(0x3FF << 2);
1485 data |= (0x1A << 2);
1486 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1487 if (ret_val)
1488 goto out;
1489 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1490 if (ret_val)
1491 goto out;
1492 e1e_rphy(hw, HV_PM_CTRL, &data);
1493 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1494 if (ret_val)
1495 goto out;
1496 } else {
1497 /* Write MAC register values back to h/w defaults */
1498 mac_reg = er32(FFLT_DBG);
1499 mac_reg &= ~(0xF << 14);
1500 ew32(FFLT_DBG, mac_reg);
1501
1502 mac_reg = er32(RCTL);
1503 mac_reg &= ~E1000_RCTL_SECRC;
1504 ew32(FFLT_DBG, mac_reg);
1505
1506 ret_val = e1000e_read_kmrn_reg(hw,
1507 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1508 &data);
1509 if (ret_val)
1510 goto out;
1511 ret_val = e1000e_write_kmrn_reg(hw,
1512 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1513 data & ~(1 << 0));
1514 if (ret_val)
1515 goto out;
1516 ret_val = e1000e_read_kmrn_reg(hw,
1517 E1000_KMRNCTRLSTA_HD_CTRL,
1518 &data);
1519 if (ret_val)
1520 goto out;
1521 data &= ~(0xF << 8);
1522 data |= (0xB << 8);
1523 ret_val = e1000e_write_kmrn_reg(hw,
1524 E1000_KMRNCTRLSTA_HD_CTRL,
1525 data);
1526 if (ret_val)
1527 goto out;
1528
1529 /* Write PHY register values back to h/w defaults */
1530 e1e_rphy(hw, PHY_REG(769, 20), &data);
1531 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1532 if (ret_val)
1533 goto out;
1534 e1e_rphy(hw, PHY_REG(769, 23), &data);
1535 data &= ~(0x7F << 5);
1536 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1537 if (ret_val)
1538 goto out;
1539 e1e_rphy(hw, PHY_REG(769, 16), &data);
1540 data &= ~(1 << 12);
1541 data |= (1 << 13);
1542 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1543 if (ret_val)
1544 goto out;
1545 e1e_rphy(hw, PHY_REG(776, 20), &data);
1546 data &= ~(0x3FF << 2);
1547 data |= (0x8 << 2);
1548 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1549 if (ret_val)
1550 goto out;
1551 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1552 if (ret_val)
1553 goto out;
1554 e1e_rphy(hw, HV_PM_CTRL, &data);
1555 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1556 if (ret_val)
1557 goto out;
1558 }
1559
1560 /* re-enable Rx path after enabling/disabling workaround */
1561 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1562
1563out:
1564 return ret_val;
1565}
1566
1567/**
1568 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1569 * done after every PHY reset.
1570 **/
1571static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1572{
1573 s32 ret_val = 0;
1574
1575 if (hw->mac.type != e1000_pch2lan)
1576 goto out;
1577
1578 /* Set MDIO slow mode before any other MDIO access */
1579 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1580
1581out:
1582 return ret_val;
1583}
1584
fc0c7760
BA		 1585/**
1586 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1587 * @hw: pointer to the HW structure
1588 *
1589 * Check the appropriate indication the MAC has finished configuring the
1590 * PHY after a software reset.
1591 **/
1592static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1593{
1594 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1595
1596 /* Wait for basic configuration completes before proceeding */
1597 do {
1598 data = er32(STATUS);
1599 data &= E1000_STATUS_LAN_INIT_DONE;
1600 udelay(100);
1601 } while ((!data) && --loop);
1602
1603 /*
1604 * If basic configuration is incomplete before the above loop
1605 * count reaches 0, loading the configuration from NVM will
1606 * leave the PHY in a bad state possibly resulting in no link.
1607 */
1608 if (loop == 0)
3bb99fe2 1609 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 1610
1611 /* Clear the Init Done bit for the next init event */
1612 data = er32(STATUS);
1613 data &= ~E1000_STATUS_LAN_INIT_DONE;
1614 ew32(STATUS, data);
1615}
1616
bc7f75fa 1617/**
e98cac44 1618 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 1619 * @hw: pointer to the HW structure
bc7f75fa 1620 **/
e98cac44 1621static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 1622{
f523d211
BA		 1623 s32 ret_val = 0;
1624 u16 reg;
bc7f75fa 1625
e98cac44
BA		 1626 if (e1000_check_reset_block(hw))
1627 goto out;
fc0c7760 1628
5f3eed6f
BA		 1629 /* Allow time for h/w to get to quiescent state after reset */
1630 msleep(10);
1631
fddaa1af 1632 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 1633 switch (hw->mac.type) {
1634 case e1000_pchlan:
a4f58f54
BA		 1635 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1636 if (ret_val)
e98cac44
BA		 1637 goto out;
1638 break;
d3738bb8
BA		 1639 case e1000_pch2lan:
1640 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1641 if (ret_val)
1642 goto out;
1643 break;
e98cac44
BA		 1644 default:
1645 break;
a4f58f54
BA		 1646 }
1647
db2932ec 1648 /* Dummy read to clear the phy wakeup bit after lcd reset */
d3738bb8 1649 if (hw->mac.type >= e1000_pchlan)
db2932ec
BA		 1650 e1e_rphy(hw, BM_WUC, &reg);
1651
f523d211
BA		 1652 /* Configure the LCD with the extended configuration region in NVM */
1653 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1654 if (ret_val)
1655 goto out;
bc7f75fa 1656
f523d211 1657 /* Configure the LCD with the OEM bits in NVM */
e98cac44 1658 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 1659
f523d211 1660out:
e98cac44
BA		 1661 return ret_val;
1662}
1663
1664/**
1665 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1666 * @hw: pointer to the HW structure
1667 *
1668 * Resets the PHY
1669 * This is a function pointer entry point called by drivers
1670 * or other shared routines.
1671 **/
1672static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1673{
1674 s32 ret_val = 0;
1675
1676 ret_val = e1000e_phy_hw_reset_generic(hw);
1677 if (ret_val)
1678 goto out;
1679
1680 ret_val = e1000_post_phy_reset_ich8lan(hw);
1681
1682out:
1683 return ret_val;
bc7f75fa
AK		 1684}
1685
fa2ce13c
BA		 1686/**
1687 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1688 * @hw: pointer to the HW structure
1689 * @active: true to enable LPLU, false to disable
1690 *
1691 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1692 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1693 * the phy speed. This function will manually set the LPLU bit and restart
1694 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1695 * since it configures the same bit.
1696 **/
1697static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1698{
1699 s32 ret_val = 0;
1700 u16 oem_reg;
1701
1702 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1703 if (ret_val)
1704 goto out;
1705
1706 if (active)
1707 oem_reg |= HV_OEM_BITS_LPLU;
1708 else
1709 oem_reg &= ~HV_OEM_BITS_LPLU;
1710
1711 oem_reg |= HV_OEM_BITS_RESTART_AN;
1712 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1713
1714out:
1715 return ret_val;
1716}
1717
bc7f75fa
AK		 1718/**
1719 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1720 * @hw: pointer to the HW structure
564ea9bb 1721 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1722 *
1723 * Sets the LPLU D0 state according to the active flag. When
1724 * activating LPLU this function also disables smart speed
1725 * and vice versa. LPLU will not be activated unless the
1726 * device autonegotiation advertisement meets standards of
1727 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1728 * This is a function pointer entry point only called by
1729 * PHY setup routines.
1730 **/
1731static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1732{
1733 struct e1000_phy_info *phy = &hw->phy;
1734 u32 phy_ctrl;
1735 s32 ret_val = 0;
1736 u16 data;
1737
97ac8cae 1738 if (phy->type == e1000_phy_ife)
bc7f75fa
AK		 1739 return ret_val;
1740
1741 phy_ctrl = er32(PHY_CTRL);
1742
1743 if (active) {
1744 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1745 ew32(PHY_CTRL, phy_ctrl);
1746
60f1292f
BA		 1747 if (phy->type != e1000_phy_igp_3)
1748 return 0;
1749
ad68076e
BA		 1750 /*
1751 * Call gig speed drop workaround on LPLU before accessing
1752 * any PHY registers
1753 */
60f1292f 1754 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1755 e1000e_gig_downshift_workaround_ich8lan(hw);
1756
1757 /* When LPLU is enabled, we should disable SmartSpeed */
1758 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1759 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1760 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1761 if (ret_val)
1762 return ret_val;
1763 } else {
1764 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1765 ew32(PHY_CTRL, phy_ctrl);
1766
60f1292f
BA		 1767 if (phy->type != e1000_phy_igp_3)
1768 return 0;
1769
ad68076e
BA		 1770 /*
1771 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1772 * during Dx states where the power conservation is most
1773 * important. During driver activity we should enable
ad68076e
BA		 1774 * SmartSpeed, so performance is maintained.
1775 */
bc7f75fa
AK		 1776 if (phy->smart_speed == e1000_smart_speed_on) {
1777 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1778 &data);
bc7f75fa
AK		 1779 if (ret_val)
1780 return ret_val;
1781
1782 data |= IGP01E1000_PSCFR_SMART_SPEED;
1783 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1784 data);
bc7f75fa
AK		 1785 if (ret_val)
1786 return ret_val;
1787 } else if (phy->smart_speed == e1000_smart_speed_off) {
1788 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1789 &data);
bc7f75fa
AK		 1790 if (ret_val)
1791 return ret_val;
1792
1793 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1794 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1795 data);
bc7f75fa
AK		 1796 if (ret_val)
1797 return ret_val;
1798 }
1799 }
1800
1801 return 0;
1802}
1803
1804/**
1805 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1806 * @hw: pointer to the HW structure
564ea9bb 1807 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1808 *
1809 * Sets the LPLU D3 state according to the active flag. When
1810 * activating LPLU this function also disables smart speed
1811 * and vice versa. LPLU will not be activated unless the
1812 * device autonegotiation advertisement meets standards of
1813 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1814 * This is a function pointer entry point only called by
1815 * PHY setup routines.
1816 **/
1817static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1818{
1819 struct e1000_phy_info *phy = &hw->phy;
1820 u32 phy_ctrl;
1821 s32 ret_val;
1822 u16 data;
1823
1824 phy_ctrl = er32(PHY_CTRL);
1825
1826 if (!active) {
1827 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1828 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 1829
1830 if (phy->type != e1000_phy_igp_3)
1831 return 0;
1832
ad68076e
BA		 1833 /*
1834 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1835 * during Dx states where the power conservation is most
1836 * important. During driver activity we should enable
ad68076e
BA		 1837 * SmartSpeed, so performance is maintained.
1838 */
bc7f75fa 1839 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 1840 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1841 &data);
bc7f75fa
AK		 1842 if (ret_val)
1843 return ret_val;
1844
1845 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1846 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1847 data);
bc7f75fa
AK		 1848 if (ret_val)
1849 return ret_val;
1850 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 1851 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1852 &data);
bc7f75fa
AK		 1853 if (ret_val)
1854 return ret_val;
1855
1856 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1857 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1858 data);
bc7f75fa
AK		 1859 if (ret_val)
1860 return ret_val;
1861 }
1862 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1863 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1864 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1865 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1866 ew32(PHY_CTRL, phy_ctrl);
1867
60f1292f
BA		 1868 if (phy->type != e1000_phy_igp_3)
1869 return 0;
1870
ad68076e
BA		 1871 /*
1872 * Call gig speed drop workaround on LPLU before accessing
1873 * any PHY registers
1874 */
60f1292f 1875 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1876 e1000e_gig_downshift_workaround_ich8lan(hw);
1877
1878 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 1879 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 1880 if (ret_val)
1881 return ret_val;
1882
1883 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 1884 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 1885 }
1886
1887 return 0;
1888}
1889
f4187b56
BA		 1890/**
1891 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1892 * @hw: pointer to the HW structure
1893 * @bank: pointer to the variable that returns the active bank
1894 *
1895 * Reads signature byte from the NVM using the flash access registers.
e243455d 1896 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 1897 **/
1898static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1899{
e243455d 1900 u32 eecd;
f4187b56 1901 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 1902 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1903 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d
BA		 1904 u8 sig_byte = 0;
1905 s32 ret_val = 0;
f4187b56 1906
e243455d
BA		 1907 switch (hw->mac.type) {
1908 case e1000_ich8lan:
1909 case e1000_ich9lan:
1910 eecd = er32(EECD);
1911 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1912 E1000_EECD_SEC1VAL_VALID_MASK) {
1913 if (eecd & E1000_EECD_SEC1VAL)
1914 *bank = 1;
1915 else
1916 *bank = 0;
1917
1918 return 0;
1919 }
3bb99fe2 1920 e_dbg("Unable to determine valid NVM bank via EEC - "
e243455d
BA		 1921 "reading flash signature\n");
1922 /* fall-thru */
1923 default:
1924 /* set bank to 0 in case flash read fails */
1925 *bank = 0;
1926
1927 /* Check bank 0 */
1928 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1929 &sig_byte);
1930 if (ret_val)
1931 return ret_val;
1932 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1933 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 1934 *bank = 0;
e243455d
BA		 1935 return 0;
1936 }
f4187b56 1937
e243455d
BA		 1938 /* Check bank 1 */
1939 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1940 bank1_offset,
1941 &sig_byte);
1942 if (ret_val)
1943 return ret_val;
1944 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1945 E1000_ICH_NVM_SIG_VALUE) {
1946 *bank = 1;
1947 return 0;
f4187b56 1948 }
e243455d 1949
3bb99fe2 1950 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 1951 return -E1000_ERR_NVM;
f4187b56
BA		 1952 }
1953
1954 return 0;
1955}
1956
bc7f75fa
AK		 1957/**
1958 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
1959 * @hw: pointer to the HW structure
1960 * @offset: The offset (in bytes) of the word(s) to read.
1961 * @words: Size of data to read in words
1962 * @data: Pointer to the word(s) to read at offset.
1963 *
1964 * Reads a word(s) from the NVM using the flash access registers.
1965 **/
1966static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1967 u16 *data)
1968{
1969 struct e1000_nvm_info *nvm = &hw->nvm;
1970 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1971 u32 act_offset;
148675a7 1972 s32 ret_val = 0;
f4187b56 1973 u32 bank = 0;
bc7f75fa
AK		 1974 u16 i, word;
1975
1976 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1977 (words == 0)) {
3bb99fe2 1978 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 1979 ret_val = -E1000_ERR_NVM;
1980 goto out;
bc7f75fa
AK		 1981 }
1982
94d8186a 1983 nvm->ops.acquire(hw);
bc7f75fa 1984
f4187b56 1985 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 1986 if (ret_val) {
3bb99fe2 1987 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 1988 bank = 0;
1989 }
f4187b56
BA		 1990
1991 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 1992 act_offset += offset;
1993
148675a7 1994 ret_val = 0;
bc7f75fa
AK		 1995 for (i = 0; i < words; i++) {
1996 if ((dev_spec->shadow_ram) &&
1997 (dev_spec->shadow_ram[offset+i].modified)) {
1998 data[i] = dev_spec->shadow_ram[offset+i].value;
1999 } else {
2000 ret_val = e1000_read_flash_word_ich8lan(hw,
2001 act_offset + i,
2002 &word);
2003 if (ret_val)
2004 break;
2005 data[i] = word;
2006 }
2007 }
2008
94d8186a 2009 nvm->ops.release(hw);
bc7f75fa 2010
e243455d
BA		 2011out:
2012 if (ret_val)
3bb99fe2 2013 e_dbg("NVM read error: %d\n", ret_val);
e243455d 2014
bc7f75fa
AK		 2015 return ret_val;
2016}
2017
2018/**
2019 * e1000_flash_cycle_init_ich8lan - Initialize flash
2020 * @hw: pointer to the HW structure
2021 *
2022 * This function does initial flash setup so that a new read/write/erase cycle
2023 * can be started.
2024 **/
2025static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2026{
2027 union ich8_hws_flash_status hsfsts;
2028 s32 ret_val = -E1000_ERR_NVM;
2029 s32 i = 0;
2030
2031 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2032
2033 /* Check if the flash descriptor is valid */
2034 if (hsfsts.hsf_status.fldesvalid == 0) {
3bb99fe2 2035 e_dbg("Flash descriptor invalid. "
2c73e1fe 2036 "SW Sequencing must be used.\n");
bc7f75fa
AK		 2037 return -E1000_ERR_NVM;
2038 }
2039
2040 /* Clear FCERR and DAEL in hw status by writing 1 */
2041 hsfsts.hsf_status.flcerr = 1;
2042 hsfsts.hsf_status.dael = 1;
2043
2044 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2045
ad68076e
BA		 2046 /*
2047 * Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 2048 * bit to check against, in order to start a new cycle or
2049 * FDONE bit should be changed in the hardware so that it
489815ce 2050 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 2051 * indication whether a cycle is in progress or has been
2052 * completed.
2053 */
2054
2055 if (hsfsts.hsf_status.flcinprog == 0) {
ad68076e
BA		 2056 /*
2057 * There is no cycle running at present,
5ff5b664 2058 * so we can start a cycle.
ad68076e
BA		 2059 * Begin by setting Flash Cycle Done.
2060 */
bc7f75fa
AK		 2061 hsfsts.hsf_status.flcdone = 1;
2062 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2063 ret_val = 0;
2064 } else {
ad68076e 2065 /*
5ff5b664 2066 * Otherwise poll for sometime so the current
ad68076e
BA		 2067 * cycle has a chance to end before giving up.
2068 */
bc7f75fa
AK		 2069 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2070 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2071 if (hsfsts.hsf_status.flcinprog == 0) {
2072 ret_val = 0;
2073 break;
2074 }
2075 udelay(1);
2076 }
2077 if (ret_val == 0) {
ad68076e
BA		 2078 /*
2079 * Successful in waiting for previous cycle to timeout,
2080 * now set the Flash Cycle Done.
2081 */
bc7f75fa
AK		 2082 hsfsts.hsf_status.flcdone = 1;
2083 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2084 } else {
2c73e1fe 2085 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 2086 }
2087 }
2088
2089 return ret_val;
2090}
2091
2092/**
2093 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2094 * @hw: pointer to the HW structure
2095 * @timeout: maximum time to wait for completion
2096 *
2097 * This function starts a flash cycle and waits for its completion.
2098 **/
2099static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2100{
2101 union ich8_hws_flash_ctrl hsflctl;
2102 union ich8_hws_flash_status hsfsts;
2103 s32 ret_val = -E1000_ERR_NVM;
2104 u32 i = 0;
2105
2106 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2107 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2108 hsflctl.hsf_ctrl.flcgo = 1;
2109 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2110
2111 /* wait till FDONE bit is set to 1 */
2112 do {
2113 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2114 if (hsfsts.hsf_status.flcdone == 1)
2115 break;
2116 udelay(1);
2117 } while (i++ < timeout);
2118
2119 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2120 return 0;
2121
2122 return ret_val;
2123}
2124
2125/**
2126 * e1000_read_flash_word_ich8lan - Read word from flash
2127 * @hw: pointer to the HW structure
2128 * @offset: offset to data location
2129 * @data: pointer to the location for storing the data
2130 *
2131 * Reads the flash word at offset into data. Offset is converted
2132 * to bytes before read.
2133 **/
2134static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2135 u16 *data)
2136{
2137 /* Must convert offset into bytes. */
2138 offset <<= 1;
2139
2140 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2141}
2142
f4187b56
BA		 2143/**
2144 * e1000_read_flash_byte_ich8lan - Read byte from flash
2145 * @hw: pointer to the HW structure
2146 * @offset: The offset of the byte to read.
2147 * @data: Pointer to a byte to store the value read.
2148 *
2149 * Reads a single byte from the NVM using the flash access registers.
2150 **/
2151static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2152 u8 *data)
2153{
2154 s32 ret_val;
2155 u16 word = 0;
2156
2157 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2158 if (ret_val)
2159 return ret_val;
2160
2161 *data = (u8)word;
2162
2163 return 0;
2164}
2165
bc7f75fa
AK		 2166/**
2167 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2168 * @hw: pointer to the HW structure
2169 * @offset: The offset (in bytes) of the byte or word to read.
2170 * @size: Size of data to read, 1=byte 2=word
2171 * @data: Pointer to the word to store the value read.
2172 *
2173 * Reads a byte or word from the NVM using the flash access registers.
2174 **/
2175static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2176 u8 size, u16 *data)
2177{
2178 union ich8_hws_flash_status hsfsts;
2179 union ich8_hws_flash_ctrl hsflctl;
2180 u32 flash_linear_addr;
2181 u32 flash_data = 0;
2182 s32 ret_val = -E1000_ERR_NVM;
2183 u8 count = 0;
2184
2185 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2186 return -E1000_ERR_NVM;
2187
2188 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2189 hw->nvm.flash_base_addr;
2190
2191 do {
2192 udelay(1);
2193 /* Steps */
2194 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2195 if (ret_val != 0)
2196 break;
2197
2198 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2199 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2200 hsflctl.hsf_ctrl.fldbcount = size - 1;
2201 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2202 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2203
2204 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2205
2206 ret_val = e1000_flash_cycle_ich8lan(hw,
2207 ICH_FLASH_READ_COMMAND_TIMEOUT);
2208
ad68076e
BA		 2209 /*
2210 * Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 2211 * and try the whole sequence a few more times, else
2212 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 2213 * least significant byte first msb to lsb
2214 */
bc7f75fa
AK		 2215 if (ret_val == 0) {
2216 flash_data = er32flash(ICH_FLASH_FDATA0);
2217 if (size == 1) {
2218 *data = (u8)(flash_data & 0x000000FF);
2219 } else if (size == 2) {
2220 *data = (u16)(flash_data & 0x0000FFFF);
2221 }
2222 break;
2223 } else {
ad68076e
BA		 2224 /*
2225 * If we've gotten here, then things are probably
bc7f75fa
AK		 2226 * completely hosed, but if the error condition is
2227 * detected, it won't hurt to give it another try...
2228 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2229 */
2230 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2231 if (hsfsts.hsf_status.flcerr == 1) {
2232 /* Repeat for some time before giving up. */
2233 continue;
2234 } else if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2235 e_dbg("Timeout error - flash cycle "
2c73e1fe 2236 "did not complete.\n");
bc7f75fa
AK		 2237 break;
2238 }
2239 }
2240 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2241
2242 return ret_val;
2243}
2244
2245/**
2246 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2247 * @hw: pointer to the HW structure
2248 * @offset: The offset (in bytes) of the word(s) to write.
2249 * @words: Size of data to write in words
2250 * @data: Pointer to the word(s) to write at offset.
2251 *
2252 * Writes a byte or word to the NVM using the flash access registers.
2253 **/
2254static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2255 u16 *data)
2256{
2257 struct e1000_nvm_info *nvm = &hw->nvm;
2258 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 2259 u16 i;
2260
2261 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2262 (words == 0)) {
3bb99fe2 2263 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 2264 return -E1000_ERR_NVM;
2265 }
2266
94d8186a 2267 nvm->ops.acquire(hw);
ca15df58 2268
bc7f75fa 2269 for (i = 0; i < words; i++) {
564ea9bb 2270 dev_spec->shadow_ram[offset+i].modified = true;
bc7f75fa
AK		 2271 dev_spec->shadow_ram[offset+i].value = data[i];
2272 }
2273
94d8186a 2274 nvm->ops.release(hw);
ca15df58 2275
bc7f75fa
AK		 2276 return 0;
2277}
2278
2279/**
2280 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2281 * @hw: pointer to the HW structure
2282 *
2283 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2284 * which writes the checksum to the shadow ram. The changes in the shadow
2285 * ram are then committed to the EEPROM by processing each bank at a time
2286 * checking for the modified bit and writing only the pending changes.
489815ce 2287 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 2288 * future writes.
2289 **/
2290static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2291{
2292 struct e1000_nvm_info *nvm = &hw->nvm;
2293 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 2294 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 2295 s32 ret_val;
2296 u16 data;
2297
2298 ret_val = e1000e_update_nvm_checksum_generic(hw);
2299 if (ret_val)
e243455d 2300 goto out;
bc7f75fa
AK		 2301
2302 if (nvm->type != e1000_nvm_flash_sw)
e243455d 2303 goto out;
bc7f75fa 2304
94d8186a 2305 nvm->ops.acquire(hw);
bc7f75fa 2306
ad68076e
BA		 2307 /*
2308 * We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 2309 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 2310 * is going to be written
2311 */
f4187b56 2312 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 2313 if (ret_val) {
3bb99fe2 2314 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 2315 bank = 0;
e243455d 2316 }
f4187b56
BA		 2317
2318 if (bank == 0) {
bc7f75fa
AK		 2319 new_bank_offset = nvm->flash_bank_size;
2320 old_bank_offset = 0;
e243455d 2321 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 2322 if (ret_val)
2323 goto release;
bc7f75fa
AK		 2324 } else {
2325 old_bank_offset = nvm->flash_bank_size;
2326 new_bank_offset = 0;
e243455d 2327 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 2328 if (ret_val)
2329 goto release;
bc7f75fa
AK		 2330 }
2331
2332 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
ad68076e
BA		 2333 /*
2334 * Determine whether to write the value stored
bc7f75fa 2335 * in the other NVM bank or a modified value stored
ad68076e
BA		 2336 * in the shadow RAM
2337 */
bc7f75fa
AK		 2338 if (dev_spec->shadow_ram[i].modified) {
2339 data = dev_spec->shadow_ram[i].value;
2340 } else {
e243455d
BA		 2341 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2342 old_bank_offset,
2343 &data);
2344 if (ret_val)
2345 break;
bc7f75fa
AK		 2346 }
2347
ad68076e
BA		 2348 /*
2349 * If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 2350 * (15:14) are 11b until the commit has completed.
2351 * This will allow us to write 10b which indicates the
2352 * signature is valid. We want to do this after the write
2353 * has completed so that we don't mark the segment valid
ad68076e
BA		 2354 * while the write is still in progress
2355 */
bc7f75fa
AK		 2356 if (i == E1000_ICH_NVM_SIG_WORD)
2357 data |= E1000_ICH_NVM_SIG_MASK;
2358
2359 /* Convert offset to bytes. */
2360 act_offset = (i + new_bank_offset) << 1;
2361
2362 udelay(100);
2363 /* Write the bytes to the new bank. */
2364 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2365 act_offset,
2366 (u8)data);
2367 if (ret_val)
2368 break;
2369
2370 udelay(100);
2371 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2372 act_offset + 1,
2373 (u8)(data >> 8));
2374 if (ret_val)
2375 break;
2376 }
2377
ad68076e
BA		 2378 /*
2379 * Don't bother writing the segment valid bits if sector
2380 * programming failed.
2381 */
bc7f75fa 2382 if (ret_val) {
4a770358 2383 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 2384 e_dbg("Flash commit failed.\n");
9c5e209d 2385 goto release;
bc7f75fa
AK		 2386 }
2387
ad68076e
BA		 2388 /*
2389 * Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 2390 * to 10b in word 0x13 , this can be done without an
2391 * erase as well since these bits are 11 to start with
ad68076e
BA		 2392 * and we need to change bit 14 to 0b
2393 */
bc7f75fa 2394 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 2395 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 2396 if (ret_val)
2397 goto release;
2398
bc7f75fa
AK		 2399 data &= 0xBFFF;
2400 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2401 act_offset * 2 + 1,
2402 (u8)(data >> 8));
9c5e209d
BA		 2403 if (ret_val)
2404 goto release;
bc7f75fa 2405
ad68076e
BA		 2406 /*
2407 * And invalidate the previously valid segment by setting
bc7f75fa
AK		 2408 * its signature word (0x13) high_byte to 0b. This can be
2409 * done without an erase because flash erase sets all bits
ad68076e
BA		 2410 * to 1's. We can write 1's to 0's without an erase
2411 */
bc7f75fa
AK		 2412 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2413 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 2414 if (ret_val)
2415 goto release;
bc7f75fa
AK		 2416
2417 /* Great! Everything worked, we can now clear the cached entries. */
2418 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 2419 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 2420 dev_spec->shadow_ram[i].value = 0xFFFF;
2421 }
2422
9c5e209d 2423release:
94d8186a 2424 nvm->ops.release(hw);
bc7f75fa 2425
ad68076e
BA		 2426 /*
2427 * Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 2428 * until after the next adapter reset.
2429 */
9c5e209d
BA		 2430 if (!ret_val) {
2431 e1000e_reload_nvm(hw);
2432 msleep(10);
2433 }
bc7f75fa 2434
e243455d
BA		 2435out:
2436 if (ret_val)
3bb99fe2 2437 e_dbg("NVM update error: %d\n", ret_val);
e243455d 2438
bc7f75fa
AK		 2439 return ret_val;
2440}
2441
2442/**
2443 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2444 * @hw: pointer to the HW structure
2445 *
2446 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2447 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2448 * calculated, in which case we need to calculate the checksum and set bit 6.
2449 **/
2450static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2451{
2452 s32 ret_val;
2453 u16 data;
2454
ad68076e
BA		 2455 /*
2456 * Read 0x19 and check bit 6. If this bit is 0, the checksum
bc7f75fa
AK		 2457 * needs to be fixed. This bit is an indication that the NVM
2458 * was prepared by OEM software and did not calculate the
2459 * checksum...a likely scenario.
2460 */
2461 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2462 if (ret_val)
2463 return ret_val;
2464
2465 if ((data & 0x40) == 0) {
2466 data |= 0x40;
2467 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2468 if (ret_val)
2469 return ret_val;
2470 ret_val = e1000e_update_nvm_checksum(hw);
2471 if (ret_val)
2472 return ret_val;
2473 }
2474
2475 return e1000e_validate_nvm_checksum_generic(hw);
2476}
2477
4a770358
BA		 2478/**
2479 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2480 * @hw: pointer to the HW structure
2481 *
2482 * To prevent malicious write/erase of the NVM, set it to be read-only
2483 * so that the hardware ignores all write/erase cycles of the NVM via
2484 * the flash control registers. The shadow-ram copy of the NVM will
2485 * still be updated, however any updates to this copy will not stick
2486 * across driver reloads.
2487 **/
2488void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2489{
ca15df58 2490 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 2491 union ich8_flash_protected_range pr0;
2492 union ich8_hws_flash_status hsfsts;
2493 u32 gfpreg;
4a770358 2494
94d8186a 2495 nvm->ops.acquire(hw);
4a770358
BA		 2496
2497 gfpreg = er32flash(ICH_FLASH_GFPREG);
2498
2499 /* Write-protect GbE Sector of NVM */
2500 pr0.regval = er32flash(ICH_FLASH_PR0);
2501 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2502 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2503 pr0.range.wpe = true;
2504 ew32flash(ICH_FLASH_PR0, pr0.regval);
2505
2506 /*
2507 * Lock down a subset of GbE Flash Control Registers, e.g.
2508 * PR0 to prevent the write-protection from being lifted.
2509 * Once FLOCKDN is set, the registers protected by it cannot
2510 * be written until FLOCKDN is cleared by a hardware reset.
2511 */
2512 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2513 hsfsts.hsf_status.flockdn = true;
2514 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2515
94d8186a 2516 nvm->ops.release(hw);
4a770358
BA		 2517}
2518
bc7f75fa
AK		 2519/**
2520 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2521 * @hw: pointer to the HW structure
2522 * @offset: The offset (in bytes) of the byte/word to read.
2523 * @size: Size of data to read, 1=byte 2=word
2524 * @data: The byte(s) to write to the NVM.
2525 *
2526 * Writes one/two bytes to the NVM using the flash access registers.
2527 **/
2528static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2529 u8 size, u16 data)
2530{
2531 union ich8_hws_flash_status hsfsts;
2532 union ich8_hws_flash_ctrl hsflctl;
2533 u32 flash_linear_addr;
2534 u32 flash_data = 0;
2535 s32 ret_val;
2536 u8 count = 0;
2537
2538 if (size < 1 || size > 2 || data > size * 0xff ||
2539 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2540 return -E1000_ERR_NVM;
2541
2542 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2543 hw->nvm.flash_base_addr;
2544
2545 do {
2546 udelay(1);
2547 /* Steps */
2548 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2549 if (ret_val)
2550 break;
2551
2552 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2553 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2554 hsflctl.hsf_ctrl.fldbcount = size -1;
2555 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2556 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2557
2558 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2559
2560 if (size == 1)
2561 flash_data = (u32)data & 0x00FF;
2562 else
2563 flash_data = (u32)data;
2564
2565 ew32flash(ICH_FLASH_FDATA0, flash_data);
2566
ad68076e
BA		 2567 /*
2568 * check if FCERR is set to 1 , if set to 1, clear it
2569 * and try the whole sequence a few more times else done
2570 */
bc7f75fa
AK		 2571 ret_val = e1000_flash_cycle_ich8lan(hw,
2572 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2573 if (!ret_val)
2574 break;
2575
ad68076e
BA		 2576 /*
2577 * If we're here, then things are most likely
bc7f75fa
AK		 2578 * completely hosed, but if the error condition
2579 * is detected, it won't hurt to give it another
2580 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2581 */
2582 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2583 if (hsfsts.hsf_status.flcerr == 1)
2584 /* Repeat for some time before giving up. */
2585 continue;
2586 if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2587 e_dbg("Timeout error - flash cycle "
bc7f75fa
AK		 2588 "did not complete.");
2589 break;
2590 }
2591 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2592
2593 return ret_val;
2594}
2595
2596/**
2597 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2598 * @hw: pointer to the HW structure
2599 * @offset: The index of the byte to read.
2600 * @data: The byte to write to the NVM.
2601 *
2602 * Writes a single byte to the NVM using the flash access registers.
2603 **/
2604static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2605 u8 data)
2606{
2607 u16 word = (u16)data;
2608
2609 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2610}
2611
2612/**
2613 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2614 * @hw: pointer to the HW structure
2615 * @offset: The offset of the byte to write.
2616 * @byte: The byte to write to the NVM.
2617 *
2618 * Writes a single byte to the NVM using the flash access registers.
2619 * Goes through a retry algorithm before giving up.
2620 **/
2621static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2622 u32 offset, u8 byte)
2623{
2624 s32 ret_val;
2625 u16 program_retries;
2626
2627 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2628 if (!ret_val)
2629 return ret_val;
2630
2631 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 2632 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
bc7f75fa
AK		 2633 udelay(100);
2634 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2635 if (!ret_val)
2636 break;
2637 }
2638 if (program_retries == 100)
2639 return -E1000_ERR_NVM;
2640
2641 return 0;
2642}
2643
2644/**
2645 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2646 * @hw: pointer to the HW structure
2647 * @bank: 0 for first bank, 1 for second bank, etc.
2648 *
2649 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2650 * bank N is 4096 * N + flash_reg_addr.
2651 **/
2652static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2653{
2654 struct e1000_nvm_info *nvm = &hw->nvm;
2655 union ich8_hws_flash_status hsfsts;
2656 union ich8_hws_flash_ctrl hsflctl;
2657 u32 flash_linear_addr;
2658 /* bank size is in 16bit words - adjust to bytes */
2659 u32 flash_bank_size = nvm->flash_bank_size * 2;
2660 s32 ret_val;
2661 s32 count = 0;
a708dd88 2662 s32 j, iteration, sector_size;
bc7f75fa
AK		 2663
2664 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2665
ad68076e
BA		 2666 /*
2667 * Determine HW Sector size: Read BERASE bits of hw flash status
2668 * register
2669 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 2670 * consecutive sectors. The start index for the nth Hw sector
2671 * can be calculated as = bank * 4096 + n * 256
2672 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2673 * The start index for the nth Hw sector can be calculated
2674 * as = bank * 4096
2675 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2676 * (ich9 only, otherwise error condition)
2677 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2678 */
2679 switch (hsfsts.hsf_status.berasesz) {
2680 case 0:
2681 /* Hw sector size 256 */
2682 sector_size = ICH_FLASH_SEG_SIZE_256;
2683 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2684 break;
2685 case 1:
2686 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 2687 iteration = 1;
bc7f75fa
AK		 2688 break;
2689 case 2:
148675a7
BA		 2690 sector_size = ICH_FLASH_SEG_SIZE_8K;
2691 iteration = 1;
bc7f75fa
AK		 2692 break;
2693 case 3:
2694 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 2695 iteration = 1;
bc7f75fa
AK		 2696 break;
2697 default:
2698 return -E1000_ERR_NVM;
2699 }
2700
2701 /* Start with the base address, then add the sector offset. */
2702 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 2703 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa
AK		 2704
2705 for (j = 0; j < iteration ; j++) {
2706 do {
2707 /* Steps */
2708 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2709 if (ret_val)
2710 return ret_val;
2711
ad68076e
BA		 2712 /*
2713 * Write a value 11 (block Erase) in Flash
2714 * Cycle field in hw flash control
2715 */
bc7f75fa
AK		 2716 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2717 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2718 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2719
ad68076e
BA		 2720 /*
2721 * Write the last 24 bits of an index within the
bc7f75fa
AK		 2722 * block into Flash Linear address field in Flash
2723 * Address.
2724 */
2725 flash_linear_addr += (j * sector_size);
2726 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2727
2728 ret_val = e1000_flash_cycle_ich8lan(hw,
2729 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2730 if (ret_val == 0)
2731 break;
2732
ad68076e
BA		 2733 /*
2734 * Check if FCERR is set to 1. If 1,
bc7f75fa 2735 * clear it and try the whole sequence
ad68076e
BA		 2736 * a few more times else Done
2737 */
bc7f75fa
AK		 2738 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2739 if (hsfsts.hsf_status.flcerr == 1)
ad68076e 2740 /* repeat for some time before giving up */
bc7f75fa
AK		 2741 continue;
2742 else if (hsfsts.hsf_status.flcdone == 0)
2743 return ret_val;
2744 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2745 }
2746
2747 return 0;
2748}
2749
2750/**
2751 * e1000_valid_led_default_ich8lan - Set the default LED settings
2752 * @hw: pointer to the HW structure
2753 * @data: Pointer to the LED settings
2754 *
2755 * Reads the LED default settings from the NVM to data. If the NVM LED
2756 * settings is all 0's or F's, set the LED default to a valid LED default
2757 * setting.
2758 **/
2759static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2760{
2761 s32 ret_val;
2762
2763 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2764 if (ret_val) {
3bb99fe2 2765 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 2766 return ret_val;
2767 }
2768
2769 if (*data == ID_LED_RESERVED_0000 ||
2770 *data == ID_LED_RESERVED_FFFF)
2771 *data = ID_LED_DEFAULT_ICH8LAN;
2772
2773 return 0;
2774}
2775
a4f58f54
BA		 2776/**
2777 * e1000_id_led_init_pchlan - store LED configurations
2778 * @hw: pointer to the HW structure
2779 *
2780 * PCH does not control LEDs via the LEDCTL register, rather it uses
2781 * the PHY LED configuration register.
2782 *
2783 * PCH also does not have an "always on" or "always off" mode which
2784 * complicates the ID feature. Instead of using the "on" mode to indicate
2785 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2786 * use "link_up" mode. The LEDs will still ID on request if there is no
2787 * link based on logic in e1000_led_[on|off]_pchlan().
2788 **/
2789static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2790{
2791 struct e1000_mac_info *mac = &hw->mac;
2792 s32 ret_val;
2793 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2794 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2795 u16 data, i, temp, shift;
2796
2797 /* Get default ID LED modes */
2798 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2799 if (ret_val)
2800 goto out;
2801
2802 mac->ledctl_default = er32(LEDCTL);
2803 mac->ledctl_mode1 = mac->ledctl_default;
2804 mac->ledctl_mode2 = mac->ledctl_default;
2805
2806 for (i = 0; i < 4; i++) {
2807 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2808 shift = (i * 5);
2809 switch (temp) {
2810 case ID_LED_ON1_DEF2:
2811 case ID_LED_ON1_ON2:
2812 case ID_LED_ON1_OFF2:
2813 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2814 mac->ledctl_mode1 |= (ledctl_on << shift);
2815 break;
2816 case ID_LED_OFF1_DEF2:
2817 case ID_LED_OFF1_ON2:
2818 case ID_LED_OFF1_OFF2:
2819 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2820 mac->ledctl_mode1 |= (ledctl_off << shift);
2821 break;
2822 default:
2823 /* Do nothing */
2824 break;
2825 }
2826 switch (temp) {
2827 case ID_LED_DEF1_ON2:
2828 case ID_LED_ON1_ON2:
2829 case ID_LED_OFF1_ON2:
2830 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2831 mac->ledctl_mode2 |= (ledctl_on << shift);
2832 break;
2833 case ID_LED_DEF1_OFF2:
2834 case ID_LED_ON1_OFF2:
2835 case ID_LED_OFF1_OFF2:
2836 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2837 mac->ledctl_mode2 |= (ledctl_off << shift);
2838 break;
2839 default:
2840 /* Do nothing */
2841 break;
2842 }
2843 }
2844
2845out:
2846 return ret_val;
2847}
2848
bc7f75fa
AK		 2849/**
2850 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2851 * @hw: pointer to the HW structure
2852 *
2853 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2854 * register, so the the bus width is hard coded.
2855 **/
2856static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2857{
2858 struct e1000_bus_info *bus = &hw->bus;
2859 s32 ret_val;
2860
2861 ret_val = e1000e_get_bus_info_pcie(hw);
2862
ad68076e
BA		 2863 /*
2864 * ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 2865 * a configuration space, but do not contain
2866 * PCI Express Capability registers, so bus width
2867 * must be hardcoded.
2868 */
2869 if (bus->width == e1000_bus_width_unknown)
2870 bus->width = e1000_bus_width_pcie_x1;
2871
2872 return ret_val;
2873}
2874
2875/**
2876 * e1000_reset_hw_ich8lan - Reset the hardware
2877 * @hw: pointer to the HW structure
2878 *
2879 * Does a full reset of the hardware which includes a reset of the PHY and
2880 * MAC.
2881 **/
2882static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2883{
1d5846b9 2884 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
db2932ec 2885 u16 reg;
bc7f75fa
AK		 2886 u32 ctrl, icr, kab;
2887 s32 ret_val;
2888
ad68076e
BA		 2889 /*
2890 * Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 2891 * on the last TLP read/write transaction when MAC is reset.
2892 */
2893 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 2894 if (ret_val)
3bb99fe2 2895 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 2896
3bb99fe2 2897 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 2898 ew32(IMC, 0xffffffff);
2899
ad68076e
BA		 2900 /*
2901 * Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 2902 * any pending transactions to complete before we hit the MAC
2903 * with the global reset.
2904 */
2905 ew32(RCTL, 0);
2906 ew32(TCTL, E1000_TCTL_PSP);
2907 e1e_flush();
2908
2909 msleep(10);
2910
2911 /* Workaround for ICH8 bit corruption issue in FIFO memory */
2912 if (hw->mac.type == e1000_ich8lan) {
2913 /* Set Tx and Rx buffer allocation to 8k apiece. */
2914 ew32(PBA, E1000_PBA_8K);
2915 /* Set Packet Buffer Size to 16k. */
2916 ew32(PBS, E1000_PBS_16K);
2917 }
2918
1d5846b9
BA		 2919 if (hw->mac.type == e1000_pchlan) {
2920 /* Save the NVM K1 bit setting*/
2921 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2922 if (ret_val)
2923 return ret_val;
2924
2925 if (reg & E1000_NVM_K1_ENABLE)
2926 dev_spec->nvm_k1_enabled = true;
2927 else
2928 dev_spec->nvm_k1_enabled = false;
2929 }
2930
bc7f75fa
AK		 2931 ctrl = er32(CTRL);
2932
2933 if (!e1000_check_reset_block(hw)) {
ad68076e 2934 /*
e98cac44 2935 * Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 2936 * time to make sure the interface between MAC and the
2937 * external PHY is reset.
2938 */
2939 ctrl |= E1000_CTRL_PHY_RST;
2940 }
2941 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 2942 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa
AK		 2943 ew32(CTRL, (ctrl | E1000_CTRL_RST));
2944 msleep(20);
2945
fc0c7760 2946 if (!ret_val)
30bb0e0d 2947 e1000_release_swflag_ich8lan(hw);
37f40239 2948
e98cac44 2949 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 2950 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44
BA		 2951 if (ret_val)
2952 goto out;
fc0c7760 2953
e98cac44 2954 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211
BA		 2955 if (ret_val)
2956 goto out;
2957 }
e98cac44 2958
7d3cabbc
BA		 2959 /*
2960 * For PCH, this write will make sure that any noise
2961 * will be detected as a CRC error and be dropped rather than show up
2962 * as a bad packet to the DMA engine.
2963 */
2964 if (hw->mac.type == e1000_pchlan)
2965 ew32(CRC_OFFSET, 0x65656565);
2966
bc7f75fa
AK		 2967 ew32(IMC, 0xffffffff);
2968 icr = er32(ICR);
2969
2970 kab = er32(KABGTXD);
2971 kab |= E1000_KABGTXD_BGSQLBIAS;
2972 ew32(KABGTXD, kab);
2973
f523d211 2974out:
bc7f75fa
AK		 2975 return ret_val;
2976}
2977
2978/**
2979 * e1000_init_hw_ich8lan - Initialize the hardware
2980 * @hw: pointer to the HW structure
2981 *
2982 * Prepares the hardware for transmit and receive by doing the following:
2983 * - initialize hardware bits
2984 * - initialize LED identification
2985 * - setup receive address registers
2986 * - setup flow control
489815ce 2987 * - setup transmit descriptors
bc7f75fa
AK		 2988 * - clear statistics
2989 **/
2990static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2991{
2992 struct e1000_mac_info *mac = &hw->mac;
2993 u32 ctrl_ext, txdctl, snoop;
2994 s32 ret_val;
2995 u16 i;
2996
2997 e1000_initialize_hw_bits_ich8lan(hw);
2998
2999 /* Initialize identification LED */
a4f58f54 3000 ret_val = mac->ops.id_led_init(hw);
de39b752 3001 if (ret_val)
3bb99fe2 3002 e_dbg("Error initializing identification LED\n");
de39b752 3003 /* This is not fatal and we should not stop init due to this */
bc7f75fa
AK		 3004
3005 /* Setup the receive address. */
3006 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3007
3008 /* Zero out the Multicast HASH table */
3bb99fe2 3009 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 3010 for (i = 0; i < mac->mta_reg_count; i++)
3011 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3012
fc0c7760
BA		 3013 /*
3014 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3015 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
3016 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3017 */
3018 if (hw->phy.type == e1000_phy_82578) {
94d8186a 3019 hw->phy.ops.read_reg(hw, BM_WUC, &i);
fc0c7760
BA		 3020 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3021 if (ret_val)
3022 return ret_val;
3023 }
3024
bc7f75fa
AK		 3025 /* Setup link and flow control */
3026 ret_val = e1000_setup_link_ich8lan(hw);
3027
3028 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 3029 txdctl = er32(TXDCTL(0));
bc7f75fa
AK		 3030 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3031 E1000_TXDCTL_FULL_TX_DESC_WB;
3032 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3033 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f
JK		 3034 ew32(TXDCTL(0), txdctl);
3035 txdctl = er32(TXDCTL(1));
bc7f75fa
AK		 3036 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3037 E1000_TXDCTL_FULL_TX_DESC_WB;
3038 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3039 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f 3040 ew32(TXDCTL(1), txdctl);
bc7f75fa 3041
ad68076e
BA		 3042 /*
3043 * ICH8 has opposite polarity of no_snoop bits.
3044 * By default, we should use snoop behavior.
3045 */
bc7f75fa
AK		 3046 if (mac->type == e1000_ich8lan)
3047 snoop = PCIE_ICH8_SNOOP_ALL;
3048 else
3049 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3050 e1000e_set_pcie_no_snoop(hw, snoop);
3051
3052 ctrl_ext = er32(CTRL_EXT);
3053 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3054 ew32(CTRL_EXT, ctrl_ext);
3055
ad68076e
BA		 3056 /*
3057 * Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 3058 * important that we do this after we have tried to establish link
3059 * because the symbol error count will increment wildly if there
3060 * is no link.
3061 */
3062 e1000_clear_hw_cntrs_ich8lan(hw);
3063
3064 return 0;
3065}
3066/**
3067 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3068 * @hw: pointer to the HW structure
3069 *
3070 * Sets/Clears required hardware bits necessary for correctly setting up the
3071 * hardware for transmit and receive.
3072 **/
3073static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3074{
3075 u32 reg;
3076
3077 /* Extended Device Control */
3078 reg = er32(CTRL_EXT);
3079 reg |= (1 << 22);
a4f58f54
BA		 3080 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3081 if (hw->mac.type >= e1000_pchlan)
3082 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 3083 ew32(CTRL_EXT, reg);
3084
3085 /* Transmit Descriptor Control 0 */
e9ec2c0f 3086 reg = er32(TXDCTL(0));
bc7f75fa 3087 reg |= (1 << 22);
e9ec2c0f 3088 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 3089
3090 /* Transmit Descriptor Control 1 */
e9ec2c0f 3091 reg = er32(TXDCTL(1));
bc7f75fa 3092 reg |= (1 << 22);
e9ec2c0f 3093 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 3094
3095 /* Transmit Arbitration Control 0 */
e9ec2c0f 3096 reg = er32(TARC(0));
bc7f75fa
AK		 3097 if (hw->mac.type == e1000_ich8lan)
3098 reg |= (1 << 28) | (1 << 29);
3099 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 3100 ew32(TARC(0), reg);
bc7f75fa
AK		 3101
3102 /* Transmit Arbitration Control 1 */
e9ec2c0f 3103 reg = er32(TARC(1));
bc7f75fa
AK		 3104 if (er32(TCTL) & E1000_TCTL_MULR)
3105 reg &= ~(1 << 28);
3106 else
3107 reg |= (1 << 28);
3108 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 3109 ew32(TARC(1), reg);
bc7f75fa
AK		 3110
3111 /* Device Status */
3112 if (hw->mac.type == e1000_ich8lan) {
3113 reg = er32(STATUS);
3114 reg &= ~(1 << 31);
3115 ew32(STATUS, reg);
3116 }
a80483d3
JB		 3117
3118 /*
3119 * work-around descriptor data corruption issue during nfs v2 udp
3120 * traffic, just disable the nfs filtering capability
3121 */
3122 reg = er32(RFCTL);
3123 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3124 ew32(RFCTL, reg);
bc7f75fa
AK		 3125}
3126
3127/**
3128 * e1000_setup_link_ich8lan - Setup flow control and link settings
3129 * @hw: pointer to the HW structure
3130 *
3131 * Determines which flow control settings to use, then configures flow
3132 * control. Calls the appropriate media-specific link configuration
3133 * function. Assuming the adapter has a valid link partner, a valid link
3134 * should be established. Assumes the hardware has previously been reset
3135 * and the transmitter and receiver are not enabled.
3136 **/
3137static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3138{
bc7f75fa
AK		 3139 s32 ret_val;
3140
3141 if (e1000_check_reset_block(hw))
3142 return 0;
3143
ad68076e
BA		 3144 /*
3145 * ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 3146 * the default flow control setting, so we explicitly
3147 * set it to full.
3148 */
37289d9c
BA		 3149 if (hw->fc.requested_mode == e1000_fc_default) {
3150 /* Workaround h/w hang when Tx flow control enabled */
3151 if (hw->mac.type == e1000_pchlan)
3152 hw->fc.requested_mode = e1000_fc_rx_pause;
3153 else
3154 hw->fc.requested_mode = e1000_fc_full;
3155 }
bc7f75fa 3156
5c48ef3e
BA		 3157 /*
3158 * Save off the requested flow control mode for use later. Depending
3159 * on the link partner's capabilities, we may or may not use this mode.
3160 */
3161 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 3162
3bb99fe2 3163 e_dbg("After fix-ups FlowControl is now = %x\n",
5c48ef3e 3164 hw->fc.current_mode);
bc7f75fa
AK		 3165
3166 /* Continue to configure the copper link. */
3167 ret_val = e1000_setup_copper_link_ich8lan(hw);
3168 if (ret_val)
3169 return ret_val;
3170
318a94d6 3171 ew32(FCTTV, hw->fc.pause_time);
a4f58f54 3172 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3173 (hw->phy.type == e1000_phy_82579) ||
a4f58f54 3174 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 3175 ew32(FCRTV_PCH, hw->fc.refresh_time);
3176
94d8186a 3177 ret_val = hw->phy.ops.write_reg(hw,
a4f58f54
BA		 3178 PHY_REG(BM_PORT_CTRL_PAGE, 27),
3179 hw->fc.pause_time);
3180 if (ret_val)
3181 return ret_val;
3182 }
bc7f75fa
AK		 3183
3184 return e1000e_set_fc_watermarks(hw);
3185}
3186
3187/**
3188 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3189 * @hw: pointer to the HW structure
3190 *
3191 * Configures the kumeran interface to the PHY to wait the appropriate time
3192 * when polling the PHY, then call the generic setup_copper_link to finish
3193 * configuring the copper link.
3194 **/
3195static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3196{
3197 u32 ctrl;
3198 s32 ret_val;
3199 u16 reg_data;
3200
3201 ctrl = er32(CTRL);
3202 ctrl |= E1000_CTRL_SLU;
3203 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3204 ew32(CTRL, ctrl);
3205
ad68076e
BA		 3206 /*
3207 * Set the mac to wait the maximum time between each iteration
bc7f75fa 3208 * and increase the max iterations when polling the phy;
ad68076e
BA		 3209 * this fixes erroneous timeouts at 10Mbps.
3210 */
07818950 3211 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 3212 if (ret_val)
3213 return ret_val;
07818950
BA		 3214 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3215 &reg_data);
bc7f75fa
AK		 3216 if (ret_val)
3217 return ret_val;
3218 reg_data |= 0x3F;
07818950
BA		 3219 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3220 reg_data);
bc7f75fa
AK		 3221 if (ret_val)
3222 return ret_val;
3223
a4f58f54
BA		 3224 switch (hw->phy.type) {
3225 case e1000_phy_igp_3:
bc7f75fa
AK		 3226 ret_val = e1000e_copper_link_setup_igp(hw);
3227 if (ret_val)
3228 return ret_val;
a4f58f54
BA		 3229 break;
3230 case e1000_phy_bm:
3231 case e1000_phy_82578:
97ac8cae
BA		 3232 ret_val = e1000e_copper_link_setup_m88(hw);
3233 if (ret_val)
3234 return ret_val;
a4f58f54
BA		 3235 break;
3236 case e1000_phy_82577:
d3738bb8 3237 case e1000_phy_82579:
a4f58f54
BA		 3238 ret_val = e1000_copper_link_setup_82577(hw);
3239 if (ret_val)
3240 return ret_val;
3241 break;
3242 case e1000_phy_ife:
94d8186a 3243 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 3244 &reg_data);
97ac8cae
BA		 3245 if (ret_val)
3246 return ret_val;
3247
3248 reg_data &= ~IFE_PMC_AUTO_MDIX;
3249
3250 switch (hw->phy.mdix) {
3251 case 1:
3252 reg_data &= ~IFE_PMC_FORCE_MDIX;
3253 break;
3254 case 2:
3255 reg_data |= IFE_PMC_FORCE_MDIX;
3256 break;
3257 case 0:
3258 default:
3259 reg_data |= IFE_PMC_AUTO_MDIX;
3260 break;
3261 }
94d8186a 3262 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 3263 reg_data);
97ac8cae
BA		 3264 if (ret_val)
3265 return ret_val;
a4f58f54
BA		 3266 break;
3267 default:
3268 break;
97ac8cae 3269 }
bc7f75fa
AK		 3270 return e1000e_setup_copper_link(hw);
3271}
3272
3273/**
3274 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3275 * @hw: pointer to the HW structure
3276 * @speed: pointer to store current link speed
3277 * @duplex: pointer to store the current link duplex
3278 *
ad68076e 3279 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 3280 * information and then calls the Kumeran lock loss workaround for links at
3281 * gigabit speeds.
3282 **/
3283static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3284 u16 *duplex)
3285{
3286 s32 ret_val;
3287
3288 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3289 if (ret_val)
3290 return ret_val;
3291
3292 if ((hw->mac.type == e1000_ich8lan) &&
3293 (hw->phy.type == e1000_phy_igp_3) &&
3294 (*speed == SPEED_1000)) {
3295 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3296 }
3297
3298 return ret_val;
3299}
3300
3301/**
3302 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3303 * @hw: pointer to the HW structure
3304 *
3305 * Work-around for 82566 Kumeran PCS lock loss:
3306 * On link status change (i.e. PCI reset, speed change) and link is up and
3307 * speed is gigabit-
3308 * 0) if workaround is optionally disabled do nothing
3309 * 1) wait 1ms for Kumeran link to come up
3310 * 2) check Kumeran Diagnostic register PCS lock loss bit
3311 * 3) if not set the link is locked (all is good), otherwise...
3312 * 4) reset the PHY
3313 * 5) repeat up to 10 times
3314 * Note: this is only called for IGP3 copper when speed is 1gb.
3315 **/
3316static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3317{
3318 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3319 u32 phy_ctrl;
3320 s32 ret_val;
3321 u16 i, data;
3322 bool link;
3323
3324 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3325 return 0;
3326
ad68076e
BA		 3327 /*
3328 * Make sure link is up before proceeding. If not just return.
bc7f75fa 3329 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 3330 * stability
3331 */
bc7f75fa
AK		 3332 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3333 if (!link)
3334 return 0;
3335
3336 for (i = 0; i < 10; i++) {
3337 /* read once to clear */
3338 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3339 if (ret_val)
3340 return ret_val;
3341 /* and again to get new status */
3342 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3343 if (ret_val)
3344 return ret_val;
3345
3346 /* check for PCS lock */
3347 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3348 return 0;
3349
3350 /* Issue PHY reset */
3351 e1000_phy_hw_reset(hw);
3352 mdelay(5);
3353 }
3354 /* Disable GigE link negotiation */
3355 phy_ctrl = er32(PHY_CTRL);
3356 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3357 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3358 ew32(PHY_CTRL, phy_ctrl);
3359
ad68076e
BA		 3360 /*
3361 * Call gig speed drop workaround on Gig disable before accessing
3362 * any PHY registers
3363 */
bc7f75fa
AK		 3364 e1000e_gig_downshift_workaround_ich8lan(hw);
3365
3366 /* unable to acquire PCS lock */
3367 return -E1000_ERR_PHY;
3368}
3369
3370/**
ad68076e 3371 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 3372 * @hw: pointer to the HW structure
489815ce 3373 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 3374 *
564ea9bb
BA		 3375 * If ICH8, set the current Kumeran workaround state (enabled - true
3376 * /disabled - false).
bc7f75fa
AK		 3377 **/
3378void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3379 bool state)
3380{
3381 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3382
3383 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 3384 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 3385 return;
3386 }
3387
3388 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3389}
3390
3391/**
3392 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3393 * @hw: pointer to the HW structure
3394 *
3395 * Workaround for 82566 power-down on D3 entry:
3396 * 1) disable gigabit link
3397 * 2) write VR power-down enable
3398 * 3) read it back
3399 * Continue if successful, else issue LCD reset and repeat
3400 **/
3401void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3402{
3403 u32 reg;
3404 u16 data;
3405 u8 retry = 0;
3406
3407 if (hw->phy.type != e1000_phy_igp_3)
3408 return;
3409
3410 /* Try the workaround twice (if needed) */
3411 do {
3412 /* Disable link */
3413 reg = er32(PHY_CTRL);
3414 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3415 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3416 ew32(PHY_CTRL, reg);
3417
ad68076e
BA		 3418 /*
3419 * Call gig speed drop workaround on Gig disable before
3420 * accessing any PHY registers
3421 */
bc7f75fa
AK		 3422 if (hw->mac.type == e1000_ich8lan)
3423 e1000e_gig_downshift_workaround_ich8lan(hw);
3424
3425 /* Write VR power-down enable */
3426 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3427 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3428 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3429
3430 /* Read it back and test */
3431 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3432 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3433 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3434 break;
3435
3436 /* Issue PHY reset and repeat at most one more time */
3437 reg = er32(CTRL);
3438 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3439 retry++;
3440 } while (retry);
3441}
3442
3443/**
3444 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3445 * @hw: pointer to the HW structure
3446 *
3447 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 3448 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 3449 * 1) Set Kumeran Near-end loopback
3450 * 2) Clear Kumeran Near-end loopback
3451 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3452 **/
3453void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3454{
3455 s32 ret_val;
3456 u16 reg_data;
3457
3458 if ((hw->mac.type != e1000_ich8lan) ||
3459 (hw->phy.type != e1000_phy_igp_3))
3460 return;
3461
3462 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3463 &reg_data);
3464 if (ret_val)
3465 return;
3466 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3467 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3468 reg_data);
3469 if (ret_val)
3470 return;
3471 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3472 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3473 reg_data);
3474}
3475
97ac8cae
BA		 3476/**
3477 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3478 * @hw: pointer to the HW structure
3479 *
3480 * During S0 to Sx transition, it is possible the link remains at gig
3481 * instead of negotiating to a lower speed. Before going to Sx, set
3482 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3483 * to a lower speed.
3484 *
a4f58f54 3485 * Should only be called for applicable parts.
97ac8cae
BA		 3486 **/
3487void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3488{
3489 u32 phy_ctrl;
8395ae83 3490 s32 ret_val;
97ac8cae 3491
17f085df
BA		 3492 phy_ctrl = er32(PHY_CTRL);
3493 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3494 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 3495
8395ae83
BA		 3496 if (hw->mac.type >= e1000_pchlan) {
3497 e1000_oem_bits_config_ich8lan(hw, true);
3498 ret_val = hw->phy.ops.acquire(hw);
3499 if (ret_val)
3500 return;
3501 e1000_write_smbus_addr(hw);
3502 hw->phy.ops.release(hw);
3503 }
97ac8cae
BA		 3504}
3505
bc7f75fa
AK		 3506/**
3507 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3508 * @hw: pointer to the HW structure
3509 *
3510 * Return the LED back to the default configuration.
3511 **/
3512static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3513{
3514 if (hw->phy.type == e1000_phy_ife)
3515 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3516
3517 ew32(LEDCTL, hw->mac.ledctl_default);
3518 return 0;
3519}
3520
3521/**
489815ce 3522 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 3523 * @hw: pointer to the HW structure
3524 *
489815ce 3525 * Turn on the LEDs.
bc7f75fa
AK		 3526 **/
3527static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3528{
3529 if (hw->phy.type == e1000_phy_ife)
3530 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3531 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3532
3533 ew32(LEDCTL, hw->mac.ledctl_mode2);
3534 return 0;
3535}
3536
3537/**
489815ce 3538 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 3539 * @hw: pointer to the HW structure
3540 *
489815ce 3541 * Turn off the LEDs.
bc7f75fa
AK		 3542 **/
3543static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3544{
3545 if (hw->phy.type == e1000_phy_ife)
3546 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3547 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3548
3549 ew32(LEDCTL, hw->mac.ledctl_mode1);
3550 return 0;
3551}
3552
a4f58f54
BA		 3553/**
3554 * e1000_setup_led_pchlan - Configures SW controllable LED
3555 * @hw: pointer to the HW structure
3556 *
3557 * This prepares the SW controllable LED for use.
3558 **/
3559static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3560{
94d8186a 3561 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3562 (u16)hw->mac.ledctl_mode1);
3563}
3564
3565/**
3566 * e1000_cleanup_led_pchlan - Restore the default LED operation
3567 * @hw: pointer to the HW structure
3568 *
3569 * Return the LED back to the default configuration.
3570 **/
3571static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3572{
94d8186a 3573 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3574 (u16)hw->mac.ledctl_default);
3575}
3576
3577/**
3578 * e1000_led_on_pchlan - Turn LEDs on
3579 * @hw: pointer to the HW structure
3580 *
3581 * Turn on the LEDs.
3582 **/
3583static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3584{
3585 u16 data = (u16)hw->mac.ledctl_mode2;
3586 u32 i, led;
3587
3588 /*
3589 * If no link, then turn LED on by setting the invert bit
3590 * for each LED that's mode is "link_up" in ledctl_mode2.
3591 */
3592 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3593 for (i = 0; i < 3; i++) {
3594 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3595 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3596 E1000_LEDCTL_MODE_LINK_UP)
3597 continue;
3598 if (led & E1000_PHY_LED0_IVRT)
3599 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3600 else
3601 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3602 }
3603 }
3604
94d8186a 3605 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3606}
3607
3608/**
3609 * e1000_led_off_pchlan - Turn LEDs off
3610 * @hw: pointer to the HW structure
3611 *
3612 * Turn off the LEDs.
3613 **/
3614static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3615{
3616 u16 data = (u16)hw->mac.ledctl_mode1;
3617 u32 i, led;
3618
3619 /*
3620 * If no link, then turn LED off by clearing the invert bit
3621 * for each LED that's mode is "link_up" in ledctl_mode1.
3622 */
3623 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3624 for (i = 0; i < 3; i++) {
3625 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3626 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3627 E1000_LEDCTL_MODE_LINK_UP)
3628 continue;
3629 if (led & E1000_PHY_LED0_IVRT)
3630 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3631 else
3632 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3633 }
3634 }
3635
94d8186a 3636 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3637}
3638
f4187b56 3639/**
e98cac44 3640 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 3641 * @hw: pointer to the HW structure
3642 *
e98cac44
BA		 3643 * Read appropriate register for the config done bit for completion status
3644 * and configure the PHY through s/w for EEPROM-less parts.
3645 *
3646 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3647 * config done bit, so only an error is logged and continues. If we were
3648 * to return with error, EEPROM-less silicon would not be able to be reset
3649 * or change link.
f4187b56
BA		 3650 **/
3651static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3652{
e98cac44 3653 s32 ret_val = 0;
f4187b56 3654 u32 bank = 0;
e98cac44 3655 u32 status;
f4187b56 3656
e98cac44 3657 e1000e_get_cfg_done(hw);
fc0c7760 3658
e98cac44
BA		 3659 /* Wait for indication from h/w that it has completed basic config */
3660 if (hw->mac.type >= e1000_ich10lan) {
3661 e1000_lan_init_done_ich8lan(hw);
3662 } else {
3663 ret_val = e1000e_get_auto_rd_done(hw);
3664 if (ret_val) {
3665 /*
3666 * When auto config read does not complete, do not
3667 * return with an error. This can happen in situations
3668 * where there is no eeprom and prevents getting link.
3669 */
3670 e_dbg("Auto Read Done did not complete\n");
3671 ret_val = 0;
3672 }
fc0c7760
BA		 3673 }
3674
e98cac44
BA		 3675 /* Clear PHY Reset Asserted bit */
3676 status = er32(STATUS);
3677 if (status & E1000_STATUS_PHYRA)
3678 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3679 else
3680 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 3681
3682 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 3683 if (hw->mac.type <= e1000_ich9lan) {
f4187b56
BA		 3684 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3685 (hw->phy.type == e1000_phy_igp_3)) {
3686 e1000e_phy_init_script_igp3(hw);
3687 }
3688 } else {
3689 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3690 /* Maybe we should do a basic PHY config */
3bb99fe2 3691 e_dbg("EEPROM not present\n");
e98cac44 3692 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 3693 }
3694 }
3695
e98cac44 3696 return ret_val;
f4187b56
BA		 3697}
3698
17f208de
BA		 3699/**
3700 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3701 * @hw: pointer to the HW structure
3702 *
3703 * In the case of a PHY power down to save power, or to turn off link during a
3704 * driver unload, or wake on lan is not enabled, remove the link.
3705 **/
3706static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3707{
3708 /* If the management interface is not enabled, then power down */
3709 if (!(hw->mac.ops.check_mng_mode(hw) ||
3710 hw->phy.ops.check_reset_block(hw)))
3711 e1000_power_down_phy_copper(hw);
17f208de
BA		 3712}
3713
bc7f75fa
AK		 3714/**
3715 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3716 * @hw: pointer to the HW structure
3717 *
3718 * Clears hardware counters specific to the silicon family and calls
3719 * clear_hw_cntrs_generic to clear all general purpose counters.
3720 **/
3721static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3722{
a4f58f54 3723 u16 phy_data;
bc7f75fa
AK		 3724
3725 e1000e_clear_hw_cntrs_base(hw);
3726
99673d9b
BA		 3727 er32(ALGNERRC);
3728 er32(RXERRC);
3729 er32(TNCRS);
3730 er32(CEXTERR);
3731 er32(TSCTC);
3732 er32(TSCTFC);
bc7f75fa 3733
99673d9b
BA		 3734 er32(MGTPRC);
3735 er32(MGTPDC);
3736 er32(MGTPTC);
bc7f75fa 3737
99673d9b
BA		 3738 er32(IAC);
3739 er32(ICRXOC);
bc7f75fa 3740
a4f58f54
BA		 3741 /* Clear PHY statistics registers */
3742 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3743 (hw->phy.type == e1000_phy_82579) ||
a4f58f54 3744 (hw->phy.type == e1000_phy_82577)) {
94d8186a
BA		 3745 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3746 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3747 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3748 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3749 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3750 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3751 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3752 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3753 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3754 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3755 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3756 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3757 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3758 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
a4f58f54 3759 }
bc7f75fa
AK		 3760}
3761
3762static struct e1000_mac_operations ich8_mac_ops = {
a4f58f54 3763 .id_led_init = e1000e_id_led_init,
eb7700dc 3764 /* check_mng_mode dependent on mac type */
7d3cabbc 3765 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 3766 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 3767 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3768 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 3769 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 3770 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 3771 /* led_on dependent on mac type */
3772 /* led_off dependent on mac type */
e2de3eb6 3773 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 3774 .reset_hw = e1000_reset_hw_ich8lan,
3775 .init_hw = e1000_init_hw_ich8lan,
3776 .setup_link = e1000_setup_link_ich8lan,
3777 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
a4f58f54 3778 /* id_led_init dependent on mac type */
bc7f75fa
AK		 3779};
3780
3781static struct e1000_phy_operations ich8_phy_ops = {
94d8186a 3782 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 3783 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 3784 .commit = NULL,
f4187b56 3785 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 3786 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 3787 .read_reg = e1000e_read_phy_reg_igp,
3788 .release = e1000_release_swflag_ich8lan,
3789 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 3790 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3791 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 3792 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 3793};
3794
3795static struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a
BA		 3796 .acquire = e1000_acquire_nvm_ich8lan,
3797 .read = e1000_read_nvm_ich8lan,
3798 .release = e1000_release_nvm_ich8lan,
3799 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 3800 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 3801 .validate = e1000_validate_nvm_checksum_ich8lan,
3802 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 3803};
3804
3805struct e1000_info e1000_ich8_info = {
3806 .mac = e1000_ich8lan,
3807 .flags = FLAG_HAS_WOL
97ac8cae 3808 | FLAG_IS_ICH
bc7f75fa
AK		 3809 | FLAG_RX_CSUM_ENABLED
3810 | FLAG_HAS_CTRLEXT_ON_LOAD
3811 | FLAG_HAS_AMT
3812 | FLAG_HAS_FLASH
3813 | FLAG_APME_IN_WUC,
3814 .pba = 8,
2adc55c9 3815 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 3816 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3817 .mac_ops = &ich8_mac_ops,
3818 .phy_ops = &ich8_phy_ops,
3819 .nvm_ops = &ich8_nvm_ops,
3820};
3821
3822struct e1000_info e1000_ich9_info = {
3823 .mac = e1000_ich9lan,
3824 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 3825 | FLAG_IS_ICH
bc7f75fa
AK		 3826 | FLAG_HAS_WOL
3827 | FLAG_RX_CSUM_ENABLED
3828 | FLAG_HAS_CTRLEXT_ON_LOAD
3829 | FLAG_HAS_AMT
3830 | FLAG_HAS_ERT
3831 | FLAG_HAS_FLASH
3832 | FLAG_APME_IN_WUC,
3833 .pba = 10,
2adc55c9 3834 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 3835 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3836 .mac_ops = &ich8_mac_ops,
3837 .phy_ops = &ich8_phy_ops,
3838 .nvm_ops = &ich8_nvm_ops,
3839};
3840
f4187b56
BA		 3841struct e1000_info e1000_ich10_info = {
3842 .mac = e1000_ich10lan,
3843 .flags = FLAG_HAS_JUMBO_FRAMES
3844 | FLAG_IS_ICH
3845 | FLAG_HAS_WOL
3846 | FLAG_RX_CSUM_ENABLED
3847 | FLAG_HAS_CTRLEXT_ON_LOAD
3848 | FLAG_HAS_AMT
3849 | FLAG_HAS_ERT
3850 | FLAG_HAS_FLASH
3851 | FLAG_APME_IN_WUC,
3852 .pba = 10,
2adc55c9 3853 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 3854 .get_variants = e1000_get_variants_ich8lan,
3855 .mac_ops = &ich8_mac_ops,
3856 .phy_ops = &ich8_phy_ops,
3857 .nvm_ops = &ich8_nvm_ops,
3858};
a4f58f54
BA		 3859
3860struct e1000_info e1000_pch_info = {
3861 .mac = e1000_pchlan,
3862 .flags = FLAG_IS_ICH
3863 | FLAG_HAS_WOL
3864 | FLAG_RX_CSUM_ENABLED
3865 | FLAG_HAS_CTRLEXT_ON_LOAD
3866 | FLAG_HAS_AMT
3867 | FLAG_HAS_FLASH
3868 | FLAG_HAS_JUMBO_FRAMES
38eb394e 3869 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54 3870 | FLAG_APME_IN_WUC,
8c7bbb92 3871 .flags2 = FLAG2_HAS_PHY_STATS,
a4f58f54
BA		 3872 .pba = 26,
3873 .max_hw_frame_size = 4096,
3874 .get_variants = e1000_get_variants_ich8lan,
3875 .mac_ops = &ich8_mac_ops,
3876 .phy_ops = &ich8_phy_ops,
3877 .nvm_ops = &ich8_nvm_ops,
3878};
d3738bb8
BA		 3879
3880struct e1000_info e1000_pch2_info = {
3881 .mac = e1000_pch2lan,
3882 .flags = FLAG_IS_ICH
3883 | FLAG_HAS_WOL
3884 | FLAG_RX_CSUM_ENABLED
3885 | FLAG_HAS_CTRLEXT_ON_LOAD
3886 | FLAG_HAS_AMT
3887 | FLAG_HAS_FLASH
3888 | FLAG_HAS_JUMBO_FRAMES
3889 | FLAG_APME_IN_WUC,
e52997f9
BA		 3890 .flags2 = FLAG2_HAS_PHY_STATS
3891 | FLAG2_HAS_EEE,
d3738bb8
BA		 3892 .pba = 18,
3893 .max_hw_frame_size = DEFAULT_JUMBO,
3894 .get_variants = e1000_get_variants_ich8lan,
3895 .mac_ops = &ich8_mac_ops,
3896 .phy_ops = &ich8_phy_ops,
3897 .nvm_ops = &ich8_nvm_ops,
3898};
Linux kernel - Deliverables
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