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e1000e: checkpatch warnings - braces
[deliverable/linux.git] / drivers / net / e1000e / ich8lan.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
451152d9 4 Copyright(c) 1999 - 2010 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29/*
1605927f 30 * 82562G 10/100 Network Connection
bc7f75fa
AK		 31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
97ac8cae
BA		 42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
1605927f 44 * 82567V Gigabit Network Connection
97ac8cae
BA		 45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
f4187b56
BA		 48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
2f15f9d6 50 * 82567LM-4 Gigabit Network Connection
a4f58f54
BA		 51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
d3738bb8
BA		 55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
bc7f75fa
AK		 57 */
58
bc7f75fa
AK		 59#include "e1000.h"
60
61#define ICH_FLASH_GFPREG 0x0000
62#define ICH_FLASH_HSFSTS 0x0004
63#define ICH_FLASH_HSFCTL 0x0006
64#define ICH_FLASH_FADDR 0x0008
65#define ICH_FLASH_FDATA0 0x0010
4a770358 66#define ICH_FLASH_PR0 0x0074
bc7f75fa
AK		 67
68#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69#define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70#define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
73
74#define ICH_CYCLE_READ 0
75#define ICH_CYCLE_WRITE 2
76#define ICH_CYCLE_ERASE 3
77
78#define FLASH_GFPREG_BASE_MASK 0x1FFF
79#define FLASH_SECTOR_ADDR_SHIFT 12
80
81#define ICH_FLASH_SEG_SIZE_256 256
82#define ICH_FLASH_SEG_SIZE_4K 4096
83#define ICH_FLASH_SEG_SIZE_8K 8192
84#define ICH_FLASH_SEG_SIZE_64K 65536
85
86
87#define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
6dfaa769
BA		 88/* FW established a valid mode */
89#define E1000_ICH_FWSM_FW_VALID 0x00008000
bc7f75fa
AK		 90
91#define E1000_ICH_MNG_IAMT_MODE 0x2
92
93#define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
96 (ID_LED_DEF1_DEF2))
97
98#define E1000_ICH_NVM_SIG_WORD 0x13
99#define E1000_ICH_NVM_SIG_MASK 0xC000
e243455d
BA		 100#define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101#define E1000_ICH_NVM_SIG_VALUE 0x80
bc7f75fa
AK		 102
103#define E1000_ICH8_LAN_INIT_TIMEOUT 1500
104
105#define E1000_FEXTNVM_SW_CONFIG 1
106#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
107
831bd2e6
BA		 108#define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109#define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110#define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
111
bc7f75fa
AK		 112#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
113
114#define E1000_ICH_RAR_ENTRIES 7
115
116#define PHY_PAGE_SHIFT 5
117#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119#define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120#define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
121
122#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124#define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
125
a4f58f54
BA		 126#define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
127
53ac5a88
BA		 128#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
129
f523d211
BA		 130/* SMBus Address Phy Register */
131#define HV_SMB_ADDR PHY_REG(768, 26)
8395ae83 132#define HV_SMB_ADDR_MASK 0x007F
f523d211
BA		 133#define HV_SMB_ADDR_PEC_EN 0x0200
134#define HV_SMB_ADDR_VALID 0x0080
135
d3738bb8
BA		 136/* PHY Power Management Control */
137#define HV_PM_CTRL PHY_REG(770, 17)
138
e52997f9
BA		 139/* PHY Low Power Idle Control */
140#define I82579_LPI_CTRL PHY_REG(772, 20)
141#define I82579_LPI_CTRL_ENABLE_MASK 0x6000
142
f523d211
BA		 143/* Strapping Option Register - RO */
144#define E1000_STRAP 0x0000C
145#define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
146#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
147
fa2ce13c
BA		 148/* OEM Bits Phy Register */
149#define HV_OEM_BITS PHY_REG(768, 25)
150#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
f523d211 151#define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
fa2ce13c
BA		 152#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
153
1d5846b9
BA		 154#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
155#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
156
fddaa1af
BA		 157/* KMRN Mode Control */
158#define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
159#define HV_KMRN_MDIO_SLOW 0x0400
160
bc7f75fa
AK		 161/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
162/* Offset 04h HSFSTS */
163union ich8_hws_flash_status {
164 struct ich8_hsfsts {
165 u16 flcdone :1; /* bit 0 Flash Cycle Done */
166 u16 flcerr :1; /* bit 1 Flash Cycle Error */
167 u16 dael :1; /* bit 2 Direct Access error Log */
168 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
169 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
170 u16 reserved1 :2; /* bit 13:6 Reserved */
171 u16 reserved2 :6; /* bit 13:6 Reserved */
172 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
173 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
174 } hsf_status;
175 u16 regval;
176};
177
178/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
179/* Offset 06h FLCTL */
180union ich8_hws_flash_ctrl {
181 struct ich8_hsflctl {
182 u16 flcgo :1; /* 0 Flash Cycle Go */
183 u16 flcycle :2; /* 2:1 Flash Cycle */
184 u16 reserved :5; /* 7:3 Reserved */
185 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
186 u16 flockdn :6; /* 15:10 Reserved */
187 } hsf_ctrl;
188 u16 regval;
189};
190
191/* ICH Flash Region Access Permissions */
192union ich8_hws_flash_regacc {
193 struct ich8_flracc {
194 u32 grra :8; /* 0:7 GbE region Read Access */
195 u32 grwa :8; /* 8:15 GbE region Write Access */
196 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
197 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
198 } hsf_flregacc;
199 u16 regval;
200};
201
4a770358
BA		 202/* ICH Flash Protected Region */
203union ich8_flash_protected_range {
204 struct ich8_pr {
205 u32 base:13; /* 0:12 Protected Range Base */
206 u32 reserved1:2; /* 13:14 Reserved */
207 u32 rpe:1; /* 15 Read Protection Enable */
208 u32 limit:13; /* 16:28 Protected Range Limit */
209 u32 reserved2:2; /* 29:30 Reserved */
210 u32 wpe:1; /* 31 Write Protection Enable */
211 } range;
212 u32 regval;
213};
214
bc7f75fa
AK		 215static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
216static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
217static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
bc7f75fa
AK		 218static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
219static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
220 u32 offset, u8 byte);
f4187b56
BA		 221static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
222 u8 *data);
bc7f75fa
AK		 223static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
224 u16 *data);
225static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
226 u8 size, u16 *data);
227static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
228static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
f4187b56 229static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
a4f58f54
BA		 230static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
231static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
232static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
233static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
234static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
235static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
236static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
237static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
fa2ce13c 238static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
17f208de 239static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
f523d211 240static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
1d5846b9 241static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
fddaa1af 242static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
eb7700dc
BA		 243static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
244static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
831bd2e6 245static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
605c82ba 246static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
bc7f75fa
AK		 247
248static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
249{
250 return readw(hw->flash_address + reg);
251}
252
253static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
254{
255 return readl(hw->flash_address + reg);
256}
257
258static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
259{
260 writew(val, hw->flash_address + reg);
261}
262
263static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
264{
265 writel(val, hw->flash_address + reg);
266}
267
268#define er16flash(reg) __er16flash(hw, (reg))
269#define er32flash(reg) __er32flash(hw, (reg))
270#define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
271#define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
272
a4f58f54
BA		 273/**
274 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
275 * @hw: pointer to the HW structure
276 *
277 * Initialize family-specific PHY parameters and function pointers.
278 **/
279static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
280{
281 struct e1000_phy_info *phy = &hw->phy;
605c82ba 282 u32 ctrl, fwsm;
a4f58f54
BA		 283 s32 ret_val = 0;
284
285 phy->addr = 1;
286 phy->reset_delay_us = 100;
287
94d8186a
BA		 288 phy->ops.read_reg = e1000_read_phy_reg_hv;
289 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
fa2ce13c
BA		 290 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
291 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
94d8186a
BA		 292 phy->ops.write_reg = e1000_write_phy_reg_hv;
293 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
17f208de
BA		 294 phy->ops.power_up = e1000_power_up_phy_copper;
295 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
a4f58f54
BA		 296 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
297
d3738bb8
BA		 298 /*
299 * The MAC-PHY interconnect may still be in SMBus mode
300 * after Sx->S0. If the manageability engine (ME) is
301 * disabled, then toggle the LANPHYPC Value bit to force
302 * the interconnect to PCIe mode.
303 */
605c82ba
BA		 304 fwsm = er32(FWSM);
305 if (!(fwsm & E1000_ICH_FWSM_FW_VALID)) {
6dfaa769
BA		 306 ctrl = er32(CTRL);
307 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
308 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
309 ew32(CTRL, ctrl);
310 udelay(10);
311 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
312 ew32(CTRL, ctrl);
313 msleep(50);
605c82ba
BA		 314
315 /*
316 * Gate automatic PHY configuration by hardware on
317 * non-managed 82579
318 */
319 if (hw->mac.type == e1000_pch2lan)
320 e1000_gate_hw_phy_config_ich8lan(hw, true);
6dfaa769
BA		 321 }
322
627c8a04
BA		 323 /*
324 * Reset the PHY before any acccess to it. Doing so, ensures that
325 * the PHY is in a known good state before we read/write PHY registers.
326 * The generic reset is sufficient here, because we haven't determined
327 * the PHY type yet.
328 */
329 ret_val = e1000e_phy_hw_reset_generic(hw);
330 if (ret_val)
331 goto out;
332
605c82ba
BA		 333 /* Ungate automatic PHY configuration on non-managed 82579 */
334 if ((hw->mac.type == e1000_pch2lan) &&
335 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
336 msleep(10);
337 e1000_gate_hw_phy_config_ich8lan(hw, false);
338 }
339
a4f58f54 340 phy->id = e1000_phy_unknown;
664dc878
BA		 341 switch (hw->mac.type) {
342 default:
343 ret_val = e1000e_get_phy_id(hw);
344 if (ret_val)
345 goto out;
346 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
347 break;
348 /* fall-through */
349 case e1000_pch2lan:
fddaa1af 350 /*
664dc878 351 * In case the PHY needs to be in mdio slow mode,
fddaa1af
BA		 352 * set slow mode and try to get the PHY id again.
353 */
354 ret_val = e1000_set_mdio_slow_mode_hv(hw);
355 if (ret_val)
356 goto out;
357 ret_val = e1000e_get_phy_id(hw);
358 if (ret_val)
359 goto out;
664dc878 360 break;
fddaa1af 361 }
a4f58f54
BA		 362 phy->type = e1000e_get_phy_type_from_id(phy->id);
363
0be84010
BA		 364 switch (phy->type) {
365 case e1000_phy_82577:
d3738bb8 366 case e1000_phy_82579:
a4f58f54
BA		 367 phy->ops.check_polarity = e1000_check_polarity_82577;
368 phy->ops.force_speed_duplex =
369 e1000_phy_force_speed_duplex_82577;
0be84010 370 phy->ops.get_cable_length = e1000_get_cable_length_82577;
94d8186a
BA		 371 phy->ops.get_info = e1000_get_phy_info_82577;
372 phy->ops.commit = e1000e_phy_sw_reset;
eab50ffb 373 break;
0be84010
BA		 374 case e1000_phy_82578:
375 phy->ops.check_polarity = e1000_check_polarity_m88;
376 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
377 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
378 phy->ops.get_info = e1000e_get_phy_info_m88;
379 break;
380 default:
381 ret_val = -E1000_ERR_PHY;
382 break;
a4f58f54
BA		 383 }
384
fddaa1af 385out:
a4f58f54
BA		 386 return ret_val;
387}
388
bc7f75fa
AK		 389/**
390 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
391 * @hw: pointer to the HW structure
392 *
393 * Initialize family-specific PHY parameters and function pointers.
394 **/
395static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
396{
397 struct e1000_phy_info *phy = &hw->phy;
398 s32 ret_val;
399 u16 i = 0;
400
401 phy->addr = 1;
402 phy->reset_delay_us = 100;
403
17f208de
BA		 404 phy->ops.power_up = e1000_power_up_phy_copper;
405 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
406
97ac8cae
BA		 407 /*
408 * We may need to do this twice - once for IGP and if that fails,
409 * we'll set BM func pointers and try again
410 */
411 ret_val = e1000e_determine_phy_address(hw);
412 if (ret_val) {
94d8186a
BA		 413 phy->ops.write_reg = e1000e_write_phy_reg_bm;
414 phy->ops.read_reg = e1000e_read_phy_reg_bm;
97ac8cae 415 ret_val = e1000e_determine_phy_address(hw);
9b71b419
BA		 416 if (ret_val) {
417 e_dbg("Cannot determine PHY addr. Erroring out\n");
97ac8cae 418 return ret_val;
9b71b419 419 }
97ac8cae
BA		 420 }
421
bc7f75fa
AK		 422 phy->id = 0;
423 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
424 (i++ < 100)) {
425 msleep(1);
426 ret_val = e1000e_get_phy_id(hw);
427 if (ret_val)
428 return ret_val;
429 }
430
431 /* Verify phy id */
432 switch (phy->id) {
433 case IGP03E1000_E_PHY_ID:
434 phy->type = e1000_phy_igp_3;
435 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 436 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
437 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
0be84010
BA		 438 phy->ops.get_info = e1000e_get_phy_info_igp;
439 phy->ops.check_polarity = e1000_check_polarity_igp;
440 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
bc7f75fa
AK		 441 break;
442 case IFE_E_PHY_ID:
443 case IFE_PLUS_E_PHY_ID:
444 case IFE_C_E_PHY_ID:
445 phy->type = e1000_phy_ife;
446 phy->autoneg_mask = E1000_ALL_NOT_GIG;
0be84010
BA		 447 phy->ops.get_info = e1000_get_phy_info_ife;
448 phy->ops.check_polarity = e1000_check_polarity_ife;
449 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
bc7f75fa 450 break;
97ac8cae
BA		 451 case BME1000_E_PHY_ID:
452 phy->type = e1000_phy_bm;
453 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94d8186a
BA		 454 phy->ops.read_reg = e1000e_read_phy_reg_bm;
455 phy->ops.write_reg = e1000e_write_phy_reg_bm;
456 phy->ops.commit = e1000e_phy_sw_reset;
0be84010
BA		 457 phy->ops.get_info = e1000e_get_phy_info_m88;
458 phy->ops.check_polarity = e1000_check_polarity_m88;
459 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
97ac8cae 460 break;
bc7f75fa
AK		 461 default:
462 return -E1000_ERR_PHY;
463 break;
464 }
465
466 return 0;
467}
468
469/**
470 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
471 * @hw: pointer to the HW structure
472 *
473 * Initialize family-specific NVM parameters and function
474 * pointers.
475 **/
476static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
477{
478 struct e1000_nvm_info *nvm = &hw->nvm;
479 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
148675a7 480 u32 gfpreg, sector_base_addr, sector_end_addr;
bc7f75fa
AK		 481 u16 i;
482
ad68076e 483 /* Can't read flash registers if the register set isn't mapped. */
bc7f75fa 484 if (!hw->flash_address) {
3bb99fe2 485 e_dbg("ERROR: Flash registers not mapped\n");
bc7f75fa
AK		 486 return -E1000_ERR_CONFIG;
487 }
488
489 nvm->type = e1000_nvm_flash_sw;
490
491 gfpreg = er32flash(ICH_FLASH_GFPREG);
492
ad68076e
BA		 493 /*
494 * sector_X_addr is a "sector"-aligned address (4096 bytes)
bc7f75fa 495 * Add 1 to sector_end_addr since this sector is included in
ad68076e
BA		 496 * the overall size.
497 */
bc7f75fa
AK		 498 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
499 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
500
501 /* flash_base_addr is byte-aligned */
502 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
503
ad68076e
BA		 504 /*
505 * find total size of the NVM, then cut in half since the total
506 * size represents two separate NVM banks.
507 */
bc7f75fa
AK		 508 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
509 << FLASH_SECTOR_ADDR_SHIFT;
510 nvm->flash_bank_size /= 2;
511 /* Adjust to word count */
512 nvm->flash_bank_size /= sizeof(u16);
513
514 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
515
516 /* Clear shadow ram */
517 for (i = 0; i < nvm->word_size; i++) {
564ea9bb 518 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 519 dev_spec->shadow_ram[i].value = 0xFFFF;
520 }
521
522 return 0;
523}
524
525/**
526 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
527 * @hw: pointer to the HW structure
528 *
529 * Initialize family-specific MAC parameters and function
530 * pointers.
531 **/
532static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
533{
534 struct e1000_hw *hw = &adapter->hw;
535 struct e1000_mac_info *mac = &hw->mac;
536
537 /* Set media type function pointer */
318a94d6 538 hw->phy.media_type = e1000_media_type_copper;
bc7f75fa
AK		 539
540 /* Set mta register count */
541 mac->mta_reg_count = 32;
542 /* Set rar entry count */
543 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
544 if (mac->type == e1000_ich8lan)
545 mac->rar_entry_count--;
a65a4a0d
BA		 546 /* FWSM register */
547 mac->has_fwsm = true;
548 /* ARC subsystem not supported */
549 mac->arc_subsystem_valid = false;
f464ba87
BA		 550 /* Adaptive IFS supported */
551 mac->adaptive_ifs = true;
bc7f75fa 552
a4f58f54
BA		 553 /* LED operations */
554 switch (mac->type) {
555 case e1000_ich8lan:
556 case e1000_ich9lan:
557 case e1000_ich10lan:
eb7700dc
BA		 558 /* check management mode */
559 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
a4f58f54
BA		 560 /* ID LED init */
561 mac->ops.id_led_init = e1000e_id_led_init;
562 /* setup LED */
563 mac->ops.setup_led = e1000e_setup_led_generic;
564 /* cleanup LED */
565 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
566 /* turn on/off LED */
567 mac->ops.led_on = e1000_led_on_ich8lan;
568 mac->ops.led_off = e1000_led_off_ich8lan;
569 break;
570 case e1000_pchlan:
d3738bb8 571 case e1000_pch2lan:
eb7700dc
BA		 572 /* check management mode */
573 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
a4f58f54
BA		 574 /* ID LED init */
575 mac->ops.id_led_init = e1000_id_led_init_pchlan;
576 /* setup LED */
577 mac->ops.setup_led = e1000_setup_led_pchlan;
578 /* cleanup LED */
579 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
580 /* turn on/off LED */
581 mac->ops.led_on = e1000_led_on_pchlan;
582 mac->ops.led_off = e1000_led_off_pchlan;
583 break;
584 default:
585 break;
586 }
587
bc7f75fa
AK		 588 /* Enable PCS Lock-loss workaround for ICH8 */
589 if (mac->type == e1000_ich8lan)
564ea9bb 590 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
bc7f75fa 591
605c82ba
BA		 592 /* Gate automatic PHY configuration by hardware on managed 82579 */
593 if ((mac->type == e1000_pch2lan) &&
594 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
595 e1000_gate_hw_phy_config_ich8lan(hw, true);
d3738bb8 596
bc7f75fa
AK		 597 return 0;
598}
599
e52997f9
BA		 600/**
601 * e1000_set_eee_pchlan - Enable/disable EEE support
602 * @hw: pointer to the HW structure
603 *
604 * Enable/disable EEE based on setting in dev_spec structure. The bits in
605 * the LPI Control register will remain set only if/when link is up.
606 **/
607static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
608{
609 s32 ret_val = 0;
610 u16 phy_reg;
611
612 if (hw->phy.type != e1000_phy_82579)
613 goto out;
614
615 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
616 if (ret_val)
617 goto out;
618
619 if (hw->dev_spec.ich8lan.eee_disable)
620 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
621 else
622 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
623
624 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
625out:
626 return ret_val;
627}
628
7d3cabbc
BA		 629/**
630 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
631 * @hw: pointer to the HW structure
632 *
633 * Checks to see of the link status of the hardware has changed. If a
634 * change in link status has been detected, then we read the PHY registers
635 * to get the current speed/duplex if link exists.
636 **/
637static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
638{
639 struct e1000_mac_info *mac = &hw->mac;
640 s32 ret_val;
641 bool link;
642
643 /*
644 * We only want to go out to the PHY registers to see if Auto-Neg
645 * has completed and/or if our link status has changed. The
646 * get_link_status flag is set upon receiving a Link Status
647 * Change or Rx Sequence Error interrupt.
648 */
649 if (!mac->get_link_status) {
650 ret_val = 0;
651 goto out;
652 }
653
7d3cabbc
BA		 654 /*
655 * First we want to see if the MII Status Register reports
656 * link. If so, then we want to get the current speed/duplex
657 * of the PHY.
658 */
659 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
660 if (ret_val)
661 goto out;
662
1d5846b9
BA		 663 if (hw->mac.type == e1000_pchlan) {
664 ret_val = e1000_k1_gig_workaround_hv(hw, link);
665 if (ret_val)
666 goto out;
667 }
668
7d3cabbc
BA		 669 if (!link)
670 goto out; /* No link detected */
671
672 mac->get_link_status = false;
673
674 if (hw->phy.type == e1000_phy_82578) {
675 ret_val = e1000_link_stall_workaround_hv(hw);
676 if (ret_val)
677 goto out;
678 }
679
831bd2e6
BA		 680 if (hw->mac.type == e1000_pch2lan) {
681 ret_val = e1000_k1_workaround_lv(hw);
682 if (ret_val)
683 goto out;
684 }
685
7d3cabbc
BA		 686 /*
687 * Check if there was DownShift, must be checked
688 * immediately after link-up
689 */
690 e1000e_check_downshift(hw);
691
e52997f9
BA		 692 /* Enable/Disable EEE after link up */
693 ret_val = e1000_set_eee_pchlan(hw);
694 if (ret_val)
695 goto out;
696
7d3cabbc
BA		 697 /*
698 * If we are forcing speed/duplex, then we simply return since
699 * we have already determined whether we have link or not.
700 */
701 if (!mac->autoneg) {
702 ret_val = -E1000_ERR_CONFIG;
703 goto out;
704 }
705
706 /*
707 * Auto-Neg is enabled. Auto Speed Detection takes care
708 * of MAC speed/duplex configuration. So we only need to
709 * configure Collision Distance in the MAC.
710 */
711 e1000e_config_collision_dist(hw);
712
713 /*
714 * Configure Flow Control now that Auto-Neg has completed.
715 * First, we need to restore the desired flow control
716 * settings because we may have had to re-autoneg with a
717 * different link partner.
718 */
719 ret_val = e1000e_config_fc_after_link_up(hw);
720 if (ret_val)
3bb99fe2 721 e_dbg("Error configuring flow control\n");
7d3cabbc
BA		 722
723out:
724 return ret_val;
725}
726
69e3fd8c 727static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
bc7f75fa
AK		 728{
729 struct e1000_hw *hw = &adapter->hw;
730 s32 rc;
731
732 rc = e1000_init_mac_params_ich8lan(adapter);
733 if (rc)
734 return rc;
735
736 rc = e1000_init_nvm_params_ich8lan(hw);
737 if (rc)
738 return rc;
739
d3738bb8
BA		 740 switch (hw->mac.type) {
741 case e1000_ich8lan:
742 case e1000_ich9lan:
743 case e1000_ich10lan:
a4f58f54 744 rc = e1000_init_phy_params_ich8lan(hw);
d3738bb8
BA		 745 break;
746 case e1000_pchlan:
747 case e1000_pch2lan:
748 rc = e1000_init_phy_params_pchlan(hw);
749 break;
750 default:
751 break;
752 }
bc7f75fa
AK		 753 if (rc)
754 return rc;
755
2adc55c9
BA		 756 if (adapter->hw.phy.type == e1000_phy_ife) {
757 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
758 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
759 }
760
bc7f75fa
AK		 761 if ((adapter->hw.mac.type == e1000_ich8lan) &&
762 (adapter->hw.phy.type == e1000_phy_igp_3))
763 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
764
5a86f28f
BA		 765 /* Disable EEE by default until IEEE802.3az spec is finalized */
766 if (adapter->flags2 & FLAG2_HAS_EEE)
767 adapter->hw.dev_spec.ich8lan.eee_disable = true;
768
bc7f75fa
AK		 769 return 0;
770}
771
717d438d 772static DEFINE_MUTEX(nvm_mutex);
717d438d 773
ca15df58
BA		 774/**
775 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
776 * @hw: pointer to the HW structure
777 *
778 * Acquires the mutex for performing NVM operations.
779 **/
780static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
781{
782 mutex_lock(&nvm_mutex);
783
784 return 0;
785}
786
787/**
788 * e1000_release_nvm_ich8lan - Release NVM mutex
789 * @hw: pointer to the HW structure
790 *
791 * Releases the mutex used while performing NVM operations.
792 **/
793static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
794{
795 mutex_unlock(&nvm_mutex);
ca15df58
BA		 796}
797
798static DEFINE_MUTEX(swflag_mutex);
799
bc7f75fa
AK		 800/**
801 * e1000_acquire_swflag_ich8lan - Acquire software control flag
802 * @hw: pointer to the HW structure
803 *
ca15df58
BA		 804 * Acquires the software control flag for performing PHY and select
805 * MAC CSR accesses.
bc7f75fa
AK		 806 **/
807static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
808{
373a88d7
BA		 809 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
810 s32 ret_val = 0;
bc7f75fa 811
ca15df58 812 mutex_lock(&swflag_mutex);
717d438d 813
bc7f75fa
AK		 814 while (timeout) {
815 extcnf_ctrl = er32(EXTCNF_CTRL);
373a88d7
BA		 816 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
817 break;
bc7f75fa 818
373a88d7
BA		 819 mdelay(1);
820 timeout--;
821 }
822
823 if (!timeout) {
3bb99fe2 824 e_dbg("SW/FW/HW has locked the resource for too long.\n");
373a88d7
BA		 825 ret_val = -E1000_ERR_CONFIG;
826 goto out;
827 }
828
53ac5a88 829 timeout = SW_FLAG_TIMEOUT;
373a88d7
BA		 830
831 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
832 ew32(EXTCNF_CTRL, extcnf_ctrl);
833
834 while (timeout) {
835 extcnf_ctrl = er32(EXTCNF_CTRL);
836 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
837 break;
a4f58f54 838
bc7f75fa
AK		 839 mdelay(1);
840 timeout--;
841 }
842
843 if (!timeout) {
3bb99fe2 844 e_dbg("Failed to acquire the semaphore.\n");
2e2e8d53
BA		 845 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
846 ew32(EXTCNF_CTRL, extcnf_ctrl);
373a88d7
BA		 847 ret_val = -E1000_ERR_CONFIG;
848 goto out;
bc7f75fa
AK		 849 }
850
373a88d7
BA		 851out:
852 if (ret_val)
ca15df58 853 mutex_unlock(&swflag_mutex);
373a88d7
BA		 854
855 return ret_val;
bc7f75fa
AK		 856}
857
858/**
859 * e1000_release_swflag_ich8lan - Release software control flag
860 * @hw: pointer to the HW structure
861 *
ca15df58
BA		 862 * Releases the software control flag for performing PHY and select
863 * MAC CSR accesses.
bc7f75fa
AK		 864 **/
865static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
866{
867 u32 extcnf_ctrl;
868
869 extcnf_ctrl = er32(EXTCNF_CTRL);
870 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
871 ew32(EXTCNF_CTRL, extcnf_ctrl);
717d438d 872
ca15df58 873 mutex_unlock(&swflag_mutex);
bc7f75fa
AK		 874}
875
4662e82b
BA		 876/**
877 * e1000_check_mng_mode_ich8lan - Checks management mode
878 * @hw: pointer to the HW structure
879 *
eb7700dc 880 * This checks if the adapter has any manageability enabled.
4662e82b
BA		 881 * This is a function pointer entry point only called by read/write
882 * routines for the PHY and NVM parts.
883 **/
884static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
885{
a708dd88
BA		 886 u32 fwsm;
887
888 fwsm = er32(FWSM);
eb7700dc
BA		 889 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
890 ((fwsm & E1000_FWSM_MODE_MASK) ==
891 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
892}
4662e82b 893
eb7700dc
BA		 894/**
895 * e1000_check_mng_mode_pchlan - Checks management mode
896 * @hw: pointer to the HW structure
897 *
898 * This checks if the adapter has iAMT enabled.
899 * This is a function pointer entry point only called by read/write
900 * routines for the PHY and NVM parts.
901 **/
902static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
903{
904 u32 fwsm;
905
906 fwsm = er32(FWSM);
907 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
908 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
4662e82b
BA		 909}
910
bc7f75fa
AK		 911/**
912 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
913 * @hw: pointer to the HW structure
914 *
915 * Checks if firmware is blocking the reset of the PHY.
916 * This is a function pointer entry point only called by
917 * reset routines.
918 **/
919static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
920{
921 u32 fwsm;
922
923 fwsm = er32(FWSM);
924
925 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
926}
927
8395ae83
BA		 928/**
929 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
930 * @hw: pointer to the HW structure
931 *
932 * Assumes semaphore already acquired.
933 *
934 **/
935static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
936{
937 u16 phy_data;
938 u32 strap = er32(STRAP);
939 s32 ret_val = 0;
940
941 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
942
943 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
944 if (ret_val)
945 goto out;
946
947 phy_data &= ~HV_SMB_ADDR_MASK;
948 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
949 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
950 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
951
952out:
953 return ret_val;
954}
955
f523d211
BA		 956/**
957 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
958 * @hw: pointer to the HW structure
959 *
960 * SW should configure the LCD from the NVM extended configuration region
961 * as a workaround for certain parts.
962 **/
963static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
964{
965 struct e1000_phy_info *phy = &hw->phy;
966 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
8b802a7e 967 s32 ret_val = 0;
f523d211
BA		 968 u16 word_addr, reg_data, reg_addr, phy_page = 0;
969
f523d211
BA		 970 /*
971 * Initialize the PHY from the NVM on ICH platforms. This
972 * is needed due to an issue where the NVM configuration is
973 * not properly autoloaded after power transitions.
974 * Therefore, after each PHY reset, we will load the
975 * configuration data out of the NVM manually.
976 */
3f0c16e8
BA		 977 switch (hw->mac.type) {
978 case e1000_ich8lan:
979 if (phy->type != e1000_phy_igp_3)
980 return ret_val;
981
5f3eed6f
BA		 982 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
983 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
3f0c16e8
BA		 984 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
985 break;
986 }
987 /* Fall-thru */
988 case e1000_pchlan:
d3738bb8 989 case e1000_pch2lan:
8b802a7e 990 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
3f0c16e8
BA		 991 break;
992 default:
993 return ret_val;
994 }
995
996 ret_val = hw->phy.ops.acquire(hw);
997 if (ret_val)
998 return ret_val;
8b802a7e
BA		 999
1000 data = er32(FEXTNVM);
1001 if (!(data & sw_cfg_mask))
1002 goto out;
f523d211 1003
8b802a7e
BA		 1004 /*
1005 * Make sure HW does not configure LCD from PHY
1006 * extended configuration before SW configuration
1007 */
1008 data = er32(EXTCNF_CTRL);
d3738bb8
BA		 1009 if (!(hw->mac.type == e1000_pch2lan)) {
1010 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1011 goto out;
1012 }
8b802a7e
BA		 1013
1014 cnf_size = er32(EXTCNF_SIZE);
1015 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1016 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1017 if (!cnf_size)
1018 goto out;
1019
1020 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1021 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1022
87fb7410
BA		 1023 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1024 (hw->mac.type == e1000_pchlan)) ||
1025 (hw->mac.type == e1000_pch2lan)) {
f523d211 1026 /*
8b802a7e
BA		 1027 * HW configures the SMBus address and LEDs when the
1028 * OEM and LCD Write Enable bits are set in the NVM.
1029 * When both NVM bits are cleared, SW will configure
1030 * them instead.
f523d211 1031 */
8395ae83 1032 ret_val = e1000_write_smbus_addr(hw);
8b802a7e 1033 if (ret_val)
f523d211
BA		 1034 goto out;
1035
8b802a7e
BA		 1036 data = er32(LEDCTL);
1037 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1038 (u16)data);
1039 if (ret_val)
f523d211 1040 goto out;
8b802a7e 1041 }
f523d211 1042
8b802a7e
BA		 1043 /* Configure LCD from extended configuration region. */
1044
1045 /* cnf_base_addr is in DWORD */
1046 word_addr = (u16)(cnf_base_addr << 1);
1047
1048 for (i = 0; i < cnf_size; i++) {
1049 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1050 &reg_data);
1051 if (ret_val)
1052 goto out;
1053
1054 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1055 1, &reg_addr);
1056 if (ret_val)
1057 goto out;
1058
1059 /* Save off the PHY page for future writes. */
1060 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1061 phy_page = reg_data;
1062 continue;
f523d211 1063 }
8b802a7e
BA		 1064
1065 reg_addr &= PHY_REG_MASK;
1066 reg_addr |= phy_page;
1067
1068 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1069 reg_data);
1070 if (ret_val)
1071 goto out;
f523d211
BA		 1072 }
1073
1074out:
94d8186a 1075 hw->phy.ops.release(hw);
f523d211
BA		 1076 return ret_val;
1077}
1078
1d5846b9
BA		 1079/**
1080 * e1000_k1_gig_workaround_hv - K1 Si workaround
1081 * @hw: pointer to the HW structure
1082 * @link: link up bool flag
1083 *
1084 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1085 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1086 * If link is down, the function will restore the default K1 setting located
1087 * in the NVM.
1088 **/
1089static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1090{
1091 s32 ret_val = 0;
1092 u16 status_reg = 0;
1093 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1094
1095 if (hw->mac.type != e1000_pchlan)
1096 goto out;
1097
1098 /* Wrap the whole flow with the sw flag */
94d8186a 1099 ret_val = hw->phy.ops.acquire(hw);
1d5846b9
BA		 1100 if (ret_val)
1101 goto out;
1102
1103 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1104 if (link) {
1105 if (hw->phy.type == e1000_phy_82578) {
94d8186a 1106 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1d5846b9
BA		 1107 &status_reg);
1108 if (ret_val)
1109 goto release;
1110
1111 status_reg &= BM_CS_STATUS_LINK_UP |
1112 BM_CS_STATUS_RESOLVED |
1113 BM_CS_STATUS_SPEED_MASK;
1114
1115 if (status_reg == (BM_CS_STATUS_LINK_UP |
1116 BM_CS_STATUS_RESOLVED |
1117 BM_CS_STATUS_SPEED_1000))
1118 k1_enable = false;
1119 }
1120
1121 if (hw->phy.type == e1000_phy_82577) {
94d8186a 1122 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1d5846b9
BA		 1123 &status_reg);
1124 if (ret_val)
1125 goto release;
1126
1127 status_reg &= HV_M_STATUS_LINK_UP |
1128 HV_M_STATUS_AUTONEG_COMPLETE |
1129 HV_M_STATUS_SPEED_MASK;
1130
1131 if (status_reg == (HV_M_STATUS_LINK_UP |
1132 HV_M_STATUS_AUTONEG_COMPLETE |
1133 HV_M_STATUS_SPEED_1000))
1134 k1_enable = false;
1135 }
1136
1137 /* Link stall fix for link up */
94d8186a 1138 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 1139 0x0100);
1140 if (ret_val)
1141 goto release;
1142
1143 } else {
1144 /* Link stall fix for link down */
94d8186a 1145 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1d5846b9
BA		 1146 0x4100);
1147 if (ret_val)
1148 goto release;
1149 }
1150
1151 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1152
1153release:
94d8186a 1154 hw->phy.ops.release(hw);
1d5846b9
BA		 1155out:
1156 return ret_val;
1157}
1158
1159/**
1160 * e1000_configure_k1_ich8lan - Configure K1 power state
1161 * @hw: pointer to the HW structure
1162 * @enable: K1 state to configure
1163 *
1164 * Configure the K1 power state based on the provided parameter.
1165 * Assumes semaphore already acquired.
1166 *
1167 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1168 **/
bb436b20 1169s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1d5846b9
BA		 1170{
1171 s32 ret_val = 0;
1172 u32 ctrl_reg = 0;
1173 u32 ctrl_ext = 0;
1174 u32 reg = 0;
1175 u16 kmrn_reg = 0;
1176
1177 ret_val = e1000e_read_kmrn_reg_locked(hw,
1178 E1000_KMRNCTRLSTA_K1_CONFIG,
1179 &kmrn_reg);
1180 if (ret_val)
1181 goto out;
1182
1183 if (k1_enable)
1184 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1185 else
1186 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1187
1188 ret_val = e1000e_write_kmrn_reg_locked(hw,
1189 E1000_KMRNCTRLSTA_K1_CONFIG,
1190 kmrn_reg);
1191 if (ret_val)
1192 goto out;
1193
1194 udelay(20);
1195 ctrl_ext = er32(CTRL_EXT);
1196 ctrl_reg = er32(CTRL);
1197
1198 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1199 reg |= E1000_CTRL_FRCSPD;
1200 ew32(CTRL, reg);
1201
1202 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1203 udelay(20);
1204 ew32(CTRL, ctrl_reg);
1205 ew32(CTRL_EXT, ctrl_ext);
1206 udelay(20);
1207
1208out:
1209 return ret_val;
1210}
1211
f523d211
BA		 1212/**
1213 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1214 * @hw: pointer to the HW structure
1215 * @d0_state: boolean if entering d0 or d3 device state
1216 *
1217 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1218 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1219 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1220 **/
1221static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1222{
1223 s32 ret_val = 0;
1224 u32 mac_reg;
1225 u16 oem_reg;
1226
d3738bb8 1227 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
f523d211
BA		 1228 return ret_val;
1229
94d8186a 1230 ret_val = hw->phy.ops.acquire(hw);
f523d211
BA		 1231 if (ret_val)
1232 return ret_val;
1233
d3738bb8
BA		 1234 if (!(hw->mac.type == e1000_pch2lan)) {
1235 mac_reg = er32(EXTCNF_CTRL);
1236 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1237 goto out;
1238 }
f523d211
BA		 1239
1240 mac_reg = er32(FEXTNVM);
1241 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1242 goto out;
1243
1244 mac_reg = er32(PHY_CTRL);
1245
94d8186a 1246 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
f523d211
BA		 1247 if (ret_val)
1248 goto out;
1249
1250 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1251
1252 if (d0_state) {
1253 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1254 oem_reg |= HV_OEM_BITS_GBE_DIS;
1255
1256 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1257 oem_reg |= HV_OEM_BITS_LPLU;
1258 } else {
1259 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1260 oem_reg |= HV_OEM_BITS_GBE_DIS;
1261
1262 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1263 oem_reg |= HV_OEM_BITS_LPLU;
1264 }
1265 /* Restart auto-neg to activate the bits */
818f3331
BA		 1266 if (!e1000_check_reset_block(hw))
1267 oem_reg |= HV_OEM_BITS_RESTART_AN;
94d8186a 1268 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
f523d211
BA		 1269
1270out:
94d8186a 1271 hw->phy.ops.release(hw);
f523d211
BA		 1272
1273 return ret_val;
1274}
1275
1276
fddaa1af
BA		 1277/**
1278 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1279 * @hw: pointer to the HW structure
1280 **/
1281static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1282{
1283 s32 ret_val;
1284 u16 data;
1285
1286 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1287 if (ret_val)
1288 return ret_val;
1289
1290 data |= HV_KMRN_MDIO_SLOW;
1291
1292 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1293
1294 return ret_val;
1295}
1296
a4f58f54
BA		 1297/**
1298 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1299 * done after every PHY reset.
1300 **/
1301static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1302{
1303 s32 ret_val = 0;
baf86c9d 1304 u16 phy_data;
a4f58f54
BA		 1305
1306 if (hw->mac.type != e1000_pchlan)
1307 return ret_val;
1308
fddaa1af
BA		 1309 /* Set MDIO slow mode before any other MDIO access */
1310 if (hw->phy.type == e1000_phy_82577) {
1311 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1312 if (ret_val)
1313 goto out;
1314 }
1315
a4f58f54
BA		 1316 if (((hw->phy.type == e1000_phy_82577) &&
1317 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1318 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1319 /* Disable generation of early preamble */
1320 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1321 if (ret_val)
1322 return ret_val;
1323
1324 /* Preamble tuning for SSC */
1325 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1326 if (ret_val)
1327 return ret_val;
1328 }
1329
1330 if (hw->phy.type == e1000_phy_82578) {
1331 /*
1332 * Return registers to default by doing a soft reset then
1333 * writing 0x3140 to the control register.
1334 */
1335 if (hw->phy.revision < 2) {
1336 e1000e_phy_sw_reset(hw);
1337 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1338 }
1339 }
1340
1341 /* Select page 0 */
94d8186a 1342 ret_val = hw->phy.ops.acquire(hw);
a4f58f54
BA		 1343 if (ret_val)
1344 return ret_val;
1d5846b9 1345
a4f58f54 1346 hw->phy.addr = 1;
1d5846b9 1347 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
baf86c9d 1348 hw->phy.ops.release(hw);
1d5846b9
BA		 1349 if (ret_val)
1350 goto out;
a4f58f54 1351
1d5846b9
BA		 1352 /*
1353 * Configure the K1 Si workaround during phy reset assuming there is
1354 * link so that it disables K1 if link is in 1Gbps.
1355 */
1356 ret_val = e1000_k1_gig_workaround_hv(hw, true);
baf86c9d
BA		 1357 if (ret_val)
1358 goto out;
1d5846b9 1359
baf86c9d
BA		 1360 /* Workaround for link disconnects on a busy hub in half duplex */
1361 ret_val = hw->phy.ops.acquire(hw);
1362 if (ret_val)
1363 goto out;
1364 ret_val = hw->phy.ops.read_reg_locked(hw,
1365 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1366 &phy_data);
1367 if (ret_val)
1368 goto release;
1369 ret_val = hw->phy.ops.write_reg_locked(hw,
1370 PHY_REG(BM_PORT_CTRL_PAGE, 17),
1371 phy_data & 0x00FF);
1372release:
1373 hw->phy.ops.release(hw);
1d5846b9 1374out:
a4f58f54
BA		 1375 return ret_val;
1376}
1377
d3738bb8
BA		 1378/**
1379 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1380 * @hw: pointer to the HW structure
1381 **/
1382void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1383{
1384 u32 mac_reg;
1385 u16 i;
1386
1387 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1388 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1389 mac_reg = er32(RAL(i));
1390 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1391 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1392 mac_reg = er32(RAH(i));
1393 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1394 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1395 }
1396}
1397
1398static u32 e1000_calc_rx_da_crc(u8 mac[])
1399{
1400 u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */
1401 u32 i, j, mask, crc;
1402
1403 crc = 0xffffffff;
1404 for (i = 0; i < 6; i++) {
1405 crc = crc ^ mac[i];
1406 for (j = 8; j > 0; j--) {
1407 mask = (crc & 1) * (-1);
1408 crc = (crc >> 1) ^ (poly & mask);
1409 }
1410 }
1411 return ~crc;
1412}
1413
1414/**
1415 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1416 * with 82579 PHY
1417 * @hw: pointer to the HW structure
1418 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1419 **/
1420s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1421{
1422 s32 ret_val = 0;
1423 u16 phy_reg, data;
1424 u32 mac_reg;
1425 u16 i;
1426
1427 if (hw->mac.type != e1000_pch2lan)
1428 goto out;
1429
1430 /* disable Rx path while enabling/disabling workaround */
1431 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1432 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1433 if (ret_val)
1434 goto out;
1435
1436 if (enable) {
1437 /*
1438 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1439 * SHRAL/H) and initial CRC values to the MAC
1440 */
1441 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1442 u8 mac_addr[ETH_ALEN] = {0};
1443 u32 addr_high, addr_low;
1444
1445 addr_high = er32(RAH(i));
1446 if (!(addr_high & E1000_RAH_AV))
1447 continue;
1448 addr_low = er32(RAL(i));
1449 mac_addr[0] = (addr_low & 0xFF);
1450 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1451 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1452 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1453 mac_addr[4] = (addr_high & 0xFF);
1454 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1455
1456 ew32(PCH_RAICC(i),
1457 e1000_calc_rx_da_crc(mac_addr));
1458 }
1459
1460 /* Write Rx addresses to the PHY */
1461 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1462
1463 /* Enable jumbo frame workaround in the MAC */
1464 mac_reg = er32(FFLT_DBG);
1465 mac_reg &= ~(1 << 14);
1466 mac_reg |= (7 << 15);
1467 ew32(FFLT_DBG, mac_reg);
1468
1469 mac_reg = er32(RCTL);
1470 mac_reg |= E1000_RCTL_SECRC;
1471 ew32(RCTL, mac_reg);
1472
1473 ret_val = e1000e_read_kmrn_reg(hw,
1474 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1475 &data);
1476 if (ret_val)
1477 goto out;
1478 ret_val = e1000e_write_kmrn_reg(hw,
1479 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1480 data | (1 << 0));
1481 if (ret_val)
1482 goto out;
1483 ret_val = e1000e_read_kmrn_reg(hw,
1484 E1000_KMRNCTRLSTA_HD_CTRL,
1485 &data);
1486 if (ret_val)
1487 goto out;
1488 data &= ~(0xF << 8);
1489 data |= (0xB << 8);
1490 ret_val = e1000e_write_kmrn_reg(hw,
1491 E1000_KMRNCTRLSTA_HD_CTRL,
1492 data);
1493 if (ret_val)
1494 goto out;
1495
1496 /* Enable jumbo frame workaround in the PHY */
d3738bb8
BA		 1497 e1e_rphy(hw, PHY_REG(769, 23), &data);
1498 data &= ~(0x7F << 5);
1499 data |= (0x37 << 5);
1500 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1501 if (ret_val)
1502 goto out;
1503 e1e_rphy(hw, PHY_REG(769, 16), &data);
1504 data &= ~(1 << 13);
d3738bb8
BA		 1505 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1506 if (ret_val)
1507 goto out;
1508 e1e_rphy(hw, PHY_REG(776, 20), &data);
1509 data &= ~(0x3FF << 2);
1510 data |= (0x1A << 2);
1511 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1512 if (ret_val)
1513 goto out;
1514 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1515 if (ret_val)
1516 goto out;
1517 e1e_rphy(hw, HV_PM_CTRL, &data);
1518 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1519 if (ret_val)
1520 goto out;
1521 } else {
1522 /* Write MAC register values back to h/w defaults */
1523 mac_reg = er32(FFLT_DBG);
1524 mac_reg &= ~(0xF << 14);
1525 ew32(FFLT_DBG, mac_reg);
1526
1527 mac_reg = er32(RCTL);
1528 mac_reg &= ~E1000_RCTL_SECRC;
a1ce6473 1529 ew32(RCTL, mac_reg);
d3738bb8
BA		 1530
1531 ret_val = e1000e_read_kmrn_reg(hw,
1532 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1533 &data);
1534 if (ret_val)
1535 goto out;
1536 ret_val = e1000e_write_kmrn_reg(hw,
1537 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1538 data & ~(1 << 0));
1539 if (ret_val)
1540 goto out;
1541 ret_val = e1000e_read_kmrn_reg(hw,
1542 E1000_KMRNCTRLSTA_HD_CTRL,
1543 &data);
1544 if (ret_val)
1545 goto out;
1546 data &= ~(0xF << 8);
1547 data |= (0xB << 8);
1548 ret_val = e1000e_write_kmrn_reg(hw,
1549 E1000_KMRNCTRLSTA_HD_CTRL,
1550 data);
1551 if (ret_val)
1552 goto out;
1553
1554 /* Write PHY register values back to h/w defaults */
d3738bb8
BA		 1555 e1e_rphy(hw, PHY_REG(769, 23), &data);
1556 data &= ~(0x7F << 5);
1557 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1558 if (ret_val)
1559 goto out;
1560 e1e_rphy(hw, PHY_REG(769, 16), &data);
d3738bb8
BA		 1561 data |= (1 << 13);
1562 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1563 if (ret_val)
1564 goto out;
1565 e1e_rphy(hw, PHY_REG(776, 20), &data);
1566 data &= ~(0x3FF << 2);
1567 data |= (0x8 << 2);
1568 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1569 if (ret_val)
1570 goto out;
1571 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1572 if (ret_val)
1573 goto out;
1574 e1e_rphy(hw, HV_PM_CTRL, &data);
1575 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1576 if (ret_val)
1577 goto out;
1578 }
1579
1580 /* re-enable Rx path after enabling/disabling workaround */
1581 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1582
1583out:
1584 return ret_val;
1585}
1586
1587/**
1588 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1589 * done after every PHY reset.
1590 **/
1591static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1592{
1593 s32 ret_val = 0;
1594
1595 if (hw->mac.type != e1000_pch2lan)
1596 goto out;
1597
1598 /* Set MDIO slow mode before any other MDIO access */
1599 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1600
1601out:
1602 return ret_val;
1603}
1604
831bd2e6
BA		 1605/**
1606 * e1000_k1_gig_workaround_lv - K1 Si workaround
1607 * @hw: pointer to the HW structure
1608 *
1609 * Workaround to set the K1 beacon duration for 82579 parts
1610 **/
1611static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1612{
1613 s32 ret_val = 0;
1614 u16 status_reg = 0;
1615 u32 mac_reg;
1616
1617 if (hw->mac.type != e1000_pch2lan)
1618 goto out;
1619
1620 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1621 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1622 if (ret_val)
1623 goto out;
1624
1625 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1626 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1627 mac_reg = er32(FEXTNVM4);
1628 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1629
1630 if (status_reg & HV_M_STATUS_SPEED_1000)
1631 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1632 else
1633 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1634
1635 ew32(FEXTNVM4, mac_reg);
1636 }
1637
1638out:
1639 return ret_val;
1640}
1641
605c82ba
BA		 1642/**
1643 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1644 * @hw: pointer to the HW structure
1645 * @gate: boolean set to true to gate, false to ungate
1646 *
1647 * Gate/ungate the automatic PHY configuration via hardware; perform
1648 * the configuration via software instead.
1649 **/
1650static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1651{
1652 u32 extcnf_ctrl;
1653
1654 if (hw->mac.type != e1000_pch2lan)
1655 return;
1656
1657 extcnf_ctrl = er32(EXTCNF_CTRL);
1658
1659 if (gate)
1660 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1661 else
1662 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1663
1664 ew32(EXTCNF_CTRL, extcnf_ctrl);
1665 return;
1666}
1667
fc0c7760
BA		 1668/**
1669 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1670 * @hw: pointer to the HW structure
1671 *
1672 * Check the appropriate indication the MAC has finished configuring the
1673 * PHY after a software reset.
1674 **/
1675static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1676{
1677 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1678
1679 /* Wait for basic configuration completes before proceeding */
1680 do {
1681 data = er32(STATUS);
1682 data &= E1000_STATUS_LAN_INIT_DONE;
1683 udelay(100);
1684 } while ((!data) && --loop);
1685
1686 /*
1687 * If basic configuration is incomplete before the above loop
1688 * count reaches 0, loading the configuration from NVM will
1689 * leave the PHY in a bad state possibly resulting in no link.
1690 */
1691 if (loop == 0)
3bb99fe2 1692 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
fc0c7760
BA		 1693
1694 /* Clear the Init Done bit for the next init event */
1695 data = er32(STATUS);
1696 data &= ~E1000_STATUS_LAN_INIT_DONE;
1697 ew32(STATUS, data);
1698}
1699
bc7f75fa 1700/**
e98cac44 1701 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
bc7f75fa 1702 * @hw: pointer to the HW structure
bc7f75fa 1703 **/
e98cac44 1704static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
bc7f75fa 1705{
f523d211
BA		 1706 s32 ret_val = 0;
1707 u16 reg;
bc7f75fa 1708
e98cac44
BA		 1709 if (e1000_check_reset_block(hw))
1710 goto out;
fc0c7760 1711
5f3eed6f
BA		 1712 /* Allow time for h/w to get to quiescent state after reset */
1713 msleep(10);
1714
fddaa1af 1715 /* Perform any necessary post-reset workarounds */
e98cac44
BA		 1716 switch (hw->mac.type) {
1717 case e1000_pchlan:
a4f58f54
BA		 1718 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1719 if (ret_val)
e98cac44
BA		 1720 goto out;
1721 break;
d3738bb8
BA		 1722 case e1000_pch2lan:
1723 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1724 if (ret_val)
1725 goto out;
1726 break;
e98cac44
BA		 1727 default:
1728 break;
a4f58f54
BA		 1729 }
1730
db2932ec 1731 /* Dummy read to clear the phy wakeup bit after lcd reset */
d3738bb8 1732 if (hw->mac.type >= e1000_pchlan)
db2932ec
BA		 1733 e1e_rphy(hw, BM_WUC, &reg);
1734
f523d211
BA		 1735 /* Configure the LCD with the extended configuration region in NVM */
1736 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1737 if (ret_val)
1738 goto out;
bc7f75fa 1739
f523d211 1740 /* Configure the LCD with the OEM bits in NVM */
e98cac44 1741 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
bc7f75fa 1742
605c82ba
BA		 1743 /* Ungate automatic PHY configuration on non-managed 82579 */
1744 if ((hw->mac.type == e1000_pch2lan) &&
1745 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1746 msleep(10);
1747 e1000_gate_hw_phy_config_ich8lan(hw, false);
1748 }
1749
f523d211 1750out:
e98cac44
BA		 1751 return ret_val;
1752}
1753
1754/**
1755 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1756 * @hw: pointer to the HW structure
1757 *
1758 * Resets the PHY
1759 * This is a function pointer entry point called by drivers
1760 * or other shared routines.
1761 **/
1762static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1763{
1764 s32 ret_val = 0;
1765
605c82ba
BA		 1766 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1767 if ((hw->mac.type == e1000_pch2lan) &&
1768 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1769 e1000_gate_hw_phy_config_ich8lan(hw, true);
1770
e98cac44
BA		 1771 ret_val = e1000e_phy_hw_reset_generic(hw);
1772 if (ret_val)
1773 goto out;
1774
1775 ret_val = e1000_post_phy_reset_ich8lan(hw);
1776
1777out:
1778 return ret_val;
bc7f75fa
AK		 1779}
1780
fa2ce13c
BA		 1781/**
1782 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1783 * @hw: pointer to the HW structure
1784 * @active: true to enable LPLU, false to disable
1785 *
1786 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1787 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1788 * the phy speed. This function will manually set the LPLU bit and restart
1789 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1790 * since it configures the same bit.
1791 **/
1792static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1793{
1794 s32 ret_val = 0;
1795 u16 oem_reg;
1796
1797 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1798 if (ret_val)
1799 goto out;
1800
1801 if (active)
1802 oem_reg |= HV_OEM_BITS_LPLU;
1803 else
1804 oem_reg &= ~HV_OEM_BITS_LPLU;
1805
1806 oem_reg |= HV_OEM_BITS_RESTART_AN;
1807 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1808
1809out:
1810 return ret_val;
1811}
1812
bc7f75fa
AK		 1813/**
1814 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1815 * @hw: pointer to the HW structure
564ea9bb 1816 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1817 *
1818 * Sets the LPLU D0 state according to the active flag. When
1819 * activating LPLU this function also disables smart speed
1820 * and vice versa. LPLU will not be activated unless the
1821 * device autonegotiation advertisement meets standards of
1822 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1823 * This is a function pointer entry point only called by
1824 * PHY setup routines.
1825 **/
1826static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1827{
1828 struct e1000_phy_info *phy = &hw->phy;
1829 u32 phy_ctrl;
1830 s32 ret_val = 0;
1831 u16 data;
1832
97ac8cae 1833 if (phy->type == e1000_phy_ife)
bc7f75fa
AK		 1834 return ret_val;
1835
1836 phy_ctrl = er32(PHY_CTRL);
1837
1838 if (active) {
1839 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1840 ew32(PHY_CTRL, phy_ctrl);
1841
60f1292f
BA		 1842 if (phy->type != e1000_phy_igp_3)
1843 return 0;
1844
ad68076e
BA		 1845 /*
1846 * Call gig speed drop workaround on LPLU before accessing
1847 * any PHY registers
1848 */
60f1292f 1849 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1850 e1000e_gig_downshift_workaround_ich8lan(hw);
1851
1852 /* When LPLU is enabled, we should disable SmartSpeed */
1853 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1854 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1855 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1856 if (ret_val)
1857 return ret_val;
1858 } else {
1859 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1860 ew32(PHY_CTRL, phy_ctrl);
1861
60f1292f
BA		 1862 if (phy->type != e1000_phy_igp_3)
1863 return 0;
1864
ad68076e
BA		 1865 /*
1866 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1867 * during Dx states where the power conservation is most
1868 * important. During driver activity we should enable
ad68076e
BA		 1869 * SmartSpeed, so performance is maintained.
1870 */
bc7f75fa
AK		 1871 if (phy->smart_speed == e1000_smart_speed_on) {
1872 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1873 &data);
bc7f75fa
AK		 1874 if (ret_val)
1875 return ret_val;
1876
1877 data |= IGP01E1000_PSCFR_SMART_SPEED;
1878 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1879 data);
bc7f75fa
AK		 1880 if (ret_val)
1881 return ret_val;
1882 } else if (phy->smart_speed == e1000_smart_speed_off) {
1883 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1884 &data);
bc7f75fa
AK		 1885 if (ret_val)
1886 return ret_val;
1887
1888 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1889 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
ad68076e 1890 data);
bc7f75fa
AK		 1891 if (ret_val)
1892 return ret_val;
1893 }
1894 }
1895
1896 return 0;
1897}
1898
1899/**
1900 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1901 * @hw: pointer to the HW structure
564ea9bb 1902 * @active: true to enable LPLU, false to disable
bc7f75fa
AK		 1903 *
1904 * Sets the LPLU D3 state according to the active flag. When
1905 * activating LPLU this function also disables smart speed
1906 * and vice versa. LPLU will not be activated unless the
1907 * device autonegotiation advertisement meets standards of
1908 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1909 * This is a function pointer entry point only called by
1910 * PHY setup routines.
1911 **/
1912static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1913{
1914 struct e1000_phy_info *phy = &hw->phy;
1915 u32 phy_ctrl;
1916 s32 ret_val;
1917 u16 data;
1918
1919 phy_ctrl = er32(PHY_CTRL);
1920
1921 if (!active) {
1922 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1923 ew32(PHY_CTRL, phy_ctrl);
60f1292f
BA		 1924
1925 if (phy->type != e1000_phy_igp_3)
1926 return 0;
1927
ad68076e
BA		 1928 /*
1929 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
bc7f75fa
AK		 1930 * during Dx states where the power conservation is most
1931 * important. During driver activity we should enable
ad68076e
BA		 1932 * SmartSpeed, so performance is maintained.
1933 */
bc7f75fa 1934 if (phy->smart_speed == e1000_smart_speed_on) {
ad68076e
BA		 1935 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1936 &data);
bc7f75fa
AK		 1937 if (ret_val)
1938 return ret_val;
1939
1940 data |= IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1941 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1942 data);
bc7f75fa
AK		 1943 if (ret_val)
1944 return ret_val;
1945 } else if (phy->smart_speed == e1000_smart_speed_off) {
ad68076e
BA		 1946 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1947 &data);
bc7f75fa
AK		 1948 if (ret_val)
1949 return ret_val;
1950
1951 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e
BA		 1952 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1953 data);
bc7f75fa
AK		 1954 if (ret_val)
1955 return ret_val;
1956 }
1957 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1958 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1959 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1960 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1961 ew32(PHY_CTRL, phy_ctrl);
1962
60f1292f
BA		 1963 if (phy->type != e1000_phy_igp_3)
1964 return 0;
1965
ad68076e
BA		 1966 /*
1967 * Call gig speed drop workaround on LPLU before accessing
1968 * any PHY registers
1969 */
60f1292f 1970 if (hw->mac.type == e1000_ich8lan)
bc7f75fa
AK		 1971 e1000e_gig_downshift_workaround_ich8lan(hw);
1972
1973 /* When LPLU is enabled, we should disable SmartSpeed */
ad68076e 1974 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
bc7f75fa
AK		 1975 if (ret_val)
1976 return ret_val;
1977
1978 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
ad68076e 1979 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
bc7f75fa
AK		 1980 }
1981
1982 return 0;
1983}
1984
f4187b56
BA		 1985/**
1986 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1987 * @hw: pointer to the HW structure
1988 * @bank: pointer to the variable that returns the active bank
1989 *
1990 * Reads signature byte from the NVM using the flash access registers.
e243455d 1991 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
f4187b56
BA		 1992 **/
1993static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1994{
e243455d 1995 u32 eecd;
f4187b56 1996 struct e1000_nvm_info *nvm = &hw->nvm;
f4187b56
BA		 1997 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1998 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
e243455d
BA		 1999 u8 sig_byte = 0;
2000 s32 ret_val = 0;
f4187b56 2001
e243455d
BA		 2002 switch (hw->mac.type) {
2003 case e1000_ich8lan:
2004 case e1000_ich9lan:
2005 eecd = er32(EECD);
2006 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2007 E1000_EECD_SEC1VAL_VALID_MASK) {
2008 if (eecd & E1000_EECD_SEC1VAL)
2009 *bank = 1;
2010 else
2011 *bank = 0;
2012
2013 return 0;
2014 }
3bb99fe2 2015 e_dbg("Unable to determine valid NVM bank via EEC - "
e243455d
BA		 2016 "reading flash signature\n");
2017 /* fall-thru */
2018 default:
2019 /* set bank to 0 in case flash read fails */
2020 *bank = 0;
2021
2022 /* Check bank 0 */
2023 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2024 &sig_byte);
2025 if (ret_val)
2026 return ret_val;
2027 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2028 E1000_ICH_NVM_SIG_VALUE) {
f4187b56 2029 *bank = 0;
e243455d
BA		 2030 return 0;
2031 }
f4187b56 2032
e243455d
BA		 2033 /* Check bank 1 */
2034 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2035 bank1_offset,
2036 &sig_byte);
2037 if (ret_val)
2038 return ret_val;
2039 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2040 E1000_ICH_NVM_SIG_VALUE) {
2041 *bank = 1;
2042 return 0;
f4187b56 2043 }
e243455d 2044
3bb99fe2 2045 e_dbg("ERROR: No valid NVM bank present\n");
e243455d 2046 return -E1000_ERR_NVM;
f4187b56
BA		 2047 }
2048
2049 return 0;
2050}
2051
bc7f75fa
AK		 2052/**
2053 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2054 * @hw: pointer to the HW structure
2055 * @offset: The offset (in bytes) of the word(s) to read.
2056 * @words: Size of data to read in words
2057 * @data: Pointer to the word(s) to read at offset.
2058 *
2059 * Reads a word(s) from the NVM using the flash access registers.
2060 **/
2061static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2062 u16 *data)
2063{
2064 struct e1000_nvm_info *nvm = &hw->nvm;
2065 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2066 u32 act_offset;
148675a7 2067 s32 ret_val = 0;
f4187b56 2068 u32 bank = 0;
bc7f75fa
AK		 2069 u16 i, word;
2070
2071 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2072 (words == 0)) {
3bb99fe2 2073 e_dbg("nvm parameter(s) out of bounds\n");
ca15df58
BA		 2074 ret_val = -E1000_ERR_NVM;
2075 goto out;
bc7f75fa
AK		 2076 }
2077
94d8186a 2078 nvm->ops.acquire(hw);
bc7f75fa 2079
f4187b56 2080 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
148675a7 2081 if (ret_val) {
3bb99fe2 2082 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7
BA		 2083 bank = 0;
2084 }
f4187b56
BA		 2085
2086 act_offset = (bank) ? nvm->flash_bank_size : 0;
bc7f75fa
AK		 2087 act_offset += offset;
2088
148675a7 2089 ret_val = 0;
bc7f75fa
AK		 2090 for (i = 0; i < words; i++) {
2091 if ((dev_spec->shadow_ram) &&
2092 (dev_spec->shadow_ram[offset+i].modified)) {
2093 data[i] = dev_spec->shadow_ram[offset+i].value;
2094 } else {
2095 ret_val = e1000_read_flash_word_ich8lan(hw,
2096 act_offset + i,
2097 &word);
2098 if (ret_val)
2099 break;
2100 data[i] = word;
2101 }
2102 }
2103
94d8186a 2104 nvm->ops.release(hw);
bc7f75fa 2105
e243455d
BA		 2106out:
2107 if (ret_val)
3bb99fe2 2108 e_dbg("NVM read error: %d\n", ret_val);
e243455d 2109
bc7f75fa
AK		 2110 return ret_val;
2111}
2112
2113/**
2114 * e1000_flash_cycle_init_ich8lan - Initialize flash
2115 * @hw: pointer to the HW structure
2116 *
2117 * This function does initial flash setup so that a new read/write/erase cycle
2118 * can be started.
2119 **/
2120static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2121{
2122 union ich8_hws_flash_status hsfsts;
2123 s32 ret_val = -E1000_ERR_NVM;
2124 s32 i = 0;
2125
2126 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2127
2128 /* Check if the flash descriptor is valid */
2129 if (hsfsts.hsf_status.fldesvalid == 0) {
3bb99fe2 2130 e_dbg("Flash descriptor invalid. "
2c73e1fe 2131 "SW Sequencing must be used.\n");
bc7f75fa
AK		 2132 return -E1000_ERR_NVM;
2133 }
2134
2135 /* Clear FCERR and DAEL in hw status by writing 1 */
2136 hsfsts.hsf_status.flcerr = 1;
2137 hsfsts.hsf_status.dael = 1;
2138
2139 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2140
ad68076e
BA		 2141 /*
2142 * Either we should have a hardware SPI cycle in progress
bc7f75fa
AK		 2143 * bit to check against, in order to start a new cycle or
2144 * FDONE bit should be changed in the hardware so that it
489815ce 2145 * is 1 after hardware reset, which can then be used as an
bc7f75fa
AK		 2146 * indication whether a cycle is in progress or has been
2147 * completed.
2148 */
2149
2150 if (hsfsts.hsf_status.flcinprog == 0) {
ad68076e
BA		 2151 /*
2152 * There is no cycle running at present,
5ff5b664 2153 * so we can start a cycle.
ad68076e
BA		 2154 * Begin by setting Flash Cycle Done.
2155 */
bc7f75fa
AK		 2156 hsfsts.hsf_status.flcdone = 1;
2157 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2158 ret_val = 0;
2159 } else {
ad68076e 2160 /*
5ff5b664 2161 * Otherwise poll for sometime so the current
ad68076e
BA		 2162 * cycle has a chance to end before giving up.
2163 */
bc7f75fa
AK		 2164 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2165 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2166 if (hsfsts.hsf_status.flcinprog == 0) {
2167 ret_val = 0;
2168 break;
2169 }
2170 udelay(1);
2171 }
2172 if (ret_val == 0) {
ad68076e
BA		 2173 /*
2174 * Successful in waiting for previous cycle to timeout,
2175 * now set the Flash Cycle Done.
2176 */
bc7f75fa
AK		 2177 hsfsts.hsf_status.flcdone = 1;
2178 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2179 } else {
2c73e1fe 2180 e_dbg("Flash controller busy, cannot get access\n");
bc7f75fa
AK		 2181 }
2182 }
2183
2184 return ret_val;
2185}
2186
2187/**
2188 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2189 * @hw: pointer to the HW structure
2190 * @timeout: maximum time to wait for completion
2191 *
2192 * This function starts a flash cycle and waits for its completion.
2193 **/
2194static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2195{
2196 union ich8_hws_flash_ctrl hsflctl;
2197 union ich8_hws_flash_status hsfsts;
2198 s32 ret_val = -E1000_ERR_NVM;
2199 u32 i = 0;
2200
2201 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2202 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2203 hsflctl.hsf_ctrl.flcgo = 1;
2204 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2205
2206 /* wait till FDONE bit is set to 1 */
2207 do {
2208 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2209 if (hsfsts.hsf_status.flcdone == 1)
2210 break;
2211 udelay(1);
2212 } while (i++ < timeout);
2213
2214 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2215 return 0;
2216
2217 return ret_val;
2218}
2219
2220/**
2221 * e1000_read_flash_word_ich8lan - Read word from flash
2222 * @hw: pointer to the HW structure
2223 * @offset: offset to data location
2224 * @data: pointer to the location for storing the data
2225 *
2226 * Reads the flash word at offset into data. Offset is converted
2227 * to bytes before read.
2228 **/
2229static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2230 u16 *data)
2231{
2232 /* Must convert offset into bytes. */
2233 offset <<= 1;
2234
2235 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2236}
2237
f4187b56
BA		 2238/**
2239 * e1000_read_flash_byte_ich8lan - Read byte from flash
2240 * @hw: pointer to the HW structure
2241 * @offset: The offset of the byte to read.
2242 * @data: Pointer to a byte to store the value read.
2243 *
2244 * Reads a single byte from the NVM using the flash access registers.
2245 **/
2246static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2247 u8 *data)
2248{
2249 s32 ret_val;
2250 u16 word = 0;
2251
2252 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2253 if (ret_val)
2254 return ret_val;
2255
2256 *data = (u8)word;
2257
2258 return 0;
2259}
2260
bc7f75fa
AK		 2261/**
2262 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2263 * @hw: pointer to the HW structure
2264 * @offset: The offset (in bytes) of the byte or word to read.
2265 * @size: Size of data to read, 1=byte 2=word
2266 * @data: Pointer to the word to store the value read.
2267 *
2268 * Reads a byte or word from the NVM using the flash access registers.
2269 **/
2270static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2271 u8 size, u16 *data)
2272{
2273 union ich8_hws_flash_status hsfsts;
2274 union ich8_hws_flash_ctrl hsflctl;
2275 u32 flash_linear_addr;
2276 u32 flash_data = 0;
2277 s32 ret_val = -E1000_ERR_NVM;
2278 u8 count = 0;
2279
2280 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2281 return -E1000_ERR_NVM;
2282
2283 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2284 hw->nvm.flash_base_addr;
2285
2286 do {
2287 udelay(1);
2288 /* Steps */
2289 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2290 if (ret_val != 0)
2291 break;
2292
2293 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2294 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2295 hsflctl.hsf_ctrl.fldbcount = size - 1;
2296 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2297 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2298
2299 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2300
2301 ret_val = e1000_flash_cycle_ich8lan(hw,
2302 ICH_FLASH_READ_COMMAND_TIMEOUT);
2303
ad68076e
BA		 2304 /*
2305 * Check if FCERR is set to 1, if set to 1, clear it
bc7f75fa
AK		 2306 * and try the whole sequence a few more times, else
2307 * read in (shift in) the Flash Data0, the order is
ad68076e
BA		 2308 * least significant byte first msb to lsb
2309 */
bc7f75fa
AK		 2310 if (ret_val == 0) {
2311 flash_data = er32flash(ICH_FLASH_FDATA0);
b1cdfead 2312 if (size == 1)
bc7f75fa 2313 *data = (u8)(flash_data & 0x000000FF);
b1cdfead 2314 else if (size == 2)
bc7f75fa 2315 *data = (u16)(flash_data & 0x0000FFFF);
bc7f75fa
AK		 2316 break;
2317 } else {
ad68076e
BA		 2318 /*
2319 * If we've gotten here, then things are probably
bc7f75fa
AK		 2320 * completely hosed, but if the error condition is
2321 * detected, it won't hurt to give it another try...
2322 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2323 */
2324 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2325 if (hsfsts.hsf_status.flcerr == 1) {
2326 /* Repeat for some time before giving up. */
2327 continue;
2328 } else if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2329 e_dbg("Timeout error - flash cycle "
2c73e1fe 2330 "did not complete.\n");
bc7f75fa
AK		 2331 break;
2332 }
2333 }
2334 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2335
2336 return ret_val;
2337}
2338
2339/**
2340 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2341 * @hw: pointer to the HW structure
2342 * @offset: The offset (in bytes) of the word(s) to write.
2343 * @words: Size of data to write in words
2344 * @data: Pointer to the word(s) to write at offset.
2345 *
2346 * Writes a byte or word to the NVM using the flash access registers.
2347 **/
2348static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2349 u16 *data)
2350{
2351 struct e1000_nvm_info *nvm = &hw->nvm;
2352 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
bc7f75fa
AK		 2353 u16 i;
2354
2355 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2356 (words == 0)) {
3bb99fe2 2357 e_dbg("nvm parameter(s) out of bounds\n");
bc7f75fa
AK		 2358 return -E1000_ERR_NVM;
2359 }
2360
94d8186a 2361 nvm->ops.acquire(hw);
ca15df58 2362
bc7f75fa 2363 for (i = 0; i < words; i++) {
564ea9bb 2364 dev_spec->shadow_ram[offset+i].modified = true;
bc7f75fa
AK		 2365 dev_spec->shadow_ram[offset+i].value = data[i];
2366 }
2367
94d8186a 2368 nvm->ops.release(hw);
ca15df58 2369
bc7f75fa
AK		 2370 return 0;
2371}
2372
2373/**
2374 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2375 * @hw: pointer to the HW structure
2376 *
2377 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2378 * which writes the checksum to the shadow ram. The changes in the shadow
2379 * ram are then committed to the EEPROM by processing each bank at a time
2380 * checking for the modified bit and writing only the pending changes.
489815ce 2381 * After a successful commit, the shadow ram is cleared and is ready for
bc7f75fa
AK		 2382 * future writes.
2383 **/
2384static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2385{
2386 struct e1000_nvm_info *nvm = &hw->nvm;
2387 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
f4187b56 2388 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
bc7f75fa
AK		 2389 s32 ret_val;
2390 u16 data;
2391
2392 ret_val = e1000e_update_nvm_checksum_generic(hw);
2393 if (ret_val)
e243455d 2394 goto out;
bc7f75fa
AK		 2395
2396 if (nvm->type != e1000_nvm_flash_sw)
e243455d 2397 goto out;
bc7f75fa 2398
94d8186a 2399 nvm->ops.acquire(hw);
bc7f75fa 2400
ad68076e
BA		 2401 /*
2402 * We're writing to the opposite bank so if we're on bank 1,
bc7f75fa 2403 * write to bank 0 etc. We also need to erase the segment that
ad68076e
BA		 2404 * is going to be written
2405 */
f4187b56 2406 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
e243455d 2407 if (ret_val) {
3bb99fe2 2408 e_dbg("Could not detect valid bank, assuming bank 0\n");
148675a7 2409 bank = 0;
e243455d 2410 }
f4187b56
BA		 2411
2412 if (bank == 0) {
bc7f75fa
AK		 2413 new_bank_offset = nvm->flash_bank_size;
2414 old_bank_offset = 0;
e243455d 2415 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
9c5e209d
BA		 2416 if (ret_val)
2417 goto release;
bc7f75fa
AK		 2418 } else {
2419 old_bank_offset = nvm->flash_bank_size;
2420 new_bank_offset = 0;
e243455d 2421 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
9c5e209d
BA		 2422 if (ret_val)
2423 goto release;
bc7f75fa
AK		 2424 }
2425
2426 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
ad68076e
BA		 2427 /*
2428 * Determine whether to write the value stored
bc7f75fa 2429 * in the other NVM bank or a modified value stored
ad68076e
BA		 2430 * in the shadow RAM
2431 */
bc7f75fa
AK		 2432 if (dev_spec->shadow_ram[i].modified) {
2433 data = dev_spec->shadow_ram[i].value;
2434 } else {
e243455d
BA		 2435 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2436 old_bank_offset,
2437 &data);
2438 if (ret_val)
2439 break;
bc7f75fa
AK		 2440 }
2441
ad68076e
BA		 2442 /*
2443 * If the word is 0x13, then make sure the signature bits
bc7f75fa
AK		 2444 * (15:14) are 11b until the commit has completed.
2445 * This will allow us to write 10b which indicates the
2446 * signature is valid. We want to do this after the write
2447 * has completed so that we don't mark the segment valid
ad68076e
BA		 2448 * while the write is still in progress
2449 */
bc7f75fa
AK		 2450 if (i == E1000_ICH_NVM_SIG_WORD)
2451 data |= E1000_ICH_NVM_SIG_MASK;
2452
2453 /* Convert offset to bytes. */
2454 act_offset = (i + new_bank_offset) << 1;
2455
2456 udelay(100);
2457 /* Write the bytes to the new bank. */
2458 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2459 act_offset,
2460 (u8)data);
2461 if (ret_val)
2462 break;
2463
2464 udelay(100);
2465 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2466 act_offset + 1,
2467 (u8)(data >> 8));
2468 if (ret_val)
2469 break;
2470 }
2471
ad68076e
BA		 2472 /*
2473 * Don't bother writing the segment valid bits if sector
2474 * programming failed.
2475 */
bc7f75fa 2476 if (ret_val) {
4a770358 2477 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3bb99fe2 2478 e_dbg("Flash commit failed.\n");
9c5e209d 2479 goto release;
bc7f75fa
AK		 2480 }
2481
ad68076e
BA		 2482 /*
2483 * Finally validate the new segment by setting bit 15:14
bc7f75fa
AK		 2484 * to 10b in word 0x13 , this can be done without an
2485 * erase as well since these bits are 11 to start with
ad68076e
BA		 2486 * and we need to change bit 14 to 0b
2487 */
bc7f75fa 2488 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
e243455d 2489 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
9c5e209d
BA		 2490 if (ret_val)
2491 goto release;
2492
bc7f75fa
AK		 2493 data &= 0xBFFF;
2494 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2495 act_offset * 2 + 1,
2496 (u8)(data >> 8));
9c5e209d
BA		 2497 if (ret_val)
2498 goto release;
bc7f75fa 2499
ad68076e
BA		 2500 /*
2501 * And invalidate the previously valid segment by setting
bc7f75fa
AK		 2502 * its signature word (0x13) high_byte to 0b. This can be
2503 * done without an erase because flash erase sets all bits
ad68076e
BA		 2504 * to 1's. We can write 1's to 0's without an erase
2505 */
bc7f75fa
AK		 2506 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2507 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
9c5e209d
BA		 2508 if (ret_val)
2509 goto release;
bc7f75fa
AK		 2510
2511 /* Great! Everything worked, we can now clear the cached entries. */
2512 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
564ea9bb 2513 dev_spec->shadow_ram[i].modified = false;
bc7f75fa
AK		 2514 dev_spec->shadow_ram[i].value = 0xFFFF;
2515 }
2516
9c5e209d 2517release:
94d8186a 2518 nvm->ops.release(hw);
bc7f75fa 2519
ad68076e
BA		 2520 /*
2521 * Reload the EEPROM, or else modifications will not appear
bc7f75fa
AK		 2522 * until after the next adapter reset.
2523 */
9c5e209d
BA		 2524 if (!ret_val) {
2525 e1000e_reload_nvm(hw);
2526 msleep(10);
2527 }
bc7f75fa 2528
e243455d
BA		 2529out:
2530 if (ret_val)
3bb99fe2 2531 e_dbg("NVM update error: %d\n", ret_val);
e243455d 2532
bc7f75fa
AK		 2533 return ret_val;
2534}
2535
2536/**
2537 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2538 * @hw: pointer to the HW structure
2539 *
2540 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2541 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2542 * calculated, in which case we need to calculate the checksum and set bit 6.
2543 **/
2544static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2545{
2546 s32 ret_val;
2547 u16 data;
2548
ad68076e
BA		 2549 /*
2550 * Read 0x19 and check bit 6. If this bit is 0, the checksum
bc7f75fa
AK		 2551 * needs to be fixed. This bit is an indication that the NVM
2552 * was prepared by OEM software and did not calculate the
2553 * checksum...a likely scenario.
2554 */
2555 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2556 if (ret_val)
2557 return ret_val;
2558
2559 if ((data & 0x40) == 0) {
2560 data |= 0x40;
2561 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2562 if (ret_val)
2563 return ret_val;
2564 ret_val = e1000e_update_nvm_checksum(hw);
2565 if (ret_val)
2566 return ret_val;
2567 }
2568
2569 return e1000e_validate_nvm_checksum_generic(hw);
2570}
2571
4a770358
BA		 2572/**
2573 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2574 * @hw: pointer to the HW structure
2575 *
2576 * To prevent malicious write/erase of the NVM, set it to be read-only
2577 * so that the hardware ignores all write/erase cycles of the NVM via
2578 * the flash control registers. The shadow-ram copy of the NVM will
2579 * still be updated, however any updates to this copy will not stick
2580 * across driver reloads.
2581 **/
2582void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2583{
ca15df58 2584 struct e1000_nvm_info *nvm = &hw->nvm;
4a770358
BA		 2585 union ich8_flash_protected_range pr0;
2586 union ich8_hws_flash_status hsfsts;
2587 u32 gfpreg;
4a770358 2588
94d8186a 2589 nvm->ops.acquire(hw);
4a770358
BA		 2590
2591 gfpreg = er32flash(ICH_FLASH_GFPREG);
2592
2593 /* Write-protect GbE Sector of NVM */
2594 pr0.regval = er32flash(ICH_FLASH_PR0);
2595 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2596 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2597 pr0.range.wpe = true;
2598 ew32flash(ICH_FLASH_PR0, pr0.regval);
2599
2600 /*
2601 * Lock down a subset of GbE Flash Control Registers, e.g.
2602 * PR0 to prevent the write-protection from being lifted.
2603 * Once FLOCKDN is set, the registers protected by it cannot
2604 * be written until FLOCKDN is cleared by a hardware reset.
2605 */
2606 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2607 hsfsts.hsf_status.flockdn = true;
2608 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2609
94d8186a 2610 nvm->ops.release(hw);
4a770358
BA		 2611}
2612
bc7f75fa
AK		 2613/**
2614 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2615 * @hw: pointer to the HW structure
2616 * @offset: The offset (in bytes) of the byte/word to read.
2617 * @size: Size of data to read, 1=byte 2=word
2618 * @data: The byte(s) to write to the NVM.
2619 *
2620 * Writes one/two bytes to the NVM using the flash access registers.
2621 **/
2622static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2623 u8 size, u16 data)
2624{
2625 union ich8_hws_flash_status hsfsts;
2626 union ich8_hws_flash_ctrl hsflctl;
2627 u32 flash_linear_addr;
2628 u32 flash_data = 0;
2629 s32 ret_val;
2630 u8 count = 0;
2631
2632 if (size < 1 || size > 2 || data > size * 0xff ||
2633 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2634 return -E1000_ERR_NVM;
2635
2636 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2637 hw->nvm.flash_base_addr;
2638
2639 do {
2640 udelay(1);
2641 /* Steps */
2642 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2643 if (ret_val)
2644 break;
2645
2646 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2647 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2648 hsflctl.hsf_ctrl.fldbcount = size -1;
2649 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2650 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2651
2652 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2653
2654 if (size == 1)
2655 flash_data = (u32)data & 0x00FF;
2656 else
2657 flash_data = (u32)data;
2658
2659 ew32flash(ICH_FLASH_FDATA0, flash_data);
2660
ad68076e
BA		 2661 /*
2662 * check if FCERR is set to 1 , if set to 1, clear it
2663 * and try the whole sequence a few more times else done
2664 */
bc7f75fa
AK		 2665 ret_val = e1000_flash_cycle_ich8lan(hw,
2666 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2667 if (!ret_val)
2668 break;
2669
ad68076e
BA		 2670 /*
2671 * If we're here, then things are most likely
bc7f75fa
AK		 2672 * completely hosed, but if the error condition
2673 * is detected, it won't hurt to give it another
2674 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2675 */
2676 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2677 if (hsfsts.hsf_status.flcerr == 1)
2678 /* Repeat for some time before giving up. */
2679 continue;
2680 if (hsfsts.hsf_status.flcdone == 0) {
3bb99fe2 2681 e_dbg("Timeout error - flash cycle "
bc7f75fa
AK		 2682 "did not complete.");
2683 break;
2684 }
2685 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2686
2687 return ret_val;
2688}
2689
2690/**
2691 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2692 * @hw: pointer to the HW structure
2693 * @offset: The index of the byte to read.
2694 * @data: The byte to write to the NVM.
2695 *
2696 * Writes a single byte to the NVM using the flash access registers.
2697 **/
2698static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2699 u8 data)
2700{
2701 u16 word = (u16)data;
2702
2703 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2704}
2705
2706/**
2707 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2708 * @hw: pointer to the HW structure
2709 * @offset: The offset of the byte to write.
2710 * @byte: The byte to write to the NVM.
2711 *
2712 * Writes a single byte to the NVM using the flash access registers.
2713 * Goes through a retry algorithm before giving up.
2714 **/
2715static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2716 u32 offset, u8 byte)
2717{
2718 s32 ret_val;
2719 u16 program_retries;
2720
2721 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2722 if (!ret_val)
2723 return ret_val;
2724
2725 for (program_retries = 0; program_retries < 100; program_retries++) {
3bb99fe2 2726 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
bc7f75fa
AK		 2727 udelay(100);
2728 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2729 if (!ret_val)
2730 break;
2731 }
2732 if (program_retries == 100)
2733 return -E1000_ERR_NVM;
2734
2735 return 0;
2736}
2737
2738/**
2739 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2740 * @hw: pointer to the HW structure
2741 * @bank: 0 for first bank, 1 for second bank, etc.
2742 *
2743 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2744 * bank N is 4096 * N + flash_reg_addr.
2745 **/
2746static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2747{
2748 struct e1000_nvm_info *nvm = &hw->nvm;
2749 union ich8_hws_flash_status hsfsts;
2750 union ich8_hws_flash_ctrl hsflctl;
2751 u32 flash_linear_addr;
2752 /* bank size is in 16bit words - adjust to bytes */
2753 u32 flash_bank_size = nvm->flash_bank_size * 2;
2754 s32 ret_val;
2755 s32 count = 0;
a708dd88 2756 s32 j, iteration, sector_size;
bc7f75fa
AK		 2757
2758 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2759
ad68076e
BA		 2760 /*
2761 * Determine HW Sector size: Read BERASE bits of hw flash status
2762 * register
2763 * 00: The Hw sector is 256 bytes, hence we need to erase 16
bc7f75fa
AK		 2764 * consecutive sectors. The start index for the nth Hw sector
2765 * can be calculated as = bank * 4096 + n * 256
2766 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2767 * The start index for the nth Hw sector can be calculated
2768 * as = bank * 4096
2769 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2770 * (ich9 only, otherwise error condition)
2771 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2772 */
2773 switch (hsfsts.hsf_status.berasesz) {
2774 case 0:
2775 /* Hw sector size 256 */
2776 sector_size = ICH_FLASH_SEG_SIZE_256;
2777 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2778 break;
2779 case 1:
2780 sector_size = ICH_FLASH_SEG_SIZE_4K;
28c9195a 2781 iteration = 1;
bc7f75fa
AK		 2782 break;
2783 case 2:
148675a7
BA		 2784 sector_size = ICH_FLASH_SEG_SIZE_8K;
2785 iteration = 1;
bc7f75fa
AK		 2786 break;
2787 case 3:
2788 sector_size = ICH_FLASH_SEG_SIZE_64K;
28c9195a 2789 iteration = 1;
bc7f75fa
AK		 2790 break;
2791 default:
2792 return -E1000_ERR_NVM;
2793 }
2794
2795 /* Start with the base address, then add the sector offset. */
2796 flash_linear_addr = hw->nvm.flash_base_addr;
148675a7 2797 flash_linear_addr += (bank) ? flash_bank_size : 0;
bc7f75fa
AK		 2798
2799 for (j = 0; j < iteration ; j++) {
2800 do {
2801 /* Steps */
2802 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2803 if (ret_val)
2804 return ret_val;
2805
ad68076e
BA		 2806 /*
2807 * Write a value 11 (block Erase) in Flash
2808 * Cycle field in hw flash control
2809 */
bc7f75fa
AK		 2810 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2811 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2812 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2813
ad68076e
BA		 2814 /*
2815 * Write the last 24 bits of an index within the
bc7f75fa
AK		 2816 * block into Flash Linear address field in Flash
2817 * Address.
2818 */
2819 flash_linear_addr += (j * sector_size);
2820 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2821
2822 ret_val = e1000_flash_cycle_ich8lan(hw,
2823 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2824 if (ret_val == 0)
2825 break;
2826
ad68076e
BA		 2827 /*
2828 * Check if FCERR is set to 1. If 1,
bc7f75fa 2829 * clear it and try the whole sequence
ad68076e
BA		 2830 * a few more times else Done
2831 */
bc7f75fa
AK		 2832 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2833 if (hsfsts.hsf_status.flcerr == 1)
ad68076e 2834 /* repeat for some time before giving up */
bc7f75fa
AK		 2835 continue;
2836 else if (hsfsts.hsf_status.flcdone == 0)
2837 return ret_val;
2838 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2839 }
2840
2841 return 0;
2842}
2843
2844/**
2845 * e1000_valid_led_default_ich8lan - Set the default LED settings
2846 * @hw: pointer to the HW structure
2847 * @data: Pointer to the LED settings
2848 *
2849 * Reads the LED default settings from the NVM to data. If the NVM LED
2850 * settings is all 0's or F's, set the LED default to a valid LED default
2851 * setting.
2852 **/
2853static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2854{
2855 s32 ret_val;
2856
2857 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2858 if (ret_val) {
3bb99fe2 2859 e_dbg("NVM Read Error\n");
bc7f75fa
AK		 2860 return ret_val;
2861 }
2862
2863 if (*data == ID_LED_RESERVED_0000 ||
2864 *data == ID_LED_RESERVED_FFFF)
2865 *data = ID_LED_DEFAULT_ICH8LAN;
2866
2867 return 0;
2868}
2869
a4f58f54
BA		 2870/**
2871 * e1000_id_led_init_pchlan - store LED configurations
2872 * @hw: pointer to the HW structure
2873 *
2874 * PCH does not control LEDs via the LEDCTL register, rather it uses
2875 * the PHY LED configuration register.
2876 *
2877 * PCH also does not have an "always on" or "always off" mode which
2878 * complicates the ID feature. Instead of using the "on" mode to indicate
2879 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2880 * use "link_up" mode. The LEDs will still ID on request if there is no
2881 * link based on logic in e1000_led_[on|off]_pchlan().
2882 **/
2883static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2884{
2885 struct e1000_mac_info *mac = &hw->mac;
2886 s32 ret_val;
2887 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2888 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2889 u16 data, i, temp, shift;
2890
2891 /* Get default ID LED modes */
2892 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2893 if (ret_val)
2894 goto out;
2895
2896 mac->ledctl_default = er32(LEDCTL);
2897 mac->ledctl_mode1 = mac->ledctl_default;
2898 mac->ledctl_mode2 = mac->ledctl_default;
2899
2900 for (i = 0; i < 4; i++) {
2901 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2902 shift = (i * 5);
2903 switch (temp) {
2904 case ID_LED_ON1_DEF2:
2905 case ID_LED_ON1_ON2:
2906 case ID_LED_ON1_OFF2:
2907 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2908 mac->ledctl_mode1 |= (ledctl_on << shift);
2909 break;
2910 case ID_LED_OFF1_DEF2:
2911 case ID_LED_OFF1_ON2:
2912 case ID_LED_OFF1_OFF2:
2913 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2914 mac->ledctl_mode1 |= (ledctl_off << shift);
2915 break;
2916 default:
2917 /* Do nothing */
2918 break;
2919 }
2920 switch (temp) {
2921 case ID_LED_DEF1_ON2:
2922 case ID_LED_ON1_ON2:
2923 case ID_LED_OFF1_ON2:
2924 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2925 mac->ledctl_mode2 |= (ledctl_on << shift);
2926 break;
2927 case ID_LED_DEF1_OFF2:
2928 case ID_LED_ON1_OFF2:
2929 case ID_LED_OFF1_OFF2:
2930 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2931 mac->ledctl_mode2 |= (ledctl_off << shift);
2932 break;
2933 default:
2934 /* Do nothing */
2935 break;
2936 }
2937 }
2938
2939out:
2940 return ret_val;
2941}
2942
bc7f75fa
AK		 2943/**
2944 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2945 * @hw: pointer to the HW structure
2946 *
2947 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2948 * register, so the the bus width is hard coded.
2949 **/
2950static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2951{
2952 struct e1000_bus_info *bus = &hw->bus;
2953 s32 ret_val;
2954
2955 ret_val = e1000e_get_bus_info_pcie(hw);
2956
ad68076e
BA		 2957 /*
2958 * ICH devices are "PCI Express"-ish. They have
bc7f75fa
AK		 2959 * a configuration space, but do not contain
2960 * PCI Express Capability registers, so bus width
2961 * must be hardcoded.
2962 */
2963 if (bus->width == e1000_bus_width_unknown)
2964 bus->width = e1000_bus_width_pcie_x1;
2965
2966 return ret_val;
2967}
2968
2969/**
2970 * e1000_reset_hw_ich8lan - Reset the hardware
2971 * @hw: pointer to the HW structure
2972 *
2973 * Does a full reset of the hardware which includes a reset of the PHY and
2974 * MAC.
2975 **/
2976static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2977{
1d5846b9 2978 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
db2932ec 2979 u16 reg;
bc7f75fa
AK		 2980 u32 ctrl, icr, kab;
2981 s32 ret_val;
2982
ad68076e
BA		 2983 /*
2984 * Prevent the PCI-E bus from sticking if there is no TLP connection
bc7f75fa
AK		 2985 * on the last TLP read/write transaction when MAC is reset.
2986 */
2987 ret_val = e1000e_disable_pcie_master(hw);
e98cac44 2988 if (ret_val)
3bb99fe2 2989 e_dbg("PCI-E Master disable polling has failed.\n");
bc7f75fa 2990
3bb99fe2 2991 e_dbg("Masking off all interrupts\n");
bc7f75fa
AK		 2992 ew32(IMC, 0xffffffff);
2993
ad68076e
BA		 2994 /*
2995 * Disable the Transmit and Receive units. Then delay to allow
bc7f75fa
AK		 2996 * any pending transactions to complete before we hit the MAC
2997 * with the global reset.
2998 */
2999 ew32(RCTL, 0);
3000 ew32(TCTL, E1000_TCTL_PSP);
3001 e1e_flush();
3002
3003 msleep(10);
3004
3005 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3006 if (hw->mac.type == e1000_ich8lan) {
3007 /* Set Tx and Rx buffer allocation to 8k apiece. */
3008 ew32(PBA, E1000_PBA_8K);
3009 /* Set Packet Buffer Size to 16k. */
3010 ew32(PBS, E1000_PBS_16K);
3011 }
3012
1d5846b9
BA		 3013 if (hw->mac.type == e1000_pchlan) {
3014 /* Save the NVM K1 bit setting*/
3015 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3016 if (ret_val)
3017 return ret_val;
3018
3019 if (reg & E1000_NVM_K1_ENABLE)
3020 dev_spec->nvm_k1_enabled = true;
3021 else
3022 dev_spec->nvm_k1_enabled = false;
3023 }
3024
bc7f75fa
AK		 3025 ctrl = er32(CTRL);
3026
3027 if (!e1000_check_reset_block(hw)) {
ad68076e 3028 /*
e98cac44 3029 * Full-chip reset requires MAC and PHY reset at the same
bc7f75fa
AK		 3030 * time to make sure the interface between MAC and the
3031 * external PHY is reset.
3032 */
3033 ctrl |= E1000_CTRL_PHY_RST;
605c82ba
BA		 3034
3035 /*
3036 * Gate automatic PHY configuration by hardware on
3037 * non-managed 82579
3038 */
3039 if ((hw->mac.type == e1000_pch2lan) &&
3040 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3041 e1000_gate_hw_phy_config_ich8lan(hw, true);
bc7f75fa
AK		 3042 }
3043 ret_val = e1000_acquire_swflag_ich8lan(hw);
3bb99fe2 3044 e_dbg("Issuing a global reset to ich8lan\n");
bc7f75fa
AK		 3045 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3046 msleep(20);
3047
fc0c7760 3048 if (!ret_val)
30bb0e0d 3049 e1000_release_swflag_ich8lan(hw);
37f40239 3050
e98cac44 3051 if (ctrl & E1000_CTRL_PHY_RST) {
fc0c7760 3052 ret_val = hw->phy.ops.get_cfg_done(hw);
e98cac44
BA		 3053 if (ret_val)
3054 goto out;
fc0c7760 3055
e98cac44 3056 ret_val = e1000_post_phy_reset_ich8lan(hw);
f523d211
BA		 3057 if (ret_val)
3058 goto out;
3059 }
e98cac44 3060
7d3cabbc
BA		 3061 /*
3062 * For PCH, this write will make sure that any noise
3063 * will be detected as a CRC error and be dropped rather than show up
3064 * as a bad packet to the DMA engine.
3065 */
3066 if (hw->mac.type == e1000_pchlan)
3067 ew32(CRC_OFFSET, 0x65656565);
3068
bc7f75fa
AK		 3069 ew32(IMC, 0xffffffff);
3070 icr = er32(ICR);
3071
3072 kab = er32(KABGTXD);
3073 kab |= E1000_KABGTXD_BGSQLBIAS;
3074 ew32(KABGTXD, kab);
3075
f523d211 3076out:
bc7f75fa
AK		 3077 return ret_val;
3078}
3079
3080/**
3081 * e1000_init_hw_ich8lan - Initialize the hardware
3082 * @hw: pointer to the HW structure
3083 *
3084 * Prepares the hardware for transmit and receive by doing the following:
3085 * - initialize hardware bits
3086 * - initialize LED identification
3087 * - setup receive address registers
3088 * - setup flow control
489815ce 3089 * - setup transmit descriptors
bc7f75fa
AK		 3090 * - clear statistics
3091 **/
3092static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3093{
3094 struct e1000_mac_info *mac = &hw->mac;
3095 u32 ctrl_ext, txdctl, snoop;
3096 s32 ret_val;
3097 u16 i;
3098
3099 e1000_initialize_hw_bits_ich8lan(hw);
3100
3101 /* Initialize identification LED */
a4f58f54 3102 ret_val = mac->ops.id_led_init(hw);
de39b752 3103 if (ret_val)
3bb99fe2 3104 e_dbg("Error initializing identification LED\n");
de39b752 3105 /* This is not fatal and we should not stop init due to this */
bc7f75fa
AK		 3106
3107 /* Setup the receive address. */
3108 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3109
3110 /* Zero out the Multicast HASH table */
3bb99fe2 3111 e_dbg("Zeroing the MTA\n");
bc7f75fa
AK		 3112 for (i = 0; i < mac->mta_reg_count; i++)
3113 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3114
fc0c7760
BA		 3115 /*
3116 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3117 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
3118 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3119 */
3120 if (hw->phy.type == e1000_phy_82578) {
94d8186a 3121 hw->phy.ops.read_reg(hw, BM_WUC, &i);
fc0c7760
BA		 3122 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3123 if (ret_val)
3124 return ret_val;
3125 }
3126
bc7f75fa
AK		 3127 /* Setup link and flow control */
3128 ret_val = e1000_setup_link_ich8lan(hw);
3129
3130 /* Set the transmit descriptor write-back policy for both queues */
e9ec2c0f 3131 txdctl = er32(TXDCTL(0));
bc7f75fa
AK		 3132 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3133 E1000_TXDCTL_FULL_TX_DESC_WB;
3134 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3135 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f
JK		 3136 ew32(TXDCTL(0), txdctl);
3137 txdctl = er32(TXDCTL(1));
bc7f75fa
AK		 3138 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3139 E1000_TXDCTL_FULL_TX_DESC_WB;
3140 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3141 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
e9ec2c0f 3142 ew32(TXDCTL(1), txdctl);
bc7f75fa 3143
ad68076e
BA		 3144 /*
3145 * ICH8 has opposite polarity of no_snoop bits.
3146 * By default, we should use snoop behavior.
3147 */
bc7f75fa
AK		 3148 if (mac->type == e1000_ich8lan)
3149 snoop = PCIE_ICH8_SNOOP_ALL;
3150 else
3151 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3152 e1000e_set_pcie_no_snoop(hw, snoop);
3153
3154 ctrl_ext = er32(CTRL_EXT);
3155 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3156 ew32(CTRL_EXT, ctrl_ext);
3157
ad68076e
BA		 3158 /*
3159 * Clear all of the statistics registers (clear on read). It is
bc7f75fa
AK		 3160 * important that we do this after we have tried to establish link
3161 * because the symbol error count will increment wildly if there
3162 * is no link.
3163 */
3164 e1000_clear_hw_cntrs_ich8lan(hw);
3165
3166 return 0;
3167}
3168/**
3169 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3170 * @hw: pointer to the HW structure
3171 *
3172 * Sets/Clears required hardware bits necessary for correctly setting up the
3173 * hardware for transmit and receive.
3174 **/
3175static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3176{
3177 u32 reg;
3178
3179 /* Extended Device Control */
3180 reg = er32(CTRL_EXT);
3181 reg |= (1 << 22);
a4f58f54
BA		 3182 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3183 if (hw->mac.type >= e1000_pchlan)
3184 reg |= E1000_CTRL_EXT_PHYPDEN;
bc7f75fa
AK		 3185 ew32(CTRL_EXT, reg);
3186
3187 /* Transmit Descriptor Control 0 */
e9ec2c0f 3188 reg = er32(TXDCTL(0));
bc7f75fa 3189 reg |= (1 << 22);
e9ec2c0f 3190 ew32(TXDCTL(0), reg);
bc7f75fa
AK		 3191
3192 /* Transmit Descriptor Control 1 */
e9ec2c0f 3193 reg = er32(TXDCTL(1));
bc7f75fa 3194 reg |= (1 << 22);
e9ec2c0f 3195 ew32(TXDCTL(1), reg);
bc7f75fa
AK		 3196
3197 /* Transmit Arbitration Control 0 */
e9ec2c0f 3198 reg = er32(TARC(0));
bc7f75fa
AK		 3199 if (hw->mac.type == e1000_ich8lan)
3200 reg |= (1 << 28) | (1 << 29);
3201 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
e9ec2c0f 3202 ew32(TARC(0), reg);
bc7f75fa
AK		 3203
3204 /* Transmit Arbitration Control 1 */
e9ec2c0f 3205 reg = er32(TARC(1));
bc7f75fa
AK		 3206 if (er32(TCTL) & E1000_TCTL_MULR)
3207 reg &= ~(1 << 28);
3208 else
3209 reg |= (1 << 28);
3210 reg |= (1 << 24) | (1 << 26) | (1 << 30);
e9ec2c0f 3211 ew32(TARC(1), reg);
bc7f75fa
AK		 3212
3213 /* Device Status */
3214 if (hw->mac.type == e1000_ich8lan) {
3215 reg = er32(STATUS);
3216 reg &= ~(1 << 31);
3217 ew32(STATUS, reg);
3218 }
a80483d3
JB		 3219
3220 /*
3221 * work-around descriptor data corruption issue during nfs v2 udp
3222 * traffic, just disable the nfs filtering capability
3223 */
3224 reg = er32(RFCTL);
3225 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3226 ew32(RFCTL, reg);
bc7f75fa
AK		 3227}
3228
3229/**
3230 * e1000_setup_link_ich8lan - Setup flow control and link settings
3231 * @hw: pointer to the HW structure
3232 *
3233 * Determines which flow control settings to use, then configures flow
3234 * control. Calls the appropriate media-specific link configuration
3235 * function. Assuming the adapter has a valid link partner, a valid link
3236 * should be established. Assumes the hardware has previously been reset
3237 * and the transmitter and receiver are not enabled.
3238 **/
3239static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3240{
bc7f75fa
AK		 3241 s32 ret_val;
3242
3243 if (e1000_check_reset_block(hw))
3244 return 0;
3245
ad68076e
BA		 3246 /*
3247 * ICH parts do not have a word in the NVM to determine
bc7f75fa
AK		 3248 * the default flow control setting, so we explicitly
3249 * set it to full.
3250 */
37289d9c
BA		 3251 if (hw->fc.requested_mode == e1000_fc_default) {
3252 /* Workaround h/w hang when Tx flow control enabled */
3253 if (hw->mac.type == e1000_pchlan)
3254 hw->fc.requested_mode = e1000_fc_rx_pause;
3255 else
3256 hw->fc.requested_mode = e1000_fc_full;
3257 }
bc7f75fa 3258
5c48ef3e
BA		 3259 /*
3260 * Save off the requested flow control mode for use later. Depending
3261 * on the link partner's capabilities, we may or may not use this mode.
3262 */
3263 hw->fc.current_mode = hw->fc.requested_mode;
bc7f75fa 3264
3bb99fe2 3265 e_dbg("After fix-ups FlowControl is now = %x\n",
5c48ef3e 3266 hw->fc.current_mode);
bc7f75fa
AK		 3267
3268 /* Continue to configure the copper link. */
3269 ret_val = e1000_setup_copper_link_ich8lan(hw);
3270 if (ret_val)
3271 return ret_val;
3272
318a94d6 3273 ew32(FCTTV, hw->fc.pause_time);
a4f58f54 3274 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3275 (hw->phy.type == e1000_phy_82579) ||
a4f58f54 3276 (hw->phy.type == e1000_phy_82577)) {
a305595b
BA		 3277 ew32(FCRTV_PCH, hw->fc.refresh_time);
3278
94d8186a 3279 ret_val = hw->phy.ops.write_reg(hw,
a4f58f54
BA		 3280 PHY_REG(BM_PORT_CTRL_PAGE, 27),
3281 hw->fc.pause_time);
3282 if (ret_val)
3283 return ret_val;
3284 }
bc7f75fa
AK		 3285
3286 return e1000e_set_fc_watermarks(hw);
3287}
3288
3289/**
3290 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3291 * @hw: pointer to the HW structure
3292 *
3293 * Configures the kumeran interface to the PHY to wait the appropriate time
3294 * when polling the PHY, then call the generic setup_copper_link to finish
3295 * configuring the copper link.
3296 **/
3297static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3298{
3299 u32 ctrl;
3300 s32 ret_val;
3301 u16 reg_data;
3302
3303 ctrl = er32(CTRL);
3304 ctrl |= E1000_CTRL_SLU;
3305 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3306 ew32(CTRL, ctrl);
3307
ad68076e
BA		 3308 /*
3309 * Set the mac to wait the maximum time between each iteration
bc7f75fa 3310 * and increase the max iterations when polling the phy;
ad68076e
BA		 3311 * this fixes erroneous timeouts at 10Mbps.
3312 */
07818950 3313 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
bc7f75fa
AK		 3314 if (ret_val)
3315 return ret_val;
07818950
BA		 3316 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3317 &reg_data);
bc7f75fa
AK		 3318 if (ret_val)
3319 return ret_val;
3320 reg_data |= 0x3F;
07818950
BA		 3321 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3322 reg_data);
bc7f75fa
AK		 3323 if (ret_val)
3324 return ret_val;
3325
a4f58f54
BA		 3326 switch (hw->phy.type) {
3327 case e1000_phy_igp_3:
bc7f75fa
AK		 3328 ret_val = e1000e_copper_link_setup_igp(hw);
3329 if (ret_val)
3330 return ret_val;
a4f58f54
BA		 3331 break;
3332 case e1000_phy_bm:
3333 case e1000_phy_82578:
97ac8cae
BA		 3334 ret_val = e1000e_copper_link_setup_m88(hw);
3335 if (ret_val)
3336 return ret_val;
a4f58f54
BA		 3337 break;
3338 case e1000_phy_82577:
d3738bb8 3339 case e1000_phy_82579:
a4f58f54
BA		 3340 ret_val = e1000_copper_link_setup_82577(hw);
3341 if (ret_val)
3342 return ret_val;
3343 break;
3344 case e1000_phy_ife:
94d8186a 3345 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 3346 &reg_data);
97ac8cae
BA		 3347 if (ret_val)
3348 return ret_val;
3349
3350 reg_data &= ~IFE_PMC_AUTO_MDIX;
3351
3352 switch (hw->phy.mdix) {
3353 case 1:
3354 reg_data &= ~IFE_PMC_FORCE_MDIX;
3355 break;
3356 case 2:
3357 reg_data |= IFE_PMC_FORCE_MDIX;
3358 break;
3359 case 0:
3360 default:
3361 reg_data |= IFE_PMC_AUTO_MDIX;
3362 break;
3363 }
94d8186a 3364 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
a4f58f54 3365 reg_data);
97ac8cae
BA		 3366 if (ret_val)
3367 return ret_val;
a4f58f54
BA		 3368 break;
3369 default:
3370 break;
97ac8cae 3371 }
bc7f75fa
AK		 3372 return e1000e_setup_copper_link(hw);
3373}
3374
3375/**
3376 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3377 * @hw: pointer to the HW structure
3378 * @speed: pointer to store current link speed
3379 * @duplex: pointer to store the current link duplex
3380 *
ad68076e 3381 * Calls the generic get_speed_and_duplex to retrieve the current link
bc7f75fa
AK		 3382 * information and then calls the Kumeran lock loss workaround for links at
3383 * gigabit speeds.
3384 **/
3385static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3386 u16 *duplex)
3387{
3388 s32 ret_val;
3389
3390 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3391 if (ret_val)
3392 return ret_val;
3393
3394 if ((hw->mac.type == e1000_ich8lan) &&
3395 (hw->phy.type == e1000_phy_igp_3) &&
3396 (*speed == SPEED_1000)) {
3397 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3398 }
3399
3400 return ret_val;
3401}
3402
3403/**
3404 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3405 * @hw: pointer to the HW structure
3406 *
3407 * Work-around for 82566 Kumeran PCS lock loss:
3408 * On link status change (i.e. PCI reset, speed change) and link is up and
3409 * speed is gigabit-
3410 * 0) if workaround is optionally disabled do nothing
3411 * 1) wait 1ms for Kumeran link to come up
3412 * 2) check Kumeran Diagnostic register PCS lock loss bit
3413 * 3) if not set the link is locked (all is good), otherwise...
3414 * 4) reset the PHY
3415 * 5) repeat up to 10 times
3416 * Note: this is only called for IGP3 copper when speed is 1gb.
3417 **/
3418static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3419{
3420 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3421 u32 phy_ctrl;
3422 s32 ret_val;
3423 u16 i, data;
3424 bool link;
3425
3426 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3427 return 0;
3428
ad68076e
BA		 3429 /*
3430 * Make sure link is up before proceeding. If not just return.
bc7f75fa 3431 * Attempting this while link is negotiating fouled up link
ad68076e
BA		 3432 * stability
3433 */
bc7f75fa
AK		 3434 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3435 if (!link)
3436 return 0;
3437
3438 for (i = 0; i < 10; i++) {
3439 /* read once to clear */
3440 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3441 if (ret_val)
3442 return ret_val;
3443 /* and again to get new status */
3444 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3445 if (ret_val)
3446 return ret_val;
3447
3448 /* check for PCS lock */
3449 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3450 return 0;
3451
3452 /* Issue PHY reset */
3453 e1000_phy_hw_reset(hw);
3454 mdelay(5);
3455 }
3456 /* Disable GigE link negotiation */
3457 phy_ctrl = er32(PHY_CTRL);
3458 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3459 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3460 ew32(PHY_CTRL, phy_ctrl);
3461
ad68076e
BA		 3462 /*
3463 * Call gig speed drop workaround on Gig disable before accessing
3464 * any PHY registers
3465 */
bc7f75fa
AK		 3466 e1000e_gig_downshift_workaround_ich8lan(hw);
3467
3468 /* unable to acquire PCS lock */
3469 return -E1000_ERR_PHY;
3470}
3471
3472/**
ad68076e 3473 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
bc7f75fa 3474 * @hw: pointer to the HW structure
489815ce 3475 * @state: boolean value used to set the current Kumeran workaround state
bc7f75fa 3476 *
564ea9bb
BA		 3477 * If ICH8, set the current Kumeran workaround state (enabled - true
3478 * /disabled - false).
bc7f75fa
AK		 3479 **/
3480void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3481 bool state)
3482{
3483 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3484
3485 if (hw->mac.type != e1000_ich8lan) {
3bb99fe2 3486 e_dbg("Workaround applies to ICH8 only.\n");
bc7f75fa
AK		 3487 return;
3488 }
3489
3490 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3491}
3492
3493/**
3494 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3495 * @hw: pointer to the HW structure
3496 *
3497 * Workaround for 82566 power-down on D3 entry:
3498 * 1) disable gigabit link
3499 * 2) write VR power-down enable
3500 * 3) read it back
3501 * Continue if successful, else issue LCD reset and repeat
3502 **/
3503void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3504{
3505 u32 reg;
3506 u16 data;
3507 u8 retry = 0;
3508
3509 if (hw->phy.type != e1000_phy_igp_3)
3510 return;
3511
3512 /* Try the workaround twice (if needed) */
3513 do {
3514 /* Disable link */
3515 reg = er32(PHY_CTRL);
3516 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3517 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3518 ew32(PHY_CTRL, reg);
3519
ad68076e
BA		 3520 /*
3521 * Call gig speed drop workaround on Gig disable before
3522 * accessing any PHY registers
3523 */
bc7f75fa
AK		 3524 if (hw->mac.type == e1000_ich8lan)
3525 e1000e_gig_downshift_workaround_ich8lan(hw);
3526
3527 /* Write VR power-down enable */
3528 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3529 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3530 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3531
3532 /* Read it back and test */
3533 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3534 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3535 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3536 break;
3537
3538 /* Issue PHY reset and repeat at most one more time */
3539 reg = er32(CTRL);
3540 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3541 retry++;
3542 } while (retry);
3543}
3544
3545/**
3546 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3547 * @hw: pointer to the HW structure
3548 *
3549 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
489815ce 3550 * LPLU, Gig disable, MDIC PHY reset):
bc7f75fa
AK		 3551 * 1) Set Kumeran Near-end loopback
3552 * 2) Clear Kumeran Near-end loopback
3553 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3554 **/
3555void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3556{
3557 s32 ret_val;
3558 u16 reg_data;
3559
3560 if ((hw->mac.type != e1000_ich8lan) ||
3561 (hw->phy.type != e1000_phy_igp_3))
3562 return;
3563
3564 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3565 &reg_data);
3566 if (ret_val)
3567 return;
3568 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3569 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3570 reg_data);
3571 if (ret_val)
3572 return;
3573 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3574 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3575 reg_data);
3576}
3577
97ac8cae
BA		 3578/**
3579 * e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3580 * @hw: pointer to the HW structure
3581 *
3582 * During S0 to Sx transition, it is possible the link remains at gig
3583 * instead of negotiating to a lower speed. Before going to Sx, set
3584 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3585 * to a lower speed.
3586 *
a4f58f54 3587 * Should only be called for applicable parts.
97ac8cae
BA		 3588 **/
3589void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3590{
3591 u32 phy_ctrl;
8395ae83 3592 s32 ret_val;
97ac8cae 3593
17f085df
BA		 3594 phy_ctrl = er32(PHY_CTRL);
3595 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3596 ew32(PHY_CTRL, phy_ctrl);
a4f58f54 3597
8395ae83 3598 if (hw->mac.type >= e1000_pchlan) {
ce54afd1 3599 e1000_oem_bits_config_ich8lan(hw, false);
8395ae83
BA		 3600 ret_val = hw->phy.ops.acquire(hw);
3601 if (ret_val)
3602 return;
3603 e1000_write_smbus_addr(hw);
3604 hw->phy.ops.release(hw);
3605 }
97ac8cae
BA		 3606}
3607
bc7f75fa
AK		 3608/**
3609 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3610 * @hw: pointer to the HW structure
3611 *
3612 * Return the LED back to the default configuration.
3613 **/
3614static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3615{
3616 if (hw->phy.type == e1000_phy_ife)
3617 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3618
3619 ew32(LEDCTL, hw->mac.ledctl_default);
3620 return 0;
3621}
3622
3623/**
489815ce 3624 * e1000_led_on_ich8lan - Turn LEDs on
bc7f75fa
AK		 3625 * @hw: pointer to the HW structure
3626 *
489815ce 3627 * Turn on the LEDs.
bc7f75fa
AK		 3628 **/
3629static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3630{
3631 if (hw->phy.type == e1000_phy_ife)
3632 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3633 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3634
3635 ew32(LEDCTL, hw->mac.ledctl_mode2);
3636 return 0;
3637}
3638
3639/**
489815ce 3640 * e1000_led_off_ich8lan - Turn LEDs off
bc7f75fa
AK		 3641 * @hw: pointer to the HW structure
3642 *
489815ce 3643 * Turn off the LEDs.
bc7f75fa
AK		 3644 **/
3645static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3646{
3647 if (hw->phy.type == e1000_phy_ife)
3648 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3649 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3650
3651 ew32(LEDCTL, hw->mac.ledctl_mode1);
3652 return 0;
3653}
3654
a4f58f54
BA		 3655/**
3656 * e1000_setup_led_pchlan - Configures SW controllable LED
3657 * @hw: pointer to the HW structure
3658 *
3659 * This prepares the SW controllable LED for use.
3660 **/
3661static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3662{
94d8186a 3663 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3664 (u16)hw->mac.ledctl_mode1);
3665}
3666
3667/**
3668 * e1000_cleanup_led_pchlan - Restore the default LED operation
3669 * @hw: pointer to the HW structure
3670 *
3671 * Return the LED back to the default configuration.
3672 **/
3673static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3674{
94d8186a 3675 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
a4f58f54
BA		 3676 (u16)hw->mac.ledctl_default);
3677}
3678
3679/**
3680 * e1000_led_on_pchlan - Turn LEDs on
3681 * @hw: pointer to the HW structure
3682 *
3683 * Turn on the LEDs.
3684 **/
3685static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3686{
3687 u16 data = (u16)hw->mac.ledctl_mode2;
3688 u32 i, led;
3689
3690 /*
3691 * If no link, then turn LED on by setting the invert bit
3692 * for each LED that's mode is "link_up" in ledctl_mode2.
3693 */
3694 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3695 for (i = 0; i < 3; i++) {
3696 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3697 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3698 E1000_LEDCTL_MODE_LINK_UP)
3699 continue;
3700 if (led & E1000_PHY_LED0_IVRT)
3701 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3702 else
3703 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3704 }
3705 }
3706
94d8186a 3707 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3708}
3709
3710/**
3711 * e1000_led_off_pchlan - Turn LEDs off
3712 * @hw: pointer to the HW structure
3713 *
3714 * Turn off the LEDs.
3715 **/
3716static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3717{
3718 u16 data = (u16)hw->mac.ledctl_mode1;
3719 u32 i, led;
3720
3721 /*
3722 * If no link, then turn LED off by clearing the invert bit
3723 * for each LED that's mode is "link_up" in ledctl_mode1.
3724 */
3725 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3726 for (i = 0; i < 3; i++) {
3727 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3728 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3729 E1000_LEDCTL_MODE_LINK_UP)
3730 continue;
3731 if (led & E1000_PHY_LED0_IVRT)
3732 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3733 else
3734 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3735 }
3736 }
3737
94d8186a 3738 return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
a4f58f54
BA		 3739}
3740
f4187b56 3741/**
e98cac44 3742 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
f4187b56
BA		 3743 * @hw: pointer to the HW structure
3744 *
e98cac44
BA		 3745 * Read appropriate register for the config done bit for completion status
3746 * and configure the PHY through s/w for EEPROM-less parts.
3747 *
3748 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3749 * config done bit, so only an error is logged and continues. If we were
3750 * to return with error, EEPROM-less silicon would not be able to be reset
3751 * or change link.
f4187b56
BA		 3752 **/
3753static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3754{
e98cac44 3755 s32 ret_val = 0;
f4187b56 3756 u32 bank = 0;
e98cac44 3757 u32 status;
f4187b56 3758
e98cac44 3759 e1000e_get_cfg_done(hw);
fc0c7760 3760
e98cac44
BA		 3761 /* Wait for indication from h/w that it has completed basic config */
3762 if (hw->mac.type >= e1000_ich10lan) {
3763 e1000_lan_init_done_ich8lan(hw);
3764 } else {
3765 ret_val = e1000e_get_auto_rd_done(hw);
3766 if (ret_val) {
3767 /*
3768 * When auto config read does not complete, do not
3769 * return with an error. This can happen in situations
3770 * where there is no eeprom and prevents getting link.
3771 */
3772 e_dbg("Auto Read Done did not complete\n");
3773 ret_val = 0;
3774 }
fc0c7760
BA		 3775 }
3776
e98cac44
BA		 3777 /* Clear PHY Reset Asserted bit */
3778 status = er32(STATUS);
3779 if (status & E1000_STATUS_PHYRA)
3780 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3781 else
3782 e_dbg("PHY Reset Asserted not set - needs delay\n");
f4187b56
BA		 3783
3784 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
e98cac44 3785 if (hw->mac.type <= e1000_ich9lan) {
f4187b56
BA		 3786 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3787 (hw->phy.type == e1000_phy_igp_3)) {
3788 e1000e_phy_init_script_igp3(hw);
3789 }
3790 } else {
3791 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3792 /* Maybe we should do a basic PHY config */
3bb99fe2 3793 e_dbg("EEPROM not present\n");
e98cac44 3794 ret_val = -E1000_ERR_CONFIG;
f4187b56
BA		 3795 }
3796 }
3797
e98cac44 3798 return ret_val;
f4187b56
BA		 3799}
3800
17f208de
BA		 3801/**
3802 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3803 * @hw: pointer to the HW structure
3804 *
3805 * In the case of a PHY power down to save power, or to turn off link during a
3806 * driver unload, or wake on lan is not enabled, remove the link.
3807 **/
3808static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3809{
3810 /* If the management interface is not enabled, then power down */
3811 if (!(hw->mac.ops.check_mng_mode(hw) ||
3812 hw->phy.ops.check_reset_block(hw)))
3813 e1000_power_down_phy_copper(hw);
17f208de
BA		 3814}
3815
bc7f75fa
AK		 3816/**
3817 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3818 * @hw: pointer to the HW structure
3819 *
3820 * Clears hardware counters specific to the silicon family and calls
3821 * clear_hw_cntrs_generic to clear all general purpose counters.
3822 **/
3823static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3824{
a4f58f54 3825 u16 phy_data;
bc7f75fa
AK		 3826
3827 e1000e_clear_hw_cntrs_base(hw);
3828
99673d9b
BA		 3829 er32(ALGNERRC);
3830 er32(RXERRC);
3831 er32(TNCRS);
3832 er32(CEXTERR);
3833 er32(TSCTC);
3834 er32(TSCTFC);
bc7f75fa 3835
99673d9b
BA		 3836 er32(MGTPRC);
3837 er32(MGTPDC);
3838 er32(MGTPTC);
bc7f75fa 3839
99673d9b
BA		 3840 er32(IAC);
3841 er32(ICRXOC);
bc7f75fa 3842
a4f58f54
BA		 3843 /* Clear PHY statistics registers */
3844 if ((hw->phy.type == e1000_phy_82578) ||
d3738bb8 3845 (hw->phy.type == e1000_phy_82579) ||
a4f58f54 3846 (hw->phy.type == e1000_phy_82577)) {
94d8186a
BA		 3847 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3848 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3849 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3850 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3851 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3852 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3853 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3854 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3855 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3856 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3857 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3858 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3859 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3860 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
a4f58f54 3861 }
bc7f75fa
AK		 3862}
3863
3864static struct e1000_mac_operations ich8_mac_ops = {
a4f58f54 3865 .id_led_init = e1000e_id_led_init,
eb7700dc 3866 /* check_mng_mode dependent on mac type */
7d3cabbc 3867 .check_for_link = e1000_check_for_copper_link_ich8lan,
a4f58f54 3868 /* cleanup_led dependent on mac type */
bc7f75fa
AK		 3869 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3870 .get_bus_info = e1000_get_bus_info_ich8lan,
f4d2dd4c 3871 .set_lan_id = e1000_set_lan_id_single_port,
bc7f75fa 3872 .get_link_up_info = e1000_get_link_up_info_ich8lan,
a4f58f54
BA		 3873 /* led_on dependent on mac type */
3874 /* led_off dependent on mac type */
e2de3eb6 3875 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
bc7f75fa
AK		 3876 .reset_hw = e1000_reset_hw_ich8lan,
3877 .init_hw = e1000_init_hw_ich8lan,
3878 .setup_link = e1000_setup_link_ich8lan,
3879 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
a4f58f54 3880 /* id_led_init dependent on mac type */
bc7f75fa
AK		 3881};
3882
3883static struct e1000_phy_operations ich8_phy_ops = {
94d8186a 3884 .acquire = e1000_acquire_swflag_ich8lan,
bc7f75fa 3885 .check_reset_block = e1000_check_reset_block_ich8lan,
94d8186a 3886 .commit = NULL,
f4187b56 3887 .get_cfg_done = e1000_get_cfg_done_ich8lan,
bc7f75fa 3888 .get_cable_length = e1000e_get_cable_length_igp_2,
94d8186a
BA		 3889 .read_reg = e1000e_read_phy_reg_igp,
3890 .release = e1000_release_swflag_ich8lan,
3891 .reset = e1000_phy_hw_reset_ich8lan,
bc7f75fa
AK		 3892 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
3893 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
94d8186a 3894 .write_reg = e1000e_write_phy_reg_igp,
bc7f75fa
AK		 3895};
3896
3897static struct e1000_nvm_operations ich8_nvm_ops = {
94d8186a
BA		 3898 .acquire = e1000_acquire_nvm_ich8lan,
3899 .read = e1000_read_nvm_ich8lan,
3900 .release = e1000_release_nvm_ich8lan,
3901 .update = e1000_update_nvm_checksum_ich8lan,
bc7f75fa 3902 .valid_led_default = e1000_valid_led_default_ich8lan,
94d8186a
BA		 3903 .validate = e1000_validate_nvm_checksum_ich8lan,
3904 .write = e1000_write_nvm_ich8lan,
bc7f75fa
AK		 3905};
3906
3907struct e1000_info e1000_ich8_info = {
3908 .mac = e1000_ich8lan,
3909 .flags = FLAG_HAS_WOL
97ac8cae 3910 | FLAG_IS_ICH
bc7f75fa
AK		 3911 | FLAG_RX_CSUM_ENABLED
3912 | FLAG_HAS_CTRLEXT_ON_LOAD
3913 | FLAG_HAS_AMT
3914 | FLAG_HAS_FLASH
3915 | FLAG_APME_IN_WUC,
3916 .pba = 8,
2adc55c9 3917 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
69e3fd8c 3918 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3919 .mac_ops = &ich8_mac_ops,
3920 .phy_ops = &ich8_phy_ops,
3921 .nvm_ops = &ich8_nvm_ops,
3922};
3923
3924struct e1000_info e1000_ich9_info = {
3925 .mac = e1000_ich9lan,
3926 .flags = FLAG_HAS_JUMBO_FRAMES
97ac8cae 3927 | FLAG_IS_ICH
bc7f75fa
AK		 3928 | FLAG_HAS_WOL
3929 | FLAG_RX_CSUM_ENABLED
3930 | FLAG_HAS_CTRLEXT_ON_LOAD
3931 | FLAG_HAS_AMT
3932 | FLAG_HAS_ERT
3933 | FLAG_HAS_FLASH
3934 | FLAG_APME_IN_WUC,
3935 .pba = 10,
2adc55c9 3936 .max_hw_frame_size = DEFAULT_JUMBO,
69e3fd8c 3937 .get_variants = e1000_get_variants_ich8lan,
bc7f75fa
AK		 3938 .mac_ops = &ich8_mac_ops,
3939 .phy_ops = &ich8_phy_ops,
3940 .nvm_ops = &ich8_nvm_ops,
3941};
3942
f4187b56
BA		 3943struct e1000_info e1000_ich10_info = {
3944 .mac = e1000_ich10lan,
3945 .flags = FLAG_HAS_JUMBO_FRAMES
3946 | FLAG_IS_ICH
3947 | FLAG_HAS_WOL
3948 | FLAG_RX_CSUM_ENABLED
3949 | FLAG_HAS_CTRLEXT_ON_LOAD
3950 | FLAG_HAS_AMT
3951 | FLAG_HAS_ERT
3952 | FLAG_HAS_FLASH
3953 | FLAG_APME_IN_WUC,
3954 .pba = 10,
2adc55c9 3955 .max_hw_frame_size = DEFAULT_JUMBO,
f4187b56
BA		 3956 .get_variants = e1000_get_variants_ich8lan,
3957 .mac_ops = &ich8_mac_ops,
3958 .phy_ops = &ich8_phy_ops,
3959 .nvm_ops = &ich8_nvm_ops,
3960};
a4f58f54
BA		 3961
3962struct e1000_info e1000_pch_info = {
3963 .mac = e1000_pchlan,
3964 .flags = FLAG_IS_ICH
3965 | FLAG_HAS_WOL
3966 | FLAG_RX_CSUM_ENABLED
3967 | FLAG_HAS_CTRLEXT_ON_LOAD
3968 | FLAG_HAS_AMT
3969 | FLAG_HAS_FLASH
3970 | FLAG_HAS_JUMBO_FRAMES
38eb394e 3971 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
a4f58f54 3972 | FLAG_APME_IN_WUC,
8c7bbb92 3973 .flags2 = FLAG2_HAS_PHY_STATS,
a4f58f54
BA		 3974 .pba = 26,
3975 .max_hw_frame_size = 4096,
3976 .get_variants = e1000_get_variants_ich8lan,
3977 .mac_ops = &ich8_mac_ops,
3978 .phy_ops = &ich8_phy_ops,
3979 .nvm_ops = &ich8_nvm_ops,
3980};
d3738bb8
BA		 3981
3982struct e1000_info e1000_pch2_info = {
3983 .mac = e1000_pch2lan,
3984 .flags = FLAG_IS_ICH
3985 | FLAG_HAS_WOL
3986 | FLAG_RX_CSUM_ENABLED
3987 | FLAG_HAS_CTRLEXT_ON_LOAD
3988 | FLAG_HAS_AMT
3989 | FLAG_HAS_FLASH
3990 | FLAG_HAS_JUMBO_FRAMES
3991 | FLAG_APME_IN_WUC,
e52997f9
BA		 3992 .flags2 = FLAG2_HAS_PHY_STATS
3993 | FLAG2_HAS_EEE,
828bac87 3994 .pba = 26,
d3738bb8
BA		 3995 .max_hw_frame_size = DEFAULT_JUMBO,
3996 .get_variants = e1000_get_variants_ich8lan,
3997 .mac_ops = &ich8_mac_ops,
3998 .phy_ops = &ich8_phy_ops,
3999 .nvm_ops = &ich8_nvm_ops,
4000};
Linux kernel - Deliverables
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