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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
c7e54b1b | 4 | Copyright(c) 1999 - 2009 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/delay.h> | |
30 | ||
31 | #include "e1000.h" | |
32 | ||
33 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); | |
34 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |
35 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); | |
36 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); | |
97ac8cae BA |
37 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); |
38 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
39 | u16 *data, bool read); | |
a4f58f54 BA |
40 | static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
41 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
42 | u16 *data, bool read); | |
bc7f75fa AK |
43 | |
44 | /* Cable length tables */ | |
45 | static const u16 e1000_m88_cable_length_table[] = | |
46 | { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
eb656d45 BA |
47 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
48 | ARRAY_SIZE(e1000_m88_cable_length_table) | |
bc7f75fa AK |
49 | |
50 | static const u16 e1000_igp_2_cable_length_table[] = | |
51 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, | |
52 | 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, | |
53 | 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, | |
54 | 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, | |
55 | 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, | |
56 | 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, | |
57 | 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, | |
58 | 124}; | |
59 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ | |
c00acf46 | 60 | ARRAY_SIZE(e1000_igp_2_cable_length_table) |
bc7f75fa | 61 | |
a4f58f54 BA |
62 | #define BM_PHY_REG_PAGE(offset) \ |
63 | ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) | |
64 | #define BM_PHY_REG_NUM(offset) \ | |
65 | ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ | |
66 | (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ | |
67 | ~MAX_PHY_REG_ADDRESS))) | |
68 | ||
69 | #define HV_INTC_FC_PAGE_START 768 | |
70 | #define I82578_ADDR_REG 29 | |
71 | #define I82577_ADDR_REG 16 | |
72 | #define I82577_CFG_REG 22 | |
73 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) | |
74 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ | |
75 | #define I82577_CTRL_REG 23 | |
a4f58f54 BA |
76 | |
77 | /* 82577 specific PHY registers */ | |
78 | #define I82577_PHY_CTRL_2 18 | |
79 | #define I82577_PHY_STATUS_2 26 | |
80 | #define I82577_PHY_DIAG_STATUS 31 | |
81 | ||
82 | /* I82577 PHY Status 2 */ | |
83 | #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 | |
84 | #define I82577_PHY_STATUS2_MDIX 0x0800 | |
85 | #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 | |
86 | #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 | |
87 | ||
88 | /* I82577 PHY Control 2 */ | |
89 | #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 | |
90 | #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 | |
91 | ||
92 | /* I82577 PHY Diagnostics Status */ | |
93 | #define I82577_DSTATUS_CABLE_LENGTH 0x03FC | |
94 | #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 | |
95 | ||
96 | /* BM PHY Copper Specific Control 1 */ | |
97 | #define BM_CS_CTRL1 16 | |
98 | ||
a4f58f54 BA |
99 | #define HV_MUX_DATA_CTRL PHY_REG(776, 16) |
100 | #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 | |
101 | #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 | |
102 | ||
bc7f75fa AK |
103 | /** |
104 | * e1000e_check_reset_block_generic - Check if PHY reset is blocked | |
105 | * @hw: pointer to the HW structure | |
106 | * | |
107 | * Read the PHY management control register and check whether a PHY reset | |
108 | * is blocked. If a reset is not blocked return 0, otherwise | |
109 | * return E1000_BLK_PHY_RESET (12). | |
110 | **/ | |
111 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) | |
112 | { | |
113 | u32 manc; | |
114 | ||
115 | manc = er32(MANC); | |
116 | ||
117 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
118 | E1000_BLK_PHY_RESET : 0; | |
119 | } | |
120 | ||
121 | /** | |
122 | * e1000e_get_phy_id - Retrieve the PHY ID and revision | |
123 | * @hw: pointer to the HW structure | |
124 | * | |
125 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
126 | * revision in the hardware structure. | |
127 | **/ | |
128 | s32 e1000e_get_phy_id(struct e1000_hw *hw) | |
129 | { | |
130 | struct e1000_phy_info *phy = &hw->phy; | |
a4f58f54 | 131 | s32 ret_val = 0; |
bc7f75fa | 132 | u16 phy_id; |
a4f58f54 | 133 | u16 retry_count = 0; |
bc7f75fa | 134 | |
94d8186a | 135 | if (!(phy->ops.read_reg)) |
a4f58f54 | 136 | goto out; |
bc7f75fa | 137 | |
a4f58f54 BA |
138 | while (retry_count < 2) { |
139 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); | |
140 | if (ret_val) | |
141 | goto out; | |
bc7f75fa | 142 | |
a4f58f54 BA |
143 | phy->id = (u32)(phy_id << 16); |
144 | udelay(20); | |
145 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
146 | if (ret_val) | |
147 | goto out; | |
bc7f75fa | 148 | |
a4f58f54 BA |
149 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
150 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
151 | ||
152 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) | |
153 | goto out; | |
154 | ||
155 | /* | |
5ff5b664 BA |
156 | * If the PHY ID is still unknown, we may have an 82577 |
157 | * without link. We will try again after setting Slow MDIC | |
158 | * mode. No harm in trying again in this case since the PHY | |
159 | * ID is unknown at this point anyway. | |
a4f58f54 | 160 | */ |
94d8186a | 161 | ret_val = phy->ops.acquire(hw); |
5ccdcecb BA |
162 | if (ret_val) |
163 | goto out; | |
a4f58f54 BA |
164 | ret_val = e1000_set_mdio_slow_mode_hv(hw, true); |
165 | if (ret_val) | |
166 | goto out; | |
94d8186a | 167 | phy->ops.release(hw); |
a4f58f54 BA |
168 | |
169 | retry_count++; | |
170 | } | |
171 | out: | |
172 | /* Revert to MDIO fast mode, if applicable */ | |
5ccdcecb | 173 | if (retry_count) { |
94d8186a | 174 | ret_val = phy->ops.acquire(hw); |
5ccdcecb BA |
175 | if (ret_val) |
176 | return ret_val; | |
a4f58f54 | 177 | ret_val = e1000_set_mdio_slow_mode_hv(hw, false); |
94d8186a | 178 | phy->ops.release(hw); |
5ccdcecb | 179 | } |
a4f58f54 BA |
180 | |
181 | return ret_val; | |
bc7f75fa AK |
182 | } |
183 | ||
184 | /** | |
185 | * e1000e_phy_reset_dsp - Reset PHY DSP | |
186 | * @hw: pointer to the HW structure | |
187 | * | |
188 | * Reset the digital signal processor. | |
189 | **/ | |
190 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) | |
191 | { | |
192 | s32 ret_val; | |
193 | ||
194 | ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); | |
195 | if (ret_val) | |
196 | return ret_val; | |
197 | ||
198 | return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); | |
199 | } | |
200 | ||
201 | /** | |
2d9498f3 | 202 | * e1000e_read_phy_reg_mdic - Read MDI control register |
bc7f75fa AK |
203 | * @hw: pointer to the HW structure |
204 | * @offset: register offset to be read | |
205 | * @data: pointer to the read data | |
206 | * | |
489815ce | 207 | * Reads the MDI control register in the PHY at offset and stores the |
bc7f75fa AK |
208 | * information read to data. |
209 | **/ | |
2d9498f3 | 210 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
bc7f75fa AK |
211 | { |
212 | struct e1000_phy_info *phy = &hw->phy; | |
213 | u32 i, mdic = 0; | |
214 | ||
215 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 216 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
217 | return -E1000_ERR_PARAM; |
218 | } | |
219 | ||
ad68076e BA |
220 | /* |
221 | * Set up Op-code, Phy Address, and register offset in the MDI | |
bc7f75fa AK |
222 | * Control register. The MAC will take care of interfacing with the |
223 | * PHY to retrieve the desired data. | |
224 | */ | |
225 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
226 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
227 | (E1000_MDIC_OP_READ)); | |
228 | ||
229 | ew32(MDIC, mdic); | |
230 | ||
ad68076e BA |
231 | /* |
232 | * Poll the ready bit to see if the MDI read completed | |
233 | * Increasing the time out as testing showed failures with | |
234 | * the lower time out | |
235 | */ | |
2d9498f3 | 236 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
bc7f75fa AK |
237 | udelay(50); |
238 | mdic = er32(MDIC); | |
239 | if (mdic & E1000_MDIC_READY) | |
240 | break; | |
241 | } | |
242 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 243 | e_dbg("MDI Read did not complete\n"); |
bc7f75fa AK |
244 | return -E1000_ERR_PHY; |
245 | } | |
246 | if (mdic & E1000_MDIC_ERROR) { | |
3bb99fe2 | 247 | e_dbg("MDI Error\n"); |
bc7f75fa AK |
248 | return -E1000_ERR_PHY; |
249 | } | |
250 | *data = (u16) mdic; | |
251 | ||
252 | return 0; | |
253 | } | |
254 | ||
255 | /** | |
2d9498f3 | 256 | * e1000e_write_phy_reg_mdic - Write MDI control register |
bc7f75fa AK |
257 | * @hw: pointer to the HW structure |
258 | * @offset: register offset to write to | |
259 | * @data: data to write to register at offset | |
260 | * | |
261 | * Writes data to MDI control register in the PHY at offset. | |
262 | **/ | |
2d9498f3 | 263 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
bc7f75fa AK |
264 | { |
265 | struct e1000_phy_info *phy = &hw->phy; | |
266 | u32 i, mdic = 0; | |
267 | ||
268 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 269 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
270 | return -E1000_ERR_PARAM; |
271 | } | |
272 | ||
ad68076e BA |
273 | /* |
274 | * Set up Op-code, Phy Address, and register offset in the MDI | |
bc7f75fa AK |
275 | * Control register. The MAC will take care of interfacing with the |
276 | * PHY to retrieve the desired data. | |
277 | */ | |
278 | mdic = (((u32)data) | | |
279 | (offset << E1000_MDIC_REG_SHIFT) | | |
280 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
281 | (E1000_MDIC_OP_WRITE)); | |
282 | ||
283 | ew32(MDIC, mdic); | |
284 | ||
2d9498f3 DG |
285 | /* |
286 | * Poll the ready bit to see if the MDI read completed | |
287 | * Increasing the time out as testing showed failures with | |
288 | * the lower time out | |
289 | */ | |
290 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
291 | udelay(50); | |
bc7f75fa AK |
292 | mdic = er32(MDIC); |
293 | if (mdic & E1000_MDIC_READY) | |
294 | break; | |
295 | } | |
296 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 297 | e_dbg("MDI Write did not complete\n"); |
bc7f75fa AK |
298 | return -E1000_ERR_PHY; |
299 | } | |
2d9498f3 | 300 | if (mdic & E1000_MDIC_ERROR) { |
3bb99fe2 | 301 | e_dbg("MDI Error\n"); |
2d9498f3 DG |
302 | return -E1000_ERR_PHY; |
303 | } | |
bc7f75fa AK |
304 | |
305 | return 0; | |
306 | } | |
307 | ||
308 | /** | |
309 | * e1000e_read_phy_reg_m88 - Read m88 PHY register | |
310 | * @hw: pointer to the HW structure | |
311 | * @offset: register offset to be read | |
312 | * @data: pointer to the read data | |
313 | * | |
314 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
315 | * and storing the retrieved information in data. Release any acquired | |
316 | * semaphores before exiting. | |
317 | **/ | |
318 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) | |
319 | { | |
320 | s32 ret_val; | |
321 | ||
94d8186a | 322 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
323 | if (ret_val) |
324 | return ret_val; | |
325 | ||
2d9498f3 DG |
326 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
327 | data); | |
bc7f75fa | 328 | |
94d8186a | 329 | hw->phy.ops.release(hw); |
bc7f75fa AK |
330 | |
331 | return ret_val; | |
332 | } | |
333 | ||
334 | /** | |
335 | * e1000e_write_phy_reg_m88 - Write m88 PHY register | |
336 | * @hw: pointer to the HW structure | |
337 | * @offset: register offset to write to | |
338 | * @data: data to write at register offset | |
339 | * | |
340 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
341 | * at the offset. Release any acquired semaphores before exiting. | |
342 | **/ | |
343 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) | |
344 | { | |
345 | s32 ret_val; | |
346 | ||
94d8186a | 347 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
348 | if (ret_val) |
349 | return ret_val; | |
350 | ||
2d9498f3 DG |
351 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
352 | data); | |
bc7f75fa | 353 | |
94d8186a | 354 | hw->phy.ops.release(hw); |
bc7f75fa AK |
355 | |
356 | return ret_val; | |
357 | } | |
358 | ||
359 | /** | |
5ccdcecb | 360 | * __e1000e_read_phy_reg_igp - Read igp PHY register |
bc7f75fa AK |
361 | * @hw: pointer to the HW structure |
362 | * @offset: register offset to be read | |
363 | * @data: pointer to the read data | |
5ccdcecb | 364 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
365 | * |
366 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 367 | * and stores the retrieved information in data. Release any acquired |
bc7f75fa AK |
368 | * semaphores before exiting. |
369 | **/ | |
5ccdcecb BA |
370 | static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
371 | bool locked) | |
bc7f75fa | 372 | { |
5ccdcecb | 373 | s32 ret_val = 0; |
bc7f75fa | 374 | |
5ccdcecb | 375 | if (!locked) { |
94d8186a | 376 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
377 | goto out; |
378 | ||
94d8186a | 379 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
380 | if (ret_val) |
381 | goto out; | |
382 | } | |
bc7f75fa AK |
383 | |
384 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2d9498f3 DG |
385 | ret_val = e1000e_write_phy_reg_mdic(hw, |
386 | IGP01E1000_PHY_PAGE_SELECT, | |
387 | (u16)offset); | |
5ccdcecb BA |
388 | if (ret_val) |
389 | goto release; | |
bc7f75fa AK |
390 | } |
391 | ||
2d9498f3 | 392 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
5ccdcecb | 393 | data); |
bc7f75fa | 394 | |
5ccdcecb BA |
395 | release: |
396 | if (!locked) | |
94d8186a | 397 | hw->phy.ops.release(hw); |
5ccdcecb | 398 | out: |
bc7f75fa AK |
399 | return ret_val; |
400 | } | |
401 | ||
5ccdcecb BA |
402 | /** |
403 | * e1000e_read_phy_reg_igp - Read igp PHY register | |
404 | * @hw: pointer to the HW structure | |
405 | * @offset: register offset to be read | |
406 | * @data: pointer to the read data | |
407 | * | |
408 | * Acquires semaphore then reads the PHY register at offset and stores the | |
409 | * retrieved information in data. | |
410 | * Release the acquired semaphore before exiting. | |
411 | **/ | |
412 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
413 | { | |
414 | return __e1000e_read_phy_reg_igp(hw, offset, data, false); | |
415 | } | |
416 | ||
417 | /** | |
418 | * e1000e_read_phy_reg_igp_locked - Read igp PHY register | |
419 | * @hw: pointer to the HW structure | |
420 | * @offset: register offset to be read | |
421 | * @data: pointer to the read data | |
422 | * | |
423 | * Reads the PHY register at offset and stores the retrieved information | |
424 | * in data. Assumes semaphore already acquired. | |
425 | **/ | |
426 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
427 | { | |
428 | return __e1000e_read_phy_reg_igp(hw, offset, data, true); | |
429 | } | |
430 | ||
bc7f75fa AK |
431 | /** |
432 | * e1000e_write_phy_reg_igp - Write igp PHY register | |
433 | * @hw: pointer to the HW structure | |
434 | * @offset: register offset to write to | |
435 | * @data: data to write at register offset | |
5ccdcecb | 436 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
437 | * |
438 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
439 | * at the offset. Release any acquired semaphores before exiting. | |
440 | **/ | |
5ccdcecb BA |
441 | static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
442 | bool locked) | |
bc7f75fa | 443 | { |
5ccdcecb | 444 | s32 ret_val = 0; |
bc7f75fa | 445 | |
5ccdcecb | 446 | if (!locked) { |
94d8186a | 447 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
448 | goto out; |
449 | ||
94d8186a | 450 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
451 | if (ret_val) |
452 | goto out; | |
453 | } | |
bc7f75fa AK |
454 | |
455 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2d9498f3 DG |
456 | ret_val = e1000e_write_phy_reg_mdic(hw, |
457 | IGP01E1000_PHY_PAGE_SELECT, | |
458 | (u16)offset); | |
5ccdcecb BA |
459 | if (ret_val) |
460 | goto release; | |
bc7f75fa AK |
461 | } |
462 | ||
2d9498f3 DG |
463 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
464 | data); | |
bc7f75fa | 465 | |
5ccdcecb BA |
466 | release: |
467 | if (!locked) | |
94d8186a | 468 | hw->phy.ops.release(hw); |
bc7f75fa | 469 | |
5ccdcecb | 470 | out: |
bc7f75fa AK |
471 | return ret_val; |
472 | } | |
473 | ||
474 | /** | |
5ccdcecb BA |
475 | * e1000e_write_phy_reg_igp - Write igp PHY register |
476 | * @hw: pointer to the HW structure | |
477 | * @offset: register offset to write to | |
478 | * @data: data to write at register offset | |
479 | * | |
480 | * Acquires semaphore then writes the data to PHY register | |
481 | * at the offset. Release any acquired semaphores before exiting. | |
482 | **/ | |
483 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
484 | { | |
485 | return __e1000e_write_phy_reg_igp(hw, offset, data, false); | |
486 | } | |
487 | ||
488 | /** | |
489 | * e1000e_write_phy_reg_igp_locked - Write igp PHY register | |
490 | * @hw: pointer to the HW structure | |
491 | * @offset: register offset to write to | |
492 | * @data: data to write at register offset | |
493 | * | |
494 | * Writes the data to PHY register at the offset. | |
495 | * Assumes semaphore already acquired. | |
496 | **/ | |
497 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
498 | { | |
499 | return __e1000e_write_phy_reg_igp(hw, offset, data, true); | |
500 | } | |
501 | ||
502 | /** | |
503 | * __e1000_read_kmrn_reg - Read kumeran register | |
bc7f75fa AK |
504 | * @hw: pointer to the HW structure |
505 | * @offset: register offset to be read | |
506 | * @data: pointer to the read data | |
5ccdcecb | 507 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
508 | * |
509 | * Acquires semaphore, if necessary. Then reads the PHY register at offset | |
510 | * using the kumeran interface. The information retrieved is stored in data. | |
511 | * Release any acquired semaphores before exiting. | |
512 | **/ | |
5ccdcecb BA |
513 | static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
514 | bool locked) | |
bc7f75fa AK |
515 | { |
516 | u32 kmrnctrlsta; | |
5ccdcecb | 517 | s32 ret_val = 0; |
bc7f75fa | 518 | |
5ccdcecb | 519 | if (!locked) { |
94d8186a | 520 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
521 | goto out; |
522 | ||
94d8186a | 523 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
524 | if (ret_val) |
525 | goto out; | |
526 | } | |
bc7f75fa AK |
527 | |
528 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
529 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
530 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
531 | ||
532 | udelay(2); | |
533 | ||
534 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
535 | *data = (u16)kmrnctrlsta; | |
536 | ||
5ccdcecb | 537 | if (!locked) |
94d8186a | 538 | hw->phy.ops.release(hw); |
bc7f75fa | 539 | |
5ccdcecb | 540 | out: |
bc7f75fa AK |
541 | return ret_val; |
542 | } | |
543 | ||
544 | /** | |
5ccdcecb BA |
545 | * e1000e_read_kmrn_reg - Read kumeran register |
546 | * @hw: pointer to the HW structure | |
547 | * @offset: register offset to be read | |
548 | * @data: pointer to the read data | |
549 | * | |
550 | * Acquires semaphore then reads the PHY register at offset using the | |
551 | * kumeran interface. The information retrieved is stored in data. | |
552 | * Release the acquired semaphore before exiting. | |
553 | **/ | |
554 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
555 | { | |
556 | return __e1000_read_kmrn_reg(hw, offset, data, false); | |
557 | } | |
558 | ||
559 | /** | |
1d5846b9 | 560 | * e1000e_read_kmrn_reg_locked - Read kumeran register |
5ccdcecb BA |
561 | * @hw: pointer to the HW structure |
562 | * @offset: register offset to be read | |
563 | * @data: pointer to the read data | |
564 | * | |
565 | * Reads the PHY register at offset using the kumeran interface. The | |
566 | * information retrieved is stored in data. | |
567 | * Assumes semaphore already acquired. | |
568 | **/ | |
1d5846b9 | 569 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
5ccdcecb BA |
570 | { |
571 | return __e1000_read_kmrn_reg(hw, offset, data, true); | |
572 | } | |
573 | ||
574 | /** | |
575 | * __e1000_write_kmrn_reg - Write kumeran register | |
bc7f75fa AK |
576 | * @hw: pointer to the HW structure |
577 | * @offset: register offset to write to | |
578 | * @data: data to write at register offset | |
5ccdcecb | 579 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
580 | * |
581 | * Acquires semaphore, if necessary. Then write the data to PHY register | |
582 | * at the offset using the kumeran interface. Release any acquired semaphores | |
583 | * before exiting. | |
584 | **/ | |
5ccdcecb BA |
585 | static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
586 | bool locked) | |
bc7f75fa AK |
587 | { |
588 | u32 kmrnctrlsta; | |
5ccdcecb | 589 | s32 ret_val = 0; |
bc7f75fa | 590 | |
5ccdcecb | 591 | if (!locked) { |
94d8186a | 592 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
593 | goto out; |
594 | ||
94d8186a | 595 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
596 | if (ret_val) |
597 | goto out; | |
598 | } | |
bc7f75fa AK |
599 | |
600 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
601 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
602 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
603 | ||
604 | udelay(2); | |
bc7f75fa | 605 | |
5ccdcecb | 606 | if (!locked) |
94d8186a | 607 | hw->phy.ops.release(hw); |
5ccdcecb BA |
608 | |
609 | out: | |
bc7f75fa AK |
610 | return ret_val; |
611 | } | |
612 | ||
5ccdcecb BA |
613 | /** |
614 | * e1000e_write_kmrn_reg - Write kumeran register | |
615 | * @hw: pointer to the HW structure | |
616 | * @offset: register offset to write to | |
617 | * @data: data to write at register offset | |
618 | * | |
619 | * Acquires semaphore then writes the data to the PHY register at the offset | |
620 | * using the kumeran interface. Release the acquired semaphore before exiting. | |
621 | **/ | |
622 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
623 | { | |
624 | return __e1000_write_kmrn_reg(hw, offset, data, false); | |
625 | } | |
626 | ||
627 | /** | |
1d5846b9 | 628 | * e1000e_write_kmrn_reg_locked - Write kumeran register |
5ccdcecb BA |
629 | * @hw: pointer to the HW structure |
630 | * @offset: register offset to write to | |
631 | * @data: data to write at register offset | |
632 | * | |
633 | * Write the data to PHY register at the offset using the kumeran interface. | |
634 | * Assumes semaphore already acquired. | |
635 | **/ | |
1d5846b9 | 636 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
5ccdcecb BA |
637 | { |
638 | return __e1000_write_kmrn_reg(hw, offset, data, true); | |
639 | } | |
640 | ||
a4f58f54 BA |
641 | /** |
642 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link | |
643 | * @hw: pointer to the HW structure | |
644 | * | |
645 | * Sets up Carrier-sense on Transmit and downshift values. | |
646 | **/ | |
647 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) | |
648 | { | |
649 | struct e1000_phy_info *phy = &hw->phy; | |
650 | s32 ret_val; | |
651 | u16 phy_data; | |
652 | ||
653 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
94d8186a | 654 | ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); |
a4f58f54 BA |
655 | if (ret_val) |
656 | goto out; | |
657 | ||
658 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; | |
659 | ||
660 | /* Enable downshift */ | |
661 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; | |
662 | ||
94d8186a | 663 | ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); |
a4f58f54 BA |
664 | |
665 | out: | |
666 | return ret_val; | |
667 | } | |
668 | ||
bc7f75fa AK |
669 | /** |
670 | * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link | |
671 | * @hw: pointer to the HW structure | |
672 | * | |
673 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
674 | * and downshift values are set also. | |
675 | **/ | |
676 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) | |
677 | { | |
678 | struct e1000_phy_info *phy = &hw->phy; | |
679 | s32 ret_val; | |
680 | u16 phy_data; | |
681 | ||
ad68076e | 682 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
bc7f75fa AK |
683 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
684 | if (ret_val) | |
685 | return ret_val; | |
686 | ||
a4f58f54 BA |
687 | /* For BM PHY this bit is downshift enable */ |
688 | if (phy->type != e1000_phy_bm) | |
2d9498f3 | 689 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
bc7f75fa | 690 | |
ad68076e BA |
691 | /* |
692 | * Options: | |
bc7f75fa AK |
693 | * MDI/MDI-X = 0 (default) |
694 | * 0 - Auto for all speeds | |
695 | * 1 - MDI mode | |
696 | * 2 - MDI-X mode | |
697 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
698 | */ | |
699 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
700 | ||
701 | switch (phy->mdix) { | |
702 | case 1: | |
703 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
704 | break; | |
705 | case 2: | |
706 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
707 | break; | |
708 | case 3: | |
709 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
710 | break; | |
711 | case 0: | |
712 | default: | |
713 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
714 | break; | |
715 | } | |
716 | ||
ad68076e BA |
717 | /* |
718 | * Options: | |
bc7f75fa AK |
719 | * disable_polarity_correction = 0 (default) |
720 | * Automatic Correction for Reversed Cable Polarity | |
721 | * 0 - Disabled | |
722 | * 1 - Enabled | |
723 | */ | |
724 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
725 | if (phy->disable_polarity_correction == 1) | |
726 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
727 | ||
97ac8cae BA |
728 | /* Enable downshift on BM (disabled by default) */ |
729 | if (phy->type == e1000_phy_bm) | |
730 | phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; | |
731 | ||
bc7f75fa AK |
732 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
733 | if (ret_val) | |
734 | return ret_val; | |
735 | ||
4662e82b BA |
736 | if ((phy->type == e1000_phy_m88) && |
737 | (phy->revision < E1000_REVISION_4) && | |
738 | (phy->id != BME1000_E_PHY_ID_R2)) { | |
ad68076e BA |
739 | /* |
740 | * Force TX_CLK in the Extended PHY Specific Control Register | |
bc7f75fa AK |
741 | * to 25MHz clock. |
742 | */ | |
743 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
744 | if (ret_val) | |
745 | return ret_val; | |
746 | ||
747 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
748 | ||
749 | if ((phy->revision == 2) && | |
750 | (phy->id == M88E1111_I_PHY_ID)) { | |
751 | /* 82573L PHY - set the downshift counter to 5x. */ | |
752 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
753 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
754 | } else { | |
755 | /* Configure Master and Slave downshift values */ | |
756 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
757 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
758 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
759 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
760 | } | |
761 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
762 | if (ret_val) | |
763 | return ret_val; | |
764 | } | |
765 | ||
4662e82b BA |
766 | if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
767 | /* Set PHY page 0, register 29 to 0x0003 */ | |
768 | ret_val = e1e_wphy(hw, 29, 0x0003); | |
769 | if (ret_val) | |
770 | return ret_val; | |
771 | ||
772 | /* Set PHY page 0, register 30 to 0x0000 */ | |
773 | ret_val = e1e_wphy(hw, 30, 0x0000); | |
774 | if (ret_val) | |
775 | return ret_val; | |
776 | } | |
777 | ||
bc7f75fa AK |
778 | /* Commit the changes. */ |
779 | ret_val = e1000e_commit_phy(hw); | |
a4f58f54 | 780 | if (ret_val) { |
3bb99fe2 | 781 | e_dbg("Error committing the PHY changes\n"); |
a4f58f54 BA |
782 | return ret_val; |
783 | } | |
bc7f75fa | 784 | |
a4f58f54 | 785 | if (phy->type == e1000_phy_82578) { |
94d8186a | 786 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
a4f58f54 BA |
787 | &phy_data); |
788 | if (ret_val) | |
789 | return ret_val; | |
790 | ||
791 | /* 82578 PHY - set the downshift count to 1x. */ | |
792 | phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; | |
793 | phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
94d8186a | 794 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
a4f58f54 BA |
795 | phy_data); |
796 | if (ret_val) | |
797 | return ret_val; | |
798 | } | |
799 | ||
800 | return 0; | |
bc7f75fa AK |
801 | } |
802 | ||
803 | /** | |
804 | * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link | |
805 | * @hw: pointer to the HW structure | |
806 | * | |
807 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
808 | * igp PHY's. | |
809 | **/ | |
810 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) | |
811 | { | |
812 | struct e1000_phy_info *phy = &hw->phy; | |
813 | s32 ret_val; | |
814 | u16 data; | |
815 | ||
816 | ret_val = e1000_phy_hw_reset(hw); | |
817 | if (ret_val) { | |
3bb99fe2 | 818 | e_dbg("Error resetting the PHY.\n"); |
bc7f75fa AK |
819 | return ret_val; |
820 | } | |
821 | ||
2d9498f3 DG |
822 | /* |
823 | * Wait 100ms for MAC to configure PHY from NVM settings, to avoid | |
824 | * timeout issues when LFS is enabled. | |
825 | */ | |
826 | msleep(100); | |
bc7f75fa AK |
827 | |
828 | /* disable lplu d0 during driver init */ | |
564ea9bb | 829 | ret_val = e1000_set_d0_lplu_state(hw, false); |
bc7f75fa | 830 | if (ret_val) { |
3bb99fe2 | 831 | e_dbg("Error Disabling LPLU D0\n"); |
bc7f75fa AK |
832 | return ret_val; |
833 | } | |
834 | /* Configure mdi-mdix settings */ | |
835 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); | |
836 | if (ret_val) | |
837 | return ret_val; | |
838 | ||
839 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
840 | ||
841 | switch (phy->mdix) { | |
842 | case 1: | |
843 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
844 | break; | |
845 | case 2: | |
846 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
847 | break; | |
848 | case 0: | |
849 | default: | |
850 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
851 | break; | |
852 | } | |
853 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); | |
854 | if (ret_val) | |
855 | return ret_val; | |
856 | ||
857 | /* set auto-master slave resolution settings */ | |
858 | if (hw->mac.autoneg) { | |
ad68076e BA |
859 | /* |
860 | * when autonegotiation advertisement is only 1000Mbps then we | |
bc7f75fa | 861 | * should disable SmartSpeed and enable Auto MasterSlave |
ad68076e BA |
862 | * resolution as hardware default. |
863 | */ | |
bc7f75fa AK |
864 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
865 | /* Disable SmartSpeed */ | |
866 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 867 | &data); |
bc7f75fa AK |
868 | if (ret_val) |
869 | return ret_val; | |
870 | ||
871 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
872 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 873 | data); |
bc7f75fa AK |
874 | if (ret_val) |
875 | return ret_val; | |
876 | ||
877 | /* Set auto Master/Slave resolution process */ | |
878 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); | |
879 | if (ret_val) | |
880 | return ret_val; | |
881 | ||
882 | data &= ~CR_1000T_MS_ENABLE; | |
883 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); | |
884 | if (ret_val) | |
885 | return ret_val; | |
886 | } | |
887 | ||
888 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); | |
889 | if (ret_val) | |
890 | return ret_val; | |
891 | ||
892 | /* load defaults for future use */ | |
893 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? | |
894 | ((data & CR_1000T_MS_VALUE) ? | |
895 | e1000_ms_force_master : | |
896 | e1000_ms_force_slave) : | |
897 | e1000_ms_auto; | |
898 | ||
899 | switch (phy->ms_type) { | |
900 | case e1000_ms_force_master: | |
901 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
902 | break; | |
903 | case e1000_ms_force_slave: | |
904 | data |= CR_1000T_MS_ENABLE; | |
905 | data &= ~(CR_1000T_MS_VALUE); | |
906 | break; | |
907 | case e1000_ms_auto: | |
908 | data &= ~CR_1000T_MS_ENABLE; | |
909 | default: | |
910 | break; | |
911 | } | |
912 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); | |
913 | } | |
914 | ||
915 | return ret_val; | |
916 | } | |
917 | ||
918 | /** | |
919 | * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation | |
920 | * @hw: pointer to the HW structure | |
921 | * | |
922 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
923 | * register and if the PHY is already setup for auto-negotiation, then | |
924 | * return successful. Otherwise, setup advertisement and flow control to | |
925 | * the appropriate values for the wanted auto-negotiation. | |
926 | **/ | |
927 | static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) | |
928 | { | |
929 | struct e1000_phy_info *phy = &hw->phy; | |
930 | s32 ret_val; | |
931 | u16 mii_autoneg_adv_reg; | |
932 | u16 mii_1000t_ctrl_reg = 0; | |
933 | ||
934 | phy->autoneg_advertised &= phy->autoneg_mask; | |
935 | ||
936 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
937 | ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | |
938 | if (ret_val) | |
939 | return ret_val; | |
940 | ||
941 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
942 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
943 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | |
944 | if (ret_val) | |
945 | return ret_val; | |
946 | } | |
947 | ||
ad68076e BA |
948 | /* |
949 | * Need to parse both autoneg_advertised and fc and set up | |
bc7f75fa AK |
950 | * the appropriate PHY registers. First we will parse for |
951 | * autoneg_advertised software override. Since we can advertise | |
952 | * a plethora of combinations, we need to check each bit | |
953 | * individually. | |
954 | */ | |
955 | ||
ad68076e BA |
956 | /* |
957 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
bc7f75fa AK |
958 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
959 | * the 1000Base-T Control Register (Address 9). | |
960 | */ | |
961 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | | |
962 | NWAY_AR_100TX_HD_CAPS | | |
963 | NWAY_AR_10T_FD_CAPS | | |
964 | NWAY_AR_10T_HD_CAPS); | |
965 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); | |
966 | ||
3bb99fe2 | 967 | e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
bc7f75fa AK |
968 | |
969 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
970 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
3bb99fe2 | 971 | e_dbg("Advertise 10mb Half duplex\n"); |
bc7f75fa AK |
972 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
973 | } | |
974 | ||
975 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
976 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
3bb99fe2 | 977 | e_dbg("Advertise 10mb Full duplex\n"); |
bc7f75fa AK |
978 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
979 | } | |
980 | ||
981 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
982 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
3bb99fe2 | 983 | e_dbg("Advertise 100mb Half duplex\n"); |
bc7f75fa AK |
984 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
985 | } | |
986 | ||
987 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
988 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
3bb99fe2 | 989 | e_dbg("Advertise 100mb Full duplex\n"); |
bc7f75fa AK |
990 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
991 | } | |
992 | ||
993 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
994 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
3bb99fe2 | 995 | e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
bc7f75fa AK |
996 | |
997 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
998 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
3bb99fe2 | 999 | e_dbg("Advertise 1000mb Full duplex\n"); |
bc7f75fa AK |
1000 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
1001 | } | |
1002 | ||
ad68076e BA |
1003 | /* |
1004 | * Check for a software override of the flow control settings, and | |
bc7f75fa AK |
1005 | * setup the PHY advertisement registers accordingly. If |
1006 | * auto-negotiation is enabled, then software will have to set the | |
1007 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
1008 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- | |
1009 | * negotiation. | |
1010 | * | |
1011 | * The possible values of the "fc" parameter are: | |
1012 | * 0: Flow control is completely disabled | |
1013 | * 1: Rx flow control is enabled (we can receive pause frames | |
1014 | * but not send pause frames). | |
1015 | * 2: Tx flow control is enabled (we can send pause frames | |
1016 | * but we do not support receiving pause frames). | |
ad68076e | 1017 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
bc7f75fa AK |
1018 | * other: No software override. The flow control configuration |
1019 | * in the EEPROM is used. | |
1020 | */ | |
5c48ef3e | 1021 | switch (hw->fc.current_mode) { |
bc7f75fa | 1022 | case e1000_fc_none: |
ad68076e BA |
1023 | /* |
1024 | * Flow control (Rx & Tx) is completely disabled by a | |
bc7f75fa AK |
1025 | * software over-ride. |
1026 | */ | |
1027 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1028 | break; | |
1029 | case e1000_fc_rx_pause: | |
ad68076e BA |
1030 | /* |
1031 | * Rx Flow control is enabled, and Tx Flow control is | |
bc7f75fa | 1032 | * disabled, by a software over-ride. |
ad68076e BA |
1033 | * |
1034 | * Since there really isn't a way to advertise that we are | |
1035 | * capable of Rx Pause ONLY, we will advertise that we | |
1036 | * support both symmetric and asymmetric Rx PAUSE. Later | |
bc7f75fa AK |
1037 | * (in e1000e_config_fc_after_link_up) we will disable the |
1038 | * hw's ability to send PAUSE frames. | |
1039 | */ | |
1040 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1041 | break; | |
1042 | case e1000_fc_tx_pause: | |
ad68076e BA |
1043 | /* |
1044 | * Tx Flow control is enabled, and Rx Flow control is | |
bc7f75fa AK |
1045 | * disabled, by a software over-ride. |
1046 | */ | |
1047 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
1048 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
1049 | break; | |
1050 | case e1000_fc_full: | |
ad68076e BA |
1051 | /* |
1052 | * Flow control (both Rx and Tx) is enabled by a software | |
bc7f75fa AK |
1053 | * over-ride. |
1054 | */ | |
1055 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1056 | break; | |
1057 | default: | |
3bb99fe2 | 1058 | e_dbg("Flow control param set incorrectly\n"); |
bc7f75fa AK |
1059 | ret_val = -E1000_ERR_CONFIG; |
1060 | return ret_val; | |
1061 | } | |
1062 | ||
1063 | ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | |
1064 | if (ret_val) | |
1065 | return ret_val; | |
1066 | ||
3bb99fe2 | 1067 | e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
bc7f75fa AK |
1068 | |
1069 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
1070 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); | |
1071 | } | |
1072 | ||
1073 | return ret_val; | |
1074 | } | |
1075 | ||
1076 | /** | |
1077 | * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link | |
1078 | * @hw: pointer to the HW structure | |
1079 | * | |
1080 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
1081 | * configure to advertise the full capability. Setup the PHY to autoneg | |
1082 | * and restart the negotiation process between the link partner. If | |
ad68076e | 1083 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
bc7f75fa AK |
1084 | **/ |
1085 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) | |
1086 | { | |
1087 | struct e1000_phy_info *phy = &hw->phy; | |
1088 | s32 ret_val; | |
1089 | u16 phy_ctrl; | |
1090 | ||
ad68076e BA |
1091 | /* |
1092 | * Perform some bounds checking on the autoneg advertisement | |
bc7f75fa AK |
1093 | * parameter. |
1094 | */ | |
1095 | phy->autoneg_advertised &= phy->autoneg_mask; | |
1096 | ||
ad68076e BA |
1097 | /* |
1098 | * If autoneg_advertised is zero, we assume it was not defaulted | |
bc7f75fa AK |
1099 | * by the calling code so we set to advertise full capability. |
1100 | */ | |
1101 | if (phy->autoneg_advertised == 0) | |
1102 | phy->autoneg_advertised = phy->autoneg_mask; | |
1103 | ||
3bb99fe2 | 1104 | e_dbg("Reconfiguring auto-neg advertisement params\n"); |
bc7f75fa AK |
1105 | ret_val = e1000_phy_setup_autoneg(hw); |
1106 | if (ret_val) { | |
3bb99fe2 | 1107 | e_dbg("Error Setting up Auto-Negotiation\n"); |
bc7f75fa AK |
1108 | return ret_val; |
1109 | } | |
3bb99fe2 | 1110 | e_dbg("Restarting Auto-Neg\n"); |
bc7f75fa | 1111 | |
ad68076e BA |
1112 | /* |
1113 | * Restart auto-negotiation by setting the Auto Neg Enable bit and | |
bc7f75fa AK |
1114 | * the Auto Neg Restart bit in the PHY control register. |
1115 | */ | |
1116 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); | |
1117 | if (ret_val) | |
1118 | return ret_val; | |
1119 | ||
1120 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | |
1121 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); | |
1122 | if (ret_val) | |
1123 | return ret_val; | |
1124 | ||
ad68076e BA |
1125 | /* |
1126 | * Does the user want to wait for Auto-Neg to complete here, or | |
bc7f75fa AK |
1127 | * check at a later time (for example, callback routine). |
1128 | */ | |
318a94d6 | 1129 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
1130 | ret_val = e1000_wait_autoneg(hw); |
1131 | if (ret_val) { | |
3bb99fe2 | 1132 | e_dbg("Error while waiting for " |
bc7f75fa AK |
1133 | "autoneg to complete\n"); |
1134 | return ret_val; | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | hw->mac.get_link_status = 1; | |
1139 | ||
1140 | return ret_val; | |
1141 | } | |
1142 | ||
1143 | /** | |
1144 | * e1000e_setup_copper_link - Configure copper link settings | |
1145 | * @hw: pointer to the HW structure | |
1146 | * | |
1147 | * Calls the appropriate function to configure the link for auto-neg or forced | |
1148 | * speed and duplex. Then we check for link, once link is established calls | |
1149 | * to configure collision distance and flow control are called. If link is | |
1150 | * not established, we return -E1000_ERR_PHY (-2). | |
1151 | **/ | |
1152 | s32 e1000e_setup_copper_link(struct e1000_hw *hw) | |
1153 | { | |
1154 | s32 ret_val; | |
1155 | bool link; | |
1156 | ||
1157 | if (hw->mac.autoneg) { | |
ad68076e BA |
1158 | /* |
1159 | * Setup autoneg and flow control advertisement and perform | |
1160 | * autonegotiation. | |
1161 | */ | |
bc7f75fa AK |
1162 | ret_val = e1000_copper_link_autoneg(hw); |
1163 | if (ret_val) | |
1164 | return ret_val; | |
1165 | } else { | |
ad68076e BA |
1166 | /* |
1167 | * PHY will be set to 10H, 10F, 100H or 100F | |
1168 | * depending on user settings. | |
1169 | */ | |
3bb99fe2 | 1170 | e_dbg("Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1171 | ret_val = e1000_phy_force_speed_duplex(hw); |
1172 | if (ret_val) { | |
3bb99fe2 | 1173 | e_dbg("Error Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1174 | return ret_val; |
1175 | } | |
1176 | } | |
1177 | ||
ad68076e BA |
1178 | /* |
1179 | * Check link status. Wait up to 100 microseconds for link to become | |
bc7f75fa AK |
1180 | * valid. |
1181 | */ | |
1182 | ret_val = e1000e_phy_has_link_generic(hw, | |
1183 | COPPER_LINK_UP_LIMIT, | |
1184 | 10, | |
1185 | &link); | |
1186 | if (ret_val) | |
1187 | return ret_val; | |
1188 | ||
1189 | if (link) { | |
3bb99fe2 | 1190 | e_dbg("Valid link established!!!\n"); |
bc7f75fa AK |
1191 | e1000e_config_collision_dist(hw); |
1192 | ret_val = e1000e_config_fc_after_link_up(hw); | |
1193 | } else { | |
3bb99fe2 | 1194 | e_dbg("Unable to establish link!!!\n"); |
bc7f75fa AK |
1195 | } |
1196 | ||
1197 | return ret_val; | |
1198 | } | |
1199 | ||
1200 | /** | |
1201 | * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY | |
1202 | * @hw: pointer to the HW structure | |
1203 | * | |
1204 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1205 | * auto-crossover to force MDI manually. Waits for link and returns | |
1206 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
1207 | **/ | |
1208 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
1209 | { | |
1210 | struct e1000_phy_info *phy = &hw->phy; | |
1211 | s32 ret_val; | |
1212 | u16 phy_data; | |
1213 | bool link; | |
1214 | ||
1215 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
1216 | if (ret_val) | |
1217 | return ret_val; | |
1218 | ||
1219 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1220 | ||
1221 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
1222 | if (ret_val) | |
1223 | return ret_val; | |
1224 | ||
ad68076e BA |
1225 | /* |
1226 | * Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
bc7f75fa AK |
1227 | * forced whenever speed and duplex are forced. |
1228 | */ | |
1229 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1230 | if (ret_val) | |
1231 | return ret_val; | |
1232 | ||
1233 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1234 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1235 | ||
1236 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
1237 | if (ret_val) | |
1238 | return ret_val; | |
1239 | ||
3bb99fe2 | 1240 | e_dbg("IGP PSCR: %X\n", phy_data); |
bc7f75fa AK |
1241 | |
1242 | udelay(1); | |
1243 | ||
318a94d6 | 1244 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1245 | e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
bc7f75fa AK |
1246 | |
1247 | ret_val = e1000e_phy_has_link_generic(hw, | |
1248 | PHY_FORCE_LIMIT, | |
1249 | 100000, | |
1250 | &link); | |
1251 | if (ret_val) | |
1252 | return ret_val; | |
1253 | ||
1254 | if (!link) | |
3bb99fe2 | 1255 | e_dbg("Link taking longer than expected.\n"); |
bc7f75fa AK |
1256 | |
1257 | /* Try once more */ | |
1258 | ret_val = e1000e_phy_has_link_generic(hw, | |
1259 | PHY_FORCE_LIMIT, | |
1260 | 100000, | |
1261 | &link); | |
1262 | if (ret_val) | |
1263 | return ret_val; | |
1264 | } | |
1265 | ||
1266 | return ret_val; | |
1267 | } | |
1268 | ||
1269 | /** | |
1270 | * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY | |
1271 | * @hw: pointer to the HW structure | |
1272 | * | |
1273 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1274 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
1275 | * changes. If time expires while waiting for link up, we reset the DSP. | |
ad68076e | 1276 | * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
bc7f75fa AK |
1277 | * successful completion, else return corresponding error code. |
1278 | **/ | |
1279 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
1280 | { | |
1281 | struct e1000_phy_info *phy = &hw->phy; | |
1282 | s32 ret_val; | |
1283 | u16 phy_data; | |
1284 | bool link; | |
1285 | ||
ad68076e BA |
1286 | /* |
1287 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
1288 | * forced whenever speed and duplex are forced. |
1289 | */ | |
1290 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1291 | if (ret_val) | |
1292 | return ret_val; | |
1293 | ||
1294 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1295 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1296 | if (ret_val) | |
1297 | return ret_val; | |
1298 | ||
3bb99fe2 | 1299 | e_dbg("M88E1000 PSCR: %X\n", phy_data); |
bc7f75fa AK |
1300 | |
1301 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
1302 | if (ret_val) | |
1303 | return ret_val; | |
1304 | ||
1305 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1306 | ||
bc7f75fa AK |
1307 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
1308 | if (ret_val) | |
1309 | return ret_val; | |
1310 | ||
5aa49c82 BA |
1311 | /* Reset the phy to commit changes. */ |
1312 | ret_val = e1000e_commit_phy(hw); | |
1313 | if (ret_val) | |
1314 | return ret_val; | |
bc7f75fa | 1315 | |
318a94d6 | 1316 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1317 | e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
bc7f75fa AK |
1318 | |
1319 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1320 | 100000, &link); | |
1321 | if (ret_val) | |
1322 | return ret_val; | |
1323 | ||
1324 | if (!link) { | |
ad68076e BA |
1325 | /* |
1326 | * We didn't get link. | |
bc7f75fa AK |
1327 | * Reset the DSP and cross our fingers. |
1328 | */ | |
ad68076e BA |
1329 | ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, |
1330 | 0x001d); | |
bc7f75fa AK |
1331 | if (ret_val) |
1332 | return ret_val; | |
1333 | ret_val = e1000e_phy_reset_dsp(hw); | |
1334 | if (ret_val) | |
1335 | return ret_val; | |
1336 | } | |
1337 | ||
1338 | /* Try once more */ | |
1339 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1340 | 100000, &link); | |
1341 | if (ret_val) | |
1342 | return ret_val; | |
1343 | } | |
1344 | ||
1345 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
1346 | if (ret_val) | |
1347 | return ret_val; | |
1348 | ||
ad68076e BA |
1349 | /* |
1350 | * Resetting the phy means we need to re-force TX_CLK in the | |
bc7f75fa AK |
1351 | * Extended PHY Specific Control Register to 25MHz clock from |
1352 | * the reset value of 2.5MHz. | |
1353 | */ | |
1354 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1355 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1356 | if (ret_val) | |
1357 | return ret_val; | |
1358 | ||
ad68076e BA |
1359 | /* |
1360 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
1361 | * duplex. |
1362 | */ | |
1363 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1364 | if (ret_val) | |
1365 | return ret_val; | |
1366 | ||
1367 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
1368 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1369 | ||
1370 | return ret_val; | |
1371 | } | |
1372 | ||
1373 | /** | |
1374 | * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex | |
1375 | * @hw: pointer to the HW structure | |
1376 | * @phy_ctrl: pointer to current value of PHY_CONTROL | |
1377 | * | |
1378 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
1379 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
1380 | * disable auto-negotiation, configure duplex, configure speed, configure | |
1381 | * the collision distance, write configuration to CTRL register. The | |
1382 | * caller must write to the PHY_CONTROL register for these settings to | |
1383 | * take affect. | |
1384 | **/ | |
1385 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) | |
1386 | { | |
1387 | struct e1000_mac_info *mac = &hw->mac; | |
1388 | u32 ctrl; | |
1389 | ||
1390 | /* Turn off flow control when forcing speed/duplex */ | |
5c48ef3e | 1391 | hw->fc.current_mode = e1000_fc_none; |
bc7f75fa AK |
1392 | |
1393 | /* Force speed/duplex on the mac */ | |
1394 | ctrl = er32(CTRL); | |
1395 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1396 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1397 | ||
1398 | /* Disable Auto Speed Detection */ | |
1399 | ctrl &= ~E1000_CTRL_ASDE; | |
1400 | ||
1401 | /* Disable autoneg on the phy */ | |
1402 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; | |
1403 | ||
1404 | /* Forcing Full or Half Duplex? */ | |
1405 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1406 | ctrl &= ~E1000_CTRL_FD; | |
1407 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; | |
3bb99fe2 | 1408 | e_dbg("Half Duplex\n"); |
bc7f75fa AK |
1409 | } else { |
1410 | ctrl |= E1000_CTRL_FD; | |
1411 | *phy_ctrl |= MII_CR_FULL_DUPLEX; | |
3bb99fe2 | 1412 | e_dbg("Full Duplex\n"); |
bc7f75fa AK |
1413 | } |
1414 | ||
1415 | /* Forcing 10mb or 100mb? */ | |
1416 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1417 | ctrl |= E1000_CTRL_SPD_100; | |
1418 | *phy_ctrl |= MII_CR_SPEED_100; | |
1419 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
3bb99fe2 | 1420 | e_dbg("Forcing 100mb\n"); |
bc7f75fa AK |
1421 | } else { |
1422 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1423 | *phy_ctrl |= MII_CR_SPEED_10; | |
1424 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
3bb99fe2 | 1425 | e_dbg("Forcing 10mb\n"); |
bc7f75fa AK |
1426 | } |
1427 | ||
1428 | e1000e_config_collision_dist(hw); | |
1429 | ||
1430 | ew32(CTRL, ctrl); | |
1431 | } | |
1432 | ||
1433 | /** | |
1434 | * e1000e_set_d3_lplu_state - Sets low power link up state for D3 | |
1435 | * @hw: pointer to the HW structure | |
1436 | * @active: boolean used to enable/disable lplu | |
1437 | * | |
1438 | * Success returns 0, Failure returns 1 | |
1439 | * | |
1440 | * The low power link up (lplu) state is set to the power management level D3 | |
1441 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1442 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1443 | * is used during Dx states where the power conservation is most important. | |
1444 | * During driver activity, SmartSpeed should be enabled so performance is | |
1445 | * maintained. | |
1446 | **/ | |
1447 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1448 | { | |
1449 | struct e1000_phy_info *phy = &hw->phy; | |
1450 | s32 ret_val; | |
1451 | u16 data; | |
1452 | ||
1453 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
1454 | if (ret_val) | |
1455 | return ret_val; | |
1456 | ||
1457 | if (!active) { | |
1458 | data &= ~IGP02E1000_PM_D3_LPLU; | |
2d9498f3 | 1459 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
bc7f75fa AK |
1460 | if (ret_val) |
1461 | return ret_val; | |
ad68076e BA |
1462 | /* |
1463 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
1464 | * during Dx states where the power conservation is most |
1465 | * important. During driver activity we should enable | |
ad68076e BA |
1466 | * SmartSpeed, so performance is maintained. |
1467 | */ | |
bc7f75fa AK |
1468 | if (phy->smart_speed == e1000_smart_speed_on) { |
1469 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1470 | &data); |
bc7f75fa AK |
1471 | if (ret_val) |
1472 | return ret_val; | |
1473 | ||
1474 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
1475 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1476 | data); |
bc7f75fa AK |
1477 | if (ret_val) |
1478 | return ret_val; | |
1479 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
1480 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1481 | &data); |
bc7f75fa AK |
1482 | if (ret_val) |
1483 | return ret_val; | |
1484 | ||
1485 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1486 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1487 | data); |
bc7f75fa AK |
1488 | if (ret_val) |
1489 | return ret_val; | |
1490 | } | |
1491 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1492 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1493 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1494 | data |= IGP02E1000_PM_D3_LPLU; | |
1495 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
1496 | if (ret_val) | |
1497 | return ret_val; | |
1498 | ||
1499 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
1500 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
1501 | if (ret_val) | |
1502 | return ret_val; | |
1503 | ||
1504 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1505 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
1506 | } | |
1507 | ||
1508 | return ret_val; | |
1509 | } | |
1510 | ||
1511 | /** | |
489815ce | 1512 | * e1000e_check_downshift - Checks whether a downshift in speed occurred |
bc7f75fa AK |
1513 | * @hw: pointer to the HW structure |
1514 | * | |
1515 | * Success returns 0, Failure returns 1 | |
1516 | * | |
1517 | * A downshift is detected by querying the PHY link health. | |
1518 | **/ | |
1519 | s32 e1000e_check_downshift(struct e1000_hw *hw) | |
1520 | { | |
1521 | struct e1000_phy_info *phy = &hw->phy; | |
1522 | s32 ret_val; | |
1523 | u16 phy_data, offset, mask; | |
1524 | ||
1525 | switch (phy->type) { | |
1526 | case e1000_phy_m88: | |
1527 | case e1000_phy_gg82563: | |
07f025e6 | 1528 | case e1000_phy_bm: |
a4f58f54 | 1529 | case e1000_phy_82578: |
bc7f75fa AK |
1530 | offset = M88E1000_PHY_SPEC_STATUS; |
1531 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1532 | break; | |
1533 | case e1000_phy_igp_2: | |
1534 | case e1000_phy_igp_3: | |
1535 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1536 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1537 | break; | |
1538 | default: | |
1539 | /* speed downshift not supported */ | |
564ea9bb | 1540 | phy->speed_downgraded = false; |
bc7f75fa AK |
1541 | return 0; |
1542 | } | |
1543 | ||
1544 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1545 | ||
1546 | if (!ret_val) | |
1547 | phy->speed_downgraded = (phy_data & mask); | |
1548 | ||
1549 | return ret_val; | |
1550 | } | |
1551 | ||
1552 | /** | |
1553 | * e1000_check_polarity_m88 - Checks the polarity. | |
1554 | * @hw: pointer to the HW structure | |
1555 | * | |
1556 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1557 | * | |
1558 | * Polarity is determined based on the PHY specific status register. | |
1559 | **/ | |
1560 | static s32 e1000_check_polarity_m88(struct e1000_hw *hw) | |
1561 | { | |
1562 | struct e1000_phy_info *phy = &hw->phy; | |
1563 | s32 ret_val; | |
1564 | u16 data; | |
1565 | ||
1566 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); | |
1567 | ||
1568 | if (!ret_val) | |
1569 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1570 | ? e1000_rev_polarity_reversed | |
1571 | : e1000_rev_polarity_normal; | |
1572 | ||
1573 | return ret_val; | |
1574 | } | |
1575 | ||
1576 | /** | |
1577 | * e1000_check_polarity_igp - Checks the polarity. | |
1578 | * @hw: pointer to the HW structure | |
1579 | * | |
1580 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1581 | * | |
1582 | * Polarity is determined based on the PHY port status register, and the | |
1583 | * current speed (since there is no polarity at 100Mbps). | |
1584 | **/ | |
1585 | static s32 e1000_check_polarity_igp(struct e1000_hw *hw) | |
1586 | { | |
1587 | struct e1000_phy_info *phy = &hw->phy; | |
1588 | s32 ret_val; | |
1589 | u16 data, offset, mask; | |
1590 | ||
ad68076e BA |
1591 | /* |
1592 | * Polarity is determined based on the speed of | |
1593 | * our connection. | |
1594 | */ | |
bc7f75fa AK |
1595 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
1596 | if (ret_val) | |
1597 | return ret_val; | |
1598 | ||
1599 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1600 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1601 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1602 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1603 | } else { | |
ad68076e BA |
1604 | /* |
1605 | * This really only applies to 10Mbps since | |
bc7f75fa AK |
1606 | * there is no polarity for 100Mbps (always 0). |
1607 | */ | |
1608 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1609 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1610 | } | |
1611 | ||
1612 | ret_val = e1e_rphy(hw, offset, &data); | |
1613 | ||
1614 | if (!ret_val) | |
1615 | phy->cable_polarity = (data & mask) | |
1616 | ? e1000_rev_polarity_reversed | |
1617 | : e1000_rev_polarity_normal; | |
1618 | ||
1619 | return ret_val; | |
1620 | } | |
1621 | ||
1622 | /** | |
ad68076e | 1623 | * e1000_wait_autoneg - Wait for auto-neg completion |
bc7f75fa AK |
1624 | * @hw: pointer to the HW structure |
1625 | * | |
1626 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1627 | * limit to expire, which ever happens first. | |
1628 | **/ | |
1629 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) | |
1630 | { | |
1631 | s32 ret_val = 0; | |
1632 | u16 i, phy_status; | |
1633 | ||
1634 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1635 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
1636 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1637 | if (ret_val) | |
1638 | break; | |
1639 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1640 | if (ret_val) | |
1641 | break; | |
1642 | if (phy_status & MII_SR_AUTONEG_COMPLETE) | |
1643 | break; | |
1644 | msleep(100); | |
1645 | } | |
1646 | ||
ad68076e BA |
1647 | /* |
1648 | * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation | |
bc7f75fa AK |
1649 | * has completed. |
1650 | */ | |
1651 | return ret_val; | |
1652 | } | |
1653 | ||
1654 | /** | |
1655 | * e1000e_phy_has_link_generic - Polls PHY for link | |
1656 | * @hw: pointer to the HW structure | |
1657 | * @iterations: number of times to poll for link | |
1658 | * @usec_interval: delay between polling attempts | |
1659 | * @success: pointer to whether polling was successful or not | |
1660 | * | |
1661 | * Polls the PHY status register for link, 'iterations' number of times. | |
1662 | **/ | |
1663 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, | |
1664 | u32 usec_interval, bool *success) | |
1665 | { | |
1666 | s32 ret_val = 0; | |
1667 | u16 i, phy_status; | |
1668 | ||
1669 | for (i = 0; i < iterations; i++) { | |
ad68076e BA |
1670 | /* |
1671 | * Some PHYs require the PHY_STATUS register to be read | |
bc7f75fa AK |
1672 | * twice due to the link bit being sticky. No harm doing |
1673 | * it across the board. | |
1674 | */ | |
1675 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1676 | if (ret_val) | |
906e8d97 BA |
1677 | /* |
1678 | * If the first read fails, another entity may have | |
1679 | * ownership of the resources, wait and try again to | |
1680 | * see if they have relinquished the resources yet. | |
1681 | */ | |
1682 | udelay(usec_interval); | |
bc7f75fa AK |
1683 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
1684 | if (ret_val) | |
1685 | break; | |
1686 | if (phy_status & MII_SR_LINK_STATUS) | |
1687 | break; | |
1688 | if (usec_interval >= 1000) | |
1689 | mdelay(usec_interval/1000); | |
1690 | else | |
1691 | udelay(usec_interval); | |
1692 | } | |
1693 | ||
1694 | *success = (i < iterations); | |
1695 | ||
1696 | return ret_val; | |
1697 | } | |
1698 | ||
1699 | /** | |
1700 | * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY | |
1701 | * @hw: pointer to the HW structure | |
1702 | * | |
1703 | * Reads the PHY specific status register to retrieve the cable length | |
1704 | * information. The cable length is determined by averaging the minimum and | |
1705 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1706 | * possible cable length values, which are: | |
1707 | * Register Value Cable Length | |
1708 | * 0 < 50 meters | |
1709 | * 1 50 - 80 meters | |
1710 | * 2 80 - 110 meters | |
1711 | * 3 110 - 140 meters | |
1712 | * 4 > 140 meters | |
1713 | **/ | |
1714 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) | |
1715 | { | |
1716 | struct e1000_phy_info *phy = &hw->phy; | |
1717 | s32 ret_val; | |
1718 | u16 phy_data, index; | |
1719 | ||
1720 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1721 | if (ret_val) | |
eb656d45 | 1722 | goto out; |
bc7f75fa AK |
1723 | |
1724 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
eb656d45 BA |
1725 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
1726 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { | |
1727 | ret_val = -E1000_ERR_PHY; | |
1728 | goto out; | |
1729 | } | |
1730 | ||
bc7f75fa | 1731 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
eb656d45 | 1732 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
bc7f75fa AK |
1733 | |
1734 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1735 | ||
eb656d45 | 1736 | out: |
bc7f75fa AK |
1737 | return ret_val; |
1738 | } | |
1739 | ||
1740 | /** | |
1741 | * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY | |
1742 | * @hw: pointer to the HW structure | |
1743 | * | |
1744 | * The automatic gain control (agc) normalizes the amplitude of the | |
1745 | * received signal, adjusting for the attenuation produced by the | |
489815ce | 1746 | * cable. By reading the AGC registers, which represent the |
5ff5b664 | 1747 | * combination of coarse and fine gain value, the value can be put |
bc7f75fa AK |
1748 | * into a lookup table to obtain the approximate cable length |
1749 | * for each channel. | |
1750 | **/ | |
1751 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) | |
1752 | { | |
1753 | struct e1000_phy_info *phy = &hw->phy; | |
1754 | s32 ret_val; | |
1755 | u16 phy_data, i, agc_value = 0; | |
1756 | u16 cur_agc_index, max_agc_index = 0; | |
1757 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
1758 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | |
1759 | {IGP02E1000_PHY_AGC_A, | |
1760 | IGP02E1000_PHY_AGC_B, | |
1761 | IGP02E1000_PHY_AGC_C, | |
1762 | IGP02E1000_PHY_AGC_D}; | |
1763 | ||
1764 | /* Read the AGC registers for all channels */ | |
1765 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
1766 | ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); | |
1767 | if (ret_val) | |
1768 | return ret_val; | |
1769 | ||
ad68076e BA |
1770 | /* |
1771 | * Getting bits 15:9, which represent the combination of | |
5ff5b664 | 1772 | * coarse and fine gain values. The result is a number |
bc7f75fa | 1773 | * that can be put into the lookup table to obtain the |
ad68076e BA |
1774 | * approximate cable length. |
1775 | */ | |
bc7f75fa AK |
1776 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
1777 | IGP02E1000_AGC_LENGTH_MASK; | |
1778 | ||
1779 | /* Array index bound check. */ | |
1780 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1781 | (cur_agc_index == 0)) | |
1782 | return -E1000_ERR_PHY; | |
1783 | ||
1784 | /* Remove min & max AGC values from calculation. */ | |
1785 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1786 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1787 | min_agc_index = cur_agc_index; | |
1788 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1789 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1790 | max_agc_index = cur_agc_index; | |
1791 | ||
1792 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1793 | } | |
1794 | ||
1795 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1796 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1797 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1798 | ||
1799 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1800 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1801 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1802 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1803 | ||
1804 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1805 | ||
1806 | return ret_val; | |
1807 | } | |
1808 | ||
1809 | /** | |
1810 | * e1000e_get_phy_info_m88 - Retrieve PHY information | |
1811 | * @hw: pointer to the HW structure | |
1812 | * | |
1813 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1814 | * to verify that link is up. Read the PHY special control register to | |
1815 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1816 | * special status register to determine MDI/MDIx and current speed. If | |
1817 | * speed is 1000, then determine cable length, local and remote receiver. | |
1818 | **/ | |
1819 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) | |
1820 | { | |
1821 | struct e1000_phy_info *phy = &hw->phy; | |
1822 | s32 ret_val; | |
1823 | u16 phy_data; | |
1824 | bool link; | |
1825 | ||
318a94d6 | 1826 | if (hw->phy.media_type != e1000_media_type_copper) { |
3bb99fe2 | 1827 | e_dbg("Phy info is only valid for copper media\n"); |
bc7f75fa AK |
1828 | return -E1000_ERR_CONFIG; |
1829 | } | |
1830 | ||
1831 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1832 | if (ret_val) | |
1833 | return ret_val; | |
1834 | ||
1835 | if (!link) { | |
3bb99fe2 | 1836 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1837 | return -E1000_ERR_CONFIG; |
1838 | } | |
1839 | ||
1840 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1841 | if (ret_val) | |
1842 | return ret_val; | |
1843 | ||
1844 | phy->polarity_correction = (phy_data & | |
1845 | M88E1000_PSCR_POLARITY_REVERSAL); | |
1846 | ||
1847 | ret_val = e1000_check_polarity_m88(hw); | |
1848 | if (ret_val) | |
1849 | return ret_val; | |
1850 | ||
1851 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1852 | if (ret_val) | |
1853 | return ret_val; | |
1854 | ||
1855 | phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX); | |
1856 | ||
1857 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
1858 | ret_val = e1000_get_cable_length(hw); | |
1859 | if (ret_val) | |
1860 | return ret_val; | |
1861 | ||
1862 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); | |
1863 | if (ret_val) | |
1864 | return ret_val; | |
1865 | ||
1866 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) | |
1867 | ? e1000_1000t_rx_status_ok | |
1868 | : e1000_1000t_rx_status_not_ok; | |
1869 | ||
1870 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) | |
1871 | ? e1000_1000t_rx_status_ok | |
1872 | : e1000_1000t_rx_status_not_ok; | |
1873 | } else { | |
1874 | /* Set values to "undefined" */ | |
1875 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1876 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1877 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1878 | } | |
1879 | ||
1880 | return ret_val; | |
1881 | } | |
1882 | ||
1883 | /** | |
1884 | * e1000e_get_phy_info_igp - Retrieve igp PHY information | |
1885 | * @hw: pointer to the HW structure | |
1886 | * | |
1887 | * Read PHY status to determine if link is up. If link is up, then | |
1888 | * set/determine 10base-T extended distance and polarity correction. Read | |
1889 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1890 | * determine on the cable length, local and remote receiver. | |
1891 | **/ | |
1892 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) | |
1893 | { | |
1894 | struct e1000_phy_info *phy = &hw->phy; | |
1895 | s32 ret_val; | |
1896 | u16 data; | |
1897 | bool link; | |
1898 | ||
1899 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1900 | if (ret_val) | |
1901 | return ret_val; | |
1902 | ||
1903 | if (!link) { | |
3bb99fe2 | 1904 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1905 | return -E1000_ERR_CONFIG; |
1906 | } | |
1907 | ||
564ea9bb | 1908 | phy->polarity_correction = true; |
bc7f75fa AK |
1909 | |
1910 | ret_val = e1000_check_polarity_igp(hw); | |
1911 | if (ret_val) | |
1912 | return ret_val; | |
1913 | ||
1914 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); | |
1915 | if (ret_val) | |
1916 | return ret_val; | |
1917 | ||
1918 | phy->is_mdix = (data & IGP01E1000_PSSR_MDIX); | |
1919 | ||
1920 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1921 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1922 | ret_val = e1000_get_cable_length(hw); | |
1923 | if (ret_val) | |
1924 | return ret_val; | |
1925 | ||
1926 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); | |
1927 | if (ret_val) | |
1928 | return ret_val; | |
1929 | ||
1930 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
1931 | ? e1000_1000t_rx_status_ok | |
1932 | : e1000_1000t_rx_status_not_ok; | |
1933 | ||
1934 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
1935 | ? e1000_1000t_rx_status_ok | |
1936 | : e1000_1000t_rx_status_not_ok; | |
1937 | } else { | |
1938 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1939 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1940 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1941 | } | |
1942 | ||
1943 | return ret_val; | |
1944 | } | |
1945 | ||
1946 | /** | |
1947 | * e1000e_phy_sw_reset - PHY software reset | |
1948 | * @hw: pointer to the HW structure | |
1949 | * | |
1950 | * Does a software reset of the PHY by reading the PHY control register and | |
1951 | * setting/write the control register reset bit to the PHY. | |
1952 | **/ | |
1953 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw) | |
1954 | { | |
1955 | s32 ret_val; | |
1956 | u16 phy_ctrl; | |
1957 | ||
1958 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); | |
1959 | if (ret_val) | |
1960 | return ret_val; | |
1961 | ||
1962 | phy_ctrl |= MII_CR_RESET; | |
1963 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); | |
1964 | if (ret_val) | |
1965 | return ret_val; | |
1966 | ||
1967 | udelay(1); | |
1968 | ||
1969 | return ret_val; | |
1970 | } | |
1971 | ||
1972 | /** | |
1973 | * e1000e_phy_hw_reset_generic - PHY hardware reset | |
1974 | * @hw: pointer to the HW structure | |
1975 | * | |
1976 | * Verify the reset block is not blocking us from resetting. Acquire | |
1977 | * semaphore (if necessary) and read/set/write the device control reset | |
1978 | * bit in the PHY. Wait the appropriate delay time for the device to | |
489815ce | 1979 | * reset and release the semaphore (if necessary). |
bc7f75fa AK |
1980 | **/ |
1981 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) | |
1982 | { | |
1983 | struct e1000_phy_info *phy = &hw->phy; | |
1984 | s32 ret_val; | |
1985 | u32 ctrl; | |
1986 | ||
1987 | ret_val = e1000_check_reset_block(hw); | |
1988 | if (ret_val) | |
1989 | return 0; | |
1990 | ||
94d8186a | 1991 | ret_val = phy->ops.acquire(hw); |
bc7f75fa AK |
1992 | if (ret_val) |
1993 | return ret_val; | |
1994 | ||
1995 | ctrl = er32(CTRL); | |
1996 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); | |
1997 | e1e_flush(); | |
1998 | ||
1999 | udelay(phy->reset_delay_us); | |
2000 | ||
2001 | ew32(CTRL, ctrl); | |
2002 | e1e_flush(); | |
2003 | ||
2004 | udelay(150); | |
2005 | ||
94d8186a | 2006 | phy->ops.release(hw); |
bc7f75fa AK |
2007 | |
2008 | return e1000_get_phy_cfg_done(hw); | |
2009 | } | |
2010 | ||
2011 | /** | |
2012 | * e1000e_get_cfg_done - Generic configuration done | |
2013 | * @hw: pointer to the HW structure | |
2014 | * | |
2015 | * Generic function to wait 10 milli-seconds for configuration to complete | |
2016 | * and return success. | |
2017 | **/ | |
2018 | s32 e1000e_get_cfg_done(struct e1000_hw *hw) | |
2019 | { | |
2020 | mdelay(10); | |
2021 | return 0; | |
2022 | } | |
2023 | ||
f4187b56 BA |
2024 | /** |
2025 | * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY | |
2026 | * @hw: pointer to the HW structure | |
2027 | * | |
2028 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
2029 | **/ | |
2030 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) | |
2031 | { | |
3bb99fe2 | 2032 | e_dbg("Running IGP 3 PHY init script\n"); |
f4187b56 BA |
2033 | |
2034 | /* PHY init IGP 3 */ | |
2035 | /* Enable rise/fall, 10-mode work in class-A */ | |
2036 | e1e_wphy(hw, 0x2F5B, 0x9018); | |
2037 | /* Remove all caps from Replica path filter */ | |
2038 | e1e_wphy(hw, 0x2F52, 0x0000); | |
2039 | /* Bias trimming for ADC, AFE and Driver (Default) */ | |
2040 | e1e_wphy(hw, 0x2FB1, 0x8B24); | |
2041 | /* Increase Hybrid poly bias */ | |
2042 | e1e_wphy(hw, 0x2FB2, 0xF8F0); | |
2043 | /* Add 4% to Tx amplitude in Gig mode */ | |
2044 | e1e_wphy(hw, 0x2010, 0x10B0); | |
2045 | /* Disable trimming (TTT) */ | |
2046 | e1e_wphy(hw, 0x2011, 0x0000); | |
2047 | /* Poly DC correction to 94.6% + 2% for all channels */ | |
2048 | e1e_wphy(hw, 0x20DD, 0x249A); | |
2049 | /* ABS DC correction to 95.9% */ | |
2050 | e1e_wphy(hw, 0x20DE, 0x00D3); | |
2051 | /* BG temp curve trim */ | |
2052 | e1e_wphy(hw, 0x28B4, 0x04CE); | |
2053 | /* Increasing ADC OPAMP stage 1 currents to max */ | |
2054 | e1e_wphy(hw, 0x2F70, 0x29E4); | |
2055 | /* Force 1000 ( required for enabling PHY regs configuration) */ | |
2056 | e1e_wphy(hw, 0x0000, 0x0140); | |
2057 | /* Set upd_freq to 6 */ | |
2058 | e1e_wphy(hw, 0x1F30, 0x1606); | |
2059 | /* Disable NPDFE */ | |
2060 | e1e_wphy(hw, 0x1F31, 0xB814); | |
2061 | /* Disable adaptive fixed FFE (Default) */ | |
2062 | e1e_wphy(hw, 0x1F35, 0x002A); | |
2063 | /* Enable FFE hysteresis */ | |
2064 | e1e_wphy(hw, 0x1F3E, 0x0067); | |
2065 | /* Fixed FFE for short cable lengths */ | |
2066 | e1e_wphy(hw, 0x1F54, 0x0065); | |
2067 | /* Fixed FFE for medium cable lengths */ | |
2068 | e1e_wphy(hw, 0x1F55, 0x002A); | |
2069 | /* Fixed FFE for long cable lengths */ | |
2070 | e1e_wphy(hw, 0x1F56, 0x002A); | |
2071 | /* Enable Adaptive Clip Threshold */ | |
2072 | e1e_wphy(hw, 0x1F72, 0x3FB0); | |
2073 | /* AHT reset limit to 1 */ | |
2074 | e1e_wphy(hw, 0x1F76, 0xC0FF); | |
2075 | /* Set AHT master delay to 127 msec */ | |
2076 | e1e_wphy(hw, 0x1F77, 0x1DEC); | |
2077 | /* Set scan bits for AHT */ | |
2078 | e1e_wphy(hw, 0x1F78, 0xF9EF); | |
2079 | /* Set AHT Preset bits */ | |
2080 | e1e_wphy(hw, 0x1F79, 0x0210); | |
2081 | /* Change integ_factor of channel A to 3 */ | |
2082 | e1e_wphy(hw, 0x1895, 0x0003); | |
2083 | /* Change prop_factor of channels BCD to 8 */ | |
2084 | e1e_wphy(hw, 0x1796, 0x0008); | |
2085 | /* Change cg_icount + enable integbp for channels BCD */ | |
2086 | e1e_wphy(hw, 0x1798, 0xD008); | |
2087 | /* | |
2088 | * Change cg_icount + enable integbp + change prop_factor_master | |
2089 | * to 8 for channel A | |
2090 | */ | |
2091 | e1e_wphy(hw, 0x1898, 0xD918); | |
2092 | /* Disable AHT in Slave mode on channel A */ | |
2093 | e1e_wphy(hw, 0x187A, 0x0800); | |
2094 | /* | |
2095 | * Enable LPLU and disable AN to 1000 in non-D0a states, | |
2096 | * Enable SPD+B2B | |
2097 | */ | |
2098 | e1e_wphy(hw, 0x0019, 0x008D); | |
2099 | /* Enable restart AN on an1000_dis change */ | |
2100 | e1e_wphy(hw, 0x001B, 0x2080); | |
2101 | /* Enable wh_fifo read clock in 10/100 modes */ | |
2102 | e1e_wphy(hw, 0x0014, 0x0045); | |
2103 | /* Restart AN, Speed selection is 1000 */ | |
2104 | e1e_wphy(hw, 0x0000, 0x1340); | |
2105 | ||
2106 | return 0; | |
2107 | } | |
2108 | ||
bc7f75fa AK |
2109 | /* Internal function pointers */ |
2110 | ||
2111 | /** | |
2112 | * e1000_get_phy_cfg_done - Generic PHY configuration done | |
2113 | * @hw: pointer to the HW structure | |
2114 | * | |
2115 | * Return success if silicon family did not implement a family specific | |
2116 | * get_cfg_done function. | |
2117 | **/ | |
2118 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) | |
2119 | { | |
2120 | if (hw->phy.ops.get_cfg_done) | |
2121 | return hw->phy.ops.get_cfg_done(hw); | |
2122 | ||
2123 | return 0; | |
2124 | } | |
2125 | ||
2126 | /** | |
2127 | * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex | |
2128 | * @hw: pointer to the HW structure | |
2129 | * | |
2130 | * When the silicon family has not implemented a forced speed/duplex | |
2131 | * function for the PHY, simply return 0. | |
2132 | **/ | |
2133 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |
2134 | { | |
2135 | if (hw->phy.ops.force_speed_duplex) | |
2136 | return hw->phy.ops.force_speed_duplex(hw); | |
2137 | ||
2138 | return 0; | |
2139 | } | |
2140 | ||
2141 | /** | |
2142 | * e1000e_get_phy_type_from_id - Get PHY type from id | |
2143 | * @phy_id: phy_id read from the phy | |
2144 | * | |
2145 | * Returns the phy type from the id. | |
2146 | **/ | |
2147 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) | |
2148 | { | |
2149 | enum e1000_phy_type phy_type = e1000_phy_unknown; | |
2150 | ||
2151 | switch (phy_id) { | |
2152 | case M88E1000_I_PHY_ID: | |
2153 | case M88E1000_E_PHY_ID: | |
2154 | case M88E1111_I_PHY_ID: | |
2155 | case M88E1011_I_PHY_ID: | |
2156 | phy_type = e1000_phy_m88; | |
2157 | break; | |
2158 | case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ | |
2159 | phy_type = e1000_phy_igp_2; | |
2160 | break; | |
2161 | case GG82563_E_PHY_ID: | |
2162 | phy_type = e1000_phy_gg82563; | |
2163 | break; | |
2164 | case IGP03E1000_E_PHY_ID: | |
2165 | phy_type = e1000_phy_igp_3; | |
2166 | break; | |
2167 | case IFE_E_PHY_ID: | |
2168 | case IFE_PLUS_E_PHY_ID: | |
2169 | case IFE_C_E_PHY_ID: | |
2170 | phy_type = e1000_phy_ife; | |
2171 | break; | |
97ac8cae BA |
2172 | case BME1000_E_PHY_ID: |
2173 | case BME1000_E_PHY_ID_R2: | |
2174 | phy_type = e1000_phy_bm; | |
2175 | break; | |
a4f58f54 BA |
2176 | case I82578_E_PHY_ID: |
2177 | phy_type = e1000_phy_82578; | |
2178 | break; | |
2179 | case I82577_E_PHY_ID: | |
2180 | phy_type = e1000_phy_82577; | |
2181 | break; | |
bc7f75fa AK |
2182 | default: |
2183 | phy_type = e1000_phy_unknown; | |
2184 | break; | |
2185 | } | |
2186 | return phy_type; | |
2187 | } | |
2188 | ||
97ac8cae BA |
2189 | /** |
2190 | * e1000e_determine_phy_address - Determines PHY address. | |
2191 | * @hw: pointer to the HW structure | |
2192 | * | |
2193 | * This uses a trial and error method to loop through possible PHY | |
2194 | * addresses. It tests each by reading the PHY ID registers and | |
2195 | * checking for a match. | |
2196 | **/ | |
2197 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) | |
2198 | { | |
2199 | s32 ret_val = -E1000_ERR_PHY_TYPE; | |
5eb6f3c7 BA |
2200 | u32 phy_addr = 0; |
2201 | u32 i; | |
97ac8cae BA |
2202 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
2203 | ||
5eb6f3c7 BA |
2204 | hw->phy.id = phy_type; |
2205 | ||
2206 | for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { | |
2207 | hw->phy.addr = phy_addr; | |
2208 | i = 0; | |
2209 | ||
2210 | do { | |
97ac8cae BA |
2211 | e1000e_get_phy_id(hw); |
2212 | phy_type = e1000e_get_phy_type_from_id(hw->phy.id); | |
2213 | ||
5eb6f3c7 | 2214 | /* |
97ac8cae BA |
2215 | * If phy_type is valid, break - we found our |
2216 | * PHY address | |
2217 | */ | |
2218 | if (phy_type != e1000_phy_unknown) { | |
2219 | ret_val = 0; | |
5eb6f3c7 | 2220 | goto out; |
97ac8cae | 2221 | } |
5eb6f3c7 BA |
2222 | msleep(1); |
2223 | i++; | |
2224 | } while (i < 10); | |
2225 | } | |
97ac8cae | 2226 | |
5eb6f3c7 | 2227 | out: |
97ac8cae BA |
2228 | return ret_val; |
2229 | } | |
2230 | ||
2231 | /** | |
2232 | * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address | |
2233 | * @page: page to access | |
2234 | * | |
2235 | * Returns the phy address for the page requested. | |
2236 | **/ | |
2237 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) | |
2238 | { | |
2239 | u32 phy_addr = 2; | |
2240 | ||
2241 | if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) | |
2242 | phy_addr = 1; | |
2243 | ||
2244 | return phy_addr; | |
2245 | } | |
2246 | ||
2247 | /** | |
2248 | * e1000e_write_phy_reg_bm - Write BM PHY register | |
2249 | * @hw: pointer to the HW structure | |
2250 | * @offset: register offset to write to | |
2251 | * @data: data to write at register offset | |
2252 | * | |
2253 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2254 | * at the offset. Release any acquired semaphores before exiting. | |
2255 | **/ | |
2256 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) | |
2257 | { | |
2258 | s32 ret_val; | |
2259 | u32 page_select = 0; | |
2260 | u32 page = offset >> IGP_PAGE_SHIFT; | |
2261 | u32 page_shift = 0; | |
2262 | ||
94d8186a | 2263 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2264 | if (ret_val) |
2265 | return ret_val; | |
2266 | ||
97ac8cae BA |
2267 | /* Page 800 works differently than the rest so it has its own func */ |
2268 | if (page == BM_WUC_PAGE) { | |
2269 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2270 | false); | |
2271 | goto out; | |
2272 | } | |
2273 | ||
97ac8cae BA |
2274 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2275 | ||
2276 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2277 | /* | |
2278 | * Page select is register 31 for phy address 1 and 22 for | |
2279 | * phy address 2 and 3. Page select is shifted only for | |
2280 | * phy address 1. | |
2281 | */ | |
2282 | if (hw->phy.addr == 1) { | |
2283 | page_shift = IGP_PAGE_SHIFT; | |
2284 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2285 | } else { | |
2286 | page_shift = 0; | |
2287 | page_select = BM_PHY_PAGE_SELECT; | |
2288 | } | |
2289 | ||
2290 | /* Page is shifted left, PHY expects (page x 32) */ | |
2291 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2292 | (page << page_shift)); | |
5ccdcecb | 2293 | if (ret_val) |
97ac8cae | 2294 | goto out; |
97ac8cae BA |
2295 | } |
2296 | ||
2297 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2298 | data); | |
2299 | ||
97ac8cae | 2300 | out: |
94d8186a | 2301 | hw->phy.ops.release(hw); |
97ac8cae BA |
2302 | return ret_val; |
2303 | } | |
2304 | ||
2305 | /** | |
2306 | * e1000e_read_phy_reg_bm - Read BM PHY register | |
2307 | * @hw: pointer to the HW structure | |
2308 | * @offset: register offset to be read | |
2309 | * @data: pointer to the read data | |
2310 | * | |
2311 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2312 | * and storing the retrieved information in data. Release any acquired | |
2313 | * semaphores before exiting. | |
2314 | **/ | |
2315 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) | |
2316 | { | |
2317 | s32 ret_val; | |
2318 | u32 page_select = 0; | |
2319 | u32 page = offset >> IGP_PAGE_SHIFT; | |
2320 | u32 page_shift = 0; | |
2321 | ||
94d8186a | 2322 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2323 | if (ret_val) |
2324 | return ret_val; | |
2325 | ||
97ac8cae BA |
2326 | /* Page 800 works differently than the rest so it has its own func */ |
2327 | if (page == BM_WUC_PAGE) { | |
2328 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2329 | true); | |
2330 | goto out; | |
2331 | } | |
2332 | ||
97ac8cae BA |
2333 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2334 | ||
2335 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2336 | /* | |
2337 | * Page select is register 31 for phy address 1 and 22 for | |
2338 | * phy address 2 and 3. Page select is shifted only for | |
2339 | * phy address 1. | |
2340 | */ | |
2341 | if (hw->phy.addr == 1) { | |
2342 | page_shift = IGP_PAGE_SHIFT; | |
2343 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2344 | } else { | |
2345 | page_shift = 0; | |
2346 | page_select = BM_PHY_PAGE_SELECT; | |
2347 | } | |
2348 | ||
2349 | /* Page is shifted left, PHY expects (page x 32) */ | |
2350 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2351 | (page << page_shift)); | |
5ccdcecb | 2352 | if (ret_val) |
97ac8cae | 2353 | goto out; |
97ac8cae BA |
2354 | } |
2355 | ||
2356 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2357 | data); | |
97ac8cae | 2358 | out: |
94d8186a | 2359 | hw->phy.ops.release(hw); |
97ac8cae BA |
2360 | return ret_val; |
2361 | } | |
2362 | ||
4662e82b BA |
2363 | /** |
2364 | * e1000e_read_phy_reg_bm2 - Read BM PHY register | |
2365 | * @hw: pointer to the HW structure | |
2366 | * @offset: register offset to be read | |
2367 | * @data: pointer to the read data | |
2368 | * | |
2369 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2370 | * and storing the retrieved information in data. Release any acquired | |
2371 | * semaphores before exiting. | |
2372 | **/ | |
2373 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) | |
2374 | { | |
2375 | s32 ret_val; | |
2376 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2377 | ||
94d8186a | 2378 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2379 | if (ret_val) |
2380 | return ret_val; | |
2381 | ||
4662e82b BA |
2382 | /* Page 800 works differently than the rest so it has its own func */ |
2383 | if (page == BM_WUC_PAGE) { | |
2384 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2385 | true); | |
5ccdcecb | 2386 | goto out; |
4662e82b BA |
2387 | } |
2388 | ||
4662e82b BA |
2389 | hw->phy.addr = 1; |
2390 | ||
2391 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2392 | ||
2393 | /* Page is shifted left, PHY expects (page x 32) */ | |
2394 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2395 | page); | |
2396 | ||
5ccdcecb BA |
2397 | if (ret_val) |
2398 | goto out; | |
4662e82b BA |
2399 | } |
2400 | ||
2401 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2402 | data); | |
5ccdcecb | 2403 | out: |
94d8186a | 2404 | hw->phy.ops.release(hw); |
4662e82b BA |
2405 | return ret_val; |
2406 | } | |
2407 | ||
2408 | /** | |
2409 | * e1000e_write_phy_reg_bm2 - Write BM PHY register | |
2410 | * @hw: pointer to the HW structure | |
2411 | * @offset: register offset to write to | |
2412 | * @data: data to write at register offset | |
2413 | * | |
2414 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2415 | * at the offset. Release any acquired semaphores before exiting. | |
2416 | **/ | |
2417 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) | |
2418 | { | |
2419 | s32 ret_val; | |
2420 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2421 | ||
94d8186a | 2422 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2423 | if (ret_val) |
2424 | return ret_val; | |
2425 | ||
4662e82b BA |
2426 | /* Page 800 works differently than the rest so it has its own func */ |
2427 | if (page == BM_WUC_PAGE) { | |
2428 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2429 | false); | |
5ccdcecb | 2430 | goto out; |
4662e82b BA |
2431 | } |
2432 | ||
4662e82b BA |
2433 | hw->phy.addr = 1; |
2434 | ||
2435 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2436 | /* Page is shifted left, PHY expects (page x 32) */ | |
2437 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2438 | page); | |
2439 | ||
5ccdcecb BA |
2440 | if (ret_val) |
2441 | goto out; | |
4662e82b BA |
2442 | } |
2443 | ||
2444 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2445 | data); | |
2446 | ||
5ccdcecb | 2447 | out: |
94d8186a | 2448 | hw->phy.ops.release(hw); |
4662e82b BA |
2449 | return ret_val; |
2450 | } | |
2451 | ||
97ac8cae BA |
2452 | /** |
2453 | * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register | |
2454 | * @hw: pointer to the HW structure | |
2455 | * @offset: register offset to be read or written | |
2456 | * @data: pointer to the data to read or write | |
2457 | * @read: determines if operation is read or write | |
2458 | * | |
2459 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2460 | * and storing the retrieved information in data. Release any acquired | |
2461 | * semaphores before exiting. Note that procedure to read the wakeup | |
2462 | * registers are different. It works as such: | |
2463 | * 1) Set page 769, register 17, bit 2 = 1 | |
2464 | * 2) Set page to 800 for host (801 if we were manageability) | |
2465 | * 3) Write the address using the address opcode (0x11) | |
2466 | * 4) Read or write the data using the data opcode (0x12) | |
2467 | * 5) Restore 769_17.2 to its original value | |
5ccdcecb BA |
2468 | * |
2469 | * Assumes semaphore already acquired. | |
97ac8cae BA |
2470 | **/ |
2471 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
2472 | u16 *data, bool read) | |
2473 | { | |
2474 | s32 ret_val; | |
a4f58f54 | 2475 | u16 reg = BM_PHY_REG_NUM(offset); |
97ac8cae | 2476 | u16 phy_reg = 0; |
97ac8cae | 2477 | |
a4f58f54 BA |
2478 | /* Gig must be disabled for MDIO accesses to page 800 */ |
2479 | if ((hw->mac.type == e1000_pchlan) && | |
2480 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) | |
9b71b419 | 2481 | e_dbg("Attempting to access page 800 while gig enabled.\n"); |
a4f58f54 | 2482 | |
97ac8cae BA |
2483 | /* All operations in this function are phy address 1 */ |
2484 | hw->phy.addr = 1; | |
2485 | ||
2486 | /* Set page 769 */ | |
2487 | e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2488 | (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); | |
2489 | ||
2490 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); | |
9b71b419 BA |
2491 | if (ret_val) { |
2492 | e_dbg("Could not read PHY page 769\n"); | |
97ac8cae | 2493 | goto out; |
9b71b419 | 2494 | } |
97ac8cae BA |
2495 | |
2496 | /* First clear bit 4 to avoid a power state change */ | |
2497 | phy_reg &= ~(BM_WUC_HOST_WU_BIT); | |
2498 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); | |
9b71b419 BA |
2499 | if (ret_val) { |
2500 | e_dbg("Could not clear PHY page 769 bit 4\n"); | |
97ac8cae | 2501 | goto out; |
9b71b419 | 2502 | } |
97ac8cae BA |
2503 | |
2504 | /* Write bit 2 = 1, and clear bit 4 to 769_17 */ | |
2505 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, | |
2506 | phy_reg | BM_WUC_ENABLE_BIT); | |
9b71b419 BA |
2507 | if (ret_val) { |
2508 | e_dbg("Could not write PHY page 769 bit 2\n"); | |
97ac8cae | 2509 | goto out; |
9b71b419 | 2510 | } |
97ac8cae BA |
2511 | |
2512 | /* Select page 800 */ | |
2513 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2514 | (BM_WUC_PAGE << IGP_PAGE_SHIFT)); | |
2515 | ||
2516 | /* Write the page 800 offset value using opcode 0x11 */ | |
2517 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); | |
9b71b419 BA |
2518 | if (ret_val) { |
2519 | e_dbg("Could not write address opcode to page 800\n"); | |
97ac8cae | 2520 | goto out; |
9b71b419 | 2521 | } |
97ac8cae BA |
2522 | |
2523 | if (read) { | |
2524 | /* Read the page 800 value using opcode 0x12 */ | |
2525 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, | |
2526 | data); | |
2527 | } else { | |
5ff5b664 | 2528 | /* Write the page 800 value using opcode 0x12 */ |
97ac8cae BA |
2529 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
2530 | *data); | |
2531 | } | |
2532 | ||
9b71b419 BA |
2533 | if (ret_val) { |
2534 | e_dbg("Could not access data value from page 800\n"); | |
97ac8cae | 2535 | goto out; |
9b71b419 | 2536 | } |
97ac8cae BA |
2537 | |
2538 | /* | |
2539 | * Restore 769_17.2 to its original value | |
2540 | * Set page 769 | |
2541 | */ | |
2542 | e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2543 | (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); | |
2544 | ||
2545 | /* Clear 769_17.2 */ | |
2546 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); | |
9b71b419 BA |
2547 | if (ret_val) { |
2548 | e_dbg("Could not clear PHY page 769 bit 2\n"); | |
2549 | goto out; | |
2550 | } | |
97ac8cae BA |
2551 | |
2552 | out: | |
97ac8cae BA |
2553 | return ret_val; |
2554 | } | |
2555 | ||
17f208de BA |
2556 | /** |
2557 | * e1000_power_up_phy_copper - Restore copper link in case of PHY power down | |
2558 | * @hw: pointer to the HW structure | |
2559 | * | |
2560 | * In the case of a PHY power down to save power, or to turn off link during a | |
2561 | * driver unload, or wake on lan is not enabled, restore the link to previous | |
2562 | * settings. | |
2563 | **/ | |
2564 | void e1000_power_up_phy_copper(struct e1000_hw *hw) | |
2565 | { | |
2566 | u16 mii_reg = 0; | |
2567 | ||
2568 | /* The PHY will retain its settings across a power down/up cycle */ | |
2569 | e1e_rphy(hw, PHY_CONTROL, &mii_reg); | |
2570 | mii_reg &= ~MII_CR_POWER_DOWN; | |
2571 | e1e_wphy(hw, PHY_CONTROL, mii_reg); | |
2572 | } | |
2573 | ||
2574 | /** | |
2575 | * e1000_power_down_phy_copper - Restore copper link in case of PHY power down | |
2576 | * @hw: pointer to the HW structure | |
2577 | * | |
2578 | * In the case of a PHY power down to save power, or to turn off link during a | |
2579 | * driver unload, or wake on lan is not enabled, restore the link to previous | |
2580 | * settings. | |
2581 | **/ | |
2582 | void e1000_power_down_phy_copper(struct e1000_hw *hw) | |
2583 | { | |
2584 | u16 mii_reg = 0; | |
2585 | ||
2586 | /* The PHY will retain its settings across a power down/up cycle */ | |
2587 | e1e_rphy(hw, PHY_CONTROL, &mii_reg); | |
2588 | mii_reg |= MII_CR_POWER_DOWN; | |
2589 | e1e_wphy(hw, PHY_CONTROL, mii_reg); | |
2590 | msleep(1); | |
2591 | } | |
2592 | ||
bc7f75fa AK |
2593 | /** |
2594 | * e1000e_commit_phy - Soft PHY reset | |
2595 | * @hw: pointer to the HW structure | |
2596 | * | |
2597 | * Performs a soft PHY reset on those that apply. This is a function pointer | |
2598 | * entry point called by drivers. | |
2599 | **/ | |
2600 | s32 e1000e_commit_phy(struct e1000_hw *hw) | |
2601 | { | |
94d8186a BA |
2602 | if (hw->phy.ops.commit) |
2603 | return hw->phy.ops.commit(hw); | |
bc7f75fa AK |
2604 | |
2605 | return 0; | |
2606 | } | |
2607 | ||
2608 | /** | |
2609 | * e1000_set_d0_lplu_state - Sets low power link up state for D0 | |
2610 | * @hw: pointer to the HW structure | |
2611 | * @active: boolean used to enable/disable lplu | |
2612 | * | |
2613 | * Success returns 0, Failure returns 1 | |
2614 | * | |
2615 | * The low power link up (lplu) state is set to the power management level D0 | |
2616 | * and SmartSpeed is disabled when active is true, else clear lplu for D0 | |
2617 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
2618 | * is used during Dx states where the power conservation is most important. | |
2619 | * During driver activity, SmartSpeed should be enabled so performance is | |
2620 | * maintained. This is a function pointer entry point called by drivers. | |
2621 | **/ | |
2622 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) | |
2623 | { | |
2624 | if (hw->phy.ops.set_d0_lplu_state) | |
2625 | return hw->phy.ops.set_d0_lplu_state(hw, active); | |
2626 | ||
2627 | return 0; | |
2628 | } | |
a4f58f54 | 2629 | |
5ccdcecb BA |
2630 | /** |
2631 | * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode | |
2632 | * @hw: pointer to the HW structure | |
2633 | * @slow: true for slow mode, false for normal mode | |
2634 | * | |
2635 | * Assumes semaphore already acquired. | |
2636 | **/ | |
a4f58f54 BA |
2637 | s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow) |
2638 | { | |
2639 | s32 ret_val = 0; | |
2640 | u16 data = 0; | |
2641 | ||
a4f58f54 BA |
2642 | /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */ |
2643 | hw->phy.addr = 1; | |
2644 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2645 | (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | |
5ccdcecb BA |
2646 | if (ret_val) |
2647 | goto out; | |
2648 | ||
a4f58f54 BA |
2649 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1, |
2650 | (0x2180 | (slow << 10))); | |
5ccdcecb BA |
2651 | if (ret_val) |
2652 | goto out; | |
a4f58f54 BA |
2653 | |
2654 | /* dummy read when reverting to fast mode - throw away result */ | |
2655 | if (!slow) | |
5ccdcecb | 2656 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data); |
a4f58f54 | 2657 | |
5ccdcecb | 2658 | out: |
a4f58f54 BA |
2659 | return ret_val; |
2660 | } | |
2661 | ||
2662 | /** | |
5ccdcecb | 2663 | * __e1000_read_phy_reg_hv - Read HV PHY register |
a4f58f54 BA |
2664 | * @hw: pointer to the HW structure |
2665 | * @offset: register offset to be read | |
2666 | * @data: pointer to the read data | |
5ccdcecb | 2667 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2668 | * |
2669 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 2670 | * and stores the retrieved information in data. Release any acquired |
a4f58f54 BA |
2671 | * semaphore before exiting. |
2672 | **/ | |
5ccdcecb BA |
2673 | static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
2674 | bool locked) | |
a4f58f54 BA |
2675 | { |
2676 | s32 ret_val; | |
2677 | u16 page = BM_PHY_REG_PAGE(offset); | |
2678 | u16 reg = BM_PHY_REG_NUM(offset); | |
2679 | bool in_slow_mode = false; | |
2680 | ||
5ccdcecb | 2681 | if (!locked) { |
94d8186a | 2682 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2683 | if (ret_val) |
2684 | return ret_val; | |
2685 | } | |
2686 | ||
a4f58f54 BA |
2687 | /* Workaround failure in MDIO access while cable is disconnected */ |
2688 | if ((hw->phy.type == e1000_phy_82577) && | |
2689 | !(er32(STATUS) & E1000_STATUS_LU)) { | |
2690 | ret_val = e1000_set_mdio_slow_mode_hv(hw, true); | |
2691 | if (ret_val) | |
2692 | goto out; | |
2693 | ||
2694 | in_slow_mode = true; | |
2695 | } | |
2696 | ||
2697 | /* Page 800 works differently than the rest so it has its own func */ | |
2698 | if (page == BM_WUC_PAGE) { | |
2699 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, | |
2700 | data, true); | |
2701 | goto out; | |
2702 | } | |
2703 | ||
2704 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2705 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2706 | data, true); | |
2707 | goto out; | |
2708 | } | |
2709 | ||
a4f58f54 BA |
2710 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
2711 | ||
2712 | if (page == HV_INTC_FC_PAGE_START) | |
2713 | page = 0; | |
2714 | ||
2715 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | |
842ec8b6 | 2716 | u32 phy_addr = hw->phy.addr; |
a4f58f54 | 2717 | |
842ec8b6 | 2718 | hw->phy.addr = 1; |
a4f58f54 | 2719 | |
842ec8b6 BA |
2720 | /* Page is shifted left, PHY expects (page x 32) */ |
2721 | ret_val = e1000e_write_phy_reg_mdic(hw, | |
2722 | IGP01E1000_PHY_PAGE_SELECT, | |
2723 | (page << IGP_PAGE_SHIFT)); | |
2724 | hw->phy.addr = phy_addr; | |
2725 | ||
2726 | if (ret_val) | |
2727 | goto out; | |
a4f58f54 BA |
2728 | } |
2729 | ||
2730 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | |
2731 | data); | |
a4f58f54 BA |
2732 | out: |
2733 | /* Revert to MDIO fast mode, if applicable */ | |
2734 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | |
842ec8b6 | 2735 | ret_val |= e1000_set_mdio_slow_mode_hv(hw, false); |
a4f58f54 | 2736 | |
5ccdcecb | 2737 | if (!locked) |
94d8186a | 2738 | hw->phy.ops.release(hw); |
5ccdcecb | 2739 | |
a4f58f54 BA |
2740 | return ret_val; |
2741 | } | |
2742 | ||
2743 | /** | |
5ccdcecb BA |
2744 | * e1000_read_phy_reg_hv - Read HV PHY register |
2745 | * @hw: pointer to the HW structure | |
2746 | * @offset: register offset to be read | |
2747 | * @data: pointer to the read data | |
2748 | * | |
2749 | * Acquires semaphore then reads the PHY register at offset and stores | |
2750 | * the retrieved information in data. Release the acquired semaphore | |
2751 | * before exiting. | |
2752 | **/ | |
2753 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |
2754 | { | |
2755 | return __e1000_read_phy_reg_hv(hw, offset, data, false); | |
2756 | } | |
2757 | ||
2758 | /** | |
2759 | * e1000_read_phy_reg_hv_locked - Read HV PHY register | |
2760 | * @hw: pointer to the HW structure | |
2761 | * @offset: register offset to be read | |
2762 | * @data: pointer to the read data | |
2763 | * | |
2764 | * Reads the PHY register at offset and stores the retrieved information | |
2765 | * in data. Assumes semaphore already acquired. | |
2766 | **/ | |
2767 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
2768 | { | |
2769 | return __e1000_read_phy_reg_hv(hw, offset, data, true); | |
2770 | } | |
2771 | ||
2772 | /** | |
2773 | * __e1000_write_phy_reg_hv - Write HV PHY register | |
a4f58f54 BA |
2774 | * @hw: pointer to the HW structure |
2775 | * @offset: register offset to write to | |
2776 | * @data: data to write at register offset | |
5ccdcecb | 2777 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2778 | * |
2779 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2780 | * at the offset. Release any acquired semaphores before exiting. | |
2781 | **/ | |
5ccdcecb BA |
2782 | static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
2783 | bool locked) | |
a4f58f54 BA |
2784 | { |
2785 | s32 ret_val; | |
2786 | u16 page = BM_PHY_REG_PAGE(offset); | |
2787 | u16 reg = BM_PHY_REG_NUM(offset); | |
2788 | bool in_slow_mode = false; | |
2789 | ||
5ccdcecb | 2790 | if (!locked) { |
94d8186a | 2791 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2792 | if (ret_val) |
2793 | return ret_val; | |
2794 | } | |
2795 | ||
a4f58f54 BA |
2796 | /* Workaround failure in MDIO access while cable is disconnected */ |
2797 | if ((hw->phy.type == e1000_phy_82577) && | |
2798 | !(er32(STATUS) & E1000_STATUS_LU)) { | |
2799 | ret_val = e1000_set_mdio_slow_mode_hv(hw, true); | |
2800 | if (ret_val) | |
2801 | goto out; | |
2802 | ||
2803 | in_slow_mode = true; | |
2804 | } | |
2805 | ||
2806 | /* Page 800 works differently than the rest so it has its own func */ | |
2807 | if (page == BM_WUC_PAGE) { | |
2808 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, | |
2809 | &data, false); | |
2810 | goto out; | |
2811 | } | |
2812 | ||
2813 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2814 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2815 | &data, false); | |
2816 | goto out; | |
2817 | } | |
2818 | ||
a4f58f54 BA |
2819 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
2820 | ||
2821 | if (page == HV_INTC_FC_PAGE_START) | |
2822 | page = 0; | |
2823 | ||
2824 | /* | |
2825 | * Workaround MDIO accesses being disabled after entering IEEE Power | |
2826 | * Down (whenever bit 11 of the PHY Control register is set) | |
2827 | */ | |
2828 | if ((hw->phy.type == e1000_phy_82578) && | |
2829 | (hw->phy.revision >= 1) && | |
2830 | (hw->phy.addr == 2) && | |
2831 | ((MAX_PHY_REG_ADDRESS & reg) == 0) && | |
2832 | (data & (1 << 11))) { | |
2833 | u16 data2 = 0x7EFF; | |
a4f58f54 BA |
2834 | ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, |
2835 | &data2, false); | |
2836 | if (ret_val) | |
2837 | goto out; | |
a4f58f54 BA |
2838 | } |
2839 | ||
2840 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | |
842ec8b6 | 2841 | u32 phy_addr = hw->phy.addr; |
a4f58f54 | 2842 | |
842ec8b6 | 2843 | hw->phy.addr = 1; |
a4f58f54 | 2844 | |
842ec8b6 BA |
2845 | /* Page is shifted left, PHY expects (page x 32) */ |
2846 | ret_val = e1000e_write_phy_reg_mdic(hw, | |
2847 | IGP01E1000_PHY_PAGE_SELECT, | |
2848 | (page << IGP_PAGE_SHIFT)); | |
2849 | hw->phy.addr = phy_addr; | |
2850 | ||
2851 | if (ret_val) | |
2852 | goto out; | |
a4f58f54 BA |
2853 | } |
2854 | ||
2855 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | |
2856 | data); | |
a4f58f54 BA |
2857 | |
2858 | out: | |
2859 | /* Revert to MDIO fast mode, if applicable */ | |
2860 | if ((hw->phy.type == e1000_phy_82577) && in_slow_mode) | |
842ec8b6 | 2861 | ret_val |= e1000_set_mdio_slow_mode_hv(hw, false); |
a4f58f54 | 2862 | |
5ccdcecb | 2863 | if (!locked) |
94d8186a | 2864 | hw->phy.ops.release(hw); |
5ccdcecb | 2865 | |
a4f58f54 BA |
2866 | return ret_val; |
2867 | } | |
2868 | ||
5ccdcecb BA |
2869 | /** |
2870 | * e1000_write_phy_reg_hv - Write HV PHY register | |
2871 | * @hw: pointer to the HW structure | |
2872 | * @offset: register offset to write to | |
2873 | * @data: data to write at register offset | |
2874 | * | |
2875 | * Acquires semaphore then writes the data to PHY register at the offset. | |
2876 | * Release the acquired semaphores before exiting. | |
2877 | **/ | |
2878 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | |
2879 | { | |
2880 | return __e1000_write_phy_reg_hv(hw, offset, data, false); | |
2881 | } | |
2882 | ||
2883 | /** | |
2884 | * e1000_write_phy_reg_hv_locked - Write HV PHY register | |
2885 | * @hw: pointer to the HW structure | |
2886 | * @offset: register offset to write to | |
2887 | * @data: data to write at register offset | |
2888 | * | |
2889 | * Writes the data to PHY register at the offset. Assumes semaphore | |
2890 | * already acquired. | |
2891 | **/ | |
2892 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
2893 | { | |
2894 | return __e1000_write_phy_reg_hv(hw, offset, data, true); | |
2895 | } | |
2896 | ||
a4f58f54 BA |
2897 | /** |
2898 | * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page | |
2899 | * @page: page to be accessed | |
2900 | **/ | |
2901 | static u32 e1000_get_phy_addr_for_hv_page(u32 page) | |
2902 | { | |
2903 | u32 phy_addr = 2; | |
2904 | ||
2905 | if (page >= HV_INTC_FC_PAGE_START) | |
2906 | phy_addr = 1; | |
2907 | ||
2908 | return phy_addr; | |
2909 | } | |
2910 | ||
2911 | /** | |
2912 | * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers | |
2913 | * @hw: pointer to the HW structure | |
2914 | * @offset: register offset to be read or written | |
2915 | * @data: pointer to the data to be read or written | |
2916 | * @read: determines if operation is read or written | |
2917 | * | |
5ccdcecb BA |
2918 | * Reads the PHY register at offset and stores the retreived information |
2919 | * in data. Assumes semaphore already acquired. Note that the procedure | |
2920 | * to read these regs uses the address port and data port to read/write. | |
a4f58f54 BA |
2921 | **/ |
2922 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
2923 | u16 *data, bool read) | |
2924 | { | |
2925 | s32 ret_val; | |
2926 | u32 addr_reg = 0; | |
2927 | u32 data_reg = 0; | |
a4f58f54 BA |
2928 | |
2929 | /* This takes care of the difference with desktop vs mobile phy */ | |
2930 | addr_reg = (hw->phy.type == e1000_phy_82578) ? | |
2931 | I82578_ADDR_REG : I82577_ADDR_REG; | |
2932 | data_reg = addr_reg + 1; | |
2933 | ||
a4f58f54 BA |
2934 | /* All operations in this function are phy address 2 */ |
2935 | hw->phy.addr = 2; | |
2936 | ||
2937 | /* masking with 0x3F to remove the page from offset */ | |
2938 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); | |
2939 | if (ret_val) { | |
3bb99fe2 | 2940 | e_dbg("Could not write PHY the HV address register\n"); |
a4f58f54 BA |
2941 | goto out; |
2942 | } | |
2943 | ||
2944 | /* Read or write the data value next */ | |
2945 | if (read) | |
2946 | ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); | |
2947 | else | |
2948 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); | |
2949 | ||
2950 | if (ret_val) { | |
3bb99fe2 | 2951 | e_dbg("Could not read data value from HV data register\n"); |
a4f58f54 BA |
2952 | goto out; |
2953 | } | |
2954 | ||
2955 | out: | |
a4f58f54 BA |
2956 | return ret_val; |
2957 | } | |
2958 | ||
2959 | /** | |
2960 | * e1000_link_stall_workaround_hv - Si workaround | |
2961 | * @hw: pointer to the HW structure | |
2962 | * | |
2963 | * This function works around a Si bug where the link partner can get | |
2964 | * a link up indication before the PHY does. If small packets are sent | |
2965 | * by the link partner they can be placed in the packet buffer without | |
2966 | * being properly accounted for by the PHY and will stall preventing | |
2967 | * further packets from being received. The workaround is to clear the | |
2968 | * packet buffer after the PHY detects link up. | |
2969 | **/ | |
2970 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) | |
2971 | { | |
2972 | s32 ret_val = 0; | |
2973 | u16 data; | |
2974 | ||
2975 | if (hw->phy.type != e1000_phy_82578) | |
2976 | goto out; | |
2977 | ||
e65fa87c | 2978 | /* Do not apply workaround if in PHY loopback bit 14 set */ |
94d8186a | 2979 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); |
e65fa87c BA |
2980 | if (data & PHY_CONTROL_LB) |
2981 | goto out; | |
2982 | ||
a4f58f54 | 2983 | /* check if link is up and at 1Gbps */ |
94d8186a | 2984 | ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); |
a4f58f54 BA |
2985 | if (ret_val) |
2986 | goto out; | |
2987 | ||
2988 | data &= BM_CS_STATUS_LINK_UP | | |
2989 | BM_CS_STATUS_RESOLVED | | |
2990 | BM_CS_STATUS_SPEED_MASK; | |
2991 | ||
2992 | if (data != (BM_CS_STATUS_LINK_UP | | |
2993 | BM_CS_STATUS_RESOLVED | | |
2994 | BM_CS_STATUS_SPEED_1000)) | |
2995 | goto out; | |
2996 | ||
2997 | mdelay(200); | |
2998 | ||
2999 | /* flush the packets in the fifo buffer */ | |
94d8186a | 3000 | ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, |
a4f58f54 BA |
3001 | HV_MUX_DATA_CTRL_GEN_TO_MAC | |
3002 | HV_MUX_DATA_CTRL_FORCE_SPEED); | |
3003 | if (ret_val) | |
3004 | goto out; | |
3005 | ||
94d8186a | 3006 | ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, |
a4f58f54 BA |
3007 | HV_MUX_DATA_CTRL_GEN_TO_MAC); |
3008 | ||
3009 | out: | |
3010 | return ret_val; | |
3011 | } | |
3012 | ||
3013 | /** | |
3014 | * e1000_check_polarity_82577 - Checks the polarity. | |
3015 | * @hw: pointer to the HW structure | |
3016 | * | |
3017 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
3018 | * | |
3019 | * Polarity is determined based on the PHY specific status register. | |
3020 | **/ | |
3021 | s32 e1000_check_polarity_82577(struct e1000_hw *hw) | |
3022 | { | |
3023 | struct e1000_phy_info *phy = &hw->phy; | |
3024 | s32 ret_val; | |
3025 | u16 data; | |
3026 | ||
94d8186a | 3027 | ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 BA |
3028 | |
3029 | if (!ret_val) | |
3030 | phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) | |
3031 | ? e1000_rev_polarity_reversed | |
3032 | : e1000_rev_polarity_normal; | |
3033 | ||
3034 | return ret_val; | |
3035 | } | |
3036 | ||
3037 | /** | |
3038 | * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY | |
3039 | * @hw: pointer to the HW structure | |
3040 | * | |
3041 | * Calls the PHY setup function to force speed and duplex. Clears the | |
3042 | * auto-crossover to force MDI manually. Waits for link and returns | |
3043 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
3044 | **/ | |
3045 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) | |
3046 | { | |
3047 | struct e1000_phy_info *phy = &hw->phy; | |
3048 | s32 ret_val; | |
3049 | u16 phy_data; | |
3050 | bool link; | |
3051 | ||
94d8186a | 3052 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
a4f58f54 BA |
3053 | if (ret_val) |
3054 | goto out; | |
3055 | ||
3056 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
3057 | ||
94d8186a | 3058 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
a4f58f54 BA |
3059 | if (ret_val) |
3060 | goto out; | |
3061 | ||
3062 | /* | |
3063 | * Clear Auto-Crossover to force MDI manually. 82577 requires MDI | |
3064 | * forced whenever speed and duplex are forced. | |
3065 | */ | |
94d8186a | 3066 | ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); |
a4f58f54 BA |
3067 | if (ret_val) |
3068 | goto out; | |
3069 | ||
3070 | phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX; | |
3071 | phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX; | |
3072 | ||
94d8186a | 3073 | ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); |
a4f58f54 BA |
3074 | if (ret_val) |
3075 | goto out; | |
3076 | ||
3bb99fe2 | 3077 | e_dbg("I82577_PHY_CTRL_2: %X\n", phy_data); |
a4f58f54 BA |
3078 | |
3079 | udelay(1); | |
3080 | ||
3081 | if (phy->autoneg_wait_to_complete) { | |
3bb99fe2 | 3082 | e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
a4f58f54 BA |
3083 | |
3084 | ret_val = e1000e_phy_has_link_generic(hw, | |
3085 | PHY_FORCE_LIMIT, | |
3086 | 100000, | |
3087 | &link); | |
3088 | if (ret_val) | |
3089 | goto out; | |
3090 | ||
3091 | if (!link) | |
3bb99fe2 | 3092 | e_dbg("Link taking longer than expected.\n"); |
a4f58f54 BA |
3093 | |
3094 | /* Try once more */ | |
3095 | ret_val = e1000e_phy_has_link_generic(hw, | |
3096 | PHY_FORCE_LIMIT, | |
3097 | 100000, | |
3098 | &link); | |
3099 | if (ret_val) | |
3100 | goto out; | |
3101 | } | |
3102 | ||
3103 | out: | |
3104 | return ret_val; | |
3105 | } | |
3106 | ||
3107 | /** | |
3108 | * e1000_get_phy_info_82577 - Retrieve I82577 PHY information | |
3109 | * @hw: pointer to the HW structure | |
3110 | * | |
3111 | * Read PHY status to determine if link is up. If link is up, then | |
3112 | * set/determine 10base-T extended distance and polarity correction. Read | |
3113 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
3114 | * determine on the cable length, local and remote receiver. | |
3115 | **/ | |
3116 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw) | |
3117 | { | |
3118 | struct e1000_phy_info *phy = &hw->phy; | |
3119 | s32 ret_val; | |
3120 | u16 data; | |
3121 | bool link; | |
3122 | ||
3123 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
3124 | if (ret_val) | |
3125 | goto out; | |
3126 | ||
3127 | if (!link) { | |
3bb99fe2 | 3128 | e_dbg("Phy info is only valid if link is up\n"); |
a4f58f54 BA |
3129 | ret_val = -E1000_ERR_CONFIG; |
3130 | goto out; | |
3131 | } | |
3132 | ||
3133 | phy->polarity_correction = true; | |
3134 | ||
3135 | ret_val = e1000_check_polarity_82577(hw); | |
3136 | if (ret_val) | |
3137 | goto out; | |
3138 | ||
94d8186a | 3139 | ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 BA |
3140 | if (ret_val) |
3141 | goto out; | |
3142 | ||
3143 | phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; | |
3144 | ||
3145 | if ((data & I82577_PHY_STATUS2_SPEED_MASK) == | |
3146 | I82577_PHY_STATUS2_SPEED_1000MBPS) { | |
3147 | ret_val = hw->phy.ops.get_cable_length(hw); | |
3148 | if (ret_val) | |
3149 | goto out; | |
3150 | ||
94d8186a | 3151 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
a4f58f54 BA |
3152 | if (ret_val) |
3153 | goto out; | |
3154 | ||
3155 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
3156 | ? e1000_1000t_rx_status_ok | |
3157 | : e1000_1000t_rx_status_not_ok; | |
3158 | ||
3159 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
3160 | ? e1000_1000t_rx_status_ok | |
3161 | : e1000_1000t_rx_status_not_ok; | |
3162 | } else { | |
3163 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
3164 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
3165 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
3166 | } | |
3167 | ||
3168 | out: | |
3169 | return ret_val; | |
3170 | } | |
3171 | ||
3172 | /** | |
3173 | * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY | |
3174 | * @hw: pointer to the HW structure | |
3175 | * | |
3176 | * Reads the diagnostic status register and verifies result is valid before | |
3177 | * placing it in the phy_cable_length field. | |
3178 | **/ | |
3179 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw) | |
3180 | { | |
3181 | struct e1000_phy_info *phy = &hw->phy; | |
3182 | s32 ret_val; | |
3183 | u16 phy_data, length; | |
3184 | ||
94d8186a | 3185 | ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
a4f58f54 BA |
3186 | if (ret_val) |
3187 | goto out; | |
3188 | ||
3189 | length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> | |
3190 | I82577_DSTATUS_CABLE_LENGTH_SHIFT; | |
3191 | ||
3192 | if (length == E1000_CABLE_LENGTH_UNDEFINED) | |
98086a95 | 3193 | ret_val = -E1000_ERR_PHY; |
a4f58f54 BA |
3194 | |
3195 | phy->cable_length = length; | |
3196 | ||
3197 | out: | |
3198 | return ret_val; | |
3199 | } |