Commit | Line | Data |
---|---|---|
bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
451152d9 | 4 | Copyright(c) 1999 - 2010 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
29 | #include <linux/delay.h> | |
30 | ||
31 | #include "e1000.h" | |
32 | ||
33 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw); | |
34 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); | |
35 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active); | |
36 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); | |
97ac8cae BA |
37 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg); |
38 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
39 | u16 *data, bool read); | |
a4f58f54 BA |
40 | static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
41 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
42 | u16 *data, bool read); | |
bc7f75fa AK |
43 | |
44 | /* Cable length tables */ | |
45 | static const u16 e1000_m88_cable_length_table[] = | |
46 | { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
eb656d45 BA |
47 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
48 | ARRAY_SIZE(e1000_m88_cable_length_table) | |
bc7f75fa AK |
49 | |
50 | static const u16 e1000_igp_2_cable_length_table[] = | |
51 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, | |
52 | 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, | |
53 | 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, | |
54 | 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, | |
55 | 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, | |
56 | 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, | |
57 | 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, | |
58 | 124}; | |
59 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ | |
c00acf46 | 60 | ARRAY_SIZE(e1000_igp_2_cable_length_table) |
bc7f75fa | 61 | |
a4f58f54 BA |
62 | #define BM_PHY_REG_PAGE(offset) \ |
63 | ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) | |
64 | #define BM_PHY_REG_NUM(offset) \ | |
65 | ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ | |
66 | (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ | |
67 | ~MAX_PHY_REG_ADDRESS))) | |
68 | ||
69 | #define HV_INTC_FC_PAGE_START 768 | |
70 | #define I82578_ADDR_REG 29 | |
71 | #define I82577_ADDR_REG 16 | |
72 | #define I82577_CFG_REG 22 | |
73 | #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) | |
74 | #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ | |
75 | #define I82577_CTRL_REG 23 | |
a4f58f54 BA |
76 | |
77 | /* 82577 specific PHY registers */ | |
78 | #define I82577_PHY_CTRL_2 18 | |
79 | #define I82577_PHY_STATUS_2 26 | |
80 | #define I82577_PHY_DIAG_STATUS 31 | |
81 | ||
82 | /* I82577 PHY Status 2 */ | |
83 | #define I82577_PHY_STATUS2_REV_POLARITY 0x0400 | |
84 | #define I82577_PHY_STATUS2_MDIX 0x0800 | |
85 | #define I82577_PHY_STATUS2_SPEED_MASK 0x0300 | |
86 | #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 | |
87 | ||
88 | /* I82577 PHY Control 2 */ | |
89 | #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400 | |
90 | #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 | |
91 | ||
92 | /* I82577 PHY Diagnostics Status */ | |
93 | #define I82577_DSTATUS_CABLE_LENGTH 0x03FC | |
94 | #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 | |
95 | ||
96 | /* BM PHY Copper Specific Control 1 */ | |
97 | #define BM_CS_CTRL1 16 | |
98 | ||
a4f58f54 BA |
99 | #define HV_MUX_DATA_CTRL PHY_REG(776, 16) |
100 | #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 | |
101 | #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 | |
102 | ||
bc7f75fa AK |
103 | /** |
104 | * e1000e_check_reset_block_generic - Check if PHY reset is blocked | |
105 | * @hw: pointer to the HW structure | |
106 | * | |
107 | * Read the PHY management control register and check whether a PHY reset | |
108 | * is blocked. If a reset is not blocked return 0, otherwise | |
109 | * return E1000_BLK_PHY_RESET (12). | |
110 | **/ | |
111 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) | |
112 | { | |
113 | u32 manc; | |
114 | ||
115 | manc = er32(MANC); | |
116 | ||
117 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
118 | E1000_BLK_PHY_RESET : 0; | |
119 | } | |
120 | ||
121 | /** | |
122 | * e1000e_get_phy_id - Retrieve the PHY ID and revision | |
123 | * @hw: pointer to the HW structure | |
124 | * | |
125 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
126 | * revision in the hardware structure. | |
127 | **/ | |
128 | s32 e1000e_get_phy_id(struct e1000_hw *hw) | |
129 | { | |
130 | struct e1000_phy_info *phy = &hw->phy; | |
a4f58f54 | 131 | s32 ret_val = 0; |
bc7f75fa | 132 | u16 phy_id; |
a4f58f54 | 133 | u16 retry_count = 0; |
bc7f75fa | 134 | |
94d8186a | 135 | if (!(phy->ops.read_reg)) |
a4f58f54 | 136 | goto out; |
bc7f75fa | 137 | |
a4f58f54 BA |
138 | while (retry_count < 2) { |
139 | ret_val = e1e_rphy(hw, PHY_ID1, &phy_id); | |
140 | if (ret_val) | |
141 | goto out; | |
bc7f75fa | 142 | |
a4f58f54 BA |
143 | phy->id = (u32)(phy_id << 16); |
144 | udelay(20); | |
145 | ret_val = e1e_rphy(hw, PHY_ID2, &phy_id); | |
146 | if (ret_val) | |
147 | goto out; | |
bc7f75fa | 148 | |
a4f58f54 BA |
149 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
150 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
151 | ||
152 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) | |
153 | goto out; | |
154 | ||
a4f58f54 BA |
155 | retry_count++; |
156 | } | |
157 | out: | |
a4f58f54 | 158 | return ret_val; |
bc7f75fa AK |
159 | } |
160 | ||
161 | /** | |
162 | * e1000e_phy_reset_dsp - Reset PHY DSP | |
163 | * @hw: pointer to the HW structure | |
164 | * | |
165 | * Reset the digital signal processor. | |
166 | **/ | |
167 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) | |
168 | { | |
169 | s32 ret_val; | |
170 | ||
171 | ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); | |
172 | if (ret_val) | |
173 | return ret_val; | |
174 | ||
175 | return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); | |
176 | } | |
177 | ||
178 | /** | |
2d9498f3 | 179 | * e1000e_read_phy_reg_mdic - Read MDI control register |
bc7f75fa AK |
180 | * @hw: pointer to the HW structure |
181 | * @offset: register offset to be read | |
182 | * @data: pointer to the read data | |
183 | * | |
489815ce | 184 | * Reads the MDI control register in the PHY at offset and stores the |
bc7f75fa AK |
185 | * information read to data. |
186 | **/ | |
2d9498f3 | 187 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
bc7f75fa AK |
188 | { |
189 | struct e1000_phy_info *phy = &hw->phy; | |
190 | u32 i, mdic = 0; | |
191 | ||
192 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 193 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
194 | return -E1000_ERR_PARAM; |
195 | } | |
196 | ||
ad68076e BA |
197 | /* |
198 | * Set up Op-code, Phy Address, and register offset in the MDI | |
bc7f75fa AK |
199 | * Control register. The MAC will take care of interfacing with the |
200 | * PHY to retrieve the desired data. | |
201 | */ | |
202 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
203 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
204 | (E1000_MDIC_OP_READ)); | |
205 | ||
206 | ew32(MDIC, mdic); | |
207 | ||
ad68076e BA |
208 | /* |
209 | * Poll the ready bit to see if the MDI read completed | |
210 | * Increasing the time out as testing showed failures with | |
211 | * the lower time out | |
212 | */ | |
2d9498f3 | 213 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
bc7f75fa AK |
214 | udelay(50); |
215 | mdic = er32(MDIC); | |
216 | if (mdic & E1000_MDIC_READY) | |
217 | break; | |
218 | } | |
219 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 220 | e_dbg("MDI Read did not complete\n"); |
bc7f75fa AK |
221 | return -E1000_ERR_PHY; |
222 | } | |
223 | if (mdic & E1000_MDIC_ERROR) { | |
3bb99fe2 | 224 | e_dbg("MDI Error\n"); |
bc7f75fa AK |
225 | return -E1000_ERR_PHY; |
226 | } | |
227 | *data = (u16) mdic; | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
232 | /** | |
2d9498f3 | 233 | * e1000e_write_phy_reg_mdic - Write MDI control register |
bc7f75fa AK |
234 | * @hw: pointer to the HW structure |
235 | * @offset: register offset to write to | |
236 | * @data: data to write to register at offset | |
237 | * | |
238 | * Writes data to MDI control register in the PHY at offset. | |
239 | **/ | |
2d9498f3 | 240 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
bc7f75fa AK |
241 | { |
242 | struct e1000_phy_info *phy = &hw->phy; | |
243 | u32 i, mdic = 0; | |
244 | ||
245 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 246 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
247 | return -E1000_ERR_PARAM; |
248 | } | |
249 | ||
ad68076e BA |
250 | /* |
251 | * Set up Op-code, Phy Address, and register offset in the MDI | |
bc7f75fa AK |
252 | * Control register. The MAC will take care of interfacing with the |
253 | * PHY to retrieve the desired data. | |
254 | */ | |
255 | mdic = (((u32)data) | | |
256 | (offset << E1000_MDIC_REG_SHIFT) | | |
257 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
258 | (E1000_MDIC_OP_WRITE)); | |
259 | ||
260 | ew32(MDIC, mdic); | |
261 | ||
2d9498f3 DG |
262 | /* |
263 | * Poll the ready bit to see if the MDI read completed | |
264 | * Increasing the time out as testing showed failures with | |
265 | * the lower time out | |
266 | */ | |
267 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
268 | udelay(50); | |
bc7f75fa AK |
269 | mdic = er32(MDIC); |
270 | if (mdic & E1000_MDIC_READY) | |
271 | break; | |
272 | } | |
273 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 274 | e_dbg("MDI Write did not complete\n"); |
bc7f75fa AK |
275 | return -E1000_ERR_PHY; |
276 | } | |
2d9498f3 | 277 | if (mdic & E1000_MDIC_ERROR) { |
3bb99fe2 | 278 | e_dbg("MDI Error\n"); |
2d9498f3 DG |
279 | return -E1000_ERR_PHY; |
280 | } | |
bc7f75fa AK |
281 | |
282 | return 0; | |
283 | } | |
284 | ||
285 | /** | |
286 | * e1000e_read_phy_reg_m88 - Read m88 PHY register | |
287 | * @hw: pointer to the HW structure | |
288 | * @offset: register offset to be read | |
289 | * @data: pointer to the read data | |
290 | * | |
291 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
292 | * and storing the retrieved information in data. Release any acquired | |
293 | * semaphores before exiting. | |
294 | **/ | |
295 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) | |
296 | { | |
297 | s32 ret_val; | |
298 | ||
94d8186a | 299 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
300 | if (ret_val) |
301 | return ret_val; | |
302 | ||
2d9498f3 DG |
303 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
304 | data); | |
bc7f75fa | 305 | |
94d8186a | 306 | hw->phy.ops.release(hw); |
bc7f75fa AK |
307 | |
308 | return ret_val; | |
309 | } | |
310 | ||
311 | /** | |
312 | * e1000e_write_phy_reg_m88 - Write m88 PHY register | |
313 | * @hw: pointer to the HW structure | |
314 | * @offset: register offset to write to | |
315 | * @data: data to write at register offset | |
316 | * | |
317 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
318 | * at the offset. Release any acquired semaphores before exiting. | |
319 | **/ | |
320 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) | |
321 | { | |
322 | s32 ret_val; | |
323 | ||
94d8186a | 324 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
325 | if (ret_val) |
326 | return ret_val; | |
327 | ||
2d9498f3 DG |
328 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
329 | data); | |
bc7f75fa | 330 | |
94d8186a | 331 | hw->phy.ops.release(hw); |
bc7f75fa AK |
332 | |
333 | return ret_val; | |
334 | } | |
335 | ||
336 | /** | |
5ccdcecb | 337 | * __e1000e_read_phy_reg_igp - Read igp PHY register |
bc7f75fa AK |
338 | * @hw: pointer to the HW structure |
339 | * @offset: register offset to be read | |
340 | * @data: pointer to the read data | |
5ccdcecb | 341 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
342 | * |
343 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 344 | * and stores the retrieved information in data. Release any acquired |
bc7f75fa AK |
345 | * semaphores before exiting. |
346 | **/ | |
5ccdcecb BA |
347 | static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
348 | bool locked) | |
bc7f75fa | 349 | { |
5ccdcecb | 350 | s32 ret_val = 0; |
bc7f75fa | 351 | |
5ccdcecb | 352 | if (!locked) { |
94d8186a | 353 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
354 | goto out; |
355 | ||
94d8186a | 356 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
357 | if (ret_val) |
358 | goto out; | |
359 | } | |
bc7f75fa AK |
360 | |
361 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2d9498f3 DG |
362 | ret_val = e1000e_write_phy_reg_mdic(hw, |
363 | IGP01E1000_PHY_PAGE_SELECT, | |
364 | (u16)offset); | |
5ccdcecb BA |
365 | if (ret_val) |
366 | goto release; | |
bc7f75fa AK |
367 | } |
368 | ||
2d9498f3 | 369 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
5ccdcecb | 370 | data); |
bc7f75fa | 371 | |
5ccdcecb BA |
372 | release: |
373 | if (!locked) | |
94d8186a | 374 | hw->phy.ops.release(hw); |
5ccdcecb | 375 | out: |
bc7f75fa AK |
376 | return ret_val; |
377 | } | |
378 | ||
5ccdcecb BA |
379 | /** |
380 | * e1000e_read_phy_reg_igp - Read igp PHY register | |
381 | * @hw: pointer to the HW structure | |
382 | * @offset: register offset to be read | |
383 | * @data: pointer to the read data | |
384 | * | |
385 | * Acquires semaphore then reads the PHY register at offset and stores the | |
386 | * retrieved information in data. | |
387 | * Release the acquired semaphore before exiting. | |
388 | **/ | |
389 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
390 | { | |
391 | return __e1000e_read_phy_reg_igp(hw, offset, data, false); | |
392 | } | |
393 | ||
394 | /** | |
395 | * e1000e_read_phy_reg_igp_locked - Read igp PHY register | |
396 | * @hw: pointer to the HW structure | |
397 | * @offset: register offset to be read | |
398 | * @data: pointer to the read data | |
399 | * | |
400 | * Reads the PHY register at offset and stores the retrieved information | |
401 | * in data. Assumes semaphore already acquired. | |
402 | **/ | |
403 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
404 | { | |
405 | return __e1000e_read_phy_reg_igp(hw, offset, data, true); | |
406 | } | |
407 | ||
bc7f75fa AK |
408 | /** |
409 | * e1000e_write_phy_reg_igp - Write igp PHY register | |
410 | * @hw: pointer to the HW structure | |
411 | * @offset: register offset to write to | |
412 | * @data: data to write at register offset | |
5ccdcecb | 413 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
414 | * |
415 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
416 | * at the offset. Release any acquired semaphores before exiting. | |
417 | **/ | |
5ccdcecb BA |
418 | static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
419 | bool locked) | |
bc7f75fa | 420 | { |
5ccdcecb | 421 | s32 ret_val = 0; |
bc7f75fa | 422 | |
5ccdcecb | 423 | if (!locked) { |
94d8186a | 424 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
425 | goto out; |
426 | ||
94d8186a | 427 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
428 | if (ret_val) |
429 | goto out; | |
430 | } | |
bc7f75fa AK |
431 | |
432 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2d9498f3 DG |
433 | ret_val = e1000e_write_phy_reg_mdic(hw, |
434 | IGP01E1000_PHY_PAGE_SELECT, | |
435 | (u16)offset); | |
5ccdcecb BA |
436 | if (ret_val) |
437 | goto release; | |
bc7f75fa AK |
438 | } |
439 | ||
2d9498f3 DG |
440 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
441 | data); | |
bc7f75fa | 442 | |
5ccdcecb BA |
443 | release: |
444 | if (!locked) | |
94d8186a | 445 | hw->phy.ops.release(hw); |
bc7f75fa | 446 | |
5ccdcecb | 447 | out: |
bc7f75fa AK |
448 | return ret_val; |
449 | } | |
450 | ||
451 | /** | |
5ccdcecb BA |
452 | * e1000e_write_phy_reg_igp - Write igp PHY register |
453 | * @hw: pointer to the HW structure | |
454 | * @offset: register offset to write to | |
455 | * @data: data to write at register offset | |
456 | * | |
457 | * Acquires semaphore then writes the data to PHY register | |
458 | * at the offset. Release any acquired semaphores before exiting. | |
459 | **/ | |
460 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
461 | { | |
462 | return __e1000e_write_phy_reg_igp(hw, offset, data, false); | |
463 | } | |
464 | ||
465 | /** | |
466 | * e1000e_write_phy_reg_igp_locked - Write igp PHY register | |
467 | * @hw: pointer to the HW structure | |
468 | * @offset: register offset to write to | |
469 | * @data: data to write at register offset | |
470 | * | |
471 | * Writes the data to PHY register at the offset. | |
472 | * Assumes semaphore already acquired. | |
473 | **/ | |
474 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
475 | { | |
476 | return __e1000e_write_phy_reg_igp(hw, offset, data, true); | |
477 | } | |
478 | ||
479 | /** | |
480 | * __e1000_read_kmrn_reg - Read kumeran register | |
bc7f75fa AK |
481 | * @hw: pointer to the HW structure |
482 | * @offset: register offset to be read | |
483 | * @data: pointer to the read data | |
5ccdcecb | 484 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
485 | * |
486 | * Acquires semaphore, if necessary. Then reads the PHY register at offset | |
487 | * using the kumeran interface. The information retrieved is stored in data. | |
488 | * Release any acquired semaphores before exiting. | |
489 | **/ | |
5ccdcecb BA |
490 | static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
491 | bool locked) | |
bc7f75fa AK |
492 | { |
493 | u32 kmrnctrlsta; | |
5ccdcecb | 494 | s32 ret_val = 0; |
bc7f75fa | 495 | |
5ccdcecb | 496 | if (!locked) { |
94d8186a | 497 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
498 | goto out; |
499 | ||
94d8186a | 500 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
501 | if (ret_val) |
502 | goto out; | |
503 | } | |
bc7f75fa AK |
504 | |
505 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
506 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
507 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
508 | ||
509 | udelay(2); | |
510 | ||
511 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
512 | *data = (u16)kmrnctrlsta; | |
513 | ||
5ccdcecb | 514 | if (!locked) |
94d8186a | 515 | hw->phy.ops.release(hw); |
bc7f75fa | 516 | |
5ccdcecb | 517 | out: |
bc7f75fa AK |
518 | return ret_val; |
519 | } | |
520 | ||
521 | /** | |
5ccdcecb BA |
522 | * e1000e_read_kmrn_reg - Read kumeran register |
523 | * @hw: pointer to the HW structure | |
524 | * @offset: register offset to be read | |
525 | * @data: pointer to the read data | |
526 | * | |
527 | * Acquires semaphore then reads the PHY register at offset using the | |
528 | * kumeran interface. The information retrieved is stored in data. | |
529 | * Release the acquired semaphore before exiting. | |
530 | **/ | |
531 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
532 | { | |
533 | return __e1000_read_kmrn_reg(hw, offset, data, false); | |
534 | } | |
535 | ||
536 | /** | |
1d5846b9 | 537 | * e1000e_read_kmrn_reg_locked - Read kumeran register |
5ccdcecb BA |
538 | * @hw: pointer to the HW structure |
539 | * @offset: register offset to be read | |
540 | * @data: pointer to the read data | |
541 | * | |
542 | * Reads the PHY register at offset using the kumeran interface. The | |
543 | * information retrieved is stored in data. | |
544 | * Assumes semaphore already acquired. | |
545 | **/ | |
1d5846b9 | 546 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
5ccdcecb BA |
547 | { |
548 | return __e1000_read_kmrn_reg(hw, offset, data, true); | |
549 | } | |
550 | ||
551 | /** | |
552 | * __e1000_write_kmrn_reg - Write kumeran register | |
bc7f75fa AK |
553 | * @hw: pointer to the HW structure |
554 | * @offset: register offset to write to | |
555 | * @data: data to write at register offset | |
5ccdcecb | 556 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
557 | * |
558 | * Acquires semaphore, if necessary. Then write the data to PHY register | |
559 | * at the offset using the kumeran interface. Release any acquired semaphores | |
560 | * before exiting. | |
561 | **/ | |
5ccdcecb BA |
562 | static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
563 | bool locked) | |
bc7f75fa AK |
564 | { |
565 | u32 kmrnctrlsta; | |
5ccdcecb | 566 | s32 ret_val = 0; |
bc7f75fa | 567 | |
5ccdcecb | 568 | if (!locked) { |
94d8186a | 569 | if (!(hw->phy.ops.acquire)) |
5ccdcecb BA |
570 | goto out; |
571 | ||
94d8186a | 572 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
573 | if (ret_val) |
574 | goto out; | |
575 | } | |
bc7f75fa AK |
576 | |
577 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
578 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
579 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
580 | ||
581 | udelay(2); | |
bc7f75fa | 582 | |
5ccdcecb | 583 | if (!locked) |
94d8186a | 584 | hw->phy.ops.release(hw); |
5ccdcecb BA |
585 | |
586 | out: | |
bc7f75fa AK |
587 | return ret_val; |
588 | } | |
589 | ||
5ccdcecb BA |
590 | /** |
591 | * e1000e_write_kmrn_reg - Write kumeran register | |
592 | * @hw: pointer to the HW structure | |
593 | * @offset: register offset to write to | |
594 | * @data: data to write at register offset | |
595 | * | |
596 | * Acquires semaphore then writes the data to the PHY register at the offset | |
597 | * using the kumeran interface. Release the acquired semaphore before exiting. | |
598 | **/ | |
599 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
600 | { | |
601 | return __e1000_write_kmrn_reg(hw, offset, data, false); | |
602 | } | |
603 | ||
604 | /** | |
1d5846b9 | 605 | * e1000e_write_kmrn_reg_locked - Write kumeran register |
5ccdcecb BA |
606 | * @hw: pointer to the HW structure |
607 | * @offset: register offset to write to | |
608 | * @data: data to write at register offset | |
609 | * | |
610 | * Write the data to PHY register at the offset using the kumeran interface. | |
611 | * Assumes semaphore already acquired. | |
612 | **/ | |
1d5846b9 | 613 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
5ccdcecb BA |
614 | { |
615 | return __e1000_write_kmrn_reg(hw, offset, data, true); | |
616 | } | |
617 | ||
a4f58f54 BA |
618 | /** |
619 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link | |
620 | * @hw: pointer to the HW structure | |
621 | * | |
622 | * Sets up Carrier-sense on Transmit and downshift values. | |
623 | **/ | |
624 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) | |
625 | { | |
626 | struct e1000_phy_info *phy = &hw->phy; | |
627 | s32 ret_val; | |
628 | u16 phy_data; | |
629 | ||
630 | /* Enable CRS on TX. This must be set for half-duplex operation. */ | |
94d8186a | 631 | ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data); |
a4f58f54 BA |
632 | if (ret_val) |
633 | goto out; | |
634 | ||
635 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; | |
636 | ||
637 | /* Enable downshift */ | |
638 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; | |
639 | ||
94d8186a | 640 | ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data); |
a4f58f54 BA |
641 | |
642 | out: | |
643 | return ret_val; | |
644 | } | |
645 | ||
bc7f75fa AK |
646 | /** |
647 | * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link | |
648 | * @hw: pointer to the HW structure | |
649 | * | |
650 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
651 | * and downshift values are set also. | |
652 | **/ | |
653 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) | |
654 | { | |
655 | struct e1000_phy_info *phy = &hw->phy; | |
656 | s32 ret_val; | |
657 | u16 phy_data; | |
658 | ||
ad68076e | 659 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
bc7f75fa AK |
660 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
661 | if (ret_val) | |
662 | return ret_val; | |
663 | ||
a4f58f54 BA |
664 | /* For BM PHY this bit is downshift enable */ |
665 | if (phy->type != e1000_phy_bm) | |
2d9498f3 | 666 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
bc7f75fa | 667 | |
ad68076e BA |
668 | /* |
669 | * Options: | |
bc7f75fa AK |
670 | * MDI/MDI-X = 0 (default) |
671 | * 0 - Auto for all speeds | |
672 | * 1 - MDI mode | |
673 | * 2 - MDI-X mode | |
674 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
675 | */ | |
676 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
677 | ||
678 | switch (phy->mdix) { | |
679 | case 1: | |
680 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
681 | break; | |
682 | case 2: | |
683 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
684 | break; | |
685 | case 3: | |
686 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
687 | break; | |
688 | case 0: | |
689 | default: | |
690 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
691 | break; | |
692 | } | |
693 | ||
ad68076e BA |
694 | /* |
695 | * Options: | |
bc7f75fa AK |
696 | * disable_polarity_correction = 0 (default) |
697 | * Automatic Correction for Reversed Cable Polarity | |
698 | * 0 - Disabled | |
699 | * 1 - Enabled | |
700 | */ | |
701 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
702 | if (phy->disable_polarity_correction == 1) | |
703 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; | |
704 | ||
97ac8cae BA |
705 | /* Enable downshift on BM (disabled by default) */ |
706 | if (phy->type == e1000_phy_bm) | |
707 | phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; | |
708 | ||
bc7f75fa AK |
709 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
710 | if (ret_val) | |
711 | return ret_val; | |
712 | ||
4662e82b BA |
713 | if ((phy->type == e1000_phy_m88) && |
714 | (phy->revision < E1000_REVISION_4) && | |
715 | (phy->id != BME1000_E_PHY_ID_R2)) { | |
ad68076e BA |
716 | /* |
717 | * Force TX_CLK in the Extended PHY Specific Control Register | |
bc7f75fa AK |
718 | * to 25MHz clock. |
719 | */ | |
720 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
721 | if (ret_val) | |
722 | return ret_val; | |
723 | ||
724 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
725 | ||
726 | if ((phy->revision == 2) && | |
727 | (phy->id == M88E1111_I_PHY_ID)) { | |
728 | /* 82573L PHY - set the downshift counter to 5x. */ | |
729 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
730 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
731 | } else { | |
732 | /* Configure Master and Slave downshift values */ | |
733 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
734 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
735 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
736 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
737 | } | |
738 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
739 | if (ret_val) | |
740 | return ret_val; | |
741 | } | |
742 | ||
4662e82b BA |
743 | if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
744 | /* Set PHY page 0, register 29 to 0x0003 */ | |
745 | ret_val = e1e_wphy(hw, 29, 0x0003); | |
746 | if (ret_val) | |
747 | return ret_val; | |
748 | ||
749 | /* Set PHY page 0, register 30 to 0x0000 */ | |
750 | ret_val = e1e_wphy(hw, 30, 0x0000); | |
751 | if (ret_val) | |
752 | return ret_val; | |
753 | } | |
754 | ||
bc7f75fa AK |
755 | /* Commit the changes. */ |
756 | ret_val = e1000e_commit_phy(hw); | |
a4f58f54 | 757 | if (ret_val) { |
3bb99fe2 | 758 | e_dbg("Error committing the PHY changes\n"); |
a4f58f54 BA |
759 | return ret_val; |
760 | } | |
bc7f75fa | 761 | |
a4f58f54 | 762 | if (phy->type == e1000_phy_82578) { |
94d8186a | 763 | ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
a4f58f54 BA |
764 | &phy_data); |
765 | if (ret_val) | |
766 | return ret_val; | |
767 | ||
768 | /* 82578 PHY - set the downshift count to 1x. */ | |
769 | phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; | |
770 | phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
94d8186a | 771 | ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, |
a4f58f54 BA |
772 | phy_data); |
773 | if (ret_val) | |
774 | return ret_val; | |
775 | } | |
776 | ||
777 | return 0; | |
bc7f75fa AK |
778 | } |
779 | ||
780 | /** | |
781 | * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link | |
782 | * @hw: pointer to the HW structure | |
783 | * | |
784 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
785 | * igp PHY's. | |
786 | **/ | |
787 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) | |
788 | { | |
789 | struct e1000_phy_info *phy = &hw->phy; | |
790 | s32 ret_val; | |
791 | u16 data; | |
792 | ||
793 | ret_val = e1000_phy_hw_reset(hw); | |
794 | if (ret_val) { | |
3bb99fe2 | 795 | e_dbg("Error resetting the PHY.\n"); |
bc7f75fa AK |
796 | return ret_val; |
797 | } | |
798 | ||
2d9498f3 DG |
799 | /* |
800 | * Wait 100ms for MAC to configure PHY from NVM settings, to avoid | |
801 | * timeout issues when LFS is enabled. | |
802 | */ | |
803 | msleep(100); | |
bc7f75fa AK |
804 | |
805 | /* disable lplu d0 during driver init */ | |
564ea9bb | 806 | ret_val = e1000_set_d0_lplu_state(hw, false); |
bc7f75fa | 807 | if (ret_val) { |
3bb99fe2 | 808 | e_dbg("Error Disabling LPLU D0\n"); |
bc7f75fa AK |
809 | return ret_val; |
810 | } | |
811 | /* Configure mdi-mdix settings */ | |
812 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); | |
813 | if (ret_val) | |
814 | return ret_val; | |
815 | ||
816 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
817 | ||
818 | switch (phy->mdix) { | |
819 | case 1: | |
820 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
821 | break; | |
822 | case 2: | |
823 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
824 | break; | |
825 | case 0: | |
826 | default: | |
827 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
828 | break; | |
829 | } | |
830 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); | |
831 | if (ret_val) | |
832 | return ret_val; | |
833 | ||
834 | /* set auto-master slave resolution settings */ | |
835 | if (hw->mac.autoneg) { | |
ad68076e BA |
836 | /* |
837 | * when autonegotiation advertisement is only 1000Mbps then we | |
bc7f75fa | 838 | * should disable SmartSpeed and enable Auto MasterSlave |
ad68076e BA |
839 | * resolution as hardware default. |
840 | */ | |
bc7f75fa AK |
841 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
842 | /* Disable SmartSpeed */ | |
843 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 844 | &data); |
bc7f75fa AK |
845 | if (ret_val) |
846 | return ret_val; | |
847 | ||
848 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
849 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 850 | data); |
bc7f75fa AK |
851 | if (ret_val) |
852 | return ret_val; | |
853 | ||
854 | /* Set auto Master/Slave resolution process */ | |
855 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); | |
856 | if (ret_val) | |
857 | return ret_val; | |
858 | ||
859 | data &= ~CR_1000T_MS_ENABLE; | |
860 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); | |
861 | if (ret_val) | |
862 | return ret_val; | |
863 | } | |
864 | ||
865 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data); | |
866 | if (ret_val) | |
867 | return ret_val; | |
868 | ||
869 | /* load defaults for future use */ | |
870 | phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? | |
871 | ((data & CR_1000T_MS_VALUE) ? | |
872 | e1000_ms_force_master : | |
873 | e1000_ms_force_slave) : | |
874 | e1000_ms_auto; | |
875 | ||
876 | switch (phy->ms_type) { | |
877 | case e1000_ms_force_master: | |
878 | data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); | |
879 | break; | |
880 | case e1000_ms_force_slave: | |
881 | data |= CR_1000T_MS_ENABLE; | |
882 | data &= ~(CR_1000T_MS_VALUE); | |
883 | break; | |
884 | case e1000_ms_auto: | |
885 | data &= ~CR_1000T_MS_ENABLE; | |
886 | default: | |
887 | break; | |
888 | } | |
889 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data); | |
890 | } | |
891 | ||
892 | return ret_val; | |
893 | } | |
894 | ||
895 | /** | |
896 | * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation | |
897 | * @hw: pointer to the HW structure | |
898 | * | |
899 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
900 | * register and if the PHY is already setup for auto-negotiation, then | |
901 | * return successful. Otherwise, setup advertisement and flow control to | |
902 | * the appropriate values for the wanted auto-negotiation. | |
903 | **/ | |
904 | static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) | |
905 | { | |
906 | struct e1000_phy_info *phy = &hw->phy; | |
907 | s32 ret_val; | |
908 | u16 mii_autoneg_adv_reg; | |
909 | u16 mii_1000t_ctrl_reg = 0; | |
910 | ||
911 | phy->autoneg_advertised &= phy->autoneg_mask; | |
912 | ||
913 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
914 | ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); | |
915 | if (ret_val) | |
916 | return ret_val; | |
917 | ||
918 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
919 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
920 | ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); | |
921 | if (ret_val) | |
922 | return ret_val; | |
923 | } | |
924 | ||
ad68076e BA |
925 | /* |
926 | * Need to parse both autoneg_advertised and fc and set up | |
bc7f75fa AK |
927 | * the appropriate PHY registers. First we will parse for |
928 | * autoneg_advertised software override. Since we can advertise | |
929 | * a plethora of combinations, we need to check each bit | |
930 | * individually. | |
931 | */ | |
932 | ||
ad68076e BA |
933 | /* |
934 | * First we clear all the 10/100 mb speed bits in the Auto-Neg | |
bc7f75fa AK |
935 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
936 | * the 1000Base-T Control Register (Address 9). | |
937 | */ | |
938 | mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | | |
939 | NWAY_AR_100TX_HD_CAPS | | |
940 | NWAY_AR_10T_FD_CAPS | | |
941 | NWAY_AR_10T_HD_CAPS); | |
942 | mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); | |
943 | ||
3bb99fe2 | 944 | e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
bc7f75fa AK |
945 | |
946 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
947 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
3bb99fe2 | 948 | e_dbg("Advertise 10mb Half duplex\n"); |
bc7f75fa AK |
949 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
950 | } | |
951 | ||
952 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
953 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
3bb99fe2 | 954 | e_dbg("Advertise 10mb Full duplex\n"); |
bc7f75fa AK |
955 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
956 | } | |
957 | ||
958 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
959 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
3bb99fe2 | 960 | e_dbg("Advertise 100mb Half duplex\n"); |
bc7f75fa AK |
961 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
962 | } | |
963 | ||
964 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
965 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
3bb99fe2 | 966 | e_dbg("Advertise 100mb Full duplex\n"); |
bc7f75fa AK |
967 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
968 | } | |
969 | ||
970 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
971 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
3bb99fe2 | 972 | e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
bc7f75fa AK |
973 | |
974 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
975 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
3bb99fe2 | 976 | e_dbg("Advertise 1000mb Full duplex\n"); |
bc7f75fa AK |
977 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
978 | } | |
979 | ||
ad68076e BA |
980 | /* |
981 | * Check for a software override of the flow control settings, and | |
bc7f75fa AK |
982 | * setup the PHY advertisement registers accordingly. If |
983 | * auto-negotiation is enabled, then software will have to set the | |
984 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
985 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- | |
986 | * negotiation. | |
987 | * | |
988 | * The possible values of the "fc" parameter are: | |
989 | * 0: Flow control is completely disabled | |
990 | * 1: Rx flow control is enabled (we can receive pause frames | |
991 | * but not send pause frames). | |
992 | * 2: Tx flow control is enabled (we can send pause frames | |
993 | * but we do not support receiving pause frames). | |
ad68076e | 994 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
bc7f75fa AK |
995 | * other: No software override. The flow control configuration |
996 | * in the EEPROM is used. | |
997 | */ | |
5c48ef3e | 998 | switch (hw->fc.current_mode) { |
bc7f75fa | 999 | case e1000_fc_none: |
ad68076e BA |
1000 | /* |
1001 | * Flow control (Rx & Tx) is completely disabled by a | |
bc7f75fa AK |
1002 | * software over-ride. |
1003 | */ | |
1004 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1005 | break; | |
1006 | case e1000_fc_rx_pause: | |
ad68076e BA |
1007 | /* |
1008 | * Rx Flow control is enabled, and Tx Flow control is | |
bc7f75fa | 1009 | * disabled, by a software over-ride. |
ad68076e BA |
1010 | * |
1011 | * Since there really isn't a way to advertise that we are | |
1012 | * capable of Rx Pause ONLY, we will advertise that we | |
1013 | * support both symmetric and asymmetric Rx PAUSE. Later | |
bc7f75fa AK |
1014 | * (in e1000e_config_fc_after_link_up) we will disable the |
1015 | * hw's ability to send PAUSE frames. | |
1016 | */ | |
1017 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1018 | break; | |
1019 | case e1000_fc_tx_pause: | |
ad68076e BA |
1020 | /* |
1021 | * Tx Flow control is enabled, and Rx Flow control is | |
bc7f75fa AK |
1022 | * disabled, by a software over-ride. |
1023 | */ | |
1024 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; | |
1025 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; | |
1026 | break; | |
1027 | case e1000_fc_full: | |
ad68076e BA |
1028 | /* |
1029 | * Flow control (both Rx and Tx) is enabled by a software | |
bc7f75fa AK |
1030 | * over-ride. |
1031 | */ | |
1032 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); | |
1033 | break; | |
1034 | default: | |
3bb99fe2 | 1035 | e_dbg("Flow control param set incorrectly\n"); |
bc7f75fa AK |
1036 | ret_val = -E1000_ERR_CONFIG; |
1037 | return ret_val; | |
1038 | } | |
1039 | ||
1040 | ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); | |
1041 | if (ret_val) | |
1042 | return ret_val; | |
1043 | ||
3bb99fe2 | 1044 | e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
bc7f75fa AK |
1045 | |
1046 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
1047 | ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); | |
1048 | } | |
1049 | ||
1050 | return ret_val; | |
1051 | } | |
1052 | ||
1053 | /** | |
1054 | * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link | |
1055 | * @hw: pointer to the HW structure | |
1056 | * | |
1057 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
1058 | * configure to advertise the full capability. Setup the PHY to autoneg | |
1059 | * and restart the negotiation process between the link partner. If | |
ad68076e | 1060 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
bc7f75fa AK |
1061 | **/ |
1062 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) | |
1063 | { | |
1064 | struct e1000_phy_info *phy = &hw->phy; | |
1065 | s32 ret_val; | |
1066 | u16 phy_ctrl; | |
1067 | ||
ad68076e BA |
1068 | /* |
1069 | * Perform some bounds checking on the autoneg advertisement | |
bc7f75fa AK |
1070 | * parameter. |
1071 | */ | |
1072 | phy->autoneg_advertised &= phy->autoneg_mask; | |
1073 | ||
ad68076e BA |
1074 | /* |
1075 | * If autoneg_advertised is zero, we assume it was not defaulted | |
bc7f75fa AK |
1076 | * by the calling code so we set to advertise full capability. |
1077 | */ | |
1078 | if (phy->autoneg_advertised == 0) | |
1079 | phy->autoneg_advertised = phy->autoneg_mask; | |
1080 | ||
3bb99fe2 | 1081 | e_dbg("Reconfiguring auto-neg advertisement params\n"); |
bc7f75fa AK |
1082 | ret_val = e1000_phy_setup_autoneg(hw); |
1083 | if (ret_val) { | |
3bb99fe2 | 1084 | e_dbg("Error Setting up Auto-Negotiation\n"); |
bc7f75fa AK |
1085 | return ret_val; |
1086 | } | |
3bb99fe2 | 1087 | e_dbg("Restarting Auto-Neg\n"); |
bc7f75fa | 1088 | |
ad68076e BA |
1089 | /* |
1090 | * Restart auto-negotiation by setting the Auto Neg Enable bit and | |
bc7f75fa AK |
1091 | * the Auto Neg Restart bit in the PHY control register. |
1092 | */ | |
1093 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); | |
1094 | if (ret_val) | |
1095 | return ret_val; | |
1096 | ||
1097 | phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); | |
1098 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); | |
1099 | if (ret_val) | |
1100 | return ret_val; | |
1101 | ||
ad68076e BA |
1102 | /* |
1103 | * Does the user want to wait for Auto-Neg to complete here, or | |
bc7f75fa AK |
1104 | * check at a later time (for example, callback routine). |
1105 | */ | |
318a94d6 | 1106 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
1107 | ret_val = e1000_wait_autoneg(hw); |
1108 | if (ret_val) { | |
3bb99fe2 | 1109 | e_dbg("Error while waiting for " |
bc7f75fa AK |
1110 | "autoneg to complete\n"); |
1111 | return ret_val; | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | hw->mac.get_link_status = 1; | |
1116 | ||
1117 | return ret_val; | |
1118 | } | |
1119 | ||
1120 | /** | |
1121 | * e1000e_setup_copper_link - Configure copper link settings | |
1122 | * @hw: pointer to the HW structure | |
1123 | * | |
1124 | * Calls the appropriate function to configure the link for auto-neg or forced | |
1125 | * speed and duplex. Then we check for link, once link is established calls | |
1126 | * to configure collision distance and flow control are called. If link is | |
1127 | * not established, we return -E1000_ERR_PHY (-2). | |
1128 | **/ | |
1129 | s32 e1000e_setup_copper_link(struct e1000_hw *hw) | |
1130 | { | |
1131 | s32 ret_val; | |
1132 | bool link; | |
1133 | ||
1134 | if (hw->mac.autoneg) { | |
ad68076e BA |
1135 | /* |
1136 | * Setup autoneg and flow control advertisement and perform | |
1137 | * autonegotiation. | |
1138 | */ | |
bc7f75fa AK |
1139 | ret_val = e1000_copper_link_autoneg(hw); |
1140 | if (ret_val) | |
1141 | return ret_val; | |
1142 | } else { | |
ad68076e BA |
1143 | /* |
1144 | * PHY will be set to 10H, 10F, 100H or 100F | |
1145 | * depending on user settings. | |
1146 | */ | |
3bb99fe2 | 1147 | e_dbg("Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1148 | ret_val = e1000_phy_force_speed_duplex(hw); |
1149 | if (ret_val) { | |
3bb99fe2 | 1150 | e_dbg("Error Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1151 | return ret_val; |
1152 | } | |
1153 | } | |
1154 | ||
ad68076e BA |
1155 | /* |
1156 | * Check link status. Wait up to 100 microseconds for link to become | |
bc7f75fa AK |
1157 | * valid. |
1158 | */ | |
1159 | ret_val = e1000e_phy_has_link_generic(hw, | |
1160 | COPPER_LINK_UP_LIMIT, | |
1161 | 10, | |
1162 | &link); | |
1163 | if (ret_val) | |
1164 | return ret_val; | |
1165 | ||
1166 | if (link) { | |
3bb99fe2 | 1167 | e_dbg("Valid link established!!!\n"); |
bc7f75fa AK |
1168 | e1000e_config_collision_dist(hw); |
1169 | ret_val = e1000e_config_fc_after_link_up(hw); | |
1170 | } else { | |
3bb99fe2 | 1171 | e_dbg("Unable to establish link!!!\n"); |
bc7f75fa AK |
1172 | } |
1173 | ||
1174 | return ret_val; | |
1175 | } | |
1176 | ||
1177 | /** | |
1178 | * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY | |
1179 | * @hw: pointer to the HW structure | |
1180 | * | |
1181 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1182 | * auto-crossover to force MDI manually. Waits for link and returns | |
1183 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
1184 | **/ | |
1185 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
1186 | { | |
1187 | struct e1000_phy_info *phy = &hw->phy; | |
1188 | s32 ret_val; | |
1189 | u16 phy_data; | |
1190 | bool link; | |
1191 | ||
1192 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
1193 | if (ret_val) | |
1194 | return ret_val; | |
1195 | ||
1196 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1197 | ||
1198 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); | |
1199 | if (ret_val) | |
1200 | return ret_val; | |
1201 | ||
ad68076e BA |
1202 | /* |
1203 | * Clear Auto-Crossover to force MDI manually. IGP requires MDI | |
bc7f75fa AK |
1204 | * forced whenever speed and duplex are forced. |
1205 | */ | |
1206 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1207 | if (ret_val) | |
1208 | return ret_val; | |
1209 | ||
1210 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1211 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1212 | ||
1213 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
1214 | if (ret_val) | |
1215 | return ret_val; | |
1216 | ||
3bb99fe2 | 1217 | e_dbg("IGP PSCR: %X\n", phy_data); |
bc7f75fa AK |
1218 | |
1219 | udelay(1); | |
1220 | ||
318a94d6 | 1221 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1222 | e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
bc7f75fa AK |
1223 | |
1224 | ret_val = e1000e_phy_has_link_generic(hw, | |
1225 | PHY_FORCE_LIMIT, | |
1226 | 100000, | |
1227 | &link); | |
1228 | if (ret_val) | |
1229 | return ret_val; | |
1230 | ||
1231 | if (!link) | |
3bb99fe2 | 1232 | e_dbg("Link taking longer than expected.\n"); |
bc7f75fa AK |
1233 | |
1234 | /* Try once more */ | |
1235 | ret_val = e1000e_phy_has_link_generic(hw, | |
1236 | PHY_FORCE_LIMIT, | |
1237 | 100000, | |
1238 | &link); | |
1239 | if (ret_val) | |
1240 | return ret_val; | |
1241 | } | |
1242 | ||
1243 | return ret_val; | |
1244 | } | |
1245 | ||
1246 | /** | |
1247 | * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY | |
1248 | * @hw: pointer to the HW structure | |
1249 | * | |
1250 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1251 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
1252 | * changes. If time expires while waiting for link up, we reset the DSP. | |
ad68076e | 1253 | * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
bc7f75fa AK |
1254 | * successful completion, else return corresponding error code. |
1255 | **/ | |
1256 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
1257 | { | |
1258 | struct e1000_phy_info *phy = &hw->phy; | |
1259 | s32 ret_val; | |
1260 | u16 phy_data; | |
1261 | bool link; | |
1262 | ||
ad68076e BA |
1263 | /* |
1264 | * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI | |
bc7f75fa AK |
1265 | * forced whenever speed and duplex are forced. |
1266 | */ | |
1267 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1268 | if (ret_val) | |
1269 | return ret_val; | |
1270 | ||
1271 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1272 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1273 | if (ret_val) | |
1274 | return ret_val; | |
1275 | ||
3bb99fe2 | 1276 | e_dbg("M88E1000 PSCR: %X\n", phy_data); |
bc7f75fa AK |
1277 | |
1278 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data); | |
1279 | if (ret_val) | |
1280 | return ret_val; | |
1281 | ||
1282 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1283 | ||
bc7f75fa AK |
1284 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data); |
1285 | if (ret_val) | |
1286 | return ret_val; | |
1287 | ||
5aa49c82 BA |
1288 | /* Reset the phy to commit changes. */ |
1289 | ret_val = e1000e_commit_phy(hw); | |
1290 | if (ret_val) | |
1291 | return ret_val; | |
bc7f75fa | 1292 | |
318a94d6 | 1293 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1294 | e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
bc7f75fa AK |
1295 | |
1296 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1297 | 100000, &link); | |
1298 | if (ret_val) | |
1299 | return ret_val; | |
1300 | ||
1301 | if (!link) { | |
0be84010 BA |
1302 | if (hw->phy.type != e1000_phy_m88) { |
1303 | e_dbg("Link taking longer than expected.\n"); | |
1304 | } else { | |
1305 | /* | |
1306 | * We didn't get link. | |
1307 | * Reset the DSP and cross our fingers. | |
1308 | */ | |
1309 | ret_val = e1e_wphy(hw, | |
1310 | M88E1000_PHY_PAGE_SELECT, | |
1311 | 0x001d); | |
1312 | if (ret_val) | |
1313 | return ret_val; | |
1314 | ret_val = e1000e_phy_reset_dsp(hw); | |
1315 | if (ret_val) | |
1316 | return ret_val; | |
1317 | } | |
bc7f75fa AK |
1318 | } |
1319 | ||
1320 | /* Try once more */ | |
1321 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1322 | 100000, &link); | |
1323 | if (ret_val) | |
1324 | return ret_val; | |
1325 | } | |
1326 | ||
0be84010 BA |
1327 | if (hw->phy.type != e1000_phy_m88) |
1328 | return 0; | |
1329 | ||
bc7f75fa AK |
1330 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
1331 | if (ret_val) | |
1332 | return ret_val; | |
1333 | ||
ad68076e BA |
1334 | /* |
1335 | * Resetting the phy means we need to re-force TX_CLK in the | |
bc7f75fa AK |
1336 | * Extended PHY Specific Control Register to 25MHz clock from |
1337 | * the reset value of 2.5MHz. | |
1338 | */ | |
1339 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1340 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1341 | if (ret_val) | |
1342 | return ret_val; | |
1343 | ||
ad68076e BA |
1344 | /* |
1345 | * In addition, we must re-enable CRS on Tx for both half and full | |
bc7f75fa AK |
1346 | * duplex. |
1347 | */ | |
1348 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1349 | if (ret_val) | |
1350 | return ret_val; | |
1351 | ||
1352 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
1353 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1354 | ||
1355 | return ret_val; | |
1356 | } | |
1357 | ||
0be84010 BA |
1358 | /** |
1359 | * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex | |
1360 | * @hw: pointer to the HW structure | |
1361 | * | |
1362 | * Forces the speed and duplex settings of the PHY. | |
1363 | * This is a function pointer entry point only called by | |
1364 | * PHY setup routines. | |
1365 | **/ | |
1366 | s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) | |
1367 | { | |
1368 | struct e1000_phy_info *phy = &hw->phy; | |
1369 | s32 ret_val; | |
1370 | u16 data; | |
1371 | bool link; | |
1372 | ||
1373 | ret_val = e1e_rphy(hw, PHY_CONTROL, &data); | |
1374 | if (ret_val) | |
1375 | goto out; | |
1376 | ||
1377 | e1000e_phy_force_speed_duplex_setup(hw, &data); | |
1378 | ||
1379 | ret_val = e1e_wphy(hw, PHY_CONTROL, data); | |
1380 | if (ret_val) | |
1381 | goto out; | |
1382 | ||
1383 | /* Disable MDI-X support for 10/100 */ | |
1384 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
1385 | if (ret_val) | |
1386 | goto out; | |
1387 | ||
1388 | data &= ~IFE_PMC_AUTO_MDIX; | |
1389 | data &= ~IFE_PMC_FORCE_MDIX; | |
1390 | ||
1391 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); | |
1392 | if (ret_val) | |
1393 | goto out; | |
1394 | ||
1395 | e_dbg("IFE PMC: %X\n", data); | |
1396 | ||
1397 | udelay(1); | |
1398 | ||
1399 | if (phy->autoneg_wait_to_complete) { | |
1400 | e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); | |
1401 | ||
1402 | ret_val = e1000e_phy_has_link_generic(hw, | |
1403 | PHY_FORCE_LIMIT, | |
1404 | 100000, | |
1405 | &link); | |
1406 | if (ret_val) | |
1407 | goto out; | |
1408 | ||
1409 | if (!link) | |
1410 | e_dbg("Link taking longer than expected.\n"); | |
1411 | ||
1412 | /* Try once more */ | |
1413 | ret_val = e1000e_phy_has_link_generic(hw, | |
1414 | PHY_FORCE_LIMIT, | |
1415 | 100000, | |
1416 | &link); | |
1417 | if (ret_val) | |
1418 | goto out; | |
1419 | } | |
1420 | ||
1421 | out: | |
1422 | return ret_val; | |
1423 | } | |
1424 | ||
bc7f75fa AK |
1425 | /** |
1426 | * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex | |
1427 | * @hw: pointer to the HW structure | |
1428 | * @phy_ctrl: pointer to current value of PHY_CONTROL | |
1429 | * | |
1430 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
1431 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
1432 | * disable auto-negotiation, configure duplex, configure speed, configure | |
1433 | * the collision distance, write configuration to CTRL register. The | |
1434 | * caller must write to the PHY_CONTROL register for these settings to | |
1435 | * take affect. | |
1436 | **/ | |
1437 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) | |
1438 | { | |
1439 | struct e1000_mac_info *mac = &hw->mac; | |
1440 | u32 ctrl; | |
1441 | ||
1442 | /* Turn off flow control when forcing speed/duplex */ | |
5c48ef3e | 1443 | hw->fc.current_mode = e1000_fc_none; |
bc7f75fa AK |
1444 | |
1445 | /* Force speed/duplex on the mac */ | |
1446 | ctrl = er32(CTRL); | |
1447 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1448 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1449 | ||
1450 | /* Disable Auto Speed Detection */ | |
1451 | ctrl &= ~E1000_CTRL_ASDE; | |
1452 | ||
1453 | /* Disable autoneg on the phy */ | |
1454 | *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; | |
1455 | ||
1456 | /* Forcing Full or Half Duplex? */ | |
1457 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1458 | ctrl &= ~E1000_CTRL_FD; | |
1459 | *phy_ctrl &= ~MII_CR_FULL_DUPLEX; | |
3bb99fe2 | 1460 | e_dbg("Half Duplex\n"); |
bc7f75fa AK |
1461 | } else { |
1462 | ctrl |= E1000_CTRL_FD; | |
1463 | *phy_ctrl |= MII_CR_FULL_DUPLEX; | |
3bb99fe2 | 1464 | e_dbg("Full Duplex\n"); |
bc7f75fa AK |
1465 | } |
1466 | ||
1467 | /* Forcing 10mb or 100mb? */ | |
1468 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1469 | ctrl |= E1000_CTRL_SPD_100; | |
1470 | *phy_ctrl |= MII_CR_SPEED_100; | |
1471 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); | |
3bb99fe2 | 1472 | e_dbg("Forcing 100mb\n"); |
bc7f75fa AK |
1473 | } else { |
1474 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1475 | *phy_ctrl |= MII_CR_SPEED_10; | |
1476 | *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); | |
3bb99fe2 | 1477 | e_dbg("Forcing 10mb\n"); |
bc7f75fa AK |
1478 | } |
1479 | ||
1480 | e1000e_config_collision_dist(hw); | |
1481 | ||
1482 | ew32(CTRL, ctrl); | |
1483 | } | |
1484 | ||
1485 | /** | |
1486 | * e1000e_set_d3_lplu_state - Sets low power link up state for D3 | |
1487 | * @hw: pointer to the HW structure | |
1488 | * @active: boolean used to enable/disable lplu | |
1489 | * | |
1490 | * Success returns 0, Failure returns 1 | |
1491 | * | |
1492 | * The low power link up (lplu) state is set to the power management level D3 | |
1493 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1494 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1495 | * is used during Dx states where the power conservation is most important. | |
1496 | * During driver activity, SmartSpeed should be enabled so performance is | |
1497 | * maintained. | |
1498 | **/ | |
1499 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1500 | { | |
1501 | struct e1000_phy_info *phy = &hw->phy; | |
1502 | s32 ret_val; | |
1503 | u16 data; | |
1504 | ||
1505 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
1506 | if (ret_val) | |
1507 | return ret_val; | |
1508 | ||
1509 | if (!active) { | |
1510 | data &= ~IGP02E1000_PM_D3_LPLU; | |
2d9498f3 | 1511 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
bc7f75fa AK |
1512 | if (ret_val) |
1513 | return ret_val; | |
ad68076e BA |
1514 | /* |
1515 | * LPLU and SmartSpeed are mutually exclusive. LPLU is used | |
bc7f75fa AK |
1516 | * during Dx states where the power conservation is most |
1517 | * important. During driver activity we should enable | |
ad68076e BA |
1518 | * SmartSpeed, so performance is maintained. |
1519 | */ | |
bc7f75fa AK |
1520 | if (phy->smart_speed == e1000_smart_speed_on) { |
1521 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1522 | &data); |
bc7f75fa AK |
1523 | if (ret_val) |
1524 | return ret_val; | |
1525 | ||
1526 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
1527 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1528 | data); |
bc7f75fa AK |
1529 | if (ret_val) |
1530 | return ret_val; | |
1531 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
1532 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1533 | &data); |
bc7f75fa AK |
1534 | if (ret_val) |
1535 | return ret_val; | |
1536 | ||
1537 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1538 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1539 | data); |
bc7f75fa AK |
1540 | if (ret_val) |
1541 | return ret_val; | |
1542 | } | |
1543 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1544 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1545 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1546 | data |= IGP02E1000_PM_D3_LPLU; | |
1547 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
1548 | if (ret_val) | |
1549 | return ret_val; | |
1550 | ||
1551 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
1552 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
1553 | if (ret_val) | |
1554 | return ret_val; | |
1555 | ||
1556 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1557 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
1558 | } | |
1559 | ||
1560 | return ret_val; | |
1561 | } | |
1562 | ||
1563 | /** | |
489815ce | 1564 | * e1000e_check_downshift - Checks whether a downshift in speed occurred |
bc7f75fa AK |
1565 | * @hw: pointer to the HW structure |
1566 | * | |
1567 | * Success returns 0, Failure returns 1 | |
1568 | * | |
1569 | * A downshift is detected by querying the PHY link health. | |
1570 | **/ | |
1571 | s32 e1000e_check_downshift(struct e1000_hw *hw) | |
1572 | { | |
1573 | struct e1000_phy_info *phy = &hw->phy; | |
1574 | s32 ret_val; | |
1575 | u16 phy_data, offset, mask; | |
1576 | ||
1577 | switch (phy->type) { | |
1578 | case e1000_phy_m88: | |
1579 | case e1000_phy_gg82563: | |
07f025e6 | 1580 | case e1000_phy_bm: |
a4f58f54 | 1581 | case e1000_phy_82578: |
bc7f75fa AK |
1582 | offset = M88E1000_PHY_SPEC_STATUS; |
1583 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1584 | break; | |
1585 | case e1000_phy_igp_2: | |
1586 | case e1000_phy_igp_3: | |
1587 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1588 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1589 | break; | |
1590 | default: | |
1591 | /* speed downshift not supported */ | |
564ea9bb | 1592 | phy->speed_downgraded = false; |
bc7f75fa AK |
1593 | return 0; |
1594 | } | |
1595 | ||
1596 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1597 | ||
1598 | if (!ret_val) | |
1599 | phy->speed_downgraded = (phy_data & mask); | |
1600 | ||
1601 | return ret_val; | |
1602 | } | |
1603 | ||
1604 | /** | |
1605 | * e1000_check_polarity_m88 - Checks the polarity. | |
1606 | * @hw: pointer to the HW structure | |
1607 | * | |
1608 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1609 | * | |
1610 | * Polarity is determined based on the PHY specific status register. | |
1611 | **/ | |
0be84010 | 1612 | s32 e1000_check_polarity_m88(struct e1000_hw *hw) |
bc7f75fa AK |
1613 | { |
1614 | struct e1000_phy_info *phy = &hw->phy; | |
1615 | s32 ret_val; | |
1616 | u16 data; | |
1617 | ||
1618 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); | |
1619 | ||
1620 | if (!ret_val) | |
1621 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1622 | ? e1000_rev_polarity_reversed | |
1623 | : e1000_rev_polarity_normal; | |
1624 | ||
1625 | return ret_val; | |
1626 | } | |
1627 | ||
1628 | /** | |
1629 | * e1000_check_polarity_igp - Checks the polarity. | |
1630 | * @hw: pointer to the HW structure | |
1631 | * | |
1632 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1633 | * | |
1634 | * Polarity is determined based on the PHY port status register, and the | |
1635 | * current speed (since there is no polarity at 100Mbps). | |
1636 | **/ | |
0be84010 | 1637 | s32 e1000_check_polarity_igp(struct e1000_hw *hw) |
bc7f75fa AK |
1638 | { |
1639 | struct e1000_phy_info *phy = &hw->phy; | |
1640 | s32 ret_val; | |
1641 | u16 data, offset, mask; | |
1642 | ||
ad68076e BA |
1643 | /* |
1644 | * Polarity is determined based on the speed of | |
1645 | * our connection. | |
1646 | */ | |
bc7f75fa AK |
1647 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
1648 | if (ret_val) | |
1649 | return ret_val; | |
1650 | ||
1651 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1652 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1653 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1654 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1655 | } else { | |
ad68076e BA |
1656 | /* |
1657 | * This really only applies to 10Mbps since | |
bc7f75fa AK |
1658 | * there is no polarity for 100Mbps (always 0). |
1659 | */ | |
1660 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1661 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1662 | } | |
1663 | ||
1664 | ret_val = e1e_rphy(hw, offset, &data); | |
1665 | ||
1666 | if (!ret_val) | |
1667 | phy->cable_polarity = (data & mask) | |
1668 | ? e1000_rev_polarity_reversed | |
1669 | : e1000_rev_polarity_normal; | |
1670 | ||
1671 | return ret_val; | |
1672 | } | |
1673 | ||
0be84010 BA |
1674 | /** |
1675 | * e1000_check_polarity_ife - Check cable polarity for IFE PHY | |
1676 | * @hw: pointer to the HW structure | |
1677 | * | |
1678 | * Polarity is determined on the polarity reversal feature being enabled. | |
1679 | **/ | |
1680 | s32 e1000_check_polarity_ife(struct e1000_hw *hw) | |
1681 | { | |
1682 | struct e1000_phy_info *phy = &hw->phy; | |
1683 | s32 ret_val; | |
1684 | u16 phy_data, offset, mask; | |
1685 | ||
1686 | /* | |
1687 | * Polarity is determined based on the reversal feature being enabled. | |
1688 | */ | |
1689 | if (phy->polarity_correction) { | |
1690 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; | |
1691 | mask = IFE_PESC_POLARITY_REVERSED; | |
1692 | } else { | |
1693 | offset = IFE_PHY_SPECIAL_CONTROL; | |
1694 | mask = IFE_PSC_FORCE_POLARITY; | |
1695 | } | |
1696 | ||
1697 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1698 | ||
1699 | if (!ret_val) | |
1700 | phy->cable_polarity = (phy_data & mask) | |
1701 | ? e1000_rev_polarity_reversed | |
1702 | : e1000_rev_polarity_normal; | |
1703 | ||
1704 | return ret_val; | |
1705 | } | |
1706 | ||
bc7f75fa | 1707 | /** |
ad68076e | 1708 | * e1000_wait_autoneg - Wait for auto-neg completion |
bc7f75fa AK |
1709 | * @hw: pointer to the HW structure |
1710 | * | |
1711 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1712 | * limit to expire, which ever happens first. | |
1713 | **/ | |
1714 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) | |
1715 | { | |
1716 | s32 ret_val = 0; | |
1717 | u16 i, phy_status; | |
1718 | ||
1719 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1720 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
1721 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1722 | if (ret_val) | |
1723 | break; | |
1724 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1725 | if (ret_val) | |
1726 | break; | |
1727 | if (phy_status & MII_SR_AUTONEG_COMPLETE) | |
1728 | break; | |
1729 | msleep(100); | |
1730 | } | |
1731 | ||
ad68076e BA |
1732 | /* |
1733 | * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation | |
bc7f75fa AK |
1734 | * has completed. |
1735 | */ | |
1736 | return ret_val; | |
1737 | } | |
1738 | ||
1739 | /** | |
1740 | * e1000e_phy_has_link_generic - Polls PHY for link | |
1741 | * @hw: pointer to the HW structure | |
1742 | * @iterations: number of times to poll for link | |
1743 | * @usec_interval: delay between polling attempts | |
1744 | * @success: pointer to whether polling was successful or not | |
1745 | * | |
1746 | * Polls the PHY status register for link, 'iterations' number of times. | |
1747 | **/ | |
1748 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, | |
1749 | u32 usec_interval, bool *success) | |
1750 | { | |
1751 | s32 ret_val = 0; | |
1752 | u16 i, phy_status; | |
1753 | ||
1754 | for (i = 0; i < iterations; i++) { | |
ad68076e BA |
1755 | /* |
1756 | * Some PHYs require the PHY_STATUS register to be read | |
bc7f75fa AK |
1757 | * twice due to the link bit being sticky. No harm doing |
1758 | * it across the board. | |
1759 | */ | |
1760 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); | |
1761 | if (ret_val) | |
906e8d97 BA |
1762 | /* |
1763 | * If the first read fails, another entity may have | |
1764 | * ownership of the resources, wait and try again to | |
1765 | * see if they have relinquished the resources yet. | |
1766 | */ | |
1767 | udelay(usec_interval); | |
bc7f75fa AK |
1768 | ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status); |
1769 | if (ret_val) | |
1770 | break; | |
1771 | if (phy_status & MII_SR_LINK_STATUS) | |
1772 | break; | |
1773 | if (usec_interval >= 1000) | |
1774 | mdelay(usec_interval/1000); | |
1775 | else | |
1776 | udelay(usec_interval); | |
1777 | } | |
1778 | ||
1779 | *success = (i < iterations); | |
1780 | ||
1781 | return ret_val; | |
1782 | } | |
1783 | ||
1784 | /** | |
1785 | * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY | |
1786 | * @hw: pointer to the HW structure | |
1787 | * | |
1788 | * Reads the PHY specific status register to retrieve the cable length | |
1789 | * information. The cable length is determined by averaging the minimum and | |
1790 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1791 | * possible cable length values, which are: | |
1792 | * Register Value Cable Length | |
1793 | * 0 < 50 meters | |
1794 | * 1 50 - 80 meters | |
1795 | * 2 80 - 110 meters | |
1796 | * 3 110 - 140 meters | |
1797 | * 4 > 140 meters | |
1798 | **/ | |
1799 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) | |
1800 | { | |
1801 | struct e1000_phy_info *phy = &hw->phy; | |
1802 | s32 ret_val; | |
1803 | u16 phy_data, index; | |
1804 | ||
1805 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1806 | if (ret_val) | |
eb656d45 | 1807 | goto out; |
bc7f75fa AK |
1808 | |
1809 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
eb656d45 BA |
1810 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
1811 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { | |
1812 | ret_val = -E1000_ERR_PHY; | |
1813 | goto out; | |
1814 | } | |
1815 | ||
bc7f75fa | 1816 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
eb656d45 | 1817 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
bc7f75fa AK |
1818 | |
1819 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1820 | ||
eb656d45 | 1821 | out: |
bc7f75fa AK |
1822 | return ret_val; |
1823 | } | |
1824 | ||
1825 | /** | |
1826 | * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY | |
1827 | * @hw: pointer to the HW structure | |
1828 | * | |
1829 | * The automatic gain control (agc) normalizes the amplitude of the | |
1830 | * received signal, adjusting for the attenuation produced by the | |
489815ce | 1831 | * cable. By reading the AGC registers, which represent the |
5ff5b664 | 1832 | * combination of coarse and fine gain value, the value can be put |
bc7f75fa AK |
1833 | * into a lookup table to obtain the approximate cable length |
1834 | * for each channel. | |
1835 | **/ | |
1836 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) | |
1837 | { | |
1838 | struct e1000_phy_info *phy = &hw->phy; | |
1839 | s32 ret_val; | |
1840 | u16 phy_data, i, agc_value = 0; | |
1841 | u16 cur_agc_index, max_agc_index = 0; | |
1842 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
1843 | u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = | |
1844 | {IGP02E1000_PHY_AGC_A, | |
1845 | IGP02E1000_PHY_AGC_B, | |
1846 | IGP02E1000_PHY_AGC_C, | |
1847 | IGP02E1000_PHY_AGC_D}; | |
1848 | ||
1849 | /* Read the AGC registers for all channels */ | |
1850 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
1851 | ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); | |
1852 | if (ret_val) | |
1853 | return ret_val; | |
1854 | ||
ad68076e BA |
1855 | /* |
1856 | * Getting bits 15:9, which represent the combination of | |
5ff5b664 | 1857 | * coarse and fine gain values. The result is a number |
bc7f75fa | 1858 | * that can be put into the lookup table to obtain the |
ad68076e BA |
1859 | * approximate cable length. |
1860 | */ | |
bc7f75fa AK |
1861 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
1862 | IGP02E1000_AGC_LENGTH_MASK; | |
1863 | ||
1864 | /* Array index bound check. */ | |
1865 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1866 | (cur_agc_index == 0)) | |
1867 | return -E1000_ERR_PHY; | |
1868 | ||
1869 | /* Remove min & max AGC values from calculation. */ | |
1870 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1871 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1872 | min_agc_index = cur_agc_index; | |
1873 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1874 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1875 | max_agc_index = cur_agc_index; | |
1876 | ||
1877 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1878 | } | |
1879 | ||
1880 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1881 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1882 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1883 | ||
1884 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1885 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1886 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1887 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1888 | ||
1889 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1890 | ||
1891 | return ret_val; | |
1892 | } | |
1893 | ||
1894 | /** | |
1895 | * e1000e_get_phy_info_m88 - Retrieve PHY information | |
1896 | * @hw: pointer to the HW structure | |
1897 | * | |
1898 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1899 | * to verify that link is up. Read the PHY special control register to | |
1900 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1901 | * special status register to determine MDI/MDIx and current speed. If | |
1902 | * speed is 1000, then determine cable length, local and remote receiver. | |
1903 | **/ | |
1904 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) | |
1905 | { | |
1906 | struct e1000_phy_info *phy = &hw->phy; | |
1907 | s32 ret_val; | |
1908 | u16 phy_data; | |
1909 | bool link; | |
1910 | ||
0be84010 | 1911 | if (phy->media_type != e1000_media_type_copper) { |
3bb99fe2 | 1912 | e_dbg("Phy info is only valid for copper media\n"); |
bc7f75fa AK |
1913 | return -E1000_ERR_CONFIG; |
1914 | } | |
1915 | ||
1916 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1917 | if (ret_val) | |
1918 | return ret_val; | |
1919 | ||
1920 | if (!link) { | |
3bb99fe2 | 1921 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1922 | return -E1000_ERR_CONFIG; |
1923 | } | |
1924 | ||
1925 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1926 | if (ret_val) | |
1927 | return ret_val; | |
1928 | ||
1929 | phy->polarity_correction = (phy_data & | |
1930 | M88E1000_PSCR_POLARITY_REVERSAL); | |
1931 | ||
1932 | ret_val = e1000_check_polarity_m88(hw); | |
1933 | if (ret_val) | |
1934 | return ret_val; | |
1935 | ||
1936 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1937 | if (ret_val) | |
1938 | return ret_val; | |
1939 | ||
1940 | phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX); | |
1941 | ||
1942 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
1943 | ret_val = e1000_get_cable_length(hw); | |
1944 | if (ret_val) | |
1945 | return ret_val; | |
1946 | ||
1947 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data); | |
1948 | if (ret_val) | |
1949 | return ret_val; | |
1950 | ||
1951 | phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) | |
1952 | ? e1000_1000t_rx_status_ok | |
1953 | : e1000_1000t_rx_status_not_ok; | |
1954 | ||
1955 | phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) | |
1956 | ? e1000_1000t_rx_status_ok | |
1957 | : e1000_1000t_rx_status_not_ok; | |
1958 | } else { | |
1959 | /* Set values to "undefined" */ | |
1960 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1961 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1962 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1963 | } | |
1964 | ||
1965 | return ret_val; | |
1966 | } | |
1967 | ||
1968 | /** | |
1969 | * e1000e_get_phy_info_igp - Retrieve igp PHY information | |
1970 | * @hw: pointer to the HW structure | |
1971 | * | |
1972 | * Read PHY status to determine if link is up. If link is up, then | |
1973 | * set/determine 10base-T extended distance and polarity correction. Read | |
1974 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1975 | * determine on the cable length, local and remote receiver. | |
1976 | **/ | |
1977 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) | |
1978 | { | |
1979 | struct e1000_phy_info *phy = &hw->phy; | |
1980 | s32 ret_val; | |
1981 | u16 data; | |
1982 | bool link; | |
1983 | ||
1984 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1985 | if (ret_val) | |
1986 | return ret_val; | |
1987 | ||
1988 | if (!link) { | |
3bb99fe2 | 1989 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1990 | return -E1000_ERR_CONFIG; |
1991 | } | |
1992 | ||
564ea9bb | 1993 | phy->polarity_correction = true; |
bc7f75fa AK |
1994 | |
1995 | ret_val = e1000_check_polarity_igp(hw); | |
1996 | if (ret_val) | |
1997 | return ret_val; | |
1998 | ||
1999 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); | |
2000 | if (ret_val) | |
2001 | return ret_val; | |
2002 | ||
2003 | phy->is_mdix = (data & IGP01E1000_PSSR_MDIX); | |
2004 | ||
2005 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
2006 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
2007 | ret_val = e1000_get_cable_length(hw); | |
2008 | if (ret_val) | |
2009 | return ret_val; | |
2010 | ||
2011 | ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data); | |
2012 | if (ret_val) | |
2013 | return ret_val; | |
2014 | ||
2015 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
2016 | ? e1000_1000t_rx_status_ok | |
2017 | : e1000_1000t_rx_status_not_ok; | |
2018 | ||
2019 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
2020 | ? e1000_1000t_rx_status_ok | |
2021 | : e1000_1000t_rx_status_not_ok; | |
2022 | } else { | |
2023 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2024 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2025 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2026 | } | |
2027 | ||
2028 | return ret_val; | |
2029 | } | |
2030 | ||
0be84010 BA |
2031 | /** |
2032 | * e1000_get_phy_info_ife - Retrieves various IFE PHY states | |
2033 | * @hw: pointer to the HW structure | |
2034 | * | |
2035 | * Populates "phy" structure with various feature states. | |
2036 | **/ | |
2037 | s32 e1000_get_phy_info_ife(struct e1000_hw *hw) | |
2038 | { | |
2039 | struct e1000_phy_info *phy = &hw->phy; | |
2040 | s32 ret_val; | |
2041 | u16 data; | |
2042 | bool link; | |
2043 | ||
2044 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
2045 | if (ret_val) | |
2046 | goto out; | |
2047 | ||
2048 | if (!link) { | |
2049 | e_dbg("Phy info is only valid if link is up\n"); | |
2050 | ret_val = -E1000_ERR_CONFIG; | |
2051 | goto out; | |
2052 | } | |
2053 | ||
2054 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); | |
2055 | if (ret_val) | |
2056 | goto out; | |
2057 | phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE) | |
2058 | ? false : true; | |
2059 | ||
2060 | if (phy->polarity_correction) { | |
2061 | ret_val = e1000_check_polarity_ife(hw); | |
2062 | if (ret_val) | |
2063 | goto out; | |
2064 | } else { | |
2065 | /* Polarity is forced */ | |
2066 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) | |
2067 | ? e1000_rev_polarity_reversed | |
2068 | : e1000_rev_polarity_normal; | |
2069 | } | |
2070 | ||
2071 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
2072 | if (ret_val) | |
2073 | goto out; | |
2074 | ||
2075 | phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false; | |
2076 | ||
2077 | /* The following parameters are undefined for 10/100 operation. */ | |
2078 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2079 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2080 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2081 | ||
2082 | out: | |
2083 | return ret_val; | |
2084 | } | |
2085 | ||
bc7f75fa AK |
2086 | /** |
2087 | * e1000e_phy_sw_reset - PHY software reset | |
2088 | * @hw: pointer to the HW structure | |
2089 | * | |
2090 | * Does a software reset of the PHY by reading the PHY control register and | |
2091 | * setting/write the control register reset bit to the PHY. | |
2092 | **/ | |
2093 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw) | |
2094 | { | |
2095 | s32 ret_val; | |
2096 | u16 phy_ctrl; | |
2097 | ||
2098 | ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl); | |
2099 | if (ret_val) | |
2100 | return ret_val; | |
2101 | ||
2102 | phy_ctrl |= MII_CR_RESET; | |
2103 | ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl); | |
2104 | if (ret_val) | |
2105 | return ret_val; | |
2106 | ||
2107 | udelay(1); | |
2108 | ||
2109 | return ret_val; | |
2110 | } | |
2111 | ||
2112 | /** | |
2113 | * e1000e_phy_hw_reset_generic - PHY hardware reset | |
2114 | * @hw: pointer to the HW structure | |
2115 | * | |
2116 | * Verify the reset block is not blocking us from resetting. Acquire | |
2117 | * semaphore (if necessary) and read/set/write the device control reset | |
2118 | * bit in the PHY. Wait the appropriate delay time for the device to | |
489815ce | 2119 | * reset and release the semaphore (if necessary). |
bc7f75fa AK |
2120 | **/ |
2121 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) | |
2122 | { | |
2123 | struct e1000_phy_info *phy = &hw->phy; | |
2124 | s32 ret_val; | |
2125 | u32 ctrl; | |
2126 | ||
2127 | ret_val = e1000_check_reset_block(hw); | |
2128 | if (ret_val) | |
2129 | return 0; | |
2130 | ||
94d8186a | 2131 | ret_val = phy->ops.acquire(hw); |
bc7f75fa AK |
2132 | if (ret_val) |
2133 | return ret_val; | |
2134 | ||
2135 | ctrl = er32(CTRL); | |
2136 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); | |
2137 | e1e_flush(); | |
2138 | ||
2139 | udelay(phy->reset_delay_us); | |
2140 | ||
2141 | ew32(CTRL, ctrl); | |
2142 | e1e_flush(); | |
2143 | ||
2144 | udelay(150); | |
2145 | ||
94d8186a | 2146 | phy->ops.release(hw); |
bc7f75fa AK |
2147 | |
2148 | return e1000_get_phy_cfg_done(hw); | |
2149 | } | |
2150 | ||
2151 | /** | |
2152 | * e1000e_get_cfg_done - Generic configuration done | |
2153 | * @hw: pointer to the HW structure | |
2154 | * | |
2155 | * Generic function to wait 10 milli-seconds for configuration to complete | |
2156 | * and return success. | |
2157 | **/ | |
2158 | s32 e1000e_get_cfg_done(struct e1000_hw *hw) | |
2159 | { | |
2160 | mdelay(10); | |
2161 | return 0; | |
2162 | } | |
2163 | ||
f4187b56 BA |
2164 | /** |
2165 | * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY | |
2166 | * @hw: pointer to the HW structure | |
2167 | * | |
2168 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
2169 | **/ | |
2170 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) | |
2171 | { | |
3bb99fe2 | 2172 | e_dbg("Running IGP 3 PHY init script\n"); |
f4187b56 BA |
2173 | |
2174 | /* PHY init IGP 3 */ | |
2175 | /* Enable rise/fall, 10-mode work in class-A */ | |
2176 | e1e_wphy(hw, 0x2F5B, 0x9018); | |
2177 | /* Remove all caps from Replica path filter */ | |
2178 | e1e_wphy(hw, 0x2F52, 0x0000); | |
2179 | /* Bias trimming for ADC, AFE and Driver (Default) */ | |
2180 | e1e_wphy(hw, 0x2FB1, 0x8B24); | |
2181 | /* Increase Hybrid poly bias */ | |
2182 | e1e_wphy(hw, 0x2FB2, 0xF8F0); | |
2183 | /* Add 4% to Tx amplitude in Gig mode */ | |
2184 | e1e_wphy(hw, 0x2010, 0x10B0); | |
2185 | /* Disable trimming (TTT) */ | |
2186 | e1e_wphy(hw, 0x2011, 0x0000); | |
2187 | /* Poly DC correction to 94.6% + 2% for all channels */ | |
2188 | e1e_wphy(hw, 0x20DD, 0x249A); | |
2189 | /* ABS DC correction to 95.9% */ | |
2190 | e1e_wphy(hw, 0x20DE, 0x00D3); | |
2191 | /* BG temp curve trim */ | |
2192 | e1e_wphy(hw, 0x28B4, 0x04CE); | |
2193 | /* Increasing ADC OPAMP stage 1 currents to max */ | |
2194 | e1e_wphy(hw, 0x2F70, 0x29E4); | |
2195 | /* Force 1000 ( required for enabling PHY regs configuration) */ | |
2196 | e1e_wphy(hw, 0x0000, 0x0140); | |
2197 | /* Set upd_freq to 6 */ | |
2198 | e1e_wphy(hw, 0x1F30, 0x1606); | |
2199 | /* Disable NPDFE */ | |
2200 | e1e_wphy(hw, 0x1F31, 0xB814); | |
2201 | /* Disable adaptive fixed FFE (Default) */ | |
2202 | e1e_wphy(hw, 0x1F35, 0x002A); | |
2203 | /* Enable FFE hysteresis */ | |
2204 | e1e_wphy(hw, 0x1F3E, 0x0067); | |
2205 | /* Fixed FFE for short cable lengths */ | |
2206 | e1e_wphy(hw, 0x1F54, 0x0065); | |
2207 | /* Fixed FFE for medium cable lengths */ | |
2208 | e1e_wphy(hw, 0x1F55, 0x002A); | |
2209 | /* Fixed FFE for long cable lengths */ | |
2210 | e1e_wphy(hw, 0x1F56, 0x002A); | |
2211 | /* Enable Adaptive Clip Threshold */ | |
2212 | e1e_wphy(hw, 0x1F72, 0x3FB0); | |
2213 | /* AHT reset limit to 1 */ | |
2214 | e1e_wphy(hw, 0x1F76, 0xC0FF); | |
2215 | /* Set AHT master delay to 127 msec */ | |
2216 | e1e_wphy(hw, 0x1F77, 0x1DEC); | |
2217 | /* Set scan bits for AHT */ | |
2218 | e1e_wphy(hw, 0x1F78, 0xF9EF); | |
2219 | /* Set AHT Preset bits */ | |
2220 | e1e_wphy(hw, 0x1F79, 0x0210); | |
2221 | /* Change integ_factor of channel A to 3 */ | |
2222 | e1e_wphy(hw, 0x1895, 0x0003); | |
2223 | /* Change prop_factor of channels BCD to 8 */ | |
2224 | e1e_wphy(hw, 0x1796, 0x0008); | |
2225 | /* Change cg_icount + enable integbp for channels BCD */ | |
2226 | e1e_wphy(hw, 0x1798, 0xD008); | |
2227 | /* | |
2228 | * Change cg_icount + enable integbp + change prop_factor_master | |
2229 | * to 8 for channel A | |
2230 | */ | |
2231 | e1e_wphy(hw, 0x1898, 0xD918); | |
2232 | /* Disable AHT in Slave mode on channel A */ | |
2233 | e1e_wphy(hw, 0x187A, 0x0800); | |
2234 | /* | |
2235 | * Enable LPLU and disable AN to 1000 in non-D0a states, | |
2236 | * Enable SPD+B2B | |
2237 | */ | |
2238 | e1e_wphy(hw, 0x0019, 0x008D); | |
2239 | /* Enable restart AN on an1000_dis change */ | |
2240 | e1e_wphy(hw, 0x001B, 0x2080); | |
2241 | /* Enable wh_fifo read clock in 10/100 modes */ | |
2242 | e1e_wphy(hw, 0x0014, 0x0045); | |
2243 | /* Restart AN, Speed selection is 1000 */ | |
2244 | e1e_wphy(hw, 0x0000, 0x1340); | |
2245 | ||
2246 | return 0; | |
2247 | } | |
2248 | ||
bc7f75fa AK |
2249 | /* Internal function pointers */ |
2250 | ||
2251 | /** | |
2252 | * e1000_get_phy_cfg_done - Generic PHY configuration done | |
2253 | * @hw: pointer to the HW structure | |
2254 | * | |
2255 | * Return success if silicon family did not implement a family specific | |
2256 | * get_cfg_done function. | |
2257 | **/ | |
2258 | static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw) | |
2259 | { | |
2260 | if (hw->phy.ops.get_cfg_done) | |
2261 | return hw->phy.ops.get_cfg_done(hw); | |
2262 | ||
2263 | return 0; | |
2264 | } | |
2265 | ||
2266 | /** | |
2267 | * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex | |
2268 | * @hw: pointer to the HW structure | |
2269 | * | |
2270 | * When the silicon family has not implemented a forced speed/duplex | |
2271 | * function for the PHY, simply return 0. | |
2272 | **/ | |
2273 | static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw) | |
2274 | { | |
2275 | if (hw->phy.ops.force_speed_duplex) | |
2276 | return hw->phy.ops.force_speed_duplex(hw); | |
2277 | ||
2278 | return 0; | |
2279 | } | |
2280 | ||
2281 | /** | |
2282 | * e1000e_get_phy_type_from_id - Get PHY type from id | |
2283 | * @phy_id: phy_id read from the phy | |
2284 | * | |
2285 | * Returns the phy type from the id. | |
2286 | **/ | |
2287 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) | |
2288 | { | |
2289 | enum e1000_phy_type phy_type = e1000_phy_unknown; | |
2290 | ||
2291 | switch (phy_id) { | |
2292 | case M88E1000_I_PHY_ID: | |
2293 | case M88E1000_E_PHY_ID: | |
2294 | case M88E1111_I_PHY_ID: | |
2295 | case M88E1011_I_PHY_ID: | |
2296 | phy_type = e1000_phy_m88; | |
2297 | break; | |
2298 | case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ | |
2299 | phy_type = e1000_phy_igp_2; | |
2300 | break; | |
2301 | case GG82563_E_PHY_ID: | |
2302 | phy_type = e1000_phy_gg82563; | |
2303 | break; | |
2304 | case IGP03E1000_E_PHY_ID: | |
2305 | phy_type = e1000_phy_igp_3; | |
2306 | break; | |
2307 | case IFE_E_PHY_ID: | |
2308 | case IFE_PLUS_E_PHY_ID: | |
2309 | case IFE_C_E_PHY_ID: | |
2310 | phy_type = e1000_phy_ife; | |
2311 | break; | |
97ac8cae BA |
2312 | case BME1000_E_PHY_ID: |
2313 | case BME1000_E_PHY_ID_R2: | |
2314 | phy_type = e1000_phy_bm; | |
2315 | break; | |
a4f58f54 BA |
2316 | case I82578_E_PHY_ID: |
2317 | phy_type = e1000_phy_82578; | |
2318 | break; | |
2319 | case I82577_E_PHY_ID: | |
2320 | phy_type = e1000_phy_82577; | |
2321 | break; | |
d3738bb8 BA |
2322 | case I82579_E_PHY_ID: |
2323 | phy_type = e1000_phy_82579; | |
2324 | break; | |
bc7f75fa AK |
2325 | default: |
2326 | phy_type = e1000_phy_unknown; | |
2327 | break; | |
2328 | } | |
2329 | return phy_type; | |
2330 | } | |
2331 | ||
97ac8cae BA |
2332 | /** |
2333 | * e1000e_determine_phy_address - Determines PHY address. | |
2334 | * @hw: pointer to the HW structure | |
2335 | * | |
2336 | * This uses a trial and error method to loop through possible PHY | |
2337 | * addresses. It tests each by reading the PHY ID registers and | |
2338 | * checking for a match. | |
2339 | **/ | |
2340 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) | |
2341 | { | |
2342 | s32 ret_val = -E1000_ERR_PHY_TYPE; | |
5eb6f3c7 BA |
2343 | u32 phy_addr = 0; |
2344 | u32 i; | |
97ac8cae BA |
2345 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
2346 | ||
5eb6f3c7 BA |
2347 | hw->phy.id = phy_type; |
2348 | ||
2349 | for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { | |
2350 | hw->phy.addr = phy_addr; | |
2351 | i = 0; | |
2352 | ||
2353 | do { | |
97ac8cae BA |
2354 | e1000e_get_phy_id(hw); |
2355 | phy_type = e1000e_get_phy_type_from_id(hw->phy.id); | |
2356 | ||
5eb6f3c7 | 2357 | /* |
97ac8cae BA |
2358 | * If phy_type is valid, break - we found our |
2359 | * PHY address | |
2360 | */ | |
2361 | if (phy_type != e1000_phy_unknown) { | |
2362 | ret_val = 0; | |
5eb6f3c7 | 2363 | goto out; |
97ac8cae | 2364 | } |
5eb6f3c7 BA |
2365 | msleep(1); |
2366 | i++; | |
2367 | } while (i < 10); | |
2368 | } | |
97ac8cae | 2369 | |
5eb6f3c7 | 2370 | out: |
97ac8cae BA |
2371 | return ret_val; |
2372 | } | |
2373 | ||
2374 | /** | |
2375 | * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address | |
2376 | * @page: page to access | |
2377 | * | |
2378 | * Returns the phy address for the page requested. | |
2379 | **/ | |
2380 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) | |
2381 | { | |
2382 | u32 phy_addr = 2; | |
2383 | ||
2384 | if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) | |
2385 | phy_addr = 1; | |
2386 | ||
2387 | return phy_addr; | |
2388 | } | |
2389 | ||
2390 | /** | |
2391 | * e1000e_write_phy_reg_bm - Write BM PHY register | |
2392 | * @hw: pointer to the HW structure | |
2393 | * @offset: register offset to write to | |
2394 | * @data: data to write at register offset | |
2395 | * | |
2396 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2397 | * at the offset. Release any acquired semaphores before exiting. | |
2398 | **/ | |
2399 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) | |
2400 | { | |
2401 | s32 ret_val; | |
2402 | u32 page_select = 0; | |
2403 | u32 page = offset >> IGP_PAGE_SHIFT; | |
2404 | u32 page_shift = 0; | |
2405 | ||
94d8186a | 2406 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2407 | if (ret_val) |
2408 | return ret_val; | |
2409 | ||
97ac8cae BA |
2410 | /* Page 800 works differently than the rest so it has its own func */ |
2411 | if (page == BM_WUC_PAGE) { | |
2412 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2413 | false); | |
2414 | goto out; | |
2415 | } | |
2416 | ||
97ac8cae BA |
2417 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2418 | ||
2419 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2420 | /* | |
2421 | * Page select is register 31 for phy address 1 and 22 for | |
2422 | * phy address 2 and 3. Page select is shifted only for | |
2423 | * phy address 1. | |
2424 | */ | |
2425 | if (hw->phy.addr == 1) { | |
2426 | page_shift = IGP_PAGE_SHIFT; | |
2427 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2428 | } else { | |
2429 | page_shift = 0; | |
2430 | page_select = BM_PHY_PAGE_SELECT; | |
2431 | } | |
2432 | ||
2433 | /* Page is shifted left, PHY expects (page x 32) */ | |
2434 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2435 | (page << page_shift)); | |
5ccdcecb | 2436 | if (ret_val) |
97ac8cae | 2437 | goto out; |
97ac8cae BA |
2438 | } |
2439 | ||
2440 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2441 | data); | |
2442 | ||
97ac8cae | 2443 | out: |
94d8186a | 2444 | hw->phy.ops.release(hw); |
97ac8cae BA |
2445 | return ret_val; |
2446 | } | |
2447 | ||
2448 | /** | |
2449 | * e1000e_read_phy_reg_bm - Read BM PHY register | |
2450 | * @hw: pointer to the HW structure | |
2451 | * @offset: register offset to be read | |
2452 | * @data: pointer to the read data | |
2453 | * | |
2454 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2455 | * and storing the retrieved information in data. Release any acquired | |
2456 | * semaphores before exiting. | |
2457 | **/ | |
2458 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) | |
2459 | { | |
2460 | s32 ret_val; | |
2461 | u32 page_select = 0; | |
2462 | u32 page = offset >> IGP_PAGE_SHIFT; | |
2463 | u32 page_shift = 0; | |
2464 | ||
94d8186a | 2465 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2466 | if (ret_val) |
2467 | return ret_val; | |
2468 | ||
97ac8cae BA |
2469 | /* Page 800 works differently than the rest so it has its own func */ |
2470 | if (page == BM_WUC_PAGE) { | |
2471 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2472 | true); | |
2473 | goto out; | |
2474 | } | |
2475 | ||
97ac8cae BA |
2476 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2477 | ||
2478 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2479 | /* | |
2480 | * Page select is register 31 for phy address 1 and 22 for | |
2481 | * phy address 2 and 3. Page select is shifted only for | |
2482 | * phy address 1. | |
2483 | */ | |
2484 | if (hw->phy.addr == 1) { | |
2485 | page_shift = IGP_PAGE_SHIFT; | |
2486 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2487 | } else { | |
2488 | page_shift = 0; | |
2489 | page_select = BM_PHY_PAGE_SELECT; | |
2490 | } | |
2491 | ||
2492 | /* Page is shifted left, PHY expects (page x 32) */ | |
2493 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2494 | (page << page_shift)); | |
5ccdcecb | 2495 | if (ret_val) |
97ac8cae | 2496 | goto out; |
97ac8cae BA |
2497 | } |
2498 | ||
2499 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2500 | data); | |
97ac8cae | 2501 | out: |
94d8186a | 2502 | hw->phy.ops.release(hw); |
97ac8cae BA |
2503 | return ret_val; |
2504 | } | |
2505 | ||
4662e82b BA |
2506 | /** |
2507 | * e1000e_read_phy_reg_bm2 - Read BM PHY register | |
2508 | * @hw: pointer to the HW structure | |
2509 | * @offset: register offset to be read | |
2510 | * @data: pointer to the read data | |
2511 | * | |
2512 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2513 | * and storing the retrieved information in data. Release any acquired | |
2514 | * semaphores before exiting. | |
2515 | **/ | |
2516 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) | |
2517 | { | |
2518 | s32 ret_val; | |
2519 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2520 | ||
94d8186a | 2521 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2522 | if (ret_val) |
2523 | return ret_val; | |
2524 | ||
4662e82b BA |
2525 | /* Page 800 works differently than the rest so it has its own func */ |
2526 | if (page == BM_WUC_PAGE) { | |
2527 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2528 | true); | |
5ccdcecb | 2529 | goto out; |
4662e82b BA |
2530 | } |
2531 | ||
4662e82b BA |
2532 | hw->phy.addr = 1; |
2533 | ||
2534 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2535 | ||
2536 | /* Page is shifted left, PHY expects (page x 32) */ | |
2537 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2538 | page); | |
2539 | ||
5ccdcecb BA |
2540 | if (ret_val) |
2541 | goto out; | |
4662e82b BA |
2542 | } |
2543 | ||
2544 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2545 | data); | |
5ccdcecb | 2546 | out: |
94d8186a | 2547 | hw->phy.ops.release(hw); |
4662e82b BA |
2548 | return ret_val; |
2549 | } | |
2550 | ||
2551 | /** | |
2552 | * e1000e_write_phy_reg_bm2 - Write BM PHY register | |
2553 | * @hw: pointer to the HW structure | |
2554 | * @offset: register offset to write to | |
2555 | * @data: data to write at register offset | |
2556 | * | |
2557 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2558 | * at the offset. Release any acquired semaphores before exiting. | |
2559 | **/ | |
2560 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) | |
2561 | { | |
2562 | s32 ret_val; | |
2563 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2564 | ||
94d8186a | 2565 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2566 | if (ret_val) |
2567 | return ret_val; | |
2568 | ||
4662e82b BA |
2569 | /* Page 800 works differently than the rest so it has its own func */ |
2570 | if (page == BM_WUC_PAGE) { | |
2571 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2572 | false); | |
5ccdcecb | 2573 | goto out; |
4662e82b BA |
2574 | } |
2575 | ||
4662e82b BA |
2576 | hw->phy.addr = 1; |
2577 | ||
2578 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2579 | /* Page is shifted left, PHY expects (page x 32) */ | |
2580 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2581 | page); | |
2582 | ||
5ccdcecb BA |
2583 | if (ret_val) |
2584 | goto out; | |
4662e82b BA |
2585 | } |
2586 | ||
2587 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2588 | data); | |
2589 | ||
5ccdcecb | 2590 | out: |
94d8186a | 2591 | hw->phy.ops.release(hw); |
4662e82b BA |
2592 | return ret_val; |
2593 | } | |
2594 | ||
97ac8cae BA |
2595 | /** |
2596 | * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register | |
2597 | * @hw: pointer to the HW structure | |
2598 | * @offset: register offset to be read or written | |
2599 | * @data: pointer to the data to read or write | |
2600 | * @read: determines if operation is read or write | |
2601 | * | |
2602 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2603 | * and storing the retrieved information in data. Release any acquired | |
2604 | * semaphores before exiting. Note that procedure to read the wakeup | |
2605 | * registers are different. It works as such: | |
2606 | * 1) Set page 769, register 17, bit 2 = 1 | |
2607 | * 2) Set page to 800 for host (801 if we were manageability) | |
2608 | * 3) Write the address using the address opcode (0x11) | |
2609 | * 4) Read or write the data using the data opcode (0x12) | |
2610 | * 5) Restore 769_17.2 to its original value | |
5ccdcecb BA |
2611 | * |
2612 | * Assumes semaphore already acquired. | |
97ac8cae BA |
2613 | **/ |
2614 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
2615 | u16 *data, bool read) | |
2616 | { | |
2617 | s32 ret_val; | |
a4f58f54 | 2618 | u16 reg = BM_PHY_REG_NUM(offset); |
97ac8cae | 2619 | u16 phy_reg = 0; |
97ac8cae | 2620 | |
a4f58f54 BA |
2621 | /* Gig must be disabled for MDIO accesses to page 800 */ |
2622 | if ((hw->mac.type == e1000_pchlan) && | |
2623 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) | |
9b71b419 | 2624 | e_dbg("Attempting to access page 800 while gig enabled.\n"); |
a4f58f54 | 2625 | |
97ac8cae BA |
2626 | /* All operations in this function are phy address 1 */ |
2627 | hw->phy.addr = 1; | |
2628 | ||
2629 | /* Set page 769 */ | |
2630 | e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2631 | (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); | |
2632 | ||
2633 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg); | |
9b71b419 BA |
2634 | if (ret_val) { |
2635 | e_dbg("Could not read PHY page 769\n"); | |
97ac8cae | 2636 | goto out; |
9b71b419 | 2637 | } |
97ac8cae BA |
2638 | |
2639 | /* First clear bit 4 to avoid a power state change */ | |
2640 | phy_reg &= ~(BM_WUC_HOST_WU_BIT); | |
2641 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); | |
9b71b419 BA |
2642 | if (ret_val) { |
2643 | e_dbg("Could not clear PHY page 769 bit 4\n"); | |
97ac8cae | 2644 | goto out; |
9b71b419 | 2645 | } |
97ac8cae BA |
2646 | |
2647 | /* Write bit 2 = 1, and clear bit 4 to 769_17 */ | |
2648 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, | |
2649 | phy_reg | BM_WUC_ENABLE_BIT); | |
9b71b419 BA |
2650 | if (ret_val) { |
2651 | e_dbg("Could not write PHY page 769 bit 2\n"); | |
97ac8cae | 2652 | goto out; |
9b71b419 | 2653 | } |
97ac8cae BA |
2654 | |
2655 | /* Select page 800 */ | |
2656 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2657 | (BM_WUC_PAGE << IGP_PAGE_SHIFT)); | |
2658 | ||
2659 | /* Write the page 800 offset value using opcode 0x11 */ | |
2660 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); | |
9b71b419 BA |
2661 | if (ret_val) { |
2662 | e_dbg("Could not write address opcode to page 800\n"); | |
97ac8cae | 2663 | goto out; |
9b71b419 | 2664 | } |
97ac8cae BA |
2665 | |
2666 | if (read) { | |
2667 | /* Read the page 800 value using opcode 0x12 */ | |
2668 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, | |
2669 | data); | |
2670 | } else { | |
5ff5b664 | 2671 | /* Write the page 800 value using opcode 0x12 */ |
97ac8cae BA |
2672 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
2673 | *data); | |
2674 | } | |
2675 | ||
9b71b419 BA |
2676 | if (ret_val) { |
2677 | e_dbg("Could not access data value from page 800\n"); | |
97ac8cae | 2678 | goto out; |
9b71b419 | 2679 | } |
97ac8cae BA |
2680 | |
2681 | /* | |
2682 | * Restore 769_17.2 to its original value | |
2683 | * Set page 769 | |
2684 | */ | |
2685 | e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, | |
2686 | (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT)); | |
2687 | ||
2688 | /* Clear 769_17.2 */ | |
2689 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); | |
9b71b419 BA |
2690 | if (ret_val) { |
2691 | e_dbg("Could not clear PHY page 769 bit 2\n"); | |
2692 | goto out; | |
2693 | } | |
97ac8cae BA |
2694 | |
2695 | out: | |
97ac8cae BA |
2696 | return ret_val; |
2697 | } | |
2698 | ||
17f208de BA |
2699 | /** |
2700 | * e1000_power_up_phy_copper - Restore copper link in case of PHY power down | |
2701 | * @hw: pointer to the HW structure | |
2702 | * | |
2703 | * In the case of a PHY power down to save power, or to turn off link during a | |
2704 | * driver unload, or wake on lan is not enabled, restore the link to previous | |
2705 | * settings. | |
2706 | **/ | |
2707 | void e1000_power_up_phy_copper(struct e1000_hw *hw) | |
2708 | { | |
2709 | u16 mii_reg = 0; | |
2710 | ||
2711 | /* The PHY will retain its settings across a power down/up cycle */ | |
2712 | e1e_rphy(hw, PHY_CONTROL, &mii_reg); | |
2713 | mii_reg &= ~MII_CR_POWER_DOWN; | |
2714 | e1e_wphy(hw, PHY_CONTROL, mii_reg); | |
2715 | } | |
2716 | ||
2717 | /** | |
2718 | * e1000_power_down_phy_copper - Restore copper link in case of PHY power down | |
2719 | * @hw: pointer to the HW structure | |
2720 | * | |
2721 | * In the case of a PHY power down to save power, or to turn off link during a | |
2722 | * driver unload, or wake on lan is not enabled, restore the link to previous | |
2723 | * settings. | |
2724 | **/ | |
2725 | void e1000_power_down_phy_copper(struct e1000_hw *hw) | |
2726 | { | |
2727 | u16 mii_reg = 0; | |
2728 | ||
2729 | /* The PHY will retain its settings across a power down/up cycle */ | |
2730 | e1e_rphy(hw, PHY_CONTROL, &mii_reg); | |
2731 | mii_reg |= MII_CR_POWER_DOWN; | |
2732 | e1e_wphy(hw, PHY_CONTROL, mii_reg); | |
2733 | msleep(1); | |
2734 | } | |
2735 | ||
bc7f75fa AK |
2736 | /** |
2737 | * e1000e_commit_phy - Soft PHY reset | |
2738 | * @hw: pointer to the HW structure | |
2739 | * | |
2740 | * Performs a soft PHY reset on those that apply. This is a function pointer | |
2741 | * entry point called by drivers. | |
2742 | **/ | |
2743 | s32 e1000e_commit_phy(struct e1000_hw *hw) | |
2744 | { | |
94d8186a BA |
2745 | if (hw->phy.ops.commit) |
2746 | return hw->phy.ops.commit(hw); | |
bc7f75fa AK |
2747 | |
2748 | return 0; | |
2749 | } | |
2750 | ||
2751 | /** | |
2752 | * e1000_set_d0_lplu_state - Sets low power link up state for D0 | |
2753 | * @hw: pointer to the HW structure | |
2754 | * @active: boolean used to enable/disable lplu | |
2755 | * | |
2756 | * Success returns 0, Failure returns 1 | |
2757 | * | |
2758 | * The low power link up (lplu) state is set to the power management level D0 | |
2759 | * and SmartSpeed is disabled when active is true, else clear lplu for D0 | |
2760 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
2761 | * is used during Dx states where the power conservation is most important. | |
2762 | * During driver activity, SmartSpeed should be enabled so performance is | |
2763 | * maintained. This is a function pointer entry point called by drivers. | |
2764 | **/ | |
2765 | static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) | |
2766 | { | |
2767 | if (hw->phy.ops.set_d0_lplu_state) | |
2768 | return hw->phy.ops.set_d0_lplu_state(hw, active); | |
2769 | ||
2770 | return 0; | |
2771 | } | |
a4f58f54 | 2772 | |
a4f58f54 | 2773 | /** |
5ccdcecb | 2774 | * __e1000_read_phy_reg_hv - Read HV PHY register |
a4f58f54 BA |
2775 | * @hw: pointer to the HW structure |
2776 | * @offset: register offset to be read | |
2777 | * @data: pointer to the read data | |
5ccdcecb | 2778 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2779 | * |
2780 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 2781 | * and stores the retrieved information in data. Release any acquired |
a4f58f54 BA |
2782 | * semaphore before exiting. |
2783 | **/ | |
5ccdcecb BA |
2784 | static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
2785 | bool locked) | |
a4f58f54 BA |
2786 | { |
2787 | s32 ret_val; | |
2788 | u16 page = BM_PHY_REG_PAGE(offset); | |
2789 | u16 reg = BM_PHY_REG_NUM(offset); | |
a4f58f54 | 2790 | |
5ccdcecb | 2791 | if (!locked) { |
94d8186a | 2792 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2793 | if (ret_val) |
2794 | return ret_val; | |
2795 | } | |
2796 | ||
a4f58f54 BA |
2797 | /* Page 800 works differently than the rest so it has its own func */ |
2798 | if (page == BM_WUC_PAGE) { | |
2799 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, | |
2800 | data, true); | |
2801 | goto out; | |
2802 | } | |
2803 | ||
2804 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2805 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2806 | data, true); | |
2807 | goto out; | |
2808 | } | |
2809 | ||
a4f58f54 BA |
2810 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
2811 | ||
2812 | if (page == HV_INTC_FC_PAGE_START) | |
2813 | page = 0; | |
2814 | ||
2815 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | |
842ec8b6 | 2816 | u32 phy_addr = hw->phy.addr; |
a4f58f54 | 2817 | |
842ec8b6 | 2818 | hw->phy.addr = 1; |
a4f58f54 | 2819 | |
842ec8b6 BA |
2820 | /* Page is shifted left, PHY expects (page x 32) */ |
2821 | ret_val = e1000e_write_phy_reg_mdic(hw, | |
2822 | IGP01E1000_PHY_PAGE_SELECT, | |
2823 | (page << IGP_PAGE_SHIFT)); | |
2824 | hw->phy.addr = phy_addr; | |
2825 | ||
2826 | if (ret_val) | |
2827 | goto out; | |
a4f58f54 BA |
2828 | } |
2829 | ||
2830 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | |
2831 | data); | |
a4f58f54 | 2832 | out: |
5ccdcecb | 2833 | if (!locked) |
94d8186a | 2834 | hw->phy.ops.release(hw); |
5ccdcecb | 2835 | |
a4f58f54 BA |
2836 | return ret_val; |
2837 | } | |
2838 | ||
2839 | /** | |
5ccdcecb BA |
2840 | * e1000_read_phy_reg_hv - Read HV PHY register |
2841 | * @hw: pointer to the HW structure | |
2842 | * @offset: register offset to be read | |
2843 | * @data: pointer to the read data | |
2844 | * | |
2845 | * Acquires semaphore then reads the PHY register at offset and stores | |
2846 | * the retrieved information in data. Release the acquired semaphore | |
2847 | * before exiting. | |
2848 | **/ | |
2849 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |
2850 | { | |
2851 | return __e1000_read_phy_reg_hv(hw, offset, data, false); | |
2852 | } | |
2853 | ||
2854 | /** | |
2855 | * e1000_read_phy_reg_hv_locked - Read HV PHY register | |
2856 | * @hw: pointer to the HW structure | |
2857 | * @offset: register offset to be read | |
2858 | * @data: pointer to the read data | |
2859 | * | |
2860 | * Reads the PHY register at offset and stores the retrieved information | |
2861 | * in data. Assumes semaphore already acquired. | |
2862 | **/ | |
2863 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
2864 | { | |
2865 | return __e1000_read_phy_reg_hv(hw, offset, data, true); | |
2866 | } | |
2867 | ||
2868 | /** | |
2869 | * __e1000_write_phy_reg_hv - Write HV PHY register | |
a4f58f54 BA |
2870 | * @hw: pointer to the HW structure |
2871 | * @offset: register offset to write to | |
2872 | * @data: data to write at register offset | |
5ccdcecb | 2873 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2874 | * |
2875 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2876 | * at the offset. Release any acquired semaphores before exiting. | |
2877 | **/ | |
5ccdcecb BA |
2878 | static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
2879 | bool locked) | |
a4f58f54 BA |
2880 | { |
2881 | s32 ret_val; | |
2882 | u16 page = BM_PHY_REG_PAGE(offset); | |
2883 | u16 reg = BM_PHY_REG_NUM(offset); | |
a4f58f54 | 2884 | |
5ccdcecb | 2885 | if (!locked) { |
94d8186a | 2886 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2887 | if (ret_val) |
2888 | return ret_val; | |
2889 | } | |
2890 | ||
a4f58f54 BA |
2891 | /* Page 800 works differently than the rest so it has its own func */ |
2892 | if (page == BM_WUC_PAGE) { | |
2893 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, | |
2894 | &data, false); | |
2895 | goto out; | |
2896 | } | |
2897 | ||
2898 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2899 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2900 | &data, false); | |
2901 | goto out; | |
2902 | } | |
2903 | ||
a4f58f54 BA |
2904 | hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
2905 | ||
2906 | if (page == HV_INTC_FC_PAGE_START) | |
2907 | page = 0; | |
2908 | ||
2909 | /* | |
2910 | * Workaround MDIO accesses being disabled after entering IEEE Power | |
2911 | * Down (whenever bit 11 of the PHY Control register is set) | |
2912 | */ | |
2913 | if ((hw->phy.type == e1000_phy_82578) && | |
2914 | (hw->phy.revision >= 1) && | |
2915 | (hw->phy.addr == 2) && | |
2916 | ((MAX_PHY_REG_ADDRESS & reg) == 0) && | |
2917 | (data & (1 << 11))) { | |
2918 | u16 data2 = 0x7EFF; | |
a4f58f54 BA |
2919 | ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3, |
2920 | &data2, false); | |
2921 | if (ret_val) | |
2922 | goto out; | |
a4f58f54 BA |
2923 | } |
2924 | ||
2925 | if (reg > MAX_PHY_MULTI_PAGE_REG) { | |
842ec8b6 | 2926 | u32 phy_addr = hw->phy.addr; |
a4f58f54 | 2927 | |
842ec8b6 | 2928 | hw->phy.addr = 1; |
a4f58f54 | 2929 | |
842ec8b6 BA |
2930 | /* Page is shifted left, PHY expects (page x 32) */ |
2931 | ret_val = e1000e_write_phy_reg_mdic(hw, | |
2932 | IGP01E1000_PHY_PAGE_SELECT, | |
2933 | (page << IGP_PAGE_SHIFT)); | |
2934 | hw->phy.addr = phy_addr; | |
2935 | ||
2936 | if (ret_val) | |
2937 | goto out; | |
a4f58f54 BA |
2938 | } |
2939 | ||
2940 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, | |
2941 | data); | |
a4f58f54 BA |
2942 | |
2943 | out: | |
5ccdcecb | 2944 | if (!locked) |
94d8186a | 2945 | hw->phy.ops.release(hw); |
5ccdcecb | 2946 | |
a4f58f54 BA |
2947 | return ret_val; |
2948 | } | |
2949 | ||
5ccdcecb BA |
2950 | /** |
2951 | * e1000_write_phy_reg_hv - Write HV PHY register | |
2952 | * @hw: pointer to the HW structure | |
2953 | * @offset: register offset to write to | |
2954 | * @data: data to write at register offset | |
2955 | * | |
2956 | * Acquires semaphore then writes the data to PHY register at the offset. | |
2957 | * Release the acquired semaphores before exiting. | |
2958 | **/ | |
2959 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | |
2960 | { | |
2961 | return __e1000_write_phy_reg_hv(hw, offset, data, false); | |
2962 | } | |
2963 | ||
2964 | /** | |
2965 | * e1000_write_phy_reg_hv_locked - Write HV PHY register | |
2966 | * @hw: pointer to the HW structure | |
2967 | * @offset: register offset to write to | |
2968 | * @data: data to write at register offset | |
2969 | * | |
2970 | * Writes the data to PHY register at the offset. Assumes semaphore | |
2971 | * already acquired. | |
2972 | **/ | |
2973 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
2974 | { | |
2975 | return __e1000_write_phy_reg_hv(hw, offset, data, true); | |
2976 | } | |
2977 | ||
a4f58f54 | 2978 | /** |
b595076a | 2979 | * e1000_get_phy_addr_for_hv_page - Get PHY address based on page |
a4f58f54 BA |
2980 | * @page: page to be accessed |
2981 | **/ | |
2982 | static u32 e1000_get_phy_addr_for_hv_page(u32 page) | |
2983 | { | |
2984 | u32 phy_addr = 2; | |
2985 | ||
2986 | if (page >= HV_INTC_FC_PAGE_START) | |
2987 | phy_addr = 1; | |
2988 | ||
2989 | return phy_addr; | |
2990 | } | |
2991 | ||
2992 | /** | |
2993 | * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers | |
2994 | * @hw: pointer to the HW structure | |
2995 | * @offset: register offset to be read or written | |
2996 | * @data: pointer to the data to be read or written | |
2997 | * @read: determines if operation is read or written | |
2998 | * | |
5ccdcecb BA |
2999 | * Reads the PHY register at offset and stores the retreived information |
3000 | * in data. Assumes semaphore already acquired. Note that the procedure | |
3001 | * to read these regs uses the address port and data port to read/write. | |
a4f58f54 BA |
3002 | **/ |
3003 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
3004 | u16 *data, bool read) | |
3005 | { | |
3006 | s32 ret_val; | |
3007 | u32 addr_reg = 0; | |
3008 | u32 data_reg = 0; | |
a4f58f54 BA |
3009 | |
3010 | /* This takes care of the difference with desktop vs mobile phy */ | |
3011 | addr_reg = (hw->phy.type == e1000_phy_82578) ? | |
3012 | I82578_ADDR_REG : I82577_ADDR_REG; | |
3013 | data_reg = addr_reg + 1; | |
3014 | ||
a4f58f54 BA |
3015 | /* All operations in this function are phy address 2 */ |
3016 | hw->phy.addr = 2; | |
3017 | ||
3018 | /* masking with 0x3F to remove the page from offset */ | |
3019 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); | |
3020 | if (ret_val) { | |
3bb99fe2 | 3021 | e_dbg("Could not write PHY the HV address register\n"); |
a4f58f54 BA |
3022 | goto out; |
3023 | } | |
3024 | ||
3025 | /* Read or write the data value next */ | |
3026 | if (read) | |
3027 | ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); | |
3028 | else | |
3029 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); | |
3030 | ||
3031 | if (ret_val) { | |
3bb99fe2 | 3032 | e_dbg("Could not read data value from HV data register\n"); |
a4f58f54 BA |
3033 | goto out; |
3034 | } | |
3035 | ||
3036 | out: | |
a4f58f54 BA |
3037 | return ret_val; |
3038 | } | |
3039 | ||
3040 | /** | |
3041 | * e1000_link_stall_workaround_hv - Si workaround | |
3042 | * @hw: pointer to the HW structure | |
3043 | * | |
3044 | * This function works around a Si bug where the link partner can get | |
3045 | * a link up indication before the PHY does. If small packets are sent | |
3046 | * by the link partner they can be placed in the packet buffer without | |
3047 | * being properly accounted for by the PHY and will stall preventing | |
3048 | * further packets from being received. The workaround is to clear the | |
3049 | * packet buffer after the PHY detects link up. | |
3050 | **/ | |
3051 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) | |
3052 | { | |
3053 | s32 ret_val = 0; | |
3054 | u16 data; | |
3055 | ||
3056 | if (hw->phy.type != e1000_phy_82578) | |
3057 | goto out; | |
3058 | ||
e65fa87c | 3059 | /* Do not apply workaround if in PHY loopback bit 14 set */ |
94d8186a | 3060 | hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); |
e65fa87c BA |
3061 | if (data & PHY_CONTROL_LB) |
3062 | goto out; | |
3063 | ||
a4f58f54 | 3064 | /* check if link is up and at 1Gbps */ |
94d8186a | 3065 | ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); |
a4f58f54 BA |
3066 | if (ret_val) |
3067 | goto out; | |
3068 | ||
3069 | data &= BM_CS_STATUS_LINK_UP | | |
3070 | BM_CS_STATUS_RESOLVED | | |
3071 | BM_CS_STATUS_SPEED_MASK; | |
3072 | ||
3073 | if (data != (BM_CS_STATUS_LINK_UP | | |
3074 | BM_CS_STATUS_RESOLVED | | |
3075 | BM_CS_STATUS_SPEED_1000)) | |
3076 | goto out; | |
3077 | ||
3078 | mdelay(200); | |
3079 | ||
3080 | /* flush the packets in the fifo buffer */ | |
94d8186a | 3081 | ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, |
a4f58f54 BA |
3082 | HV_MUX_DATA_CTRL_GEN_TO_MAC | |
3083 | HV_MUX_DATA_CTRL_FORCE_SPEED); | |
3084 | if (ret_val) | |
3085 | goto out; | |
3086 | ||
94d8186a | 3087 | ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, |
a4f58f54 BA |
3088 | HV_MUX_DATA_CTRL_GEN_TO_MAC); |
3089 | ||
3090 | out: | |
3091 | return ret_val; | |
3092 | } | |
3093 | ||
3094 | /** | |
3095 | * e1000_check_polarity_82577 - Checks the polarity. | |
3096 | * @hw: pointer to the HW structure | |
3097 | * | |
3098 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
3099 | * | |
3100 | * Polarity is determined based on the PHY specific status register. | |
3101 | **/ | |
3102 | s32 e1000_check_polarity_82577(struct e1000_hw *hw) | |
3103 | { | |
3104 | struct e1000_phy_info *phy = &hw->phy; | |
3105 | s32 ret_val; | |
3106 | u16 data; | |
3107 | ||
94d8186a | 3108 | ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 BA |
3109 | |
3110 | if (!ret_val) | |
3111 | phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) | |
3112 | ? e1000_rev_polarity_reversed | |
3113 | : e1000_rev_polarity_normal; | |
3114 | ||
3115 | return ret_val; | |
3116 | } | |
3117 | ||
3118 | /** | |
3119 | * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY | |
3120 | * @hw: pointer to the HW structure | |
3121 | * | |
eab50ffb | 3122 | * Calls the PHY setup function to force speed and duplex. |
a4f58f54 BA |
3123 | **/ |
3124 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) | |
3125 | { | |
3126 | struct e1000_phy_info *phy = &hw->phy; | |
3127 | s32 ret_val; | |
3128 | u16 phy_data; | |
3129 | bool link; | |
3130 | ||
94d8186a | 3131 | ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); |
a4f58f54 BA |
3132 | if (ret_val) |
3133 | goto out; | |
3134 | ||
3135 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
3136 | ||
94d8186a | 3137 | ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); |
a4f58f54 BA |
3138 | if (ret_val) |
3139 | goto out; | |
3140 | ||
a4f58f54 BA |
3141 | udelay(1); |
3142 | ||
3143 | if (phy->autoneg_wait_to_complete) { | |
3bb99fe2 | 3144 | e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
a4f58f54 BA |
3145 | |
3146 | ret_val = e1000e_phy_has_link_generic(hw, | |
3147 | PHY_FORCE_LIMIT, | |
3148 | 100000, | |
3149 | &link); | |
3150 | if (ret_val) | |
3151 | goto out; | |
3152 | ||
3153 | if (!link) | |
3bb99fe2 | 3154 | e_dbg("Link taking longer than expected.\n"); |
a4f58f54 BA |
3155 | |
3156 | /* Try once more */ | |
3157 | ret_val = e1000e_phy_has_link_generic(hw, | |
3158 | PHY_FORCE_LIMIT, | |
3159 | 100000, | |
3160 | &link); | |
3161 | if (ret_val) | |
3162 | goto out; | |
3163 | } | |
3164 | ||
3165 | out: | |
3166 | return ret_val; | |
3167 | } | |
3168 | ||
3169 | /** | |
3170 | * e1000_get_phy_info_82577 - Retrieve I82577 PHY information | |
3171 | * @hw: pointer to the HW structure | |
3172 | * | |
3173 | * Read PHY status to determine if link is up. If link is up, then | |
3174 | * set/determine 10base-T extended distance and polarity correction. Read | |
3175 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
3176 | * determine on the cable length, local and remote receiver. | |
3177 | **/ | |
3178 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw) | |
3179 | { | |
3180 | struct e1000_phy_info *phy = &hw->phy; | |
3181 | s32 ret_val; | |
3182 | u16 data; | |
3183 | bool link; | |
3184 | ||
3185 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
3186 | if (ret_val) | |
3187 | goto out; | |
3188 | ||
3189 | if (!link) { | |
3bb99fe2 | 3190 | e_dbg("Phy info is only valid if link is up\n"); |
a4f58f54 BA |
3191 | ret_val = -E1000_ERR_CONFIG; |
3192 | goto out; | |
3193 | } | |
3194 | ||
3195 | phy->polarity_correction = true; | |
3196 | ||
3197 | ret_val = e1000_check_polarity_82577(hw); | |
3198 | if (ret_val) | |
3199 | goto out; | |
3200 | ||
94d8186a | 3201 | ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 BA |
3202 | if (ret_val) |
3203 | goto out; | |
3204 | ||
3205 | phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false; | |
3206 | ||
3207 | if ((data & I82577_PHY_STATUS2_SPEED_MASK) == | |
3208 | I82577_PHY_STATUS2_SPEED_1000MBPS) { | |
3209 | ret_val = hw->phy.ops.get_cable_length(hw); | |
3210 | if (ret_val) | |
3211 | goto out; | |
3212 | ||
94d8186a | 3213 | ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); |
a4f58f54 BA |
3214 | if (ret_val) |
3215 | goto out; | |
3216 | ||
3217 | phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) | |
3218 | ? e1000_1000t_rx_status_ok | |
3219 | : e1000_1000t_rx_status_not_ok; | |
3220 | ||
3221 | phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) | |
3222 | ? e1000_1000t_rx_status_ok | |
3223 | : e1000_1000t_rx_status_not_ok; | |
3224 | } else { | |
3225 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
3226 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
3227 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
3228 | } | |
3229 | ||
3230 | out: | |
3231 | return ret_val; | |
3232 | } | |
3233 | ||
3234 | /** | |
3235 | * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY | |
3236 | * @hw: pointer to the HW structure | |
3237 | * | |
3238 | * Reads the diagnostic status register and verifies result is valid before | |
3239 | * placing it in the phy_cable_length field. | |
3240 | **/ | |
3241 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw) | |
3242 | { | |
3243 | struct e1000_phy_info *phy = &hw->phy; | |
3244 | s32 ret_val; | |
3245 | u16 phy_data, length; | |
3246 | ||
94d8186a | 3247 | ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
a4f58f54 BA |
3248 | if (ret_val) |
3249 | goto out; | |
3250 | ||
3251 | length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> | |
3252 | I82577_DSTATUS_CABLE_LENGTH_SHIFT; | |
3253 | ||
3254 | if (length == E1000_CABLE_LENGTH_UNDEFINED) | |
98086a95 | 3255 | ret_val = -E1000_ERR_PHY; |
a4f58f54 BA |
3256 | |
3257 | phy->cable_length = length; | |
3258 | ||
3259 | out: | |
3260 | return ret_val; | |
3261 | } |