projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
phy: fix blackfin build failure
[deliverable/linux.git] / drivers / net / ethernet / adi / bfin_mac.c
CommitLineData
e190d6b1 1/*
2fb9d6f5 2 * Blackfin On-Chip MAC Driver
e190d6b1 3 *
02460d08 4 * Copyright 2004-2010 Analog Devices Inc.
e190d6b1 5 *
2fb9d6f5 6 * Enter bugs at http://blackfin.uclinux.org/
e190d6b1 7 *
2fb9d6f5 8 * Licensed under the GPL-2 or later.
e190d6b1
BW		 9 */
10
c6dd5098
MF		 11#define DRV_VERSION "1.1"
12#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
e190d6b1
BW		 16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/crc32.h>
28#include <linux/device.h>
29#include <linux/spinlock.h>
e190d6b1 30#include <linux/mii.h>
e190d6b1
BW		 31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
679dce39 33#include <linux/ethtool.h>
e190d6b1 34#include <linux/skbuff.h>
e190d6b1 35#include <linux/platform_device.h>
e190d6b1
BW		 36
37#include <asm/dma.h>
38#include <linux/dma-mapping.h>
39
fe92afed 40#include <asm/div64.h>
98f672ca 41#include <asm/dpmc.h>
e190d6b1
BW		 42#include <asm/blackfin.h>
43#include <asm/cacheflush.h>
44#include <asm/portmux.h>
3dcc1e7f 45#include <mach/pll.h>
e190d6b1
BW		 46
47#include "bfin_mac.h"
48
c6dd5098 49MODULE_AUTHOR("Bryan Wu, Luke Yang");
e190d6b1
BW		 50MODULE_LICENSE("GPL");
51MODULE_DESCRIPTION(DRV_DESC);
72abb461 52MODULE_ALIAS("platform:bfin_mac");
e190d6b1
BW		 53
54#if defined(CONFIG_BFIN_MAC_USE_L1)
118133e6
SZ		 55# define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56# define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
e190d6b1 57#else
118133e6
SZ		 58# define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60# define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
e190d6b1
BW		 62#endif
63
64#define PKT_BUF_SZ 1580
65
66#define MAX_TIMEOUT_CNT 500
67
68/* pointers to maintain transmit list */
69static struct net_dma_desc_tx *tx_list_head;
70static struct net_dma_desc_tx *tx_list_tail;
71static struct net_dma_desc_rx *rx_list_head;
72static struct net_dma_desc_rx *rx_list_tail;
73static struct net_dma_desc_rx *current_rx_ptr;
74static struct net_dma_desc_tx *current_tx_ptr;
75static struct net_dma_desc_tx *tx_desc;
76static struct net_dma_desc_rx *rx_desc;
77
78static void desc_list_free(void)
79{
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
82 int i;
83#if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
85#endif
86
87 if (tx_desc) {
88 t = tx_list_head;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
90 if (t) {
91 if (t->skb) {
92 dev_kfree_skb(t->skb);
93 t->skb = NULL;
94 }
95 t = t->next;
96 }
97 }
118133e6 98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
e190d6b1
BW		 99 }
100
101 if (rx_desc) {
102 r = rx_list_head;
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
104 if (r) {
105 if (r->skb) {
106 dev_kfree_skb(r->skb);
107 r->skb = NULL;
108 }
109 r = r->next;
110 }
111 }
118133e6 112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
e190d6b1
BW		 113 }
114}
115
1ab0d2ec 116static int desc_list_init(struct net_device *dev)
e190d6b1
BW		 117{
118 int i;
119 struct sk_buff *new_skb;
120#if !defined(CONFIG_BFIN_MAC_USE_L1)
121 /*
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
124 */
125 dma_addr_t dma_handle;
126#endif
127
128 tx_desc = bfin_mac_alloc(&dma_handle,
118133e6 129 sizeof(struct net_dma_desc_tx),
e190d6b1
BW		 130 CONFIG_BFIN_TX_DESC_NUM);
131 if (tx_desc == NULL)
132 goto init_error;
133
134 rx_desc = bfin_mac_alloc(&dma_handle,
118133e6 135 sizeof(struct net_dma_desc_rx),
e190d6b1
BW		 136 CONFIG_BFIN_RX_DESC_NUM);
137 if (rx_desc == NULL)
138 goto init_error;
139
140 /* init tx_list */
141 tx_list_head = tx_list_tail = tx_desc;
142
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
147
148 /*
149 * disable DMA
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
153 * large desc flow
154 */
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
157 a->x_count = 0;
158 a->next_dma_desc = b;
159
160 /*
161 * enabled DMA
162 * write to memory WNR = 1
163 * wordsize is 32 bits
164 * disable interrupt
165 * 6 half words is desc size
166 * large desc flow
167 */
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
170 b->x_count = 0;
171
172 t->skb = NULL;
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
175 tx_list_tail = t;
176 }
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
180
181 /* init rx_list */
182 rx_list_head = rx_list_tail = rx_desc;
183
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
188
189 /* allocate a new skb for next time receive */
1ab0d2ec 190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
720a43ef 191 if (!new_skb)
e190d6b1 192 goto init_error;
720a43ef 193
015dac88 194 skb_reserve(new_skb, NET_IP_ALIGN);
f6e1e4f3
SZ		 195 /* Invidate the data cache of skb->data range when it is write back
196 * cache. It will prevent overwritting the new data from DMA
197 */
198 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
199 (unsigned long)new_skb->end);
e190d6b1
BW		 200 r->skb = new_skb;
201
202 /*
203 * enabled DMA
204 * write to memory WNR = 1
205 * wordsize is 32 bits
206 * disable interrupt
207 * 6 half words is desc size
208 * large desc flow
209 */
210 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
211 /* since RXDWA is enabled */
212 a->start_addr = (unsigned long)new_skb->data - 2;
213 a->x_count = 0;
214 a->next_dma_desc = b;
215
216 /*
217 * enabled DMA
218 * write to memory WNR = 1
219 * wordsize is 32 bits
220 * enable interrupt
221 * 6 half words is desc size
222 * large desc flow
223 */
224 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
225 NDSIZE_6 | DMAFLOW_LARGE;
226 b->start_addr = (unsigned long)(&(r->status));
227 b->x_count = 0;
228
229 rx_list_tail->desc_b.next_dma_desc = a;
230 rx_list_tail->next = r;
231 rx_list_tail = r;
232 }
233 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
234 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
235 current_rx_ptr = rx_list_head;
236
237 return 0;
238
239init_error:
240 desc_list_free();
c6dd5098 241 pr_err("kmalloc failed\n");
e190d6b1
BW		 242 return -ENOMEM;
243}
244
245
246/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
247
4ae5a3ad
BW		 248/*
249 * MII operations
250 */
e190d6b1 251/* Wait until the previous MDC/MDIO transaction has completed */
2bfa0f0c 252static int bfin_mdio_poll(void)
e190d6b1
BW		 253{
254 int timeout_cnt = MAX_TIMEOUT_CNT;
255
256 /* poll the STABUSY bit */
257 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
6db9e461 258 udelay(1);
e190d6b1 259 if (timeout_cnt-- < 0) {
c6dd5098 260 pr_err("wait MDC/MDIO transaction to complete timeout\n");
2bfa0f0c 261 return -ETIMEDOUT;
e190d6b1
BW		 262 }
263 }
2bfa0f0c
MF		 264
265 return 0;
e190d6b1
BW		 266}
267
268/* Read an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e 269static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
e190d6b1 270{
2bfa0f0c
MF		 271 int ret;
272
273 ret = bfin_mdio_poll();
274 if (ret)
275 return ret;
4ae5a3ad 276
e190d6b1 277 /* read mode */
4ae5a3ad
BW		 278 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
279 SET_REGAD((u16) regnum) |
e190d6b1 280 STABUSY);
e190d6b1 281
2bfa0f0c
MF		 282 ret = bfin_mdio_poll();
283 if (ret)
284 return ret;
4ae5a3ad
BW		 285
286 return (int) bfin_read_EMAC_STADAT();
e190d6b1
BW		 287}
288
289/* Write an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e
AB		 290static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
291 u16 value)
e190d6b1 292{
2bfa0f0c
MF		 293 int ret;
294
295 ret = bfin_mdio_poll();
296 if (ret)
297 return ret;
4ae5a3ad
BW		 298
299 bfin_write_EMAC_STADAT((u32) value);
e190d6b1
BW		 300
301 /* write mode */
4ae5a3ad
BW		 302 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303 SET_REGAD((u16) regnum) |
e190d6b1
BW		 304 STAOP |
305 STABUSY);
306
2bfa0f0c 307 return bfin_mdio_poll();
e190d6b1
BW		 308}
309
7ef0a7ee 310static void bfin_mac_adjust_link(struct net_device *dev)
e190d6b1 311{
7ef0a7ee 312 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 313 struct phy_device *phydev = lp->phydev;
314 unsigned long flags;
315 int new_state = 0;
316
317 spin_lock_irqsave(&lp->lock, flags);
318 if (phydev->link) {
319 /* Now we make sure that we can be in full duplex mode.
320 * If not, we operate in half-duplex mode. */
321 if (phydev->duplex != lp->old_duplex) {
322 u32 opmode = bfin_read_EMAC_OPMODE();
323 new_state = 1;
324
325 if (phydev->duplex)
326 opmode |= FDMODE;
327 else
328 opmode &= ~(FDMODE);
329
330 bfin_write_EMAC_OPMODE(opmode);
331 lp->old_duplex = phydev->duplex;
332 }
e190d6b1 333
4ae5a3ad 334 if (phydev->speed != lp->old_speed) {
02460d08
SZ		 335 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
336 u32 opmode = bfin_read_EMAC_OPMODE();
337 switch (phydev->speed) {
338 case 10:
339 opmode |= RMII_10;
340 break;
341 case 100:
342 opmode &= ~RMII_10;
343 break;
344 default:
c6dd5098
MF		 345 netdev_warn(dev,
346 "Ack! Speed (%d) is not 10/100!\n",
347 phydev->speed);
02460d08
SZ		 348 break;
349 }
350 bfin_write_EMAC_OPMODE(opmode);
4ae5a3ad 351 }
e190d6b1 352
4ae5a3ad
BW		 353 new_state = 1;
354 lp->old_speed = phydev->speed;
355 }
e190d6b1 356
4ae5a3ad
BW		 357 if (!lp->old_link) {
358 new_state = 1;
359 lp->old_link = 1;
4ae5a3ad
BW		 360 }
361 } else if (lp->old_link) {
362 new_state = 1;
363 lp->old_link = 0;
364 lp->old_speed = 0;
365 lp->old_duplex = -1;
e190d6b1
BW		 366 }
367
4ae5a3ad
BW		 368 if (new_state) {
369 u32 opmode = bfin_read_EMAC_OPMODE();
370 phy_print_status(phydev);
371 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
e190d6b1 372 }
4ae5a3ad
BW		 373
374 spin_unlock_irqrestore(&lp->lock, flags);
e190d6b1
BW		 375}
376
7cc8f381
BW		 377/* MDC = 2.5 MHz */
378#define MDC_CLK 2500000
379
02460d08 380static int mii_probe(struct net_device *dev, int phy_mode)
e190d6b1 381{
7ef0a7ee 382 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 383 struct phy_device *phydev = NULL;
384 unsigned short sysctl;
385 int i;
7cc8f381 386 u32 sclk, mdc_div;
e190d6b1 387
4ae5a3ad 388 /* Enable PHY output early */
98f672ca
MF		 389 if (!(bfin_read_VR_CTL() & CLKBUFOE))
390 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
e190d6b1 391
7cc8f381
BW		 392 sclk = get_sclk();
393 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
394
4ae5a3ad 395 sysctl = bfin_read_EMAC_SYSCTL();
9dc7f30e 396 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
e190d6b1 397 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1 398
02460d08
SZ		 399 /* search for connected PHY device */
400 for (i = 0; i < PHY_MAX_ADDR; ++i) {
053842a8
SM		 401 struct phy_device *const tmp_phydev =
402 mdiobus_get_phy(lp->mii_bus, i);
e190d6b1 403
4ae5a3ad
BW		 404 if (!tmp_phydev)
405 continue; /* no PHY here... */
e190d6b1 406
4ae5a3ad
BW		 407 phydev = tmp_phydev;
408 break; /* found it */
409 }
410
411 /* now we are supposed to have a proper phydev, to attach to... */
412 if (!phydev) {
c6dd5098 413 netdev_err(dev, "no phy device found\n");
4ae5a3ad 414 return -ENODEV;
e190d6b1
BW		 415 }
416
02460d08
SZ		 417 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
418 phy_mode != PHY_INTERFACE_MODE_MII) {
c6dd5098 419 netdev_err(dev, "invalid phy interface mode\n");
02460d08
SZ		 420 return -EINVAL;
421 }
422
84eff6d1 423 phydev = phy_connect(dev, phydev_name(phydev),
f9a8f83b 424 &bfin_mac_adjust_link, phy_mode);
e190d6b1 425
4ae5a3ad 426 if (IS_ERR(phydev)) {
c6dd5098 427 netdev_err(dev, "could not attach PHY\n");
4ae5a3ad
BW		 428 return PTR_ERR(phydev);
429 }
430
431 /* mask with MAC supported features */
432 phydev->supported &= (SUPPORTED_10baseT_Half
433 | SUPPORTED_10baseT_Full
434 | SUPPORTED_100baseT_Half
435 | SUPPORTED_100baseT_Full
436 | SUPPORTED_Autoneg
437 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
438 | SUPPORTED_MII
439 | SUPPORTED_TP);
440
441 phydev->advertising = phydev->supported;
442
443 lp->old_link = 0;
444 lp->old_speed = 0;
445 lp->old_duplex = -1;
446 lp->phydev = phydev;
447
2220943a
AL		 448 phy_attached_print(phydev, "mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
449 MDC_CLK, mdc_div, sclk / 1000000);
4ae5a3ad
BW		 450
451 return 0;
452}
453
679dce39
BW		 454/*
455 * Ethtool support
456 */
457
53fd3f28
MH		 458/*
459 * interrupt routine for magic packet wakeup
460 */
461static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
462{
463 return IRQ_HANDLED;
464}
465
679dce39
BW		 466static int
467bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
468{
469 struct bfin_mac_local *lp = netdev_priv(dev);
470
471 if (lp->phydev)
472 return phy_ethtool_gset(lp->phydev, cmd);
473
474 return -EINVAL;
475}
476
477static int
478bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
479{
480 struct bfin_mac_local *lp = netdev_priv(dev);
481
482 if (!capable(CAP_NET_ADMIN))
483 return -EPERM;
484
485 if (lp->phydev)
486 return phy_ethtool_sset(lp->phydev, cmd);
487
488 return -EINVAL;
489}
490
491static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
492 struct ethtool_drvinfo *info)
493{
7826d43f
JP		 494 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
495 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
496 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
497 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
679dce39
BW		 498}
499
53fd3f28
MH		 500static void bfin_mac_ethtool_getwol(struct net_device *dev,
501 struct ethtool_wolinfo *wolinfo)
502{
503 struct bfin_mac_local *lp = netdev_priv(dev);
504
505 wolinfo->supported = WAKE_MAGIC;
506 wolinfo->wolopts = lp->wol;
507}
508
509static int bfin_mac_ethtool_setwol(struct net_device *dev,
510 struct ethtool_wolinfo *wolinfo)
511{
512 struct bfin_mac_local *lp = netdev_priv(dev);
513 int rc;
514
515 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
516 WAKE_UCAST |
517 WAKE_MCAST |
518 WAKE_BCAST |
519 WAKE_ARP))
520 return -EOPNOTSUPP;
521
522 lp->wol = wolinfo->wolopts;
523
524 if (lp->wol && !lp->irq_wake_requested) {
525 /* register wake irq handler */
526 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
63aca0f7 527 0, "EMAC_WAKE", dev);
53fd3f28
MH		 528 if (rc)
529 return rc;
530 lp->irq_wake_requested = true;
531 }
532
533 if (!lp->wol && lp->irq_wake_requested) {
534 free_irq(IRQ_MAC_WAKEDET, dev);
535 lp->irq_wake_requested = false;
536 }
537
538 /* Make sure the PHY driver doesn't suspend */
539 device_init_wakeup(&dev->dev, lp->wol);
540
541 return 0;
542}
543
85c153d2 544#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
a85bbddd 545static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
3ffa4290 546 struct ethtool_ts_info *info)
a85bbddd 547{
dd87b22f
RC		 548 struct bfin_mac_local *lp = netdev_priv(dev);
549
a85bbddd
RC		 550 info->so_timestamping =
551 SOF_TIMESTAMPING_TX_HARDWARE |
552 SOF_TIMESTAMPING_RX_HARDWARE |
bc3c5f63 553 SOF_TIMESTAMPING_RAW_HARDWARE;
dd87b22f 554 info->phc_index = lp->phc_index;
a85bbddd
RC		 555 info->tx_types =
556 (1 << HWTSTAMP_TX_OFF) |
557 (1 << HWTSTAMP_TX_ON);
558 info->rx_filters =
559 (1 << HWTSTAMP_FILTER_NONE) |
560 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
561 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
562 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
563 return 0;
564}
85c153d2 565#endif
a85bbddd 566
0fc0b732 567static const struct ethtool_ops bfin_mac_ethtool_ops = {
679dce39
BW		 568 .get_settings = bfin_mac_ethtool_getsettings,
569 .set_settings = bfin_mac_ethtool_setsettings,
570 .get_link = ethtool_op_get_link,
571 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
53fd3f28
MH		 572 .get_wol = bfin_mac_ethtool_getwol,
573 .set_wol = bfin_mac_ethtool_setwol,
85c153d2 574#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
a85bbddd 575 .get_ts_info = bfin_mac_ethtool_get_ts_info,
85c153d2 576#endif
679dce39
BW		 577};
578
4ae5a3ad 579/**************************************************************************/
5ca1bb5a 580static void setup_system_regs(struct net_device *dev)
4ae5a3ad 581{
02460d08
SZ		 582 struct bfin_mac_local *lp = netdev_priv(dev);
583 int i;
4ae5a3ad
BW		 584 unsigned short sysctl;
585
586 /*
587 * Odd word alignment for Receive Frame DMA word
588 * Configure checksum support and rcve frame word alignment
589 */
590 sysctl = bfin_read_EMAC_SYSCTL();
02460d08
SZ		 591 /*
592 * check if interrupt is requested for any PHY,
593 * enable PHY interrupt only if needed
594 */
595 for (i = 0; i < PHY_MAX_ADDR; ++i)
596 if (lp->mii_bus->irq[i] != PHY_POLL)
597 break;
598 if (i < PHY_MAX_ADDR)
599 sysctl |= PHYIE;
812a9de7 600 sysctl |= RXDWA;
4ae5a3ad 601#if defined(BFIN_MAC_CSUM_OFFLOAD)
812a9de7 602 sysctl |= RXCKS;
4ae5a3ad 603#else
812a9de7 604 sysctl &= ~RXCKS;
4ae5a3ad
BW		 605#endif
606 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1
BW		 607
608 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
609
c599bd6b
MF		 610 /* Set vlan regs to let 1522 bytes long packets pass through */
611 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
612 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
613
e190d6b1
BW		 614 /* Initialize the TX DMA channel registers */
615 bfin_write_DMA2_X_COUNT(0);
616 bfin_write_DMA2_X_MODIFY(4);
617 bfin_write_DMA2_Y_COUNT(0);
618 bfin_write_DMA2_Y_MODIFY(0);
619
620 /* Initialize the RX DMA channel registers */
621 bfin_write_DMA1_X_COUNT(0);
622 bfin_write_DMA1_X_MODIFY(4);
623 bfin_write_DMA1_Y_COUNT(0);
624 bfin_write_DMA1_Y_MODIFY(0);
625}
626
73f83182 627static void setup_mac_addr(u8 *mac_addr)
e190d6b1
BW		 628{
629 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
630 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
631
632 /* this depends on a little-endian machine */
633 bfin_write_EMAC_ADDRLO(addr_low);
634 bfin_write_EMAC_ADDRHI(addr_hi);
635}
636
7ef0a7ee 637static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
73f83182
AL		 638{
639 struct sockaddr *addr = p;
640 if (netif_running(dev))
641 return -EBUSY;
642 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
643 setup_mac_addr(dev->dev_addr);
644 return 0;
645}
646
fe92afed
BS		 647#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
648#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
649
bc3c5f63
RC		 650static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
651{
652 u32 ipn = 1000000000UL / input_clk;
653 u32 ppn = 1;
654 unsigned int shift = 0;
655
656 while (ppn <= ipn) {
657 ppn <<= 1;
658 shift++;
659 }
660 *shift_result = shift;
661 return 1000000000UL / ppn;
662}
663
7575c917
BH		 664static int bfin_mac_hwtstamp_set(struct net_device *netdev,
665 struct ifreq *ifr)
fe92afed
BS		 666{
667 struct hwtstamp_config config;
668 struct bfin_mac_local *lp = netdev_priv(netdev);
669 u16 ptpctl;
670 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
671
672 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
673 return -EFAULT;
674
675 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
676 __func__, config.flags, config.tx_type, config.rx_filter);
677
678 /* reserved for future extensions */
679 if (config.flags)
680 return -EINVAL;
681
682 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
683 (config.tx_type != HWTSTAMP_TX_ON))
684 return -ERANGE;
685
686 ptpctl = bfin_read_EMAC_PTP_CTL();
687
688 switch (config.rx_filter) {
689 case HWTSTAMP_FILTER_NONE:
690 /*
691 * Dont allow any timestamping
692 */
693 ptpfv3 = 0xFFFFFFFF;
694 bfin_write_EMAC_PTP_FV3(ptpfv3);
695 break;
696 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
697 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
698 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
699 /*
700 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
701 * to enable all the field matches.
702 */
703 ptpctl &= ~0x1F00;
704 bfin_write_EMAC_PTP_CTL(ptpctl);
705 /*
706 * Keep the default values of the EMAC_PTP_FOFF register.
707 */
708 ptpfoff = 0x4A24170C;
709 bfin_write_EMAC_PTP_FOFF(ptpfoff);
710 /*
711 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
712 * registers.
713 */
714 ptpfv1 = 0x11040800;
715 bfin_write_EMAC_PTP_FV1(ptpfv1);
716 ptpfv2 = 0x0140013F;
717 bfin_write_EMAC_PTP_FV2(ptpfv2);
718 /*
719 * The default value (0xFFFC) allows the timestamping of both
720 * received Sync messages and Delay_Req messages.
721 */
722 ptpfv3 = 0xFFFFFFFC;
723 bfin_write_EMAC_PTP_FV3(ptpfv3);
724
725 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
726 break;
727 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
728 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
729 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
730 /* Clear all five comparison mask bits (bits[12:8]) in the
731 * EMAC_PTP_CTL register to enable all the field matches.
732 */
733 ptpctl &= ~0x1F00;
734 bfin_write_EMAC_PTP_CTL(ptpctl);
735 /*
736 * Keep the default values of the EMAC_PTP_FOFF register, except set
737 * the PTPCOF field to 0x2A.
738 */
739 ptpfoff = 0x2A24170C;
740 bfin_write_EMAC_PTP_FOFF(ptpfoff);
741 /*
742 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
743 * registers.
744 */
745 ptpfv1 = 0x11040800;
746 bfin_write_EMAC_PTP_FV1(ptpfv1);
747 ptpfv2 = 0x0140013F;
748 bfin_write_EMAC_PTP_FV2(ptpfv2);
749 /*
750 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
751 * the value to 0xFFF0.
752 */
753 ptpfv3 = 0xFFFFFFF0;
754 bfin_write_EMAC_PTP_FV3(ptpfv3);
755
756 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
757 break;
758 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
759 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
760 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
761 /*
762 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
763 * EFTM and PTPCM field comparison.
764 */
765 ptpctl &= ~0x1100;
766 bfin_write_EMAC_PTP_CTL(ptpctl);
767 /*
768 * Keep the default values of all the fields of the EMAC_PTP_FOFF
769 * register, except set the PTPCOF field to 0x0E.
770 */
771 ptpfoff = 0x0E24170C;
772 bfin_write_EMAC_PTP_FOFF(ptpfoff);
773 /*
774 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
775 * corresponds to PTP messages on the MAC layer.
776 */
777 ptpfv1 = 0x110488F7;
778 bfin_write_EMAC_PTP_FV1(ptpfv1);
779 ptpfv2 = 0x0140013F;
780 bfin_write_EMAC_PTP_FV2(ptpfv2);
781 /*
782 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
783 * messages, set the value to 0xFFF0.
784 */
785 ptpfv3 = 0xFFFFFFF0;
786 bfin_write_EMAC_PTP_FV3(ptpfv3);
787
788 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
789 break;
790 default:
791 return -ERANGE;
792 }
793
794 if (config.tx_type == HWTSTAMP_TX_OFF &&
795 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
796 ptpctl &= ~PTP_EN;
797 bfin_write_EMAC_PTP_CTL(ptpctl);
798
799 SSYNC();
800 } else {
801 ptpctl |= PTP_EN;
802 bfin_write_EMAC_PTP_CTL(ptpctl);
803
804 /*
805 * clear any existing timestamp
806 */
807 bfin_read_EMAC_PTP_RXSNAPLO();
808 bfin_read_EMAC_PTP_RXSNAPHI();
809
810 bfin_read_EMAC_PTP_TXSNAPLO();
811 bfin_read_EMAC_PTP_TXSNAPHI();
812
fe92afed 813 SSYNC();
fe92afed
BS		 814 }
815
816 lp->stamp_cfg = config;
817 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
818 -EFAULT : 0;
819}
820
7575c917
BH		 821static int bfin_mac_hwtstamp_get(struct net_device *netdev,
822 struct ifreq *ifr)
823{
824 struct bfin_mac_local *lp = netdev_priv(netdev);
825
826 return copy_to_user(ifr->ifr_data, &lp->stamp_cfg,
827 sizeof(lp->stamp_cfg)) ?
828 -EFAULT : 0;
829}
830
fe92afed
BS		 831static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
832{
833 struct bfin_mac_local *lp = netdev_priv(netdev);
fe92afed 834
2244d07b 835 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
fe92afed
BS		 836 int timeout_cnt = MAX_TIMEOUT_CNT;
837
838 /* When doing time stamping, keep the connection to the socket
839 * a while longer
840 */
2244d07b 841 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
fe92afed
BS		 842
843 /*
844 * The timestamping is done at the EMAC module's MII/RMII interface
845 * when the module sees the Start of Frame of an event message packet. This
846 * interface is the closest possible place to the physical Ethernet transmission
847 * medium, providing the best timing accuracy.
848 */
849 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
850 udelay(1);
851 if (timeout_cnt == 0)
c6dd5098 852 netdev_err(netdev, "timestamp the TX packet failed\n");
fe92afed
BS		 853 else {
854 struct skb_shared_hwtstamps shhwtstamps;
855 u64 ns;
856 u64 regval;
857
858 regval = bfin_read_EMAC_PTP_TXSNAPLO();
859 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
860 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
bc3c5f63 861 ns = regval << lp->shift;
fe92afed 862 shhwtstamps.hwtstamp = ns_to_ktime(ns);
fe92afed 863 skb_tstamp_tx(skb, &shhwtstamps);
fe92afed
BS		 864 }
865 }
866}
867
868static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
869{
870 struct bfin_mac_local *lp = netdev_priv(netdev);
871 u32 valid;
872 u64 regval, ns;
873 struct skb_shared_hwtstamps *shhwtstamps;
874
875 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
876 return;
877
878 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
879 if (!valid)
880 return;
881
882 shhwtstamps = skb_hwtstamps(skb);
883
884 regval = bfin_read_EMAC_PTP_RXSNAPLO();
885 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
bc3c5f63 886 ns = regval << lp->shift;
fe92afed
BS		 887 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
888 shhwtstamps->hwtstamp = ns_to_ktime(ns);
fe92afed
BS		 889}
890
fe92afed
BS		 891static void bfin_mac_hwtstamp_init(struct net_device *netdev)
892{
893 struct bfin_mac_local *lp = netdev_priv(netdev);
dd87b22f 894 u64 addend, ppb;
bc3c5f63 895 u32 input_clk, phc_clk;
fe92afed
BS		 896
897 /* Initialize hardware timer */
bc3c5f63
RC		 898 input_clk = get_sclk();
899 phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
900 addend = phc_clk * (1ULL << 32);
901 do_div(addend, input_clk);
902 bfin_write_EMAC_PTP_ADDEND((u32)addend);
903
904 lp->addend = addend;
dd87b22f
RC		 905 ppb = 1000000000ULL * input_clk;
906 do_div(ppb, phc_clk);
907 lp->max_ppb = ppb - 1000000000ULL - 1ULL;
fe92afed
BS		 908
909 /* Initialize hwstamp config */
910 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
911 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
912}
913
dd87b22f
RC		 914static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
915{
916 u64 ns;
917 u32 lo, hi;
918
919 lo = bfin_read_EMAC_PTP_TIMELO();
920 hi = bfin_read_EMAC_PTP_TIMEHI();
921
922 ns = ((u64) hi) << 32;
923 ns |= lo;
924 ns <<= lp->shift;
925
926 return ns;
927}
928
929static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
930{
931 u32 hi, lo;
932
933 ns >>= lp->shift;
934 hi = ns >> 32;
935 lo = ns & 0xffffffff;
936
937 bfin_write_EMAC_PTP_TIMELO(lo);
938 bfin_write_EMAC_PTP_TIMEHI(hi);
939}
940
941/* PTP Hardware Clock operations */
942
943static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
944{
945 u64 adj;
946 u32 diff, addend;
947 int neg_adj = 0;
948 struct bfin_mac_local *lp =
949 container_of(ptp, struct bfin_mac_local, caps);
950
951 if (ppb < 0) {
952 neg_adj = 1;
953 ppb = -ppb;
954 }
955 addend = lp->addend;
956 adj = addend;
957 adj *= ppb;
958 diff = div_u64(adj, 1000000000ULL);
959
960 addend = neg_adj ? addend - diff : addend + diff;
961
962 bfin_write_EMAC_PTP_ADDEND(addend);
963
964 return 0;
965}
966
967static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
968{
969 s64 now;
970 unsigned long flags;
971 struct bfin_mac_local *lp =
972 container_of(ptp, struct bfin_mac_local, caps);
973
974 spin_lock_irqsave(&lp->phc_lock, flags);
975
976 now = bfin_ptp_time_read(lp);
977 now += delta;
978 bfin_ptp_time_write(lp, now);
979
980 spin_unlock_irqrestore(&lp->phc_lock, flags);
981
982 return 0;
983}
984
20ca7fb6 985static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
dd87b22f
RC		 986{
987 u64 ns;
dd87b22f
RC		 988 unsigned long flags;
989 struct bfin_mac_local *lp =
990 container_of(ptp, struct bfin_mac_local, caps);
991
992 spin_lock_irqsave(&lp->phc_lock, flags);
993
994 ns = bfin_ptp_time_read(lp);
995
996 spin_unlock_irqrestore(&lp->phc_lock, flags);
997
96ff1c37
RC		 998 *ts = ns_to_timespec64(ns);
999
dd87b22f
RC		 1000 return 0;
1001}
1002
1003static int bfin_ptp_settime(struct ptp_clock_info *ptp,
20ca7fb6 1004 const struct timespec64 *ts)
dd87b22f
RC		 1005{
1006 u64 ns;
1007 unsigned long flags;
1008 struct bfin_mac_local *lp =
1009 container_of(ptp, struct bfin_mac_local, caps);
1010
96ff1c37 1011 ns = timespec64_to_ns(ts);
dd87b22f
RC		 1012
1013 spin_lock_irqsave(&lp->phc_lock, flags);
1014
1015 bfin_ptp_time_write(lp, ns);
1016
1017 spin_unlock_irqrestore(&lp->phc_lock, flags);
1018
1019 return 0;
1020}
1021
1022static int bfin_ptp_enable(struct ptp_clock_info *ptp,
1023 struct ptp_clock_request *rq, int on)
1024{
1025 return -EOPNOTSUPP;
1026}
1027
1028static struct ptp_clock_info bfin_ptp_caps = {
1029 .owner = THIS_MODULE,
1030 .name = "BF518 clock",
1031 .max_adj = 0,
1032 .n_alarm = 0,
1033 .n_ext_ts = 0,
1034 .n_per_out = 0,
4986b4f0 1035 .n_pins = 0,
dd87b22f
RC		 1036 .pps = 0,
1037 .adjfreq = bfin_ptp_adjfreq,
1038 .adjtime = bfin_ptp_adjtime,
20ca7fb6
RC		 1039 .gettime64 = bfin_ptp_gettime,
1040 .settime64 = bfin_ptp_settime,
dd87b22f
RC		 1041 .enable = bfin_ptp_enable,
1042};
1043
1044static int bfin_phc_init(struct net_device *netdev, struct device *dev)
1045{
1046 struct bfin_mac_local *lp = netdev_priv(netdev);
1047
1048 lp->caps = bfin_ptp_caps;
1049 lp->caps.max_adj = lp->max_ppb;
1050 lp->clock = ptp_clock_register(&lp->caps, dev);
1051 if (IS_ERR(lp->clock))
1052 return PTR_ERR(lp->clock);
1053
1054 lp->phc_index = ptp_clock_index(lp->clock);
1055 spin_lock_init(&lp->phc_lock);
1056
1057 return 0;
1058}
1059
1060static void bfin_phc_release(struct bfin_mac_local *lp)
1061{
1062 ptp_clock_unregister(lp->clock);
1063}
1064
fe92afed
BS		 1065#else
1066# define bfin_mac_hwtstamp_is_none(cfg) 0
1067# define bfin_mac_hwtstamp_init(dev)
7575c917
BH		 1068# define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP)
1069# define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP)
fe92afed
BS		 1070# define bfin_rx_hwtstamp(dev, skb)
1071# define bfin_tx_hwtstamp(dev, skb)
dd87b22f
RC		 1072# define bfin_phc_init(netdev, dev) 0
1073# define bfin_phc_release(lp)
fe92afed
BS		 1074#endif
1075
4fcc3d34
SZ		 1076static inline void _tx_reclaim_skb(void)
1077{
1078 do {
1079 tx_list_head->desc_a.config &= ~DMAEN;
1080 tx_list_head->status.status_word = 0;
1081 if (tx_list_head->skb) {
21534d20 1082 dev_consume_skb_any(tx_list_head->skb);
4fcc3d34
SZ		 1083 tx_list_head->skb = NULL;
1084 }
1085 tx_list_head = tx_list_head->next;
1086
1087 } while (tx_list_head->status.status_word != 0);
1088}
1089
1090static void tx_reclaim_skb(struct bfin_mac_local *lp)
e190d6b1
BW		 1091{
1092 int timeout_cnt = MAX_TIMEOUT_CNT;
1093
4fcc3d34
SZ		 1094 if (tx_list_head->status.status_word != 0)
1095 _tx_reclaim_skb();
e190d6b1 1096
4fcc3d34 1097 if (current_tx_ptr->next == tx_list_head) {
e190d6b1 1098 while (tx_list_head->status.status_word == 0) {
4fcc3d34 1099 /* slow down polling to avoid too many queue stop. */
015dac88 1100 udelay(10);
4fcc3d34
SZ		 1101 /* reclaim skb if DMA is not running. */
1102 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
1103 break;
1104 if (timeout_cnt-- < 0)
e190d6b1 1105 break;
e190d6b1 1106 }
4fcc3d34
SZ		 1107
1108 if (timeout_cnt >= 0)
1109 _tx_reclaim_skb();
1110 else
1111 netif_stop_queue(lp->ndev);
e190d6b1
BW		 1112 }
1113
4fcc3d34
SZ		 1114 if (current_tx_ptr->next != tx_list_head &&
1115 netif_queue_stopped(lp->ndev))
1116 netif_wake_queue(lp->ndev);
1117
1118 if (tx_list_head != current_tx_ptr) {
1119 /* shorten the timer interval if tx queue is stopped */
1120 if (netif_queue_stopped(lp->ndev))
1121 lp->tx_reclaim_timer.expires =
1122 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1123 else
1124 lp->tx_reclaim_timer.expires =
1125 jiffies + TX_RECLAIM_JIFFIES;
1126
1127 mod_timer(&lp->tx_reclaim_timer,
1128 lp->tx_reclaim_timer.expires);
1129 }
e190d6b1 1130
e190d6b1 1131 return;
4fcc3d34 1132}
e190d6b1 1133
4fcc3d34
SZ		 1134static void tx_reclaim_skb_timeout(unsigned long lp)
1135{
1136 tx_reclaim_skb((struct bfin_mac_local *)lp);
e190d6b1
BW		 1137}
1138
7ef0a7ee 1139static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
e190d6b1
BW		 1140 struct net_device *dev)
1141{
4fcc3d34 1142 struct bfin_mac_local *lp = netdev_priv(dev);
a50c0c05 1143 u16 *data;
015dac88 1144 u32 data_align = (unsigned long)(skb->data) & 0x3;
fe92afed 1145
e190d6b1
BW		 1146 current_tx_ptr->skb = skb;
1147
015dac88
MH		 1148 if (data_align == 0x2) {
1149 /* move skb->data to current_tx_ptr payload */
1150 data = (u16 *)(skb->data) - 1;
fe92afed
BS		 1151 *data = (u16)(skb->len);
1152 /*
1153 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1154 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1155 * of this field are the length of the packet payload in bytes and the higher
1156 * 4 bits are the timestamping enable field.
1157 */
2244d07b 1158 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed
BS		 1159 *data |= 0x1000;
1160
015dac88
MH		 1161 current_tx_ptr->desc_a.start_addr = (u32)data;
1162 /* this is important! */
1163 blackfin_dcache_flush_range((u32)data,
1164 (u32)((u8 *)data + skb->len + 4));
e190d6b1 1165 } else {
015dac88 1166 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
fe92afed 1167 /* enable timestamping for the sent packet */
2244d07b 1168 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed 1169 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
015dac88
MH		 1170 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1171 skb->len);
1172 current_tx_ptr->desc_a.start_addr =
1173 (u32)current_tx_ptr->packet;
015dac88
MH		 1174 blackfin_dcache_flush_range(
1175 (u32)current_tx_ptr->packet,
1176 (u32)(current_tx_ptr->packet + skb->len + 2));
e190d6b1
BW		 1177 }
1178
805a8ab3
SZ		 1179 /* make sure the internal data buffers in the core are drained
1180 * so that the DMA descriptors are completely written when the
1181 * DMA engine goes to fetch them below
1182 */
1183 SSYNC();
1184
4fcc3d34
SZ		 1185 /* always clear status buffer before start tx dma */
1186 current_tx_ptr->status.status_word = 0;
1187
e190d6b1
BW		 1188 /* enable this packet's dma */
1189 current_tx_ptr->desc_a.config |= DMAEN;
1190
1191 /* tx dma is running, just return */
015dac88 1192 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
e190d6b1
BW		 1193 goto out;
1194
1195 /* tx dma is not running */
1196 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1197 /* dma enabled, read from memory, size is 6 */
1198 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1199 /* Turn on the EMAC tx */
1200 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1201
1202out:
fe92afed
BS		 1203 bfin_tx_hwtstamp(dev, skb);
1204
e190d6b1 1205 current_tx_ptr = current_tx_ptr->next;
09f75cd7
JG		 1206 dev->stats.tx_packets++;
1207 dev->stats.tx_bytes += (skb->len);
4fcc3d34
SZ		 1208
1209 tx_reclaim_skb(lp);
1210
6ed10654 1211 return NETDEV_TX_OK;
e190d6b1
BW		 1212}
1213
ad2864d8 1214#define IP_HEADER_OFF 0
ec497b32
PM		 1215#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1216 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1217
159945af 1218static void bfin_mac_rx(struct bfin_mac_local *lp)
e190d6b1 1219{
159945af 1220 struct net_device *dev = lp->ndev;
e190d6b1 1221 struct sk_buff *skb, *new_skb;
e190d6b1 1222 unsigned short len;
ad2864d8
SZ		 1223#if defined(BFIN_MAC_CSUM_OFFLOAD)
1224 unsigned int i;
1225 unsigned char fcs[ETH_FCS_LEN + 1];
1226#endif
e190d6b1 1227
ec497b32
PM		 1228 /* check if frame status word reports an error condition
1229 * we which case we simply drop the packet
1230 */
1231 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
c6dd5098 1232 netdev_notice(dev, "rx: receive error - packet dropped\n");
ec497b32
PM		 1233 dev->stats.rx_dropped++;
1234 goto out;
1235 }
1236
e190d6b1
BW		 1237 /* allocate a new skb for next time receive */
1238 skb = current_rx_ptr->skb;
fe92afed 1239
1ab0d2ec 1240 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1 1241 if (!new_skb) {
09f75cd7 1242 dev->stats.rx_dropped++;
e190d6b1
BW		 1243 goto out;
1244 }
1245 /* reserve 2 bytes for RXDWA padding */
015dac88 1246 skb_reserve(new_skb, NET_IP_ALIGN);
6e01d1a4
AD		 1247 /* Invidate the data cache of skb->data range when it is write back
1248 * cache. It will prevent overwritting the new data from DMA
1249 */
1250 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1251 (unsigned long)new_skb->end);
1252
f6e1e4f3
SZ		 1253 current_rx_ptr->skb = new_skb;
1254 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1255
159945af 1256 len = (unsigned short)(current_rx_ptr->status.status_word & RX_FRLEN);
ad2864d8
SZ		 1257 /* Deduce Ethernet FCS length from Ethernet payload length */
1258 len -= ETH_FCS_LEN;
e190d6b1 1259 skb_put(skb, len);
e190d6b1 1260
e190d6b1 1261 skb->protocol = eth_type_trans(skb, dev);
fe92afed
BS		 1262
1263 bfin_rx_hwtstamp(dev, skb);
1264
e190d6b1 1265#if defined(BFIN_MAC_CSUM_OFFLOAD)
ad2864d8
SZ		 1266 /* Checksum offloading only works for IPv4 packets with the standard IP header
1267 * length of 20 bytes, because the blackfin MAC checksum calculation is
1268 * based on that assumption. We must NOT use the calculated checksum if our
1269 * IP version or header break that assumption.
1270 */
1271 if (skb->data[IP_HEADER_OFF] == 0x45) {
1272 skb->csum = current_rx_ptr->status.ip_payload_csum;
1273 /*
1274 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1275 * IP checksum is based on 16-bit one's complement algorithm.
1276 * To deduce a value from checksum is equal to add its inversion.
1277 * If the IP payload len is odd, the inversed FCS should also
1278 * begin from odd address and leave first byte zero.
1279 */
1280 if (skb->len % 2) {
1281 fcs[0] = 0;
1282 for (i = 0; i < ETH_FCS_LEN; i++)
1283 fcs[i + 1] = ~skb->data[skb->len + i];
1284 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1285 } else {
1286 for (i = 0; i < ETH_FCS_LEN; i++)
1287 fcs[i] = ~skb->data[skb->len + i];
1288 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1289 }
1290 skb->ip_summed = CHECKSUM_COMPLETE;
1291 }
e190d6b1
BW		 1292#endif
1293
159945af
SZ		 1294 napi_gro_receive(&lp->napi, skb);
1295
09f75cd7
JG		 1296 dev->stats.rx_packets++;
1297 dev->stats.rx_bytes += len;
ec497b32 1298out:
e190d6b1
BW		 1299 current_rx_ptr->status.status_word = 0x00000000;
1300 current_rx_ptr = current_rx_ptr->next;
e190d6b1
BW		 1301}
1302
159945af
SZ		 1303static int bfin_mac_poll(struct napi_struct *napi, int budget)
1304{
1305 int i = 0;
1306 struct bfin_mac_local *lp = container_of(napi,
1307 struct bfin_mac_local,
1308 napi);
1309
1310 while (current_rx_ptr->status.status_word != 0 && i < budget) {
1311 bfin_mac_rx(lp);
1312 i++;
1313 }
1314
1315 if (i < budget) {
1316 napi_complete(napi);
1317 if (test_and_clear_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags))
1318 enable_irq(IRQ_MAC_RX);
1319 }
1320
1321 return i;
1322}
1323
e190d6b1 1324/* interrupt routine to handle rx and error signal */
7ef0a7ee 1325static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
e190d6b1 1326{
159945af
SZ		 1327 struct bfin_mac_local *lp = netdev_priv(dev_id);
1328 u32 status;
1329
1330 status = bfin_read_DMA1_IRQ_STATUS();
1331
1332 bfin_write_DMA1_IRQ_STATUS(status | DMA_DONE | DMA_ERR);
1333 if (status & DMA_DONE) {
1334 disable_irq_nosync(IRQ_MAC_RX);
1335 set_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags);
1336 napi_schedule(&lp->napi);
e190d6b1
BW		 1337 }
1338
159945af 1339 return IRQ_HANDLED;
e190d6b1
BW		 1340}
1341
1342#ifdef CONFIG_NET_POLL_CONTROLLER
159945af 1343static void bfin_mac_poll_controller(struct net_device *dev)
e190d6b1 1344{
4fcc3d34
SZ		 1345 struct bfin_mac_local *lp = netdev_priv(dev);
1346
7ef0a7ee 1347 bfin_mac_interrupt(IRQ_MAC_RX, dev);
4fcc3d34 1348 tx_reclaim_skb(lp);
e190d6b1
BW		 1349}
1350#endif /* CONFIG_NET_POLL_CONTROLLER */
1351
7ef0a7ee 1352static void bfin_mac_disable(void)
e190d6b1
BW		 1353{
1354 unsigned int opmode;
1355
1356 opmode = bfin_read_EMAC_OPMODE();
1357 opmode &= (~RE);
1358 opmode &= (~TE);
1359 /* Turn off the EMAC */
1360 bfin_write_EMAC_OPMODE(opmode);
1361}
1362
1363/*
1364 * Enable Interrupts, Receive, and Transmit
1365 */
02460d08 1366static int bfin_mac_enable(struct phy_device *phydev)
e190d6b1 1367{
2bfa0f0c 1368 int ret;
e190d6b1
BW		 1369 u32 opmode;
1370
c6dd5098 1371 pr_debug("%s\n", __func__);
e190d6b1
BW		 1372
1373 /* Set RX DMA */
1374 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1375 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1376
1377 /* Wait MII done */
2bfa0f0c
MF		 1378 ret = bfin_mdio_poll();
1379 if (ret)
1380 return ret;
e190d6b1
BW		 1381
1382 /* We enable only RX here */
1383 /* ASTP : Enable Automatic Pad Stripping
1384 PR : Promiscuous Mode for test
1385 PSF : Receive frames with total length less than 64 bytes.
1386 FDMODE : Full Duplex Mode
1387 LB : Internal Loopback for test
1388 RE : Receiver Enable */
1389 opmode = bfin_read_EMAC_OPMODE();
1390 if (opmode & FDMODE)
1391 opmode |= PSF;
1392 else
1393 opmode |= DRO | DC | PSF;
1394 opmode |= RE;
1395
02460d08
SZ		 1396 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1397 opmode |= RMII; /* For Now only 100MBit are supported */
72f49050
MF		 1398#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1399 if (__SILICON_REVISION__ < 3) {
1400 /*
1401 * This isn't publicly documented (fun times!), but in
1402 * silicon <=0.2, the RX and TX pins are clocked together.
1403 * So in order to recv, we must enable the transmit side
1404 * as well. This will cause a spurious TX interrupt too,
1405 * but we can easily consume that.
1406 */
1407 opmode |= TE;
1408 }
e190d6b1 1409#endif
02460d08
SZ		 1410 }
1411
e190d6b1
BW		 1412 /* Turn on the EMAC rx */
1413 bfin_write_EMAC_OPMODE(opmode);
2bfa0f0c
MF		 1414
1415 return 0;
e190d6b1
BW		 1416}
1417
1418/* Our watchdog timed out. Called by the networking layer */
7ef0a7ee 1419static void bfin_mac_timeout(struct net_device *dev)
e190d6b1 1420{
4fcc3d34
SZ		 1421 struct bfin_mac_local *lp = netdev_priv(dev);
1422
b39d66a8 1423 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1 1424
7ef0a7ee 1425 bfin_mac_disable();
e190d6b1 1426
4fcc3d34
SZ		 1427 del_timer(&lp->tx_reclaim_timer);
1428
1429 /* reset tx queue and free skb */
1430 while (tx_list_head != current_tx_ptr) {
1431 tx_list_head->desc_a.config &= ~DMAEN;
1432 tx_list_head->status.status_word = 0;
1433 if (tx_list_head->skb) {
1434 dev_kfree_skb(tx_list_head->skb);
1435 tx_list_head->skb = NULL;
1436 }
1437 tx_list_head = tx_list_head->next;
1438 }
1439
159945af
SZ		 1440 if (netif_queue_stopped(dev))
1441 netif_wake_queue(dev);
e190d6b1 1442
02460d08 1443 bfin_mac_enable(lp->phydev);
e190d6b1
BW		 1444
1445 /* We can accept TX packets again */
1ae5dc34 1446 dev->trans_start = jiffies; /* prevent tx timeout */
e190d6b1
BW		 1447}
1448
7ef0a7ee 1449static void bfin_mac_multicast_hash(struct net_device *dev)
775919bc
AW		 1450{
1451 u32 emac_hashhi, emac_hashlo;
22bedad3 1452 struct netdev_hw_addr *ha;
775919bc
AW		 1453 u32 crc;
1454
1455 emac_hashhi = emac_hashlo = 0;
1456
22bedad3 1457 netdev_for_each_mc_addr(ha, dev) {
f767b6df 1458 crc = ether_crc(ETH_ALEN, ha->addr);
775919bc
AW		 1459 crc >>= 26;
1460
1461 if (crc & 0x20)
1462 emac_hashhi |= 1 << (crc & 0x1f);
1463 else
1464 emac_hashlo |= 1 << (crc & 0x1f);
1465 }
1466
1467 bfin_write_EMAC_HASHHI(emac_hashhi);
1468 bfin_write_EMAC_HASHLO(emac_hashlo);
775919bc
AW		 1469}
1470
e190d6b1
BW		 1471/*
1472 * This routine will, depending on the values passed to it,
1473 * either make it accept multicast packets, go into
1474 * promiscuous mode (for TCPDUMP and cousins) or accept
1475 * a select set of multicast packets
1476 */
7ef0a7ee 1477static void bfin_mac_set_multicast_list(struct net_device *dev)
e190d6b1
BW		 1478{
1479 u32 sysctl;
1480
1481 if (dev->flags & IFF_PROMISC) {
c6dd5098 1482 netdev_info(dev, "set promisc mode\n");
e190d6b1 1483 sysctl = bfin_read_EMAC_OPMODE();
c0da776b 1484 sysctl |= PR;
e190d6b1 1485 bfin_write_EMAC_OPMODE(sysctl);
775919bc 1486 } else if (dev->flags & IFF_ALLMULTI) {
e190d6b1
BW		 1487 /* accept all multicast */
1488 sysctl = bfin_read_EMAC_OPMODE();
1489 sysctl |= PAM;
1490 bfin_write_EMAC_OPMODE(sysctl);
4cd24eaf 1491 } else if (!netdev_mc_empty(dev)) {
775919bc
AW		 1492 /* set up multicast hash table */
1493 sysctl = bfin_read_EMAC_OPMODE();
1494 sysctl |= HM;
1495 bfin_write_EMAC_OPMODE(sysctl);
7ef0a7ee 1496 bfin_mac_multicast_hash(dev);
e190d6b1
BW		 1497 } else {
1498 /* clear promisc or multicast mode */
1499 sysctl = bfin_read_EMAC_OPMODE();
1500 sysctl &= ~(RAF | PAM);
1501 bfin_write_EMAC_OPMODE(sysctl);
1502 }
1503}
1504
fe92afed
BS		 1505static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1506{
02460d08
SZ		 1507 struct bfin_mac_local *lp = netdev_priv(netdev);
1508
1509 if (!netif_running(netdev))
1510 return -EINVAL;
1511
fe92afed
BS		 1512 switch (cmd) {
1513 case SIOCSHWTSTAMP:
7575c917
BH		 1514 return bfin_mac_hwtstamp_set(netdev, ifr);
1515 case SIOCGHWTSTAMP:
1516 return bfin_mac_hwtstamp_get(netdev, ifr);
fe92afed 1517 default:
02460d08
SZ		 1518 if (lp->phydev)
1519 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1520 else
1521 return -EOPNOTSUPP;
fe92afed
BS		 1522 }
1523}
1524
e190d6b1
BW		 1525/*
1526 * this puts the device in an inactive state
1527 */
7ef0a7ee 1528static void bfin_mac_shutdown(struct net_device *dev)
e190d6b1
BW		 1529{
1530 /* Turn off the EMAC */
1531 bfin_write_EMAC_OPMODE(0x00000000);
1532 /* Turn off the EMAC RX DMA */
1533 bfin_write_DMA1_CONFIG(0x0000);
1534 bfin_write_DMA2_CONFIG(0x0000);
1535}
1536
1537/*
1538 * Open and Initialize the interface
1539 *
1540 * Set up everything, reset the card, etc..
1541 */
7ef0a7ee 1542static int bfin_mac_open(struct net_device *dev)
e190d6b1 1543{
7ef0a7ee 1544 struct bfin_mac_local *lp = netdev_priv(dev);
2bfa0f0c 1545 int ret;
b39d66a8 1546 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1547
1548 /*
1549 * Check that the address is valid. If its not, refuse
1550 * to bring the device up. The user must specify an
1551 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1552 */
1553 if (!is_valid_ether_addr(dev->dev_addr)) {
c6dd5098 1554 netdev_warn(dev, "no valid ethernet hw addr\n");
e190d6b1
BW		 1555 return -EINVAL;
1556 }
1557
1558 /* initial rx and tx list */
1ab0d2ec 1559 ret = desc_list_init(dev);
2bfa0f0c
MF		 1560 if (ret)
1561 return ret;
e190d6b1 1562
4ae5a3ad 1563 phy_start(lp->phydev);
e190d6b1 1564 setup_system_regs(dev);
ee02fee8 1565 setup_mac_addr(dev->dev_addr);
2bfa0f0c 1566
7ef0a7ee 1567 bfin_mac_disable();
02460d08 1568 ret = bfin_mac_enable(lp->phydev);
2bfa0f0c
MF		 1569 if (ret)
1570 return ret;
e190d6b1 1571 pr_debug("hardware init finished\n");
2bfa0f0c 1572
159945af 1573 napi_enable(&lp->napi);
e190d6b1
BW		 1574 netif_start_queue(dev);
1575 netif_carrier_on(dev);
1576
1577 return 0;
1578}
1579
1580/*
e190d6b1
BW		 1581 * this makes the board clean up everything that it can
1582 * and not talk to the outside world. Caused by
1583 * an 'ifconfig ethX down'
1584 */
7ef0a7ee 1585static int bfin_mac_close(struct net_device *dev)
e190d6b1 1586{
7ef0a7ee 1587 struct bfin_mac_local *lp = netdev_priv(dev);
b39d66a8 1588 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1589
1590 netif_stop_queue(dev);
159945af 1591 napi_disable(&lp->napi);
e190d6b1
BW		 1592 netif_carrier_off(dev);
1593
4ae5a3ad 1594 phy_stop(lp->phydev);
136492b2 1595 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
4ae5a3ad 1596
e190d6b1 1597 /* clear everything */
7ef0a7ee 1598 bfin_mac_shutdown(dev);
e190d6b1
BW		 1599
1600 /* free the rx/tx buffers */
1601 desc_list_free();
1602
1603 return 0;
1604}
1605
b63dc8fe
MF		 1606static const struct net_device_ops bfin_mac_netdev_ops = {
1607 .ndo_open = bfin_mac_open,
1608 .ndo_stop = bfin_mac_close,
1609 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1610 .ndo_set_mac_address = bfin_mac_set_mac_address,
1611 .ndo_tx_timeout = bfin_mac_timeout,
afc4b13d 1612 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
fe92afed 1613 .ndo_do_ioctl = bfin_mac_ioctl,
b63dc8fe
MF		 1614 .ndo_validate_addr = eth_validate_addr,
1615 .ndo_change_mtu = eth_change_mtu,
1616#ifdef CONFIG_NET_POLL_CONTROLLER
159945af 1617 .ndo_poll_controller = bfin_mac_poll_controller,
b63dc8fe
MF		 1618#endif
1619};
1620
49f7315b 1621static int bfin_mac_probe(struct platform_device *pdev)
e190d6b1 1622{
7ef0a7ee
BW		 1623 struct net_device *ndev;
1624 struct bfin_mac_local *lp;
080c8255 1625 struct platform_device *pd;
02460d08 1626 struct bfin_mii_bus_platform_data *mii_bus_data;
080c8255 1627 int rc;
7ef0a7ee
BW		 1628
1629 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
41de8d4c 1630 if (!ndev)
7ef0a7ee 1631 return -ENOMEM;
7ef0a7ee
BW		 1632
1633 SET_NETDEV_DEV(ndev, &pdev->dev);
1634 platform_set_drvdata(pdev, ndev);
1635 lp = netdev_priv(ndev);
4fcc3d34 1636 lp->ndev = ndev;
e190d6b1
BW		 1637
1638 /* Grab the MAC address in the MAC */
7ef0a7ee
BW		 1639 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1640 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
e190d6b1
BW		 1641
1642 /* probe mac */
1643 /*todo: how to proble? which is revision_register */
1644 bfin_write_EMAC_ADDRLO(0x12345678);
1645 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
7ef0a7ee
BW		 1646 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1647 rc = -ENODEV;
1648 goto out_err_probe_mac;
e190d6b1
BW		 1649 }
1650
e190d6b1 1651
7ef0a7ee
BW		 1652 /*
1653 * Is it valid? (Did bootloader initialize it?)
1654 * Grab the MAC from the board somehow
1655 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1656 */
5055d2f2
DK		 1657 if (!is_valid_ether_addr(ndev->dev_addr)) {
1658 if (bfin_get_ether_addr(ndev->dev_addr) ||
1659 !is_valid_ether_addr(ndev->dev_addr)) {
1660 /* Still not valid, get a random one */
1661 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1662 eth_hw_addr_random(ndev);
1663 }
1664 }
e190d6b1 1665
7ef0a7ee 1666 setup_mac_addr(ndev->dev_addr);
e190d6b1 1667
a63b82c4 1668 if (!dev_get_platdata(&pdev->dev)) {
080c8255
GY		 1669 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1670 rc = -ENODEV;
1671 goto out_err_probe_mac;
7ef0a7ee 1672 }
a63b82c4 1673 pd = dev_get_platdata(&pdev->dev);
080c8255 1674 lp->mii_bus = platform_get_drvdata(pd);
0e995cd3
SZ		 1675 if (!lp->mii_bus) {
1676 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1677 rc = -ENODEV;
02460d08 1678 goto out_err_probe_mac;
0e995cd3 1679 }
080c8255 1680 lp->mii_bus->priv = ndev;
a63b82c4 1681 mii_bus_data = dev_get_platdata(&pd->dev);
4ae5a3ad 1682
02460d08 1683 rc = mii_probe(ndev, mii_bus_data->phy_mode);
7ef0a7ee
BW		 1684 if (rc) {
1685 dev_err(&pdev->dev, "MII Probe failed!\n");
1686 goto out_err_mii_probe;
1687 }
4ae5a3ad 1688
c599bd6b
MF		 1689 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1690 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1691
149da651 1692 ndev->netdev_ops = &bfin_mac_netdev_ops;
679dce39 1693 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
e190d6b1 1694
4fcc3d34
SZ		 1695 init_timer(&lp->tx_reclaim_timer);
1696 lp->tx_reclaim_timer.data = (unsigned long)lp;
1697 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1698
159945af
SZ		 1699 lp->flags = 0;
1700 netif_napi_add(ndev, &lp->napi, bfin_mac_poll, CONFIG_BFIN_RX_DESC_NUM);
1701
e190d6b1
BW		 1702 spin_lock_init(&lp->lock);
1703
1704 /* now, enable interrupts */
1705 /* register irq handler */
7ef0a7ee 1706 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
63aca0f7 1707 0, "EMAC_RX", ndev);
7ef0a7ee
BW		 1708 if (rc) {
1709 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1710 rc = -EBUSY;
1711 goto out_err_request_irq;
e190d6b1
BW		 1712 }
1713
7ef0a7ee
BW		 1714 rc = register_netdev(ndev);
1715 if (rc) {
1716 dev_err(&pdev->dev, "Cannot register net device!\n");
1717 goto out_err_reg_ndev;
e190d6b1
BW		 1718 }
1719
fe92afed 1720 bfin_mac_hwtstamp_init(ndev);
2c006994
WY		 1721 rc = bfin_phc_init(ndev, &pdev->dev);
1722 if (rc) {
dd87b22f
RC		 1723 dev_err(&pdev->dev, "Cannot register PHC device!\n");
1724 goto out_err_phc;
1725 }
fe92afed 1726
7ef0a7ee 1727 /* now, print out the card info, in a short format.. */
c6dd5098 1728 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
e190d6b1 1729
7ef0a7ee 1730 return 0;
e190d6b1 1731
dd87b22f 1732out_err_phc:
7ef0a7ee
BW		 1733out_err_reg_ndev:
1734 free_irq(IRQ_MAC_RX, ndev);
1735out_err_request_irq:
159945af 1736 netif_napi_del(&lp->napi);
7ef0a7ee 1737out_err_mii_probe:
298cf9be 1738 mdiobus_unregister(lp->mii_bus);
298cf9be 1739 mdiobus_free(lp->mii_bus);
7ef0a7ee 1740out_err_probe_mac:
7ef0a7ee 1741 free_netdev(ndev);
e190d6b1 1742
7ef0a7ee 1743 return rc;
e190d6b1
BW		 1744}
1745
49f7315b 1746static int bfin_mac_remove(struct platform_device *pdev)
e190d6b1
BW		 1747{
1748 struct net_device *ndev = platform_get_drvdata(pdev);
7ef0a7ee 1749 struct bfin_mac_local *lp = netdev_priv(ndev);
e190d6b1 1750
dd87b22f
RC		 1751 bfin_phc_release(lp);
1752
080c8255 1753 lp->mii_bus->priv = NULL;
7ef0a7ee 1754
e190d6b1
BW		 1755 unregister_netdev(ndev);
1756
159945af
SZ		 1757 netif_napi_del(&lp->napi);
1758
e190d6b1
BW		 1759 free_irq(IRQ_MAC_RX, ndev);
1760
1761 free_netdev(ndev);
1762
e190d6b1
BW		 1763 return 0;
1764}
1765
496a34c2
BW		 1766#ifdef CONFIG_PM
1767static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
e190d6b1 1768{
496a34c2 1769 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1770 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1771
53fd3f28
MH		 1772 if (lp->wol) {
1773 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1774 bfin_write_EMAC_WKUP_CTL(MPKE);
1775 enable_irq_wake(IRQ_MAC_WAKEDET);
1776 } else {
1777 if (netif_running(net_dev))
1778 bfin_mac_close(net_dev);
1779 }
496a34c2 1780
e190d6b1
BW		 1781 return 0;
1782}
1783
1784static int bfin_mac_resume(struct platform_device *pdev)
1785{
496a34c2 1786 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1787 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1788
53fd3f28
MH		 1789 if (lp->wol) {
1790 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1791 bfin_write_EMAC_WKUP_CTL(0);
1792 disable_irq_wake(IRQ_MAC_WAKEDET);
1793 } else {
1794 if (netif_running(net_dev))
1795 bfin_mac_open(net_dev);
1796 }
496a34c2 1797
e190d6b1
BW		 1798 return 0;
1799}
496a34c2
BW		 1800#else
1801#define bfin_mac_suspend NULL
1802#define bfin_mac_resume NULL
1803#endif /* CONFIG_PM */
e190d6b1 1804
49f7315b 1805static int bfin_mii_bus_probe(struct platform_device *pdev)
080c8255
GY		 1806{
1807 struct mii_bus *miibus;
02460d08
SZ		 1808 struct bfin_mii_bus_platform_data *mii_bus_pd;
1809 const unsigned short *pin_req;
080c8255
GY		 1810 int rc, i;
1811
02460d08
SZ		 1812 mii_bus_pd = dev_get_platdata(&pdev->dev);
1813 if (!mii_bus_pd) {
1814 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1815 return -EINVAL;
1816 }
1817
080c8255
GY		 1818 /*
1819 * We are setting up a network card,
1820 * so set the GPIO pins to Ethernet mode
1821 */
02460d08 1822 pin_req = mii_bus_pd->mac_peripherals;
c6dd5098 1823 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
080c8255
GY		 1824 if (rc) {
1825 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1826 return rc;
1827 }
1828
1829 rc = -ENOMEM;
1830 miibus = mdiobus_alloc();
1831 if (miibus == NULL)
1832 goto out_err_alloc;
1833 miibus->read = bfin_mdiobus_read;
1834 miibus->write = bfin_mdiobus_write;
080c8255
GY		 1835
1836 miibus->parent = &pdev->dev;
1837 miibus->name = "bfin_mii_bus";
02460d08
SZ		 1838 miibus->phy_mask = mii_bus_pd->phy_mask;
1839
75432fd2
FF		 1840 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1841 pdev->name, pdev->id);
080c8255 1842
02460d08
SZ		 1843 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1844 if (rc != mii_bus_pd->phydev_number)
1845 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1846 mii_bus_pd->phydev_number);
1847 for (i = 0; i < rc; ++i) {
1848 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1849 if (phyaddr < PHY_MAX_ADDR)
1850 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1851 else
1852 dev_err(&pdev->dev,
1853 "Invalid PHY address %i for phydev %i\n",
1854 phyaddr, i);
1855 }
1856
080c8255
GY		 1857 rc = mdiobus_register(miibus);
1858 if (rc) {
1859 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
e7f4dc35 1860 goto out_err_alloc;
080c8255
GY		 1861 }
1862
1863 platform_set_drvdata(pdev, miibus);
1864 return 0;
1865
02460d08 1866out_err_irq_alloc:
080c8255
GY		 1867 mdiobus_free(miibus);
1868out_err_alloc:
1869 peripheral_free_list(pin_req);
1870
1871 return rc;
1872}
1873
49f7315b 1874static int bfin_mii_bus_remove(struct platform_device *pdev)
080c8255
GY		 1875{
1876 struct mii_bus *miibus = platform_get_drvdata(pdev);
02460d08
SZ		 1877 struct bfin_mii_bus_platform_data *mii_bus_pd =
1878 dev_get_platdata(&pdev->dev);
1879
080c8255
GY		 1880 mdiobus_unregister(miibus);
1881 mdiobus_free(miibus);
02460d08
SZ		 1882 peripheral_free_list(mii_bus_pd->mac_peripherals);
1883
080c8255
GY		 1884 return 0;
1885}
1886
1887static struct platform_driver bfin_mii_bus_driver = {
1888 .probe = bfin_mii_bus_probe,
49f7315b 1889 .remove = bfin_mii_bus_remove,
080c8255
GY		 1890 .driver = {
1891 .name = "bfin_mii_bus",
080c8255
GY		 1892 },
1893};
1894
e190d6b1
BW		 1895static struct platform_driver bfin_mac_driver = {
1896 .probe = bfin_mac_probe,
49f7315b 1897 .remove = bfin_mac_remove,
e190d6b1
BW		 1898 .resume = bfin_mac_resume,
1899 .suspend = bfin_mac_suspend,
1900 .driver = {
c6dd5098 1901 .name = KBUILD_MODNAME,
72abb461 1902 },
e190d6b1
BW		 1903};
1904
36b9ddd5
TR		 1905static struct platform_driver * const drivers[] = {
1906 &bfin_mii_bus_driver,
1907 &bfin_mac_driver,
1908};
1909
e190d6b1
BW		 1910static int __init bfin_mac_init(void)
1911{
36b9ddd5 1912 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
e190d6b1
BW		 1913}
1914
1915module_init(bfin_mac_init);
1916
1917static void __exit bfin_mac_cleanup(void)
1918{
36b9ddd5 1919 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
e190d6b1
BW		 1920}
1921
1922module_exit(bfin_mac_cleanup);
72abb461 1923
Linux kernel - Deliverables
This page took 0.850909 seconds and 5 git commands to generate.