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bfin_mac: only advertise hardware time stamped when enabled.
[deliverable/linux.git] / drivers / net / ethernet / adi / bfin_mac.c
CommitLineData
e190d6b1 1/*
2fb9d6f5 2 * Blackfin On-Chip MAC Driver
e190d6b1 3 *
02460d08 4 * Copyright 2004-2010 Analog Devices Inc.
e190d6b1 5 *
2fb9d6f5 6 * Enter bugs at http://blackfin.uclinux.org/
e190d6b1 7 *
2fb9d6f5 8 * Licensed under the GPL-2 or later.
e190d6b1
BW		 9 */
10
c6dd5098
MF		 11#define DRV_VERSION "1.1"
12#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
e190d6b1
BW		 16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/crc32.h>
28#include <linux/device.h>
29#include <linux/spinlock.h>
e190d6b1 30#include <linux/mii.h>
e190d6b1
BW		 31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
679dce39 33#include <linux/ethtool.h>
e190d6b1 34#include <linux/skbuff.h>
e190d6b1 35#include <linux/platform_device.h>
e190d6b1
BW		 36
37#include <asm/dma.h>
38#include <linux/dma-mapping.h>
39
fe92afed 40#include <asm/div64.h>
98f672ca 41#include <asm/dpmc.h>
e190d6b1
BW		 42#include <asm/blackfin.h>
43#include <asm/cacheflush.h>
44#include <asm/portmux.h>
3dcc1e7f 45#include <mach/pll.h>
e190d6b1
BW		 46
47#include "bfin_mac.h"
48
c6dd5098 49MODULE_AUTHOR("Bryan Wu, Luke Yang");
e190d6b1
BW		 50MODULE_LICENSE("GPL");
51MODULE_DESCRIPTION(DRV_DESC);
72abb461 52MODULE_ALIAS("platform:bfin_mac");
e190d6b1
BW		 53
54#if defined(CONFIG_BFIN_MAC_USE_L1)
118133e6
SZ		 55# define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56# define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
e190d6b1 57#else
118133e6
SZ		 58# define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60# define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
e190d6b1
BW		 62#endif
63
64#define PKT_BUF_SZ 1580
65
66#define MAX_TIMEOUT_CNT 500
67
68/* pointers to maintain transmit list */
69static struct net_dma_desc_tx *tx_list_head;
70static struct net_dma_desc_tx *tx_list_tail;
71static struct net_dma_desc_rx *rx_list_head;
72static struct net_dma_desc_rx *rx_list_tail;
73static struct net_dma_desc_rx *current_rx_ptr;
74static struct net_dma_desc_tx *current_tx_ptr;
75static struct net_dma_desc_tx *tx_desc;
76static struct net_dma_desc_rx *rx_desc;
77
78static void desc_list_free(void)
79{
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
82 int i;
83#if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
85#endif
86
87 if (tx_desc) {
88 t = tx_list_head;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
90 if (t) {
91 if (t->skb) {
92 dev_kfree_skb(t->skb);
93 t->skb = NULL;
94 }
95 t = t->next;
96 }
97 }
118133e6 98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
e190d6b1
BW		 99 }
100
101 if (rx_desc) {
102 r = rx_list_head;
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
104 if (r) {
105 if (r->skb) {
106 dev_kfree_skb(r->skb);
107 r->skb = NULL;
108 }
109 r = r->next;
110 }
111 }
118133e6 112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
e190d6b1
BW		 113 }
114}
115
1ab0d2ec 116static int desc_list_init(struct net_device *dev)
e190d6b1
BW		 117{
118 int i;
119 struct sk_buff *new_skb;
120#if !defined(CONFIG_BFIN_MAC_USE_L1)
121 /*
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
124 */
125 dma_addr_t dma_handle;
126#endif
127
128 tx_desc = bfin_mac_alloc(&dma_handle,
118133e6 129 sizeof(struct net_dma_desc_tx),
e190d6b1
BW		 130 CONFIG_BFIN_TX_DESC_NUM);
131 if (tx_desc == NULL)
132 goto init_error;
133
134 rx_desc = bfin_mac_alloc(&dma_handle,
118133e6 135 sizeof(struct net_dma_desc_rx),
e190d6b1
BW		 136 CONFIG_BFIN_RX_DESC_NUM);
137 if (rx_desc == NULL)
138 goto init_error;
139
140 /* init tx_list */
141 tx_list_head = tx_list_tail = tx_desc;
142
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
147
148 /*
149 * disable DMA
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
153 * large desc flow
154 */
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
157 a->x_count = 0;
158 a->next_dma_desc = b;
159
160 /*
161 * enabled DMA
162 * write to memory WNR = 1
163 * wordsize is 32 bits
164 * disable interrupt
165 * 6 half words is desc size
166 * large desc flow
167 */
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
170 b->x_count = 0;
171
172 t->skb = NULL;
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
175 tx_list_tail = t;
176 }
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
180
181 /* init rx_list */
182 rx_list_head = rx_list_tail = rx_desc;
183
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
188
189 /* allocate a new skb for next time receive */
1ab0d2ec 190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1 191 if (!new_skb) {
c6dd5098 192 pr_notice("init: low on mem - packet dropped\n");
e190d6b1
BW		 193 goto init_error;
194 }
015dac88 195 skb_reserve(new_skb, NET_IP_ALIGN);
f6e1e4f3
SZ		 196 /* Invidate the data cache of skb->data range when it is write back
197 * cache. It will prevent overwritting the new data from DMA
198 */
199 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
200 (unsigned long)new_skb->end);
e190d6b1
BW		 201 r->skb = new_skb;
202
203 /*
204 * enabled DMA
205 * write to memory WNR = 1
206 * wordsize is 32 bits
207 * disable interrupt
208 * 6 half words is desc size
209 * large desc flow
210 */
211 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
212 /* since RXDWA is enabled */
213 a->start_addr = (unsigned long)new_skb->data - 2;
214 a->x_count = 0;
215 a->next_dma_desc = b;
216
217 /*
218 * enabled DMA
219 * write to memory WNR = 1
220 * wordsize is 32 bits
221 * enable interrupt
222 * 6 half words is desc size
223 * large desc flow
224 */
225 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
226 NDSIZE_6 | DMAFLOW_LARGE;
227 b->start_addr = (unsigned long)(&(r->status));
228 b->x_count = 0;
229
230 rx_list_tail->desc_b.next_dma_desc = a;
231 rx_list_tail->next = r;
232 rx_list_tail = r;
233 }
234 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
235 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
236 current_rx_ptr = rx_list_head;
237
238 return 0;
239
240init_error:
241 desc_list_free();
c6dd5098 242 pr_err("kmalloc failed\n");
e190d6b1
BW		 243 return -ENOMEM;
244}
245
246
247/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
248
4ae5a3ad
BW		 249/*
250 * MII operations
251 */
e190d6b1 252/* Wait until the previous MDC/MDIO transaction has completed */
2bfa0f0c 253static int bfin_mdio_poll(void)
e190d6b1
BW		 254{
255 int timeout_cnt = MAX_TIMEOUT_CNT;
256
257 /* poll the STABUSY bit */
258 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
6db9e461 259 udelay(1);
e190d6b1 260 if (timeout_cnt-- < 0) {
c6dd5098 261 pr_err("wait MDC/MDIO transaction to complete timeout\n");
2bfa0f0c 262 return -ETIMEDOUT;
e190d6b1
BW		 263 }
264 }
2bfa0f0c
MF		 265
266 return 0;
e190d6b1
BW		 267}
268
269/* Read an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e 270static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
e190d6b1 271{
2bfa0f0c
MF		 272 int ret;
273
274 ret = bfin_mdio_poll();
275 if (ret)
276 return ret;
4ae5a3ad 277
e190d6b1 278 /* read mode */
4ae5a3ad
BW		 279 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
280 SET_REGAD((u16) regnum) |
e190d6b1 281 STABUSY);
e190d6b1 282
2bfa0f0c
MF		 283 ret = bfin_mdio_poll();
284 if (ret)
285 return ret;
4ae5a3ad
BW		 286
287 return (int) bfin_read_EMAC_STADAT();
e190d6b1
BW		 288}
289
290/* Write an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e
AB		 291static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
292 u16 value)
e190d6b1 293{
2bfa0f0c
MF		 294 int ret;
295
296 ret = bfin_mdio_poll();
297 if (ret)
298 return ret;
4ae5a3ad
BW		 299
300 bfin_write_EMAC_STADAT((u32) value);
e190d6b1
BW		 301
302 /* write mode */
4ae5a3ad
BW		 303 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
304 SET_REGAD((u16) regnum) |
e190d6b1
BW		 305 STAOP |
306 STABUSY);
307
2bfa0f0c 308 return bfin_mdio_poll();
e190d6b1
BW		 309}
310
0ed0563e 311static int bfin_mdiobus_reset(struct mii_bus *bus)
e190d6b1 312{
4ae5a3ad 313 return 0;
e190d6b1
BW		 314}
315
7ef0a7ee 316static void bfin_mac_adjust_link(struct net_device *dev)
e190d6b1 317{
7ef0a7ee 318 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 319 struct phy_device *phydev = lp->phydev;
320 unsigned long flags;
321 int new_state = 0;
322
323 spin_lock_irqsave(&lp->lock, flags);
324 if (phydev->link) {
325 /* Now we make sure that we can be in full duplex mode.
326 * If not, we operate in half-duplex mode. */
327 if (phydev->duplex != lp->old_duplex) {
328 u32 opmode = bfin_read_EMAC_OPMODE();
329 new_state = 1;
330
331 if (phydev->duplex)
332 opmode |= FDMODE;
333 else
334 opmode &= ~(FDMODE);
335
336 bfin_write_EMAC_OPMODE(opmode);
337 lp->old_duplex = phydev->duplex;
338 }
e190d6b1 339
4ae5a3ad 340 if (phydev->speed != lp->old_speed) {
02460d08
SZ		 341 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
342 u32 opmode = bfin_read_EMAC_OPMODE();
343 switch (phydev->speed) {
344 case 10:
345 opmode |= RMII_10;
346 break;
347 case 100:
348 opmode &= ~RMII_10;
349 break;
350 default:
c6dd5098
MF		 351 netdev_warn(dev,
352 "Ack! Speed (%d) is not 10/100!\n",
353 phydev->speed);
02460d08
SZ		 354 break;
355 }
356 bfin_write_EMAC_OPMODE(opmode);
4ae5a3ad 357 }
e190d6b1 358
4ae5a3ad
BW		 359 new_state = 1;
360 lp->old_speed = phydev->speed;
361 }
e190d6b1 362
4ae5a3ad
BW		 363 if (!lp->old_link) {
364 new_state = 1;
365 lp->old_link = 1;
4ae5a3ad
BW		 366 }
367 } else if (lp->old_link) {
368 new_state = 1;
369 lp->old_link = 0;
370 lp->old_speed = 0;
371 lp->old_duplex = -1;
e190d6b1
BW		 372 }
373
4ae5a3ad
BW		 374 if (new_state) {
375 u32 opmode = bfin_read_EMAC_OPMODE();
376 phy_print_status(phydev);
377 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
e190d6b1 378 }
4ae5a3ad
BW		 379
380 spin_unlock_irqrestore(&lp->lock, flags);
e190d6b1
BW		 381}
382
7cc8f381
BW		 383/* MDC = 2.5 MHz */
384#define MDC_CLK 2500000
385
02460d08 386static int mii_probe(struct net_device *dev, int phy_mode)
e190d6b1 387{
7ef0a7ee 388 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 389 struct phy_device *phydev = NULL;
390 unsigned short sysctl;
391 int i;
7cc8f381 392 u32 sclk, mdc_div;
e190d6b1 393
4ae5a3ad 394 /* Enable PHY output early */
98f672ca
MF		 395 if (!(bfin_read_VR_CTL() & CLKBUFOE))
396 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
e190d6b1 397
7cc8f381
BW		 398 sclk = get_sclk();
399 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
400
4ae5a3ad 401 sysctl = bfin_read_EMAC_SYSCTL();
9dc7f30e 402 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
e190d6b1 403 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1 404
02460d08
SZ		 405 /* search for connected PHY device */
406 for (i = 0; i < PHY_MAX_ADDR; ++i) {
298cf9be 407 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
e190d6b1 408
4ae5a3ad
BW		 409 if (!tmp_phydev)
410 continue; /* no PHY here... */
e190d6b1 411
4ae5a3ad
BW		 412 phydev = tmp_phydev;
413 break; /* found it */
414 }
415
416 /* now we are supposed to have a proper phydev, to attach to... */
417 if (!phydev) {
c6dd5098 418 netdev_err(dev, "no phy device found\n");
4ae5a3ad 419 return -ENODEV;
e190d6b1
BW		 420 }
421
02460d08
SZ		 422 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
423 phy_mode != PHY_INTERFACE_MODE_MII) {
c6dd5098 424 netdev_err(dev, "invalid phy interface mode\n");
02460d08
SZ		 425 return -EINVAL;
426 }
427
c2313557 428 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
02460d08 429 0, phy_mode);
e190d6b1 430
4ae5a3ad 431 if (IS_ERR(phydev)) {
c6dd5098 432 netdev_err(dev, "could not attach PHY\n");
4ae5a3ad
BW		 433 return PTR_ERR(phydev);
434 }
435
436 /* mask with MAC supported features */
437 phydev->supported &= (SUPPORTED_10baseT_Half
438 | SUPPORTED_10baseT_Full
439 | SUPPORTED_100baseT_Half
440 | SUPPORTED_100baseT_Full
441 | SUPPORTED_Autoneg
442 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
443 | SUPPORTED_MII
444 | SUPPORTED_TP);
445
446 phydev->advertising = phydev->supported;
447
448 lp->old_link = 0;
449 lp->old_speed = 0;
450 lp->old_duplex = -1;
451 lp->phydev = phydev;
452
c6dd5098
MF		 453 pr_info("attached PHY driver [%s] "
454 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
455 phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
456 MDC_CLK, mdc_div, sclk/1000000);
4ae5a3ad
BW		 457
458 return 0;
459}
460
679dce39
BW		 461/*
462 * Ethtool support
463 */
464
53fd3f28
MH		 465/*
466 * interrupt routine for magic packet wakeup
467 */
468static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
469{
470 return IRQ_HANDLED;
471}
472
679dce39
BW		 473static int
474bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
475{
476 struct bfin_mac_local *lp = netdev_priv(dev);
477
478 if (lp->phydev)
479 return phy_ethtool_gset(lp->phydev, cmd);
480
481 return -EINVAL;
482}
483
484static int
485bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
486{
487 struct bfin_mac_local *lp = netdev_priv(dev);
488
489 if (!capable(CAP_NET_ADMIN))
490 return -EPERM;
491
492 if (lp->phydev)
493 return phy_ethtool_sset(lp->phydev, cmd);
494
495 return -EINVAL;
496}
497
498static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
499 struct ethtool_drvinfo *info)
500{
c6dd5098 501 strcpy(info->driver, KBUILD_MODNAME);
679dce39
BW		 502 strcpy(info->version, DRV_VERSION);
503 strcpy(info->fw_version, "N/A");
c2313557 504 strcpy(info->bus_info, dev_name(&dev->dev));
679dce39
BW		 505}
506
53fd3f28
MH		 507static void bfin_mac_ethtool_getwol(struct net_device *dev,
508 struct ethtool_wolinfo *wolinfo)
509{
510 struct bfin_mac_local *lp = netdev_priv(dev);
511
512 wolinfo->supported = WAKE_MAGIC;
513 wolinfo->wolopts = lp->wol;
514}
515
516static int bfin_mac_ethtool_setwol(struct net_device *dev,
517 struct ethtool_wolinfo *wolinfo)
518{
519 struct bfin_mac_local *lp = netdev_priv(dev);
520 int rc;
521
522 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
523 WAKE_UCAST |
524 WAKE_MCAST |
525 WAKE_BCAST |
526 WAKE_ARP))
527 return -EOPNOTSUPP;
528
529 lp->wol = wolinfo->wolopts;
530
531 if (lp->wol && !lp->irq_wake_requested) {
532 /* register wake irq handler */
533 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
534 IRQF_DISABLED, "EMAC_WAKE", dev);
535 if (rc)
536 return rc;
537 lp->irq_wake_requested = true;
538 }
539
540 if (!lp->wol && lp->irq_wake_requested) {
541 free_irq(IRQ_MAC_WAKEDET, dev);
542 lp->irq_wake_requested = false;
543 }
544
545 /* Make sure the PHY driver doesn't suspend */
546 device_init_wakeup(&dev->dev, lp->wol);
547
548 return 0;
549}
550
85c153d2 551#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
a85bbddd 552static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
3ffa4290 553 struct ethtool_ts_info *info)
a85bbddd
RC		 554{
555 info->so_timestamping =
556 SOF_TIMESTAMPING_TX_HARDWARE |
557 SOF_TIMESTAMPING_RX_HARDWARE |
558 SOF_TIMESTAMPING_SYS_HARDWARE;
559 info->phc_index = -1;
560 info->tx_types =
561 (1 << HWTSTAMP_TX_OFF) |
562 (1 << HWTSTAMP_TX_ON);
563 info->rx_filters =
564 (1 << HWTSTAMP_FILTER_NONE) |
565 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
566 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
567 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
568 return 0;
569}
85c153d2 570#endif
a85bbddd 571
0fc0b732 572static const struct ethtool_ops bfin_mac_ethtool_ops = {
679dce39
BW		 573 .get_settings = bfin_mac_ethtool_getsettings,
574 .set_settings = bfin_mac_ethtool_setsettings,
575 .get_link = ethtool_op_get_link,
576 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
53fd3f28
MH		 577 .get_wol = bfin_mac_ethtool_getwol,
578 .set_wol = bfin_mac_ethtool_setwol,
85c153d2 579#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
a85bbddd 580 .get_ts_info = bfin_mac_ethtool_get_ts_info,
85c153d2 581#endif
679dce39
BW		 582};
583
4ae5a3ad 584/**************************************************************************/
5ca1bb5a 585static void setup_system_regs(struct net_device *dev)
4ae5a3ad 586{
02460d08
SZ		 587 struct bfin_mac_local *lp = netdev_priv(dev);
588 int i;
4ae5a3ad
BW		 589 unsigned short sysctl;
590
591 /*
592 * Odd word alignment for Receive Frame DMA word
593 * Configure checksum support and rcve frame word alignment
594 */
595 sysctl = bfin_read_EMAC_SYSCTL();
02460d08
SZ		 596 /*
597 * check if interrupt is requested for any PHY,
598 * enable PHY interrupt only if needed
599 */
600 for (i = 0; i < PHY_MAX_ADDR; ++i)
601 if (lp->mii_bus->irq[i] != PHY_POLL)
602 break;
603 if (i < PHY_MAX_ADDR)
604 sysctl |= PHYIE;
812a9de7 605 sysctl |= RXDWA;
4ae5a3ad 606#if defined(BFIN_MAC_CSUM_OFFLOAD)
812a9de7 607 sysctl |= RXCKS;
4ae5a3ad 608#else
812a9de7 609 sysctl &= ~RXCKS;
4ae5a3ad
BW		 610#endif
611 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1
BW		 612
613 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
614
c599bd6b
MF		 615 /* Set vlan regs to let 1522 bytes long packets pass through */
616 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
617 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
618
e190d6b1
BW		 619 /* Initialize the TX DMA channel registers */
620 bfin_write_DMA2_X_COUNT(0);
621 bfin_write_DMA2_X_MODIFY(4);
622 bfin_write_DMA2_Y_COUNT(0);
623 bfin_write_DMA2_Y_MODIFY(0);
624
625 /* Initialize the RX DMA channel registers */
626 bfin_write_DMA1_X_COUNT(0);
627 bfin_write_DMA1_X_MODIFY(4);
628 bfin_write_DMA1_Y_COUNT(0);
629 bfin_write_DMA1_Y_MODIFY(0);
630}
631
73f83182 632static void setup_mac_addr(u8 *mac_addr)
e190d6b1
BW		 633{
634 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
635 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
636
637 /* this depends on a little-endian machine */
638 bfin_write_EMAC_ADDRLO(addr_low);
639 bfin_write_EMAC_ADDRHI(addr_hi);
640}
641
7ef0a7ee 642static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
73f83182
AL		 643{
644 struct sockaddr *addr = p;
645 if (netif_running(dev))
646 return -EBUSY;
647 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5055d2f2 648 dev->addr_assign_type &= ~NET_ADDR_RANDOM;
73f83182
AL		 649 setup_mac_addr(dev->dev_addr);
650 return 0;
651}
652
fe92afed
BS		 653#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
654#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
655
656static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
657 struct ifreq *ifr, int cmd)
658{
659 struct hwtstamp_config config;
660 struct bfin_mac_local *lp = netdev_priv(netdev);
661 u16 ptpctl;
662 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
663
664 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
665 return -EFAULT;
666
667 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
668 __func__, config.flags, config.tx_type, config.rx_filter);
669
670 /* reserved for future extensions */
671 if (config.flags)
672 return -EINVAL;
673
674 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
675 (config.tx_type != HWTSTAMP_TX_ON))
676 return -ERANGE;
677
678 ptpctl = bfin_read_EMAC_PTP_CTL();
679
680 switch (config.rx_filter) {
681 case HWTSTAMP_FILTER_NONE:
682 /*
683 * Dont allow any timestamping
684 */
685 ptpfv3 = 0xFFFFFFFF;
686 bfin_write_EMAC_PTP_FV3(ptpfv3);
687 break;
688 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
689 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
690 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
691 /*
692 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
693 * to enable all the field matches.
694 */
695 ptpctl &= ~0x1F00;
696 bfin_write_EMAC_PTP_CTL(ptpctl);
697 /*
698 * Keep the default values of the EMAC_PTP_FOFF register.
699 */
700 ptpfoff = 0x4A24170C;
701 bfin_write_EMAC_PTP_FOFF(ptpfoff);
702 /*
703 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
704 * registers.
705 */
706 ptpfv1 = 0x11040800;
707 bfin_write_EMAC_PTP_FV1(ptpfv1);
708 ptpfv2 = 0x0140013F;
709 bfin_write_EMAC_PTP_FV2(ptpfv2);
710 /*
711 * The default value (0xFFFC) allows the timestamping of both
712 * received Sync messages and Delay_Req messages.
713 */
714 ptpfv3 = 0xFFFFFFFC;
715 bfin_write_EMAC_PTP_FV3(ptpfv3);
716
717 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
718 break;
719 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
720 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
721 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
722 /* Clear all five comparison mask bits (bits[12:8]) in the
723 * EMAC_PTP_CTL register to enable all the field matches.
724 */
725 ptpctl &= ~0x1F00;
726 bfin_write_EMAC_PTP_CTL(ptpctl);
727 /*
728 * Keep the default values of the EMAC_PTP_FOFF register, except set
729 * the PTPCOF field to 0x2A.
730 */
731 ptpfoff = 0x2A24170C;
732 bfin_write_EMAC_PTP_FOFF(ptpfoff);
733 /*
734 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
735 * registers.
736 */
737 ptpfv1 = 0x11040800;
738 bfin_write_EMAC_PTP_FV1(ptpfv1);
739 ptpfv2 = 0x0140013F;
740 bfin_write_EMAC_PTP_FV2(ptpfv2);
741 /*
742 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
743 * the value to 0xFFF0.
744 */
745 ptpfv3 = 0xFFFFFFF0;
746 bfin_write_EMAC_PTP_FV3(ptpfv3);
747
748 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
749 break;
750 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
751 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
752 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
753 /*
754 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
755 * EFTM and PTPCM field comparison.
756 */
757 ptpctl &= ~0x1100;
758 bfin_write_EMAC_PTP_CTL(ptpctl);
759 /*
760 * Keep the default values of all the fields of the EMAC_PTP_FOFF
761 * register, except set the PTPCOF field to 0x0E.
762 */
763 ptpfoff = 0x0E24170C;
764 bfin_write_EMAC_PTP_FOFF(ptpfoff);
765 /*
766 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
767 * corresponds to PTP messages on the MAC layer.
768 */
769 ptpfv1 = 0x110488F7;
770 bfin_write_EMAC_PTP_FV1(ptpfv1);
771 ptpfv2 = 0x0140013F;
772 bfin_write_EMAC_PTP_FV2(ptpfv2);
773 /*
774 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
775 * messages, set the value to 0xFFF0.
776 */
777 ptpfv3 = 0xFFFFFFF0;
778 bfin_write_EMAC_PTP_FV3(ptpfv3);
779
780 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
781 break;
782 default:
783 return -ERANGE;
784 }
785
786 if (config.tx_type == HWTSTAMP_TX_OFF &&
787 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
788 ptpctl &= ~PTP_EN;
789 bfin_write_EMAC_PTP_CTL(ptpctl);
790
791 SSYNC();
792 } else {
793 ptpctl |= PTP_EN;
794 bfin_write_EMAC_PTP_CTL(ptpctl);
795
796 /*
797 * clear any existing timestamp
798 */
799 bfin_read_EMAC_PTP_RXSNAPLO();
800 bfin_read_EMAC_PTP_RXSNAPHI();
801
802 bfin_read_EMAC_PTP_TXSNAPLO();
803 bfin_read_EMAC_PTP_TXSNAPHI();
804
805 /*
806 * Set registers so that rollover occurs soon to test this.
807 */
808 bfin_write_EMAC_PTP_TIMELO(0x00000000);
809 bfin_write_EMAC_PTP_TIMEHI(0xFF800000);
810
811 SSYNC();
812
813 lp->compare.last_update = 0;
814 timecounter_init(&lp->clock,
815 &lp->cycles,
816 ktime_to_ns(ktime_get_real()));
817 timecompare_update(&lp->compare, 0);
818 }
819
820 lp->stamp_cfg = config;
821 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
822 -EFAULT : 0;
823}
824
825static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp)
826{
827 ktime_t sys = ktime_get_real();
828
829 pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n",
830 __func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec,
831 sys.tv.nsec, cmp->offset, cmp->skew);
832}
833
834static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
835{
836 struct bfin_mac_local *lp = netdev_priv(netdev);
fe92afed 837
2244d07b 838 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
fe92afed
BS		 839 int timeout_cnt = MAX_TIMEOUT_CNT;
840
841 /* When doing time stamping, keep the connection to the socket
842 * a while longer
843 */
2244d07b 844 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
fe92afed
BS		 845
846 /*
847 * The timestamping is done at the EMAC module's MII/RMII interface
848 * when the module sees the Start of Frame of an event message packet. This
849 * interface is the closest possible place to the physical Ethernet transmission
850 * medium, providing the best timing accuracy.
851 */
852 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
853 udelay(1);
854 if (timeout_cnt == 0)
c6dd5098 855 netdev_err(netdev, "timestamp the TX packet failed\n");
fe92afed
BS		 856 else {
857 struct skb_shared_hwtstamps shhwtstamps;
858 u64 ns;
859 u64 regval;
860
861 regval = bfin_read_EMAC_PTP_TXSNAPLO();
862 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
863 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
864 ns = timecounter_cyc2time(&lp->clock,
865 regval);
866 timecompare_update(&lp->compare, ns);
867 shhwtstamps.hwtstamp = ns_to_ktime(ns);
868 shhwtstamps.syststamp =
869 timecompare_transform(&lp->compare, ns);
870 skb_tstamp_tx(skb, &shhwtstamps);
871
872 bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare);
873 }
874 }
875}
876
877static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
878{
879 struct bfin_mac_local *lp = netdev_priv(netdev);
880 u32 valid;
881 u64 regval, ns;
882 struct skb_shared_hwtstamps *shhwtstamps;
883
884 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
885 return;
886
887 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
888 if (!valid)
889 return;
890
891 shhwtstamps = skb_hwtstamps(skb);
892
893 regval = bfin_read_EMAC_PTP_RXSNAPLO();
894 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
895 ns = timecounter_cyc2time(&lp->clock, regval);
896 timecompare_update(&lp->compare, ns);
897 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
898 shhwtstamps->hwtstamp = ns_to_ktime(ns);
899 shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns);
900
901 bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare);
902}
903
904/*
905 * bfin_read_clock - read raw cycle counter (to be used by time counter)
906 */
907static cycle_t bfin_read_clock(const struct cyclecounter *tc)
908{
909 u64 stamp;
910
911 stamp = bfin_read_EMAC_PTP_TIMELO();
912 stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL;
913
914 return stamp;
915}
916
917#define PTP_CLK 25000000
918
919static void bfin_mac_hwtstamp_init(struct net_device *netdev)
920{
921 struct bfin_mac_local *lp = netdev_priv(netdev);
922 u64 append;
923
924 /* Initialize hardware timer */
925 append = PTP_CLK * (1ULL << 32);
926 do_div(append, get_sclk());
927 bfin_write_EMAC_PTP_ADDEND((u32)append);
928
929 memset(&lp->cycles, 0, sizeof(lp->cycles));
930 lp->cycles.read = bfin_read_clock;
931 lp->cycles.mask = CLOCKSOURCE_MASK(64);
932 lp->cycles.mult = 1000000000 / PTP_CLK;
933 lp->cycles.shift = 0;
934
935 /* Synchronize our NIC clock against system wall clock */
936 memset(&lp->compare, 0, sizeof(lp->compare));
937 lp->compare.source = &lp->clock;
938 lp->compare.target = ktime_get_real;
939 lp->compare.num_samples = 10;
940
941 /* Initialize hwstamp config */
942 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
943 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
944}
945
946#else
947# define bfin_mac_hwtstamp_is_none(cfg) 0
948# define bfin_mac_hwtstamp_init(dev)
949# define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
950# define bfin_rx_hwtstamp(dev, skb)
951# define bfin_tx_hwtstamp(dev, skb)
952#endif
953
4fcc3d34
SZ		 954static inline void _tx_reclaim_skb(void)
955{
956 do {
957 tx_list_head->desc_a.config &= ~DMAEN;
958 tx_list_head->status.status_word = 0;
959 if (tx_list_head->skb) {
960 dev_kfree_skb(tx_list_head->skb);
961 tx_list_head->skb = NULL;
962 }
963 tx_list_head = tx_list_head->next;
964
965 } while (tx_list_head->status.status_word != 0);
966}
967
968static void tx_reclaim_skb(struct bfin_mac_local *lp)
e190d6b1
BW		 969{
970 int timeout_cnt = MAX_TIMEOUT_CNT;
971
4fcc3d34
SZ		 972 if (tx_list_head->status.status_word != 0)
973 _tx_reclaim_skb();
e190d6b1 974
4fcc3d34 975 if (current_tx_ptr->next == tx_list_head) {
e190d6b1 976 while (tx_list_head->status.status_word == 0) {
4fcc3d34 977 /* slow down polling to avoid too many queue stop. */
015dac88 978 udelay(10);
4fcc3d34
SZ		 979 /* reclaim skb if DMA is not running. */
980 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
981 break;
982 if (timeout_cnt-- < 0)
e190d6b1 983 break;
e190d6b1 984 }
4fcc3d34
SZ		 985
986 if (timeout_cnt >= 0)
987 _tx_reclaim_skb();
988 else
989 netif_stop_queue(lp->ndev);
e190d6b1
BW		 990 }
991
4fcc3d34
SZ		 992 if (current_tx_ptr->next != tx_list_head &&
993 netif_queue_stopped(lp->ndev))
994 netif_wake_queue(lp->ndev);
995
996 if (tx_list_head != current_tx_ptr) {
997 /* shorten the timer interval if tx queue is stopped */
998 if (netif_queue_stopped(lp->ndev))
999 lp->tx_reclaim_timer.expires =
1000 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1001 else
1002 lp->tx_reclaim_timer.expires =
1003 jiffies + TX_RECLAIM_JIFFIES;
1004
1005 mod_timer(&lp->tx_reclaim_timer,
1006 lp->tx_reclaim_timer.expires);
1007 }
e190d6b1 1008
e190d6b1 1009 return;
4fcc3d34 1010}
e190d6b1 1011
4fcc3d34
SZ		 1012static void tx_reclaim_skb_timeout(unsigned long lp)
1013{
1014 tx_reclaim_skb((struct bfin_mac_local *)lp);
e190d6b1
BW		 1015}
1016
7ef0a7ee 1017static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
e190d6b1
BW		 1018 struct net_device *dev)
1019{
4fcc3d34 1020 struct bfin_mac_local *lp = netdev_priv(dev);
a50c0c05 1021 u16 *data;
015dac88 1022 u32 data_align = (unsigned long)(skb->data) & 0x3;
fe92afed 1023
e190d6b1
BW		 1024 current_tx_ptr->skb = skb;
1025
015dac88
MH		 1026 if (data_align == 0x2) {
1027 /* move skb->data to current_tx_ptr payload */
1028 data = (u16 *)(skb->data) - 1;
fe92afed
BS		 1029 *data = (u16)(skb->len);
1030 /*
1031 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1032 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1033 * of this field are the length of the packet payload in bytes and the higher
1034 * 4 bits are the timestamping enable field.
1035 */
2244d07b 1036 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed
BS		 1037 *data |= 0x1000;
1038
015dac88
MH		 1039 current_tx_ptr->desc_a.start_addr = (u32)data;
1040 /* this is important! */
1041 blackfin_dcache_flush_range((u32)data,
1042 (u32)((u8 *)data + skb->len + 4));
e190d6b1 1043 } else {
015dac88 1044 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
fe92afed 1045 /* enable timestamping for the sent packet */
2244d07b 1046 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed 1047 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
015dac88
MH		 1048 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1049 skb->len);
1050 current_tx_ptr->desc_a.start_addr =
1051 (u32)current_tx_ptr->packet;
015dac88
MH		 1052 blackfin_dcache_flush_range(
1053 (u32)current_tx_ptr->packet,
1054 (u32)(current_tx_ptr->packet + skb->len + 2));
e190d6b1
BW		 1055 }
1056
805a8ab3
SZ		 1057 /* make sure the internal data buffers in the core are drained
1058 * so that the DMA descriptors are completely written when the
1059 * DMA engine goes to fetch them below
1060 */
1061 SSYNC();
1062
4fcc3d34
SZ		 1063 /* always clear status buffer before start tx dma */
1064 current_tx_ptr->status.status_word = 0;
1065
e190d6b1
BW		 1066 /* enable this packet's dma */
1067 current_tx_ptr->desc_a.config |= DMAEN;
1068
1069 /* tx dma is running, just return */
015dac88 1070 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
e190d6b1
BW		 1071 goto out;
1072
1073 /* tx dma is not running */
1074 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1075 /* dma enabled, read from memory, size is 6 */
1076 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1077 /* Turn on the EMAC tx */
1078 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1079
1080out:
fe92afed
BS		 1081 bfin_tx_hwtstamp(dev, skb);
1082
e190d6b1 1083 current_tx_ptr = current_tx_ptr->next;
09f75cd7
JG		 1084 dev->stats.tx_packets++;
1085 dev->stats.tx_bytes += (skb->len);
4fcc3d34
SZ		 1086
1087 tx_reclaim_skb(lp);
1088
6ed10654 1089 return NETDEV_TX_OK;
e190d6b1
BW		 1090}
1091
ad2864d8 1092#define IP_HEADER_OFF 0
ec497b32
PM		 1093#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1094 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1095
7ef0a7ee 1096static void bfin_mac_rx(struct net_device *dev)
e190d6b1
BW		 1097{
1098 struct sk_buff *skb, *new_skb;
e190d6b1 1099 unsigned short len;
fe92afed 1100 struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
ad2864d8
SZ		 1101#if defined(BFIN_MAC_CSUM_OFFLOAD)
1102 unsigned int i;
1103 unsigned char fcs[ETH_FCS_LEN + 1];
1104#endif
e190d6b1 1105
ec497b32
PM		 1106 /* check if frame status word reports an error condition
1107 * we which case we simply drop the packet
1108 */
1109 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
c6dd5098 1110 netdev_notice(dev, "rx: receive error - packet dropped\n");
ec497b32
PM		 1111 dev->stats.rx_dropped++;
1112 goto out;
1113 }
1114
e190d6b1
BW		 1115 /* allocate a new skb for next time receive */
1116 skb = current_rx_ptr->skb;
fe92afed 1117
1ab0d2ec 1118 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1 1119 if (!new_skb) {
c6dd5098 1120 netdev_notice(dev, "rx: low on mem - packet dropped\n");
09f75cd7 1121 dev->stats.rx_dropped++;
e190d6b1
BW		 1122 goto out;
1123 }
1124 /* reserve 2 bytes for RXDWA padding */
015dac88 1125 skb_reserve(new_skb, NET_IP_ALIGN);
6e01d1a4
AD		 1126 /* Invidate the data cache of skb->data range when it is write back
1127 * cache. It will prevent overwritting the new data from DMA
1128 */
1129 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1130 (unsigned long)new_skb->end);
1131
f6e1e4f3
SZ		 1132 current_rx_ptr->skb = new_skb;
1133 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1134
e190d6b1 1135 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
ad2864d8
SZ		 1136 /* Deduce Ethernet FCS length from Ethernet payload length */
1137 len -= ETH_FCS_LEN;
e190d6b1 1138 skb_put(skb, len);
e190d6b1 1139
e190d6b1 1140 skb->protocol = eth_type_trans(skb, dev);
fe92afed
BS		 1141
1142 bfin_rx_hwtstamp(dev, skb);
1143
e190d6b1 1144#if defined(BFIN_MAC_CSUM_OFFLOAD)
ad2864d8
SZ		 1145 /* Checksum offloading only works for IPv4 packets with the standard IP header
1146 * length of 20 bytes, because the blackfin MAC checksum calculation is
1147 * based on that assumption. We must NOT use the calculated checksum if our
1148 * IP version or header break that assumption.
1149 */
1150 if (skb->data[IP_HEADER_OFF] == 0x45) {
1151 skb->csum = current_rx_ptr->status.ip_payload_csum;
1152 /*
1153 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1154 * IP checksum is based on 16-bit one's complement algorithm.
1155 * To deduce a value from checksum is equal to add its inversion.
1156 * If the IP payload len is odd, the inversed FCS should also
1157 * begin from odd address and leave first byte zero.
1158 */
1159 if (skb->len % 2) {
1160 fcs[0] = 0;
1161 for (i = 0; i < ETH_FCS_LEN; i++)
1162 fcs[i + 1] = ~skb->data[skb->len + i];
1163 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1164 } else {
1165 for (i = 0; i < ETH_FCS_LEN; i++)
1166 fcs[i] = ~skb->data[skb->len + i];
1167 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1168 }
1169 skb->ip_summed = CHECKSUM_COMPLETE;
1170 }
e190d6b1
BW		 1171#endif
1172
1173 netif_rx(skb);
09f75cd7
JG		 1174 dev->stats.rx_packets++;
1175 dev->stats.rx_bytes += len;
ec497b32 1176out:
e190d6b1
BW		 1177 current_rx_ptr->status.status_word = 0x00000000;
1178 current_rx_ptr = current_rx_ptr->next;
e190d6b1
BW		 1179}
1180
1181/* interrupt routine to handle rx and error signal */
7ef0a7ee 1182static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
e190d6b1
BW		 1183{
1184 struct net_device *dev = dev_id;
1185 int number = 0;
1186
1187get_one_packet:
1188 if (current_rx_ptr->status.status_word == 0) {
1189 /* no more new packet received */
1190 if (number == 0) {
1191 if (current_rx_ptr->next->status.status_word != 0) {
1192 current_rx_ptr = current_rx_ptr->next;
1193 goto real_rx;
1194 }
1195 }
1196 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1197 DMA_DONE | DMA_ERR);
1198 return IRQ_HANDLED;
1199 }
1200
1201real_rx:
7ef0a7ee 1202 bfin_mac_rx(dev);
e190d6b1
BW		 1203 number++;
1204 goto get_one_packet;
1205}
1206
1207#ifdef CONFIG_NET_POLL_CONTROLLER
7ef0a7ee 1208static void bfin_mac_poll(struct net_device *dev)
e190d6b1 1209{
4fcc3d34
SZ		 1210 struct bfin_mac_local *lp = netdev_priv(dev);
1211
e190d6b1 1212 disable_irq(IRQ_MAC_RX);
7ef0a7ee 1213 bfin_mac_interrupt(IRQ_MAC_RX, dev);
4fcc3d34 1214 tx_reclaim_skb(lp);
e190d6b1
BW		 1215 enable_irq(IRQ_MAC_RX);
1216}
1217#endif /* CONFIG_NET_POLL_CONTROLLER */
1218
7ef0a7ee 1219static void bfin_mac_disable(void)
e190d6b1
BW		 1220{
1221 unsigned int opmode;
1222
1223 opmode = bfin_read_EMAC_OPMODE();
1224 opmode &= (~RE);
1225 opmode &= (~TE);
1226 /* Turn off the EMAC */
1227 bfin_write_EMAC_OPMODE(opmode);
1228}
1229
1230/*
1231 * Enable Interrupts, Receive, and Transmit
1232 */
02460d08 1233static int bfin_mac_enable(struct phy_device *phydev)
e190d6b1 1234{
2bfa0f0c 1235 int ret;
e190d6b1
BW		 1236 u32 opmode;
1237
c6dd5098 1238 pr_debug("%s\n", __func__);
e190d6b1
BW		 1239
1240 /* Set RX DMA */
1241 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1242 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1243
1244 /* Wait MII done */
2bfa0f0c
MF		 1245 ret = bfin_mdio_poll();
1246 if (ret)
1247 return ret;
e190d6b1
BW		 1248
1249 /* We enable only RX here */
1250 /* ASTP : Enable Automatic Pad Stripping
1251 PR : Promiscuous Mode for test
1252 PSF : Receive frames with total length less than 64 bytes.
1253 FDMODE : Full Duplex Mode
1254 LB : Internal Loopback for test
1255 RE : Receiver Enable */
1256 opmode = bfin_read_EMAC_OPMODE();
1257 if (opmode & FDMODE)
1258 opmode |= PSF;
1259 else
1260 opmode |= DRO | DC | PSF;
1261 opmode |= RE;
1262
02460d08
SZ		 1263 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1264 opmode |= RMII; /* For Now only 100MBit are supported */
72f49050
MF		 1265#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1266 if (__SILICON_REVISION__ < 3) {
1267 /*
1268 * This isn't publicly documented (fun times!), but in
1269 * silicon <=0.2, the RX and TX pins are clocked together.
1270 * So in order to recv, we must enable the transmit side
1271 * as well. This will cause a spurious TX interrupt too,
1272 * but we can easily consume that.
1273 */
1274 opmode |= TE;
1275 }
e190d6b1 1276#endif
02460d08
SZ		 1277 }
1278
e190d6b1
BW		 1279 /* Turn on the EMAC rx */
1280 bfin_write_EMAC_OPMODE(opmode);
2bfa0f0c
MF		 1281
1282 return 0;
e190d6b1
BW		 1283}
1284
1285/* Our watchdog timed out. Called by the networking layer */
7ef0a7ee 1286static void bfin_mac_timeout(struct net_device *dev)
e190d6b1 1287{
4fcc3d34
SZ		 1288 struct bfin_mac_local *lp = netdev_priv(dev);
1289
b39d66a8 1290 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1 1291
7ef0a7ee 1292 bfin_mac_disable();
e190d6b1 1293
4fcc3d34
SZ		 1294 del_timer(&lp->tx_reclaim_timer);
1295
1296 /* reset tx queue and free skb */
1297 while (tx_list_head != current_tx_ptr) {
1298 tx_list_head->desc_a.config &= ~DMAEN;
1299 tx_list_head->status.status_word = 0;
1300 if (tx_list_head->skb) {
1301 dev_kfree_skb(tx_list_head->skb);
1302 tx_list_head->skb = NULL;
1303 }
1304 tx_list_head = tx_list_head->next;
1305 }
1306
1307 if (netif_queue_stopped(lp->ndev))
1308 netif_wake_queue(lp->ndev);
e190d6b1 1309
02460d08 1310 bfin_mac_enable(lp->phydev);
e190d6b1
BW		 1311
1312 /* We can accept TX packets again */
1ae5dc34 1313 dev->trans_start = jiffies; /* prevent tx timeout */
e190d6b1
BW		 1314 netif_wake_queue(dev);
1315}
1316
7ef0a7ee 1317static void bfin_mac_multicast_hash(struct net_device *dev)
775919bc
AW		 1318{
1319 u32 emac_hashhi, emac_hashlo;
22bedad3 1320 struct netdev_hw_addr *ha;
775919bc
AW		 1321 u32 crc;
1322
1323 emac_hashhi = emac_hashlo = 0;
1324
22bedad3 1325 netdev_for_each_mc_addr(ha, dev) {
f767b6df 1326 crc = ether_crc(ETH_ALEN, ha->addr);
775919bc
AW		 1327 crc >>= 26;
1328
1329 if (crc & 0x20)
1330 emac_hashhi |= 1 << (crc & 0x1f);
1331 else
1332 emac_hashlo |= 1 << (crc & 0x1f);
1333 }
1334
1335 bfin_write_EMAC_HASHHI(emac_hashhi);
1336 bfin_write_EMAC_HASHLO(emac_hashlo);
775919bc
AW		 1337}
1338
e190d6b1
BW		 1339/*
1340 * This routine will, depending on the values passed to it,
1341 * either make it accept multicast packets, go into
1342 * promiscuous mode (for TCPDUMP and cousins) or accept
1343 * a select set of multicast packets
1344 */
7ef0a7ee 1345static void bfin_mac_set_multicast_list(struct net_device *dev)
e190d6b1
BW		 1346{
1347 u32 sysctl;
1348
1349 if (dev->flags & IFF_PROMISC) {
c6dd5098 1350 netdev_info(dev, "set promisc mode\n");
e190d6b1 1351 sysctl = bfin_read_EMAC_OPMODE();
c0da776b 1352 sysctl |= PR;
e190d6b1 1353 bfin_write_EMAC_OPMODE(sysctl);
775919bc 1354 } else if (dev->flags & IFF_ALLMULTI) {
e190d6b1
BW		 1355 /* accept all multicast */
1356 sysctl = bfin_read_EMAC_OPMODE();
1357 sysctl |= PAM;
1358 bfin_write_EMAC_OPMODE(sysctl);
4cd24eaf 1359 } else if (!netdev_mc_empty(dev)) {
775919bc
AW		 1360 /* set up multicast hash table */
1361 sysctl = bfin_read_EMAC_OPMODE();
1362 sysctl |= HM;
1363 bfin_write_EMAC_OPMODE(sysctl);
7ef0a7ee 1364 bfin_mac_multicast_hash(dev);
e190d6b1
BW		 1365 } else {
1366 /* clear promisc or multicast mode */
1367 sysctl = bfin_read_EMAC_OPMODE();
1368 sysctl &= ~(RAF | PAM);
1369 bfin_write_EMAC_OPMODE(sysctl);
1370 }
1371}
1372
fe92afed
BS		 1373static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1374{
02460d08
SZ		 1375 struct bfin_mac_local *lp = netdev_priv(netdev);
1376
1377 if (!netif_running(netdev))
1378 return -EINVAL;
1379
fe92afed
BS		 1380 switch (cmd) {
1381 case SIOCSHWTSTAMP:
1382 return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1383 default:
02460d08
SZ		 1384 if (lp->phydev)
1385 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1386 else
1387 return -EOPNOTSUPP;
fe92afed
BS		 1388 }
1389}
1390
e190d6b1
BW		 1391/*
1392 * this puts the device in an inactive state
1393 */
7ef0a7ee 1394static void bfin_mac_shutdown(struct net_device *dev)
e190d6b1
BW		 1395{
1396 /* Turn off the EMAC */
1397 bfin_write_EMAC_OPMODE(0x00000000);
1398 /* Turn off the EMAC RX DMA */
1399 bfin_write_DMA1_CONFIG(0x0000);
1400 bfin_write_DMA2_CONFIG(0x0000);
1401}
1402
1403/*
1404 * Open and Initialize the interface
1405 *
1406 * Set up everything, reset the card, etc..
1407 */
7ef0a7ee 1408static int bfin_mac_open(struct net_device *dev)
e190d6b1 1409{
7ef0a7ee 1410 struct bfin_mac_local *lp = netdev_priv(dev);
2bfa0f0c 1411 int ret;
b39d66a8 1412 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1413
1414 /*
1415 * Check that the address is valid. If its not, refuse
1416 * to bring the device up. The user must specify an
1417 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1418 */
1419 if (!is_valid_ether_addr(dev->dev_addr)) {
c6dd5098 1420 netdev_warn(dev, "no valid ethernet hw addr\n");
e190d6b1
BW		 1421 return -EINVAL;
1422 }
1423
1424 /* initial rx and tx list */
1ab0d2ec 1425 ret = desc_list_init(dev);
2bfa0f0c
MF		 1426 if (ret)
1427 return ret;
e190d6b1 1428
4ae5a3ad 1429 phy_start(lp->phydev);
136492b2 1430 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
e190d6b1 1431 setup_system_regs(dev);
ee02fee8 1432 setup_mac_addr(dev->dev_addr);
2bfa0f0c 1433
7ef0a7ee 1434 bfin_mac_disable();
02460d08 1435 ret = bfin_mac_enable(lp->phydev);
2bfa0f0c
MF		 1436 if (ret)
1437 return ret;
e190d6b1 1438 pr_debug("hardware init finished\n");
2bfa0f0c 1439
e190d6b1
BW		 1440 netif_start_queue(dev);
1441 netif_carrier_on(dev);
1442
1443 return 0;
1444}
1445
1446/*
e190d6b1
BW		 1447 * this makes the board clean up everything that it can
1448 * and not talk to the outside world. Caused by
1449 * an 'ifconfig ethX down'
1450 */
7ef0a7ee 1451static int bfin_mac_close(struct net_device *dev)
e190d6b1 1452{
7ef0a7ee 1453 struct bfin_mac_local *lp = netdev_priv(dev);
b39d66a8 1454 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1455
1456 netif_stop_queue(dev);
1457 netif_carrier_off(dev);
1458
4ae5a3ad 1459 phy_stop(lp->phydev);
136492b2 1460 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
4ae5a3ad 1461
e190d6b1 1462 /* clear everything */
7ef0a7ee 1463 bfin_mac_shutdown(dev);
e190d6b1
BW		 1464
1465 /* free the rx/tx buffers */
1466 desc_list_free();
1467
1468 return 0;
1469}
1470
b63dc8fe
MF		 1471static const struct net_device_ops bfin_mac_netdev_ops = {
1472 .ndo_open = bfin_mac_open,
1473 .ndo_stop = bfin_mac_close,
1474 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1475 .ndo_set_mac_address = bfin_mac_set_mac_address,
1476 .ndo_tx_timeout = bfin_mac_timeout,
afc4b13d 1477 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
fe92afed 1478 .ndo_do_ioctl = bfin_mac_ioctl,
b63dc8fe
MF		 1479 .ndo_validate_addr = eth_validate_addr,
1480 .ndo_change_mtu = eth_change_mtu,
1481#ifdef CONFIG_NET_POLL_CONTROLLER
1482 .ndo_poll_controller = bfin_mac_poll,
1483#endif
1484};
1485
d7b843d3 1486static int __devinit bfin_mac_probe(struct platform_device *pdev)
e190d6b1 1487{
7ef0a7ee
BW		 1488 struct net_device *ndev;
1489 struct bfin_mac_local *lp;
080c8255 1490 struct platform_device *pd;
02460d08 1491 struct bfin_mii_bus_platform_data *mii_bus_data;
080c8255 1492 int rc;
7ef0a7ee
BW		 1493
1494 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
41de8d4c 1495 if (!ndev)
7ef0a7ee 1496 return -ENOMEM;
7ef0a7ee
BW		 1497
1498 SET_NETDEV_DEV(ndev, &pdev->dev);
1499 platform_set_drvdata(pdev, ndev);
1500 lp = netdev_priv(ndev);
4fcc3d34 1501 lp->ndev = ndev;
e190d6b1
BW		 1502
1503 /* Grab the MAC address in the MAC */
7ef0a7ee
BW		 1504 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1505 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
e190d6b1
BW		 1506
1507 /* probe mac */
1508 /*todo: how to proble? which is revision_register */
1509 bfin_write_EMAC_ADDRLO(0x12345678);
1510 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
7ef0a7ee
BW		 1511 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1512 rc = -ENODEV;
1513 goto out_err_probe_mac;
e190d6b1
BW		 1514 }
1515
e190d6b1 1516
7ef0a7ee
BW		 1517 /*
1518 * Is it valid? (Did bootloader initialize it?)
1519 * Grab the MAC from the board somehow
1520 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1521 */
5055d2f2
DK		 1522 if (!is_valid_ether_addr(ndev->dev_addr)) {
1523 if (bfin_get_ether_addr(ndev->dev_addr) ||
1524 !is_valid_ether_addr(ndev->dev_addr)) {
1525 /* Still not valid, get a random one */
1526 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1527 eth_hw_addr_random(ndev);
1528 }
1529 }
e190d6b1 1530
7ef0a7ee 1531 setup_mac_addr(ndev->dev_addr);
e190d6b1 1532
080c8255
GY		 1533 if (!pdev->dev.platform_data) {
1534 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1535 rc = -ENODEV;
1536 goto out_err_probe_mac;
7ef0a7ee 1537 }
080c8255
GY		 1538 pd = pdev->dev.platform_data;
1539 lp->mii_bus = platform_get_drvdata(pd);
0e995cd3
SZ		 1540 if (!lp->mii_bus) {
1541 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1542 rc = -ENODEV;
02460d08 1543 goto out_err_probe_mac;
0e995cd3 1544 }
080c8255 1545 lp->mii_bus->priv = ndev;
02460d08 1546 mii_bus_data = pd->dev.platform_data;
4ae5a3ad 1547
02460d08 1548 rc = mii_probe(ndev, mii_bus_data->phy_mode);
7ef0a7ee
BW		 1549 if (rc) {
1550 dev_err(&pdev->dev, "MII Probe failed!\n");
1551 goto out_err_mii_probe;
1552 }
4ae5a3ad 1553
c599bd6b
MF		 1554 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1555 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1556
e190d6b1 1557 /* Fill in the fields of the device structure with ethernet values. */
7ef0a7ee
BW		 1558 ether_setup(ndev);
1559
149da651 1560 ndev->netdev_ops = &bfin_mac_netdev_ops;
679dce39 1561 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
e190d6b1 1562
4fcc3d34
SZ		 1563 init_timer(&lp->tx_reclaim_timer);
1564 lp->tx_reclaim_timer.data = (unsigned long)lp;
1565 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1566
e190d6b1
BW		 1567 spin_lock_init(&lp->lock);
1568
1569 /* now, enable interrupts */
1570 /* register irq handler */
7ef0a7ee 1571 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
91a455f0 1572 IRQF_DISABLED, "EMAC_RX", ndev);
7ef0a7ee
BW		 1573 if (rc) {
1574 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1575 rc = -EBUSY;
1576 goto out_err_request_irq;
e190d6b1
BW		 1577 }
1578
7ef0a7ee
BW		 1579 rc = register_netdev(ndev);
1580 if (rc) {
1581 dev_err(&pdev->dev, "Cannot register net device!\n");
1582 goto out_err_reg_ndev;
e190d6b1
BW		 1583 }
1584
fe92afed
BS		 1585 bfin_mac_hwtstamp_init(ndev);
1586
7ef0a7ee 1587 /* now, print out the card info, in a short format.. */
c6dd5098 1588 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
e190d6b1 1589
7ef0a7ee 1590 return 0;
e190d6b1 1591
7ef0a7ee
BW		 1592out_err_reg_ndev:
1593 free_irq(IRQ_MAC_RX, ndev);
1594out_err_request_irq:
1595out_err_mii_probe:
298cf9be 1596 mdiobus_unregister(lp->mii_bus);
298cf9be 1597 mdiobus_free(lp->mii_bus);
7ef0a7ee
BW		 1598out_err_probe_mac:
1599 platform_set_drvdata(pdev, NULL);
1600 free_netdev(ndev);
e190d6b1 1601
7ef0a7ee 1602 return rc;
e190d6b1
BW		 1603}
1604
d7b843d3 1605static int __devexit bfin_mac_remove(struct platform_device *pdev)
e190d6b1
BW		 1606{
1607 struct net_device *ndev = platform_get_drvdata(pdev);
7ef0a7ee 1608 struct bfin_mac_local *lp = netdev_priv(ndev);
e190d6b1
BW		 1609
1610 platform_set_drvdata(pdev, NULL);
1611
080c8255 1612 lp->mii_bus->priv = NULL;
7ef0a7ee 1613
e190d6b1
BW		 1614 unregister_netdev(ndev);
1615
1616 free_irq(IRQ_MAC_RX, ndev);
1617
1618 free_netdev(ndev);
1619
e190d6b1
BW		 1620 return 0;
1621}
1622
496a34c2
BW		 1623#ifdef CONFIG_PM
1624static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
e190d6b1 1625{
496a34c2 1626 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1627 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1628
53fd3f28
MH		 1629 if (lp->wol) {
1630 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1631 bfin_write_EMAC_WKUP_CTL(MPKE);
1632 enable_irq_wake(IRQ_MAC_WAKEDET);
1633 } else {
1634 if (netif_running(net_dev))
1635 bfin_mac_close(net_dev);
1636 }
496a34c2 1637
e190d6b1
BW		 1638 return 0;
1639}
1640
1641static int bfin_mac_resume(struct platform_device *pdev)
1642{
496a34c2 1643 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1644 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1645
53fd3f28
MH		 1646 if (lp->wol) {
1647 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1648 bfin_write_EMAC_WKUP_CTL(0);
1649 disable_irq_wake(IRQ_MAC_WAKEDET);
1650 } else {
1651 if (netif_running(net_dev))
1652 bfin_mac_open(net_dev);
1653 }
496a34c2 1654
e190d6b1
BW		 1655 return 0;
1656}
496a34c2
BW		 1657#else
1658#define bfin_mac_suspend NULL
1659#define bfin_mac_resume NULL
1660#endif /* CONFIG_PM */
e190d6b1 1661
080c8255
GY		 1662static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1663{
1664 struct mii_bus *miibus;
02460d08
SZ		 1665 struct bfin_mii_bus_platform_data *mii_bus_pd;
1666 const unsigned short *pin_req;
080c8255
GY		 1667 int rc, i;
1668
02460d08
SZ		 1669 mii_bus_pd = dev_get_platdata(&pdev->dev);
1670 if (!mii_bus_pd) {
1671 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1672 return -EINVAL;
1673 }
1674
080c8255
GY		 1675 /*
1676 * We are setting up a network card,
1677 * so set the GPIO pins to Ethernet mode
1678 */
02460d08 1679 pin_req = mii_bus_pd->mac_peripherals;
c6dd5098 1680 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
080c8255
GY		 1681 if (rc) {
1682 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1683 return rc;
1684 }
1685
1686 rc = -ENOMEM;
1687 miibus = mdiobus_alloc();
1688 if (miibus == NULL)
1689 goto out_err_alloc;
1690 miibus->read = bfin_mdiobus_read;
1691 miibus->write = bfin_mdiobus_write;
1692 miibus->reset = bfin_mdiobus_reset;
1693
1694 miibus->parent = &pdev->dev;
1695 miibus->name = "bfin_mii_bus";
02460d08
SZ		 1696 miibus->phy_mask = mii_bus_pd->phy_mask;
1697
75432fd2
FF		 1698 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1699 pdev->name, pdev->id);
080c8255 1700 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
02460d08
SZ		 1701 if (!miibus->irq)
1702 goto out_err_irq_alloc;
1703
1704 for (i = rc; i < PHY_MAX_ADDR; ++i)
080c8255
GY		 1705 miibus->irq[i] = PHY_POLL;
1706
02460d08
SZ		 1707 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1708 if (rc != mii_bus_pd->phydev_number)
1709 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1710 mii_bus_pd->phydev_number);
1711 for (i = 0; i < rc; ++i) {
1712 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1713 if (phyaddr < PHY_MAX_ADDR)
1714 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1715 else
1716 dev_err(&pdev->dev,
1717 "Invalid PHY address %i for phydev %i\n",
1718 phyaddr, i);
1719 }
1720
080c8255
GY		 1721 rc = mdiobus_register(miibus);
1722 if (rc) {
1723 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1724 goto out_err_mdiobus_register;
1725 }
1726
1727 platform_set_drvdata(pdev, miibus);
1728 return 0;
1729
1730out_err_mdiobus_register:
7f267de4 1731 kfree(miibus->irq);
02460d08 1732out_err_irq_alloc:
080c8255
GY		 1733 mdiobus_free(miibus);
1734out_err_alloc:
1735 peripheral_free_list(pin_req);
1736
1737 return rc;
1738}
1739
1740static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1741{
1742 struct mii_bus *miibus = platform_get_drvdata(pdev);
02460d08
SZ		 1743 struct bfin_mii_bus_platform_data *mii_bus_pd =
1744 dev_get_platdata(&pdev->dev);
1745
080c8255
GY		 1746 platform_set_drvdata(pdev, NULL);
1747 mdiobus_unregister(miibus);
7f267de4 1748 kfree(miibus->irq);
080c8255 1749 mdiobus_free(miibus);
02460d08
SZ		 1750 peripheral_free_list(mii_bus_pd->mac_peripherals);
1751
080c8255
GY		 1752 return 0;
1753}
1754
1755static struct platform_driver bfin_mii_bus_driver = {
1756 .probe = bfin_mii_bus_probe,
1757 .remove = __devexit_p(bfin_mii_bus_remove),
1758 .driver = {
1759 .name = "bfin_mii_bus",
1760 .owner = THIS_MODULE,
1761 },
1762};
1763
e190d6b1
BW		 1764static struct platform_driver bfin_mac_driver = {
1765 .probe = bfin_mac_probe,
d7b843d3 1766 .remove = __devexit_p(bfin_mac_remove),
e190d6b1
BW		 1767 .resume = bfin_mac_resume,
1768 .suspend = bfin_mac_suspend,
1769 .driver = {
c6dd5098 1770 .name = KBUILD_MODNAME,
72abb461
KS		 1771 .owner = THIS_MODULE,
1772 },
e190d6b1
BW		 1773};
1774
1775static int __init bfin_mac_init(void)
1776{
080c8255
GY		 1777 int ret;
1778 ret = platform_driver_register(&bfin_mii_bus_driver);
1779 if (!ret)
1780 return platform_driver_register(&bfin_mac_driver);
1781 return -ENODEV;
e190d6b1
BW		 1782}
1783
1784module_init(bfin_mac_init);
1785
1786static void __exit bfin_mac_cleanup(void)
1787{
1788 platform_driver_unregister(&bfin_mac_driver);
080c8255 1789 platform_driver_unregister(&bfin_mii_bus_driver);
e190d6b1
BW		 1790}
1791
1792module_exit(bfin_mac_cleanup);
72abb461 1793
Linux kernel - Deliverables
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