Commit | Line | Data |
---|---|---|
e190d6b1 | 1 | /* |
2fb9d6f5 | 2 | * Blackfin On-Chip MAC Driver |
e190d6b1 | 3 | * |
02460d08 | 4 | * Copyright 2004-2010 Analog Devices Inc. |
e190d6b1 | 5 | * |
2fb9d6f5 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
e190d6b1 | 7 | * |
2fb9d6f5 | 8 | * Licensed under the GPL-2 or later. |
e190d6b1 BW |
9 | */ |
10 | ||
c6dd5098 MF |
11 | #define DRV_VERSION "1.1" |
12 | #define DRV_DESC "Blackfin on-chip Ethernet MAC driver" | |
13 | ||
14 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
15 | ||
e190d6b1 BW |
16 | #include <linux/init.h> |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/sched.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/timer.h> | |
23 | #include <linux/errno.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/ioport.h> | |
27 | #include <linux/crc32.h> | |
28 | #include <linux/device.h> | |
29 | #include <linux/spinlock.h> | |
e190d6b1 | 30 | #include <linux/mii.h> |
e190d6b1 BW |
31 | #include <linux/netdevice.h> |
32 | #include <linux/etherdevice.h> | |
679dce39 | 33 | #include <linux/ethtool.h> |
e190d6b1 | 34 | #include <linux/skbuff.h> |
e190d6b1 | 35 | #include <linux/platform_device.h> |
e190d6b1 BW |
36 | |
37 | #include <asm/dma.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | ||
fe92afed | 40 | #include <asm/div64.h> |
98f672ca | 41 | #include <asm/dpmc.h> |
e190d6b1 BW |
42 | #include <asm/blackfin.h> |
43 | #include <asm/cacheflush.h> | |
44 | #include <asm/portmux.h> | |
3dcc1e7f | 45 | #include <mach/pll.h> |
e190d6b1 BW |
46 | |
47 | #include "bfin_mac.h" | |
48 | ||
c6dd5098 | 49 | MODULE_AUTHOR("Bryan Wu, Luke Yang"); |
e190d6b1 BW |
50 | MODULE_LICENSE("GPL"); |
51 | MODULE_DESCRIPTION(DRV_DESC); | |
72abb461 | 52 | MODULE_ALIAS("platform:bfin_mac"); |
e190d6b1 BW |
53 | |
54 | #if defined(CONFIG_BFIN_MAC_USE_L1) | |
118133e6 SZ |
55 | # define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num) |
56 | # define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr) | |
e190d6b1 | 57 | #else |
118133e6 SZ |
58 | # define bfin_mac_alloc(dma_handle, size, num) \ |
59 | dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL) | |
60 | # define bfin_mac_free(dma_handle, ptr, num) \ | |
61 | dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle) | |
e190d6b1 BW |
62 | #endif |
63 | ||
64 | #define PKT_BUF_SZ 1580 | |
65 | ||
66 | #define MAX_TIMEOUT_CNT 500 | |
67 | ||
68 | /* pointers to maintain transmit list */ | |
69 | static struct net_dma_desc_tx *tx_list_head; | |
70 | static struct net_dma_desc_tx *tx_list_tail; | |
71 | static struct net_dma_desc_rx *rx_list_head; | |
72 | static struct net_dma_desc_rx *rx_list_tail; | |
73 | static struct net_dma_desc_rx *current_rx_ptr; | |
74 | static struct net_dma_desc_tx *current_tx_ptr; | |
75 | static struct net_dma_desc_tx *tx_desc; | |
76 | static struct net_dma_desc_rx *rx_desc; | |
77 | ||
78 | static void desc_list_free(void) | |
79 | { | |
80 | struct net_dma_desc_rx *r; | |
81 | struct net_dma_desc_tx *t; | |
82 | int i; | |
83 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
84 | dma_addr_t dma_handle = 0; | |
85 | #endif | |
86 | ||
87 | if (tx_desc) { | |
88 | t = tx_list_head; | |
89 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
90 | if (t) { | |
91 | if (t->skb) { | |
92 | dev_kfree_skb(t->skb); | |
93 | t->skb = NULL; | |
94 | } | |
95 | t = t->next; | |
96 | } | |
97 | } | |
118133e6 | 98 | bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM); |
e190d6b1 BW |
99 | } |
100 | ||
101 | if (rx_desc) { | |
102 | r = rx_list_head; | |
103 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
104 | if (r) { | |
105 | if (r->skb) { | |
106 | dev_kfree_skb(r->skb); | |
107 | r->skb = NULL; | |
108 | } | |
109 | r = r->next; | |
110 | } | |
111 | } | |
118133e6 | 112 | bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM); |
e190d6b1 BW |
113 | } |
114 | } | |
115 | ||
1ab0d2ec | 116 | static int desc_list_init(struct net_device *dev) |
e190d6b1 BW |
117 | { |
118 | int i; | |
119 | struct sk_buff *new_skb; | |
120 | #if !defined(CONFIG_BFIN_MAC_USE_L1) | |
121 | /* | |
122 | * This dma_handle is useless in Blackfin dma_alloc_coherent(). | |
123 | * The real dma handler is the return value of dma_alloc_coherent(). | |
124 | */ | |
125 | dma_addr_t dma_handle; | |
126 | #endif | |
127 | ||
128 | tx_desc = bfin_mac_alloc(&dma_handle, | |
118133e6 | 129 | sizeof(struct net_dma_desc_tx), |
e190d6b1 BW |
130 | CONFIG_BFIN_TX_DESC_NUM); |
131 | if (tx_desc == NULL) | |
132 | goto init_error; | |
133 | ||
134 | rx_desc = bfin_mac_alloc(&dma_handle, | |
118133e6 | 135 | sizeof(struct net_dma_desc_rx), |
e190d6b1 BW |
136 | CONFIG_BFIN_RX_DESC_NUM); |
137 | if (rx_desc == NULL) | |
138 | goto init_error; | |
139 | ||
140 | /* init tx_list */ | |
141 | tx_list_head = tx_list_tail = tx_desc; | |
142 | ||
143 | for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) { | |
144 | struct net_dma_desc_tx *t = tx_desc + i; | |
145 | struct dma_descriptor *a = &(t->desc_a); | |
146 | struct dma_descriptor *b = &(t->desc_b); | |
147 | ||
148 | /* | |
149 | * disable DMA | |
150 | * read from memory WNR = 0 | |
151 | * wordsize is 32 bits | |
152 | * 6 half words is desc size | |
153 | * large desc flow | |
154 | */ | |
155 | a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
156 | a->start_addr = (unsigned long)t->packet; | |
157 | a->x_count = 0; | |
158 | a->next_dma_desc = b; | |
159 | ||
160 | /* | |
161 | * enabled DMA | |
162 | * write to memory WNR = 1 | |
163 | * wordsize is 32 bits | |
164 | * disable interrupt | |
165 | * 6 half words is desc size | |
166 | * large desc flow | |
167 | */ | |
168 | b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
169 | b->start_addr = (unsigned long)(&(t->status)); | |
170 | b->x_count = 0; | |
171 | ||
172 | t->skb = NULL; | |
173 | tx_list_tail->desc_b.next_dma_desc = a; | |
174 | tx_list_tail->next = t; | |
175 | tx_list_tail = t; | |
176 | } | |
177 | tx_list_tail->next = tx_list_head; /* tx_list is a circle */ | |
178 | tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a); | |
179 | current_tx_ptr = tx_list_head; | |
180 | ||
181 | /* init rx_list */ | |
182 | rx_list_head = rx_list_tail = rx_desc; | |
183 | ||
184 | for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) { | |
185 | struct net_dma_desc_rx *r = rx_desc + i; | |
186 | struct dma_descriptor *a = &(r->desc_a); | |
187 | struct dma_descriptor *b = &(r->desc_b); | |
188 | ||
189 | /* allocate a new skb for next time receive */ | |
1ab0d2ec | 190 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 | 191 | if (!new_skb) { |
c6dd5098 | 192 | pr_notice("init: low on mem - packet dropped\n"); |
e190d6b1 BW |
193 | goto init_error; |
194 | } | |
015dac88 | 195 | skb_reserve(new_skb, NET_IP_ALIGN); |
f6e1e4f3 SZ |
196 | /* Invidate the data cache of skb->data range when it is write back |
197 | * cache. It will prevent overwritting the new data from DMA | |
198 | */ | |
199 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
200 | (unsigned long)new_skb->end); | |
e190d6b1 BW |
201 | r->skb = new_skb; |
202 | ||
203 | /* | |
204 | * enabled DMA | |
205 | * write to memory WNR = 1 | |
206 | * wordsize is 32 bits | |
207 | * disable interrupt | |
208 | * 6 half words is desc size | |
209 | * large desc flow | |
210 | */ | |
211 | a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE; | |
212 | /* since RXDWA is enabled */ | |
213 | a->start_addr = (unsigned long)new_skb->data - 2; | |
214 | a->x_count = 0; | |
215 | a->next_dma_desc = b; | |
216 | ||
217 | /* | |
218 | * enabled DMA | |
219 | * write to memory WNR = 1 | |
220 | * wordsize is 32 bits | |
221 | * enable interrupt | |
222 | * 6 half words is desc size | |
223 | * large desc flow | |
224 | */ | |
225 | b->config = DMAEN | WNR | WDSIZE_32 | DI_EN | | |
226 | NDSIZE_6 | DMAFLOW_LARGE; | |
227 | b->start_addr = (unsigned long)(&(r->status)); | |
228 | b->x_count = 0; | |
229 | ||
230 | rx_list_tail->desc_b.next_dma_desc = a; | |
231 | rx_list_tail->next = r; | |
232 | rx_list_tail = r; | |
233 | } | |
234 | rx_list_tail->next = rx_list_head; /* rx_list is a circle */ | |
235 | rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a); | |
236 | current_rx_ptr = rx_list_head; | |
237 | ||
238 | return 0; | |
239 | ||
240 | init_error: | |
241 | desc_list_free(); | |
c6dd5098 | 242 | pr_err("kmalloc failed\n"); |
e190d6b1 BW |
243 | return -ENOMEM; |
244 | } | |
245 | ||
246 | ||
247 | /*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/ | |
248 | ||
4ae5a3ad BW |
249 | /* |
250 | * MII operations | |
251 | */ | |
e190d6b1 | 252 | /* Wait until the previous MDC/MDIO transaction has completed */ |
2bfa0f0c | 253 | static int bfin_mdio_poll(void) |
e190d6b1 BW |
254 | { |
255 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
256 | ||
257 | /* poll the STABUSY bit */ | |
258 | while ((bfin_read_EMAC_STAADD()) & STABUSY) { | |
6db9e461 | 259 | udelay(1); |
e190d6b1 | 260 | if (timeout_cnt-- < 0) { |
c6dd5098 | 261 | pr_err("wait MDC/MDIO transaction to complete timeout\n"); |
2bfa0f0c | 262 | return -ETIMEDOUT; |
e190d6b1 BW |
263 | } |
264 | } | |
2bfa0f0c MF |
265 | |
266 | return 0; | |
e190d6b1 BW |
267 | } |
268 | ||
269 | /* Read an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e | 270 | static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
e190d6b1 | 271 | { |
2bfa0f0c MF |
272 | int ret; |
273 | ||
274 | ret = bfin_mdio_poll(); | |
275 | if (ret) | |
276 | return ret; | |
4ae5a3ad | 277 | |
e190d6b1 | 278 | /* read mode */ |
4ae5a3ad BW |
279 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
280 | SET_REGAD((u16) regnum) | | |
e190d6b1 | 281 | STABUSY); |
e190d6b1 | 282 | |
2bfa0f0c MF |
283 | ret = bfin_mdio_poll(); |
284 | if (ret) | |
285 | return ret; | |
4ae5a3ad BW |
286 | |
287 | return (int) bfin_read_EMAC_STADAT(); | |
e190d6b1 BW |
288 | } |
289 | ||
290 | /* Write an off-chip register in a PHY through the MDC/MDIO port */ | |
0ed0563e AB |
291 | static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
292 | u16 value) | |
e190d6b1 | 293 | { |
2bfa0f0c MF |
294 | int ret; |
295 | ||
296 | ret = bfin_mdio_poll(); | |
297 | if (ret) | |
298 | return ret; | |
4ae5a3ad BW |
299 | |
300 | bfin_write_EMAC_STADAT((u32) value); | |
e190d6b1 BW |
301 | |
302 | /* write mode */ | |
4ae5a3ad BW |
303 | bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) | |
304 | SET_REGAD((u16) regnum) | | |
e190d6b1 BW |
305 | STAOP | |
306 | STABUSY); | |
307 | ||
2bfa0f0c | 308 | return bfin_mdio_poll(); |
e190d6b1 BW |
309 | } |
310 | ||
0ed0563e | 311 | static int bfin_mdiobus_reset(struct mii_bus *bus) |
e190d6b1 | 312 | { |
4ae5a3ad | 313 | return 0; |
e190d6b1 BW |
314 | } |
315 | ||
7ef0a7ee | 316 | static void bfin_mac_adjust_link(struct net_device *dev) |
e190d6b1 | 317 | { |
7ef0a7ee | 318 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
319 | struct phy_device *phydev = lp->phydev; |
320 | unsigned long flags; | |
321 | int new_state = 0; | |
322 | ||
323 | spin_lock_irqsave(&lp->lock, flags); | |
324 | if (phydev->link) { | |
325 | /* Now we make sure that we can be in full duplex mode. | |
326 | * If not, we operate in half-duplex mode. */ | |
327 | if (phydev->duplex != lp->old_duplex) { | |
328 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
329 | new_state = 1; | |
330 | ||
331 | if (phydev->duplex) | |
332 | opmode |= FDMODE; | |
333 | else | |
334 | opmode &= ~(FDMODE); | |
335 | ||
336 | bfin_write_EMAC_OPMODE(opmode); | |
337 | lp->old_duplex = phydev->duplex; | |
338 | } | |
e190d6b1 | 339 | |
4ae5a3ad | 340 | if (phydev->speed != lp->old_speed) { |
02460d08 SZ |
341 | if (phydev->interface == PHY_INTERFACE_MODE_RMII) { |
342 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
343 | switch (phydev->speed) { | |
344 | case 10: | |
345 | opmode |= RMII_10; | |
346 | break; | |
347 | case 100: | |
348 | opmode &= ~RMII_10; | |
349 | break; | |
350 | default: | |
c6dd5098 MF |
351 | netdev_warn(dev, |
352 | "Ack! Speed (%d) is not 10/100!\n", | |
353 | phydev->speed); | |
02460d08 SZ |
354 | break; |
355 | } | |
356 | bfin_write_EMAC_OPMODE(opmode); | |
4ae5a3ad | 357 | } |
e190d6b1 | 358 | |
4ae5a3ad BW |
359 | new_state = 1; |
360 | lp->old_speed = phydev->speed; | |
361 | } | |
e190d6b1 | 362 | |
4ae5a3ad BW |
363 | if (!lp->old_link) { |
364 | new_state = 1; | |
365 | lp->old_link = 1; | |
4ae5a3ad BW |
366 | } |
367 | } else if (lp->old_link) { | |
368 | new_state = 1; | |
369 | lp->old_link = 0; | |
370 | lp->old_speed = 0; | |
371 | lp->old_duplex = -1; | |
e190d6b1 BW |
372 | } |
373 | ||
4ae5a3ad BW |
374 | if (new_state) { |
375 | u32 opmode = bfin_read_EMAC_OPMODE(); | |
376 | phy_print_status(phydev); | |
377 | pr_debug("EMAC_OPMODE = 0x%08x\n", opmode); | |
e190d6b1 | 378 | } |
4ae5a3ad BW |
379 | |
380 | spin_unlock_irqrestore(&lp->lock, flags); | |
e190d6b1 BW |
381 | } |
382 | ||
7cc8f381 BW |
383 | /* MDC = 2.5 MHz */ |
384 | #define MDC_CLK 2500000 | |
385 | ||
02460d08 | 386 | static int mii_probe(struct net_device *dev, int phy_mode) |
e190d6b1 | 387 | { |
7ef0a7ee | 388 | struct bfin_mac_local *lp = netdev_priv(dev); |
4ae5a3ad BW |
389 | struct phy_device *phydev = NULL; |
390 | unsigned short sysctl; | |
391 | int i; | |
7cc8f381 | 392 | u32 sclk, mdc_div; |
e190d6b1 | 393 | |
4ae5a3ad | 394 | /* Enable PHY output early */ |
98f672ca MF |
395 | if (!(bfin_read_VR_CTL() & CLKBUFOE)) |
396 | bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); | |
e190d6b1 | 397 | |
7cc8f381 BW |
398 | sclk = get_sclk(); |
399 | mdc_div = ((sclk / MDC_CLK) / 2) - 1; | |
400 | ||
4ae5a3ad | 401 | sysctl = bfin_read_EMAC_SYSCTL(); |
9dc7f30e | 402 | sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div); |
e190d6b1 | 403 | bfin_write_EMAC_SYSCTL(sysctl); |
e190d6b1 | 404 | |
02460d08 SZ |
405 | /* search for connected PHY device */ |
406 | for (i = 0; i < PHY_MAX_ADDR; ++i) { | |
298cf9be | 407 | struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i]; |
e190d6b1 | 408 | |
4ae5a3ad BW |
409 | if (!tmp_phydev) |
410 | continue; /* no PHY here... */ | |
e190d6b1 | 411 | |
4ae5a3ad BW |
412 | phydev = tmp_phydev; |
413 | break; /* found it */ | |
414 | } | |
415 | ||
416 | /* now we are supposed to have a proper phydev, to attach to... */ | |
417 | if (!phydev) { | |
c6dd5098 | 418 | netdev_err(dev, "no phy device found\n"); |
4ae5a3ad | 419 | return -ENODEV; |
e190d6b1 BW |
420 | } |
421 | ||
02460d08 SZ |
422 | if (phy_mode != PHY_INTERFACE_MODE_RMII && |
423 | phy_mode != PHY_INTERFACE_MODE_MII) { | |
c6dd5098 | 424 | netdev_err(dev, "invalid phy interface mode\n"); |
02460d08 SZ |
425 | return -EINVAL; |
426 | } | |
427 | ||
c2313557 | 428 | phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link, |
02460d08 | 429 | 0, phy_mode); |
e190d6b1 | 430 | |
4ae5a3ad | 431 | if (IS_ERR(phydev)) { |
c6dd5098 | 432 | netdev_err(dev, "could not attach PHY\n"); |
4ae5a3ad BW |
433 | return PTR_ERR(phydev); |
434 | } | |
435 | ||
436 | /* mask with MAC supported features */ | |
437 | phydev->supported &= (SUPPORTED_10baseT_Half | |
438 | | SUPPORTED_10baseT_Full | |
439 | | SUPPORTED_100baseT_Half | |
440 | | SUPPORTED_100baseT_Full | |
441 | | SUPPORTED_Autoneg | |
442 | | SUPPORTED_Pause | SUPPORTED_Asym_Pause | |
443 | | SUPPORTED_MII | |
444 | | SUPPORTED_TP); | |
445 | ||
446 | phydev->advertising = phydev->supported; | |
447 | ||
448 | lp->old_link = 0; | |
449 | lp->old_speed = 0; | |
450 | lp->old_duplex = -1; | |
451 | lp->phydev = phydev; | |
452 | ||
c6dd5098 MF |
453 | pr_info("attached PHY driver [%s] " |
454 | "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n", | |
455 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq, | |
456 | MDC_CLK, mdc_div, sclk/1000000); | |
4ae5a3ad BW |
457 | |
458 | return 0; | |
459 | } | |
460 | ||
679dce39 BW |
461 | /* |
462 | * Ethtool support | |
463 | */ | |
464 | ||
53fd3f28 MH |
465 | /* |
466 | * interrupt routine for magic packet wakeup | |
467 | */ | |
468 | static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id) | |
469 | { | |
470 | return IRQ_HANDLED; | |
471 | } | |
472 | ||
679dce39 BW |
473 | static int |
474 | bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
475 | { | |
476 | struct bfin_mac_local *lp = netdev_priv(dev); | |
477 | ||
478 | if (lp->phydev) | |
479 | return phy_ethtool_gset(lp->phydev, cmd); | |
480 | ||
481 | return -EINVAL; | |
482 | } | |
483 | ||
484 | static int | |
485 | bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd) | |
486 | { | |
487 | struct bfin_mac_local *lp = netdev_priv(dev); | |
488 | ||
489 | if (!capable(CAP_NET_ADMIN)) | |
490 | return -EPERM; | |
491 | ||
492 | if (lp->phydev) | |
493 | return phy_ethtool_sset(lp->phydev, cmd); | |
494 | ||
495 | return -EINVAL; | |
496 | } | |
497 | ||
498 | static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev, | |
499 | struct ethtool_drvinfo *info) | |
500 | { | |
c6dd5098 | 501 | strcpy(info->driver, KBUILD_MODNAME); |
679dce39 BW |
502 | strcpy(info->version, DRV_VERSION); |
503 | strcpy(info->fw_version, "N/A"); | |
c2313557 | 504 | strcpy(info->bus_info, dev_name(&dev->dev)); |
679dce39 BW |
505 | } |
506 | ||
53fd3f28 MH |
507 | static void bfin_mac_ethtool_getwol(struct net_device *dev, |
508 | struct ethtool_wolinfo *wolinfo) | |
509 | { | |
510 | struct bfin_mac_local *lp = netdev_priv(dev); | |
511 | ||
512 | wolinfo->supported = WAKE_MAGIC; | |
513 | wolinfo->wolopts = lp->wol; | |
514 | } | |
515 | ||
516 | static int bfin_mac_ethtool_setwol(struct net_device *dev, | |
517 | struct ethtool_wolinfo *wolinfo) | |
518 | { | |
519 | struct bfin_mac_local *lp = netdev_priv(dev); | |
520 | int rc; | |
521 | ||
522 | if (wolinfo->wolopts & (WAKE_MAGICSECURE | | |
523 | WAKE_UCAST | | |
524 | WAKE_MCAST | | |
525 | WAKE_BCAST | | |
526 | WAKE_ARP)) | |
527 | return -EOPNOTSUPP; | |
528 | ||
529 | lp->wol = wolinfo->wolopts; | |
530 | ||
531 | if (lp->wol && !lp->irq_wake_requested) { | |
532 | /* register wake irq handler */ | |
533 | rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt, | |
534 | IRQF_DISABLED, "EMAC_WAKE", dev); | |
535 | if (rc) | |
536 | return rc; | |
537 | lp->irq_wake_requested = true; | |
538 | } | |
539 | ||
540 | if (!lp->wol && lp->irq_wake_requested) { | |
541 | free_irq(IRQ_MAC_WAKEDET, dev); | |
542 | lp->irq_wake_requested = false; | |
543 | } | |
544 | ||
545 | /* Make sure the PHY driver doesn't suspend */ | |
546 | device_init_wakeup(&dev->dev, lp->wol); | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
85c153d2 | 551 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
a85bbddd | 552 | static int bfin_mac_ethtool_get_ts_info(struct net_device *dev, |
3ffa4290 | 553 | struct ethtool_ts_info *info) |
a85bbddd RC |
554 | { |
555 | info->so_timestamping = | |
556 | SOF_TIMESTAMPING_TX_HARDWARE | | |
557 | SOF_TIMESTAMPING_RX_HARDWARE | | |
bc3c5f63 | 558 | SOF_TIMESTAMPING_RAW_HARDWARE; |
a85bbddd RC |
559 | info->phc_index = -1; |
560 | info->tx_types = | |
561 | (1 << HWTSTAMP_TX_OFF) | | |
562 | (1 << HWTSTAMP_TX_ON); | |
563 | info->rx_filters = | |
564 | (1 << HWTSTAMP_FILTER_NONE) | | |
565 | (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | | |
566 | (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | | |
567 | (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT); | |
568 | return 0; | |
569 | } | |
85c153d2 | 570 | #endif |
a85bbddd | 571 | |
0fc0b732 | 572 | static const struct ethtool_ops bfin_mac_ethtool_ops = { |
679dce39 BW |
573 | .get_settings = bfin_mac_ethtool_getsettings, |
574 | .set_settings = bfin_mac_ethtool_setsettings, | |
575 | .get_link = ethtool_op_get_link, | |
576 | .get_drvinfo = bfin_mac_ethtool_getdrvinfo, | |
53fd3f28 MH |
577 | .get_wol = bfin_mac_ethtool_getwol, |
578 | .set_wol = bfin_mac_ethtool_setwol, | |
85c153d2 | 579 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
a85bbddd | 580 | .get_ts_info = bfin_mac_ethtool_get_ts_info, |
85c153d2 | 581 | #endif |
679dce39 BW |
582 | }; |
583 | ||
4ae5a3ad | 584 | /**************************************************************************/ |
5ca1bb5a | 585 | static void setup_system_regs(struct net_device *dev) |
4ae5a3ad | 586 | { |
02460d08 SZ |
587 | struct bfin_mac_local *lp = netdev_priv(dev); |
588 | int i; | |
4ae5a3ad BW |
589 | unsigned short sysctl; |
590 | ||
591 | /* | |
592 | * Odd word alignment for Receive Frame DMA word | |
593 | * Configure checksum support and rcve frame word alignment | |
594 | */ | |
595 | sysctl = bfin_read_EMAC_SYSCTL(); | |
02460d08 SZ |
596 | /* |
597 | * check if interrupt is requested for any PHY, | |
598 | * enable PHY interrupt only if needed | |
599 | */ | |
600 | for (i = 0; i < PHY_MAX_ADDR; ++i) | |
601 | if (lp->mii_bus->irq[i] != PHY_POLL) | |
602 | break; | |
603 | if (i < PHY_MAX_ADDR) | |
604 | sysctl |= PHYIE; | |
812a9de7 | 605 | sysctl |= RXDWA; |
4ae5a3ad | 606 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
812a9de7 | 607 | sysctl |= RXCKS; |
4ae5a3ad | 608 | #else |
812a9de7 | 609 | sysctl &= ~RXCKS; |
4ae5a3ad BW |
610 | #endif |
611 | bfin_write_EMAC_SYSCTL(sysctl); | |
e190d6b1 BW |
612 | |
613 | bfin_write_EMAC_MMC_CTL(RSTC | CROLL); | |
614 | ||
c599bd6b MF |
615 | /* Set vlan regs to let 1522 bytes long packets pass through */ |
616 | bfin_write_EMAC_VLAN1(lp->vlan1_mask); | |
617 | bfin_write_EMAC_VLAN2(lp->vlan2_mask); | |
618 | ||
e190d6b1 BW |
619 | /* Initialize the TX DMA channel registers */ |
620 | bfin_write_DMA2_X_COUNT(0); | |
621 | bfin_write_DMA2_X_MODIFY(4); | |
622 | bfin_write_DMA2_Y_COUNT(0); | |
623 | bfin_write_DMA2_Y_MODIFY(0); | |
624 | ||
625 | /* Initialize the RX DMA channel registers */ | |
626 | bfin_write_DMA1_X_COUNT(0); | |
627 | bfin_write_DMA1_X_MODIFY(4); | |
628 | bfin_write_DMA1_Y_COUNT(0); | |
629 | bfin_write_DMA1_Y_MODIFY(0); | |
630 | } | |
631 | ||
73f83182 | 632 | static void setup_mac_addr(u8 *mac_addr) |
e190d6b1 BW |
633 | { |
634 | u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]); | |
635 | u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]); | |
636 | ||
637 | /* this depends on a little-endian machine */ | |
638 | bfin_write_EMAC_ADDRLO(addr_low); | |
639 | bfin_write_EMAC_ADDRHI(addr_hi); | |
640 | } | |
641 | ||
7ef0a7ee | 642 | static int bfin_mac_set_mac_address(struct net_device *dev, void *p) |
73f83182 AL |
643 | { |
644 | struct sockaddr *addr = p; | |
645 | if (netif_running(dev)) | |
646 | return -EBUSY; | |
647 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
5055d2f2 | 648 | dev->addr_assign_type &= ~NET_ADDR_RANDOM; |
73f83182 AL |
649 | setup_mac_addr(dev->dev_addr); |
650 | return 0; | |
651 | } | |
652 | ||
fe92afed BS |
653 | #ifdef CONFIG_BFIN_MAC_USE_HWSTAMP |
654 | #define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE) | |
655 | ||
bc3c5f63 RC |
656 | static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result) |
657 | { | |
658 | u32 ipn = 1000000000UL / input_clk; | |
659 | u32 ppn = 1; | |
660 | unsigned int shift = 0; | |
661 | ||
662 | while (ppn <= ipn) { | |
663 | ppn <<= 1; | |
664 | shift++; | |
665 | } | |
666 | *shift_result = shift; | |
667 | return 1000000000UL / ppn; | |
668 | } | |
669 | ||
fe92afed BS |
670 | static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev, |
671 | struct ifreq *ifr, int cmd) | |
672 | { | |
673 | struct hwtstamp_config config; | |
674 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
675 | u16 ptpctl; | |
676 | u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff; | |
677 | ||
678 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
679 | return -EFAULT; | |
680 | ||
681 | pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n", | |
682 | __func__, config.flags, config.tx_type, config.rx_filter); | |
683 | ||
684 | /* reserved for future extensions */ | |
685 | if (config.flags) | |
686 | return -EINVAL; | |
687 | ||
688 | if ((config.tx_type != HWTSTAMP_TX_OFF) && | |
689 | (config.tx_type != HWTSTAMP_TX_ON)) | |
690 | return -ERANGE; | |
691 | ||
692 | ptpctl = bfin_read_EMAC_PTP_CTL(); | |
693 | ||
694 | switch (config.rx_filter) { | |
695 | case HWTSTAMP_FILTER_NONE: | |
696 | /* | |
697 | * Dont allow any timestamping | |
698 | */ | |
699 | ptpfv3 = 0xFFFFFFFF; | |
700 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
701 | break; | |
702 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
703 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
704 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
705 | /* | |
706 | * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL) | |
707 | * to enable all the field matches. | |
708 | */ | |
709 | ptpctl &= ~0x1F00; | |
710 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
711 | /* | |
712 | * Keep the default values of the EMAC_PTP_FOFF register. | |
713 | */ | |
714 | ptpfoff = 0x4A24170C; | |
715 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
716 | /* | |
717 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 | |
718 | * registers. | |
719 | */ | |
720 | ptpfv1 = 0x11040800; | |
721 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
722 | ptpfv2 = 0x0140013F; | |
723 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
724 | /* | |
725 | * The default value (0xFFFC) allows the timestamping of both | |
726 | * received Sync messages and Delay_Req messages. | |
727 | */ | |
728 | ptpfv3 = 0xFFFFFFFC; | |
729 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
730 | ||
731 | config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; | |
732 | break; | |
733 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
734 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
735 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
736 | /* Clear all five comparison mask bits (bits[12:8]) in the | |
737 | * EMAC_PTP_CTL register to enable all the field matches. | |
738 | */ | |
739 | ptpctl &= ~0x1F00; | |
740 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
741 | /* | |
742 | * Keep the default values of the EMAC_PTP_FOFF register, except set | |
743 | * the PTPCOF field to 0x2A. | |
744 | */ | |
745 | ptpfoff = 0x2A24170C; | |
746 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
747 | /* | |
748 | * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2 | |
749 | * registers. | |
750 | */ | |
751 | ptpfv1 = 0x11040800; | |
752 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
753 | ptpfv2 = 0x0140013F; | |
754 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
755 | /* | |
756 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set | |
757 | * the value to 0xFFF0. | |
758 | */ | |
759 | ptpfv3 = 0xFFFFFFF0; | |
760 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
761 | ||
762 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; | |
763 | break; | |
764 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
765 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
766 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
767 | /* | |
768 | * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the | |
769 | * EFTM and PTPCM field comparison. | |
770 | */ | |
771 | ptpctl &= ~0x1100; | |
772 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
773 | /* | |
774 | * Keep the default values of all the fields of the EMAC_PTP_FOFF | |
775 | * register, except set the PTPCOF field to 0x0E. | |
776 | */ | |
777 | ptpfoff = 0x0E24170C; | |
778 | bfin_write_EMAC_PTP_FOFF(ptpfoff); | |
779 | /* | |
780 | * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which | |
781 | * corresponds to PTP messages on the MAC layer. | |
782 | */ | |
783 | ptpfv1 = 0x110488F7; | |
784 | bfin_write_EMAC_PTP_FV1(ptpfv1); | |
785 | ptpfv2 = 0x0140013F; | |
786 | bfin_write_EMAC_PTP_FV2(ptpfv2); | |
787 | /* | |
788 | * To allow the timestamping of Pdelay_Req and Pdelay_Resp | |
789 | * messages, set the value to 0xFFF0. | |
790 | */ | |
791 | ptpfv3 = 0xFFFFFFF0; | |
792 | bfin_write_EMAC_PTP_FV3(ptpfv3); | |
793 | ||
794 | config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; | |
795 | break; | |
796 | default: | |
797 | return -ERANGE; | |
798 | } | |
799 | ||
800 | if (config.tx_type == HWTSTAMP_TX_OFF && | |
801 | bfin_mac_hwtstamp_is_none(config.rx_filter)) { | |
802 | ptpctl &= ~PTP_EN; | |
803 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
804 | ||
805 | SSYNC(); | |
806 | } else { | |
807 | ptpctl |= PTP_EN; | |
808 | bfin_write_EMAC_PTP_CTL(ptpctl); | |
809 | ||
810 | /* | |
811 | * clear any existing timestamp | |
812 | */ | |
813 | bfin_read_EMAC_PTP_RXSNAPLO(); | |
814 | bfin_read_EMAC_PTP_RXSNAPHI(); | |
815 | ||
816 | bfin_read_EMAC_PTP_TXSNAPLO(); | |
817 | bfin_read_EMAC_PTP_TXSNAPHI(); | |
818 | ||
fe92afed | 819 | SSYNC(); |
fe92afed BS |
820 | } |
821 | ||
822 | lp->stamp_cfg = config; | |
823 | return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? | |
824 | -EFAULT : 0; | |
825 | } | |
826 | ||
fe92afed BS |
827 | static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) |
828 | { | |
829 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
fe92afed | 830 | |
2244d07b | 831 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { |
fe92afed BS |
832 | int timeout_cnt = MAX_TIMEOUT_CNT; |
833 | ||
834 | /* When doing time stamping, keep the connection to the socket | |
835 | * a while longer | |
836 | */ | |
2244d07b | 837 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; |
fe92afed BS |
838 | |
839 | /* | |
840 | * The timestamping is done at the EMAC module's MII/RMII interface | |
841 | * when the module sees the Start of Frame of an event message packet. This | |
842 | * interface is the closest possible place to the physical Ethernet transmission | |
843 | * medium, providing the best timing accuracy. | |
844 | */ | |
845 | while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt)) | |
846 | udelay(1); | |
847 | if (timeout_cnt == 0) | |
c6dd5098 | 848 | netdev_err(netdev, "timestamp the TX packet failed\n"); |
fe92afed BS |
849 | else { |
850 | struct skb_shared_hwtstamps shhwtstamps; | |
851 | u64 ns; | |
852 | u64 regval; | |
853 | ||
854 | regval = bfin_read_EMAC_PTP_TXSNAPLO(); | |
855 | regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32; | |
856 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | |
bc3c5f63 | 857 | ns = regval << lp->shift; |
fe92afed | 858 | shhwtstamps.hwtstamp = ns_to_ktime(ns); |
fe92afed | 859 | skb_tstamp_tx(skb, &shhwtstamps); |
fe92afed BS |
860 | } |
861 | } | |
862 | } | |
863 | ||
864 | static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb) | |
865 | { | |
866 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
867 | u32 valid; | |
868 | u64 regval, ns; | |
869 | struct skb_shared_hwtstamps *shhwtstamps; | |
870 | ||
871 | if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter)) | |
872 | return; | |
873 | ||
874 | valid = bfin_read_EMAC_PTP_ISTAT() & RXEL; | |
875 | if (!valid) | |
876 | return; | |
877 | ||
878 | shhwtstamps = skb_hwtstamps(skb); | |
879 | ||
880 | regval = bfin_read_EMAC_PTP_RXSNAPLO(); | |
881 | regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32; | |
bc3c5f63 | 882 | ns = regval << lp->shift; |
fe92afed BS |
883 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
884 | shhwtstamps->hwtstamp = ns_to_ktime(ns); | |
fe92afed BS |
885 | } |
886 | ||
fe92afed BS |
887 | static void bfin_mac_hwtstamp_init(struct net_device *netdev) |
888 | { | |
889 | struct bfin_mac_local *lp = netdev_priv(netdev); | |
bc3c5f63 RC |
890 | u64 addend; |
891 | u32 input_clk, phc_clk; | |
fe92afed BS |
892 | |
893 | /* Initialize hardware timer */ | |
bc3c5f63 RC |
894 | input_clk = get_sclk(); |
895 | phc_clk = bfin_select_phc_clock(input_clk, &lp->shift); | |
896 | addend = phc_clk * (1ULL << 32); | |
897 | do_div(addend, input_clk); | |
898 | bfin_write_EMAC_PTP_ADDEND((u32)addend); | |
899 | ||
900 | lp->addend = addend; | |
fe92afed BS |
901 | |
902 | /* Initialize hwstamp config */ | |
903 | lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE; | |
904 | lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF; | |
905 | } | |
906 | ||
907 | #else | |
908 | # define bfin_mac_hwtstamp_is_none(cfg) 0 | |
909 | # define bfin_mac_hwtstamp_init(dev) | |
910 | # define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP) | |
911 | # define bfin_rx_hwtstamp(dev, skb) | |
912 | # define bfin_tx_hwtstamp(dev, skb) | |
913 | #endif | |
914 | ||
4fcc3d34 SZ |
915 | static inline void _tx_reclaim_skb(void) |
916 | { | |
917 | do { | |
918 | tx_list_head->desc_a.config &= ~DMAEN; | |
919 | tx_list_head->status.status_word = 0; | |
920 | if (tx_list_head->skb) { | |
921 | dev_kfree_skb(tx_list_head->skb); | |
922 | tx_list_head->skb = NULL; | |
923 | } | |
924 | tx_list_head = tx_list_head->next; | |
925 | ||
926 | } while (tx_list_head->status.status_word != 0); | |
927 | } | |
928 | ||
929 | static void tx_reclaim_skb(struct bfin_mac_local *lp) | |
e190d6b1 BW |
930 | { |
931 | int timeout_cnt = MAX_TIMEOUT_CNT; | |
932 | ||
4fcc3d34 SZ |
933 | if (tx_list_head->status.status_word != 0) |
934 | _tx_reclaim_skb(); | |
e190d6b1 | 935 | |
4fcc3d34 | 936 | if (current_tx_ptr->next == tx_list_head) { |
e190d6b1 | 937 | while (tx_list_head->status.status_word == 0) { |
4fcc3d34 | 938 | /* slow down polling to avoid too many queue stop. */ |
015dac88 | 939 | udelay(10); |
4fcc3d34 SZ |
940 | /* reclaim skb if DMA is not running. */ |
941 | if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)) | |
942 | break; | |
943 | if (timeout_cnt-- < 0) | |
e190d6b1 | 944 | break; |
e190d6b1 | 945 | } |
4fcc3d34 SZ |
946 | |
947 | if (timeout_cnt >= 0) | |
948 | _tx_reclaim_skb(); | |
949 | else | |
950 | netif_stop_queue(lp->ndev); | |
e190d6b1 BW |
951 | } |
952 | ||
4fcc3d34 SZ |
953 | if (current_tx_ptr->next != tx_list_head && |
954 | netif_queue_stopped(lp->ndev)) | |
955 | netif_wake_queue(lp->ndev); | |
956 | ||
957 | if (tx_list_head != current_tx_ptr) { | |
958 | /* shorten the timer interval if tx queue is stopped */ | |
959 | if (netif_queue_stopped(lp->ndev)) | |
960 | lp->tx_reclaim_timer.expires = | |
961 | jiffies + (TX_RECLAIM_JIFFIES >> 4); | |
962 | else | |
963 | lp->tx_reclaim_timer.expires = | |
964 | jiffies + TX_RECLAIM_JIFFIES; | |
965 | ||
966 | mod_timer(&lp->tx_reclaim_timer, | |
967 | lp->tx_reclaim_timer.expires); | |
968 | } | |
e190d6b1 | 969 | |
e190d6b1 | 970 | return; |
4fcc3d34 | 971 | } |
e190d6b1 | 972 | |
4fcc3d34 SZ |
973 | static void tx_reclaim_skb_timeout(unsigned long lp) |
974 | { | |
975 | tx_reclaim_skb((struct bfin_mac_local *)lp); | |
e190d6b1 BW |
976 | } |
977 | ||
7ef0a7ee | 978 | static int bfin_mac_hard_start_xmit(struct sk_buff *skb, |
e190d6b1 BW |
979 | struct net_device *dev) |
980 | { | |
4fcc3d34 | 981 | struct bfin_mac_local *lp = netdev_priv(dev); |
a50c0c05 | 982 | u16 *data; |
015dac88 | 983 | u32 data_align = (unsigned long)(skb->data) & 0x3; |
fe92afed | 984 | |
e190d6b1 BW |
985 | current_tx_ptr->skb = skb; |
986 | ||
015dac88 MH |
987 | if (data_align == 0x2) { |
988 | /* move skb->data to current_tx_ptr payload */ | |
989 | data = (u16 *)(skb->data) - 1; | |
fe92afed BS |
990 | *data = (u16)(skb->len); |
991 | /* | |
992 | * When transmitting an Ethernet packet, the PTP_TSYNC module requires | |
993 | * a DMA_Length_Word field associated with the packet. The lower 12 bits | |
994 | * of this field are the length of the packet payload in bytes and the higher | |
995 | * 4 bits are the timestamping enable field. | |
996 | */ | |
2244d07b | 997 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) |
fe92afed BS |
998 | *data |= 0x1000; |
999 | ||
015dac88 MH |
1000 | current_tx_ptr->desc_a.start_addr = (u32)data; |
1001 | /* this is important! */ | |
1002 | blackfin_dcache_flush_range((u32)data, | |
1003 | (u32)((u8 *)data + skb->len + 4)); | |
e190d6b1 | 1004 | } else { |
015dac88 | 1005 | *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len); |
fe92afed | 1006 | /* enable timestamping for the sent packet */ |
2244d07b | 1007 | if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) |
fe92afed | 1008 | *((u16 *)(current_tx_ptr->packet)) |= 0x1000; |
015dac88 MH |
1009 | memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data, |
1010 | skb->len); | |
1011 | current_tx_ptr->desc_a.start_addr = | |
1012 | (u32)current_tx_ptr->packet; | |
015dac88 MH |
1013 | blackfin_dcache_flush_range( |
1014 | (u32)current_tx_ptr->packet, | |
1015 | (u32)(current_tx_ptr->packet + skb->len + 2)); | |
e190d6b1 BW |
1016 | } |
1017 | ||
805a8ab3 SZ |
1018 | /* make sure the internal data buffers in the core are drained |
1019 | * so that the DMA descriptors are completely written when the | |
1020 | * DMA engine goes to fetch them below | |
1021 | */ | |
1022 | SSYNC(); | |
1023 | ||
4fcc3d34 SZ |
1024 | /* always clear status buffer before start tx dma */ |
1025 | current_tx_ptr->status.status_word = 0; | |
1026 | ||
e190d6b1 BW |
1027 | /* enable this packet's dma */ |
1028 | current_tx_ptr->desc_a.config |= DMAEN; | |
1029 | ||
1030 | /* tx dma is running, just return */ | |
015dac88 | 1031 | if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN) |
e190d6b1 BW |
1032 | goto out; |
1033 | ||
1034 | /* tx dma is not running */ | |
1035 | bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a)); | |
1036 | /* dma enabled, read from memory, size is 6 */ | |
1037 | bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config); | |
1038 | /* Turn on the EMAC tx */ | |
1039 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
1040 | ||
1041 | out: | |
fe92afed BS |
1042 | bfin_tx_hwtstamp(dev, skb); |
1043 | ||
e190d6b1 | 1044 | current_tx_ptr = current_tx_ptr->next; |
09f75cd7 JG |
1045 | dev->stats.tx_packets++; |
1046 | dev->stats.tx_bytes += (skb->len); | |
4fcc3d34 SZ |
1047 | |
1048 | tx_reclaim_skb(lp); | |
1049 | ||
6ed10654 | 1050 | return NETDEV_TX_OK; |
e190d6b1 BW |
1051 | } |
1052 | ||
ad2864d8 | 1053 | #define IP_HEADER_OFF 0 |
ec497b32 PM |
1054 | #define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \ |
1055 | RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE) | |
1056 | ||
7ef0a7ee | 1057 | static void bfin_mac_rx(struct net_device *dev) |
e190d6b1 BW |
1058 | { |
1059 | struct sk_buff *skb, *new_skb; | |
e190d6b1 | 1060 | unsigned short len; |
fe92afed | 1061 | struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev); |
ad2864d8 SZ |
1062 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
1063 | unsigned int i; | |
1064 | unsigned char fcs[ETH_FCS_LEN + 1]; | |
1065 | #endif | |
e190d6b1 | 1066 | |
ec497b32 PM |
1067 | /* check if frame status word reports an error condition |
1068 | * we which case we simply drop the packet | |
1069 | */ | |
1070 | if (current_rx_ptr->status.status_word & RX_ERROR_MASK) { | |
c6dd5098 | 1071 | netdev_notice(dev, "rx: receive error - packet dropped\n"); |
ec497b32 PM |
1072 | dev->stats.rx_dropped++; |
1073 | goto out; | |
1074 | } | |
1075 | ||
e190d6b1 BW |
1076 | /* allocate a new skb for next time receive */ |
1077 | skb = current_rx_ptr->skb; | |
fe92afed | 1078 | |
1ab0d2ec | 1079 | new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN); |
e190d6b1 | 1080 | if (!new_skb) { |
c6dd5098 | 1081 | netdev_notice(dev, "rx: low on mem - packet dropped\n"); |
09f75cd7 | 1082 | dev->stats.rx_dropped++; |
e190d6b1 BW |
1083 | goto out; |
1084 | } | |
1085 | /* reserve 2 bytes for RXDWA padding */ | |
015dac88 | 1086 | skb_reserve(new_skb, NET_IP_ALIGN); |
6e01d1a4 AD |
1087 | /* Invidate the data cache of skb->data range when it is write back |
1088 | * cache. It will prevent overwritting the new data from DMA | |
1089 | */ | |
1090 | blackfin_dcache_invalidate_range((unsigned long)new_skb->head, | |
1091 | (unsigned long)new_skb->end); | |
1092 | ||
f6e1e4f3 SZ |
1093 | current_rx_ptr->skb = new_skb; |
1094 | current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2; | |
1095 | ||
e190d6b1 | 1096 | len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN); |
ad2864d8 SZ |
1097 | /* Deduce Ethernet FCS length from Ethernet payload length */ |
1098 | len -= ETH_FCS_LEN; | |
e190d6b1 | 1099 | skb_put(skb, len); |
e190d6b1 | 1100 | |
e190d6b1 | 1101 | skb->protocol = eth_type_trans(skb, dev); |
fe92afed BS |
1102 | |
1103 | bfin_rx_hwtstamp(dev, skb); | |
1104 | ||
e190d6b1 | 1105 | #if defined(BFIN_MAC_CSUM_OFFLOAD) |
ad2864d8 SZ |
1106 | /* Checksum offloading only works for IPv4 packets with the standard IP header |
1107 | * length of 20 bytes, because the blackfin MAC checksum calculation is | |
1108 | * based on that assumption. We must NOT use the calculated checksum if our | |
1109 | * IP version or header break that assumption. | |
1110 | */ | |
1111 | if (skb->data[IP_HEADER_OFF] == 0x45) { | |
1112 | skb->csum = current_rx_ptr->status.ip_payload_csum; | |
1113 | /* | |
1114 | * Deduce Ethernet FCS from hardware generated IP payload checksum. | |
1115 | * IP checksum is based on 16-bit one's complement algorithm. | |
1116 | * To deduce a value from checksum is equal to add its inversion. | |
1117 | * If the IP payload len is odd, the inversed FCS should also | |
1118 | * begin from odd address and leave first byte zero. | |
1119 | */ | |
1120 | if (skb->len % 2) { | |
1121 | fcs[0] = 0; | |
1122 | for (i = 0; i < ETH_FCS_LEN; i++) | |
1123 | fcs[i + 1] = ~skb->data[skb->len + i]; | |
1124 | skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum); | |
1125 | } else { | |
1126 | for (i = 0; i < ETH_FCS_LEN; i++) | |
1127 | fcs[i] = ~skb->data[skb->len + i]; | |
1128 | skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum); | |
1129 | } | |
1130 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1131 | } | |
e190d6b1 BW |
1132 | #endif |
1133 | ||
1134 | netif_rx(skb); | |
09f75cd7 JG |
1135 | dev->stats.rx_packets++; |
1136 | dev->stats.rx_bytes += len; | |
ec497b32 | 1137 | out: |
e190d6b1 BW |
1138 | current_rx_ptr->status.status_word = 0x00000000; |
1139 | current_rx_ptr = current_rx_ptr->next; | |
e190d6b1 BW |
1140 | } |
1141 | ||
1142 | /* interrupt routine to handle rx and error signal */ | |
7ef0a7ee | 1143 | static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id) |
e190d6b1 BW |
1144 | { |
1145 | struct net_device *dev = dev_id; | |
1146 | int number = 0; | |
1147 | ||
1148 | get_one_packet: | |
1149 | if (current_rx_ptr->status.status_word == 0) { | |
1150 | /* no more new packet received */ | |
1151 | if (number == 0) { | |
1152 | if (current_rx_ptr->next->status.status_word != 0) { | |
1153 | current_rx_ptr = current_rx_ptr->next; | |
1154 | goto real_rx; | |
1155 | } | |
1156 | } | |
1157 | bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() | | |
1158 | DMA_DONE | DMA_ERR); | |
1159 | return IRQ_HANDLED; | |
1160 | } | |
1161 | ||
1162 | real_rx: | |
7ef0a7ee | 1163 | bfin_mac_rx(dev); |
e190d6b1 BW |
1164 | number++; |
1165 | goto get_one_packet; | |
1166 | } | |
1167 | ||
1168 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7ef0a7ee | 1169 | static void bfin_mac_poll(struct net_device *dev) |
e190d6b1 | 1170 | { |
4fcc3d34 SZ |
1171 | struct bfin_mac_local *lp = netdev_priv(dev); |
1172 | ||
e190d6b1 | 1173 | disable_irq(IRQ_MAC_RX); |
7ef0a7ee | 1174 | bfin_mac_interrupt(IRQ_MAC_RX, dev); |
4fcc3d34 | 1175 | tx_reclaim_skb(lp); |
e190d6b1 BW |
1176 | enable_irq(IRQ_MAC_RX); |
1177 | } | |
1178 | #endif /* CONFIG_NET_POLL_CONTROLLER */ | |
1179 | ||
7ef0a7ee | 1180 | static void bfin_mac_disable(void) |
e190d6b1 BW |
1181 | { |
1182 | unsigned int opmode; | |
1183 | ||
1184 | opmode = bfin_read_EMAC_OPMODE(); | |
1185 | opmode &= (~RE); | |
1186 | opmode &= (~TE); | |
1187 | /* Turn off the EMAC */ | |
1188 | bfin_write_EMAC_OPMODE(opmode); | |
1189 | } | |
1190 | ||
1191 | /* | |
1192 | * Enable Interrupts, Receive, and Transmit | |
1193 | */ | |
02460d08 | 1194 | static int bfin_mac_enable(struct phy_device *phydev) |
e190d6b1 | 1195 | { |
2bfa0f0c | 1196 | int ret; |
e190d6b1 BW |
1197 | u32 opmode; |
1198 | ||
c6dd5098 | 1199 | pr_debug("%s\n", __func__); |
e190d6b1 BW |
1200 | |
1201 | /* Set RX DMA */ | |
1202 | bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a)); | |
1203 | bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config); | |
1204 | ||
1205 | /* Wait MII done */ | |
2bfa0f0c MF |
1206 | ret = bfin_mdio_poll(); |
1207 | if (ret) | |
1208 | return ret; | |
e190d6b1 BW |
1209 | |
1210 | /* We enable only RX here */ | |
1211 | /* ASTP : Enable Automatic Pad Stripping | |
1212 | PR : Promiscuous Mode for test | |
1213 | PSF : Receive frames with total length less than 64 bytes. | |
1214 | FDMODE : Full Duplex Mode | |
1215 | LB : Internal Loopback for test | |
1216 | RE : Receiver Enable */ | |
1217 | opmode = bfin_read_EMAC_OPMODE(); | |
1218 | if (opmode & FDMODE) | |
1219 | opmode |= PSF; | |
1220 | else | |
1221 | opmode |= DRO | DC | PSF; | |
1222 | opmode |= RE; | |
1223 | ||
02460d08 SZ |
1224 | if (phydev->interface == PHY_INTERFACE_MODE_RMII) { |
1225 | opmode |= RMII; /* For Now only 100MBit are supported */ | |
72f49050 MF |
1226 | #if defined(CONFIG_BF537) || defined(CONFIG_BF536) |
1227 | if (__SILICON_REVISION__ < 3) { | |
1228 | /* | |
1229 | * This isn't publicly documented (fun times!), but in | |
1230 | * silicon <=0.2, the RX and TX pins are clocked together. | |
1231 | * So in order to recv, we must enable the transmit side | |
1232 | * as well. This will cause a spurious TX interrupt too, | |
1233 | * but we can easily consume that. | |
1234 | */ | |
1235 | opmode |= TE; | |
1236 | } | |
e190d6b1 | 1237 | #endif |
02460d08 SZ |
1238 | } |
1239 | ||
e190d6b1 BW |
1240 | /* Turn on the EMAC rx */ |
1241 | bfin_write_EMAC_OPMODE(opmode); | |
2bfa0f0c MF |
1242 | |
1243 | return 0; | |
e190d6b1 BW |
1244 | } |
1245 | ||
1246 | /* Our watchdog timed out. Called by the networking layer */ | |
7ef0a7ee | 1247 | static void bfin_mac_timeout(struct net_device *dev) |
e190d6b1 | 1248 | { |
4fcc3d34 SZ |
1249 | struct bfin_mac_local *lp = netdev_priv(dev); |
1250 | ||
b39d66a8 | 1251 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 | 1252 | |
7ef0a7ee | 1253 | bfin_mac_disable(); |
e190d6b1 | 1254 | |
4fcc3d34 SZ |
1255 | del_timer(&lp->tx_reclaim_timer); |
1256 | ||
1257 | /* reset tx queue and free skb */ | |
1258 | while (tx_list_head != current_tx_ptr) { | |
1259 | tx_list_head->desc_a.config &= ~DMAEN; | |
1260 | tx_list_head->status.status_word = 0; | |
1261 | if (tx_list_head->skb) { | |
1262 | dev_kfree_skb(tx_list_head->skb); | |
1263 | tx_list_head->skb = NULL; | |
1264 | } | |
1265 | tx_list_head = tx_list_head->next; | |
1266 | } | |
1267 | ||
1268 | if (netif_queue_stopped(lp->ndev)) | |
1269 | netif_wake_queue(lp->ndev); | |
e190d6b1 | 1270 | |
02460d08 | 1271 | bfin_mac_enable(lp->phydev); |
e190d6b1 BW |
1272 | |
1273 | /* We can accept TX packets again */ | |
1ae5dc34 | 1274 | dev->trans_start = jiffies; /* prevent tx timeout */ |
e190d6b1 BW |
1275 | netif_wake_queue(dev); |
1276 | } | |
1277 | ||
7ef0a7ee | 1278 | static void bfin_mac_multicast_hash(struct net_device *dev) |
775919bc AW |
1279 | { |
1280 | u32 emac_hashhi, emac_hashlo; | |
22bedad3 | 1281 | struct netdev_hw_addr *ha; |
775919bc AW |
1282 | u32 crc; |
1283 | ||
1284 | emac_hashhi = emac_hashlo = 0; | |
1285 | ||
22bedad3 | 1286 | netdev_for_each_mc_addr(ha, dev) { |
f767b6df | 1287 | crc = ether_crc(ETH_ALEN, ha->addr); |
775919bc AW |
1288 | crc >>= 26; |
1289 | ||
1290 | if (crc & 0x20) | |
1291 | emac_hashhi |= 1 << (crc & 0x1f); | |
1292 | else | |
1293 | emac_hashlo |= 1 << (crc & 0x1f); | |
1294 | } | |
1295 | ||
1296 | bfin_write_EMAC_HASHHI(emac_hashhi); | |
1297 | bfin_write_EMAC_HASHLO(emac_hashlo); | |
775919bc AW |
1298 | } |
1299 | ||
e190d6b1 BW |
1300 | /* |
1301 | * This routine will, depending on the values passed to it, | |
1302 | * either make it accept multicast packets, go into | |
1303 | * promiscuous mode (for TCPDUMP and cousins) or accept | |
1304 | * a select set of multicast packets | |
1305 | */ | |
7ef0a7ee | 1306 | static void bfin_mac_set_multicast_list(struct net_device *dev) |
e190d6b1 BW |
1307 | { |
1308 | u32 sysctl; | |
1309 | ||
1310 | if (dev->flags & IFF_PROMISC) { | |
c6dd5098 | 1311 | netdev_info(dev, "set promisc mode\n"); |
e190d6b1 | 1312 | sysctl = bfin_read_EMAC_OPMODE(); |
c0da776b | 1313 | sysctl |= PR; |
e190d6b1 | 1314 | bfin_write_EMAC_OPMODE(sysctl); |
775919bc | 1315 | } else if (dev->flags & IFF_ALLMULTI) { |
e190d6b1 BW |
1316 | /* accept all multicast */ |
1317 | sysctl = bfin_read_EMAC_OPMODE(); | |
1318 | sysctl |= PAM; | |
1319 | bfin_write_EMAC_OPMODE(sysctl); | |
4cd24eaf | 1320 | } else if (!netdev_mc_empty(dev)) { |
775919bc AW |
1321 | /* set up multicast hash table */ |
1322 | sysctl = bfin_read_EMAC_OPMODE(); | |
1323 | sysctl |= HM; | |
1324 | bfin_write_EMAC_OPMODE(sysctl); | |
7ef0a7ee | 1325 | bfin_mac_multicast_hash(dev); |
e190d6b1 BW |
1326 | } else { |
1327 | /* clear promisc or multicast mode */ | |
1328 | sysctl = bfin_read_EMAC_OPMODE(); | |
1329 | sysctl &= ~(RAF | PAM); | |
1330 | bfin_write_EMAC_OPMODE(sysctl); | |
1331 | } | |
1332 | } | |
1333 | ||
fe92afed BS |
1334 | static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
1335 | { | |
02460d08 SZ |
1336 | struct bfin_mac_local *lp = netdev_priv(netdev); |
1337 | ||
1338 | if (!netif_running(netdev)) | |
1339 | return -EINVAL; | |
1340 | ||
fe92afed BS |
1341 | switch (cmd) { |
1342 | case SIOCSHWTSTAMP: | |
1343 | return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd); | |
1344 | default: | |
02460d08 SZ |
1345 | if (lp->phydev) |
1346 | return phy_mii_ioctl(lp->phydev, ifr, cmd); | |
1347 | else | |
1348 | return -EOPNOTSUPP; | |
fe92afed BS |
1349 | } |
1350 | } | |
1351 | ||
e190d6b1 BW |
1352 | /* |
1353 | * this puts the device in an inactive state | |
1354 | */ | |
7ef0a7ee | 1355 | static void bfin_mac_shutdown(struct net_device *dev) |
e190d6b1 BW |
1356 | { |
1357 | /* Turn off the EMAC */ | |
1358 | bfin_write_EMAC_OPMODE(0x00000000); | |
1359 | /* Turn off the EMAC RX DMA */ | |
1360 | bfin_write_DMA1_CONFIG(0x0000); | |
1361 | bfin_write_DMA2_CONFIG(0x0000); | |
1362 | } | |
1363 | ||
1364 | /* | |
1365 | * Open and Initialize the interface | |
1366 | * | |
1367 | * Set up everything, reset the card, etc.. | |
1368 | */ | |
7ef0a7ee | 1369 | static int bfin_mac_open(struct net_device *dev) |
e190d6b1 | 1370 | { |
7ef0a7ee | 1371 | struct bfin_mac_local *lp = netdev_priv(dev); |
2bfa0f0c | 1372 | int ret; |
b39d66a8 | 1373 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
1374 | |
1375 | /* | |
1376 | * Check that the address is valid. If its not, refuse | |
1377 | * to bring the device up. The user must specify an | |
1378 | * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx | |
1379 | */ | |
1380 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
c6dd5098 | 1381 | netdev_warn(dev, "no valid ethernet hw addr\n"); |
e190d6b1 BW |
1382 | return -EINVAL; |
1383 | } | |
1384 | ||
1385 | /* initial rx and tx list */ | |
1ab0d2ec | 1386 | ret = desc_list_init(dev); |
2bfa0f0c MF |
1387 | if (ret) |
1388 | return ret; | |
e190d6b1 | 1389 | |
4ae5a3ad | 1390 | phy_start(lp->phydev); |
136492b2 | 1391 | phy_write(lp->phydev, MII_BMCR, BMCR_RESET); |
e190d6b1 | 1392 | setup_system_regs(dev); |
ee02fee8 | 1393 | setup_mac_addr(dev->dev_addr); |
2bfa0f0c | 1394 | |
7ef0a7ee | 1395 | bfin_mac_disable(); |
02460d08 | 1396 | ret = bfin_mac_enable(lp->phydev); |
2bfa0f0c MF |
1397 | if (ret) |
1398 | return ret; | |
e190d6b1 | 1399 | pr_debug("hardware init finished\n"); |
2bfa0f0c | 1400 | |
e190d6b1 BW |
1401 | netif_start_queue(dev); |
1402 | netif_carrier_on(dev); | |
1403 | ||
1404 | return 0; | |
1405 | } | |
1406 | ||
1407 | /* | |
e190d6b1 BW |
1408 | * this makes the board clean up everything that it can |
1409 | * and not talk to the outside world. Caused by | |
1410 | * an 'ifconfig ethX down' | |
1411 | */ | |
7ef0a7ee | 1412 | static int bfin_mac_close(struct net_device *dev) |
e190d6b1 | 1413 | { |
7ef0a7ee | 1414 | struct bfin_mac_local *lp = netdev_priv(dev); |
b39d66a8 | 1415 | pr_debug("%s: %s\n", dev->name, __func__); |
e190d6b1 BW |
1416 | |
1417 | netif_stop_queue(dev); | |
1418 | netif_carrier_off(dev); | |
1419 | ||
4ae5a3ad | 1420 | phy_stop(lp->phydev); |
136492b2 | 1421 | phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); |
4ae5a3ad | 1422 | |
e190d6b1 | 1423 | /* clear everything */ |
7ef0a7ee | 1424 | bfin_mac_shutdown(dev); |
e190d6b1 BW |
1425 | |
1426 | /* free the rx/tx buffers */ | |
1427 | desc_list_free(); | |
1428 | ||
1429 | return 0; | |
1430 | } | |
1431 | ||
b63dc8fe MF |
1432 | static const struct net_device_ops bfin_mac_netdev_ops = { |
1433 | .ndo_open = bfin_mac_open, | |
1434 | .ndo_stop = bfin_mac_close, | |
1435 | .ndo_start_xmit = bfin_mac_hard_start_xmit, | |
1436 | .ndo_set_mac_address = bfin_mac_set_mac_address, | |
1437 | .ndo_tx_timeout = bfin_mac_timeout, | |
afc4b13d | 1438 | .ndo_set_rx_mode = bfin_mac_set_multicast_list, |
fe92afed | 1439 | .ndo_do_ioctl = bfin_mac_ioctl, |
b63dc8fe MF |
1440 | .ndo_validate_addr = eth_validate_addr, |
1441 | .ndo_change_mtu = eth_change_mtu, | |
1442 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1443 | .ndo_poll_controller = bfin_mac_poll, | |
1444 | #endif | |
1445 | }; | |
1446 | ||
d7b843d3 | 1447 | static int __devinit bfin_mac_probe(struct platform_device *pdev) |
e190d6b1 | 1448 | { |
7ef0a7ee BW |
1449 | struct net_device *ndev; |
1450 | struct bfin_mac_local *lp; | |
080c8255 | 1451 | struct platform_device *pd; |
02460d08 | 1452 | struct bfin_mii_bus_platform_data *mii_bus_data; |
080c8255 | 1453 | int rc; |
7ef0a7ee BW |
1454 | |
1455 | ndev = alloc_etherdev(sizeof(struct bfin_mac_local)); | |
41de8d4c | 1456 | if (!ndev) |
7ef0a7ee | 1457 | return -ENOMEM; |
7ef0a7ee BW |
1458 | |
1459 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1460 | platform_set_drvdata(pdev, ndev); | |
1461 | lp = netdev_priv(ndev); | |
4fcc3d34 | 1462 | lp->ndev = ndev; |
e190d6b1 BW |
1463 | |
1464 | /* Grab the MAC address in the MAC */ | |
7ef0a7ee BW |
1465 | *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO()); |
1466 | *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI()); | |
e190d6b1 BW |
1467 | |
1468 | /* probe mac */ | |
1469 | /*todo: how to proble? which is revision_register */ | |
1470 | bfin_write_EMAC_ADDRLO(0x12345678); | |
1471 | if (bfin_read_EMAC_ADDRLO() != 0x12345678) { | |
7ef0a7ee BW |
1472 | dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n"); |
1473 | rc = -ENODEV; | |
1474 | goto out_err_probe_mac; | |
e190d6b1 BW |
1475 | } |
1476 | ||
e190d6b1 | 1477 | |
7ef0a7ee BW |
1478 | /* |
1479 | * Is it valid? (Did bootloader initialize it?) | |
1480 | * Grab the MAC from the board somehow | |
1481 | * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c | |
1482 | */ | |
5055d2f2 DK |
1483 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
1484 | if (bfin_get_ether_addr(ndev->dev_addr) || | |
1485 | !is_valid_ether_addr(ndev->dev_addr)) { | |
1486 | /* Still not valid, get a random one */ | |
1487 | netdev_warn(ndev, "Setting Ethernet MAC to a random one\n"); | |
1488 | eth_hw_addr_random(ndev); | |
1489 | } | |
1490 | } | |
e190d6b1 | 1491 | |
7ef0a7ee | 1492 | setup_mac_addr(ndev->dev_addr); |
e190d6b1 | 1493 | |
080c8255 GY |
1494 | if (!pdev->dev.platform_data) { |
1495 | dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n"); | |
1496 | rc = -ENODEV; | |
1497 | goto out_err_probe_mac; | |
7ef0a7ee | 1498 | } |
080c8255 GY |
1499 | pd = pdev->dev.platform_data; |
1500 | lp->mii_bus = platform_get_drvdata(pd); | |
0e995cd3 SZ |
1501 | if (!lp->mii_bus) { |
1502 | dev_err(&pdev->dev, "Cannot get mii_bus!\n"); | |
1503 | rc = -ENODEV; | |
02460d08 | 1504 | goto out_err_probe_mac; |
0e995cd3 | 1505 | } |
080c8255 | 1506 | lp->mii_bus->priv = ndev; |
02460d08 | 1507 | mii_bus_data = pd->dev.platform_data; |
4ae5a3ad | 1508 | |
02460d08 | 1509 | rc = mii_probe(ndev, mii_bus_data->phy_mode); |
7ef0a7ee BW |
1510 | if (rc) { |
1511 | dev_err(&pdev->dev, "MII Probe failed!\n"); | |
1512 | goto out_err_mii_probe; | |
1513 | } | |
4ae5a3ad | 1514 | |
c599bd6b MF |
1515 | lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask; |
1516 | lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask; | |
1517 | ||
e190d6b1 | 1518 | /* Fill in the fields of the device structure with ethernet values. */ |
7ef0a7ee BW |
1519 | ether_setup(ndev); |
1520 | ||
149da651 | 1521 | ndev->netdev_ops = &bfin_mac_netdev_ops; |
679dce39 | 1522 | ndev->ethtool_ops = &bfin_mac_ethtool_ops; |
e190d6b1 | 1523 | |
4fcc3d34 SZ |
1524 | init_timer(&lp->tx_reclaim_timer); |
1525 | lp->tx_reclaim_timer.data = (unsigned long)lp; | |
1526 | lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout; | |
1527 | ||
e190d6b1 BW |
1528 | spin_lock_init(&lp->lock); |
1529 | ||
1530 | /* now, enable interrupts */ | |
1531 | /* register irq handler */ | |
7ef0a7ee | 1532 | rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt, |
91a455f0 | 1533 | IRQF_DISABLED, "EMAC_RX", ndev); |
7ef0a7ee BW |
1534 | if (rc) { |
1535 | dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n"); | |
1536 | rc = -EBUSY; | |
1537 | goto out_err_request_irq; | |
e190d6b1 BW |
1538 | } |
1539 | ||
7ef0a7ee BW |
1540 | rc = register_netdev(ndev); |
1541 | if (rc) { | |
1542 | dev_err(&pdev->dev, "Cannot register net device!\n"); | |
1543 | goto out_err_reg_ndev; | |
e190d6b1 BW |
1544 | } |
1545 | ||
fe92afed BS |
1546 | bfin_mac_hwtstamp_init(ndev); |
1547 | ||
7ef0a7ee | 1548 | /* now, print out the card info, in a short format.. */ |
c6dd5098 | 1549 | netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION); |
e190d6b1 | 1550 | |
7ef0a7ee | 1551 | return 0; |
e190d6b1 | 1552 | |
7ef0a7ee BW |
1553 | out_err_reg_ndev: |
1554 | free_irq(IRQ_MAC_RX, ndev); | |
1555 | out_err_request_irq: | |
1556 | out_err_mii_probe: | |
298cf9be | 1557 | mdiobus_unregister(lp->mii_bus); |
298cf9be | 1558 | mdiobus_free(lp->mii_bus); |
7ef0a7ee BW |
1559 | out_err_probe_mac: |
1560 | platform_set_drvdata(pdev, NULL); | |
1561 | free_netdev(ndev); | |
e190d6b1 | 1562 | |
7ef0a7ee | 1563 | return rc; |
e190d6b1 BW |
1564 | } |
1565 | ||
d7b843d3 | 1566 | static int __devexit bfin_mac_remove(struct platform_device *pdev) |
e190d6b1 BW |
1567 | { |
1568 | struct net_device *ndev = platform_get_drvdata(pdev); | |
7ef0a7ee | 1569 | struct bfin_mac_local *lp = netdev_priv(ndev); |
e190d6b1 BW |
1570 | |
1571 | platform_set_drvdata(pdev, NULL); | |
1572 | ||
080c8255 | 1573 | lp->mii_bus->priv = NULL; |
7ef0a7ee | 1574 | |
e190d6b1 BW |
1575 | unregister_netdev(ndev); |
1576 | ||
1577 | free_irq(IRQ_MAC_RX, ndev); | |
1578 | ||
1579 | free_netdev(ndev); | |
1580 | ||
e190d6b1 BW |
1581 | return 0; |
1582 | } | |
1583 | ||
496a34c2 BW |
1584 | #ifdef CONFIG_PM |
1585 | static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg) | |
e190d6b1 | 1586 | { |
496a34c2 | 1587 | struct net_device *net_dev = platform_get_drvdata(pdev); |
53fd3f28 | 1588 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
496a34c2 | 1589 | |
53fd3f28 MH |
1590 | if (lp->wol) { |
1591 | bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE); | |
1592 | bfin_write_EMAC_WKUP_CTL(MPKE); | |
1593 | enable_irq_wake(IRQ_MAC_WAKEDET); | |
1594 | } else { | |
1595 | if (netif_running(net_dev)) | |
1596 | bfin_mac_close(net_dev); | |
1597 | } | |
496a34c2 | 1598 | |
e190d6b1 BW |
1599 | return 0; |
1600 | } | |
1601 | ||
1602 | static int bfin_mac_resume(struct platform_device *pdev) | |
1603 | { | |
496a34c2 | 1604 | struct net_device *net_dev = platform_get_drvdata(pdev); |
53fd3f28 | 1605 | struct bfin_mac_local *lp = netdev_priv(net_dev); |
496a34c2 | 1606 | |
53fd3f28 MH |
1607 | if (lp->wol) { |
1608 | bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE); | |
1609 | bfin_write_EMAC_WKUP_CTL(0); | |
1610 | disable_irq_wake(IRQ_MAC_WAKEDET); | |
1611 | } else { | |
1612 | if (netif_running(net_dev)) | |
1613 | bfin_mac_open(net_dev); | |
1614 | } | |
496a34c2 | 1615 | |
e190d6b1 BW |
1616 | return 0; |
1617 | } | |
496a34c2 BW |
1618 | #else |
1619 | #define bfin_mac_suspend NULL | |
1620 | #define bfin_mac_resume NULL | |
1621 | #endif /* CONFIG_PM */ | |
e190d6b1 | 1622 | |
080c8255 GY |
1623 | static int __devinit bfin_mii_bus_probe(struct platform_device *pdev) |
1624 | { | |
1625 | struct mii_bus *miibus; | |
02460d08 SZ |
1626 | struct bfin_mii_bus_platform_data *mii_bus_pd; |
1627 | const unsigned short *pin_req; | |
080c8255 GY |
1628 | int rc, i; |
1629 | ||
02460d08 SZ |
1630 | mii_bus_pd = dev_get_platdata(&pdev->dev); |
1631 | if (!mii_bus_pd) { | |
1632 | dev_err(&pdev->dev, "No peripherals in platform data!\n"); | |
1633 | return -EINVAL; | |
1634 | } | |
1635 | ||
080c8255 GY |
1636 | /* |
1637 | * We are setting up a network card, | |
1638 | * so set the GPIO pins to Ethernet mode | |
1639 | */ | |
02460d08 | 1640 | pin_req = mii_bus_pd->mac_peripherals; |
c6dd5098 | 1641 | rc = peripheral_request_list(pin_req, KBUILD_MODNAME); |
080c8255 GY |
1642 | if (rc) { |
1643 | dev_err(&pdev->dev, "Requesting peripherals failed!\n"); | |
1644 | return rc; | |
1645 | } | |
1646 | ||
1647 | rc = -ENOMEM; | |
1648 | miibus = mdiobus_alloc(); | |
1649 | if (miibus == NULL) | |
1650 | goto out_err_alloc; | |
1651 | miibus->read = bfin_mdiobus_read; | |
1652 | miibus->write = bfin_mdiobus_write; | |
1653 | miibus->reset = bfin_mdiobus_reset; | |
1654 | ||
1655 | miibus->parent = &pdev->dev; | |
1656 | miibus->name = "bfin_mii_bus"; | |
02460d08 SZ |
1657 | miibus->phy_mask = mii_bus_pd->phy_mask; |
1658 | ||
75432fd2 FF |
1659 | snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x", |
1660 | pdev->name, pdev->id); | |
080c8255 | 1661 | miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
02460d08 SZ |
1662 | if (!miibus->irq) |
1663 | goto out_err_irq_alloc; | |
1664 | ||
1665 | for (i = rc; i < PHY_MAX_ADDR; ++i) | |
080c8255 GY |
1666 | miibus->irq[i] = PHY_POLL; |
1667 | ||
02460d08 SZ |
1668 | rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR); |
1669 | if (rc != mii_bus_pd->phydev_number) | |
1670 | dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n", | |
1671 | mii_bus_pd->phydev_number); | |
1672 | for (i = 0; i < rc; ++i) { | |
1673 | unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr; | |
1674 | if (phyaddr < PHY_MAX_ADDR) | |
1675 | miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq; | |
1676 | else | |
1677 | dev_err(&pdev->dev, | |
1678 | "Invalid PHY address %i for phydev %i\n", | |
1679 | phyaddr, i); | |
1680 | } | |
1681 | ||
080c8255 GY |
1682 | rc = mdiobus_register(miibus); |
1683 | if (rc) { | |
1684 | dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); | |
1685 | goto out_err_mdiobus_register; | |
1686 | } | |
1687 | ||
1688 | platform_set_drvdata(pdev, miibus); | |
1689 | return 0; | |
1690 | ||
1691 | out_err_mdiobus_register: | |
7f267de4 | 1692 | kfree(miibus->irq); |
02460d08 | 1693 | out_err_irq_alloc: |
080c8255 GY |
1694 | mdiobus_free(miibus); |
1695 | out_err_alloc: | |
1696 | peripheral_free_list(pin_req); | |
1697 | ||
1698 | return rc; | |
1699 | } | |
1700 | ||
1701 | static int __devexit bfin_mii_bus_remove(struct platform_device *pdev) | |
1702 | { | |
1703 | struct mii_bus *miibus = platform_get_drvdata(pdev); | |
02460d08 SZ |
1704 | struct bfin_mii_bus_platform_data *mii_bus_pd = |
1705 | dev_get_platdata(&pdev->dev); | |
1706 | ||
080c8255 GY |
1707 | platform_set_drvdata(pdev, NULL); |
1708 | mdiobus_unregister(miibus); | |
7f267de4 | 1709 | kfree(miibus->irq); |
080c8255 | 1710 | mdiobus_free(miibus); |
02460d08 SZ |
1711 | peripheral_free_list(mii_bus_pd->mac_peripherals); |
1712 | ||
080c8255 GY |
1713 | return 0; |
1714 | } | |
1715 | ||
1716 | static struct platform_driver bfin_mii_bus_driver = { | |
1717 | .probe = bfin_mii_bus_probe, | |
1718 | .remove = __devexit_p(bfin_mii_bus_remove), | |
1719 | .driver = { | |
1720 | .name = "bfin_mii_bus", | |
1721 | .owner = THIS_MODULE, | |
1722 | }, | |
1723 | }; | |
1724 | ||
e190d6b1 BW |
1725 | static struct platform_driver bfin_mac_driver = { |
1726 | .probe = bfin_mac_probe, | |
d7b843d3 | 1727 | .remove = __devexit_p(bfin_mac_remove), |
e190d6b1 BW |
1728 | .resume = bfin_mac_resume, |
1729 | .suspend = bfin_mac_suspend, | |
1730 | .driver = { | |
c6dd5098 | 1731 | .name = KBUILD_MODNAME, |
72abb461 KS |
1732 | .owner = THIS_MODULE, |
1733 | }, | |
e190d6b1 BW |
1734 | }; |
1735 | ||
1736 | static int __init bfin_mac_init(void) | |
1737 | { | |
080c8255 GY |
1738 | int ret; |
1739 | ret = platform_driver_register(&bfin_mii_bus_driver); | |
1740 | if (!ret) | |
1741 | return platform_driver_register(&bfin_mac_driver); | |
1742 | return -ENODEV; | |
e190d6b1 BW |
1743 | } |
1744 | ||
1745 | module_init(bfin_mac_init); | |
1746 | ||
1747 | static void __exit bfin_mac_cleanup(void) | |
1748 | { | |
1749 | platform_driver_unregister(&bfin_mac_driver); | |
080c8255 | 1750 | platform_driver_unregister(&bfin_mii_bus_driver); |
e190d6b1 BW |
1751 | } |
1752 | ||
1753 | module_exit(bfin_mac_cleanup); | |
72abb461 | 1754 |