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net: replace continue with break to reduce unnecessary loop in xxx_xmarksources
[deliverable/linux.git] / drivers / net / ethernet / adi / bfin_mac.c
CommitLineData
e190d6b1 1/*
2fb9d6f5 2 * Blackfin On-Chip MAC Driver
e190d6b1 3 *
02460d08 4 * Copyright 2004-2010 Analog Devices Inc.
e190d6b1 5 *
2fb9d6f5 6 * Enter bugs at http://blackfin.uclinux.org/
e190d6b1 7 *
2fb9d6f5 8 * Licensed under the GPL-2 or later.
e190d6b1
BW		 9 */
10
c6dd5098
MF		 11#define DRV_VERSION "1.1"
12#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
e190d6b1
BW		 16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/crc32.h>
28#include <linux/device.h>
29#include <linux/spinlock.h>
e190d6b1 30#include <linux/mii.h>
e190d6b1
BW		 31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
679dce39 33#include <linux/ethtool.h>
e190d6b1 34#include <linux/skbuff.h>
e190d6b1 35#include <linux/platform_device.h>
e190d6b1
BW		 36
37#include <asm/dma.h>
38#include <linux/dma-mapping.h>
39
fe92afed 40#include <asm/div64.h>
98f672ca 41#include <asm/dpmc.h>
e190d6b1
BW		 42#include <asm/blackfin.h>
43#include <asm/cacheflush.h>
44#include <asm/portmux.h>
3dcc1e7f 45#include <mach/pll.h>
e190d6b1
BW		 46
47#include "bfin_mac.h"
48
c6dd5098 49MODULE_AUTHOR("Bryan Wu, Luke Yang");
e190d6b1
BW		 50MODULE_LICENSE("GPL");
51MODULE_DESCRIPTION(DRV_DESC);
72abb461 52MODULE_ALIAS("platform:bfin_mac");
e190d6b1
BW		 53
54#if defined(CONFIG_BFIN_MAC_USE_L1)
118133e6
SZ		 55# define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56# define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
e190d6b1 57#else
118133e6
SZ		 58# define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60# define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
e190d6b1
BW		 62#endif
63
64#define PKT_BUF_SZ 1580
65
66#define MAX_TIMEOUT_CNT 500
67
68/* pointers to maintain transmit list */
69static struct net_dma_desc_tx *tx_list_head;
70static struct net_dma_desc_tx *tx_list_tail;
71static struct net_dma_desc_rx *rx_list_head;
72static struct net_dma_desc_rx *rx_list_tail;
73static struct net_dma_desc_rx *current_rx_ptr;
74static struct net_dma_desc_tx *current_tx_ptr;
75static struct net_dma_desc_tx *tx_desc;
76static struct net_dma_desc_rx *rx_desc;
77
78static void desc_list_free(void)
79{
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
82 int i;
83#if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
85#endif
86
87 if (tx_desc) {
88 t = tx_list_head;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
90 if (t) {
91 if (t->skb) {
92 dev_kfree_skb(t->skb);
93 t->skb = NULL;
94 }
95 t = t->next;
96 }
97 }
118133e6 98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
e190d6b1
BW		 99 }
100
101 if (rx_desc) {
102 r = rx_list_head;
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
104 if (r) {
105 if (r->skb) {
106 dev_kfree_skb(r->skb);
107 r->skb = NULL;
108 }
109 r = r->next;
110 }
111 }
118133e6 112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
e190d6b1
BW		 113 }
114}
115
1ab0d2ec 116static int desc_list_init(struct net_device *dev)
e190d6b1
BW		 117{
118 int i;
119 struct sk_buff *new_skb;
120#if !defined(CONFIG_BFIN_MAC_USE_L1)
121 /*
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
124 */
125 dma_addr_t dma_handle;
126#endif
127
128 tx_desc = bfin_mac_alloc(&dma_handle,
118133e6 129 sizeof(struct net_dma_desc_tx),
e190d6b1
BW		 130 CONFIG_BFIN_TX_DESC_NUM);
131 if (tx_desc == NULL)
132 goto init_error;
133
134 rx_desc = bfin_mac_alloc(&dma_handle,
118133e6 135 sizeof(struct net_dma_desc_rx),
e190d6b1
BW		 136 CONFIG_BFIN_RX_DESC_NUM);
137 if (rx_desc == NULL)
138 goto init_error;
139
140 /* init tx_list */
141 tx_list_head = tx_list_tail = tx_desc;
142
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
147
148 /*
149 * disable DMA
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
153 * large desc flow
154 */
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
157 a->x_count = 0;
158 a->next_dma_desc = b;
159
160 /*
161 * enabled DMA
162 * write to memory WNR = 1
163 * wordsize is 32 bits
164 * disable interrupt
165 * 6 half words is desc size
166 * large desc flow
167 */
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
170 b->x_count = 0;
171
172 t->skb = NULL;
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
175 tx_list_tail = t;
176 }
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
180
181 /* init rx_list */
182 rx_list_head = rx_list_tail = rx_desc;
183
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
188
189 /* allocate a new skb for next time receive */
1ab0d2ec 190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1 191 if (!new_skb) {
c6dd5098 192 pr_notice("init: low on mem - packet dropped\n");
e190d6b1
BW		 193 goto init_error;
194 }
015dac88 195 skb_reserve(new_skb, NET_IP_ALIGN);
f6e1e4f3
SZ		 196 /* Invidate the data cache of skb->data range when it is write back
197 * cache. It will prevent overwritting the new data from DMA
198 */
199 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
200 (unsigned long)new_skb->end);
e190d6b1
BW		 201 r->skb = new_skb;
202
203 /*
204 * enabled DMA
205 * write to memory WNR = 1
206 * wordsize is 32 bits
207 * disable interrupt
208 * 6 half words is desc size
209 * large desc flow
210 */
211 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
212 /* since RXDWA is enabled */
213 a->start_addr = (unsigned long)new_skb->data - 2;
214 a->x_count = 0;
215 a->next_dma_desc = b;
216
217 /*
218 * enabled DMA
219 * write to memory WNR = 1
220 * wordsize is 32 bits
221 * enable interrupt
222 * 6 half words is desc size
223 * large desc flow
224 */
225 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
226 NDSIZE_6 | DMAFLOW_LARGE;
227 b->start_addr = (unsigned long)(&(r->status));
228 b->x_count = 0;
229
230 rx_list_tail->desc_b.next_dma_desc = a;
231 rx_list_tail->next = r;
232 rx_list_tail = r;
233 }
234 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
235 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
236 current_rx_ptr = rx_list_head;
237
238 return 0;
239
240init_error:
241 desc_list_free();
c6dd5098 242 pr_err("kmalloc failed\n");
e190d6b1
BW		 243 return -ENOMEM;
244}
245
246
247/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
248
4ae5a3ad
BW		 249/*
250 * MII operations
251 */
e190d6b1 252/* Wait until the previous MDC/MDIO transaction has completed */
2bfa0f0c 253static int bfin_mdio_poll(void)
e190d6b1
BW		 254{
255 int timeout_cnt = MAX_TIMEOUT_CNT;
256
257 /* poll the STABUSY bit */
258 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
6db9e461 259 udelay(1);
e190d6b1 260 if (timeout_cnt-- < 0) {
c6dd5098 261 pr_err("wait MDC/MDIO transaction to complete timeout\n");
2bfa0f0c 262 return -ETIMEDOUT;
e190d6b1
BW		 263 }
264 }
2bfa0f0c
MF		 265
266 return 0;
e190d6b1
BW		 267}
268
269/* Read an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e 270static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
e190d6b1 271{
2bfa0f0c
MF		 272 int ret;
273
274 ret = bfin_mdio_poll();
275 if (ret)
276 return ret;
4ae5a3ad 277
e190d6b1 278 /* read mode */
4ae5a3ad
BW		 279 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
280 SET_REGAD((u16) regnum) |
e190d6b1 281 STABUSY);
e190d6b1 282
2bfa0f0c
MF		 283 ret = bfin_mdio_poll();
284 if (ret)
285 return ret;
4ae5a3ad
BW		 286
287 return (int) bfin_read_EMAC_STADAT();
e190d6b1
BW		 288}
289
290/* Write an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e
AB		 291static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
292 u16 value)
e190d6b1 293{
2bfa0f0c
MF		 294 int ret;
295
296 ret = bfin_mdio_poll();
297 if (ret)
298 return ret;
4ae5a3ad
BW		 299
300 bfin_write_EMAC_STADAT((u32) value);
e190d6b1
BW		 301
302 /* write mode */
4ae5a3ad
BW		 303 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
304 SET_REGAD((u16) regnum) |
e190d6b1
BW		 305 STAOP |
306 STABUSY);
307
2bfa0f0c 308 return bfin_mdio_poll();
e190d6b1
BW		 309}
310
0ed0563e 311static int bfin_mdiobus_reset(struct mii_bus *bus)
e190d6b1 312{
4ae5a3ad 313 return 0;
e190d6b1
BW		 314}
315
7ef0a7ee 316static void bfin_mac_adjust_link(struct net_device *dev)
e190d6b1 317{
7ef0a7ee 318 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 319 struct phy_device *phydev = lp->phydev;
320 unsigned long flags;
321 int new_state = 0;
322
323 spin_lock_irqsave(&lp->lock, flags);
324 if (phydev->link) {
325 /* Now we make sure that we can be in full duplex mode.
326 * If not, we operate in half-duplex mode. */
327 if (phydev->duplex != lp->old_duplex) {
328 u32 opmode = bfin_read_EMAC_OPMODE();
329 new_state = 1;
330
331 if (phydev->duplex)
332 opmode |= FDMODE;
333 else
334 opmode &= ~(FDMODE);
335
336 bfin_write_EMAC_OPMODE(opmode);
337 lp->old_duplex = phydev->duplex;
338 }
e190d6b1 339
4ae5a3ad 340 if (phydev->speed != lp->old_speed) {
02460d08
SZ		 341 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
342 u32 opmode = bfin_read_EMAC_OPMODE();
343 switch (phydev->speed) {
344 case 10:
345 opmode |= RMII_10;
346 break;
347 case 100:
348 opmode &= ~RMII_10;
349 break;
350 default:
c6dd5098
MF		 351 netdev_warn(dev,
352 "Ack! Speed (%d) is not 10/100!\n",
353 phydev->speed);
02460d08
SZ		 354 break;
355 }
356 bfin_write_EMAC_OPMODE(opmode);
4ae5a3ad 357 }
e190d6b1 358
4ae5a3ad
BW		 359 new_state = 1;
360 lp->old_speed = phydev->speed;
361 }
e190d6b1 362
4ae5a3ad
BW		 363 if (!lp->old_link) {
364 new_state = 1;
365 lp->old_link = 1;
4ae5a3ad
BW		 366 }
367 } else if (lp->old_link) {
368 new_state = 1;
369 lp->old_link = 0;
370 lp->old_speed = 0;
371 lp->old_duplex = -1;
e190d6b1
BW		 372 }
373
4ae5a3ad
BW		 374 if (new_state) {
375 u32 opmode = bfin_read_EMAC_OPMODE();
376 phy_print_status(phydev);
377 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
e190d6b1 378 }
4ae5a3ad
BW		 379
380 spin_unlock_irqrestore(&lp->lock, flags);
e190d6b1
BW		 381}
382
7cc8f381
BW		 383/* MDC = 2.5 MHz */
384#define MDC_CLK 2500000
385
02460d08 386static int mii_probe(struct net_device *dev, int phy_mode)
e190d6b1 387{
7ef0a7ee 388 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 389 struct phy_device *phydev = NULL;
390 unsigned short sysctl;
391 int i;
7cc8f381 392 u32 sclk, mdc_div;
e190d6b1 393
4ae5a3ad 394 /* Enable PHY output early */
98f672ca
MF		 395 if (!(bfin_read_VR_CTL() & CLKBUFOE))
396 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
e190d6b1 397
7cc8f381
BW		 398 sclk = get_sclk();
399 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
400
4ae5a3ad 401 sysctl = bfin_read_EMAC_SYSCTL();
9dc7f30e 402 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
e190d6b1 403 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1 404
02460d08
SZ		 405 /* search for connected PHY device */
406 for (i = 0; i < PHY_MAX_ADDR; ++i) {
298cf9be 407 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
e190d6b1 408
4ae5a3ad
BW		 409 if (!tmp_phydev)
410 continue; /* no PHY here... */
e190d6b1 411
4ae5a3ad
BW		 412 phydev = tmp_phydev;
413 break; /* found it */
414 }
415
416 /* now we are supposed to have a proper phydev, to attach to... */
417 if (!phydev) {
c6dd5098 418 netdev_err(dev, "no phy device found\n");
4ae5a3ad 419 return -ENODEV;
e190d6b1
BW		 420 }
421
02460d08
SZ		 422 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
423 phy_mode != PHY_INTERFACE_MODE_MII) {
c6dd5098 424 netdev_err(dev, "invalid phy interface mode\n");
02460d08
SZ		 425 return -EINVAL;
426 }
427
c2313557 428 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
02460d08 429 0, phy_mode);
e190d6b1 430
4ae5a3ad 431 if (IS_ERR(phydev)) {
c6dd5098 432 netdev_err(dev, "could not attach PHY\n");
4ae5a3ad
BW		 433 return PTR_ERR(phydev);
434 }
435
436 /* mask with MAC supported features */
437 phydev->supported &= (SUPPORTED_10baseT_Half
438 | SUPPORTED_10baseT_Full
439 | SUPPORTED_100baseT_Half
440 | SUPPORTED_100baseT_Full
441 | SUPPORTED_Autoneg
442 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
443 | SUPPORTED_MII
444 | SUPPORTED_TP);
445
446 phydev->advertising = phydev->supported;
447
448 lp->old_link = 0;
449 lp->old_speed = 0;
450 lp->old_duplex = -1;
451 lp->phydev = phydev;
452
c6dd5098
MF		 453 pr_info("attached PHY driver [%s] "
454 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
455 phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
456 MDC_CLK, mdc_div, sclk/1000000);
4ae5a3ad
BW		 457
458 return 0;
459}
460
679dce39
BW		 461/*
462 * Ethtool support
463 */
464
53fd3f28
MH		 465/*
466 * interrupt routine for magic packet wakeup
467 */
468static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
469{
470 return IRQ_HANDLED;
471}
472
679dce39
BW		 473static int
474bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
475{
476 struct bfin_mac_local *lp = netdev_priv(dev);
477
478 if (lp->phydev)
479 return phy_ethtool_gset(lp->phydev, cmd);
480
481 return -EINVAL;
482}
483
484static int
485bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
486{
487 struct bfin_mac_local *lp = netdev_priv(dev);
488
489 if (!capable(CAP_NET_ADMIN))
490 return -EPERM;
491
492 if (lp->phydev)
493 return phy_ethtool_sset(lp->phydev, cmd);
494
495 return -EINVAL;
496}
497
498static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
499 struct ethtool_drvinfo *info)
500{
c6dd5098 501 strcpy(info->driver, KBUILD_MODNAME);
679dce39
BW		 502 strcpy(info->version, DRV_VERSION);
503 strcpy(info->fw_version, "N/A");
c2313557 504 strcpy(info->bus_info, dev_name(&dev->dev));
679dce39
BW		 505}
506
53fd3f28
MH		 507static void bfin_mac_ethtool_getwol(struct net_device *dev,
508 struct ethtool_wolinfo *wolinfo)
509{
510 struct bfin_mac_local *lp = netdev_priv(dev);
511
512 wolinfo->supported = WAKE_MAGIC;
513 wolinfo->wolopts = lp->wol;
514}
515
516static int bfin_mac_ethtool_setwol(struct net_device *dev,
517 struct ethtool_wolinfo *wolinfo)
518{
519 struct bfin_mac_local *lp = netdev_priv(dev);
520 int rc;
521
522 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
523 WAKE_UCAST |
524 WAKE_MCAST |
525 WAKE_BCAST |
526 WAKE_ARP))
527 return -EOPNOTSUPP;
528
529 lp->wol = wolinfo->wolopts;
530
531 if (lp->wol && !lp->irq_wake_requested) {
532 /* register wake irq handler */
533 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
534 IRQF_DISABLED, "EMAC_WAKE", dev);
535 if (rc)
536 return rc;
537 lp->irq_wake_requested = true;
538 }
539
540 if (!lp->wol && lp->irq_wake_requested) {
541 free_irq(IRQ_MAC_WAKEDET, dev);
542 lp->irq_wake_requested = false;
543 }
544
545 /* Make sure the PHY driver doesn't suspend */
546 device_init_wakeup(&dev->dev, lp->wol);
547
548 return 0;
549}
550
a85bbddd
RC		 551static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
552 struct ethtool_ts_info *info);
553{
554 info->so_timestamping =
555 SOF_TIMESTAMPING_TX_HARDWARE |
556 SOF_TIMESTAMPING_RX_HARDWARE |
557 SOF_TIMESTAMPING_SYS_HARDWARE;
558 info->phc_index = -1;
559 info->tx_types =
560 (1 << HWTSTAMP_TX_OFF) |
561 (1 << HWTSTAMP_TX_ON);
562 info->rx_filters =
563 (1 << HWTSTAMP_FILTER_NONE) |
564 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
565 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
566 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
567 return 0;
568}
569
0fc0b732 570static const struct ethtool_ops bfin_mac_ethtool_ops = {
679dce39
BW		 571 .get_settings = bfin_mac_ethtool_getsettings,
572 .set_settings = bfin_mac_ethtool_setsettings,
573 .get_link = ethtool_op_get_link,
574 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
53fd3f28
MH		 575 .get_wol = bfin_mac_ethtool_getwol,
576 .set_wol = bfin_mac_ethtool_setwol,
a85bbddd 577 .get_ts_info = bfin_mac_ethtool_get_ts_info,
679dce39
BW		 578};
579
4ae5a3ad 580/**************************************************************************/
5ca1bb5a 581static void setup_system_regs(struct net_device *dev)
4ae5a3ad 582{
02460d08
SZ		 583 struct bfin_mac_local *lp = netdev_priv(dev);
584 int i;
4ae5a3ad
BW		 585 unsigned short sysctl;
586
587 /*
588 * Odd word alignment for Receive Frame DMA word
589 * Configure checksum support and rcve frame word alignment
590 */
591 sysctl = bfin_read_EMAC_SYSCTL();
02460d08
SZ		 592 /*
593 * check if interrupt is requested for any PHY,
594 * enable PHY interrupt only if needed
595 */
596 for (i = 0; i < PHY_MAX_ADDR; ++i)
597 if (lp->mii_bus->irq[i] != PHY_POLL)
598 break;
599 if (i < PHY_MAX_ADDR)
600 sysctl |= PHYIE;
812a9de7 601 sysctl |= RXDWA;
4ae5a3ad 602#if defined(BFIN_MAC_CSUM_OFFLOAD)
812a9de7 603 sysctl |= RXCKS;
4ae5a3ad 604#else
812a9de7 605 sysctl &= ~RXCKS;
4ae5a3ad
BW		 606#endif
607 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1
BW		 608
609 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
610
c599bd6b
MF		 611 /* Set vlan regs to let 1522 bytes long packets pass through */
612 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
613 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
614
e190d6b1
BW		 615 /* Initialize the TX DMA channel registers */
616 bfin_write_DMA2_X_COUNT(0);
617 bfin_write_DMA2_X_MODIFY(4);
618 bfin_write_DMA2_Y_COUNT(0);
619 bfin_write_DMA2_Y_MODIFY(0);
620
621 /* Initialize the RX DMA channel registers */
622 bfin_write_DMA1_X_COUNT(0);
623 bfin_write_DMA1_X_MODIFY(4);
624 bfin_write_DMA1_Y_COUNT(0);
625 bfin_write_DMA1_Y_MODIFY(0);
626}
627
73f83182 628static void setup_mac_addr(u8 *mac_addr)
e190d6b1
BW		 629{
630 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
631 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
632
633 /* this depends on a little-endian machine */
634 bfin_write_EMAC_ADDRLO(addr_low);
635 bfin_write_EMAC_ADDRHI(addr_hi);
636}
637
7ef0a7ee 638static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
73f83182
AL		 639{
640 struct sockaddr *addr = p;
641 if (netif_running(dev))
642 return -EBUSY;
643 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5055d2f2 644 dev->addr_assign_type &= ~NET_ADDR_RANDOM;
73f83182
AL		 645 setup_mac_addr(dev->dev_addr);
646 return 0;
647}
648
fe92afed
BS		 649#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
650#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
651
652static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
653 struct ifreq *ifr, int cmd)
654{
655 struct hwtstamp_config config;
656 struct bfin_mac_local *lp = netdev_priv(netdev);
657 u16 ptpctl;
658 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
659
660 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
661 return -EFAULT;
662
663 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
664 __func__, config.flags, config.tx_type, config.rx_filter);
665
666 /* reserved for future extensions */
667 if (config.flags)
668 return -EINVAL;
669
670 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
671 (config.tx_type != HWTSTAMP_TX_ON))
672 return -ERANGE;
673
674 ptpctl = bfin_read_EMAC_PTP_CTL();
675
676 switch (config.rx_filter) {
677 case HWTSTAMP_FILTER_NONE:
678 /*
679 * Dont allow any timestamping
680 */
681 ptpfv3 = 0xFFFFFFFF;
682 bfin_write_EMAC_PTP_FV3(ptpfv3);
683 break;
684 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
685 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
686 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
687 /*
688 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
689 * to enable all the field matches.
690 */
691 ptpctl &= ~0x1F00;
692 bfin_write_EMAC_PTP_CTL(ptpctl);
693 /*
694 * Keep the default values of the EMAC_PTP_FOFF register.
695 */
696 ptpfoff = 0x4A24170C;
697 bfin_write_EMAC_PTP_FOFF(ptpfoff);
698 /*
699 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
700 * registers.
701 */
702 ptpfv1 = 0x11040800;
703 bfin_write_EMAC_PTP_FV1(ptpfv1);
704 ptpfv2 = 0x0140013F;
705 bfin_write_EMAC_PTP_FV2(ptpfv2);
706 /*
707 * The default value (0xFFFC) allows the timestamping of both
708 * received Sync messages and Delay_Req messages.
709 */
710 ptpfv3 = 0xFFFFFFFC;
711 bfin_write_EMAC_PTP_FV3(ptpfv3);
712
713 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
714 break;
715 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
716 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
717 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
718 /* Clear all five comparison mask bits (bits[12:8]) in the
719 * EMAC_PTP_CTL register to enable all the field matches.
720 */
721 ptpctl &= ~0x1F00;
722 bfin_write_EMAC_PTP_CTL(ptpctl);
723 /*
724 * Keep the default values of the EMAC_PTP_FOFF register, except set
725 * the PTPCOF field to 0x2A.
726 */
727 ptpfoff = 0x2A24170C;
728 bfin_write_EMAC_PTP_FOFF(ptpfoff);
729 /*
730 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
731 * registers.
732 */
733 ptpfv1 = 0x11040800;
734 bfin_write_EMAC_PTP_FV1(ptpfv1);
735 ptpfv2 = 0x0140013F;
736 bfin_write_EMAC_PTP_FV2(ptpfv2);
737 /*
738 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
739 * the value to 0xFFF0.
740 */
741 ptpfv3 = 0xFFFFFFF0;
742 bfin_write_EMAC_PTP_FV3(ptpfv3);
743
744 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
745 break;
746 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
747 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
748 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
749 /*
750 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
751 * EFTM and PTPCM field comparison.
752 */
753 ptpctl &= ~0x1100;
754 bfin_write_EMAC_PTP_CTL(ptpctl);
755 /*
756 * Keep the default values of all the fields of the EMAC_PTP_FOFF
757 * register, except set the PTPCOF field to 0x0E.
758 */
759 ptpfoff = 0x0E24170C;
760 bfin_write_EMAC_PTP_FOFF(ptpfoff);
761 /*
762 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
763 * corresponds to PTP messages on the MAC layer.
764 */
765 ptpfv1 = 0x110488F7;
766 bfin_write_EMAC_PTP_FV1(ptpfv1);
767 ptpfv2 = 0x0140013F;
768 bfin_write_EMAC_PTP_FV2(ptpfv2);
769 /*
770 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
771 * messages, set the value to 0xFFF0.
772 */
773 ptpfv3 = 0xFFFFFFF0;
774 bfin_write_EMAC_PTP_FV3(ptpfv3);
775
776 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
777 break;
778 default:
779 return -ERANGE;
780 }
781
782 if (config.tx_type == HWTSTAMP_TX_OFF &&
783 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
784 ptpctl &= ~PTP_EN;
785 bfin_write_EMAC_PTP_CTL(ptpctl);
786
787 SSYNC();
788 } else {
789 ptpctl |= PTP_EN;
790 bfin_write_EMAC_PTP_CTL(ptpctl);
791
792 /*
793 * clear any existing timestamp
794 */
795 bfin_read_EMAC_PTP_RXSNAPLO();
796 bfin_read_EMAC_PTP_RXSNAPHI();
797
798 bfin_read_EMAC_PTP_TXSNAPLO();
799 bfin_read_EMAC_PTP_TXSNAPHI();
800
801 /*
802 * Set registers so that rollover occurs soon to test this.
803 */
804 bfin_write_EMAC_PTP_TIMELO(0x00000000);
805 bfin_write_EMAC_PTP_TIMEHI(0xFF800000);
806
807 SSYNC();
808
809 lp->compare.last_update = 0;
810 timecounter_init(&lp->clock,
811 &lp->cycles,
812 ktime_to_ns(ktime_get_real()));
813 timecompare_update(&lp->compare, 0);
814 }
815
816 lp->stamp_cfg = config;
817 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
818 -EFAULT : 0;
819}
820
821static void bfin_dump_hwtamp(char *s, ktime_t *hw, ktime_t *ts, struct timecompare *cmp)
822{
823 ktime_t sys = ktime_get_real();
824
825 pr_debug("%s %s hardware:%d,%d transform system:%d,%d system:%d,%d, cmp:%lld, %lld\n",
826 __func__, s, hw->tv.sec, hw->tv.nsec, ts->tv.sec, ts->tv.nsec, sys.tv.sec,
827 sys.tv.nsec, cmp->offset, cmp->skew);
828}
829
830static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
831{
832 struct bfin_mac_local *lp = netdev_priv(netdev);
fe92afed 833
2244d07b 834 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
fe92afed
BS		 835 int timeout_cnt = MAX_TIMEOUT_CNT;
836
837 /* When doing time stamping, keep the connection to the socket
838 * a while longer
839 */
2244d07b 840 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
fe92afed
BS		 841
842 /*
843 * The timestamping is done at the EMAC module's MII/RMII interface
844 * when the module sees the Start of Frame of an event message packet. This
845 * interface is the closest possible place to the physical Ethernet transmission
846 * medium, providing the best timing accuracy.
847 */
848 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
849 udelay(1);
850 if (timeout_cnt == 0)
c6dd5098 851 netdev_err(netdev, "timestamp the TX packet failed\n");
fe92afed
BS		 852 else {
853 struct skb_shared_hwtstamps shhwtstamps;
854 u64 ns;
855 u64 regval;
856
857 regval = bfin_read_EMAC_PTP_TXSNAPLO();
858 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
859 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
860 ns = timecounter_cyc2time(&lp->clock,
861 regval);
862 timecompare_update(&lp->compare, ns);
863 shhwtstamps.hwtstamp = ns_to_ktime(ns);
864 shhwtstamps.syststamp =
865 timecompare_transform(&lp->compare, ns);
866 skb_tstamp_tx(skb, &shhwtstamps);
867
868 bfin_dump_hwtamp("TX", &shhwtstamps.hwtstamp, &shhwtstamps.syststamp, &lp->compare);
869 }
870 }
871}
872
873static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
874{
875 struct bfin_mac_local *lp = netdev_priv(netdev);
876 u32 valid;
877 u64 regval, ns;
878 struct skb_shared_hwtstamps *shhwtstamps;
879
880 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
881 return;
882
883 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
884 if (!valid)
885 return;
886
887 shhwtstamps = skb_hwtstamps(skb);
888
889 regval = bfin_read_EMAC_PTP_RXSNAPLO();
890 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
891 ns = timecounter_cyc2time(&lp->clock, regval);
892 timecompare_update(&lp->compare, ns);
893 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
894 shhwtstamps->hwtstamp = ns_to_ktime(ns);
895 shhwtstamps->syststamp = timecompare_transform(&lp->compare, ns);
896
897 bfin_dump_hwtamp("RX", &shhwtstamps->hwtstamp, &shhwtstamps->syststamp, &lp->compare);
898}
899
900/*
901 * bfin_read_clock - read raw cycle counter (to be used by time counter)
902 */
903static cycle_t bfin_read_clock(const struct cyclecounter *tc)
904{
905 u64 stamp;
906
907 stamp = bfin_read_EMAC_PTP_TIMELO();
908 stamp |= (u64)bfin_read_EMAC_PTP_TIMEHI() << 32ULL;
909
910 return stamp;
911}
912
913#define PTP_CLK 25000000
914
915static void bfin_mac_hwtstamp_init(struct net_device *netdev)
916{
917 struct bfin_mac_local *lp = netdev_priv(netdev);
918 u64 append;
919
920 /* Initialize hardware timer */
921 append = PTP_CLK * (1ULL << 32);
922 do_div(append, get_sclk());
923 bfin_write_EMAC_PTP_ADDEND((u32)append);
924
925 memset(&lp->cycles, 0, sizeof(lp->cycles));
926 lp->cycles.read = bfin_read_clock;
927 lp->cycles.mask = CLOCKSOURCE_MASK(64);
928 lp->cycles.mult = 1000000000 / PTP_CLK;
929 lp->cycles.shift = 0;
930
931 /* Synchronize our NIC clock against system wall clock */
932 memset(&lp->compare, 0, sizeof(lp->compare));
933 lp->compare.source = &lp->clock;
934 lp->compare.target = ktime_get_real;
935 lp->compare.num_samples = 10;
936
937 /* Initialize hwstamp config */
938 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
939 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
940}
941
942#else
943# define bfin_mac_hwtstamp_is_none(cfg) 0
944# define bfin_mac_hwtstamp_init(dev)
945# define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
946# define bfin_rx_hwtstamp(dev, skb)
947# define bfin_tx_hwtstamp(dev, skb)
948#endif
949
4fcc3d34
SZ		 950static inline void _tx_reclaim_skb(void)
951{
952 do {
953 tx_list_head->desc_a.config &= ~DMAEN;
954 tx_list_head->status.status_word = 0;
955 if (tx_list_head->skb) {
956 dev_kfree_skb(tx_list_head->skb);
957 tx_list_head->skb = NULL;
958 }
959 tx_list_head = tx_list_head->next;
960
961 } while (tx_list_head->status.status_word != 0);
962}
963
964static void tx_reclaim_skb(struct bfin_mac_local *lp)
e190d6b1
BW		 965{
966 int timeout_cnt = MAX_TIMEOUT_CNT;
967
4fcc3d34
SZ		 968 if (tx_list_head->status.status_word != 0)
969 _tx_reclaim_skb();
e190d6b1 970
4fcc3d34 971 if (current_tx_ptr->next == tx_list_head) {
e190d6b1 972 while (tx_list_head->status.status_word == 0) {
4fcc3d34 973 /* slow down polling to avoid too many queue stop. */
015dac88 974 udelay(10);
4fcc3d34
SZ		 975 /* reclaim skb if DMA is not running. */
976 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
977 break;
978 if (timeout_cnt-- < 0)
e190d6b1 979 break;
e190d6b1 980 }
4fcc3d34
SZ		 981
982 if (timeout_cnt >= 0)
983 _tx_reclaim_skb();
984 else
985 netif_stop_queue(lp->ndev);
e190d6b1
BW		 986 }
987
4fcc3d34
SZ		 988 if (current_tx_ptr->next != tx_list_head &&
989 netif_queue_stopped(lp->ndev))
990 netif_wake_queue(lp->ndev);
991
992 if (tx_list_head != current_tx_ptr) {
993 /* shorten the timer interval if tx queue is stopped */
994 if (netif_queue_stopped(lp->ndev))
995 lp->tx_reclaim_timer.expires =
996 jiffies + (TX_RECLAIM_JIFFIES >> 4);
997 else
998 lp->tx_reclaim_timer.expires =
999 jiffies + TX_RECLAIM_JIFFIES;
1000
1001 mod_timer(&lp->tx_reclaim_timer,
1002 lp->tx_reclaim_timer.expires);
1003 }
e190d6b1 1004
e190d6b1 1005 return;
4fcc3d34 1006}
e190d6b1 1007
4fcc3d34
SZ		 1008static void tx_reclaim_skb_timeout(unsigned long lp)
1009{
1010 tx_reclaim_skb((struct bfin_mac_local *)lp);
e190d6b1
BW		 1011}
1012
7ef0a7ee 1013static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
e190d6b1
BW		 1014 struct net_device *dev)
1015{
4fcc3d34 1016 struct bfin_mac_local *lp = netdev_priv(dev);
a50c0c05 1017 u16 *data;
015dac88 1018 u32 data_align = (unsigned long)(skb->data) & 0x3;
fe92afed 1019
e190d6b1
BW		 1020 current_tx_ptr->skb = skb;
1021
015dac88
MH		 1022 if (data_align == 0x2) {
1023 /* move skb->data to current_tx_ptr payload */
1024 data = (u16 *)(skb->data) - 1;
fe92afed
BS		 1025 *data = (u16)(skb->len);
1026 /*
1027 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1028 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1029 * of this field are the length of the packet payload in bytes and the higher
1030 * 4 bits are the timestamping enable field.
1031 */
2244d07b 1032 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed
BS		 1033 *data |= 0x1000;
1034
015dac88
MH		 1035 current_tx_ptr->desc_a.start_addr = (u32)data;
1036 /* this is important! */
1037 blackfin_dcache_flush_range((u32)data,
1038 (u32)((u8 *)data + skb->len + 4));
e190d6b1 1039 } else {
015dac88 1040 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
fe92afed 1041 /* enable timestamping for the sent packet */
2244d07b 1042 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed 1043 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
015dac88
MH		 1044 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1045 skb->len);
1046 current_tx_ptr->desc_a.start_addr =
1047 (u32)current_tx_ptr->packet;
015dac88
MH		 1048 blackfin_dcache_flush_range(
1049 (u32)current_tx_ptr->packet,
1050 (u32)(current_tx_ptr->packet + skb->len + 2));
e190d6b1
BW		 1051 }
1052
805a8ab3
SZ		 1053 /* make sure the internal data buffers in the core are drained
1054 * so that the DMA descriptors are completely written when the
1055 * DMA engine goes to fetch them below
1056 */
1057 SSYNC();
1058
4fcc3d34
SZ		 1059 /* always clear status buffer before start tx dma */
1060 current_tx_ptr->status.status_word = 0;
1061
e190d6b1
BW		 1062 /* enable this packet's dma */
1063 current_tx_ptr->desc_a.config |= DMAEN;
1064
1065 /* tx dma is running, just return */
015dac88 1066 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
e190d6b1
BW		 1067 goto out;
1068
1069 /* tx dma is not running */
1070 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1071 /* dma enabled, read from memory, size is 6 */
1072 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1073 /* Turn on the EMAC tx */
1074 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1075
1076out:
fe92afed
BS		 1077 bfin_tx_hwtstamp(dev, skb);
1078
e190d6b1 1079 current_tx_ptr = current_tx_ptr->next;
09f75cd7
JG		 1080 dev->stats.tx_packets++;
1081 dev->stats.tx_bytes += (skb->len);
4fcc3d34
SZ		 1082
1083 tx_reclaim_skb(lp);
1084
6ed10654 1085 return NETDEV_TX_OK;
e190d6b1
BW		 1086}
1087
ad2864d8 1088#define IP_HEADER_OFF 0
ec497b32
PM		 1089#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1090 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1091
7ef0a7ee 1092static void bfin_mac_rx(struct net_device *dev)
e190d6b1
BW		 1093{
1094 struct sk_buff *skb, *new_skb;
e190d6b1 1095 unsigned short len;
fe92afed 1096 struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
ad2864d8
SZ		 1097#if defined(BFIN_MAC_CSUM_OFFLOAD)
1098 unsigned int i;
1099 unsigned char fcs[ETH_FCS_LEN + 1];
1100#endif
e190d6b1 1101
ec497b32
PM		 1102 /* check if frame status word reports an error condition
1103 * we which case we simply drop the packet
1104 */
1105 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
c6dd5098 1106 netdev_notice(dev, "rx: receive error - packet dropped\n");
ec497b32
PM		 1107 dev->stats.rx_dropped++;
1108 goto out;
1109 }
1110
e190d6b1
BW		 1111 /* allocate a new skb for next time receive */
1112 skb = current_rx_ptr->skb;
fe92afed 1113
1ab0d2ec 1114 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1 1115 if (!new_skb) {
c6dd5098 1116 netdev_notice(dev, "rx: low on mem - packet dropped\n");
09f75cd7 1117 dev->stats.rx_dropped++;
e190d6b1
BW		 1118 goto out;
1119 }
1120 /* reserve 2 bytes for RXDWA padding */
015dac88 1121 skb_reserve(new_skb, NET_IP_ALIGN);
6e01d1a4
AD		 1122 /* Invidate the data cache of skb->data range when it is write back
1123 * cache. It will prevent overwritting the new data from DMA
1124 */
1125 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1126 (unsigned long)new_skb->end);
1127
f6e1e4f3
SZ		 1128 current_rx_ptr->skb = new_skb;
1129 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1130
e190d6b1 1131 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
ad2864d8
SZ		 1132 /* Deduce Ethernet FCS length from Ethernet payload length */
1133 len -= ETH_FCS_LEN;
e190d6b1 1134 skb_put(skb, len);
e190d6b1 1135
e190d6b1 1136 skb->protocol = eth_type_trans(skb, dev);
fe92afed
BS		 1137
1138 bfin_rx_hwtstamp(dev, skb);
1139
e190d6b1 1140#if defined(BFIN_MAC_CSUM_OFFLOAD)
ad2864d8
SZ		 1141 /* Checksum offloading only works for IPv4 packets with the standard IP header
1142 * length of 20 bytes, because the blackfin MAC checksum calculation is
1143 * based on that assumption. We must NOT use the calculated checksum if our
1144 * IP version or header break that assumption.
1145 */
1146 if (skb->data[IP_HEADER_OFF] == 0x45) {
1147 skb->csum = current_rx_ptr->status.ip_payload_csum;
1148 /*
1149 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1150 * IP checksum is based on 16-bit one's complement algorithm.
1151 * To deduce a value from checksum is equal to add its inversion.
1152 * If the IP payload len is odd, the inversed FCS should also
1153 * begin from odd address and leave first byte zero.
1154 */
1155 if (skb->len % 2) {
1156 fcs[0] = 0;
1157 for (i = 0; i < ETH_FCS_LEN; i++)
1158 fcs[i + 1] = ~skb->data[skb->len + i];
1159 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1160 } else {
1161 for (i = 0; i < ETH_FCS_LEN; i++)
1162 fcs[i] = ~skb->data[skb->len + i];
1163 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1164 }
1165 skb->ip_summed = CHECKSUM_COMPLETE;
1166 }
e190d6b1
BW		 1167#endif
1168
1169 netif_rx(skb);
09f75cd7
JG		 1170 dev->stats.rx_packets++;
1171 dev->stats.rx_bytes += len;
ec497b32 1172out:
e190d6b1
BW		 1173 current_rx_ptr->status.status_word = 0x00000000;
1174 current_rx_ptr = current_rx_ptr->next;
e190d6b1
BW		 1175}
1176
1177/* interrupt routine to handle rx and error signal */
7ef0a7ee 1178static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
e190d6b1
BW		 1179{
1180 struct net_device *dev = dev_id;
1181 int number = 0;
1182
1183get_one_packet:
1184 if (current_rx_ptr->status.status_word == 0) {
1185 /* no more new packet received */
1186 if (number == 0) {
1187 if (current_rx_ptr->next->status.status_word != 0) {
1188 current_rx_ptr = current_rx_ptr->next;
1189 goto real_rx;
1190 }
1191 }
1192 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1193 DMA_DONE | DMA_ERR);
1194 return IRQ_HANDLED;
1195 }
1196
1197real_rx:
7ef0a7ee 1198 bfin_mac_rx(dev);
e190d6b1
BW		 1199 number++;
1200 goto get_one_packet;
1201}
1202
1203#ifdef CONFIG_NET_POLL_CONTROLLER
7ef0a7ee 1204static void bfin_mac_poll(struct net_device *dev)
e190d6b1 1205{
4fcc3d34
SZ		 1206 struct bfin_mac_local *lp = netdev_priv(dev);
1207
e190d6b1 1208 disable_irq(IRQ_MAC_RX);
7ef0a7ee 1209 bfin_mac_interrupt(IRQ_MAC_RX, dev);
4fcc3d34 1210 tx_reclaim_skb(lp);
e190d6b1
BW		 1211 enable_irq(IRQ_MAC_RX);
1212}
1213#endif /* CONFIG_NET_POLL_CONTROLLER */
1214
7ef0a7ee 1215static void bfin_mac_disable(void)
e190d6b1
BW		 1216{
1217 unsigned int opmode;
1218
1219 opmode = bfin_read_EMAC_OPMODE();
1220 opmode &= (~RE);
1221 opmode &= (~TE);
1222 /* Turn off the EMAC */
1223 bfin_write_EMAC_OPMODE(opmode);
1224}
1225
1226/*
1227 * Enable Interrupts, Receive, and Transmit
1228 */
02460d08 1229static int bfin_mac_enable(struct phy_device *phydev)
e190d6b1 1230{
2bfa0f0c 1231 int ret;
e190d6b1
BW		 1232 u32 opmode;
1233
c6dd5098 1234 pr_debug("%s\n", __func__);
e190d6b1
BW		 1235
1236 /* Set RX DMA */
1237 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1238 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1239
1240 /* Wait MII done */
2bfa0f0c
MF		 1241 ret = bfin_mdio_poll();
1242 if (ret)
1243 return ret;
e190d6b1
BW		 1244
1245 /* We enable only RX here */
1246 /* ASTP : Enable Automatic Pad Stripping
1247 PR : Promiscuous Mode for test
1248 PSF : Receive frames with total length less than 64 bytes.
1249 FDMODE : Full Duplex Mode
1250 LB : Internal Loopback for test
1251 RE : Receiver Enable */
1252 opmode = bfin_read_EMAC_OPMODE();
1253 if (opmode & FDMODE)
1254 opmode |= PSF;
1255 else
1256 opmode |= DRO | DC | PSF;
1257 opmode |= RE;
1258
02460d08
SZ		 1259 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1260 opmode |= RMII; /* For Now only 100MBit are supported */
72f49050
MF		 1261#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1262 if (__SILICON_REVISION__ < 3) {
1263 /*
1264 * This isn't publicly documented (fun times!), but in
1265 * silicon <=0.2, the RX and TX pins are clocked together.
1266 * So in order to recv, we must enable the transmit side
1267 * as well. This will cause a spurious TX interrupt too,
1268 * but we can easily consume that.
1269 */
1270 opmode |= TE;
1271 }
e190d6b1 1272#endif
02460d08
SZ		 1273 }
1274
e190d6b1
BW		 1275 /* Turn on the EMAC rx */
1276 bfin_write_EMAC_OPMODE(opmode);
2bfa0f0c
MF		 1277
1278 return 0;
e190d6b1
BW		 1279}
1280
1281/* Our watchdog timed out. Called by the networking layer */
7ef0a7ee 1282static void bfin_mac_timeout(struct net_device *dev)
e190d6b1 1283{
4fcc3d34
SZ		 1284 struct bfin_mac_local *lp = netdev_priv(dev);
1285
b39d66a8 1286 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1 1287
7ef0a7ee 1288 bfin_mac_disable();
e190d6b1 1289
4fcc3d34
SZ		 1290 del_timer(&lp->tx_reclaim_timer);
1291
1292 /* reset tx queue and free skb */
1293 while (tx_list_head != current_tx_ptr) {
1294 tx_list_head->desc_a.config &= ~DMAEN;
1295 tx_list_head->status.status_word = 0;
1296 if (tx_list_head->skb) {
1297 dev_kfree_skb(tx_list_head->skb);
1298 tx_list_head->skb = NULL;
1299 }
1300 tx_list_head = tx_list_head->next;
1301 }
1302
1303 if (netif_queue_stopped(lp->ndev))
1304 netif_wake_queue(lp->ndev);
e190d6b1 1305
02460d08 1306 bfin_mac_enable(lp->phydev);
e190d6b1
BW		 1307
1308 /* We can accept TX packets again */
1ae5dc34 1309 dev->trans_start = jiffies; /* prevent tx timeout */
e190d6b1
BW		 1310 netif_wake_queue(dev);
1311}
1312
7ef0a7ee 1313static void bfin_mac_multicast_hash(struct net_device *dev)
775919bc
AW		 1314{
1315 u32 emac_hashhi, emac_hashlo;
22bedad3 1316 struct netdev_hw_addr *ha;
775919bc
AW		 1317 u32 crc;
1318
1319 emac_hashhi = emac_hashlo = 0;
1320
22bedad3 1321 netdev_for_each_mc_addr(ha, dev) {
f767b6df 1322 crc = ether_crc(ETH_ALEN, ha->addr);
775919bc
AW		 1323 crc >>= 26;
1324
1325 if (crc & 0x20)
1326 emac_hashhi |= 1 << (crc & 0x1f);
1327 else
1328 emac_hashlo |= 1 << (crc & 0x1f);
1329 }
1330
1331 bfin_write_EMAC_HASHHI(emac_hashhi);
1332 bfin_write_EMAC_HASHLO(emac_hashlo);
775919bc
AW		 1333}
1334
e190d6b1
BW		 1335/*
1336 * This routine will, depending on the values passed to it,
1337 * either make it accept multicast packets, go into
1338 * promiscuous mode (for TCPDUMP and cousins) or accept
1339 * a select set of multicast packets
1340 */
7ef0a7ee 1341static void bfin_mac_set_multicast_list(struct net_device *dev)
e190d6b1
BW		 1342{
1343 u32 sysctl;
1344
1345 if (dev->flags & IFF_PROMISC) {
c6dd5098 1346 netdev_info(dev, "set promisc mode\n");
e190d6b1 1347 sysctl = bfin_read_EMAC_OPMODE();
c0da776b 1348 sysctl |= PR;
e190d6b1 1349 bfin_write_EMAC_OPMODE(sysctl);
775919bc 1350 } else if (dev->flags & IFF_ALLMULTI) {
e190d6b1
BW		 1351 /* accept all multicast */
1352 sysctl = bfin_read_EMAC_OPMODE();
1353 sysctl |= PAM;
1354 bfin_write_EMAC_OPMODE(sysctl);
4cd24eaf 1355 } else if (!netdev_mc_empty(dev)) {
775919bc
AW		 1356 /* set up multicast hash table */
1357 sysctl = bfin_read_EMAC_OPMODE();
1358 sysctl |= HM;
1359 bfin_write_EMAC_OPMODE(sysctl);
7ef0a7ee 1360 bfin_mac_multicast_hash(dev);
e190d6b1
BW		 1361 } else {
1362 /* clear promisc or multicast mode */
1363 sysctl = bfin_read_EMAC_OPMODE();
1364 sysctl &= ~(RAF | PAM);
1365 bfin_write_EMAC_OPMODE(sysctl);
1366 }
1367}
1368
fe92afed
BS		 1369static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1370{
02460d08
SZ		 1371 struct bfin_mac_local *lp = netdev_priv(netdev);
1372
1373 if (!netif_running(netdev))
1374 return -EINVAL;
1375
fe92afed
BS		 1376 switch (cmd) {
1377 case SIOCSHWTSTAMP:
1378 return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1379 default:
02460d08
SZ		 1380 if (lp->phydev)
1381 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1382 else
1383 return -EOPNOTSUPP;
fe92afed
BS		 1384 }
1385}
1386
e190d6b1
BW		 1387/*
1388 * this puts the device in an inactive state
1389 */
7ef0a7ee 1390static void bfin_mac_shutdown(struct net_device *dev)
e190d6b1
BW		 1391{
1392 /* Turn off the EMAC */
1393 bfin_write_EMAC_OPMODE(0x00000000);
1394 /* Turn off the EMAC RX DMA */
1395 bfin_write_DMA1_CONFIG(0x0000);
1396 bfin_write_DMA2_CONFIG(0x0000);
1397}
1398
1399/*
1400 * Open and Initialize the interface
1401 *
1402 * Set up everything, reset the card, etc..
1403 */
7ef0a7ee 1404static int bfin_mac_open(struct net_device *dev)
e190d6b1 1405{
7ef0a7ee 1406 struct bfin_mac_local *lp = netdev_priv(dev);
2bfa0f0c 1407 int ret;
b39d66a8 1408 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1409
1410 /*
1411 * Check that the address is valid. If its not, refuse
1412 * to bring the device up. The user must specify an
1413 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1414 */
1415 if (!is_valid_ether_addr(dev->dev_addr)) {
c6dd5098 1416 netdev_warn(dev, "no valid ethernet hw addr\n");
e190d6b1
BW		 1417 return -EINVAL;
1418 }
1419
1420 /* initial rx and tx list */
1ab0d2ec 1421 ret = desc_list_init(dev);
2bfa0f0c
MF		 1422 if (ret)
1423 return ret;
e190d6b1 1424
4ae5a3ad 1425 phy_start(lp->phydev);
136492b2 1426 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
e190d6b1 1427 setup_system_regs(dev);
ee02fee8 1428 setup_mac_addr(dev->dev_addr);
2bfa0f0c 1429
7ef0a7ee 1430 bfin_mac_disable();
02460d08 1431 ret = bfin_mac_enable(lp->phydev);
2bfa0f0c
MF		 1432 if (ret)
1433 return ret;
e190d6b1 1434 pr_debug("hardware init finished\n");
2bfa0f0c 1435
e190d6b1
BW		 1436 netif_start_queue(dev);
1437 netif_carrier_on(dev);
1438
1439 return 0;
1440}
1441
1442/*
e190d6b1
BW		 1443 * this makes the board clean up everything that it can
1444 * and not talk to the outside world. Caused by
1445 * an 'ifconfig ethX down'
1446 */
7ef0a7ee 1447static int bfin_mac_close(struct net_device *dev)
e190d6b1 1448{
7ef0a7ee 1449 struct bfin_mac_local *lp = netdev_priv(dev);
b39d66a8 1450 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1451
1452 netif_stop_queue(dev);
1453 netif_carrier_off(dev);
1454
4ae5a3ad 1455 phy_stop(lp->phydev);
136492b2 1456 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
4ae5a3ad 1457
e190d6b1 1458 /* clear everything */
7ef0a7ee 1459 bfin_mac_shutdown(dev);
e190d6b1
BW		 1460
1461 /* free the rx/tx buffers */
1462 desc_list_free();
1463
1464 return 0;
1465}
1466
b63dc8fe
MF		 1467static const struct net_device_ops bfin_mac_netdev_ops = {
1468 .ndo_open = bfin_mac_open,
1469 .ndo_stop = bfin_mac_close,
1470 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1471 .ndo_set_mac_address = bfin_mac_set_mac_address,
1472 .ndo_tx_timeout = bfin_mac_timeout,
afc4b13d 1473 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
fe92afed 1474 .ndo_do_ioctl = bfin_mac_ioctl,
b63dc8fe
MF		 1475 .ndo_validate_addr = eth_validate_addr,
1476 .ndo_change_mtu = eth_change_mtu,
1477#ifdef CONFIG_NET_POLL_CONTROLLER
1478 .ndo_poll_controller = bfin_mac_poll,
1479#endif
1480};
1481
d7b843d3 1482static int __devinit bfin_mac_probe(struct platform_device *pdev)
e190d6b1 1483{
7ef0a7ee
BW		 1484 struct net_device *ndev;
1485 struct bfin_mac_local *lp;
080c8255 1486 struct platform_device *pd;
02460d08 1487 struct bfin_mii_bus_platform_data *mii_bus_data;
080c8255 1488 int rc;
7ef0a7ee
BW		 1489
1490 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
41de8d4c 1491 if (!ndev)
7ef0a7ee 1492 return -ENOMEM;
7ef0a7ee
BW		 1493
1494 SET_NETDEV_DEV(ndev, &pdev->dev);
1495 platform_set_drvdata(pdev, ndev);
1496 lp = netdev_priv(ndev);
4fcc3d34 1497 lp->ndev = ndev;
e190d6b1
BW		 1498
1499 /* Grab the MAC address in the MAC */
7ef0a7ee
BW		 1500 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1501 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
e190d6b1
BW		 1502
1503 /* probe mac */
1504 /*todo: how to proble? which is revision_register */
1505 bfin_write_EMAC_ADDRLO(0x12345678);
1506 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
7ef0a7ee
BW		 1507 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1508 rc = -ENODEV;
1509 goto out_err_probe_mac;
e190d6b1
BW		 1510 }
1511
e190d6b1 1512
7ef0a7ee
BW		 1513 /*
1514 * Is it valid? (Did bootloader initialize it?)
1515 * Grab the MAC from the board somehow
1516 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1517 */
5055d2f2
DK		 1518 if (!is_valid_ether_addr(ndev->dev_addr)) {
1519 if (bfin_get_ether_addr(ndev->dev_addr) ||
1520 !is_valid_ether_addr(ndev->dev_addr)) {
1521 /* Still not valid, get a random one */
1522 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1523 eth_hw_addr_random(ndev);
1524 }
1525 }
e190d6b1 1526
7ef0a7ee 1527 setup_mac_addr(ndev->dev_addr);
e190d6b1 1528
080c8255
GY		 1529 if (!pdev->dev.platform_data) {
1530 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1531 rc = -ENODEV;
1532 goto out_err_probe_mac;
7ef0a7ee 1533 }
080c8255
GY		 1534 pd = pdev->dev.platform_data;
1535 lp->mii_bus = platform_get_drvdata(pd);
0e995cd3
SZ		 1536 if (!lp->mii_bus) {
1537 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1538 rc = -ENODEV;
02460d08 1539 goto out_err_probe_mac;
0e995cd3 1540 }
080c8255 1541 lp->mii_bus->priv = ndev;
02460d08 1542 mii_bus_data = pd->dev.platform_data;
4ae5a3ad 1543
02460d08 1544 rc = mii_probe(ndev, mii_bus_data->phy_mode);
7ef0a7ee
BW		 1545 if (rc) {
1546 dev_err(&pdev->dev, "MII Probe failed!\n");
1547 goto out_err_mii_probe;
1548 }
4ae5a3ad 1549
c599bd6b
MF		 1550 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1551 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1552
e190d6b1 1553 /* Fill in the fields of the device structure with ethernet values. */
7ef0a7ee
BW		 1554 ether_setup(ndev);
1555
149da651 1556 ndev->netdev_ops = &bfin_mac_netdev_ops;
679dce39 1557 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
e190d6b1 1558
4fcc3d34
SZ		 1559 init_timer(&lp->tx_reclaim_timer);
1560 lp->tx_reclaim_timer.data = (unsigned long)lp;
1561 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1562
e190d6b1
BW		 1563 spin_lock_init(&lp->lock);
1564
1565 /* now, enable interrupts */
1566 /* register irq handler */
7ef0a7ee 1567 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
91a455f0 1568 IRQF_DISABLED, "EMAC_RX", ndev);
7ef0a7ee
BW		 1569 if (rc) {
1570 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1571 rc = -EBUSY;
1572 goto out_err_request_irq;
e190d6b1
BW		 1573 }
1574
7ef0a7ee
BW		 1575 rc = register_netdev(ndev);
1576 if (rc) {
1577 dev_err(&pdev->dev, "Cannot register net device!\n");
1578 goto out_err_reg_ndev;
e190d6b1
BW		 1579 }
1580
fe92afed
BS		 1581 bfin_mac_hwtstamp_init(ndev);
1582
7ef0a7ee 1583 /* now, print out the card info, in a short format.. */
c6dd5098 1584 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
e190d6b1 1585
7ef0a7ee 1586 return 0;
e190d6b1 1587
7ef0a7ee
BW		 1588out_err_reg_ndev:
1589 free_irq(IRQ_MAC_RX, ndev);
1590out_err_request_irq:
1591out_err_mii_probe:
298cf9be 1592 mdiobus_unregister(lp->mii_bus);
298cf9be 1593 mdiobus_free(lp->mii_bus);
7ef0a7ee
BW		 1594out_err_probe_mac:
1595 platform_set_drvdata(pdev, NULL);
1596 free_netdev(ndev);
e190d6b1 1597
7ef0a7ee 1598 return rc;
e190d6b1
BW		 1599}
1600
d7b843d3 1601static int __devexit bfin_mac_remove(struct platform_device *pdev)
e190d6b1
BW		 1602{
1603 struct net_device *ndev = platform_get_drvdata(pdev);
7ef0a7ee 1604 struct bfin_mac_local *lp = netdev_priv(ndev);
e190d6b1
BW		 1605
1606 platform_set_drvdata(pdev, NULL);
1607
080c8255 1608 lp->mii_bus->priv = NULL;
7ef0a7ee 1609
e190d6b1
BW		 1610 unregister_netdev(ndev);
1611
1612 free_irq(IRQ_MAC_RX, ndev);
1613
1614 free_netdev(ndev);
1615
e190d6b1
BW		 1616 return 0;
1617}
1618
496a34c2
BW		 1619#ifdef CONFIG_PM
1620static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
e190d6b1 1621{
496a34c2 1622 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1623 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1624
53fd3f28
MH		 1625 if (lp->wol) {
1626 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1627 bfin_write_EMAC_WKUP_CTL(MPKE);
1628 enable_irq_wake(IRQ_MAC_WAKEDET);
1629 } else {
1630 if (netif_running(net_dev))
1631 bfin_mac_close(net_dev);
1632 }
496a34c2 1633
e190d6b1
BW		 1634 return 0;
1635}
1636
1637static int bfin_mac_resume(struct platform_device *pdev)
1638{
496a34c2 1639 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1640 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1641
53fd3f28
MH		 1642 if (lp->wol) {
1643 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1644 bfin_write_EMAC_WKUP_CTL(0);
1645 disable_irq_wake(IRQ_MAC_WAKEDET);
1646 } else {
1647 if (netif_running(net_dev))
1648 bfin_mac_open(net_dev);
1649 }
496a34c2 1650
e190d6b1
BW		 1651 return 0;
1652}
496a34c2
BW		 1653#else
1654#define bfin_mac_suspend NULL
1655#define bfin_mac_resume NULL
1656#endif /* CONFIG_PM */
e190d6b1 1657
080c8255
GY		 1658static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1659{
1660 struct mii_bus *miibus;
02460d08
SZ		 1661 struct bfin_mii_bus_platform_data *mii_bus_pd;
1662 const unsigned short *pin_req;
080c8255
GY		 1663 int rc, i;
1664
02460d08
SZ		 1665 mii_bus_pd = dev_get_platdata(&pdev->dev);
1666 if (!mii_bus_pd) {
1667 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1668 return -EINVAL;
1669 }
1670
080c8255
GY		 1671 /*
1672 * We are setting up a network card,
1673 * so set the GPIO pins to Ethernet mode
1674 */
02460d08 1675 pin_req = mii_bus_pd->mac_peripherals;
c6dd5098 1676 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
080c8255
GY		 1677 if (rc) {
1678 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1679 return rc;
1680 }
1681
1682 rc = -ENOMEM;
1683 miibus = mdiobus_alloc();
1684 if (miibus == NULL)
1685 goto out_err_alloc;
1686 miibus->read = bfin_mdiobus_read;
1687 miibus->write = bfin_mdiobus_write;
1688 miibus->reset = bfin_mdiobus_reset;
1689
1690 miibus->parent = &pdev->dev;
1691 miibus->name = "bfin_mii_bus";
02460d08
SZ		 1692 miibus->phy_mask = mii_bus_pd->phy_mask;
1693
75432fd2
FF		 1694 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1695 pdev->name, pdev->id);
080c8255 1696 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
02460d08
SZ		 1697 if (!miibus->irq)
1698 goto out_err_irq_alloc;
1699
1700 for (i = rc; i < PHY_MAX_ADDR; ++i)
080c8255
GY		 1701 miibus->irq[i] = PHY_POLL;
1702
02460d08
SZ		 1703 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1704 if (rc != mii_bus_pd->phydev_number)
1705 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1706 mii_bus_pd->phydev_number);
1707 for (i = 0; i < rc; ++i) {
1708 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1709 if (phyaddr < PHY_MAX_ADDR)
1710 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1711 else
1712 dev_err(&pdev->dev,
1713 "Invalid PHY address %i for phydev %i\n",
1714 phyaddr, i);
1715 }
1716
080c8255
GY		 1717 rc = mdiobus_register(miibus);
1718 if (rc) {
1719 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1720 goto out_err_mdiobus_register;
1721 }
1722
1723 platform_set_drvdata(pdev, miibus);
1724 return 0;
1725
1726out_err_mdiobus_register:
7f267de4 1727 kfree(miibus->irq);
02460d08 1728out_err_irq_alloc:
080c8255
GY		 1729 mdiobus_free(miibus);
1730out_err_alloc:
1731 peripheral_free_list(pin_req);
1732
1733 return rc;
1734}
1735
1736static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1737{
1738 struct mii_bus *miibus = platform_get_drvdata(pdev);
02460d08
SZ		 1739 struct bfin_mii_bus_platform_data *mii_bus_pd =
1740 dev_get_platdata(&pdev->dev);
1741
080c8255
GY		 1742 platform_set_drvdata(pdev, NULL);
1743 mdiobus_unregister(miibus);
7f267de4 1744 kfree(miibus->irq);
080c8255 1745 mdiobus_free(miibus);
02460d08
SZ		 1746 peripheral_free_list(mii_bus_pd->mac_peripherals);
1747
080c8255
GY		 1748 return 0;
1749}
1750
1751static struct platform_driver bfin_mii_bus_driver = {
1752 .probe = bfin_mii_bus_probe,
1753 .remove = __devexit_p(bfin_mii_bus_remove),
1754 .driver = {
1755 .name = "bfin_mii_bus",
1756 .owner = THIS_MODULE,
1757 },
1758};
1759
e190d6b1
BW		 1760static struct platform_driver bfin_mac_driver = {
1761 .probe = bfin_mac_probe,
d7b843d3 1762 .remove = __devexit_p(bfin_mac_remove),
e190d6b1
BW		 1763 .resume = bfin_mac_resume,
1764 .suspend = bfin_mac_suspend,
1765 .driver = {
c6dd5098 1766 .name = KBUILD_MODNAME,
72abb461
KS		 1767 .owner = THIS_MODULE,
1768 },
e190d6b1
BW		 1769};
1770
1771static int __init bfin_mac_init(void)
1772{
080c8255
GY		 1773 int ret;
1774 ret = platform_driver_register(&bfin_mii_bus_driver);
1775 if (!ret)
1776 return platform_driver_register(&bfin_mac_driver);
1777 return -ENODEV;
e190d6b1
BW		 1778}
1779
1780module_init(bfin_mac_init);
1781
1782static void __exit bfin_mac_cleanup(void)
1783{
1784 platform_driver_unregister(&bfin_mac_driver);
080c8255 1785 platform_driver_unregister(&bfin_mii_bus_driver);
e190d6b1
BW		 1786}
1787
1788module_exit(bfin_mac_cleanup);
72abb461 1789
Linux kernel - Deliverables
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