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starfire: remove __dev* attributes
[deliverable/linux.git] / drivers / net / ethernet / adi / bfin_mac.c
CommitLineData
e190d6b1 1/*
2fb9d6f5 2 * Blackfin On-Chip MAC Driver
e190d6b1 3 *
02460d08 4 * Copyright 2004-2010 Analog Devices Inc.
e190d6b1 5 *
2fb9d6f5 6 * Enter bugs at http://blackfin.uclinux.org/
e190d6b1 7 *
2fb9d6f5 8 * Licensed under the GPL-2 or later.
e190d6b1
BW		 9 */
10
c6dd5098
MF		 11#define DRV_VERSION "1.1"
12#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
e190d6b1
BW		 16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/crc32.h>
28#include <linux/device.h>
29#include <linux/spinlock.h>
e190d6b1 30#include <linux/mii.h>
e190d6b1
BW		 31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
679dce39 33#include <linux/ethtool.h>
e190d6b1 34#include <linux/skbuff.h>
e190d6b1 35#include <linux/platform_device.h>
e190d6b1
BW		 36
37#include <asm/dma.h>
38#include <linux/dma-mapping.h>
39
fe92afed 40#include <asm/div64.h>
98f672ca 41#include <asm/dpmc.h>
e190d6b1
BW		 42#include <asm/blackfin.h>
43#include <asm/cacheflush.h>
44#include <asm/portmux.h>
3dcc1e7f 45#include <mach/pll.h>
e190d6b1
BW		 46
47#include "bfin_mac.h"
48
c6dd5098 49MODULE_AUTHOR("Bryan Wu, Luke Yang");
e190d6b1
BW		 50MODULE_LICENSE("GPL");
51MODULE_DESCRIPTION(DRV_DESC);
72abb461 52MODULE_ALIAS("platform:bfin_mac");
e190d6b1
BW		 53
54#if defined(CONFIG_BFIN_MAC_USE_L1)
118133e6
SZ		 55# define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56# define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
e190d6b1 57#else
118133e6
SZ		 58# define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60# define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
e190d6b1
BW		 62#endif
63
64#define PKT_BUF_SZ 1580
65
66#define MAX_TIMEOUT_CNT 500
67
68/* pointers to maintain transmit list */
69static struct net_dma_desc_tx *tx_list_head;
70static struct net_dma_desc_tx *tx_list_tail;
71static struct net_dma_desc_rx *rx_list_head;
72static struct net_dma_desc_rx *rx_list_tail;
73static struct net_dma_desc_rx *current_rx_ptr;
74static struct net_dma_desc_tx *current_tx_ptr;
75static struct net_dma_desc_tx *tx_desc;
76static struct net_dma_desc_rx *rx_desc;
77
78static void desc_list_free(void)
79{
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
82 int i;
83#if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
85#endif
86
87 if (tx_desc) {
88 t = tx_list_head;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
90 if (t) {
91 if (t->skb) {
92 dev_kfree_skb(t->skb);
93 t->skb = NULL;
94 }
95 t = t->next;
96 }
97 }
118133e6 98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
e190d6b1
BW		 99 }
100
101 if (rx_desc) {
102 r = rx_list_head;
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
104 if (r) {
105 if (r->skb) {
106 dev_kfree_skb(r->skb);
107 r->skb = NULL;
108 }
109 r = r->next;
110 }
111 }
118133e6 112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
e190d6b1
BW		 113 }
114}
115
1ab0d2ec 116static int desc_list_init(struct net_device *dev)
e190d6b1
BW		 117{
118 int i;
119 struct sk_buff *new_skb;
120#if !defined(CONFIG_BFIN_MAC_USE_L1)
121 /*
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
124 */
125 dma_addr_t dma_handle;
126#endif
127
128 tx_desc = bfin_mac_alloc(&dma_handle,
118133e6 129 sizeof(struct net_dma_desc_tx),
e190d6b1
BW		 130 CONFIG_BFIN_TX_DESC_NUM);
131 if (tx_desc == NULL)
132 goto init_error;
133
134 rx_desc = bfin_mac_alloc(&dma_handle,
118133e6 135 sizeof(struct net_dma_desc_rx),
e190d6b1
BW		 136 CONFIG_BFIN_RX_DESC_NUM);
137 if (rx_desc == NULL)
138 goto init_error;
139
140 /* init tx_list */
141 tx_list_head = tx_list_tail = tx_desc;
142
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
147
148 /*
149 * disable DMA
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
153 * large desc flow
154 */
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
157 a->x_count = 0;
158 a->next_dma_desc = b;
159
160 /*
161 * enabled DMA
162 * write to memory WNR = 1
163 * wordsize is 32 bits
164 * disable interrupt
165 * 6 half words is desc size
166 * large desc flow
167 */
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
170 b->x_count = 0;
171
172 t->skb = NULL;
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
175 tx_list_tail = t;
176 }
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
180
181 /* init rx_list */
182 rx_list_head = rx_list_tail = rx_desc;
183
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
188
189 /* allocate a new skb for next time receive */
1ab0d2ec 190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1 191 if (!new_skb) {
c6dd5098 192 pr_notice("init: low on mem - packet dropped\n");
e190d6b1
BW		 193 goto init_error;
194 }
015dac88 195 skb_reserve(new_skb, NET_IP_ALIGN);
f6e1e4f3
SZ		 196 /* Invidate the data cache of skb->data range when it is write back
197 * cache. It will prevent overwritting the new data from DMA
198 */
199 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
200 (unsigned long)new_skb->end);
e190d6b1
BW		 201 r->skb = new_skb;
202
203 /*
204 * enabled DMA
205 * write to memory WNR = 1
206 * wordsize is 32 bits
207 * disable interrupt
208 * 6 half words is desc size
209 * large desc flow
210 */
211 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
212 /* since RXDWA is enabled */
213 a->start_addr = (unsigned long)new_skb->data - 2;
214 a->x_count = 0;
215 a->next_dma_desc = b;
216
217 /*
218 * enabled DMA
219 * write to memory WNR = 1
220 * wordsize is 32 bits
221 * enable interrupt
222 * 6 half words is desc size
223 * large desc flow
224 */
225 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
226 NDSIZE_6 | DMAFLOW_LARGE;
227 b->start_addr = (unsigned long)(&(r->status));
228 b->x_count = 0;
229
230 rx_list_tail->desc_b.next_dma_desc = a;
231 rx_list_tail->next = r;
232 rx_list_tail = r;
233 }
234 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
235 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
236 current_rx_ptr = rx_list_head;
237
238 return 0;
239
240init_error:
241 desc_list_free();
c6dd5098 242 pr_err("kmalloc failed\n");
e190d6b1
BW		 243 return -ENOMEM;
244}
245
246
247/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
248
4ae5a3ad
BW		 249/*
250 * MII operations
251 */
e190d6b1 252/* Wait until the previous MDC/MDIO transaction has completed */
2bfa0f0c 253static int bfin_mdio_poll(void)
e190d6b1
BW		 254{
255 int timeout_cnt = MAX_TIMEOUT_CNT;
256
257 /* poll the STABUSY bit */
258 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
6db9e461 259 udelay(1);
e190d6b1 260 if (timeout_cnt-- < 0) {
c6dd5098 261 pr_err("wait MDC/MDIO transaction to complete timeout\n");
2bfa0f0c 262 return -ETIMEDOUT;
e190d6b1
BW		 263 }
264 }
2bfa0f0c
MF		 265
266 return 0;
e190d6b1
BW		 267}
268
269/* Read an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e 270static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
e190d6b1 271{
2bfa0f0c
MF		 272 int ret;
273
274 ret = bfin_mdio_poll();
275 if (ret)
276 return ret;
4ae5a3ad 277
e190d6b1 278 /* read mode */
4ae5a3ad
BW		 279 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
280 SET_REGAD((u16) regnum) |
e190d6b1 281 STABUSY);
e190d6b1 282
2bfa0f0c
MF		 283 ret = bfin_mdio_poll();
284 if (ret)
285 return ret;
4ae5a3ad
BW		 286
287 return (int) bfin_read_EMAC_STADAT();
e190d6b1
BW		 288}
289
290/* Write an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e
AB		 291static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
292 u16 value)
e190d6b1 293{
2bfa0f0c
MF		 294 int ret;
295
296 ret = bfin_mdio_poll();
297 if (ret)
298 return ret;
4ae5a3ad
BW		 299
300 bfin_write_EMAC_STADAT((u32) value);
e190d6b1
BW		 301
302 /* write mode */
4ae5a3ad
BW		 303 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
304 SET_REGAD((u16) regnum) |
e190d6b1
BW		 305 STAOP |
306 STABUSY);
307
2bfa0f0c 308 return bfin_mdio_poll();
e190d6b1
BW		 309}
310
0ed0563e 311static int bfin_mdiobus_reset(struct mii_bus *bus)
e190d6b1 312{
4ae5a3ad 313 return 0;
e190d6b1
BW		 314}
315
7ef0a7ee 316static void bfin_mac_adjust_link(struct net_device *dev)
e190d6b1 317{
7ef0a7ee 318 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 319 struct phy_device *phydev = lp->phydev;
320 unsigned long flags;
321 int new_state = 0;
322
323 spin_lock_irqsave(&lp->lock, flags);
324 if (phydev->link) {
325 /* Now we make sure that we can be in full duplex mode.
326 * If not, we operate in half-duplex mode. */
327 if (phydev->duplex != lp->old_duplex) {
328 u32 opmode = bfin_read_EMAC_OPMODE();
329 new_state = 1;
330
331 if (phydev->duplex)
332 opmode |= FDMODE;
333 else
334 opmode &= ~(FDMODE);
335
336 bfin_write_EMAC_OPMODE(opmode);
337 lp->old_duplex = phydev->duplex;
338 }
e190d6b1 339
4ae5a3ad 340 if (phydev->speed != lp->old_speed) {
02460d08
SZ		 341 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
342 u32 opmode = bfin_read_EMAC_OPMODE();
343 switch (phydev->speed) {
344 case 10:
345 opmode |= RMII_10;
346 break;
347 case 100:
348 opmode &= ~RMII_10;
349 break;
350 default:
c6dd5098
MF		 351 netdev_warn(dev,
352 "Ack! Speed (%d) is not 10/100!\n",
353 phydev->speed);
02460d08
SZ		 354 break;
355 }
356 bfin_write_EMAC_OPMODE(opmode);
4ae5a3ad 357 }
e190d6b1 358
4ae5a3ad
BW		 359 new_state = 1;
360 lp->old_speed = phydev->speed;
361 }
e190d6b1 362
4ae5a3ad
BW		 363 if (!lp->old_link) {
364 new_state = 1;
365 lp->old_link = 1;
4ae5a3ad
BW		 366 }
367 } else if (lp->old_link) {
368 new_state = 1;
369 lp->old_link = 0;
370 lp->old_speed = 0;
371 lp->old_duplex = -1;
e190d6b1
BW		 372 }
373
4ae5a3ad
BW		 374 if (new_state) {
375 u32 opmode = bfin_read_EMAC_OPMODE();
376 phy_print_status(phydev);
377 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
e190d6b1 378 }
4ae5a3ad
BW		 379
380 spin_unlock_irqrestore(&lp->lock, flags);
e190d6b1
BW		 381}
382
7cc8f381
BW		 383/* MDC = 2.5 MHz */
384#define MDC_CLK 2500000
385
02460d08 386static int mii_probe(struct net_device *dev, int phy_mode)
e190d6b1 387{
7ef0a7ee 388 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 389 struct phy_device *phydev = NULL;
390 unsigned short sysctl;
391 int i;
7cc8f381 392 u32 sclk, mdc_div;
e190d6b1 393
4ae5a3ad 394 /* Enable PHY output early */
98f672ca
MF		 395 if (!(bfin_read_VR_CTL() & CLKBUFOE))
396 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
e190d6b1 397
7cc8f381
BW		 398 sclk = get_sclk();
399 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
400
4ae5a3ad 401 sysctl = bfin_read_EMAC_SYSCTL();
9dc7f30e 402 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
e190d6b1 403 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1 404
02460d08
SZ		 405 /* search for connected PHY device */
406 for (i = 0; i < PHY_MAX_ADDR; ++i) {
298cf9be 407 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
e190d6b1 408
4ae5a3ad
BW		 409 if (!tmp_phydev)
410 continue; /* no PHY here... */
e190d6b1 411
4ae5a3ad
BW		 412 phydev = tmp_phydev;
413 break; /* found it */
414 }
415
416 /* now we are supposed to have a proper phydev, to attach to... */
417 if (!phydev) {
c6dd5098 418 netdev_err(dev, "no phy device found\n");
4ae5a3ad 419 return -ENODEV;
e190d6b1
BW		 420 }
421
02460d08
SZ		 422 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
423 phy_mode != PHY_INTERFACE_MODE_MII) {
c6dd5098 424 netdev_err(dev, "invalid phy interface mode\n");
02460d08
SZ		 425 return -EINVAL;
426 }
427
c2313557 428 phydev = phy_connect(dev, dev_name(&phydev->dev), &bfin_mac_adjust_link,
02460d08 429 0, phy_mode);
e190d6b1 430
4ae5a3ad 431 if (IS_ERR(phydev)) {
c6dd5098 432 netdev_err(dev, "could not attach PHY\n");
4ae5a3ad
BW		 433 return PTR_ERR(phydev);
434 }
435
436 /* mask with MAC supported features */
437 phydev->supported &= (SUPPORTED_10baseT_Half
438 | SUPPORTED_10baseT_Full
439 | SUPPORTED_100baseT_Half
440 | SUPPORTED_100baseT_Full
441 | SUPPORTED_Autoneg
442 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
443 | SUPPORTED_MII
444 | SUPPORTED_TP);
445
446 phydev->advertising = phydev->supported;
447
448 lp->old_link = 0;
449 lp->old_speed = 0;
450 lp->old_duplex = -1;
451 lp->phydev = phydev;
452
c6dd5098
MF		 453 pr_info("attached PHY driver [%s] "
454 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
455 phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
456 MDC_CLK, mdc_div, sclk/1000000);
4ae5a3ad
BW		 457
458 return 0;
459}
460
679dce39
BW		 461/*
462 * Ethtool support
463 */
464
53fd3f28
MH		 465/*
466 * interrupt routine for magic packet wakeup
467 */
468static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
469{
470 return IRQ_HANDLED;
471}
472
679dce39
BW		 473static int
474bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
475{
476 struct bfin_mac_local *lp = netdev_priv(dev);
477
478 if (lp->phydev)
479 return phy_ethtool_gset(lp->phydev, cmd);
480
481 return -EINVAL;
482}
483
484static int
485bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
486{
487 struct bfin_mac_local *lp = netdev_priv(dev);
488
489 if (!capable(CAP_NET_ADMIN))
490 return -EPERM;
491
492 if (lp->phydev)
493 return phy_ethtool_sset(lp->phydev, cmd);
494
495 return -EINVAL;
496}
497
498static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
499 struct ethtool_drvinfo *info)
500{
c6dd5098 501 strcpy(info->driver, KBUILD_MODNAME);
679dce39
BW		 502 strcpy(info->version, DRV_VERSION);
503 strcpy(info->fw_version, "N/A");
c2313557 504 strcpy(info->bus_info, dev_name(&dev->dev));
679dce39
BW		 505}
506
53fd3f28
MH		 507static void bfin_mac_ethtool_getwol(struct net_device *dev,
508 struct ethtool_wolinfo *wolinfo)
509{
510 struct bfin_mac_local *lp = netdev_priv(dev);
511
512 wolinfo->supported = WAKE_MAGIC;
513 wolinfo->wolopts = lp->wol;
514}
515
516static int bfin_mac_ethtool_setwol(struct net_device *dev,
517 struct ethtool_wolinfo *wolinfo)
518{
519 struct bfin_mac_local *lp = netdev_priv(dev);
520 int rc;
521
522 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
523 WAKE_UCAST |
524 WAKE_MCAST |
525 WAKE_BCAST |
526 WAKE_ARP))
527 return -EOPNOTSUPP;
528
529 lp->wol = wolinfo->wolopts;
530
531 if (lp->wol && !lp->irq_wake_requested) {
532 /* register wake irq handler */
533 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
534 IRQF_DISABLED, "EMAC_WAKE", dev);
535 if (rc)
536 return rc;
537 lp->irq_wake_requested = true;
538 }
539
540 if (!lp->wol && lp->irq_wake_requested) {
541 free_irq(IRQ_MAC_WAKEDET, dev);
542 lp->irq_wake_requested = false;
543 }
544
545 /* Make sure the PHY driver doesn't suspend */
546 device_init_wakeup(&dev->dev, lp->wol);
547
548 return 0;
549}
550
85c153d2 551#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
a85bbddd 552static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
3ffa4290 553 struct ethtool_ts_info *info)
a85bbddd 554{
dd87b22f
RC		 555 struct bfin_mac_local *lp = netdev_priv(dev);
556
a85bbddd
RC		 557 info->so_timestamping =
558 SOF_TIMESTAMPING_TX_HARDWARE |
559 SOF_TIMESTAMPING_RX_HARDWARE |
bc3c5f63 560 SOF_TIMESTAMPING_RAW_HARDWARE;
dd87b22f 561 info->phc_index = lp->phc_index;
a85bbddd
RC		 562 info->tx_types =
563 (1 << HWTSTAMP_TX_OFF) |
564 (1 << HWTSTAMP_TX_ON);
565 info->rx_filters =
566 (1 << HWTSTAMP_FILTER_NONE) |
567 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
568 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
569 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
570 return 0;
571}
85c153d2 572#endif
a85bbddd 573
0fc0b732 574static const struct ethtool_ops bfin_mac_ethtool_ops = {
679dce39
BW		 575 .get_settings = bfin_mac_ethtool_getsettings,
576 .set_settings = bfin_mac_ethtool_setsettings,
577 .get_link = ethtool_op_get_link,
578 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
53fd3f28
MH		 579 .get_wol = bfin_mac_ethtool_getwol,
580 .set_wol = bfin_mac_ethtool_setwol,
85c153d2 581#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
a85bbddd 582 .get_ts_info = bfin_mac_ethtool_get_ts_info,
85c153d2 583#endif
679dce39
BW		 584};
585
4ae5a3ad 586/**************************************************************************/
5ca1bb5a 587static void setup_system_regs(struct net_device *dev)
4ae5a3ad 588{
02460d08
SZ		 589 struct bfin_mac_local *lp = netdev_priv(dev);
590 int i;
4ae5a3ad
BW		 591 unsigned short sysctl;
592
593 /*
594 * Odd word alignment for Receive Frame DMA word
595 * Configure checksum support and rcve frame word alignment
596 */
597 sysctl = bfin_read_EMAC_SYSCTL();
02460d08
SZ		 598 /*
599 * check if interrupt is requested for any PHY,
600 * enable PHY interrupt only if needed
601 */
602 for (i = 0; i < PHY_MAX_ADDR; ++i)
603 if (lp->mii_bus->irq[i] != PHY_POLL)
604 break;
605 if (i < PHY_MAX_ADDR)
606 sysctl |= PHYIE;
812a9de7 607 sysctl |= RXDWA;
4ae5a3ad 608#if defined(BFIN_MAC_CSUM_OFFLOAD)
812a9de7 609 sysctl |= RXCKS;
4ae5a3ad 610#else
812a9de7 611 sysctl &= ~RXCKS;
4ae5a3ad
BW		 612#endif
613 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1
BW		 614
615 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
616
c599bd6b
MF		 617 /* Set vlan regs to let 1522 bytes long packets pass through */
618 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
619 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
620
e190d6b1
BW		 621 /* Initialize the TX DMA channel registers */
622 bfin_write_DMA2_X_COUNT(0);
623 bfin_write_DMA2_X_MODIFY(4);
624 bfin_write_DMA2_Y_COUNT(0);
625 bfin_write_DMA2_Y_MODIFY(0);
626
627 /* Initialize the RX DMA channel registers */
628 bfin_write_DMA1_X_COUNT(0);
629 bfin_write_DMA1_X_MODIFY(4);
630 bfin_write_DMA1_Y_COUNT(0);
631 bfin_write_DMA1_Y_MODIFY(0);
632}
633
73f83182 634static void setup_mac_addr(u8 *mac_addr)
e190d6b1
BW		 635{
636 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
637 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
638
639 /* this depends on a little-endian machine */
640 bfin_write_EMAC_ADDRLO(addr_low);
641 bfin_write_EMAC_ADDRHI(addr_hi);
642}
643
7ef0a7ee 644static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
73f83182
AL		 645{
646 struct sockaddr *addr = p;
647 if (netif_running(dev))
648 return -EBUSY;
649 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5055d2f2 650 dev->addr_assign_type &= ~NET_ADDR_RANDOM;
73f83182
AL		 651 setup_mac_addr(dev->dev_addr);
652 return 0;
653}
654
fe92afed
BS		 655#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
656#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
657
bc3c5f63
RC		 658static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
659{
660 u32 ipn = 1000000000UL / input_clk;
661 u32 ppn = 1;
662 unsigned int shift = 0;
663
664 while (ppn <= ipn) {
665 ppn <<= 1;
666 shift++;
667 }
668 *shift_result = shift;
669 return 1000000000UL / ppn;
670}
671
fe92afed
BS		 672static int bfin_mac_hwtstamp_ioctl(struct net_device *netdev,
673 struct ifreq *ifr, int cmd)
674{
675 struct hwtstamp_config config;
676 struct bfin_mac_local *lp = netdev_priv(netdev);
677 u16 ptpctl;
678 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
679
680 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
681 return -EFAULT;
682
683 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
684 __func__, config.flags, config.tx_type, config.rx_filter);
685
686 /* reserved for future extensions */
687 if (config.flags)
688 return -EINVAL;
689
690 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
691 (config.tx_type != HWTSTAMP_TX_ON))
692 return -ERANGE;
693
694 ptpctl = bfin_read_EMAC_PTP_CTL();
695
696 switch (config.rx_filter) {
697 case HWTSTAMP_FILTER_NONE:
698 /*
699 * Dont allow any timestamping
700 */
701 ptpfv3 = 0xFFFFFFFF;
702 bfin_write_EMAC_PTP_FV3(ptpfv3);
703 break;
704 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
705 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
706 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
707 /*
708 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
709 * to enable all the field matches.
710 */
711 ptpctl &= ~0x1F00;
712 bfin_write_EMAC_PTP_CTL(ptpctl);
713 /*
714 * Keep the default values of the EMAC_PTP_FOFF register.
715 */
716 ptpfoff = 0x4A24170C;
717 bfin_write_EMAC_PTP_FOFF(ptpfoff);
718 /*
719 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
720 * registers.
721 */
722 ptpfv1 = 0x11040800;
723 bfin_write_EMAC_PTP_FV1(ptpfv1);
724 ptpfv2 = 0x0140013F;
725 bfin_write_EMAC_PTP_FV2(ptpfv2);
726 /*
727 * The default value (0xFFFC) allows the timestamping of both
728 * received Sync messages and Delay_Req messages.
729 */
730 ptpfv3 = 0xFFFFFFFC;
731 bfin_write_EMAC_PTP_FV3(ptpfv3);
732
733 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
734 break;
735 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
736 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
737 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
738 /* Clear all five comparison mask bits (bits[12:8]) in the
739 * EMAC_PTP_CTL register to enable all the field matches.
740 */
741 ptpctl &= ~0x1F00;
742 bfin_write_EMAC_PTP_CTL(ptpctl);
743 /*
744 * Keep the default values of the EMAC_PTP_FOFF register, except set
745 * the PTPCOF field to 0x2A.
746 */
747 ptpfoff = 0x2A24170C;
748 bfin_write_EMAC_PTP_FOFF(ptpfoff);
749 /*
750 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
751 * registers.
752 */
753 ptpfv1 = 0x11040800;
754 bfin_write_EMAC_PTP_FV1(ptpfv1);
755 ptpfv2 = 0x0140013F;
756 bfin_write_EMAC_PTP_FV2(ptpfv2);
757 /*
758 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
759 * the value to 0xFFF0.
760 */
761 ptpfv3 = 0xFFFFFFF0;
762 bfin_write_EMAC_PTP_FV3(ptpfv3);
763
764 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
765 break;
766 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
767 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
768 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
769 /*
770 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
771 * EFTM and PTPCM field comparison.
772 */
773 ptpctl &= ~0x1100;
774 bfin_write_EMAC_PTP_CTL(ptpctl);
775 /*
776 * Keep the default values of all the fields of the EMAC_PTP_FOFF
777 * register, except set the PTPCOF field to 0x0E.
778 */
779 ptpfoff = 0x0E24170C;
780 bfin_write_EMAC_PTP_FOFF(ptpfoff);
781 /*
782 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
783 * corresponds to PTP messages on the MAC layer.
784 */
785 ptpfv1 = 0x110488F7;
786 bfin_write_EMAC_PTP_FV1(ptpfv1);
787 ptpfv2 = 0x0140013F;
788 bfin_write_EMAC_PTP_FV2(ptpfv2);
789 /*
790 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
791 * messages, set the value to 0xFFF0.
792 */
793 ptpfv3 = 0xFFFFFFF0;
794 bfin_write_EMAC_PTP_FV3(ptpfv3);
795
796 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
797 break;
798 default:
799 return -ERANGE;
800 }
801
802 if (config.tx_type == HWTSTAMP_TX_OFF &&
803 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
804 ptpctl &= ~PTP_EN;
805 bfin_write_EMAC_PTP_CTL(ptpctl);
806
807 SSYNC();
808 } else {
809 ptpctl |= PTP_EN;
810 bfin_write_EMAC_PTP_CTL(ptpctl);
811
812 /*
813 * clear any existing timestamp
814 */
815 bfin_read_EMAC_PTP_RXSNAPLO();
816 bfin_read_EMAC_PTP_RXSNAPHI();
817
818 bfin_read_EMAC_PTP_TXSNAPLO();
819 bfin_read_EMAC_PTP_TXSNAPHI();
820
fe92afed 821 SSYNC();
fe92afed
BS		 822 }
823
824 lp->stamp_cfg = config;
825 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
826 -EFAULT : 0;
827}
828
fe92afed
BS		 829static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
830{
831 struct bfin_mac_local *lp = netdev_priv(netdev);
fe92afed 832
2244d07b 833 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
fe92afed
BS		 834 int timeout_cnt = MAX_TIMEOUT_CNT;
835
836 /* When doing time stamping, keep the connection to the socket
837 * a while longer
838 */
2244d07b 839 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
fe92afed
BS		 840
841 /*
842 * The timestamping is done at the EMAC module's MII/RMII interface
843 * when the module sees the Start of Frame of an event message packet. This
844 * interface is the closest possible place to the physical Ethernet transmission
845 * medium, providing the best timing accuracy.
846 */
847 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
848 udelay(1);
849 if (timeout_cnt == 0)
c6dd5098 850 netdev_err(netdev, "timestamp the TX packet failed\n");
fe92afed
BS		 851 else {
852 struct skb_shared_hwtstamps shhwtstamps;
853 u64 ns;
854 u64 regval;
855
856 regval = bfin_read_EMAC_PTP_TXSNAPLO();
857 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
858 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
bc3c5f63 859 ns = regval << lp->shift;
fe92afed 860 shhwtstamps.hwtstamp = ns_to_ktime(ns);
fe92afed 861 skb_tstamp_tx(skb, &shhwtstamps);
fe92afed
BS		 862 }
863 }
864}
865
866static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
867{
868 struct bfin_mac_local *lp = netdev_priv(netdev);
869 u32 valid;
870 u64 regval, ns;
871 struct skb_shared_hwtstamps *shhwtstamps;
872
873 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
874 return;
875
876 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
877 if (!valid)
878 return;
879
880 shhwtstamps = skb_hwtstamps(skb);
881
882 regval = bfin_read_EMAC_PTP_RXSNAPLO();
883 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
bc3c5f63 884 ns = regval << lp->shift;
fe92afed
BS		 885 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
886 shhwtstamps->hwtstamp = ns_to_ktime(ns);
fe92afed
BS		 887}
888
fe92afed
BS		 889static void bfin_mac_hwtstamp_init(struct net_device *netdev)
890{
891 struct bfin_mac_local *lp = netdev_priv(netdev);
dd87b22f 892 u64 addend, ppb;
bc3c5f63 893 u32 input_clk, phc_clk;
fe92afed
BS		 894
895 /* Initialize hardware timer */
bc3c5f63
RC		 896 input_clk = get_sclk();
897 phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
898 addend = phc_clk * (1ULL << 32);
899 do_div(addend, input_clk);
900 bfin_write_EMAC_PTP_ADDEND((u32)addend);
901
902 lp->addend = addend;
dd87b22f
RC		 903 ppb = 1000000000ULL * input_clk;
904 do_div(ppb, phc_clk);
905 lp->max_ppb = ppb - 1000000000ULL - 1ULL;
fe92afed
BS		 906
907 /* Initialize hwstamp config */
908 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
909 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
910}
911
dd87b22f
RC		 912static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
913{
914 u64 ns;
915 u32 lo, hi;
916
917 lo = bfin_read_EMAC_PTP_TIMELO();
918 hi = bfin_read_EMAC_PTP_TIMEHI();
919
920 ns = ((u64) hi) << 32;
921 ns |= lo;
922 ns <<= lp->shift;
923
924 return ns;
925}
926
927static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
928{
929 u32 hi, lo;
930
931 ns >>= lp->shift;
932 hi = ns >> 32;
933 lo = ns & 0xffffffff;
934
935 bfin_write_EMAC_PTP_TIMELO(lo);
936 bfin_write_EMAC_PTP_TIMEHI(hi);
937}
938
939/* PTP Hardware Clock operations */
940
941static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
942{
943 u64 adj;
944 u32 diff, addend;
945 int neg_adj = 0;
946 struct bfin_mac_local *lp =
947 container_of(ptp, struct bfin_mac_local, caps);
948
949 if (ppb < 0) {
950 neg_adj = 1;
951 ppb = -ppb;
952 }
953 addend = lp->addend;
954 adj = addend;
955 adj *= ppb;
956 diff = div_u64(adj, 1000000000ULL);
957
958 addend = neg_adj ? addend - diff : addend + diff;
959
960 bfin_write_EMAC_PTP_ADDEND(addend);
961
962 return 0;
963}
964
965static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
966{
967 s64 now;
968 unsigned long flags;
969 struct bfin_mac_local *lp =
970 container_of(ptp, struct bfin_mac_local, caps);
971
972 spin_lock_irqsave(&lp->phc_lock, flags);
973
974 now = bfin_ptp_time_read(lp);
975 now += delta;
976 bfin_ptp_time_write(lp, now);
977
978 spin_unlock_irqrestore(&lp->phc_lock, flags);
979
980 return 0;
981}
982
983static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
984{
985 u64 ns;
986 u32 remainder;
987 unsigned long flags;
988 struct bfin_mac_local *lp =
989 container_of(ptp, struct bfin_mac_local, caps);
990
991 spin_lock_irqsave(&lp->phc_lock, flags);
992
993 ns = bfin_ptp_time_read(lp);
994
995 spin_unlock_irqrestore(&lp->phc_lock, flags);
996
997 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
998 ts->tv_nsec = remainder;
999 return 0;
1000}
1001
1002static int bfin_ptp_settime(struct ptp_clock_info *ptp,
1003 const struct timespec *ts)
1004{
1005 u64 ns;
1006 unsigned long flags;
1007 struct bfin_mac_local *lp =
1008 container_of(ptp, struct bfin_mac_local, caps);
1009
1010 ns = ts->tv_sec * 1000000000ULL;
1011 ns += ts->tv_nsec;
1012
1013 spin_lock_irqsave(&lp->phc_lock, flags);
1014
1015 bfin_ptp_time_write(lp, ns);
1016
1017 spin_unlock_irqrestore(&lp->phc_lock, flags);
1018
1019 return 0;
1020}
1021
1022static int bfin_ptp_enable(struct ptp_clock_info *ptp,
1023 struct ptp_clock_request *rq, int on)
1024{
1025 return -EOPNOTSUPP;
1026}
1027
1028static struct ptp_clock_info bfin_ptp_caps = {
1029 .owner = THIS_MODULE,
1030 .name = "BF518 clock",
1031 .max_adj = 0,
1032 .n_alarm = 0,
1033 .n_ext_ts = 0,
1034 .n_per_out = 0,
1035 .pps = 0,
1036 .adjfreq = bfin_ptp_adjfreq,
1037 .adjtime = bfin_ptp_adjtime,
1038 .gettime = bfin_ptp_gettime,
1039 .settime = bfin_ptp_settime,
1040 .enable = bfin_ptp_enable,
1041};
1042
1043static int bfin_phc_init(struct net_device *netdev, struct device *dev)
1044{
1045 struct bfin_mac_local *lp = netdev_priv(netdev);
1046
1047 lp->caps = bfin_ptp_caps;
1048 lp->caps.max_adj = lp->max_ppb;
1049 lp->clock = ptp_clock_register(&lp->caps, dev);
1050 if (IS_ERR(lp->clock))
1051 return PTR_ERR(lp->clock);
1052
1053 lp->phc_index = ptp_clock_index(lp->clock);
1054 spin_lock_init(&lp->phc_lock);
1055
1056 return 0;
1057}
1058
1059static void bfin_phc_release(struct bfin_mac_local *lp)
1060{
1061 ptp_clock_unregister(lp->clock);
1062}
1063
fe92afed
BS		 1064#else
1065# define bfin_mac_hwtstamp_is_none(cfg) 0
1066# define bfin_mac_hwtstamp_init(dev)
1067# define bfin_mac_hwtstamp_ioctl(dev, ifr, cmd) (-EOPNOTSUPP)
1068# define bfin_rx_hwtstamp(dev, skb)
1069# define bfin_tx_hwtstamp(dev, skb)
dd87b22f
RC		 1070# define bfin_phc_init(netdev, dev) 0
1071# define bfin_phc_release(lp)
fe92afed
BS		 1072#endif
1073
4fcc3d34
SZ		 1074static inline void _tx_reclaim_skb(void)
1075{
1076 do {
1077 tx_list_head->desc_a.config &= ~DMAEN;
1078 tx_list_head->status.status_word = 0;
1079 if (tx_list_head->skb) {
1080 dev_kfree_skb(tx_list_head->skb);
1081 tx_list_head->skb = NULL;
1082 }
1083 tx_list_head = tx_list_head->next;
1084
1085 } while (tx_list_head->status.status_word != 0);
1086}
1087
1088static void tx_reclaim_skb(struct bfin_mac_local *lp)
e190d6b1
BW		 1089{
1090 int timeout_cnt = MAX_TIMEOUT_CNT;
1091
4fcc3d34
SZ		 1092 if (tx_list_head->status.status_word != 0)
1093 _tx_reclaim_skb();
e190d6b1 1094
4fcc3d34 1095 if (current_tx_ptr->next == tx_list_head) {
e190d6b1 1096 while (tx_list_head->status.status_word == 0) {
4fcc3d34 1097 /* slow down polling to avoid too many queue stop. */
015dac88 1098 udelay(10);
4fcc3d34
SZ		 1099 /* reclaim skb if DMA is not running. */
1100 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
1101 break;
1102 if (timeout_cnt-- < 0)
e190d6b1 1103 break;
e190d6b1 1104 }
4fcc3d34
SZ		 1105
1106 if (timeout_cnt >= 0)
1107 _tx_reclaim_skb();
1108 else
1109 netif_stop_queue(lp->ndev);
e190d6b1
BW		 1110 }
1111
4fcc3d34
SZ		 1112 if (current_tx_ptr->next != tx_list_head &&
1113 netif_queue_stopped(lp->ndev))
1114 netif_wake_queue(lp->ndev);
1115
1116 if (tx_list_head != current_tx_ptr) {
1117 /* shorten the timer interval if tx queue is stopped */
1118 if (netif_queue_stopped(lp->ndev))
1119 lp->tx_reclaim_timer.expires =
1120 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1121 else
1122 lp->tx_reclaim_timer.expires =
1123 jiffies + TX_RECLAIM_JIFFIES;
1124
1125 mod_timer(&lp->tx_reclaim_timer,
1126 lp->tx_reclaim_timer.expires);
1127 }
e190d6b1 1128
e190d6b1 1129 return;
4fcc3d34 1130}
e190d6b1 1131
4fcc3d34
SZ		 1132static void tx_reclaim_skb_timeout(unsigned long lp)
1133{
1134 tx_reclaim_skb((struct bfin_mac_local *)lp);
e190d6b1
BW		 1135}
1136
7ef0a7ee 1137static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
e190d6b1
BW		 1138 struct net_device *dev)
1139{
4fcc3d34 1140 struct bfin_mac_local *lp = netdev_priv(dev);
a50c0c05 1141 u16 *data;
015dac88 1142 u32 data_align = (unsigned long)(skb->data) & 0x3;
fe92afed 1143
e190d6b1
BW		 1144 current_tx_ptr->skb = skb;
1145
015dac88
MH		 1146 if (data_align == 0x2) {
1147 /* move skb->data to current_tx_ptr payload */
1148 data = (u16 *)(skb->data) - 1;
fe92afed
BS		 1149 *data = (u16)(skb->len);
1150 /*
1151 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1152 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1153 * of this field are the length of the packet payload in bytes and the higher
1154 * 4 bits are the timestamping enable field.
1155 */
2244d07b 1156 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed
BS		 1157 *data |= 0x1000;
1158
015dac88
MH		 1159 current_tx_ptr->desc_a.start_addr = (u32)data;
1160 /* this is important! */
1161 blackfin_dcache_flush_range((u32)data,
1162 (u32)((u8 *)data + skb->len + 4));
e190d6b1 1163 } else {
015dac88 1164 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
fe92afed 1165 /* enable timestamping for the sent packet */
2244d07b 1166 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed 1167 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
015dac88
MH		 1168 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1169 skb->len);
1170 current_tx_ptr->desc_a.start_addr =
1171 (u32)current_tx_ptr->packet;
015dac88
MH		 1172 blackfin_dcache_flush_range(
1173 (u32)current_tx_ptr->packet,
1174 (u32)(current_tx_ptr->packet + skb->len + 2));
e190d6b1
BW		 1175 }
1176
805a8ab3
SZ		 1177 /* make sure the internal data buffers in the core are drained
1178 * so that the DMA descriptors are completely written when the
1179 * DMA engine goes to fetch them below
1180 */
1181 SSYNC();
1182
4fcc3d34
SZ		 1183 /* always clear status buffer before start tx dma */
1184 current_tx_ptr->status.status_word = 0;
1185
e190d6b1
BW		 1186 /* enable this packet's dma */
1187 current_tx_ptr->desc_a.config |= DMAEN;
1188
1189 /* tx dma is running, just return */
015dac88 1190 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
e190d6b1
BW		 1191 goto out;
1192
1193 /* tx dma is not running */
1194 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1195 /* dma enabled, read from memory, size is 6 */
1196 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1197 /* Turn on the EMAC tx */
1198 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1199
1200out:
fe92afed
BS		 1201 bfin_tx_hwtstamp(dev, skb);
1202
e190d6b1 1203 current_tx_ptr = current_tx_ptr->next;
09f75cd7
JG		 1204 dev->stats.tx_packets++;
1205 dev->stats.tx_bytes += (skb->len);
4fcc3d34
SZ		 1206
1207 tx_reclaim_skb(lp);
1208
6ed10654 1209 return NETDEV_TX_OK;
e190d6b1
BW		 1210}
1211
ad2864d8 1212#define IP_HEADER_OFF 0
ec497b32
PM		 1213#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1214 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1215
7ef0a7ee 1216static void bfin_mac_rx(struct net_device *dev)
e190d6b1
BW		 1217{
1218 struct sk_buff *skb, *new_skb;
e190d6b1 1219 unsigned short len;
fe92afed 1220 struct bfin_mac_local *lp __maybe_unused = netdev_priv(dev);
ad2864d8
SZ		 1221#if defined(BFIN_MAC_CSUM_OFFLOAD)
1222 unsigned int i;
1223 unsigned char fcs[ETH_FCS_LEN + 1];
1224#endif
e190d6b1 1225
ec497b32
PM		 1226 /* check if frame status word reports an error condition
1227 * we which case we simply drop the packet
1228 */
1229 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
c6dd5098 1230 netdev_notice(dev, "rx: receive error - packet dropped\n");
ec497b32
PM		 1231 dev->stats.rx_dropped++;
1232 goto out;
1233 }
1234
e190d6b1
BW		 1235 /* allocate a new skb for next time receive */
1236 skb = current_rx_ptr->skb;
fe92afed 1237
1ab0d2ec 1238 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1 1239 if (!new_skb) {
c6dd5098 1240 netdev_notice(dev, "rx: low on mem - packet dropped\n");
09f75cd7 1241 dev->stats.rx_dropped++;
e190d6b1
BW		 1242 goto out;
1243 }
1244 /* reserve 2 bytes for RXDWA padding */
015dac88 1245 skb_reserve(new_skb, NET_IP_ALIGN);
6e01d1a4
AD		 1246 /* Invidate the data cache of skb->data range when it is write back
1247 * cache. It will prevent overwritting the new data from DMA
1248 */
1249 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1250 (unsigned long)new_skb->end);
1251
f6e1e4f3
SZ		 1252 current_rx_ptr->skb = new_skb;
1253 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1254
e190d6b1 1255 len = (unsigned short)((current_rx_ptr->status.status_word) & RX_FRLEN);
ad2864d8
SZ		 1256 /* Deduce Ethernet FCS length from Ethernet payload length */
1257 len -= ETH_FCS_LEN;
e190d6b1 1258 skb_put(skb, len);
e190d6b1 1259
e190d6b1 1260 skb->protocol = eth_type_trans(skb, dev);
fe92afed
BS		 1261
1262 bfin_rx_hwtstamp(dev, skb);
1263
e190d6b1 1264#if defined(BFIN_MAC_CSUM_OFFLOAD)
ad2864d8
SZ		 1265 /* Checksum offloading only works for IPv4 packets with the standard IP header
1266 * length of 20 bytes, because the blackfin MAC checksum calculation is
1267 * based on that assumption. We must NOT use the calculated checksum if our
1268 * IP version or header break that assumption.
1269 */
1270 if (skb->data[IP_HEADER_OFF] == 0x45) {
1271 skb->csum = current_rx_ptr->status.ip_payload_csum;
1272 /*
1273 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1274 * IP checksum is based on 16-bit one's complement algorithm.
1275 * To deduce a value from checksum is equal to add its inversion.
1276 * If the IP payload len is odd, the inversed FCS should also
1277 * begin from odd address and leave first byte zero.
1278 */
1279 if (skb->len % 2) {
1280 fcs[0] = 0;
1281 for (i = 0; i < ETH_FCS_LEN; i++)
1282 fcs[i + 1] = ~skb->data[skb->len + i];
1283 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1284 } else {
1285 for (i = 0; i < ETH_FCS_LEN; i++)
1286 fcs[i] = ~skb->data[skb->len + i];
1287 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1288 }
1289 skb->ip_summed = CHECKSUM_COMPLETE;
1290 }
e190d6b1
BW		 1291#endif
1292
1293 netif_rx(skb);
09f75cd7
JG		 1294 dev->stats.rx_packets++;
1295 dev->stats.rx_bytes += len;
ec497b32 1296out:
e190d6b1
BW		 1297 current_rx_ptr->status.status_word = 0x00000000;
1298 current_rx_ptr = current_rx_ptr->next;
e190d6b1
BW		 1299}
1300
1301/* interrupt routine to handle rx and error signal */
7ef0a7ee 1302static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
e190d6b1
BW		 1303{
1304 struct net_device *dev = dev_id;
1305 int number = 0;
1306
1307get_one_packet:
1308 if (current_rx_ptr->status.status_word == 0) {
1309 /* no more new packet received */
1310 if (number == 0) {
1311 if (current_rx_ptr->next->status.status_word != 0) {
1312 current_rx_ptr = current_rx_ptr->next;
1313 goto real_rx;
1314 }
1315 }
1316 bfin_write_DMA1_IRQ_STATUS(bfin_read_DMA1_IRQ_STATUS() |
1317 DMA_DONE | DMA_ERR);
1318 return IRQ_HANDLED;
1319 }
1320
1321real_rx:
7ef0a7ee 1322 bfin_mac_rx(dev);
e190d6b1
BW		 1323 number++;
1324 goto get_one_packet;
1325}
1326
1327#ifdef CONFIG_NET_POLL_CONTROLLER
7ef0a7ee 1328static void bfin_mac_poll(struct net_device *dev)
e190d6b1 1329{
4fcc3d34
SZ		 1330 struct bfin_mac_local *lp = netdev_priv(dev);
1331
e190d6b1 1332 disable_irq(IRQ_MAC_RX);
7ef0a7ee 1333 bfin_mac_interrupt(IRQ_MAC_RX, dev);
4fcc3d34 1334 tx_reclaim_skb(lp);
e190d6b1
BW		 1335 enable_irq(IRQ_MAC_RX);
1336}
1337#endif /* CONFIG_NET_POLL_CONTROLLER */
1338
7ef0a7ee 1339static void bfin_mac_disable(void)
e190d6b1
BW		 1340{
1341 unsigned int opmode;
1342
1343 opmode = bfin_read_EMAC_OPMODE();
1344 opmode &= (~RE);
1345 opmode &= (~TE);
1346 /* Turn off the EMAC */
1347 bfin_write_EMAC_OPMODE(opmode);
1348}
1349
1350/*
1351 * Enable Interrupts, Receive, and Transmit
1352 */
02460d08 1353static int bfin_mac_enable(struct phy_device *phydev)
e190d6b1 1354{
2bfa0f0c 1355 int ret;
e190d6b1
BW		 1356 u32 opmode;
1357
c6dd5098 1358 pr_debug("%s\n", __func__);
e190d6b1
BW		 1359
1360 /* Set RX DMA */
1361 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1362 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1363
1364 /* Wait MII done */
2bfa0f0c
MF		 1365 ret = bfin_mdio_poll();
1366 if (ret)
1367 return ret;
e190d6b1
BW		 1368
1369 /* We enable only RX here */
1370 /* ASTP : Enable Automatic Pad Stripping
1371 PR : Promiscuous Mode for test
1372 PSF : Receive frames with total length less than 64 bytes.
1373 FDMODE : Full Duplex Mode
1374 LB : Internal Loopback for test
1375 RE : Receiver Enable */
1376 opmode = bfin_read_EMAC_OPMODE();
1377 if (opmode & FDMODE)
1378 opmode |= PSF;
1379 else
1380 opmode |= DRO | DC | PSF;
1381 opmode |= RE;
1382
02460d08
SZ		 1383 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1384 opmode |= RMII; /* For Now only 100MBit are supported */
72f49050
MF		 1385#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1386 if (__SILICON_REVISION__ < 3) {
1387 /*
1388 * This isn't publicly documented (fun times!), but in
1389 * silicon <=0.2, the RX and TX pins are clocked together.
1390 * So in order to recv, we must enable the transmit side
1391 * as well. This will cause a spurious TX interrupt too,
1392 * but we can easily consume that.
1393 */
1394 opmode |= TE;
1395 }
e190d6b1 1396#endif
02460d08
SZ		 1397 }
1398
e190d6b1
BW		 1399 /* Turn on the EMAC rx */
1400 bfin_write_EMAC_OPMODE(opmode);
2bfa0f0c
MF		 1401
1402 return 0;
e190d6b1
BW		 1403}
1404
1405/* Our watchdog timed out. Called by the networking layer */
7ef0a7ee 1406static void bfin_mac_timeout(struct net_device *dev)
e190d6b1 1407{
4fcc3d34
SZ		 1408 struct bfin_mac_local *lp = netdev_priv(dev);
1409
b39d66a8 1410 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1 1411
7ef0a7ee 1412 bfin_mac_disable();
e190d6b1 1413
4fcc3d34
SZ		 1414 del_timer(&lp->tx_reclaim_timer);
1415
1416 /* reset tx queue and free skb */
1417 while (tx_list_head != current_tx_ptr) {
1418 tx_list_head->desc_a.config &= ~DMAEN;
1419 tx_list_head->status.status_word = 0;
1420 if (tx_list_head->skb) {
1421 dev_kfree_skb(tx_list_head->skb);
1422 tx_list_head->skb = NULL;
1423 }
1424 tx_list_head = tx_list_head->next;
1425 }
1426
1427 if (netif_queue_stopped(lp->ndev))
1428 netif_wake_queue(lp->ndev);
e190d6b1 1429
02460d08 1430 bfin_mac_enable(lp->phydev);
e190d6b1
BW		 1431
1432 /* We can accept TX packets again */
1ae5dc34 1433 dev->trans_start = jiffies; /* prevent tx timeout */
e190d6b1
BW		 1434 netif_wake_queue(dev);
1435}
1436
7ef0a7ee 1437static void bfin_mac_multicast_hash(struct net_device *dev)
775919bc
AW		 1438{
1439 u32 emac_hashhi, emac_hashlo;
22bedad3 1440 struct netdev_hw_addr *ha;
775919bc
AW		 1441 u32 crc;
1442
1443 emac_hashhi = emac_hashlo = 0;
1444
22bedad3 1445 netdev_for_each_mc_addr(ha, dev) {
f767b6df 1446 crc = ether_crc(ETH_ALEN, ha->addr);
775919bc
AW		 1447 crc >>= 26;
1448
1449 if (crc & 0x20)
1450 emac_hashhi |= 1 << (crc & 0x1f);
1451 else
1452 emac_hashlo |= 1 << (crc & 0x1f);
1453 }
1454
1455 bfin_write_EMAC_HASHHI(emac_hashhi);
1456 bfin_write_EMAC_HASHLO(emac_hashlo);
775919bc
AW		 1457}
1458
e190d6b1
BW		 1459/*
1460 * This routine will, depending on the values passed to it,
1461 * either make it accept multicast packets, go into
1462 * promiscuous mode (for TCPDUMP and cousins) or accept
1463 * a select set of multicast packets
1464 */
7ef0a7ee 1465static void bfin_mac_set_multicast_list(struct net_device *dev)
e190d6b1
BW		 1466{
1467 u32 sysctl;
1468
1469 if (dev->flags & IFF_PROMISC) {
c6dd5098 1470 netdev_info(dev, "set promisc mode\n");
e190d6b1 1471 sysctl = bfin_read_EMAC_OPMODE();
c0da776b 1472 sysctl |= PR;
e190d6b1 1473 bfin_write_EMAC_OPMODE(sysctl);
775919bc 1474 } else if (dev->flags & IFF_ALLMULTI) {
e190d6b1
BW		 1475 /* accept all multicast */
1476 sysctl = bfin_read_EMAC_OPMODE();
1477 sysctl |= PAM;
1478 bfin_write_EMAC_OPMODE(sysctl);
4cd24eaf 1479 } else if (!netdev_mc_empty(dev)) {
775919bc
AW		 1480 /* set up multicast hash table */
1481 sysctl = bfin_read_EMAC_OPMODE();
1482 sysctl |= HM;
1483 bfin_write_EMAC_OPMODE(sysctl);
7ef0a7ee 1484 bfin_mac_multicast_hash(dev);
e190d6b1
BW		 1485 } else {
1486 /* clear promisc or multicast mode */
1487 sysctl = bfin_read_EMAC_OPMODE();
1488 sysctl &= ~(RAF | PAM);
1489 bfin_write_EMAC_OPMODE(sysctl);
1490 }
1491}
1492
fe92afed
BS		 1493static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1494{
02460d08
SZ		 1495 struct bfin_mac_local *lp = netdev_priv(netdev);
1496
1497 if (!netif_running(netdev))
1498 return -EINVAL;
1499
fe92afed
BS		 1500 switch (cmd) {
1501 case SIOCSHWTSTAMP:
1502 return bfin_mac_hwtstamp_ioctl(netdev, ifr, cmd);
1503 default:
02460d08
SZ		 1504 if (lp->phydev)
1505 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1506 else
1507 return -EOPNOTSUPP;
fe92afed
BS		 1508 }
1509}
1510
e190d6b1
BW		 1511/*
1512 * this puts the device in an inactive state
1513 */
7ef0a7ee 1514static void bfin_mac_shutdown(struct net_device *dev)
e190d6b1
BW		 1515{
1516 /* Turn off the EMAC */
1517 bfin_write_EMAC_OPMODE(0x00000000);
1518 /* Turn off the EMAC RX DMA */
1519 bfin_write_DMA1_CONFIG(0x0000);
1520 bfin_write_DMA2_CONFIG(0x0000);
1521}
1522
1523/*
1524 * Open and Initialize the interface
1525 *
1526 * Set up everything, reset the card, etc..
1527 */
7ef0a7ee 1528static int bfin_mac_open(struct net_device *dev)
e190d6b1 1529{
7ef0a7ee 1530 struct bfin_mac_local *lp = netdev_priv(dev);
2bfa0f0c 1531 int ret;
b39d66a8 1532 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1533
1534 /*
1535 * Check that the address is valid. If its not, refuse
1536 * to bring the device up. The user must specify an
1537 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1538 */
1539 if (!is_valid_ether_addr(dev->dev_addr)) {
c6dd5098 1540 netdev_warn(dev, "no valid ethernet hw addr\n");
e190d6b1
BW		 1541 return -EINVAL;
1542 }
1543
1544 /* initial rx and tx list */
1ab0d2ec 1545 ret = desc_list_init(dev);
2bfa0f0c
MF		 1546 if (ret)
1547 return ret;
e190d6b1 1548
4ae5a3ad 1549 phy_start(lp->phydev);
136492b2 1550 phy_write(lp->phydev, MII_BMCR, BMCR_RESET);
e190d6b1 1551 setup_system_regs(dev);
ee02fee8 1552 setup_mac_addr(dev->dev_addr);
2bfa0f0c 1553
7ef0a7ee 1554 bfin_mac_disable();
02460d08 1555 ret = bfin_mac_enable(lp->phydev);
2bfa0f0c
MF		 1556 if (ret)
1557 return ret;
e190d6b1 1558 pr_debug("hardware init finished\n");
2bfa0f0c 1559
e190d6b1
BW		 1560 netif_start_queue(dev);
1561 netif_carrier_on(dev);
1562
1563 return 0;
1564}
1565
1566/*
e190d6b1
BW		 1567 * this makes the board clean up everything that it can
1568 * and not talk to the outside world. Caused by
1569 * an 'ifconfig ethX down'
1570 */
7ef0a7ee 1571static int bfin_mac_close(struct net_device *dev)
e190d6b1 1572{
7ef0a7ee 1573 struct bfin_mac_local *lp = netdev_priv(dev);
b39d66a8 1574 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1575
1576 netif_stop_queue(dev);
1577 netif_carrier_off(dev);
1578
4ae5a3ad 1579 phy_stop(lp->phydev);
136492b2 1580 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
4ae5a3ad 1581
e190d6b1 1582 /* clear everything */
7ef0a7ee 1583 bfin_mac_shutdown(dev);
e190d6b1
BW		 1584
1585 /* free the rx/tx buffers */
1586 desc_list_free();
1587
1588 return 0;
1589}
1590
b63dc8fe
MF		 1591static const struct net_device_ops bfin_mac_netdev_ops = {
1592 .ndo_open = bfin_mac_open,
1593 .ndo_stop = bfin_mac_close,
1594 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1595 .ndo_set_mac_address = bfin_mac_set_mac_address,
1596 .ndo_tx_timeout = bfin_mac_timeout,
afc4b13d 1597 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
fe92afed 1598 .ndo_do_ioctl = bfin_mac_ioctl,
b63dc8fe
MF		 1599 .ndo_validate_addr = eth_validate_addr,
1600 .ndo_change_mtu = eth_change_mtu,
1601#ifdef CONFIG_NET_POLL_CONTROLLER
1602 .ndo_poll_controller = bfin_mac_poll,
1603#endif
1604};
1605
d7b843d3 1606static int __devinit bfin_mac_probe(struct platform_device *pdev)
e190d6b1 1607{
7ef0a7ee
BW		 1608 struct net_device *ndev;
1609 struct bfin_mac_local *lp;
080c8255 1610 struct platform_device *pd;
02460d08 1611 struct bfin_mii_bus_platform_data *mii_bus_data;
080c8255 1612 int rc;
7ef0a7ee
BW		 1613
1614 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
41de8d4c 1615 if (!ndev)
7ef0a7ee 1616 return -ENOMEM;
7ef0a7ee
BW		 1617
1618 SET_NETDEV_DEV(ndev, &pdev->dev);
1619 platform_set_drvdata(pdev, ndev);
1620 lp = netdev_priv(ndev);
4fcc3d34 1621 lp->ndev = ndev;
e190d6b1
BW		 1622
1623 /* Grab the MAC address in the MAC */
7ef0a7ee
BW		 1624 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1625 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
e190d6b1
BW		 1626
1627 /* probe mac */
1628 /*todo: how to proble? which is revision_register */
1629 bfin_write_EMAC_ADDRLO(0x12345678);
1630 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
7ef0a7ee
BW		 1631 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1632 rc = -ENODEV;
1633 goto out_err_probe_mac;
e190d6b1
BW		 1634 }
1635
e190d6b1 1636
7ef0a7ee
BW		 1637 /*
1638 * Is it valid? (Did bootloader initialize it?)
1639 * Grab the MAC from the board somehow
1640 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1641 */
5055d2f2
DK		 1642 if (!is_valid_ether_addr(ndev->dev_addr)) {
1643 if (bfin_get_ether_addr(ndev->dev_addr) ||
1644 !is_valid_ether_addr(ndev->dev_addr)) {
1645 /* Still not valid, get a random one */
1646 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1647 eth_hw_addr_random(ndev);
1648 }
1649 }
e190d6b1 1650
7ef0a7ee 1651 setup_mac_addr(ndev->dev_addr);
e190d6b1 1652
080c8255
GY		 1653 if (!pdev->dev.platform_data) {
1654 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1655 rc = -ENODEV;
1656 goto out_err_probe_mac;
7ef0a7ee 1657 }
080c8255
GY		 1658 pd = pdev->dev.platform_data;
1659 lp->mii_bus = platform_get_drvdata(pd);
0e995cd3
SZ		 1660 if (!lp->mii_bus) {
1661 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1662 rc = -ENODEV;
02460d08 1663 goto out_err_probe_mac;
0e995cd3 1664 }
080c8255 1665 lp->mii_bus->priv = ndev;
02460d08 1666 mii_bus_data = pd->dev.platform_data;
4ae5a3ad 1667
02460d08 1668 rc = mii_probe(ndev, mii_bus_data->phy_mode);
7ef0a7ee
BW		 1669 if (rc) {
1670 dev_err(&pdev->dev, "MII Probe failed!\n");
1671 goto out_err_mii_probe;
1672 }
4ae5a3ad 1673
c599bd6b
MF		 1674 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1675 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1676
e190d6b1 1677 /* Fill in the fields of the device structure with ethernet values. */
7ef0a7ee
BW		 1678 ether_setup(ndev);
1679
149da651 1680 ndev->netdev_ops = &bfin_mac_netdev_ops;
679dce39 1681 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
e190d6b1 1682
4fcc3d34
SZ		 1683 init_timer(&lp->tx_reclaim_timer);
1684 lp->tx_reclaim_timer.data = (unsigned long)lp;
1685 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1686
e190d6b1
BW		 1687 spin_lock_init(&lp->lock);
1688
1689 /* now, enable interrupts */
1690 /* register irq handler */
7ef0a7ee 1691 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
91a455f0 1692 IRQF_DISABLED, "EMAC_RX", ndev);
7ef0a7ee
BW		 1693 if (rc) {
1694 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1695 rc = -EBUSY;
1696 goto out_err_request_irq;
e190d6b1
BW		 1697 }
1698
7ef0a7ee
BW		 1699 rc = register_netdev(ndev);
1700 if (rc) {
1701 dev_err(&pdev->dev, "Cannot register net device!\n");
1702 goto out_err_reg_ndev;
e190d6b1
BW		 1703 }
1704
fe92afed 1705 bfin_mac_hwtstamp_init(ndev);
dd87b22f
RC		 1706 if (bfin_phc_init(ndev, &pdev->dev)) {
1707 dev_err(&pdev->dev, "Cannot register PHC device!\n");
1708 goto out_err_phc;
1709 }
fe92afed 1710
7ef0a7ee 1711 /* now, print out the card info, in a short format.. */
c6dd5098 1712 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
e190d6b1 1713
7ef0a7ee 1714 return 0;
e190d6b1 1715
dd87b22f 1716out_err_phc:
7ef0a7ee
BW		 1717out_err_reg_ndev:
1718 free_irq(IRQ_MAC_RX, ndev);
1719out_err_request_irq:
1720out_err_mii_probe:
298cf9be 1721 mdiobus_unregister(lp->mii_bus);
298cf9be 1722 mdiobus_free(lp->mii_bus);
7ef0a7ee
BW		 1723out_err_probe_mac:
1724 platform_set_drvdata(pdev, NULL);
1725 free_netdev(ndev);
e190d6b1 1726
7ef0a7ee 1727 return rc;
e190d6b1
BW		 1728}
1729
d7b843d3 1730static int __devexit bfin_mac_remove(struct platform_device *pdev)
e190d6b1
BW		 1731{
1732 struct net_device *ndev = platform_get_drvdata(pdev);
7ef0a7ee 1733 struct bfin_mac_local *lp = netdev_priv(ndev);
e190d6b1 1734
dd87b22f
RC		 1735 bfin_phc_release(lp);
1736
e190d6b1
BW		 1737 platform_set_drvdata(pdev, NULL);
1738
080c8255 1739 lp->mii_bus->priv = NULL;
7ef0a7ee 1740
e190d6b1
BW		 1741 unregister_netdev(ndev);
1742
1743 free_irq(IRQ_MAC_RX, ndev);
1744
1745 free_netdev(ndev);
1746
e190d6b1
BW		 1747 return 0;
1748}
1749
496a34c2
BW		 1750#ifdef CONFIG_PM
1751static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
e190d6b1 1752{
496a34c2 1753 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1754 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1755
53fd3f28
MH		 1756 if (lp->wol) {
1757 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1758 bfin_write_EMAC_WKUP_CTL(MPKE);
1759 enable_irq_wake(IRQ_MAC_WAKEDET);
1760 } else {
1761 if (netif_running(net_dev))
1762 bfin_mac_close(net_dev);
1763 }
496a34c2 1764
e190d6b1
BW		 1765 return 0;
1766}
1767
1768static int bfin_mac_resume(struct platform_device *pdev)
1769{
496a34c2 1770 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1771 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1772
53fd3f28
MH		 1773 if (lp->wol) {
1774 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1775 bfin_write_EMAC_WKUP_CTL(0);
1776 disable_irq_wake(IRQ_MAC_WAKEDET);
1777 } else {
1778 if (netif_running(net_dev))
1779 bfin_mac_open(net_dev);
1780 }
496a34c2 1781
e190d6b1
BW		 1782 return 0;
1783}
496a34c2
BW		 1784#else
1785#define bfin_mac_suspend NULL
1786#define bfin_mac_resume NULL
1787#endif /* CONFIG_PM */
e190d6b1 1788
080c8255
GY		 1789static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
1790{
1791 struct mii_bus *miibus;
02460d08
SZ		 1792 struct bfin_mii_bus_platform_data *mii_bus_pd;
1793 const unsigned short *pin_req;
080c8255
GY		 1794 int rc, i;
1795
02460d08
SZ		 1796 mii_bus_pd = dev_get_platdata(&pdev->dev);
1797 if (!mii_bus_pd) {
1798 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1799 return -EINVAL;
1800 }
1801
080c8255
GY		 1802 /*
1803 * We are setting up a network card,
1804 * so set the GPIO pins to Ethernet mode
1805 */
02460d08 1806 pin_req = mii_bus_pd->mac_peripherals;
c6dd5098 1807 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
080c8255
GY		 1808 if (rc) {
1809 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1810 return rc;
1811 }
1812
1813 rc = -ENOMEM;
1814 miibus = mdiobus_alloc();
1815 if (miibus == NULL)
1816 goto out_err_alloc;
1817 miibus->read = bfin_mdiobus_read;
1818 miibus->write = bfin_mdiobus_write;
1819 miibus->reset = bfin_mdiobus_reset;
1820
1821 miibus->parent = &pdev->dev;
1822 miibus->name = "bfin_mii_bus";
02460d08
SZ		 1823 miibus->phy_mask = mii_bus_pd->phy_mask;
1824
75432fd2
FF		 1825 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1826 pdev->name, pdev->id);
080c8255 1827 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
02460d08
SZ		 1828 if (!miibus->irq)
1829 goto out_err_irq_alloc;
1830
1831 for (i = rc; i < PHY_MAX_ADDR; ++i)
080c8255
GY		 1832 miibus->irq[i] = PHY_POLL;
1833
02460d08
SZ		 1834 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1835 if (rc != mii_bus_pd->phydev_number)
1836 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1837 mii_bus_pd->phydev_number);
1838 for (i = 0; i < rc; ++i) {
1839 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1840 if (phyaddr < PHY_MAX_ADDR)
1841 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1842 else
1843 dev_err(&pdev->dev,
1844 "Invalid PHY address %i for phydev %i\n",
1845 phyaddr, i);
1846 }
1847
080c8255
GY		 1848 rc = mdiobus_register(miibus);
1849 if (rc) {
1850 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1851 goto out_err_mdiobus_register;
1852 }
1853
1854 platform_set_drvdata(pdev, miibus);
1855 return 0;
1856
1857out_err_mdiobus_register:
7f267de4 1858 kfree(miibus->irq);
02460d08 1859out_err_irq_alloc:
080c8255
GY		 1860 mdiobus_free(miibus);
1861out_err_alloc:
1862 peripheral_free_list(pin_req);
1863
1864 return rc;
1865}
1866
1867static int __devexit bfin_mii_bus_remove(struct platform_device *pdev)
1868{
1869 struct mii_bus *miibus = platform_get_drvdata(pdev);
02460d08
SZ		 1870 struct bfin_mii_bus_platform_data *mii_bus_pd =
1871 dev_get_platdata(&pdev->dev);
1872
080c8255
GY		 1873 platform_set_drvdata(pdev, NULL);
1874 mdiobus_unregister(miibus);
7f267de4 1875 kfree(miibus->irq);
080c8255 1876 mdiobus_free(miibus);
02460d08
SZ		 1877 peripheral_free_list(mii_bus_pd->mac_peripherals);
1878
080c8255
GY		 1879 return 0;
1880}
1881
1882static struct platform_driver bfin_mii_bus_driver = {
1883 .probe = bfin_mii_bus_probe,
1884 .remove = __devexit_p(bfin_mii_bus_remove),
1885 .driver = {
1886 .name = "bfin_mii_bus",
1887 .owner = THIS_MODULE,
1888 },
1889};
1890
e190d6b1
BW		 1891static struct platform_driver bfin_mac_driver = {
1892 .probe = bfin_mac_probe,
d7b843d3 1893 .remove = __devexit_p(bfin_mac_remove),
e190d6b1
BW		 1894 .resume = bfin_mac_resume,
1895 .suspend = bfin_mac_suspend,
1896 .driver = {
c6dd5098 1897 .name = KBUILD_MODNAME,
72abb461
KS		 1898 .owner = THIS_MODULE,
1899 },
e190d6b1
BW		 1900};
1901
1902static int __init bfin_mac_init(void)
1903{
080c8255
GY		 1904 int ret;
1905 ret = platform_driver_register(&bfin_mii_bus_driver);
1906 if (!ret)
1907 return platform_driver_register(&bfin_mac_driver);
1908 return -ENODEV;
e190d6b1
BW		 1909}
1910
1911module_init(bfin_mac_init);
1912
1913static void __exit bfin_mac_cleanup(void)
1914{
1915 platform_driver_unregister(&bfin_mac_driver);
080c8255 1916 platform_driver_unregister(&bfin_mii_bus_driver);
e190d6b1
BW		 1917}
1918
1919module_exit(bfin_mac_cleanup);
72abb461 1920
Linux kernel - Deliverables
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