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ptp: use the 64 bit get/set time methods for the posix clock.
[deliverable/linux.git] / drivers / net / ethernet / adi / bfin_mac.c
CommitLineData
e190d6b1 1/*
2fb9d6f5 2 * Blackfin On-Chip MAC Driver
e190d6b1 3 *
02460d08 4 * Copyright 2004-2010 Analog Devices Inc.
e190d6b1 5 *
2fb9d6f5 6 * Enter bugs at http://blackfin.uclinux.org/
e190d6b1 7 *
2fb9d6f5 8 * Licensed under the GPL-2 or later.
e190d6b1
BW		 9 */
10
c6dd5098
MF		 11#define DRV_VERSION "1.1"
12#define DRV_DESC "Blackfin on-chip Ethernet MAC driver"
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
e190d6b1
BW		 16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/delay.h>
22#include <linux/timer.h>
23#include <linux/errno.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/crc32.h>
28#include <linux/device.h>
29#include <linux/spinlock.h>
e190d6b1 30#include <linux/mii.h>
e190d6b1
BW		 31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
679dce39 33#include <linux/ethtool.h>
e190d6b1 34#include <linux/skbuff.h>
e190d6b1 35#include <linux/platform_device.h>
e190d6b1
BW		 36
37#include <asm/dma.h>
38#include <linux/dma-mapping.h>
39
fe92afed 40#include <asm/div64.h>
98f672ca 41#include <asm/dpmc.h>
e190d6b1
BW		 42#include <asm/blackfin.h>
43#include <asm/cacheflush.h>
44#include <asm/portmux.h>
3dcc1e7f 45#include <mach/pll.h>
e190d6b1
BW		 46
47#include "bfin_mac.h"
48
c6dd5098 49MODULE_AUTHOR("Bryan Wu, Luke Yang");
e190d6b1
BW		 50MODULE_LICENSE("GPL");
51MODULE_DESCRIPTION(DRV_DESC);
72abb461 52MODULE_ALIAS("platform:bfin_mac");
e190d6b1
BW		 53
54#if defined(CONFIG_BFIN_MAC_USE_L1)
118133e6
SZ		 55# define bfin_mac_alloc(dma_handle, size, num) l1_data_sram_zalloc(size*num)
56# define bfin_mac_free(dma_handle, ptr, num) l1_data_sram_free(ptr)
e190d6b1 57#else
118133e6
SZ		 58# define bfin_mac_alloc(dma_handle, size, num) \
59 dma_alloc_coherent(NULL, size*num, dma_handle, GFP_KERNEL)
60# define bfin_mac_free(dma_handle, ptr, num) \
61 dma_free_coherent(NULL, sizeof(*ptr)*num, ptr, dma_handle)
e190d6b1
BW		 62#endif
63
64#define PKT_BUF_SZ 1580
65
66#define MAX_TIMEOUT_CNT 500
67
68/* pointers to maintain transmit list */
69static struct net_dma_desc_tx *tx_list_head;
70static struct net_dma_desc_tx *tx_list_tail;
71static struct net_dma_desc_rx *rx_list_head;
72static struct net_dma_desc_rx *rx_list_tail;
73static struct net_dma_desc_rx *current_rx_ptr;
74static struct net_dma_desc_tx *current_tx_ptr;
75static struct net_dma_desc_tx *tx_desc;
76static struct net_dma_desc_rx *rx_desc;
77
78static void desc_list_free(void)
79{
80 struct net_dma_desc_rx *r;
81 struct net_dma_desc_tx *t;
82 int i;
83#if !defined(CONFIG_BFIN_MAC_USE_L1)
84 dma_addr_t dma_handle = 0;
85#endif
86
87 if (tx_desc) {
88 t = tx_list_head;
89 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
90 if (t) {
91 if (t->skb) {
92 dev_kfree_skb(t->skb);
93 t->skb = NULL;
94 }
95 t = t->next;
96 }
97 }
118133e6 98 bfin_mac_free(dma_handle, tx_desc, CONFIG_BFIN_TX_DESC_NUM);
e190d6b1
BW		 99 }
100
101 if (rx_desc) {
102 r = rx_list_head;
103 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
104 if (r) {
105 if (r->skb) {
106 dev_kfree_skb(r->skb);
107 r->skb = NULL;
108 }
109 r = r->next;
110 }
111 }
118133e6 112 bfin_mac_free(dma_handle, rx_desc, CONFIG_BFIN_RX_DESC_NUM);
e190d6b1
BW		 113 }
114}
115
1ab0d2ec 116static int desc_list_init(struct net_device *dev)
e190d6b1
BW		 117{
118 int i;
119 struct sk_buff *new_skb;
120#if !defined(CONFIG_BFIN_MAC_USE_L1)
121 /*
122 * This dma_handle is useless in Blackfin dma_alloc_coherent().
123 * The real dma handler is the return value of dma_alloc_coherent().
124 */
125 dma_addr_t dma_handle;
126#endif
127
128 tx_desc = bfin_mac_alloc(&dma_handle,
118133e6 129 sizeof(struct net_dma_desc_tx),
e190d6b1
BW		 130 CONFIG_BFIN_TX_DESC_NUM);
131 if (tx_desc == NULL)
132 goto init_error;
133
134 rx_desc = bfin_mac_alloc(&dma_handle,
118133e6 135 sizeof(struct net_dma_desc_rx),
e190d6b1
BW		 136 CONFIG_BFIN_RX_DESC_NUM);
137 if (rx_desc == NULL)
138 goto init_error;
139
140 /* init tx_list */
141 tx_list_head = tx_list_tail = tx_desc;
142
143 for (i = 0; i < CONFIG_BFIN_TX_DESC_NUM; i++) {
144 struct net_dma_desc_tx *t = tx_desc + i;
145 struct dma_descriptor *a = &(t->desc_a);
146 struct dma_descriptor *b = &(t->desc_b);
147
148 /*
149 * disable DMA
150 * read from memory WNR = 0
151 * wordsize is 32 bits
152 * 6 half words is desc size
153 * large desc flow
154 */
155 a->config = WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
156 a->start_addr = (unsigned long)t->packet;
157 a->x_count = 0;
158 a->next_dma_desc = b;
159
160 /*
161 * enabled DMA
162 * write to memory WNR = 1
163 * wordsize is 32 bits
164 * disable interrupt
165 * 6 half words is desc size
166 * large desc flow
167 */
168 b->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
169 b->start_addr = (unsigned long)(&(t->status));
170 b->x_count = 0;
171
172 t->skb = NULL;
173 tx_list_tail->desc_b.next_dma_desc = a;
174 tx_list_tail->next = t;
175 tx_list_tail = t;
176 }
177 tx_list_tail->next = tx_list_head; /* tx_list is a circle */
178 tx_list_tail->desc_b.next_dma_desc = &(tx_list_head->desc_a);
179 current_tx_ptr = tx_list_head;
180
181 /* init rx_list */
182 rx_list_head = rx_list_tail = rx_desc;
183
184 for (i = 0; i < CONFIG_BFIN_RX_DESC_NUM; i++) {
185 struct net_dma_desc_rx *r = rx_desc + i;
186 struct dma_descriptor *a = &(r->desc_a);
187 struct dma_descriptor *b = &(r->desc_b);
188
189 /* allocate a new skb for next time receive */
1ab0d2ec 190 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
720a43ef 191 if (!new_skb)
e190d6b1 192 goto init_error;
720a43ef 193
015dac88 194 skb_reserve(new_skb, NET_IP_ALIGN);
f6e1e4f3
SZ		 195 /* Invidate the data cache of skb->data range when it is write back
196 * cache. It will prevent overwritting the new data from DMA
197 */
198 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
199 (unsigned long)new_skb->end);
e190d6b1
BW		 200 r->skb = new_skb;
201
202 /*
203 * enabled DMA
204 * write to memory WNR = 1
205 * wordsize is 32 bits
206 * disable interrupt
207 * 6 half words is desc size
208 * large desc flow
209 */
210 a->config = DMAEN | WNR | WDSIZE_32 | NDSIZE_6 | DMAFLOW_LARGE;
211 /* since RXDWA is enabled */
212 a->start_addr = (unsigned long)new_skb->data - 2;
213 a->x_count = 0;
214 a->next_dma_desc = b;
215
216 /*
217 * enabled DMA
218 * write to memory WNR = 1
219 * wordsize is 32 bits
220 * enable interrupt
221 * 6 half words is desc size
222 * large desc flow
223 */
224 b->config = DMAEN | WNR | WDSIZE_32 | DI_EN |
225 NDSIZE_6 | DMAFLOW_LARGE;
226 b->start_addr = (unsigned long)(&(r->status));
227 b->x_count = 0;
228
229 rx_list_tail->desc_b.next_dma_desc = a;
230 rx_list_tail->next = r;
231 rx_list_tail = r;
232 }
233 rx_list_tail->next = rx_list_head; /* rx_list is a circle */
234 rx_list_tail->desc_b.next_dma_desc = &(rx_list_head->desc_a);
235 current_rx_ptr = rx_list_head;
236
237 return 0;
238
239init_error:
240 desc_list_free();
c6dd5098 241 pr_err("kmalloc failed\n");
e190d6b1
BW		 242 return -ENOMEM;
243}
244
245
246/*---PHY CONTROL AND CONFIGURATION-----------------------------------------*/
247
4ae5a3ad
BW		 248/*
249 * MII operations
250 */
e190d6b1 251/* Wait until the previous MDC/MDIO transaction has completed */
2bfa0f0c 252static int bfin_mdio_poll(void)
e190d6b1
BW		 253{
254 int timeout_cnt = MAX_TIMEOUT_CNT;
255
256 /* poll the STABUSY bit */
257 while ((bfin_read_EMAC_STAADD()) & STABUSY) {
6db9e461 258 udelay(1);
e190d6b1 259 if (timeout_cnt-- < 0) {
c6dd5098 260 pr_err("wait MDC/MDIO transaction to complete timeout\n");
2bfa0f0c 261 return -ETIMEDOUT;
e190d6b1
BW		 262 }
263 }
2bfa0f0c
MF		 264
265 return 0;
e190d6b1
BW		 266}
267
268/* Read an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e 269static int bfin_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
e190d6b1 270{
2bfa0f0c
MF		 271 int ret;
272
273 ret = bfin_mdio_poll();
274 if (ret)
275 return ret;
4ae5a3ad 276
e190d6b1 277 /* read mode */
4ae5a3ad
BW		 278 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
279 SET_REGAD((u16) regnum) |
e190d6b1 280 STABUSY);
e190d6b1 281
2bfa0f0c
MF		 282 ret = bfin_mdio_poll();
283 if (ret)
284 return ret;
4ae5a3ad
BW		 285
286 return (int) bfin_read_EMAC_STADAT();
e190d6b1
BW		 287}
288
289/* Write an off-chip register in a PHY through the MDC/MDIO port */
0ed0563e
AB		 290static int bfin_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
291 u16 value)
e190d6b1 292{
2bfa0f0c
MF		 293 int ret;
294
295 ret = bfin_mdio_poll();
296 if (ret)
297 return ret;
4ae5a3ad
BW		 298
299 bfin_write_EMAC_STADAT((u32) value);
e190d6b1
BW		 300
301 /* write mode */
4ae5a3ad
BW		 302 bfin_write_EMAC_STAADD(SET_PHYAD((u16) phy_addr) |
303 SET_REGAD((u16) regnum) |
e190d6b1
BW		 304 STAOP |
305 STABUSY);
306
2bfa0f0c 307 return bfin_mdio_poll();
e190d6b1
BW		 308}
309
7ef0a7ee 310static void bfin_mac_adjust_link(struct net_device *dev)
e190d6b1 311{
7ef0a7ee 312 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 313 struct phy_device *phydev = lp->phydev;
314 unsigned long flags;
315 int new_state = 0;
316
317 spin_lock_irqsave(&lp->lock, flags);
318 if (phydev->link) {
319 /* Now we make sure that we can be in full duplex mode.
320 * If not, we operate in half-duplex mode. */
321 if (phydev->duplex != lp->old_duplex) {
322 u32 opmode = bfin_read_EMAC_OPMODE();
323 new_state = 1;
324
325 if (phydev->duplex)
326 opmode |= FDMODE;
327 else
328 opmode &= ~(FDMODE);
329
330 bfin_write_EMAC_OPMODE(opmode);
331 lp->old_duplex = phydev->duplex;
332 }
e190d6b1 333
4ae5a3ad 334 if (phydev->speed != lp->old_speed) {
02460d08
SZ		 335 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
336 u32 opmode = bfin_read_EMAC_OPMODE();
337 switch (phydev->speed) {
338 case 10:
339 opmode |= RMII_10;
340 break;
341 case 100:
342 opmode &= ~RMII_10;
343 break;
344 default:
c6dd5098
MF		 345 netdev_warn(dev,
346 "Ack! Speed (%d) is not 10/100!\n",
347 phydev->speed);
02460d08
SZ		 348 break;
349 }
350 bfin_write_EMAC_OPMODE(opmode);
4ae5a3ad 351 }
e190d6b1 352
4ae5a3ad
BW		 353 new_state = 1;
354 lp->old_speed = phydev->speed;
355 }
e190d6b1 356
4ae5a3ad
BW		 357 if (!lp->old_link) {
358 new_state = 1;
359 lp->old_link = 1;
4ae5a3ad
BW		 360 }
361 } else if (lp->old_link) {
362 new_state = 1;
363 lp->old_link = 0;
364 lp->old_speed = 0;
365 lp->old_duplex = -1;
e190d6b1
BW		 366 }
367
4ae5a3ad
BW		 368 if (new_state) {
369 u32 opmode = bfin_read_EMAC_OPMODE();
370 phy_print_status(phydev);
371 pr_debug("EMAC_OPMODE = 0x%08x\n", opmode);
e190d6b1 372 }
4ae5a3ad
BW		 373
374 spin_unlock_irqrestore(&lp->lock, flags);
e190d6b1
BW		 375}
376
7cc8f381
BW		 377/* MDC = 2.5 MHz */
378#define MDC_CLK 2500000
379
02460d08 380static int mii_probe(struct net_device *dev, int phy_mode)
e190d6b1 381{
7ef0a7ee 382 struct bfin_mac_local *lp = netdev_priv(dev);
4ae5a3ad
BW		 383 struct phy_device *phydev = NULL;
384 unsigned short sysctl;
385 int i;
7cc8f381 386 u32 sclk, mdc_div;
e190d6b1 387
4ae5a3ad 388 /* Enable PHY output early */
98f672ca
MF		 389 if (!(bfin_read_VR_CTL() & CLKBUFOE))
390 bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
e190d6b1 391
7cc8f381
BW		 392 sclk = get_sclk();
393 mdc_div = ((sclk / MDC_CLK) / 2) - 1;
394
4ae5a3ad 395 sysctl = bfin_read_EMAC_SYSCTL();
9dc7f30e 396 sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(mdc_div);
e190d6b1 397 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1 398
02460d08
SZ		 399 /* search for connected PHY device */
400 for (i = 0; i < PHY_MAX_ADDR; ++i) {
298cf9be 401 struct phy_device *const tmp_phydev = lp->mii_bus->phy_map[i];
e190d6b1 402
4ae5a3ad
BW		 403 if (!tmp_phydev)
404 continue; /* no PHY here... */
e190d6b1 405
4ae5a3ad
BW		 406 phydev = tmp_phydev;
407 break; /* found it */
408 }
409
410 /* now we are supposed to have a proper phydev, to attach to... */
411 if (!phydev) {
c6dd5098 412 netdev_err(dev, "no phy device found\n");
4ae5a3ad 413 return -ENODEV;
e190d6b1
BW		 414 }
415
02460d08
SZ		 416 if (phy_mode != PHY_INTERFACE_MODE_RMII &&
417 phy_mode != PHY_INTERFACE_MODE_MII) {
c6dd5098 418 netdev_err(dev, "invalid phy interface mode\n");
02460d08
SZ		 419 return -EINVAL;
420 }
421
f9a8f83b
FF		 422 phydev = phy_connect(dev, dev_name(&phydev->dev),
423 &bfin_mac_adjust_link, phy_mode);
e190d6b1 424
4ae5a3ad 425 if (IS_ERR(phydev)) {
c6dd5098 426 netdev_err(dev, "could not attach PHY\n");
4ae5a3ad
BW		 427 return PTR_ERR(phydev);
428 }
429
430 /* mask with MAC supported features */
431 phydev->supported &= (SUPPORTED_10baseT_Half
432 | SUPPORTED_10baseT_Full
433 | SUPPORTED_100baseT_Half
434 | SUPPORTED_100baseT_Full
435 | SUPPORTED_Autoneg
436 | SUPPORTED_Pause | SUPPORTED_Asym_Pause
437 | SUPPORTED_MII
438 | SUPPORTED_TP);
439
440 phydev->advertising = phydev->supported;
441
442 lp->old_link = 0;
443 lp->old_speed = 0;
444 lp->old_duplex = -1;
445 lp->phydev = phydev;
446
c6dd5098
MF		 447 pr_info("attached PHY driver [%s] "
448 "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
449 phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
450 MDC_CLK, mdc_div, sclk/1000000);
4ae5a3ad
BW		 451
452 return 0;
453}
454
679dce39
BW		 455/*
456 * Ethtool support
457 */
458
53fd3f28
MH		 459/*
460 * interrupt routine for magic packet wakeup
461 */
462static irqreturn_t bfin_mac_wake_interrupt(int irq, void *dev_id)
463{
464 return IRQ_HANDLED;
465}
466
679dce39
BW		 467static int
468bfin_mac_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
469{
470 struct bfin_mac_local *lp = netdev_priv(dev);
471
472 if (lp->phydev)
473 return phy_ethtool_gset(lp->phydev, cmd);
474
475 return -EINVAL;
476}
477
478static int
479bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
480{
481 struct bfin_mac_local *lp = netdev_priv(dev);
482
483 if (!capable(CAP_NET_ADMIN))
484 return -EPERM;
485
486 if (lp->phydev)
487 return phy_ethtool_sset(lp->phydev, cmd);
488
489 return -EINVAL;
490}
491
492static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
493 struct ethtool_drvinfo *info)
494{
7826d43f
JP		 495 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
496 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
497 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
498 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
679dce39
BW		 499}
500
53fd3f28
MH		 501static void bfin_mac_ethtool_getwol(struct net_device *dev,
502 struct ethtool_wolinfo *wolinfo)
503{
504 struct bfin_mac_local *lp = netdev_priv(dev);
505
506 wolinfo->supported = WAKE_MAGIC;
507 wolinfo->wolopts = lp->wol;
508}
509
510static int bfin_mac_ethtool_setwol(struct net_device *dev,
511 struct ethtool_wolinfo *wolinfo)
512{
513 struct bfin_mac_local *lp = netdev_priv(dev);
514 int rc;
515
516 if (wolinfo->wolopts & (WAKE_MAGICSECURE |
517 WAKE_UCAST |
518 WAKE_MCAST |
519 WAKE_BCAST |
520 WAKE_ARP))
521 return -EOPNOTSUPP;
522
523 lp->wol = wolinfo->wolopts;
524
525 if (lp->wol && !lp->irq_wake_requested) {
526 /* register wake irq handler */
527 rc = request_irq(IRQ_MAC_WAKEDET, bfin_mac_wake_interrupt,
63aca0f7 528 0, "EMAC_WAKE", dev);
53fd3f28
MH		 529 if (rc)
530 return rc;
531 lp->irq_wake_requested = true;
532 }
533
534 if (!lp->wol && lp->irq_wake_requested) {
535 free_irq(IRQ_MAC_WAKEDET, dev);
536 lp->irq_wake_requested = false;
537 }
538
539 /* Make sure the PHY driver doesn't suspend */
540 device_init_wakeup(&dev->dev, lp->wol);
541
542 return 0;
543}
544
85c153d2 545#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
a85bbddd 546static int bfin_mac_ethtool_get_ts_info(struct net_device *dev,
3ffa4290 547 struct ethtool_ts_info *info)
a85bbddd 548{
dd87b22f
RC		 549 struct bfin_mac_local *lp = netdev_priv(dev);
550
a85bbddd
RC		 551 info->so_timestamping =
552 SOF_TIMESTAMPING_TX_HARDWARE |
553 SOF_TIMESTAMPING_RX_HARDWARE |
bc3c5f63 554 SOF_TIMESTAMPING_RAW_HARDWARE;
dd87b22f 555 info->phc_index = lp->phc_index;
a85bbddd
RC		 556 info->tx_types =
557 (1 << HWTSTAMP_TX_OFF) |
558 (1 << HWTSTAMP_TX_ON);
559 info->rx_filters =
560 (1 << HWTSTAMP_FILTER_NONE) |
561 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
562 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
563 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
564 return 0;
565}
85c153d2 566#endif
a85bbddd 567
0fc0b732 568static const struct ethtool_ops bfin_mac_ethtool_ops = {
679dce39
BW		 569 .get_settings = bfin_mac_ethtool_getsettings,
570 .set_settings = bfin_mac_ethtool_setsettings,
571 .get_link = ethtool_op_get_link,
572 .get_drvinfo = bfin_mac_ethtool_getdrvinfo,
53fd3f28
MH		 573 .get_wol = bfin_mac_ethtool_getwol,
574 .set_wol = bfin_mac_ethtool_setwol,
85c153d2 575#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
a85bbddd 576 .get_ts_info = bfin_mac_ethtool_get_ts_info,
85c153d2 577#endif
679dce39
BW		 578};
579
4ae5a3ad 580/**************************************************************************/
5ca1bb5a 581static void setup_system_regs(struct net_device *dev)
4ae5a3ad 582{
02460d08
SZ		 583 struct bfin_mac_local *lp = netdev_priv(dev);
584 int i;
4ae5a3ad
BW		 585 unsigned short sysctl;
586
587 /*
588 * Odd word alignment for Receive Frame DMA word
589 * Configure checksum support and rcve frame word alignment
590 */
591 sysctl = bfin_read_EMAC_SYSCTL();
02460d08
SZ		 592 /*
593 * check if interrupt is requested for any PHY,
594 * enable PHY interrupt only if needed
595 */
596 for (i = 0; i < PHY_MAX_ADDR; ++i)
597 if (lp->mii_bus->irq[i] != PHY_POLL)
598 break;
599 if (i < PHY_MAX_ADDR)
600 sysctl |= PHYIE;
812a9de7 601 sysctl |= RXDWA;
4ae5a3ad 602#if defined(BFIN_MAC_CSUM_OFFLOAD)
812a9de7 603 sysctl |= RXCKS;
4ae5a3ad 604#else
812a9de7 605 sysctl &= ~RXCKS;
4ae5a3ad
BW		 606#endif
607 bfin_write_EMAC_SYSCTL(sysctl);
e190d6b1
BW		 608
609 bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
610
c599bd6b
MF		 611 /* Set vlan regs to let 1522 bytes long packets pass through */
612 bfin_write_EMAC_VLAN1(lp->vlan1_mask);
613 bfin_write_EMAC_VLAN2(lp->vlan2_mask);
614
e190d6b1
BW		 615 /* Initialize the TX DMA channel registers */
616 bfin_write_DMA2_X_COUNT(0);
617 bfin_write_DMA2_X_MODIFY(4);
618 bfin_write_DMA2_Y_COUNT(0);
619 bfin_write_DMA2_Y_MODIFY(0);
620
621 /* Initialize the RX DMA channel registers */
622 bfin_write_DMA1_X_COUNT(0);
623 bfin_write_DMA1_X_MODIFY(4);
624 bfin_write_DMA1_Y_COUNT(0);
625 bfin_write_DMA1_Y_MODIFY(0);
626}
627
73f83182 628static void setup_mac_addr(u8 *mac_addr)
e190d6b1
BW		 629{
630 u32 addr_low = le32_to_cpu(*(__le32 *) & mac_addr[0]);
631 u16 addr_hi = le16_to_cpu(*(__le16 *) & mac_addr[4]);
632
633 /* this depends on a little-endian machine */
634 bfin_write_EMAC_ADDRLO(addr_low);
635 bfin_write_EMAC_ADDRHI(addr_hi);
636}
637
7ef0a7ee 638static int bfin_mac_set_mac_address(struct net_device *dev, void *p)
73f83182
AL		 639{
640 struct sockaddr *addr = p;
641 if (netif_running(dev))
642 return -EBUSY;
643 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
644 setup_mac_addr(dev->dev_addr);
645 return 0;
646}
647
fe92afed
BS		 648#ifdef CONFIG_BFIN_MAC_USE_HWSTAMP
649#define bfin_mac_hwtstamp_is_none(cfg) ((cfg) == HWTSTAMP_FILTER_NONE)
650
bc3c5f63
RC		 651static u32 bfin_select_phc_clock(u32 input_clk, unsigned int *shift_result)
652{
653 u32 ipn = 1000000000UL / input_clk;
654 u32 ppn = 1;
655 unsigned int shift = 0;
656
657 while (ppn <= ipn) {
658 ppn <<= 1;
659 shift++;
660 }
661 *shift_result = shift;
662 return 1000000000UL / ppn;
663}
664
7575c917
BH		 665static int bfin_mac_hwtstamp_set(struct net_device *netdev,
666 struct ifreq *ifr)
fe92afed
BS		 667{
668 struct hwtstamp_config config;
669 struct bfin_mac_local *lp = netdev_priv(netdev);
670 u16 ptpctl;
671 u32 ptpfv1, ptpfv2, ptpfv3, ptpfoff;
672
673 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
674 return -EFAULT;
675
676 pr_debug("%s config flag:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
677 __func__, config.flags, config.tx_type, config.rx_filter);
678
679 /* reserved for future extensions */
680 if (config.flags)
681 return -EINVAL;
682
683 if ((config.tx_type != HWTSTAMP_TX_OFF) &&
684 (config.tx_type != HWTSTAMP_TX_ON))
685 return -ERANGE;
686
687 ptpctl = bfin_read_EMAC_PTP_CTL();
688
689 switch (config.rx_filter) {
690 case HWTSTAMP_FILTER_NONE:
691 /*
692 * Dont allow any timestamping
693 */
694 ptpfv3 = 0xFFFFFFFF;
695 bfin_write_EMAC_PTP_FV3(ptpfv3);
696 break;
697 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
698 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
699 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
700 /*
701 * Clear the five comparison mask bits (bits[12:8]) in EMAC_PTP_CTL)
702 * to enable all the field matches.
703 */
704 ptpctl &= ~0x1F00;
705 bfin_write_EMAC_PTP_CTL(ptpctl);
706 /*
707 * Keep the default values of the EMAC_PTP_FOFF register.
708 */
709 ptpfoff = 0x4A24170C;
710 bfin_write_EMAC_PTP_FOFF(ptpfoff);
711 /*
712 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
713 * registers.
714 */
715 ptpfv1 = 0x11040800;
716 bfin_write_EMAC_PTP_FV1(ptpfv1);
717 ptpfv2 = 0x0140013F;
718 bfin_write_EMAC_PTP_FV2(ptpfv2);
719 /*
720 * The default value (0xFFFC) allows the timestamping of both
721 * received Sync messages and Delay_Req messages.
722 */
723 ptpfv3 = 0xFFFFFFFC;
724 bfin_write_EMAC_PTP_FV3(ptpfv3);
725
726 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
727 break;
728 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
729 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
730 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
731 /* Clear all five comparison mask bits (bits[12:8]) in the
732 * EMAC_PTP_CTL register to enable all the field matches.
733 */
734 ptpctl &= ~0x1F00;
735 bfin_write_EMAC_PTP_CTL(ptpctl);
736 /*
737 * Keep the default values of the EMAC_PTP_FOFF register, except set
738 * the PTPCOF field to 0x2A.
739 */
740 ptpfoff = 0x2A24170C;
741 bfin_write_EMAC_PTP_FOFF(ptpfoff);
742 /*
743 * Keep the default values of the EMAC_PTP_FV1 and EMAC_PTP_FV2
744 * registers.
745 */
746 ptpfv1 = 0x11040800;
747 bfin_write_EMAC_PTP_FV1(ptpfv1);
748 ptpfv2 = 0x0140013F;
749 bfin_write_EMAC_PTP_FV2(ptpfv2);
750 /*
751 * To allow the timestamping of Pdelay_Req and Pdelay_Resp, set
752 * the value to 0xFFF0.
753 */
754 ptpfv3 = 0xFFFFFFF0;
755 bfin_write_EMAC_PTP_FV3(ptpfv3);
756
757 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
758 break;
759 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
760 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
761 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
762 /*
763 * Clear bits 8 and 12 of the EMAC_PTP_CTL register to enable only the
764 * EFTM and PTPCM field comparison.
765 */
766 ptpctl &= ~0x1100;
767 bfin_write_EMAC_PTP_CTL(ptpctl);
768 /*
769 * Keep the default values of all the fields of the EMAC_PTP_FOFF
770 * register, except set the PTPCOF field to 0x0E.
771 */
772 ptpfoff = 0x0E24170C;
773 bfin_write_EMAC_PTP_FOFF(ptpfoff);
774 /*
775 * Program bits [15:0] of the EMAC_PTP_FV1 register to 0x88F7, which
776 * corresponds to PTP messages on the MAC layer.
777 */
778 ptpfv1 = 0x110488F7;
779 bfin_write_EMAC_PTP_FV1(ptpfv1);
780 ptpfv2 = 0x0140013F;
781 bfin_write_EMAC_PTP_FV2(ptpfv2);
782 /*
783 * To allow the timestamping of Pdelay_Req and Pdelay_Resp
784 * messages, set the value to 0xFFF0.
785 */
786 ptpfv3 = 0xFFFFFFF0;
787 bfin_write_EMAC_PTP_FV3(ptpfv3);
788
789 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
790 break;
791 default:
792 return -ERANGE;
793 }
794
795 if (config.tx_type == HWTSTAMP_TX_OFF &&
796 bfin_mac_hwtstamp_is_none(config.rx_filter)) {
797 ptpctl &= ~PTP_EN;
798 bfin_write_EMAC_PTP_CTL(ptpctl);
799
800 SSYNC();
801 } else {
802 ptpctl |= PTP_EN;
803 bfin_write_EMAC_PTP_CTL(ptpctl);
804
805 /*
806 * clear any existing timestamp
807 */
808 bfin_read_EMAC_PTP_RXSNAPLO();
809 bfin_read_EMAC_PTP_RXSNAPHI();
810
811 bfin_read_EMAC_PTP_TXSNAPLO();
812 bfin_read_EMAC_PTP_TXSNAPHI();
813
fe92afed 814 SSYNC();
fe92afed
BS		 815 }
816
817 lp->stamp_cfg = config;
818 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
819 -EFAULT : 0;
820}
821
7575c917
BH		 822static int bfin_mac_hwtstamp_get(struct net_device *netdev,
823 struct ifreq *ifr)
824{
825 struct bfin_mac_local *lp = netdev_priv(netdev);
826
827 return copy_to_user(ifr->ifr_data, &lp->stamp_cfg,
828 sizeof(lp->stamp_cfg)) ?
829 -EFAULT : 0;
830}
831
fe92afed
BS		 832static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
833{
834 struct bfin_mac_local *lp = netdev_priv(netdev);
fe92afed 835
2244d07b 836 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
fe92afed
BS		 837 int timeout_cnt = MAX_TIMEOUT_CNT;
838
839 /* When doing time stamping, keep the connection to the socket
840 * a while longer
841 */
2244d07b 842 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
fe92afed
BS		 843
844 /*
845 * The timestamping is done at the EMAC module's MII/RMII interface
846 * when the module sees the Start of Frame of an event message packet. This
847 * interface is the closest possible place to the physical Ethernet transmission
848 * medium, providing the best timing accuracy.
849 */
850 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
851 udelay(1);
852 if (timeout_cnt == 0)
c6dd5098 853 netdev_err(netdev, "timestamp the TX packet failed\n");
fe92afed
BS		 854 else {
855 struct skb_shared_hwtstamps shhwtstamps;
856 u64 ns;
857 u64 regval;
858
859 regval = bfin_read_EMAC_PTP_TXSNAPLO();
860 regval |= (u64)bfin_read_EMAC_PTP_TXSNAPHI() << 32;
861 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
bc3c5f63 862 ns = regval << lp->shift;
fe92afed 863 shhwtstamps.hwtstamp = ns_to_ktime(ns);
fe92afed 864 skb_tstamp_tx(skb, &shhwtstamps);
fe92afed
BS		 865 }
866 }
867}
868
869static void bfin_rx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
870{
871 struct bfin_mac_local *lp = netdev_priv(netdev);
872 u32 valid;
873 u64 regval, ns;
874 struct skb_shared_hwtstamps *shhwtstamps;
875
876 if (bfin_mac_hwtstamp_is_none(lp->stamp_cfg.rx_filter))
877 return;
878
879 valid = bfin_read_EMAC_PTP_ISTAT() & RXEL;
880 if (!valid)
881 return;
882
883 shhwtstamps = skb_hwtstamps(skb);
884
885 regval = bfin_read_EMAC_PTP_RXSNAPLO();
886 regval |= (u64)bfin_read_EMAC_PTP_RXSNAPHI() << 32;
bc3c5f63 887 ns = regval << lp->shift;
fe92afed
BS		 888 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
889 shhwtstamps->hwtstamp = ns_to_ktime(ns);
fe92afed
BS		 890}
891
fe92afed
BS		 892static void bfin_mac_hwtstamp_init(struct net_device *netdev)
893{
894 struct bfin_mac_local *lp = netdev_priv(netdev);
dd87b22f 895 u64 addend, ppb;
bc3c5f63 896 u32 input_clk, phc_clk;
fe92afed
BS		 897
898 /* Initialize hardware timer */
bc3c5f63
RC		 899 input_clk = get_sclk();
900 phc_clk = bfin_select_phc_clock(input_clk, &lp->shift);
901 addend = phc_clk * (1ULL << 32);
902 do_div(addend, input_clk);
903 bfin_write_EMAC_PTP_ADDEND((u32)addend);
904
905 lp->addend = addend;
dd87b22f
RC		 906 ppb = 1000000000ULL * input_clk;
907 do_div(ppb, phc_clk);
908 lp->max_ppb = ppb - 1000000000ULL - 1ULL;
fe92afed
BS		 909
910 /* Initialize hwstamp config */
911 lp->stamp_cfg.rx_filter = HWTSTAMP_FILTER_NONE;
912 lp->stamp_cfg.tx_type = HWTSTAMP_TX_OFF;
913}
914
dd87b22f
RC		 915static u64 bfin_ptp_time_read(struct bfin_mac_local *lp)
916{
917 u64 ns;
918 u32 lo, hi;
919
920 lo = bfin_read_EMAC_PTP_TIMELO();
921 hi = bfin_read_EMAC_PTP_TIMEHI();
922
923 ns = ((u64) hi) << 32;
924 ns |= lo;
925 ns <<= lp->shift;
926
927 return ns;
928}
929
930static void bfin_ptp_time_write(struct bfin_mac_local *lp, u64 ns)
931{
932 u32 hi, lo;
933
934 ns >>= lp->shift;
935 hi = ns >> 32;
936 lo = ns & 0xffffffff;
937
938 bfin_write_EMAC_PTP_TIMELO(lo);
939 bfin_write_EMAC_PTP_TIMEHI(hi);
940}
941
942/* PTP Hardware Clock operations */
943
944static int bfin_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
945{
946 u64 adj;
947 u32 diff, addend;
948 int neg_adj = 0;
949 struct bfin_mac_local *lp =
950 container_of(ptp, struct bfin_mac_local, caps);
951
952 if (ppb < 0) {
953 neg_adj = 1;
954 ppb = -ppb;
955 }
956 addend = lp->addend;
957 adj = addend;
958 adj *= ppb;
959 diff = div_u64(adj, 1000000000ULL);
960
961 addend = neg_adj ? addend - diff : addend + diff;
962
963 bfin_write_EMAC_PTP_ADDEND(addend);
964
965 return 0;
966}
967
968static int bfin_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
969{
970 s64 now;
971 unsigned long flags;
972 struct bfin_mac_local *lp =
973 container_of(ptp, struct bfin_mac_local, caps);
974
975 spin_lock_irqsave(&lp->phc_lock, flags);
976
977 now = bfin_ptp_time_read(lp);
978 now += delta;
979 bfin_ptp_time_write(lp, now);
980
981 spin_unlock_irqrestore(&lp->phc_lock, flags);
982
983 return 0;
984}
985
986static int bfin_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
987{
988 u64 ns;
989 u32 remainder;
990 unsigned long flags;
991 struct bfin_mac_local *lp =
992 container_of(ptp, struct bfin_mac_local, caps);
993
994 spin_lock_irqsave(&lp->phc_lock, flags);
995
996 ns = bfin_ptp_time_read(lp);
997
998 spin_unlock_irqrestore(&lp->phc_lock, flags);
999
1000 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
1001 ts->tv_nsec = remainder;
1002 return 0;
1003}
1004
1005static int bfin_ptp_settime(struct ptp_clock_info *ptp,
1006 const struct timespec *ts)
1007{
1008 u64 ns;
1009 unsigned long flags;
1010 struct bfin_mac_local *lp =
1011 container_of(ptp, struct bfin_mac_local, caps);
1012
1013 ns = ts->tv_sec * 1000000000ULL;
1014 ns += ts->tv_nsec;
1015
1016 spin_lock_irqsave(&lp->phc_lock, flags);
1017
1018 bfin_ptp_time_write(lp, ns);
1019
1020 spin_unlock_irqrestore(&lp->phc_lock, flags);
1021
1022 return 0;
1023}
1024
1025static int bfin_ptp_enable(struct ptp_clock_info *ptp,
1026 struct ptp_clock_request *rq, int on)
1027{
1028 return -EOPNOTSUPP;
1029}
1030
1031static struct ptp_clock_info bfin_ptp_caps = {
1032 .owner = THIS_MODULE,
1033 .name = "BF518 clock",
1034 .max_adj = 0,
1035 .n_alarm = 0,
1036 .n_ext_ts = 0,
1037 .n_per_out = 0,
4986b4f0 1038 .n_pins = 0,
dd87b22f
RC		 1039 .pps = 0,
1040 .adjfreq = bfin_ptp_adjfreq,
1041 .adjtime = bfin_ptp_adjtime,
1042 .gettime = bfin_ptp_gettime,
1043 .settime = bfin_ptp_settime,
1044 .enable = bfin_ptp_enable,
1045};
1046
1047static int bfin_phc_init(struct net_device *netdev, struct device *dev)
1048{
1049 struct bfin_mac_local *lp = netdev_priv(netdev);
1050
1051 lp->caps = bfin_ptp_caps;
1052 lp->caps.max_adj = lp->max_ppb;
1053 lp->clock = ptp_clock_register(&lp->caps, dev);
1054 if (IS_ERR(lp->clock))
1055 return PTR_ERR(lp->clock);
1056
1057 lp->phc_index = ptp_clock_index(lp->clock);
1058 spin_lock_init(&lp->phc_lock);
1059
1060 return 0;
1061}
1062
1063static void bfin_phc_release(struct bfin_mac_local *lp)
1064{
1065 ptp_clock_unregister(lp->clock);
1066}
1067
fe92afed
BS		 1068#else
1069# define bfin_mac_hwtstamp_is_none(cfg) 0
1070# define bfin_mac_hwtstamp_init(dev)
7575c917
BH		 1071# define bfin_mac_hwtstamp_set(dev, ifr) (-EOPNOTSUPP)
1072# define bfin_mac_hwtstamp_get(dev, ifr) (-EOPNOTSUPP)
fe92afed
BS		 1073# define bfin_rx_hwtstamp(dev, skb)
1074# define bfin_tx_hwtstamp(dev, skb)
dd87b22f
RC		 1075# define bfin_phc_init(netdev, dev) 0
1076# define bfin_phc_release(lp)
fe92afed
BS		 1077#endif
1078
4fcc3d34
SZ		 1079static inline void _tx_reclaim_skb(void)
1080{
1081 do {
1082 tx_list_head->desc_a.config &= ~DMAEN;
1083 tx_list_head->status.status_word = 0;
1084 if (tx_list_head->skb) {
21534d20 1085 dev_consume_skb_any(tx_list_head->skb);
4fcc3d34
SZ		 1086 tx_list_head->skb = NULL;
1087 }
1088 tx_list_head = tx_list_head->next;
1089
1090 } while (tx_list_head->status.status_word != 0);
1091}
1092
1093static void tx_reclaim_skb(struct bfin_mac_local *lp)
e190d6b1
BW		 1094{
1095 int timeout_cnt = MAX_TIMEOUT_CNT;
1096
4fcc3d34
SZ		 1097 if (tx_list_head->status.status_word != 0)
1098 _tx_reclaim_skb();
e190d6b1 1099
4fcc3d34 1100 if (current_tx_ptr->next == tx_list_head) {
e190d6b1 1101 while (tx_list_head->status.status_word == 0) {
4fcc3d34 1102 /* slow down polling to avoid too many queue stop. */
015dac88 1103 udelay(10);
4fcc3d34
SZ		 1104 /* reclaim skb if DMA is not running. */
1105 if (!(bfin_read_DMA2_IRQ_STATUS() & DMA_RUN))
1106 break;
1107 if (timeout_cnt-- < 0)
e190d6b1 1108 break;
e190d6b1 1109 }
4fcc3d34
SZ		 1110
1111 if (timeout_cnt >= 0)
1112 _tx_reclaim_skb();
1113 else
1114 netif_stop_queue(lp->ndev);
e190d6b1
BW		 1115 }
1116
4fcc3d34
SZ		 1117 if (current_tx_ptr->next != tx_list_head &&
1118 netif_queue_stopped(lp->ndev))
1119 netif_wake_queue(lp->ndev);
1120
1121 if (tx_list_head != current_tx_ptr) {
1122 /* shorten the timer interval if tx queue is stopped */
1123 if (netif_queue_stopped(lp->ndev))
1124 lp->tx_reclaim_timer.expires =
1125 jiffies + (TX_RECLAIM_JIFFIES >> 4);
1126 else
1127 lp->tx_reclaim_timer.expires =
1128 jiffies + TX_RECLAIM_JIFFIES;
1129
1130 mod_timer(&lp->tx_reclaim_timer,
1131 lp->tx_reclaim_timer.expires);
1132 }
e190d6b1 1133
e190d6b1 1134 return;
4fcc3d34 1135}
e190d6b1 1136
4fcc3d34
SZ		 1137static void tx_reclaim_skb_timeout(unsigned long lp)
1138{
1139 tx_reclaim_skb((struct bfin_mac_local *)lp);
e190d6b1
BW		 1140}
1141
7ef0a7ee 1142static int bfin_mac_hard_start_xmit(struct sk_buff *skb,
e190d6b1
BW		 1143 struct net_device *dev)
1144{
4fcc3d34 1145 struct bfin_mac_local *lp = netdev_priv(dev);
a50c0c05 1146 u16 *data;
015dac88 1147 u32 data_align = (unsigned long)(skb->data) & 0x3;
fe92afed 1148
e190d6b1
BW		 1149 current_tx_ptr->skb = skb;
1150
015dac88
MH		 1151 if (data_align == 0x2) {
1152 /* move skb->data to current_tx_ptr payload */
1153 data = (u16 *)(skb->data) - 1;
fe92afed
BS		 1154 *data = (u16)(skb->len);
1155 /*
1156 * When transmitting an Ethernet packet, the PTP_TSYNC module requires
1157 * a DMA_Length_Word field associated with the packet. The lower 12 bits
1158 * of this field are the length of the packet payload in bytes and the higher
1159 * 4 bits are the timestamping enable field.
1160 */
2244d07b 1161 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed
BS		 1162 *data |= 0x1000;
1163
015dac88
MH		 1164 current_tx_ptr->desc_a.start_addr = (u32)data;
1165 /* this is important! */
1166 blackfin_dcache_flush_range((u32)data,
1167 (u32)((u8 *)data + skb->len + 4));
e190d6b1 1168 } else {
015dac88 1169 *((u16 *)(current_tx_ptr->packet)) = (u16)(skb->len);
fe92afed 1170 /* enable timestamping for the sent packet */
2244d07b 1171 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)
fe92afed 1172 *((u16 *)(current_tx_ptr->packet)) |= 0x1000;
015dac88
MH		 1173 memcpy((u8 *)(current_tx_ptr->packet + 2), skb->data,
1174 skb->len);
1175 current_tx_ptr->desc_a.start_addr =
1176 (u32)current_tx_ptr->packet;
015dac88
MH		 1177 blackfin_dcache_flush_range(
1178 (u32)current_tx_ptr->packet,
1179 (u32)(current_tx_ptr->packet + skb->len + 2));
e190d6b1
BW		 1180 }
1181
805a8ab3
SZ		 1182 /* make sure the internal data buffers in the core are drained
1183 * so that the DMA descriptors are completely written when the
1184 * DMA engine goes to fetch them below
1185 */
1186 SSYNC();
1187
4fcc3d34
SZ		 1188 /* always clear status buffer before start tx dma */
1189 current_tx_ptr->status.status_word = 0;
1190
e190d6b1
BW		 1191 /* enable this packet's dma */
1192 current_tx_ptr->desc_a.config |= DMAEN;
1193
1194 /* tx dma is running, just return */
015dac88 1195 if (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN)
e190d6b1
BW		 1196 goto out;
1197
1198 /* tx dma is not running */
1199 bfin_write_DMA2_NEXT_DESC_PTR(&(current_tx_ptr->desc_a));
1200 /* dma enabled, read from memory, size is 6 */
1201 bfin_write_DMA2_CONFIG(current_tx_ptr->desc_a.config);
1202 /* Turn on the EMAC tx */
1203 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1204
1205out:
fe92afed
BS		 1206 bfin_tx_hwtstamp(dev, skb);
1207
e190d6b1 1208 current_tx_ptr = current_tx_ptr->next;
09f75cd7
JG		 1209 dev->stats.tx_packets++;
1210 dev->stats.tx_bytes += (skb->len);
4fcc3d34
SZ		 1211
1212 tx_reclaim_skb(lp);
1213
6ed10654 1214 return NETDEV_TX_OK;
e190d6b1
BW		 1215}
1216
ad2864d8 1217#define IP_HEADER_OFF 0
ec497b32
PM		 1218#define RX_ERROR_MASK (RX_LONG | RX_ALIGN | RX_CRC | RX_LEN | \
1219 RX_FRAG | RX_ADDR | RX_DMAO | RX_PHY | RX_LATE | RX_RANGE)
1220
159945af 1221static void bfin_mac_rx(struct bfin_mac_local *lp)
e190d6b1 1222{
159945af 1223 struct net_device *dev = lp->ndev;
e190d6b1 1224 struct sk_buff *skb, *new_skb;
e190d6b1 1225 unsigned short len;
ad2864d8
SZ		 1226#if defined(BFIN_MAC_CSUM_OFFLOAD)
1227 unsigned int i;
1228 unsigned char fcs[ETH_FCS_LEN + 1];
1229#endif
e190d6b1 1230
ec497b32
PM		 1231 /* check if frame status word reports an error condition
1232 * we which case we simply drop the packet
1233 */
1234 if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
c6dd5098 1235 netdev_notice(dev, "rx: receive error - packet dropped\n");
ec497b32
PM		 1236 dev->stats.rx_dropped++;
1237 goto out;
1238 }
1239
e190d6b1
BW		 1240 /* allocate a new skb for next time receive */
1241 skb = current_rx_ptr->skb;
fe92afed 1242
1ab0d2ec 1243 new_skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
e190d6b1 1244 if (!new_skb) {
09f75cd7 1245 dev->stats.rx_dropped++;
e190d6b1
BW		 1246 goto out;
1247 }
1248 /* reserve 2 bytes for RXDWA padding */
015dac88 1249 skb_reserve(new_skb, NET_IP_ALIGN);
6e01d1a4
AD		 1250 /* Invidate the data cache of skb->data range when it is write back
1251 * cache. It will prevent overwritting the new data from DMA
1252 */
1253 blackfin_dcache_invalidate_range((unsigned long)new_skb->head,
1254 (unsigned long)new_skb->end);
1255
f6e1e4f3
SZ		 1256 current_rx_ptr->skb = new_skb;
1257 current_rx_ptr->desc_a.start_addr = (unsigned long)new_skb->data - 2;
1258
159945af 1259 len = (unsigned short)(current_rx_ptr->status.status_word & RX_FRLEN);
ad2864d8
SZ		 1260 /* Deduce Ethernet FCS length from Ethernet payload length */
1261 len -= ETH_FCS_LEN;
e190d6b1 1262 skb_put(skb, len);
e190d6b1 1263
e190d6b1 1264 skb->protocol = eth_type_trans(skb, dev);
fe92afed
BS		 1265
1266 bfin_rx_hwtstamp(dev, skb);
1267
e190d6b1 1268#if defined(BFIN_MAC_CSUM_OFFLOAD)
ad2864d8
SZ		 1269 /* Checksum offloading only works for IPv4 packets with the standard IP header
1270 * length of 20 bytes, because the blackfin MAC checksum calculation is
1271 * based on that assumption. We must NOT use the calculated checksum if our
1272 * IP version or header break that assumption.
1273 */
1274 if (skb->data[IP_HEADER_OFF] == 0x45) {
1275 skb->csum = current_rx_ptr->status.ip_payload_csum;
1276 /*
1277 * Deduce Ethernet FCS from hardware generated IP payload checksum.
1278 * IP checksum is based on 16-bit one's complement algorithm.
1279 * To deduce a value from checksum is equal to add its inversion.
1280 * If the IP payload len is odd, the inversed FCS should also
1281 * begin from odd address and leave first byte zero.
1282 */
1283 if (skb->len % 2) {
1284 fcs[0] = 0;
1285 for (i = 0; i < ETH_FCS_LEN; i++)
1286 fcs[i + 1] = ~skb->data[skb->len + i];
1287 skb->csum = csum_partial(fcs, ETH_FCS_LEN + 1, skb->csum);
1288 } else {
1289 for (i = 0; i < ETH_FCS_LEN; i++)
1290 fcs[i] = ~skb->data[skb->len + i];
1291 skb->csum = csum_partial(fcs, ETH_FCS_LEN, skb->csum);
1292 }
1293 skb->ip_summed = CHECKSUM_COMPLETE;
1294 }
e190d6b1
BW		 1295#endif
1296
159945af
SZ		 1297 napi_gro_receive(&lp->napi, skb);
1298
09f75cd7
JG		 1299 dev->stats.rx_packets++;
1300 dev->stats.rx_bytes += len;
ec497b32 1301out:
e190d6b1
BW		 1302 current_rx_ptr->status.status_word = 0x00000000;
1303 current_rx_ptr = current_rx_ptr->next;
e190d6b1
BW		 1304}
1305
159945af
SZ		 1306static int bfin_mac_poll(struct napi_struct *napi, int budget)
1307{
1308 int i = 0;
1309 struct bfin_mac_local *lp = container_of(napi,
1310 struct bfin_mac_local,
1311 napi);
1312
1313 while (current_rx_ptr->status.status_word != 0 && i < budget) {
1314 bfin_mac_rx(lp);
1315 i++;
1316 }
1317
1318 if (i < budget) {
1319 napi_complete(napi);
1320 if (test_and_clear_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags))
1321 enable_irq(IRQ_MAC_RX);
1322 }
1323
1324 return i;
1325}
1326
e190d6b1 1327/* interrupt routine to handle rx and error signal */
7ef0a7ee 1328static irqreturn_t bfin_mac_interrupt(int irq, void *dev_id)
e190d6b1 1329{
159945af
SZ		 1330 struct bfin_mac_local *lp = netdev_priv(dev_id);
1331 u32 status;
1332
1333 status = bfin_read_DMA1_IRQ_STATUS();
1334
1335 bfin_write_DMA1_IRQ_STATUS(status | DMA_DONE | DMA_ERR);
1336 if (status & DMA_DONE) {
1337 disable_irq_nosync(IRQ_MAC_RX);
1338 set_bit(BFIN_MAC_RX_IRQ_DISABLED, &lp->flags);
1339 napi_schedule(&lp->napi);
e190d6b1
BW		 1340 }
1341
159945af 1342 return IRQ_HANDLED;
e190d6b1
BW		 1343}
1344
1345#ifdef CONFIG_NET_POLL_CONTROLLER
159945af 1346static void bfin_mac_poll_controller(struct net_device *dev)
e190d6b1 1347{
4fcc3d34
SZ		 1348 struct bfin_mac_local *lp = netdev_priv(dev);
1349
7ef0a7ee 1350 bfin_mac_interrupt(IRQ_MAC_RX, dev);
4fcc3d34 1351 tx_reclaim_skb(lp);
e190d6b1
BW		 1352}
1353#endif /* CONFIG_NET_POLL_CONTROLLER */
1354
7ef0a7ee 1355static void bfin_mac_disable(void)
e190d6b1
BW		 1356{
1357 unsigned int opmode;
1358
1359 opmode = bfin_read_EMAC_OPMODE();
1360 opmode &= (~RE);
1361 opmode &= (~TE);
1362 /* Turn off the EMAC */
1363 bfin_write_EMAC_OPMODE(opmode);
1364}
1365
1366/*
1367 * Enable Interrupts, Receive, and Transmit
1368 */
02460d08 1369static int bfin_mac_enable(struct phy_device *phydev)
e190d6b1 1370{
2bfa0f0c 1371 int ret;
e190d6b1
BW		 1372 u32 opmode;
1373
c6dd5098 1374 pr_debug("%s\n", __func__);
e190d6b1
BW		 1375
1376 /* Set RX DMA */
1377 bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
1378 bfin_write_DMA1_CONFIG(rx_list_head->desc_a.config);
1379
1380 /* Wait MII done */
2bfa0f0c
MF		 1381 ret = bfin_mdio_poll();
1382 if (ret)
1383 return ret;
e190d6b1
BW		 1384
1385 /* We enable only RX here */
1386 /* ASTP : Enable Automatic Pad Stripping
1387 PR : Promiscuous Mode for test
1388 PSF : Receive frames with total length less than 64 bytes.
1389 FDMODE : Full Duplex Mode
1390 LB : Internal Loopback for test
1391 RE : Receiver Enable */
1392 opmode = bfin_read_EMAC_OPMODE();
1393 if (opmode & FDMODE)
1394 opmode |= PSF;
1395 else
1396 opmode |= DRO | DC | PSF;
1397 opmode |= RE;
1398
02460d08
SZ		 1399 if (phydev->interface == PHY_INTERFACE_MODE_RMII) {
1400 opmode |= RMII; /* For Now only 100MBit are supported */
72f49050
MF		 1401#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
1402 if (__SILICON_REVISION__ < 3) {
1403 /*
1404 * This isn't publicly documented (fun times!), but in
1405 * silicon <=0.2, the RX and TX pins are clocked together.
1406 * So in order to recv, we must enable the transmit side
1407 * as well. This will cause a spurious TX interrupt too,
1408 * but we can easily consume that.
1409 */
1410 opmode |= TE;
1411 }
e190d6b1 1412#endif
02460d08
SZ		 1413 }
1414
e190d6b1
BW		 1415 /* Turn on the EMAC rx */
1416 bfin_write_EMAC_OPMODE(opmode);
2bfa0f0c
MF		 1417
1418 return 0;
e190d6b1
BW		 1419}
1420
1421/* Our watchdog timed out. Called by the networking layer */
7ef0a7ee 1422static void bfin_mac_timeout(struct net_device *dev)
e190d6b1 1423{
4fcc3d34
SZ		 1424 struct bfin_mac_local *lp = netdev_priv(dev);
1425
b39d66a8 1426 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1 1427
7ef0a7ee 1428 bfin_mac_disable();
e190d6b1 1429
4fcc3d34
SZ		 1430 del_timer(&lp->tx_reclaim_timer);
1431
1432 /* reset tx queue and free skb */
1433 while (tx_list_head != current_tx_ptr) {
1434 tx_list_head->desc_a.config &= ~DMAEN;
1435 tx_list_head->status.status_word = 0;
1436 if (tx_list_head->skb) {
1437 dev_kfree_skb(tx_list_head->skb);
1438 tx_list_head->skb = NULL;
1439 }
1440 tx_list_head = tx_list_head->next;
1441 }
1442
159945af
SZ		 1443 if (netif_queue_stopped(dev))
1444 netif_wake_queue(dev);
e190d6b1 1445
02460d08 1446 bfin_mac_enable(lp->phydev);
e190d6b1
BW		 1447
1448 /* We can accept TX packets again */
1ae5dc34 1449 dev->trans_start = jiffies; /* prevent tx timeout */
e190d6b1
BW		 1450}
1451
7ef0a7ee 1452static void bfin_mac_multicast_hash(struct net_device *dev)
775919bc
AW		 1453{
1454 u32 emac_hashhi, emac_hashlo;
22bedad3 1455 struct netdev_hw_addr *ha;
775919bc
AW		 1456 u32 crc;
1457
1458 emac_hashhi = emac_hashlo = 0;
1459
22bedad3 1460 netdev_for_each_mc_addr(ha, dev) {
f767b6df 1461 crc = ether_crc(ETH_ALEN, ha->addr);
775919bc
AW		 1462 crc >>= 26;
1463
1464 if (crc & 0x20)
1465 emac_hashhi |= 1 << (crc & 0x1f);
1466 else
1467 emac_hashlo |= 1 << (crc & 0x1f);
1468 }
1469
1470 bfin_write_EMAC_HASHHI(emac_hashhi);
1471 bfin_write_EMAC_HASHLO(emac_hashlo);
775919bc
AW		 1472}
1473
e190d6b1
BW		 1474/*
1475 * This routine will, depending on the values passed to it,
1476 * either make it accept multicast packets, go into
1477 * promiscuous mode (for TCPDUMP and cousins) or accept
1478 * a select set of multicast packets
1479 */
7ef0a7ee 1480static void bfin_mac_set_multicast_list(struct net_device *dev)
e190d6b1
BW		 1481{
1482 u32 sysctl;
1483
1484 if (dev->flags & IFF_PROMISC) {
c6dd5098 1485 netdev_info(dev, "set promisc mode\n");
e190d6b1 1486 sysctl = bfin_read_EMAC_OPMODE();
c0da776b 1487 sysctl |= PR;
e190d6b1 1488 bfin_write_EMAC_OPMODE(sysctl);
775919bc 1489 } else if (dev->flags & IFF_ALLMULTI) {
e190d6b1
BW		 1490 /* accept all multicast */
1491 sysctl = bfin_read_EMAC_OPMODE();
1492 sysctl |= PAM;
1493 bfin_write_EMAC_OPMODE(sysctl);
4cd24eaf 1494 } else if (!netdev_mc_empty(dev)) {
775919bc
AW		 1495 /* set up multicast hash table */
1496 sysctl = bfin_read_EMAC_OPMODE();
1497 sysctl |= HM;
1498 bfin_write_EMAC_OPMODE(sysctl);
7ef0a7ee 1499 bfin_mac_multicast_hash(dev);
e190d6b1
BW		 1500 } else {
1501 /* clear promisc or multicast mode */
1502 sysctl = bfin_read_EMAC_OPMODE();
1503 sysctl &= ~(RAF | PAM);
1504 bfin_write_EMAC_OPMODE(sysctl);
1505 }
1506}
1507
fe92afed
BS		 1508static int bfin_mac_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1509{
02460d08
SZ		 1510 struct bfin_mac_local *lp = netdev_priv(netdev);
1511
1512 if (!netif_running(netdev))
1513 return -EINVAL;
1514
fe92afed
BS		 1515 switch (cmd) {
1516 case SIOCSHWTSTAMP:
7575c917
BH		 1517 return bfin_mac_hwtstamp_set(netdev, ifr);
1518 case SIOCGHWTSTAMP:
1519 return bfin_mac_hwtstamp_get(netdev, ifr);
fe92afed 1520 default:
02460d08
SZ		 1521 if (lp->phydev)
1522 return phy_mii_ioctl(lp->phydev, ifr, cmd);
1523 else
1524 return -EOPNOTSUPP;
fe92afed
BS		 1525 }
1526}
1527
e190d6b1
BW		 1528/*
1529 * this puts the device in an inactive state
1530 */
7ef0a7ee 1531static void bfin_mac_shutdown(struct net_device *dev)
e190d6b1
BW		 1532{
1533 /* Turn off the EMAC */
1534 bfin_write_EMAC_OPMODE(0x00000000);
1535 /* Turn off the EMAC RX DMA */
1536 bfin_write_DMA1_CONFIG(0x0000);
1537 bfin_write_DMA2_CONFIG(0x0000);
1538}
1539
1540/*
1541 * Open and Initialize the interface
1542 *
1543 * Set up everything, reset the card, etc..
1544 */
7ef0a7ee 1545static int bfin_mac_open(struct net_device *dev)
e190d6b1 1546{
7ef0a7ee 1547 struct bfin_mac_local *lp = netdev_priv(dev);
2bfa0f0c 1548 int ret;
b39d66a8 1549 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1550
1551 /*
1552 * Check that the address is valid. If its not, refuse
1553 * to bring the device up. The user must specify an
1554 * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
1555 */
1556 if (!is_valid_ether_addr(dev->dev_addr)) {
c6dd5098 1557 netdev_warn(dev, "no valid ethernet hw addr\n");
e190d6b1
BW		 1558 return -EINVAL;
1559 }
1560
1561 /* initial rx and tx list */
1ab0d2ec 1562 ret = desc_list_init(dev);
2bfa0f0c
MF		 1563 if (ret)
1564 return ret;
e190d6b1 1565
4ae5a3ad 1566 phy_start(lp->phydev);
e190d6b1 1567 setup_system_regs(dev);
ee02fee8 1568 setup_mac_addr(dev->dev_addr);
2bfa0f0c 1569
7ef0a7ee 1570 bfin_mac_disable();
02460d08 1571 ret = bfin_mac_enable(lp->phydev);
2bfa0f0c
MF		 1572 if (ret)
1573 return ret;
e190d6b1 1574 pr_debug("hardware init finished\n");
2bfa0f0c 1575
159945af 1576 napi_enable(&lp->napi);
e190d6b1
BW		 1577 netif_start_queue(dev);
1578 netif_carrier_on(dev);
1579
1580 return 0;
1581}
1582
1583/*
e190d6b1
BW		 1584 * this makes the board clean up everything that it can
1585 * and not talk to the outside world. Caused by
1586 * an 'ifconfig ethX down'
1587 */
7ef0a7ee 1588static int bfin_mac_close(struct net_device *dev)
e190d6b1 1589{
7ef0a7ee 1590 struct bfin_mac_local *lp = netdev_priv(dev);
b39d66a8 1591 pr_debug("%s: %s\n", dev->name, __func__);
e190d6b1
BW		 1592
1593 netif_stop_queue(dev);
159945af 1594 napi_disable(&lp->napi);
e190d6b1
BW		 1595 netif_carrier_off(dev);
1596
4ae5a3ad 1597 phy_stop(lp->phydev);
136492b2 1598 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN);
4ae5a3ad 1599
e190d6b1 1600 /* clear everything */
7ef0a7ee 1601 bfin_mac_shutdown(dev);
e190d6b1
BW		 1602
1603 /* free the rx/tx buffers */
1604 desc_list_free();
1605
1606 return 0;
1607}
1608
b63dc8fe
MF		 1609static const struct net_device_ops bfin_mac_netdev_ops = {
1610 .ndo_open = bfin_mac_open,
1611 .ndo_stop = bfin_mac_close,
1612 .ndo_start_xmit = bfin_mac_hard_start_xmit,
1613 .ndo_set_mac_address = bfin_mac_set_mac_address,
1614 .ndo_tx_timeout = bfin_mac_timeout,
afc4b13d 1615 .ndo_set_rx_mode = bfin_mac_set_multicast_list,
fe92afed 1616 .ndo_do_ioctl = bfin_mac_ioctl,
b63dc8fe
MF		 1617 .ndo_validate_addr = eth_validate_addr,
1618 .ndo_change_mtu = eth_change_mtu,
1619#ifdef CONFIG_NET_POLL_CONTROLLER
159945af 1620 .ndo_poll_controller = bfin_mac_poll_controller,
b63dc8fe
MF		 1621#endif
1622};
1623
49f7315b 1624static int bfin_mac_probe(struct platform_device *pdev)
e190d6b1 1625{
7ef0a7ee
BW		 1626 struct net_device *ndev;
1627 struct bfin_mac_local *lp;
080c8255 1628 struct platform_device *pd;
02460d08 1629 struct bfin_mii_bus_platform_data *mii_bus_data;
080c8255 1630 int rc;
7ef0a7ee
BW		 1631
1632 ndev = alloc_etherdev(sizeof(struct bfin_mac_local));
41de8d4c 1633 if (!ndev)
7ef0a7ee 1634 return -ENOMEM;
7ef0a7ee
BW		 1635
1636 SET_NETDEV_DEV(ndev, &pdev->dev);
1637 platform_set_drvdata(pdev, ndev);
1638 lp = netdev_priv(ndev);
4fcc3d34 1639 lp->ndev = ndev;
e190d6b1
BW		 1640
1641 /* Grab the MAC address in the MAC */
7ef0a7ee
BW		 1642 *(__le32 *) (&(ndev->dev_addr[0])) = cpu_to_le32(bfin_read_EMAC_ADDRLO());
1643 *(__le16 *) (&(ndev->dev_addr[4])) = cpu_to_le16((u16) bfin_read_EMAC_ADDRHI());
e190d6b1
BW		 1644
1645 /* probe mac */
1646 /*todo: how to proble? which is revision_register */
1647 bfin_write_EMAC_ADDRLO(0x12345678);
1648 if (bfin_read_EMAC_ADDRLO() != 0x12345678) {
7ef0a7ee
BW		 1649 dev_err(&pdev->dev, "Cannot detect Blackfin on-chip ethernet MAC controller!\n");
1650 rc = -ENODEV;
1651 goto out_err_probe_mac;
e190d6b1
BW		 1652 }
1653
e190d6b1 1654
7ef0a7ee
BW		 1655 /*
1656 * Is it valid? (Did bootloader initialize it?)
1657 * Grab the MAC from the board somehow
1658 * this is done in the arch/blackfin/mach-bfxxx/boards/eth_mac.c
1659 */
5055d2f2
DK		 1660 if (!is_valid_ether_addr(ndev->dev_addr)) {
1661 if (bfin_get_ether_addr(ndev->dev_addr) ||
1662 !is_valid_ether_addr(ndev->dev_addr)) {
1663 /* Still not valid, get a random one */
1664 netdev_warn(ndev, "Setting Ethernet MAC to a random one\n");
1665 eth_hw_addr_random(ndev);
1666 }
1667 }
e190d6b1 1668
7ef0a7ee 1669 setup_mac_addr(ndev->dev_addr);
e190d6b1 1670
a63b82c4 1671 if (!dev_get_platdata(&pdev->dev)) {
080c8255
GY		 1672 dev_err(&pdev->dev, "Cannot get platform device bfin_mii_bus!\n");
1673 rc = -ENODEV;
1674 goto out_err_probe_mac;
7ef0a7ee 1675 }
a63b82c4 1676 pd = dev_get_platdata(&pdev->dev);
080c8255 1677 lp->mii_bus = platform_get_drvdata(pd);
0e995cd3
SZ		 1678 if (!lp->mii_bus) {
1679 dev_err(&pdev->dev, "Cannot get mii_bus!\n");
1680 rc = -ENODEV;
02460d08 1681 goto out_err_probe_mac;
0e995cd3 1682 }
080c8255 1683 lp->mii_bus->priv = ndev;
a63b82c4 1684 mii_bus_data = dev_get_platdata(&pd->dev);
4ae5a3ad 1685
02460d08 1686 rc = mii_probe(ndev, mii_bus_data->phy_mode);
7ef0a7ee
BW		 1687 if (rc) {
1688 dev_err(&pdev->dev, "MII Probe failed!\n");
1689 goto out_err_mii_probe;
1690 }
4ae5a3ad 1691
c599bd6b
MF		 1692 lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
1693 lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
1694
149da651 1695 ndev->netdev_ops = &bfin_mac_netdev_ops;
679dce39 1696 ndev->ethtool_ops = &bfin_mac_ethtool_ops;
e190d6b1 1697
4fcc3d34
SZ		 1698 init_timer(&lp->tx_reclaim_timer);
1699 lp->tx_reclaim_timer.data = (unsigned long)lp;
1700 lp->tx_reclaim_timer.function = tx_reclaim_skb_timeout;
1701
159945af
SZ		 1702 lp->flags = 0;
1703 netif_napi_add(ndev, &lp->napi, bfin_mac_poll, CONFIG_BFIN_RX_DESC_NUM);
1704
e190d6b1
BW		 1705 spin_lock_init(&lp->lock);
1706
1707 /* now, enable interrupts */
1708 /* register irq handler */
7ef0a7ee 1709 rc = request_irq(IRQ_MAC_RX, bfin_mac_interrupt,
63aca0f7 1710 0, "EMAC_RX", ndev);
7ef0a7ee
BW		 1711 if (rc) {
1712 dev_err(&pdev->dev, "Cannot request Blackfin MAC RX IRQ!\n");
1713 rc = -EBUSY;
1714 goto out_err_request_irq;
e190d6b1
BW		 1715 }
1716
7ef0a7ee
BW		 1717 rc = register_netdev(ndev);
1718 if (rc) {
1719 dev_err(&pdev->dev, "Cannot register net device!\n");
1720 goto out_err_reg_ndev;
e190d6b1
BW		 1721 }
1722
fe92afed 1723 bfin_mac_hwtstamp_init(ndev);
2c006994
WY		 1724 rc = bfin_phc_init(ndev, &pdev->dev);
1725 if (rc) {
dd87b22f
RC		 1726 dev_err(&pdev->dev, "Cannot register PHC device!\n");
1727 goto out_err_phc;
1728 }
fe92afed 1729
7ef0a7ee 1730 /* now, print out the card info, in a short format.. */
c6dd5098 1731 netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
e190d6b1 1732
7ef0a7ee 1733 return 0;
e190d6b1 1734
dd87b22f 1735out_err_phc:
7ef0a7ee
BW		 1736out_err_reg_ndev:
1737 free_irq(IRQ_MAC_RX, ndev);
1738out_err_request_irq:
159945af 1739 netif_napi_del(&lp->napi);
7ef0a7ee 1740out_err_mii_probe:
298cf9be 1741 mdiobus_unregister(lp->mii_bus);
298cf9be 1742 mdiobus_free(lp->mii_bus);
7ef0a7ee 1743out_err_probe_mac:
7ef0a7ee 1744 free_netdev(ndev);
e190d6b1 1745
7ef0a7ee 1746 return rc;
e190d6b1
BW		 1747}
1748
49f7315b 1749static int bfin_mac_remove(struct platform_device *pdev)
e190d6b1
BW		 1750{
1751 struct net_device *ndev = platform_get_drvdata(pdev);
7ef0a7ee 1752 struct bfin_mac_local *lp = netdev_priv(ndev);
e190d6b1 1753
dd87b22f
RC		 1754 bfin_phc_release(lp);
1755
080c8255 1756 lp->mii_bus->priv = NULL;
7ef0a7ee 1757
e190d6b1
BW		 1758 unregister_netdev(ndev);
1759
159945af
SZ		 1760 netif_napi_del(&lp->napi);
1761
e190d6b1
BW		 1762 free_irq(IRQ_MAC_RX, ndev);
1763
1764 free_netdev(ndev);
1765
e190d6b1
BW		 1766 return 0;
1767}
1768
496a34c2
BW		 1769#ifdef CONFIG_PM
1770static int bfin_mac_suspend(struct platform_device *pdev, pm_message_t mesg)
e190d6b1 1771{
496a34c2 1772 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1773 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1774
53fd3f28
MH		 1775 if (lp->wol) {
1776 bfin_write_EMAC_OPMODE((bfin_read_EMAC_OPMODE() & ~TE) | RE);
1777 bfin_write_EMAC_WKUP_CTL(MPKE);
1778 enable_irq_wake(IRQ_MAC_WAKEDET);
1779 } else {
1780 if (netif_running(net_dev))
1781 bfin_mac_close(net_dev);
1782 }
496a34c2 1783
e190d6b1
BW		 1784 return 0;
1785}
1786
1787static int bfin_mac_resume(struct platform_device *pdev)
1788{
496a34c2 1789 struct net_device *net_dev = platform_get_drvdata(pdev);
53fd3f28 1790 struct bfin_mac_local *lp = netdev_priv(net_dev);
496a34c2 1791
53fd3f28
MH		 1792 if (lp->wol) {
1793 bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
1794 bfin_write_EMAC_WKUP_CTL(0);
1795 disable_irq_wake(IRQ_MAC_WAKEDET);
1796 } else {
1797 if (netif_running(net_dev))
1798 bfin_mac_open(net_dev);
1799 }
496a34c2 1800
e190d6b1
BW		 1801 return 0;
1802}
496a34c2
BW		 1803#else
1804#define bfin_mac_suspend NULL
1805#define bfin_mac_resume NULL
1806#endif /* CONFIG_PM */
e190d6b1 1807
49f7315b 1808static int bfin_mii_bus_probe(struct platform_device *pdev)
080c8255
GY		 1809{
1810 struct mii_bus *miibus;
02460d08
SZ		 1811 struct bfin_mii_bus_platform_data *mii_bus_pd;
1812 const unsigned short *pin_req;
080c8255
GY		 1813 int rc, i;
1814
02460d08
SZ		 1815 mii_bus_pd = dev_get_platdata(&pdev->dev);
1816 if (!mii_bus_pd) {
1817 dev_err(&pdev->dev, "No peripherals in platform data!\n");
1818 return -EINVAL;
1819 }
1820
080c8255
GY		 1821 /*
1822 * We are setting up a network card,
1823 * so set the GPIO pins to Ethernet mode
1824 */
02460d08 1825 pin_req = mii_bus_pd->mac_peripherals;
c6dd5098 1826 rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
080c8255
GY		 1827 if (rc) {
1828 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
1829 return rc;
1830 }
1831
1832 rc = -ENOMEM;
1833 miibus = mdiobus_alloc();
1834 if (miibus == NULL)
1835 goto out_err_alloc;
1836 miibus->read = bfin_mdiobus_read;
1837 miibus->write = bfin_mdiobus_write;
080c8255
GY		 1838
1839 miibus->parent = &pdev->dev;
1840 miibus->name = "bfin_mii_bus";
02460d08
SZ		 1841 miibus->phy_mask = mii_bus_pd->phy_mask;
1842
75432fd2
FF		 1843 snprintf(miibus->id, MII_BUS_ID_SIZE, "%s-%x",
1844 pdev->name, pdev->id);
080c8255 1845 miibus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
02460d08
SZ		 1846 if (!miibus->irq)
1847 goto out_err_irq_alloc;
1848
1849 for (i = rc; i < PHY_MAX_ADDR; ++i)
080c8255
GY		 1850 miibus->irq[i] = PHY_POLL;
1851
02460d08
SZ		 1852 rc = clamp(mii_bus_pd->phydev_number, 0, PHY_MAX_ADDR);
1853 if (rc != mii_bus_pd->phydev_number)
1854 dev_err(&pdev->dev, "Invalid number (%i) of phydevs\n",
1855 mii_bus_pd->phydev_number);
1856 for (i = 0; i < rc; ++i) {
1857 unsigned short phyaddr = mii_bus_pd->phydev_data[i].addr;
1858 if (phyaddr < PHY_MAX_ADDR)
1859 miibus->irq[phyaddr] = mii_bus_pd->phydev_data[i].irq;
1860 else
1861 dev_err(&pdev->dev,
1862 "Invalid PHY address %i for phydev %i\n",
1863 phyaddr, i);
1864 }
1865
080c8255
GY		 1866 rc = mdiobus_register(miibus);
1867 if (rc) {
1868 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1869 goto out_err_mdiobus_register;
1870 }
1871
1872 platform_set_drvdata(pdev, miibus);
1873 return 0;
1874
1875out_err_mdiobus_register:
7f267de4 1876 kfree(miibus->irq);
02460d08 1877out_err_irq_alloc:
080c8255
GY		 1878 mdiobus_free(miibus);
1879out_err_alloc:
1880 peripheral_free_list(pin_req);
1881
1882 return rc;
1883}
1884
49f7315b 1885static int bfin_mii_bus_remove(struct platform_device *pdev)
080c8255
GY		 1886{
1887 struct mii_bus *miibus = platform_get_drvdata(pdev);
02460d08
SZ		 1888 struct bfin_mii_bus_platform_data *mii_bus_pd =
1889 dev_get_platdata(&pdev->dev);
1890
080c8255 1891 mdiobus_unregister(miibus);
7f267de4 1892 kfree(miibus->irq);
080c8255 1893 mdiobus_free(miibus);
02460d08
SZ		 1894 peripheral_free_list(mii_bus_pd->mac_peripherals);
1895
080c8255
GY		 1896 return 0;
1897}
1898
1899static struct platform_driver bfin_mii_bus_driver = {
1900 .probe = bfin_mii_bus_probe,
49f7315b 1901 .remove = bfin_mii_bus_remove,
080c8255
GY		 1902 .driver = {
1903 .name = "bfin_mii_bus",
080c8255
GY		 1904 },
1905};
1906
e190d6b1
BW		 1907static struct platform_driver bfin_mac_driver = {
1908 .probe = bfin_mac_probe,
49f7315b 1909 .remove = bfin_mac_remove,
e190d6b1
BW		 1910 .resume = bfin_mac_resume,
1911 .suspend = bfin_mac_suspend,
1912 .driver = {
c6dd5098 1913 .name = KBUILD_MODNAME,
72abb461 1914 },
e190d6b1
BW		 1915};
1916
1917static int __init bfin_mac_init(void)
1918{
080c8255
GY		 1919 int ret;
1920 ret = platform_driver_register(&bfin_mii_bus_driver);
1921 if (!ret)
1922 return platform_driver_register(&bfin_mac_driver);
1923 return -ENODEV;
e190d6b1
BW		 1924}
1925
1926module_init(bfin_mac_init);
1927
1928static void __exit bfin_mac_cleanup(void)
1929{
1930 platform_driver_unregister(&bfin_mac_driver);
080c8255 1931 platform_driver_unregister(&bfin_mii_bus_driver);
e190d6b1
BW		 1932}
1933
1934module_exit(bfin_mac_cleanup);
72abb461 1935
Linux kernel - Deliverables
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