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net: vlan: rename NETIF_F_HW_VLAN_* feature flags to NETIF_F_HW_VLAN_CTAG_*
[deliverable/linux.git] / drivers / net / ethernet / alteon / acenic.c
CommitLineData
1da177e4
LT		 1/*
2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
3 * and other Tigon based cards.
4 *
5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
6 *
7 * Thanks to Alteon and 3Com for providing hardware and documentation
8 * enabling me to write this driver.
9 *
10 * A mailing list for discussing the use of this driver has been
11 * setup, please subscribe to the lists if you have any questions
12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
13 * see how to subscribe.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * Additional credits:
21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
22 * dump support. The trace dump support has not been
23 * integrated yet however.
24 * Troy Benjegerdes: Big Endian (PPC) patches.
25 * Nate Stahl: Better out of memory handling and stats support.
26 * Aman Singla: Nasty race between interrupt handler and tx code dealing
27 * with 'testing the tx_ret_csm and setting tx_full'
28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
29 * infrastructure and Sparc support
30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
31 * driver under Linux/Sparc64
32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
33 * ETHTOOL_GDRVINFO support
34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
35 * handler and close() cleanup.
36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
37 * memory mapped IO is enabled to
38 * make the driver work on RS/6000.
39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
40 * where the driver would disable
41 * bus master mode if it had to disable
42 * write and invalidate.
43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
44 * endian systems.
45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and
46 * rx producer index when
47 * flushing the Jumbo ring.
48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the
49 * driver init path.
50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
51 */
52
1da177e4
LT		 53#include <linux/module.h>
54#include <linux/moduleparam.h>
1da177e4
LT		 55#include <linux/types.h>
56#include <linux/errno.h>
57#include <linux/ioport.h>
58#include <linux/pci.h>
1e7f0bd8 59#include <linux/dma-mapping.h>
1da177e4
LT		 60#include <linux/kernel.h>
61#include <linux/netdevice.h>
62#include <linux/etherdevice.h>
63#include <linux/skbuff.h>
64#include <linux/init.h>
65#include <linux/delay.h>
66#include <linux/mm.h>
67#include <linux/highmem.h>
68#include <linux/sockios.h>
949b4254 69#include <linux/firmware.h>
5a0e3ad6 70#include <linux/slab.h>
268bb0ce 71#include <linux/prefetch.h>
1da177e4 72#include <linux/if_vlan.h>
1da177e4
LT		 73
74#ifdef SIOCETHTOOL
75#include <linux/ethtool.h>
76#endif
77
78#include <net/sock.h>
79#include <net/ip.h>
80
1da177e4
LT		 81#include <asm/io.h>
82#include <asm/irq.h>
83#include <asm/byteorder.h>
84#include <asm/uaccess.h>
85
86
87#define DRV_NAME "acenic"
88
89#undef INDEX_DEBUG
90
91#ifdef CONFIG_ACENIC_OMIT_TIGON_I
92#define ACE_IS_TIGON_I(ap) 0
93#define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES
94#else
95#define ACE_IS_TIGON_I(ap) (ap->version == 1)
96#define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries
97#endif
98
99#ifndef PCI_VENDOR_ID_ALTEON
6aa20a22 100#define PCI_VENDOR_ID_ALTEON 0x12ae
1da177e4
LT		 101#endif
102#ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
103#define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001
104#define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
105#endif
106#ifndef PCI_DEVICE_ID_3COM_3C985
107#define PCI_DEVICE_ID_3COM_3C985 0x0001
108#endif
109#ifndef PCI_VENDOR_ID_NETGEAR
110#define PCI_VENDOR_ID_NETGEAR 0x1385
111#define PCI_DEVICE_ID_NETGEAR_GA620 0x620a
112#endif
113#ifndef PCI_DEVICE_ID_NETGEAR_GA620T
114#define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a
115#endif
116
117
118/*
119 * Farallon used the DEC vendor ID by mistake and they seem not
120 * to care - stinky!
121 */
122#ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
123#define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a
124#endif
125#ifndef PCI_DEVICE_ID_FARALLON_PN9100T
126#define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa
127#endif
128#ifndef PCI_VENDOR_ID_SGI
129#define PCI_VENDOR_ID_SGI 0x10a9
130#endif
131#ifndef PCI_DEVICE_ID_SGI_ACENIC
132#define PCI_DEVICE_ID_SGI_ACENIC 0x0009
133#endif
134
a3aa1884 135static DEFINE_PCI_DEVICE_TABLE(acenic_pci_tbl) = {
1da177e4
LT		 136 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
137 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
140 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
142 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
146 /*
147 * Farallon used the DEC vendor ID on their cards incorrectly,
148 * then later Alteon's ID.
149 */
150 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
151 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
152 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
154 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
156 { }
157};
158MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
159
1da177e4 160#define ace_sync_irq(irq) synchronize_irq(irq)
1da177e4
LT		 161
162#ifndef offset_in_page
163#define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK)
164#endif
165
166#define ACE_MAX_MOD_PARMS 8
167#define BOARD_IDX_STATIC 0
168#define BOARD_IDX_OVERFLOW -1
169
1da177e4
LT		 170#include "acenic.h"
171
172/*
173 * These must be defined before the firmware is included.
174 */
175#define MAX_TEXT_LEN 96*1024
176#define MAX_RODATA_LEN 8*1024
177#define MAX_DATA_LEN 2*1024
178
1da177e4
LT		 179#ifndef tigon2FwReleaseLocal
180#define tigon2FwReleaseLocal 0
181#endif
182
183/*
184 * This driver currently supports Tigon I and Tigon II based cards
185 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
186 * GA620. The driver should also work on the SGI, DEC and Farallon
187 * versions of the card, however I have not been able to test that
188 * myself.
189 *
190 * This card is really neat, it supports receive hardware checksumming
191 * and jumbo frames (up to 9000 bytes) and does a lot of work in the
192 * firmware. Also the programming interface is quite neat, except for
193 * the parts dealing with the i2c eeprom on the card ;-)
194 *
195 * Using jumbo frames:
196 *
197 * To enable jumbo frames, simply specify an mtu between 1500 and 9000
198 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
199 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
200 * interface number and <MTU> being the MTU value.
201 *
202 * Module parameters:
203 *
204 * When compiled as a loadable module, the driver allows for a number
205 * of module parameters to be specified. The driver supports the
206 * following module parameters:
207 *
208 * trace=<val> - Firmware trace level. This requires special traced
209 * firmware to replace the firmware supplied with
210 * the driver - for debugging purposes only.
211 *
212 * link=<val> - Link state. Normally you want to use the default link
213 * parameters set by the driver. This can be used to
214 * override these in case your switch doesn't negotiate
215 * the link properly. Valid values are:
216 * 0x0001 - Force half duplex link.
217 * 0x0002 - Do not negotiate line speed with the other end.
218 * 0x0010 - 10Mbit/sec link.
219 * 0x0020 - 100Mbit/sec link.
220 * 0x0040 - 1000Mbit/sec link.
221 * 0x0100 - Do not negotiate flow control.
222 * 0x0200 - Enable RX flow control Y
223 * 0x0400 - Enable TX flow control Y (Tigon II NICs only).
224 * Default value is 0x0270, ie. enable link+flow
225 * control negotiation. Negotiating the highest
226 * possible link speed with RX flow control enabled.
227 *
228 * When disabling link speed negotiation, only one link
229 * speed is allowed to be specified!
230 *
231 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
232 * to wait for more packets to arive before
233 * interrupting the host, from the time the first
234 * packet arrives.
235 *
236 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
237 * to wait for more packets to arive in the transmit ring,
238 * before interrupting the host, after transmitting the
239 * first packet in the ring.
240 *
241 * max_tx_desc=<val> - maximum number of transmit descriptors
242 * (packets) transmitted before interrupting the host.
243 *
244 * max_rx_desc=<val> - maximum number of receive descriptors
245 * (packets) received before interrupting the host.
246 *
247 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
248 * increments of the NIC's on board memory to be used for
249 * transmit and receive buffers. For the 1MB NIC app. 800KB
250 * is available, on the 1/2MB NIC app. 300KB is available.
251 * 68KB will always be available as a minimum for both
252 * directions. The default value is a 50/50 split.
253 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
254 * operations, default (1) is to always disable this as
255 * that is what Alteon does on NT. I have not been able
256 * to measure any real performance differences with
257 * this on my systems. Set <val>=0 if you want to
258 * enable these operations.
259 *
260 * If you use more than one NIC, specify the parameters for the
261 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
262 * run tracing on NIC #2 but not on NIC #1 and #3.
263 *
264 * TODO:
265 *
266 * - Proper multicast support.
267 * - NIC dump support.
268 * - More tuning parameters.
269 *
270 * The mini ring is not used under Linux and I am not sure it makes sense
271 * to actually use it.
272 *
273 * New interrupt handler strategy:
274 *
275 * The old interrupt handler worked using the traditional method of
276 * replacing an skbuff with a new one when a packet arrives. However
277 * the rx rings do not need to contain a static number of buffer
278 * descriptors, thus it makes sense to move the memory allocation out
279 * of the main interrupt handler and do it in a bottom half handler
280 * and only allocate new buffers when the number of buffers in the
281 * ring is below a certain threshold. In order to avoid starving the
282 * NIC under heavy load it is however necessary to force allocation
283 * when hitting a minimum threshold. The strategy for alloction is as
284 * follows:
285 *
286 * RX_LOW_BUF_THRES - allocate buffers in the bottom half
287 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
288 * the buffers in the interrupt handler
289 * RX_RING_THRES - maximum number of buffers in the rx ring
290 * RX_MINI_THRES - maximum number of buffers in the mini ring
291 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring
292 *
293 * One advantagous side effect of this allocation approach is that the
294 * entire rx processing can be done without holding any spin lock
295 * since the rx rings and registers are totally independent of the tx
296 * ring and its registers. This of course includes the kmalloc's of
297 * new skb's. Thus start_xmit can run in parallel with rx processing
298 * and the memory allocation on SMP systems.
299 *
300 * Note that running the skb reallocation in a bottom half opens up
301 * another can of races which needs to be handled properly. In
302 * particular it can happen that the interrupt handler tries to run
303 * the reallocation while the bottom half is either running on another
304 * CPU or was interrupted on the same CPU. To get around this the
305 * driver uses bitops to prevent the reallocation routines from being
306 * reentered.
307 *
308 * TX handling can also be done without holding any spin lock, wheee
309 * this is fun! since tx_ret_csm is only written to by the interrupt
310 * handler. The case to be aware of is when shutting down the device
311 * and cleaning up where it is necessary to make sure that
312 * start_xmit() is not running while this is happening. Well DaveM
313 * informs me that this case is already protected against ... bye bye
314 * Mr. Spin Lock, it was nice to know you.
315 *
316 * TX interrupts are now partly disabled so the NIC will only generate
317 * TX interrupts for the number of coal ticks, not for the number of
318 * TX packets in the queue. This should reduce the number of TX only,
319 * ie. when no RX processing is done, interrupts seen.
320 */
321
322/*
323 * Threshold values for RX buffer allocation - the low water marks for
324 * when to start refilling the rings are set to 75% of the ring
325 * sizes. It seems to make sense to refill the rings entirely from the
326 * intrrupt handler once it gets below the panic threshold, that way
327 * we don't risk that the refilling is moved to another CPU when the
328 * one running the interrupt handler just got the slab code hot in its
329 * cache.
330 */
331#define RX_RING_SIZE 72
332#define RX_MINI_SIZE 64
333#define RX_JUMBO_SIZE 48
334
335#define RX_PANIC_STD_THRES 16
336#define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2
337#define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4
338#define RX_PANIC_MINI_THRES 12
339#define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2
340#define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4
341#define RX_PANIC_JUMBO_THRES 6
342#define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2
343#define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4
344
345
346/*
347 * Size of the mini ring entries, basically these just should be big
348 * enough to take TCP ACKs
349 */
350#define ACE_MINI_SIZE 100
351
352#define ACE_MINI_BUFSIZE ACE_MINI_SIZE
353#define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4)
354#define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4)
355
356/*
357 * There seems to be a magic difference in the effect between 995 and 996
358 * but little difference between 900 and 995 ... no idea why.
359 *
360 * There is now a default set of tuning parameters which is set, depending
361 * on whether or not the user enables Jumbo frames. It's assumed that if
362 * Jumbo frames are enabled, the user wants optimal tuning for that case.
363 */
364#define DEF_TX_COAL 400 /* 996 */
365#define DEF_TX_MAX_DESC 60 /* was 40 */
366#define DEF_RX_COAL 120 /* 1000 */
367#define DEF_RX_MAX_DESC 25
368#define DEF_TX_RATIO 21 /* 24 */
369
370#define DEF_JUMBO_TX_COAL 20
371#define DEF_JUMBO_TX_MAX_DESC 60
372#define DEF_JUMBO_RX_COAL 30
373#define DEF_JUMBO_RX_MAX_DESC 6
374#define DEF_JUMBO_TX_RATIO 21
375
376#if tigon2FwReleaseLocal < 20001118
377/*
378 * Standard firmware and early modifications duplicate
379 * IRQ load without this flag (coal timer is never reset).
380 * Note that with this flag tx_coal should be less than
381 * time to xmit full tx ring.
382 * 400usec is not so bad for tx ring size of 128.
383 */
384#define TX_COAL_INTS_ONLY 1 /* worth it */
385#else
386/*
387 * With modified firmware, this is not necessary, but still useful.
388 */
389#define TX_COAL_INTS_ONLY 1
390#endif
391
392#define DEF_TRACE 0
393#define DEF_STAT (2 * TICKS_PER_SEC)
394
395
ddfce6bb 396static int link_state[ACE_MAX_MOD_PARMS];
1da177e4
LT		 397static int trace[ACE_MAX_MOD_PARMS];
398static int tx_coal_tick[ACE_MAX_MOD_PARMS];
399static int rx_coal_tick[ACE_MAX_MOD_PARMS];
400static int max_tx_desc[ACE_MAX_MOD_PARMS];
401static int max_rx_desc[ACE_MAX_MOD_PARMS];
402static int tx_ratio[ACE_MAX_MOD_PARMS];
403static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
404
405MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
406MODULE_LICENSE("GPL");
407MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
949b4254
JS		 408#ifndef CONFIG_ACENIC_OMIT_TIGON_I
409MODULE_FIRMWARE("acenic/tg1.bin");
410#endif
411MODULE_FIRMWARE("acenic/tg2.bin");
1da177e4 412
ddfce6bb 413module_param_array_named(link, link_state, int, NULL, 0);
1da177e4
LT		 414module_param_array(trace, int, NULL, 0);
415module_param_array(tx_coal_tick, int, NULL, 0);
416module_param_array(max_tx_desc, int, NULL, 0);
417module_param_array(rx_coal_tick, int, NULL, 0);
418module_param_array(max_rx_desc, int, NULL, 0);
419module_param_array(tx_ratio, int, NULL, 0);
420MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
421MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
422MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
423MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
424MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
425MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
426MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
427
428
083abbb7 429static const char version[] =
1da177e4
LT		 430 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n"
431 " http://home.cern.ch/~jes/gige/acenic.html\n";
432
433static int ace_get_settings(struct net_device *, struct ethtool_cmd *);
434static int ace_set_settings(struct net_device *, struct ethtool_cmd *);
435static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
436
7282d491 437static const struct ethtool_ops ace_ethtool_ops = {
1da177e4
LT		 438 .get_settings = ace_get_settings,
439 .set_settings = ace_set_settings,
440 .get_drvinfo = ace_get_drvinfo,
441};
442
443static void ace_watchdog(struct net_device *dev);
444
d8b83c57
SH		 445static const struct net_device_ops ace_netdev_ops = {
446 .ndo_open = ace_open,
447 .ndo_stop = ace_close,
448 .ndo_tx_timeout = ace_watchdog,
449 .ndo_get_stats = ace_get_stats,
00829823 450 .ndo_start_xmit = ace_start_xmit,
afc4b13d 451 .ndo_set_rx_mode = ace_set_multicast_list,
52255bbe 452 .ndo_validate_addr = eth_validate_addr,
d8b83c57
SH		 453 .ndo_set_mac_address = ace_set_mac_addr,
454 .ndo_change_mtu = ace_change_mtu,
d8b83c57
SH		 455};
456
083abbb7 457static int acenic_probe_one(struct pci_dev *pdev,
1dd06ae8 458 const struct pci_device_id *id)
1da177e4
LT		 459{
460 struct net_device *dev;
461 struct ace_private *ap;
462 static int boards_found;
463
464 dev = alloc_etherdev(sizeof(struct ace_private));
41de8d4c 465 if (dev == NULL)
1da177e4 466 return -ENOMEM;
1da177e4 467
1da177e4
LT		 468 SET_NETDEV_DEV(dev, &pdev->dev);
469
454d7c9b 470 ap = netdev_priv(dev);
1da177e4
LT		 471 ap->pdev = pdev;
472 ap->name = pci_name(pdev);
473
474 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f646968f 475 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
25805dcf 476
25805dcf 477 dev->watchdog_timeo = 5*HZ;
1da177e4 478
d8b83c57 479 dev->netdev_ops = &ace_netdev_ops;
1da177e4 480 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops);
1da177e4
LT		 481
482 /* we only display this string ONCE */
483 if (!boards_found)
484 printk(version);
485
486 if (pci_enable_device(pdev))
487 goto fail_free_netdev;
488
489 /*
490 * Enable master mode before we start playing with the
491 * pci_command word since pci_set_master() will modify
492 * it.
493 */
494 pci_set_master(pdev);
495
496 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
497
6aa20a22 498 /* OpenFirmware on Mac's does not set this - DOH.. */
1da177e4
LT		 499 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
500 printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
501 "access - was not enabled by BIOS/Firmware\n",
502 ap->name);
503 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
504 pci_write_config_word(ap->pdev, PCI_COMMAND,
505 ap->pci_command);
506 wmb();
507 }
508
509 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
510 if (ap->pci_latency <= 0x40) {
511 ap->pci_latency = 0x40;
512 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
513 }
514
515 /*
516 * Remap the regs into kernel space - this is abuse of
517 * dev->base_addr since it was means for I/O port
518 * addresses but who gives a damn.
519 */
520 dev->base_addr = pci_resource_start(pdev, 0);
521 ap->regs = ioremap(dev->base_addr, 0x4000);
522 if (!ap->regs) {
523 printk(KERN_ERR "%s: Unable to map I/O register, "
524 "AceNIC %i will be disabled.\n",
525 ap->name, boards_found);
526 goto fail_free_netdev;
527 }
528
529 switch(pdev->vendor) {
530 case PCI_VENDOR_ID_ALTEON:
531 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
532 printk(KERN_INFO "%s: Farallon PN9100-T ",
533 ap->name);
534 } else {
535 printk(KERN_INFO "%s: Alteon AceNIC ",
536 ap->name);
537 }
538 break;
539 case PCI_VENDOR_ID_3COM:
540 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
541 break;
542 case PCI_VENDOR_ID_NETGEAR:
543 printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
544 break;
545 case PCI_VENDOR_ID_DEC:
546 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
547 printk(KERN_INFO "%s: Farallon PN9000-SX ",
548 ap->name);
549 break;
550 }
551 case PCI_VENDOR_ID_SGI:
552 printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
553 break;
554 default:
555 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
556 break;
557 }
558
559 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
c6387a48 560 printk("irq %d\n", pdev->irq);
1da177e4
LT		 561
562#ifdef CONFIG_ACENIC_OMIT_TIGON_I
563 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
564 printk(KERN_ERR "%s: Driver compiled without Tigon I"
565 " support - NIC disabled\n", dev->name);
566 goto fail_uninit;
567 }
568#endif
569
570 if (ace_allocate_descriptors(dev))
571 goto fail_free_netdev;
572
573#ifdef MODULE
574 if (boards_found >= ACE_MAX_MOD_PARMS)
575 ap->board_idx = BOARD_IDX_OVERFLOW;
576 else
577 ap->board_idx = boards_found;
578#else
579 ap->board_idx = BOARD_IDX_STATIC;
580#endif
581
582 if (ace_init(dev))
583 goto fail_free_netdev;
584
585 if (register_netdev(dev)) {
586 printk(KERN_ERR "acenic: device registration failed\n");
587 goto fail_uninit;
588 }
589 ap->name = dev->name;
590
591 if (ap->pci_using_dac)
592 dev->features |= NETIF_F_HIGHDMA;
593
594 pci_set_drvdata(pdev, dev);
595
596 boards_found++;
597 return 0;
598
599 fail_uninit:
600 ace_init_cleanup(dev);
601 fail_free_netdev:
602 free_netdev(dev);
603 return -ENODEV;
604}
605
083abbb7 606static void acenic_remove_one(struct pci_dev *pdev)
1da177e4
LT		 607{
608 struct net_device *dev = pci_get_drvdata(pdev);
609 struct ace_private *ap = netdev_priv(dev);
610 struct ace_regs __iomem *regs = ap->regs;
611 short i;
612
613 unregister_netdev(dev);
614
615 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
616 if (ap->version >= 2)
617 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
6aa20a22 618
1da177e4
LT		 619 /*
620 * This clears any pending interrupts
621 */
622 writel(1, &regs->Mb0Lo);
623 readl(&regs->CpuCtrl); /* flush */
624
625 /*
626 * Make sure no other CPUs are processing interrupts
627 * on the card before the buffers are being released.
628 * Otherwise one might experience some `interesting'
629 * effects.
630 *
631 * Then release the RX buffers - jumbo buffers were
632 * already released in ace_close().
633 */
634 ace_sync_irq(dev->irq);
635
636 for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
637 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
638
639 if (skb) {
640 struct ring_info *ringp;
641 dma_addr_t mapping;
642
643 ringp = &ap->skb->rx_std_skbuff[i];
430e55b1 644 mapping = dma_unmap_addr(ringp, mapping);
1da177e4
LT		 645 pci_unmap_page(ap->pdev, mapping,
646 ACE_STD_BUFSIZE,
647 PCI_DMA_FROMDEVICE);
648
649 ap->rx_std_ring[i].size = 0;
650 ap->skb->rx_std_skbuff[i].skb = NULL;
651 dev_kfree_skb(skb);
652 }
653 }
654
655 if (ap->version >= 2) {
656 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
657 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
658
659 if (skb) {
660 struct ring_info *ringp;
661 dma_addr_t mapping;
662
663 ringp = &ap->skb->rx_mini_skbuff[i];
430e55b1 664 mapping = dma_unmap_addr(ringp,mapping);
1da177e4
LT		 665 pci_unmap_page(ap->pdev, mapping,
666 ACE_MINI_BUFSIZE,
667 PCI_DMA_FROMDEVICE);
668
669 ap->rx_mini_ring[i].size = 0;
670 ap->skb->rx_mini_skbuff[i].skb = NULL;
671 dev_kfree_skb(skb);
672 }
673 }
674 }
675
676 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
677 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
678 if (skb) {
679 struct ring_info *ringp;
680 dma_addr_t mapping;
681
682 ringp = &ap->skb->rx_jumbo_skbuff[i];
430e55b1 683 mapping = dma_unmap_addr(ringp, mapping);
1da177e4
LT		 684 pci_unmap_page(ap->pdev, mapping,
685 ACE_JUMBO_BUFSIZE,
686 PCI_DMA_FROMDEVICE);
687
688 ap->rx_jumbo_ring[i].size = 0;
689 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
690 dev_kfree_skb(skb);
691 }
692 }
693
694 ace_init_cleanup(dev);
695 free_netdev(dev);
696}
697
698static struct pci_driver acenic_pci_driver = {
699 .name = "acenic",
700 .id_table = acenic_pci_tbl,
701 .probe = acenic_probe_one,
083abbb7 702 .remove = acenic_remove_one,
1da177e4
LT		 703};
704
705static int __init acenic_init(void)
706{
29917620 707 return pci_register_driver(&acenic_pci_driver);
1da177e4
LT		 708}
709
710static void __exit acenic_exit(void)
711{
712 pci_unregister_driver(&acenic_pci_driver);
713}
714
715module_init(acenic_init);
716module_exit(acenic_exit);
717
718static void ace_free_descriptors(struct net_device *dev)
719{
720 struct ace_private *ap = netdev_priv(dev);
721 int size;
722
723 if (ap->rx_std_ring != NULL) {
724 size = (sizeof(struct rx_desc) *
725 (RX_STD_RING_ENTRIES +
726 RX_JUMBO_RING_ENTRIES +
727 RX_MINI_RING_ENTRIES +
728 RX_RETURN_RING_ENTRIES));
729 pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
730 ap->rx_ring_base_dma);
731 ap->rx_std_ring = NULL;
732 ap->rx_jumbo_ring = NULL;
733 ap->rx_mini_ring = NULL;
734 ap->rx_return_ring = NULL;
735 }
736 if (ap->evt_ring != NULL) {
737 size = (sizeof(struct event) * EVT_RING_ENTRIES);
738 pci_free_consistent(ap->pdev, size, ap->evt_ring,
739 ap->evt_ring_dma);
740 ap->evt_ring = NULL;
741 }
742 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
743 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
744 pci_free_consistent(ap->pdev, size, ap->tx_ring,
745 ap->tx_ring_dma);
746 }
747 ap->tx_ring = NULL;
748
749 if (ap->evt_prd != NULL) {
750 pci_free_consistent(ap->pdev, sizeof(u32),
751 (void *)ap->evt_prd, ap->evt_prd_dma);
752 ap->evt_prd = NULL;
753 }
754 if (ap->rx_ret_prd != NULL) {
755 pci_free_consistent(ap->pdev, sizeof(u32),
756 (void *)ap->rx_ret_prd,
757 ap->rx_ret_prd_dma);
758 ap->rx_ret_prd = NULL;
759 }
760 if (ap->tx_csm != NULL) {
761 pci_free_consistent(ap->pdev, sizeof(u32),
762 (void *)ap->tx_csm, ap->tx_csm_dma);
763 ap->tx_csm = NULL;
764 }
765}
766
767
768static int ace_allocate_descriptors(struct net_device *dev)
769{
770 struct ace_private *ap = netdev_priv(dev);
771 int size;
772
773 size = (sizeof(struct rx_desc) *
774 (RX_STD_RING_ENTRIES +
775 RX_JUMBO_RING_ENTRIES +
776 RX_MINI_RING_ENTRIES +
777 RX_RETURN_RING_ENTRIES));
778
779 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
780 &ap->rx_ring_base_dma);
781 if (ap->rx_std_ring == NULL)
782 goto fail;
783
784 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
785 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
786 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
787
788 size = (sizeof(struct event) * EVT_RING_ENTRIES);
789
790 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
791
792 if (ap->evt_ring == NULL)
793 goto fail;
794
795 /*
796 * Only allocate a host TX ring for the Tigon II, the Tigon I
797 * has to use PCI registers for this ;-(
798 */
799 if (!ACE_IS_TIGON_I(ap)) {
800 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
801
802 ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
803 &ap->tx_ring_dma);
804
805 if (ap->tx_ring == NULL)
806 goto fail;
807 }
808
809 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
810 &ap->evt_prd_dma);
811 if (ap->evt_prd == NULL)
812 goto fail;
813
814 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
815 &ap->rx_ret_prd_dma);
816 if (ap->rx_ret_prd == NULL)
817 goto fail;
818
819 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
820 &ap->tx_csm_dma);
821 if (ap->tx_csm == NULL)
822 goto fail;
823
824 return 0;
825
826fail:
827 /* Clean up. */
828 ace_init_cleanup(dev);
829 return 1;
830}
831
832
833/*
834 * Generic cleanup handling data allocated during init. Used when the
835 * module is unloaded or if an error occurs during initialization
836 */
837static void ace_init_cleanup(struct net_device *dev)
838{
839 struct ace_private *ap;
840
841 ap = netdev_priv(dev);
842
843 ace_free_descriptors(dev);
844
845 if (ap->info)
846 pci_free_consistent(ap->pdev, sizeof(struct ace_info),
847 ap->info, ap->info_dma);
b4558ea9
JJ		 848 kfree(ap->skb);
849 kfree(ap->trace_buf);
1da177e4
LT		 850
851 if (dev->irq)
852 free_irq(dev->irq, dev);
853
854 iounmap(ap->regs);
855}
856
857
858/*
859 * Commands are considered to be slow.
860 */
861static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
862{
863 u32 idx;
864
865 idx = readl(&regs->CmdPrd);
866
867 writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
868 idx = (idx + 1) % CMD_RING_ENTRIES;
869
870 writel(idx, &regs->CmdPrd);
871}
872
873
083abbb7 874static int ace_init(struct net_device *dev)
1da177e4
LT		 875{
876 struct ace_private *ap;
877 struct ace_regs __iomem *regs;
878 struct ace_info *info = NULL;
879 struct pci_dev *pdev;
880 unsigned long myjif;
881 u64 tmp_ptr;
882 u32 tig_ver, mac1, mac2, tmp, pci_state;
883 int board_idx, ecode = 0;
884 short i;
885 unsigned char cache_size;
886
887 ap = netdev_priv(dev);
888 regs = ap->regs;
889
890 board_idx = ap->board_idx;
891
892 /*
893 * aman@sgi.com - its useful to do a NIC reset here to
894 * address the `Firmware not running' problem subsequent
895 * to any crashes involving the NIC
896 */
897 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
898 readl(&regs->HostCtrl); /* PCI write posting */
899 udelay(5);
900
901 /*
902 * Don't access any other registers before this point!
903 */
904#ifdef __BIG_ENDIAN
905 /*
906 * This will most likely need BYTE_SWAP once we switch
907 * to using __raw_writel()
908 */
909 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
910 &regs->HostCtrl);
911#else
912 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
913 &regs->HostCtrl);
914#endif
915 readl(&regs->HostCtrl); /* PCI write posting */
916
917 /*
918 * Stop the NIC CPU and clear pending interrupts
919 */
920 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
921 readl(&regs->CpuCtrl); /* PCI write posting */
922 writel(0, &regs->Mb0Lo);
923
924 tig_ver = readl(&regs->HostCtrl) >> 28;
925
926 switch(tig_ver){
927#ifndef CONFIG_ACENIC_OMIT_TIGON_I
928 case 4:
929 case 5:
930 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 931 tig_ver, ap->firmware_major, ap->firmware_minor,
932 ap->firmware_fix);
1da177e4
LT		 933 writel(0, &regs->LocalCtrl);
934 ap->version = 1;
935 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
936 break;
937#endif
938 case 6:
939 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
949b4254
JS		 940 tig_ver, ap->firmware_major, ap->firmware_minor,
941 ap->firmware_fix);
1da177e4
LT		 942 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
943 readl(&regs->CpuBCtrl); /* PCI write posting */
944 /*
945 * The SRAM bank size does _not_ indicate the amount
946 * of memory on the card, it controls the _bank_ size!
947 * Ie. a 1MB AceNIC will have two banks of 512KB.
948 */
949 writel(SRAM_BANK_512K, &regs->LocalCtrl);
950 writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
951 ap->version = 2;
952 ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
953 break;
954 default:
955 printk(KERN_WARNING " Unsupported Tigon version detected "
956 "(%i)\n", tig_ver);
957 ecode = -ENODEV;
958 goto init_error;
959 }
960
961 /*
962 * ModeStat _must_ be set after the SRAM settings as this change
963 * seems to corrupt the ModeStat and possible other registers.
964 * The SRAM settings survive resets and setting it to the same
965 * value a second time works as well. This is what caused the
966 * `Firmware not running' problem on the Tigon II.
967 */
968#ifdef __BIG_ENDIAN
969 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
970 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
971#else
972 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
973 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
974#endif
975 readl(&regs->ModeStat); /* PCI write posting */
976
977 mac1 = 0;
978 for(i = 0; i < 4; i++) {
ddfce6bb 979 int t;
6f9d4722 980
1da177e4 981 mac1 = mac1 << 8;
ddfce6bb
SH		 982 t = read_eeprom_byte(dev, 0x8c+i);
983 if (t < 0) {
1da177e4
LT		 984 ecode = -EIO;
985 goto init_error;
986 } else
ddfce6bb 987 mac1 |= (t & 0xff);
1da177e4
LT		 988 }
989 mac2 = 0;
990 for(i = 4; i < 8; i++) {
ddfce6bb 991 int t;
6f9d4722 992
1da177e4 993 mac2 = mac2 << 8;
ddfce6bb
SH		 994 t = read_eeprom_byte(dev, 0x8c+i);
995 if (t < 0) {
1da177e4
LT		 996 ecode = -EIO;
997 goto init_error;
998 } else
ddfce6bb 999 mac2 |= (t & 0xff);
1da177e4
LT		 1000 }
1001
1002 writel(mac1, &regs->MacAddrHi);
1003 writel(mac2, &regs->MacAddrLo);
1004
1da177e4
LT		 1005 dev->dev_addr[0] = (mac1 >> 8) & 0xff;
1006 dev->dev_addr[1] = mac1 & 0xff;
1007 dev->dev_addr[2] = (mac2 >> 24) & 0xff;
1008 dev->dev_addr[3] = (mac2 >> 16) & 0xff;
1009 dev->dev_addr[4] = (mac2 >> 8) & 0xff;
1010 dev->dev_addr[5] = mac2 & 0xff;
1011
e174961c 1012 printk("MAC: %pM\n", dev->dev_addr);
0795af57 1013
1da177e4
LT		 1014 /*
1015 * Looks like this is necessary to deal with on all architectures,
1016 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1017 * Ie. having two NICs in the machine, one will have the cache
1018 * line set at boot time, the other will not.
1019 */
1020 pdev = ap->pdev;
1021 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1022 cache_size <<= 2;
1023 if (cache_size != SMP_CACHE_BYTES) {
1024 printk(KERN_INFO " PCI cache line size set incorrectly "
1025 "(%i bytes) by BIOS/FW, ", cache_size);
1026 if (cache_size > SMP_CACHE_BYTES)
1027 printk("expecting %i\n", SMP_CACHE_BYTES);
1028 else {
1029 printk("correcting to %i\n", SMP_CACHE_BYTES);
1030 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1031 SMP_CACHE_BYTES >> 2);
1032 }
1033 }
1034
1035 pci_state = readl(&regs->PciState);
1036 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, "
1037 "latency: %i clks\n",
1038 (pci_state & PCI_32BIT) ? 32 : 64,
6aa20a22 1039 (pci_state & PCI_66MHZ) ? 66 : 33,
1da177e4
LT		 1040 ap->pci_latency);
1041
1042 /*
1043 * Set the max DMA transfer size. Seems that for most systems
1044 * the performance is better when no MAX parameter is
1045 * set. However for systems enabling PCI write and invalidate,
1046 * DMA writes must be set to the L1 cache line size to get
1047 * optimal performance.
1048 *
1049 * The default is now to turn the PCI write and invalidate off
1050 * - that is what Alteon does for NT.
1051 */
1052 tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1053 if (ap->version >= 2) {
1054 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1055 /*
1056 * Tuning parameters only supported for 8 cards
1057 */
1058 if (board_idx == BOARD_IDX_OVERFLOW ||
1059 dis_pci_mem_inval[board_idx]) {
1060 if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1061 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1062 pci_write_config_word(pdev, PCI_COMMAND,
1063 ap->pci_command);
1064 printk(KERN_INFO " Disabling PCI memory "
1065 "write and invalidate\n");
1066 }
1067 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1068 printk(KERN_INFO " PCI memory write & invalidate "
1069 "enabled by BIOS, enabling counter measures\n");
1070
1071 switch(SMP_CACHE_BYTES) {
1072 case 16:
1073 tmp |= DMA_WRITE_MAX_16;
1074 break;
1075 case 32:
1076 tmp |= DMA_WRITE_MAX_32;
1077 break;
1078 case 64:
1079 tmp |= DMA_WRITE_MAX_64;
1080 break;
1081 case 128:
1082 tmp |= DMA_WRITE_MAX_128;
1083 break;
1084 default:
1085 printk(KERN_INFO " Cache line size %i not "
1086 "supported, PCI write and invalidate "
1087 "disabled\n", SMP_CACHE_BYTES);
1088 ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1089 pci_write_config_word(pdev, PCI_COMMAND,
1090 ap->pci_command);
1091 }
1092 }
1093 }
1094
1095#ifdef __sparc__
1096 /*
1097 * On this platform, we know what the best dma settings
1098 * are. We use 64-byte maximum bursts, because if we
1099 * burst larger than the cache line size (or even cross
1100 * a 64byte boundary in a single burst) the UltraSparc
1101 * PCI controller will disconnect at 64-byte multiples.
1102 *
1103 * Read-multiple will be properly enabled above, and when
1104 * set will give the PCI controller proper hints about
1105 * prefetching.
1106 */
1107 tmp &= ~DMA_READ_WRITE_MASK;
1108 tmp |= DMA_READ_MAX_64;
1109 tmp |= DMA_WRITE_MAX_64;
1110#endif
1111#ifdef __alpha__
1112 tmp &= ~DMA_READ_WRITE_MASK;
1113 tmp |= DMA_READ_MAX_128;
1114 /*
1115 * All the docs say MUST NOT. Well, I did.
1116 * Nothing terrible happens, if we load wrong size.
1117 * Bit w&i still works better!
1118 */
1119 tmp |= DMA_WRITE_MAX_128;
1120#endif
1121 writel(tmp, &regs->PciState);
1122
1123#if 0
1124 /*
1125 * The Host PCI bus controller driver has to set FBB.
1126 * If all devices on that PCI bus support FBB, then the controller
1127 * can enable FBB support in the Host PCI Bus controller (or on
1128 * the PCI-PCI bridge if that applies).
1129 * -ggg
1130 */
1131 /*
1132 * I have received reports from people having problems when this
1133 * bit is enabled.
1134 */
1135 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1136 printk(KERN_INFO " Enabling PCI Fast Back to Back\n");
1137 ap->pci_command |= PCI_COMMAND_FAST_BACK;
1138 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1139 }
1140#endif
6aa20a22 1141
1da177e4
LT		 1142 /*
1143 * Configure DMA attributes.
1144 */
6a35528a 1145 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 1146 ap->pci_using_dac = 1;
284901a9 1147 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 1148 ap->pci_using_dac = 0;
1149 } else {
1150 ecode = -ENODEV;
1151 goto init_error;
1152 }
1153
1154 /*
1155 * Initialize the generic info block and the command+event rings
1156 * and the control blocks for the transmit and receive rings
1157 * as they need to be setup once and for all.
1158 */
1159 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1160 &ap->info_dma))) {
1161 ecode = -EAGAIN;
1162 goto init_error;
1163 }
1164 ap->info = info;
1165
1166 /*
1167 * Get the memory for the skb rings.
1168 */
1169 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1170 ecode = -EAGAIN;
1171 goto init_error;
1172 }
1173
1fb9df5d 1174 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1da177e4
LT		 1175 DRV_NAME, dev);
1176 if (ecode) {
1177 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1178 DRV_NAME, pdev->irq);
1179 goto init_error;
1180 } else
1181 dev->irq = pdev->irq;
1182
1183#ifdef INDEX_DEBUG
1184 spin_lock_init(&ap->debug_lock);
1185 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1186 ap->last_std_rx = 0;
1187 ap->last_mini_rx = 0;
1188#endif
1189
1190 memset(ap->info, 0, sizeof(struct ace_info));
1191 memset(ap->skb, 0, sizeof(struct ace_skb));
1192
6c60e0c3
BH		 1193 ecode = ace_load_firmware(dev);
1194 if (ecode)
949b4254
JS		 1195 goto init_error;
1196
1da177e4
LT		 1197 ap->fw_running = 0;
1198
1199 tmp_ptr = ap->info_dma;
1200 writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1201 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1202
1203 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1204
1205 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1206 info->evt_ctrl.flags = 0;
1207
1208 *(ap->evt_prd) = 0;
1209 wmb();
1210 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1211 writel(0, &regs->EvtCsm);
1212
1213 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1214 info->cmd_ctrl.flags = 0;
1215 info->cmd_ctrl.max_len = 0;
1216
1217 for (i = 0; i < CMD_RING_ENTRIES; i++)
1218 writel(0, &regs->CmdRng[i]);
1219
1220 writel(0, &regs->CmdPrd);
1221 writel(0, &regs->CmdCsm);
1222
1223 tmp_ptr = ap->info_dma;
1224 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1225 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1226
1227 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1228 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1229 info->rx_std_ctrl.flags =
08dddfc3 1230 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1231
1232 memset(ap->rx_std_ring, 0,
1233 RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1234
1235 for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1236 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1237
1238 ap->rx_std_skbprd = 0;
1239 atomic_set(&ap->cur_rx_bufs, 0);
1240
1241 set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1242 (ap->rx_ring_base_dma +
1243 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1244 info->rx_jumbo_ctrl.max_len = 0;
1245 info->rx_jumbo_ctrl.flags =
08dddfc3 1246 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1247
1248 memset(ap->rx_jumbo_ring, 0,
1249 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1250
1251 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1252 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1253
1254 ap->rx_jumbo_skbprd = 0;
1255 atomic_set(&ap->cur_jumbo_bufs, 0);
1256
1257 memset(ap->rx_mini_ring, 0,
1258 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1259
1260 if (ap->version >= 2) {
1261 set_aceaddr(&info->rx_mini_ctrl.rngptr,
1262 (ap->rx_ring_base_dma +
1263 (sizeof(struct rx_desc) *
1264 (RX_STD_RING_ENTRIES +
1265 RX_JUMBO_RING_ENTRIES))));
1266 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
6aa20a22 1267 info->rx_mini_ctrl.flags =
08dddfc3 1268 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1269
1270 for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1271 ap->rx_mini_ring[i].flags =
1272 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1273 } else {
1274 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1275 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1276 info->rx_mini_ctrl.max_len = 0;
1277 }
1278
1279 ap->rx_mini_skbprd = 0;
1280 atomic_set(&ap->cur_mini_bufs, 0);
1281
1282 set_aceaddr(&info->rx_return_ctrl.rngptr,
1283 (ap->rx_ring_base_dma +
1284 (sizeof(struct rx_desc) *
1285 (RX_STD_RING_ENTRIES +
1286 RX_JUMBO_RING_ENTRIES +
1287 RX_MINI_RING_ENTRIES))));
1288 info->rx_return_ctrl.flags = 0;
1289 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1290
1291 memset(ap->rx_return_ring, 0,
1292 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1293
1294 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1295 *(ap->rx_ret_prd) = 0;
1296
1297 writel(TX_RING_BASE, &regs->WinBase);
1298
1299 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 1300 ap->tx_ring = (__force struct tx_desc *) regs->Window;
6aa20a22 1301 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1da177e4 1302 * sizeof(struct tx_desc)) / sizeof(u32); i++)
ddfce6bb 1303 writel(0, (__force void __iomem *)ap->tx_ring + i * 4);
1da177e4
LT		 1304
1305 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1306 } else {
1307 memset(ap->tx_ring, 0,
1308 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1309
1310 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1311 }
1312
1313 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
08dddfc3 1314 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1da177e4
LT		 1315
1316 /*
1317 * The Tigon I does not like having the TX ring in host memory ;-(
1318 */
1319 if (!ACE_IS_TIGON_I(ap))
1320 tmp |= RCB_FLG_TX_HOST_RING;
1321#if TX_COAL_INTS_ONLY
1322 tmp |= RCB_FLG_COAL_INT_ONLY;
1323#endif
1324 info->tx_ctrl.flags = tmp;
1325
1326 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1327
1328 /*
1329 * Potential item for tuning parameter
1330 */
1331#if 0 /* NO */
1332 writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1333 writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1334#else
1335 writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1336 writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1337#endif
1338
1339 writel(0, &regs->MaskInt);
1340 writel(1, &regs->IfIdx);
1341#if 0
1342 /*
1343 * McKinley boxes do not like us fiddling with AssistState
1344 * this early
1345 */
1346 writel(1, &regs->AssistState);
1347#endif
1348
1349 writel(DEF_STAT, &regs->TuneStatTicks);
1350 writel(DEF_TRACE, &regs->TuneTrace);
1351
1352 ace_set_rxtx_parms(dev, 0);
1353
1354 if (board_idx == BOARD_IDX_OVERFLOW) {
1355 printk(KERN_WARNING "%s: more than %i NICs detected, "
1356 "ignoring module parameters!\n",
1357 ap->name, ACE_MAX_MOD_PARMS);
1358 } else if (board_idx >= 0) {
1359 if (tx_coal_tick[board_idx])
1360 writel(tx_coal_tick[board_idx],
1361 &regs->TuneTxCoalTicks);
1362 if (max_tx_desc[board_idx])
1363 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1364
1365 if (rx_coal_tick[board_idx])
1366 writel(rx_coal_tick[board_idx],
1367 &regs->TuneRxCoalTicks);
1368 if (max_rx_desc[board_idx])
1369 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1370
1371 if (trace[board_idx])
1372 writel(trace[board_idx], &regs->TuneTrace);
1373
1374 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1375 writel(tx_ratio[board_idx], &regs->TxBufRat);
1376 }
1377
1378 /*
1379 * Default link parameters
1380 */
1381 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1382 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1383 if(ap->version >= 2)
1384 tmp |= LNK_TX_FLOW_CTL_Y;
1385
1386 /*
1387 * Override link default parameters
1388 */
ddfce6bb
SH		 1389 if ((board_idx >= 0) && link_state[board_idx]) {
1390 int option = link_state[board_idx];
1da177e4
LT		 1391
1392 tmp = LNK_ENABLE;
1393
1394 if (option & 0x01) {
1395 printk(KERN_INFO "%s: Setting half duplex link\n",
1396 ap->name);
1397 tmp &= ~LNK_FULL_DUPLEX;
1398 }
1399 if (option & 0x02)
1400 tmp &= ~LNK_NEGOTIATE;
1401 if (option & 0x10)
1402 tmp |= LNK_10MB;
1403 if (option & 0x20)
1404 tmp |= LNK_100MB;
1405 if (option & 0x40)
1406 tmp |= LNK_1000MB;
1407 if ((option & 0x70) == 0) {
1408 printk(KERN_WARNING "%s: No media speed specified, "
1409 "forcing auto negotiation\n", ap->name);
1410 tmp |= LNK_NEGOTIATE | LNK_1000MB |
1411 LNK_100MB | LNK_10MB;
1412 }
1413 if ((option & 0x100) == 0)
1414 tmp |= LNK_NEG_FCTL;
1415 else
1416 printk(KERN_INFO "%s: Disabling flow control "
1417 "negotiation\n", ap->name);
1418 if (option & 0x200)
1419 tmp |= LNK_RX_FLOW_CTL_Y;
1420 if ((option & 0x400) && (ap->version >= 2)) {
1421 printk(KERN_INFO "%s: Enabling TX flow control\n",
1422 ap->name);
1423 tmp |= LNK_TX_FLOW_CTL_Y;
1424 }
1425 }
1426
1427 ap->link = tmp;
1428 writel(tmp, &regs->TuneLink);
1429 if (ap->version >= 2)
1430 writel(tmp, &regs->TuneFastLink);
1431
949b4254 1432 writel(ap->firmware_start, &regs->Pc);
1da177e4
LT		 1433
1434 writel(0, &regs->Mb0Lo);
1435
1436 /*
1437 * Set tx_csm before we start receiving interrupts, otherwise
1438 * the interrupt handler might think it is supposed to process
1439 * tx ints before we are up and running, which may cause a null
1440 * pointer access in the int handler.
1441 */
1442 ap->cur_rx = 0;
1443 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1444
1445 wmb();
1446 ace_set_txprd(regs, ap, 0);
1447 writel(0, &regs->RxRetCsm);
1448
1da177e4
LT		 1449 /*
1450 * Enable DMA engine now.
1451 * If we do this sooner, Mckinley box pukes.
1452 * I assume it's because Tigon II DMA engine wants to check
1453 * *something* even before the CPU is started.
1454 */
1455 writel(1, &regs->AssistState); /* enable DMA */
1456
1457 /*
1458 * Start the NIC CPU
1459 */
1460 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1461 readl(&regs->CpuCtrl);
1462
1463 /*
1464 * Wait for the firmware to spin up - max 3 seconds.
1465 */
1466 myjif = jiffies + 3 * HZ;
1467 while (time_before(jiffies, myjif) && !ap->fw_running)
1468 cpu_relax();
1469
1470 if (!ap->fw_running) {
1471 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1472
1473 ace_dump_trace(ap);
1474 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1475 readl(&regs->CpuCtrl);
1476
1477 /* aman@sgi.com - account for badly behaving firmware/NIC:
1478 * - have observed that the NIC may continue to generate
1479 * interrupts for some reason; attempt to stop it - halt
1480 * second CPU for Tigon II cards, and also clear Mb0
1481 * - if we're a module, we'll fail to load if this was
1482 * the only GbE card in the system => if the kernel does
1483 * see an interrupt from the NIC, code to handle it is
1484 * gone and OOps! - so free_irq also
1485 */
1486 if (ap->version >= 2)
1487 writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1488 &regs->CpuBCtrl);
1489 writel(0, &regs->Mb0Lo);
1490 readl(&regs->Mb0Lo);
1491
1492 ecode = -EBUSY;
1493 goto init_error;
1494 }
1495
1496 /*
1497 * We load the ring here as there seem to be no way to tell the
1498 * firmware to wipe the ring without re-initializing it.
1499 */
1500 if (!test_and_set_bit(0, &ap->std_refill_busy))
427e21fa 1501 ace_load_std_rx_ring(dev, RX_RING_SIZE);
1da177e4
LT		 1502 else
1503 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1504 ap->name);
1505 if (ap->version >= 2) {
1506 if (!test_and_set_bit(0, &ap->mini_refill_busy))
427e21fa 1507 ace_load_mini_rx_ring(dev, RX_MINI_SIZE);
1da177e4
LT		 1508 else
1509 printk(KERN_ERR "%s: Someone is busy refilling "
1510 "the RX mini ring\n", ap->name);
1511 }
1512 return 0;
1513
1514 init_error:
1515 ace_init_cleanup(dev);
1516 return ecode;
1517}
1518
1519
1520static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1521{
1522 struct ace_private *ap = netdev_priv(dev);
1523 struct ace_regs __iomem *regs = ap->regs;
1524 int board_idx = ap->board_idx;
1525
1526 if (board_idx >= 0) {
1527 if (!jumbo) {
1528 if (!tx_coal_tick[board_idx])
1529 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1530 if (!max_tx_desc[board_idx])
1531 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1532 if (!rx_coal_tick[board_idx])
1533 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1534 if (!max_rx_desc[board_idx])
1535 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1536 if (!tx_ratio[board_idx])
1537 writel(DEF_TX_RATIO, &regs->TxBufRat);
1538 } else {
1539 if (!tx_coal_tick[board_idx])
1540 writel(DEF_JUMBO_TX_COAL,
1541 &regs->TuneTxCoalTicks);
1542 if (!max_tx_desc[board_idx])
1543 writel(DEF_JUMBO_TX_MAX_DESC,
1544 &regs->TuneMaxTxDesc);
1545 if (!rx_coal_tick[board_idx])
1546 writel(DEF_JUMBO_RX_COAL,
1547 &regs->TuneRxCoalTicks);
1548 if (!max_rx_desc[board_idx])
1549 writel(DEF_JUMBO_RX_MAX_DESC,
1550 &regs->TuneMaxRxDesc);
1551 if (!tx_ratio[board_idx])
1552 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1553 }
1554 }
1555}
1556
1557
1558static void ace_watchdog(struct net_device *data)
1559{
1560 struct net_device *dev = data;
1561 struct ace_private *ap = netdev_priv(dev);
1562 struct ace_regs __iomem *regs = ap->regs;
1563
1564 /*
1565 * We haven't received a stats update event for more than 2.5
1566 * seconds and there is data in the transmit queue, thus we
25985edc 1567 * assume the card is stuck.
1da177e4
LT		 1568 */
1569 if (*ap->tx_csm != ap->tx_ret_csm) {
1570 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1571 dev->name, (unsigned int)readl(&regs->HostCtrl));
1572 /* This can happen due to ieee flow control. */
1573 } else {
1574 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1575 dev->name);
1576#if 0
1577 netif_wake_queue(dev);
1578#endif
1579 }
1580}
1581
1582
427e21fa 1583static void ace_tasklet(unsigned long arg)
1da177e4 1584{
427e21fa 1585 struct net_device *dev = (struct net_device *) arg;
1586 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1587 int cur_size;
1588
1589 cur_size = atomic_read(&ap->cur_rx_bufs);
1590 if ((cur_size < RX_LOW_STD_THRES) &&
1591 !test_and_set_bit(0, &ap->std_refill_busy)) {
1592#ifdef DEBUG
1593 printk("refilling buffers (current %i)\n", cur_size);
1594#endif
427e21fa 1595 ace_load_std_rx_ring(dev, RX_RING_SIZE - cur_size);
1da177e4
LT		 1596 }
1597
1598 if (ap->version >= 2) {
1599 cur_size = atomic_read(&ap->cur_mini_bufs);
1600 if ((cur_size < RX_LOW_MINI_THRES) &&
1601 !test_and_set_bit(0, &ap->mini_refill_busy)) {
1602#ifdef DEBUG
1603 printk("refilling mini buffers (current %i)\n",
1604 cur_size);
1605#endif
427e21fa 1606 ace_load_mini_rx_ring(dev, RX_MINI_SIZE - cur_size);
1da177e4
LT		 1607 }
1608 }
1609
1610 cur_size = atomic_read(&ap->cur_jumbo_bufs);
1611 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1612 !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1613#ifdef DEBUG
1614 printk("refilling jumbo buffers (current %i)\n", cur_size);
1615#endif
427e21fa 1616 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE - cur_size);
1da177e4
LT		 1617 }
1618 ap->tasklet_pending = 0;
1619}
1620
1621
1622/*
1623 * Copy the contents of the NIC's trace buffer to kernel memory.
1624 */
1625static void ace_dump_trace(struct ace_private *ap)
1626{
1627#if 0
1628 if (!ap->trace_buf)
1629 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1630 return;
1631#endif
1632}
1633
1634
1635/*
1636 * Load the standard rx ring.
1637 *
1638 * Loading rings is safe without holding the spin lock since this is
1639 * done only before the device is enabled, thus no interrupts are
1640 * generated and by the interrupt handler/tasklet handler.
1641 */
427e21fa 1642static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1643{
427e21fa 1644 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1645 struct ace_regs __iomem *regs = ap->regs;
1646 short i, idx;
6aa20a22 1647
1da177e4
LT		 1648
1649 prefetchw(&ap->cur_rx_bufs);
1650
1651 idx = ap->rx_std_skbprd;
1652
1653 for (i = 0; i < nr_bufs; i++) {
1654 struct sk_buff *skb;
1655 struct rx_desc *rd;
1656 dma_addr_t mapping;
1657
427e21fa 1658 skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE);
1da177e4
LT		 1659 if (!skb)
1660 break;
1661
1da177e4
LT		 1662 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1663 offset_in_page(skb->data),
1664 ACE_STD_BUFSIZE,
1665 PCI_DMA_FROMDEVICE);
1666 ap->skb->rx_std_skbuff[idx].skb = skb;
430e55b1 1667 dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1da177e4
LT		 1668 mapping, mapping);
1669
1670 rd = &ap->rx_std_ring[idx];
1671 set_aceaddr(&rd->addr, mapping);
1672 rd->size = ACE_STD_BUFSIZE;
1673 rd->idx = idx;
1674 idx = (idx + 1) % RX_STD_RING_ENTRIES;
1675 }
1676
1677 if (!i)
1678 goto error_out;
1679
1680 atomic_add(i, &ap->cur_rx_bufs);
1681 ap->rx_std_skbprd = idx;
1682
1683 if (ACE_IS_TIGON_I(ap)) {
1684 struct cmd cmd;
1685 cmd.evt = C_SET_RX_PRD_IDX;
1686 cmd.code = 0;
1687 cmd.idx = ap->rx_std_skbprd;
1688 ace_issue_cmd(regs, &cmd);
1689 } else {
1690 writel(idx, &regs->RxStdPrd);
1691 wmb();
1692 }
1693
1694 out:
1695 clear_bit(0, &ap->std_refill_busy);
1696 return;
1697
1698 error_out:
1699 printk(KERN_INFO "Out of memory when allocating "
1700 "standard receive buffers\n");
1701 goto out;
1702}
1703
1704
427e21fa 1705static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1706{
427e21fa 1707 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1708 struct ace_regs __iomem *regs = ap->regs;
1709 short i, idx;
1710
1711 prefetchw(&ap->cur_mini_bufs);
1712
1713 idx = ap->rx_mini_skbprd;
1714 for (i = 0; i < nr_bufs; i++) {
1715 struct sk_buff *skb;
1716 struct rx_desc *rd;
1717 dma_addr_t mapping;
1718
427e21fa 1719 skb = netdev_alloc_skb_ip_align(dev, ACE_MINI_BUFSIZE);
1da177e4
LT		 1720 if (!skb)
1721 break;
1722
1da177e4
LT		 1723 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1724 offset_in_page(skb->data),
1725 ACE_MINI_BUFSIZE,
1726 PCI_DMA_FROMDEVICE);
1727 ap->skb->rx_mini_skbuff[idx].skb = skb;
430e55b1 1728 dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1da177e4
LT		 1729 mapping, mapping);
1730
1731 rd = &ap->rx_mini_ring[idx];
1732 set_aceaddr(&rd->addr, mapping);
1733 rd->size = ACE_MINI_BUFSIZE;
1734 rd->idx = idx;
1735 idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1736 }
1737
1738 if (!i)
1739 goto error_out;
1740
1741 atomic_add(i, &ap->cur_mini_bufs);
1742
1743 ap->rx_mini_skbprd = idx;
1744
1745 writel(idx, &regs->RxMiniPrd);
1746 wmb();
1747
1748 out:
1749 clear_bit(0, &ap->mini_refill_busy);
1750 return;
1751 error_out:
1752 printk(KERN_INFO "Out of memory when allocating "
1753 "mini receive buffers\n");
1754 goto out;
1755}
1756
1757
1758/*
1759 * Load the jumbo rx ring, this may happen at any time if the MTU
1760 * is changed to a value > 1500.
1761 */
427e21fa 1762static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs)
1da177e4 1763{
427e21fa 1764 struct ace_private *ap = netdev_priv(dev);
1da177e4
LT		 1765 struct ace_regs __iomem *regs = ap->regs;
1766 short i, idx;
1767
1768 idx = ap->rx_jumbo_skbprd;
1769
1770 for (i = 0; i < nr_bufs; i++) {
1771 struct sk_buff *skb;
1772 struct rx_desc *rd;
1773 dma_addr_t mapping;
1774
427e21fa 1775 skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE);
1da177e4
LT		 1776 if (!skb)
1777 break;
1778
1da177e4
LT		 1779 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1780 offset_in_page(skb->data),
1781 ACE_JUMBO_BUFSIZE,
1782 PCI_DMA_FROMDEVICE);
1783 ap->skb->rx_jumbo_skbuff[idx].skb = skb;
430e55b1 1784 dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1da177e4
LT		 1785 mapping, mapping);
1786
1787 rd = &ap->rx_jumbo_ring[idx];
1788 set_aceaddr(&rd->addr, mapping);
1789 rd->size = ACE_JUMBO_BUFSIZE;
1790 rd->idx = idx;
1791 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1792 }
1793
1794 if (!i)
1795 goto error_out;
1796
1797 atomic_add(i, &ap->cur_jumbo_bufs);
1798 ap->rx_jumbo_skbprd = idx;
1799
1800 if (ACE_IS_TIGON_I(ap)) {
1801 struct cmd cmd;
1802 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1803 cmd.code = 0;
1804 cmd.idx = ap->rx_jumbo_skbprd;
1805 ace_issue_cmd(regs, &cmd);
1806 } else {
1807 writel(idx, &regs->RxJumboPrd);
1808 wmb();
1809 }
1810
1811 out:
1812 clear_bit(0, &ap->jumbo_refill_busy);
1813 return;
1814 error_out:
1815 if (net_ratelimit())
1816 printk(KERN_INFO "Out of memory when allocating "
1817 "jumbo receive buffers\n");
1818 goto out;
1819}
1820
1821
1822/*
1823 * All events are considered to be slow (RX/TX ints do not generate
1824 * events) and are handled here, outside the main interrupt handler,
1825 * to reduce the size of the handler.
1826 */
1827static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1828{
1829 struct ace_private *ap;
1830
1831 ap = netdev_priv(dev);
1832
1833 while (evtcsm != evtprd) {
1834 switch (ap->evt_ring[evtcsm].evt) {
1835 case E_FW_RUNNING:
1836 printk(KERN_INFO "%s: Firmware up and running\n",
1837 ap->name);
1838 ap->fw_running = 1;
1839 wmb();
1840 break;
1841 case E_STATS_UPDATED:
1842 break;
1843 case E_LNK_STATE:
1844 {
1845 u16 code = ap->evt_ring[evtcsm].code;
1846 switch (code) {
1847 case E_C_LINK_UP:
1848 {
1849 u32 state = readl(&ap->regs->GigLnkState);
1850 printk(KERN_WARNING "%s: Optical link UP "
1851 "(%s Duplex, Flow Control: %s%s)\n",
1852 ap->name,
1853 state & LNK_FULL_DUPLEX ? "Full":"Half",
1854 state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1855 state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1856 break;
1857 }
1858 case E_C_LINK_DOWN:
1859 printk(KERN_WARNING "%s: Optical link DOWN\n",
1860 ap->name);
1861 break;
1862 case E_C_LINK_10_100:
1863 printk(KERN_WARNING "%s: 10/100BaseT link "
1864 "UP\n", ap->name);
1865 break;
1866 default:
1867 printk(KERN_ERR "%s: Unknown optical link "
1868 "state %02x\n", ap->name, code);
1869 }
1870 break;
1871 }
1872 case E_ERROR:
1873 switch(ap->evt_ring[evtcsm].code) {
1874 case E_C_ERR_INVAL_CMD:
1875 printk(KERN_ERR "%s: invalid command error\n",
1876 ap->name);
1877 break;
1878 case E_C_ERR_UNIMP_CMD:
1879 printk(KERN_ERR "%s: unimplemented command "
1880 "error\n", ap->name);
1881 break;
1882 case E_C_ERR_BAD_CFG:
1883 printk(KERN_ERR "%s: bad config error\n",
1884 ap->name);
1885 break;
1886 default:
1887 printk(KERN_ERR "%s: unknown error %02x\n",
1888 ap->name, ap->evt_ring[evtcsm].code);
1889 }
1890 break;
1891 case E_RESET_JUMBO_RNG:
1892 {
1893 int i;
1894 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1895 if (ap->skb->rx_jumbo_skbuff[i].skb) {
1896 ap->rx_jumbo_ring[i].size = 0;
1897 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1898 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1899 ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1900 }
1901 }
1902
1903 if (ACE_IS_TIGON_I(ap)) {
1904 struct cmd cmd;
1905 cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1906 cmd.code = 0;
1907 cmd.idx = 0;
1908 ace_issue_cmd(ap->regs, &cmd);
1909 } else {
1910 writel(0, &((ap->regs)->RxJumboPrd));
1911 wmb();
1912 }
1913
1914 ap->jumbo = 0;
1915 ap->rx_jumbo_skbprd = 0;
1916 printk(KERN_INFO "%s: Jumbo ring flushed\n",
1917 ap->name);
1918 clear_bit(0, &ap->jumbo_refill_busy);
1919 break;
1920 }
1921 default:
1922 printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1923 ap->name, ap->evt_ring[evtcsm].evt);
1924 }
1925 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1926 }
1927
1928 return evtcsm;
1929}
1930
1931
1932static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1933{
1934 struct ace_private *ap = netdev_priv(dev);
1935 u32 idx;
1936 int mini_count = 0, std_count = 0;
1937
1938 idx = rxretcsm;
1939
1940 prefetchw(&ap->cur_rx_bufs);
1941 prefetchw(&ap->cur_mini_bufs);
6aa20a22 1942
1da177e4
LT		 1943 while (idx != rxretprd) {
1944 struct ring_info *rip;
1945 struct sk_buff *skb;
1946 struct rx_desc *rxdesc, *retdesc;
1947 u32 skbidx;
1948 int bd_flags, desc_type, mapsize;
1949 u16 csum;
1950
1951
1952 /* make sure the rx descriptor isn't read before rxretprd */
6aa20a22 1953 if (idx == rxretcsm)
1da177e4
LT		 1954 rmb();
1955
1956 retdesc = &ap->rx_return_ring[idx];
1957 skbidx = retdesc->idx;
1958 bd_flags = retdesc->flags;
1959 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1960
1961 switch(desc_type) {
1962 /*
1963 * Normal frames do not have any flags set
1964 *
1965 * Mini and normal frames arrive frequently,
1966 * so use a local counter to avoid doing
1967 * atomic operations for each packet arriving.
1968 */
1969 case 0:
1970 rip = &ap->skb->rx_std_skbuff[skbidx];
1971 mapsize = ACE_STD_BUFSIZE;
1972 rxdesc = &ap->rx_std_ring[skbidx];
1973 std_count++;
1974 break;
1975 case BD_FLG_JUMBO:
1976 rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1977 mapsize = ACE_JUMBO_BUFSIZE;
1978 rxdesc = &ap->rx_jumbo_ring[skbidx];
1979 atomic_dec(&ap->cur_jumbo_bufs);
1980 break;
1981 case BD_FLG_MINI:
1982 rip = &ap->skb->rx_mini_skbuff[skbidx];
1983 mapsize = ACE_MINI_BUFSIZE;
1984 rxdesc = &ap->rx_mini_ring[skbidx];
6aa20a22 1985 mini_count++;
1da177e4
LT		 1986 break;
1987 default:
1988 printk(KERN_INFO "%s: unknown frame type (0x%02x) "
1989 "returned by NIC\n", dev->name,
1990 retdesc->flags);
1991 goto error;
1992 }
1993
1994 skb = rip->skb;
1995 rip->skb = NULL;
1996 pci_unmap_page(ap->pdev,
430e55b1 1997 dma_unmap_addr(rip, mapping),
1da177e4
LT		 1998 mapsize,
1999 PCI_DMA_FROMDEVICE);
2000 skb_put(skb, retdesc->size);
2001
2002 /*
2003 * Fly baby, fly!
2004 */
2005 csum = retdesc->tcp_udp_csum;
2006
1da177e4
LT		 2007 skb->protocol = eth_type_trans(skb, dev);
2008
2009 /*
2010 * Instead of forcing the poor tigon mips cpu to calculate
2011 * pseudo hdr checksum, we do this ourselves.
2012 */
2013 if (bd_flags & BD_FLG_TCP_UDP_SUM) {
2014 skb->csum = htons(csum);
84fa7933 2015 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4 2016 } else {
bc8acf2c 2017 skb_checksum_none_assert(skb);
1da177e4
LT		 2018 }
2019
2020 /* send it up */
08dddfc3
JP		 2021 if ((bd_flags & BD_FLG_VLAN_TAG))
2022 __vlan_hwaccel_put_tag(skb, retdesc->vlan);
2023 netif_rx(skb);
1da177e4 2024
966e37bc
PZ		 2025 dev->stats.rx_packets++;
2026 dev->stats.rx_bytes += retdesc->size;
1da177e4
LT		 2027
2028 idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2029 }
2030
2031 atomic_sub(std_count, &ap->cur_rx_bufs);
2032 if (!ACE_IS_TIGON_I(ap))
2033 atomic_sub(mini_count, &ap->cur_mini_bufs);
2034
2035 out:
2036 /*
2037 * According to the documentation RxRetCsm is obsolete with
2038 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2039 */
2040 if (ACE_IS_TIGON_I(ap)) {
2041 writel(idx, &ap->regs->RxRetCsm);
2042 }
2043 ap->cur_rx = idx;
2044
2045 return;
2046 error:
2047 idx = rxretprd;
2048 goto out;
2049}
2050
2051
2052static inline void ace_tx_int(struct net_device *dev,
2053 u32 txcsm, u32 idx)
2054{
2055 struct ace_private *ap = netdev_priv(dev);
2056
2057 do {
2058 struct sk_buff *skb;
1da177e4
LT		 2059 struct tx_ring_info *info;
2060
2061 info = ap->skb->tx_skbuff + idx;
2062 skb = info->skb;
1da177e4 2063
07e7de8f
FT		 2064 if (dma_unmap_len(info, maplen)) {
2065 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
430e55b1 2066 dma_unmap_len(info, maplen),
1da177e4 2067 PCI_DMA_TODEVICE);
07e7de8f 2068 dma_unmap_len_set(info, maplen, 0);
1da177e4
LT		 2069 }
2070
2071 if (skb) {
966e37bc
PZ		 2072 dev->stats.tx_packets++;
2073 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 2074 dev_kfree_skb_irq(skb);
2075 info->skb = NULL;
2076 }
2077
2078 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2079 } while (idx != txcsm);
2080
2081 if (netif_queue_stopped(dev))
2082 netif_wake_queue(dev);
2083
2084 wmb();
2085 ap->tx_ret_csm = txcsm;
2086
2087 /* So... tx_ret_csm is advanced _after_ check for device wakeup.
2088 *
2089 * We could try to make it before. In this case we would get
2090 * the following race condition: hard_start_xmit on other cpu
2091 * enters after we advanced tx_ret_csm and fills space,
2092 * which we have just freed, so that we make illegal device wakeup.
2093 * There is no good way to workaround this (at entry
2094 * to ace_start_xmit detects this condition and prevents
2095 * ring corruption, but it is not a good workaround.)
2096 *
2097 * When tx_ret_csm is advanced after, we wake up device _only_
2098 * if we really have some space in ring (though the core doing
2099 * hard_start_xmit can see full ring for some period and has to
2100 * synchronize.) Superb.
2101 * BUT! We get another subtle race condition. hard_start_xmit
2102 * may think that ring is full between wakeup and advancing
2103 * tx_ret_csm and will stop device instantly! It is not so bad.
2104 * We are guaranteed that there is something in ring, so that
2105 * the next irq will resume transmission. To speedup this we could
2106 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2107 * (see ace_start_xmit).
2108 *
2109 * Well, this dilemma exists in all lock-free devices.
2110 * We, following scheme used in drivers by Donald Becker,
2111 * select the least dangerous.
2112 * --ANK
2113 */
2114}
2115
2116
7d12e780 2117static irqreturn_t ace_interrupt(int irq, void *dev_id)
1da177e4
LT		 2118{
2119 struct net_device *dev = (struct net_device *)dev_id;
2120 struct ace_private *ap = netdev_priv(dev);
2121 struct ace_regs __iomem *regs = ap->regs;
2122 u32 idx;
2123 u32 txcsm, rxretcsm, rxretprd;
2124 u32 evtcsm, evtprd;
2125
2126 /*
2127 * In case of PCI shared interrupts or spurious interrupts,
2128 * we want to make sure it is actually our interrupt before
2129 * spending any time in here.
2130 */
2131 if (!(readl(&regs->HostCtrl) & IN_INT))
2132 return IRQ_NONE;
2133
2134 /*
2135 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2136 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2137 * writel(0, &regs->Mb0Lo).
2138 *
2139 * "IRQ avoidance" recommended in docs applies to IRQs served
2140 * threads and it is wrong even for that case.
2141 */
2142 writel(0, &regs->Mb0Lo);
2143 readl(&regs->Mb0Lo);
2144
2145 /*
2146 * There is no conflict between transmit handling in
2147 * start_xmit and receive processing, thus there is no reason
2148 * to take a spin lock for RX handling. Wait until we start
2149 * working on the other stuff - hey we don't need a spin lock
2150 * anymore.
2151 */
2152 rxretprd = *ap->rx_ret_prd;
2153 rxretcsm = ap->cur_rx;
2154
2155 if (rxretprd != rxretcsm)
2156 ace_rx_int(dev, rxretprd, rxretcsm);
2157
2158 txcsm = *ap->tx_csm;
2159 idx = ap->tx_ret_csm;
2160
2161 if (txcsm != idx) {
2162 /*
2163 * If each skb takes only one descriptor this check degenerates
2164 * to identity, because new space has just been opened.
2165 * But if skbs are fragmented we must check that this index
2166 * update releases enough of space, otherwise we just
2167 * wait for device to make more work.
2168 */
2169 if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2170 ace_tx_int(dev, txcsm, idx);
2171 }
2172
2173 evtcsm = readl(&regs->EvtCsm);
2174 evtprd = *ap->evt_prd;
2175
2176 if (evtcsm != evtprd) {
2177 evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2178 writel(evtcsm, &regs->EvtCsm);
2179 }
2180
2181 /*
2182 * This has to go last in the interrupt handler and run with
2183 * the spin lock released ... what lock?
2184 */
2185 if (netif_running(dev)) {
2186 int cur_size;
2187 int run_tasklet = 0;
2188
2189 cur_size = atomic_read(&ap->cur_rx_bufs);
2190 if (cur_size < RX_LOW_STD_THRES) {
2191 if ((cur_size < RX_PANIC_STD_THRES) &&
2192 !test_and_set_bit(0, &ap->std_refill_busy)) {
2193#ifdef DEBUG
2194 printk("low on std buffers %i\n", cur_size);
2195#endif
427e21fa 2196 ace_load_std_rx_ring(dev,
1da177e4
LT		 2197 RX_RING_SIZE - cur_size);
2198 } else
2199 run_tasklet = 1;
2200 }
2201
2202 if (!ACE_IS_TIGON_I(ap)) {
2203 cur_size = atomic_read(&ap->cur_mini_bufs);
2204 if (cur_size < RX_LOW_MINI_THRES) {
2205 if ((cur_size < RX_PANIC_MINI_THRES) &&
2206 !test_and_set_bit(0,
2207 &ap->mini_refill_busy)) {
2208#ifdef DEBUG
2209 printk("low on mini buffers %i\n",
2210 cur_size);
2211#endif
427e21fa 2212 ace_load_mini_rx_ring(dev,
2213 RX_MINI_SIZE - cur_size);
1da177e4
LT		 2214 } else
2215 run_tasklet = 1;
2216 }
2217 }
2218
2219 if (ap->jumbo) {
2220 cur_size = atomic_read(&ap->cur_jumbo_bufs);
2221 if (cur_size < RX_LOW_JUMBO_THRES) {
2222 if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2223 !test_and_set_bit(0,
2224 &ap->jumbo_refill_busy)){
2225#ifdef DEBUG
2226 printk("low on jumbo buffers %i\n",
2227 cur_size);
2228#endif
427e21fa 2229 ace_load_jumbo_rx_ring(dev,
2230 RX_JUMBO_SIZE - cur_size);
1da177e4
LT		 2231 } else
2232 run_tasklet = 1;
2233 }
2234 }
2235 if (run_tasklet && !ap->tasklet_pending) {
2236 ap->tasklet_pending = 1;
2237 tasklet_schedule(&ap->ace_tasklet);
2238 }
2239 }
2240
2241 return IRQ_HANDLED;
2242}
2243
1da177e4
LT		 2244static int ace_open(struct net_device *dev)
2245{
2246 struct ace_private *ap = netdev_priv(dev);
2247 struct ace_regs __iomem *regs = ap->regs;
2248 struct cmd cmd;
2249
2250 if (!(ap->fw_running)) {
2251 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2252 return -EBUSY;
2253 }
2254
2255 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2256
2257 cmd.evt = C_CLEAR_STATS;
2258 cmd.code = 0;
2259 cmd.idx = 0;
2260 ace_issue_cmd(regs, &cmd);
2261
2262 cmd.evt = C_HOST_STATE;
2263 cmd.code = C_C_STACK_UP;
2264 cmd.idx = 0;
2265 ace_issue_cmd(regs, &cmd);
2266
2267 if (ap->jumbo &&
2268 !test_and_set_bit(0, &ap->jumbo_refill_busy))
427e21fa 2269 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
1da177e4
LT		 2270
2271 if (dev->flags & IFF_PROMISC) {
2272 cmd.evt = C_SET_PROMISC_MODE;
2273 cmd.code = C_C_PROMISC_ENABLE;
2274 cmd.idx = 0;
2275 ace_issue_cmd(regs, &cmd);
2276
2277 ap->promisc = 1;
2278 }else
2279 ap->promisc = 0;
2280 ap->mcast_all = 0;
2281
2282#if 0
2283 cmd.evt = C_LNK_NEGOTIATION;
2284 cmd.code = 0;
2285 cmd.idx = 0;
2286 ace_issue_cmd(regs, &cmd);
2287#endif
2288
2289 netif_start_queue(dev);
2290
2291 /*
2292 * Setup the bottom half rx ring refill handler
2293 */
2294 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2295 return 0;
2296}
2297
2298
2299static int ace_close(struct net_device *dev)
2300{
2301 struct ace_private *ap = netdev_priv(dev);
2302 struct ace_regs __iomem *regs = ap->regs;
2303 struct cmd cmd;
2304 unsigned long flags;
2305 short i;
2306
2307 /*
2308 * Without (or before) releasing irq and stopping hardware, this
2309 * is an absolute non-sense, by the way. It will be reset instantly
2310 * by the first irq.
2311 */
2312 netif_stop_queue(dev);
2313
6aa20a22 2314
1da177e4
LT		 2315 if (ap->promisc) {
2316 cmd.evt = C_SET_PROMISC_MODE;
2317 cmd.code = C_C_PROMISC_DISABLE;
2318 cmd.idx = 0;
2319 ace_issue_cmd(regs, &cmd);
2320 ap->promisc = 0;
2321 }
2322
2323 cmd.evt = C_HOST_STATE;
2324 cmd.code = C_C_STACK_DOWN;
2325 cmd.idx = 0;
2326 ace_issue_cmd(regs, &cmd);
2327
2328 tasklet_kill(&ap->ace_tasklet);
2329
2330 /*
2331 * Make sure one CPU is not processing packets while
2332 * buffers are being released by another.
2333 */
2334
2335 local_irq_save(flags);
2336 ace_mask_irq(dev);
2337
2338 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2339 struct sk_buff *skb;
1da177e4
LT		 2340 struct tx_ring_info *info;
2341
2342 info = ap->skb->tx_skbuff + i;
2343 skb = info->skb;
1da177e4 2344
07e7de8f 2345 if (dma_unmap_len(info, maplen)) {
1da177e4 2346 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb
SH		 2347 /* NB: TIGON_1 is special, tx_ring is in io space */
2348 struct tx_desc __iomem *tx;
2349 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
1da177e4
LT		 2350 writel(0, &tx->addr.addrhi);
2351 writel(0, &tx->addr.addrlo);
2352 writel(0, &tx->flagsize);
2353 } else
2354 memset(ap->tx_ring + i, 0,
2355 sizeof(struct tx_desc));
07e7de8f 2356 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
430e55b1 2357 dma_unmap_len(info, maplen),
1da177e4 2358 PCI_DMA_TODEVICE);
07e7de8f 2359 dma_unmap_len_set(info, maplen, 0);
1da177e4
LT		 2360 }
2361 if (skb) {
2362 dev_kfree_skb(skb);
2363 info->skb = NULL;
2364 }
2365 }
2366
2367 if (ap->jumbo) {
2368 cmd.evt = C_RESET_JUMBO_RNG;
2369 cmd.code = 0;
2370 cmd.idx = 0;
2371 ace_issue_cmd(regs, &cmd);
2372 }
2373
2374 ace_unmask_irq(dev);
2375 local_irq_restore(flags);
2376
2377 return 0;
2378}
2379
2380
2381static inline dma_addr_t
2382ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2383 struct sk_buff *tail, u32 idx)
2384{
2385 dma_addr_t mapping;
2386 struct tx_ring_info *info;
2387
2388 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2389 offset_in_page(skb->data),
2390 skb->len, PCI_DMA_TODEVICE);
2391
2392 info = ap->skb->tx_skbuff + idx;
2393 info->skb = tail;
430e55b1
FT		 2394 dma_unmap_addr_set(info, mapping, mapping);
2395 dma_unmap_len_set(info, maplen, skb->len);
1da177e4
LT		 2396 return mapping;
2397}
2398
2399
2400static inline void
2401ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2402 u32 flagsize, u32 vlan_tag)
2403{
2404#if !USE_TX_COAL_NOW
2405 flagsize &= ~BD_FLG_COAL_NOW;
2406#endif
2407
2408 if (ACE_IS_TIGON_I(ap)) {
ddfce6bb 2409 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
1da177e4
LT		 2410 writel(addr >> 32, &io->addr.addrhi);
2411 writel(addr & 0xffffffff, &io->addr.addrlo);
2412 writel(flagsize, &io->flagsize);
1da177e4 2413 writel(vlan_tag, &io->vlanres);
1da177e4
LT		 2414 } else {
2415 desc->addr.addrhi = addr >> 32;
2416 desc->addr.addrlo = addr;
2417 desc->flagsize = flagsize;
1da177e4 2418 desc->vlanres = vlan_tag;
1da177e4
LT		 2419 }
2420}
2421
2422
61357325
SH		 2423static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2424 struct net_device *dev)
1da177e4
LT		 2425{
2426 struct ace_private *ap = netdev_priv(dev);
2427 struct ace_regs __iomem *regs = ap->regs;
2428 struct tx_desc *desc;
2429 u32 idx, flagsize;
2430 unsigned long maxjiff = jiffies + 3*HZ;
2431
2432restart:
2433 idx = ap->tx_prd;
2434
2435 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2436 goto overflow;
2437
2438 if (!skb_shinfo(skb)->nr_frags) {
2439 dma_addr_t mapping;
2440 u32 vlan_tag = 0;
2441
2442 mapping = ace_map_tx_skb(ap, skb, skb, idx);
2443 flagsize = (skb->len << 16) | (BD_FLG_END);
84fa7933 2444 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 2445 flagsize |= BD_FLG_TCP_UDP_SUM;
1da177e4
LT		 2446 if (vlan_tx_tag_present(skb)) {
2447 flagsize |= BD_FLG_VLAN_TAG;
2448 vlan_tag = vlan_tx_tag_get(skb);
2449 }
1da177e4
LT		 2450 desc = ap->tx_ring + idx;
2451 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2452
2453 /* Look at ace_tx_int for explanations. */
2454 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2455 flagsize |= BD_FLG_COAL_NOW;
2456
2457 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2458 } else {
2459 dma_addr_t mapping;
2460 u32 vlan_tag = 0;
2461 int i, len = 0;
2462
2463 mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2464 flagsize = (skb_headlen(skb) << 16);
84fa7933 2465 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4 2466 flagsize |= BD_FLG_TCP_UDP_SUM;
1da177e4
LT		 2467 if (vlan_tx_tag_present(skb)) {
2468 flagsize |= BD_FLG_VLAN_TAG;
2469 vlan_tag = vlan_tx_tag_get(skb);
2470 }
1da177e4
LT		 2471
2472 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2473
2474 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2475
2476 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 2477 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1da177e4
LT		 2478 struct tx_ring_info *info;
2479
9e903e08 2480 len += skb_frag_size(frag);
1da177e4
LT		 2481 info = ap->skb->tx_skbuff + idx;
2482 desc = ap->tx_ring + idx;
2483
c4c8d579 2484 mapping = skb_frag_dma_map(&ap->pdev->dev, frag, 0,
9e903e08 2485 skb_frag_size(frag),
5d6bcdfe 2486 DMA_TO_DEVICE);
1da177e4 2487
9e903e08 2488 flagsize = skb_frag_size(frag) << 16;
84fa7933 2489 if (skb->ip_summed == CHECKSUM_PARTIAL)
1da177e4
LT		 2490 flagsize |= BD_FLG_TCP_UDP_SUM;
2491 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2492
2493 if (i == skb_shinfo(skb)->nr_frags - 1) {
2494 flagsize |= BD_FLG_END;
2495 if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2496 flagsize |= BD_FLG_COAL_NOW;
2497
2498 /*
2499 * Only the last fragment frees
2500 * the skb!
2501 */
2502 info->skb = skb;
2503 } else {
2504 info->skb = NULL;
2505 }
430e55b1 2506 dma_unmap_addr_set(info, mapping, mapping);
9e903e08 2507 dma_unmap_len_set(info, maplen, skb_frag_size(frag));
1da177e4
LT		 2508 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2509 }
2510 }
2511
2512 wmb();
2513 ap->tx_prd = idx;
2514 ace_set_txprd(regs, ap, idx);
2515
2516 if (flagsize & BD_FLG_COAL_NOW) {
2517 netif_stop_queue(dev);
2518
2519 /*
2520 * A TX-descriptor producer (an IRQ) might have gotten
25985edc 2521 * between, making the ring free again. Since xmit is
1da177e4
LT		 2522 * serialized, this is the only situation we have to
2523 * re-test.
2524 */
2525 if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2526 netif_wake_queue(dev);
2527 }
2528
1da177e4
LT		 2529 return NETDEV_TX_OK;
2530
2531overflow:
2532 /*
2533 * This race condition is unavoidable with lock-free drivers.
2534 * We wake up the queue _before_ tx_prd is advanced, so that we can
2535 * enter hard_start_xmit too early, while tx ring still looks closed.
2536 * This happens ~1-4 times per 100000 packets, so that we can allow
2537 * to loop syncing to other CPU. Probably, we need an additional
2538 * wmb() in ace_tx_intr as well.
2539 *
2540 * Note that this race is relieved by reserving one more entry
2541 * in tx ring than it is necessary (see original non-SG driver).
2542 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2543 * is already overkill.
2544 *
2545 * Alternative is to return with 1 not throttling queue. In this
2546 * case loop becomes longer, no more useful effects.
2547 */
2548 if (time_before(jiffies, maxjiff)) {
2549 barrier();
2550 cpu_relax();
2551 goto restart;
2552 }
6aa20a22 2553
1da177e4
LT		 2554 /* The ring is stuck full. */
2555 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2556 return NETDEV_TX_BUSY;
2557}
2558
2559
2560static int ace_change_mtu(struct net_device *dev, int new_mtu)
2561{
2562 struct ace_private *ap = netdev_priv(dev);
2563 struct ace_regs __iomem *regs = ap->regs;
2564
2565 if (new_mtu > ACE_JUMBO_MTU)
2566 return -EINVAL;
2567
2568 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2569 dev->mtu = new_mtu;
2570
2571 if (new_mtu > ACE_STD_MTU) {
2572 if (!(ap->jumbo)) {
2573 printk(KERN_INFO "%s: Enabling Jumbo frame "
2574 "support\n", dev->name);
2575 ap->jumbo = 1;
2576 if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
427e21fa 2577 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
1da177e4
LT		 2578 ace_set_rxtx_parms(dev, 1);
2579 }
2580 } else {
2581 while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2582 ace_sync_irq(dev->irq);
2583 ace_set_rxtx_parms(dev, 0);
2584 if (ap->jumbo) {
2585 struct cmd cmd;
2586
2587 cmd.evt = C_RESET_JUMBO_RNG;
2588 cmd.code = 0;
2589 cmd.idx = 0;
2590 ace_issue_cmd(regs, &cmd);
2591 }
2592 }
2593
2594 return 0;
2595}
2596
2597static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2598{
2599 struct ace_private *ap = netdev_priv(dev);
2600 struct ace_regs __iomem *regs = ap->regs;
2601 u32 link;
2602
2603 memset(ecmd, 0, sizeof(struct ethtool_cmd));
2604 ecmd->supported =
2605 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2606 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2607 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2608 SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2609
2610 ecmd->port = PORT_FIBRE;
2611 ecmd->transceiver = XCVR_INTERNAL;
2612
2613 link = readl(&regs->GigLnkState);
2614 if (link & LNK_1000MB)
70739497 2615 ethtool_cmd_speed_set(ecmd, SPEED_1000);
1da177e4
LT		 2616 else {
2617 link = readl(&regs->FastLnkState);
2618 if (link & LNK_100MB)
70739497 2619 ethtool_cmd_speed_set(ecmd, SPEED_100);
1da177e4 2620 else if (link & LNK_10MB)
70739497 2621 ethtool_cmd_speed_set(ecmd, SPEED_10);
1da177e4 2622 else
70739497 2623 ethtool_cmd_speed_set(ecmd, 0);
1da177e4
LT		 2624 }
2625 if (link & LNK_FULL_DUPLEX)
2626 ecmd->duplex = DUPLEX_FULL;
2627 else
2628 ecmd->duplex = DUPLEX_HALF;
2629
2630 if (link & LNK_NEGOTIATE)
2631 ecmd->autoneg = AUTONEG_ENABLE;
2632 else
2633 ecmd->autoneg = AUTONEG_DISABLE;
2634
2635#if 0
2636 /*
2637 * Current struct ethtool_cmd is insufficient
2638 */
2639 ecmd->trace = readl(&regs->TuneTrace);
2640
2641 ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2642 ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2643#endif
2644 ecmd->maxtxpkt = readl(&regs->TuneMaxTxDesc);
2645 ecmd->maxrxpkt = readl(&regs->TuneMaxRxDesc);
2646
2647 return 0;
2648}
2649
2650static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2651{
2652 struct ace_private *ap = netdev_priv(dev);
2653 struct ace_regs __iomem *regs = ap->regs;
2654 u32 link, speed;
2655
2656 link = readl(&regs->GigLnkState);
2657 if (link & LNK_1000MB)
2658 speed = SPEED_1000;
2659 else {
2660 link = readl(&regs->FastLnkState);
2661 if (link & LNK_100MB)
2662 speed = SPEED_100;
2663 else if (link & LNK_10MB)
2664 speed = SPEED_10;
2665 else
2666 speed = SPEED_100;
2667 }
2668
2669 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2670 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2671 if (!ACE_IS_TIGON_I(ap))
2672 link |= LNK_TX_FLOW_CTL_Y;
2673 if (ecmd->autoneg == AUTONEG_ENABLE)
2674 link |= LNK_NEGOTIATE;
25db0338 2675 if (ethtool_cmd_speed(ecmd) != speed) {
1da177e4 2676 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
1258c076 2677 switch (ethtool_cmd_speed(ecmd)) {
1da177e4
LT		 2678 case SPEED_1000:
2679 link |= LNK_1000MB;
2680 break;
2681 case SPEED_100:
2682 link |= LNK_100MB;
2683 break;
2684 case SPEED_10:
2685 link |= LNK_10MB;
2686 break;
2687 }
2688 }
2689
2690 if (ecmd->duplex == DUPLEX_FULL)
2691 link |= LNK_FULL_DUPLEX;
2692
2693 if (link != ap->link) {
2694 struct cmd cmd;
2695 printk(KERN_INFO "%s: Renegotiating link state\n",
2696 dev->name);
2697
2698 ap->link = link;
2699 writel(link, &regs->TuneLink);
2700 if (!ACE_IS_TIGON_I(ap))
2701 writel(link, &regs->TuneFastLink);
2702 wmb();
2703
2704 cmd.evt = C_LNK_NEGOTIATION;
2705 cmd.code = 0;
2706 cmd.idx = 0;
2707 ace_issue_cmd(regs, &cmd);
2708 }
2709 return 0;
2710}
2711
6aa20a22 2712static void ace_get_drvinfo(struct net_device *dev,
1da177e4
LT		 2713 struct ethtool_drvinfo *info)
2714{
2715 struct ace_private *ap = netdev_priv(dev);
2716
2717 strlcpy(info->driver, "acenic", sizeof(info->driver));
6aa20a22 2718 snprintf(info->version, sizeof(info->version), "%i.%i.%i",
949b4254
JS		 2719 ap->firmware_major, ap->firmware_minor,
2720 ap->firmware_fix);
1da177e4
LT		 2721
2722 if (ap->pdev)
6aa20a22 2723 strlcpy(info->bus_info, pci_name(ap->pdev),
1da177e4
LT		 2724 sizeof(info->bus_info));
2725
2726}
2727
2728/*
2729 * Set the hardware MAC address.
2730 */
2731static int ace_set_mac_addr(struct net_device *dev, void *p)
2732{
2733 struct ace_private *ap = netdev_priv(dev);
2734 struct ace_regs __iomem *regs = ap->regs;
2735 struct sockaddr *addr=p;
2736 u8 *da;
2737 struct cmd cmd;
2738
2739 if(netif_running(dev))
2740 return -EBUSY;
2741
2742 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2743
2744 da = (u8 *)dev->dev_addr;
2745
2746 writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2747 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2748 &regs->MacAddrLo);
2749
2750 cmd.evt = C_SET_MAC_ADDR;
2751 cmd.code = 0;
2752 cmd.idx = 0;
2753 ace_issue_cmd(regs, &cmd);
2754
2755 return 0;
2756}
2757
2758
2759static void ace_set_multicast_list(struct net_device *dev)
2760{
2761 struct ace_private *ap = netdev_priv(dev);
2762 struct ace_regs __iomem *regs = ap->regs;
2763 struct cmd cmd;
2764
2765 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2766 cmd.evt = C_SET_MULTICAST_MODE;
2767 cmd.code = C_C_MCAST_ENABLE;
2768 cmd.idx = 0;
2769 ace_issue_cmd(regs, &cmd);
2770 ap->mcast_all = 1;
2771 } else if (ap->mcast_all) {
2772 cmd.evt = C_SET_MULTICAST_MODE;
2773 cmd.code = C_C_MCAST_DISABLE;
2774 cmd.idx = 0;
2775 ace_issue_cmd(regs, &cmd);
2776 ap->mcast_all = 0;
2777 }
2778
2779 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2780 cmd.evt = C_SET_PROMISC_MODE;
2781 cmd.code = C_C_PROMISC_ENABLE;
2782 cmd.idx = 0;
2783 ace_issue_cmd(regs, &cmd);
2784 ap->promisc = 1;
2785 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2786 cmd.evt = C_SET_PROMISC_MODE;
2787 cmd.code = C_C_PROMISC_DISABLE;
2788 cmd.idx = 0;
2789 ace_issue_cmd(regs, &cmd);
2790 ap->promisc = 0;
2791 }
2792
2793 /*
2794 * For the time being multicast relies on the upper layers
2795 * filtering it properly. The Firmware does not allow one to
2796 * set the entire multicast list at a time and keeping track of
2797 * it here is going to be messy.
2798 */
4cd24eaf 2799 if (!netdev_mc_empty(dev) && !ap->mcast_all) {
1da177e4
LT		 2800 cmd.evt = C_SET_MULTICAST_MODE;
2801 cmd.code = C_C_MCAST_ENABLE;
2802 cmd.idx = 0;
2803 ace_issue_cmd(regs, &cmd);
2804 }else if (!ap->mcast_all) {
2805 cmd.evt = C_SET_MULTICAST_MODE;
2806 cmd.code = C_C_MCAST_DISABLE;
2807 cmd.idx = 0;
2808 ace_issue_cmd(regs, &cmd);
2809 }
2810}
2811
2812
2813static struct net_device_stats *ace_get_stats(struct net_device *dev)
2814{
2815 struct ace_private *ap = netdev_priv(dev);
2816 struct ace_mac_stats __iomem *mac_stats =
2817 (struct ace_mac_stats __iomem *)ap->regs->Stats;
2818
966e37bc
PZ		 2819 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2820 dev->stats.multicast = readl(&mac_stats->kept_mc);
2821 dev->stats.collisions = readl(&mac_stats->coll);
1da177e4 2822
966e37bc 2823 return &dev->stats;
1da177e4
LT		 2824}
2825
2826
083abbb7 2827static void ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
1dd06ae8 2828 u32 dest, int size)
1da177e4
LT		 2829{
2830 void __iomem *tdest;
1da177e4
LT		 2831 short tsize, i;
2832
2833 if (size <= 0)
2834 return;
2835
2836 while (size > 0) {
2837 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2838 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2839 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2840 (dest & (ACE_WINDOW_SIZE - 1));
2841 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
1da177e4 2842 for (i = 0; i < (tsize / 4); i++) {
949b4254
JS		 2843 /* Firmware is big-endian */
2844 writel(be32_to_cpup(src), tdest);
2845 src++;
2846 tdest += 4;
2847 dest += 4;
2848 size -= 4;
1da177e4 2849 }
1da177e4 2850 }
1da177e4
LT		 2851}
2852
2853
083abbb7 2854static void ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
1da177e4
LT		 2855{
2856 void __iomem *tdest;
2857 short tsize = 0, i;
2858
2859 if (size <= 0)
2860 return;
2861
2862 while (size > 0) {
2863 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2864 min_t(u32, size, ACE_WINDOW_SIZE));
6aa20a22 2865 tdest = (void __iomem *) &regs->Window +
1da177e4
LT		 2866 (dest & (ACE_WINDOW_SIZE - 1));
2867 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2868
2869 for (i = 0; i < (tsize / 4); i++) {
2870 writel(0, tdest + i*4);
2871 }
2872
2873 dest += tsize;
2874 size -= tsize;
2875 }
1da177e4
LT		 2876}
2877
2878
2879/*
2880 * Download the firmware into the SRAM on the NIC
2881 *
2882 * This operation requires the NIC to be halted and is performed with
2883 * interrupts disabled and with the spinlock hold.
2884 */
083abbb7 2885static int ace_load_firmware(struct net_device *dev)
1da177e4 2886{
949b4254
JS		 2887 const struct firmware *fw;
2888 const char *fw_name = "acenic/tg2.bin";
1da177e4
LT		 2889 struct ace_private *ap = netdev_priv(dev);
2890 struct ace_regs __iomem *regs = ap->regs;
949b4254
JS		 2891 const __be32 *fw_data;
2892 u32 load_addr;
2893 int ret;
1da177e4
LT		 2894
2895 if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2896 printk(KERN_ERR "%s: trying to download firmware while the "
2897 "CPU is running!\n", ap->name);
2898 return -EFAULT;
2899 }
2900
949b4254
JS		 2901 if (ACE_IS_TIGON_I(ap))
2902 fw_name = "acenic/tg1.bin";
2903
2904 ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2905 if (ret) {
2906 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2907 ap->name, fw_name);
2908 return ret;
2909 }
2910
2911 fw_data = (void *)fw->data;
2912
2913 /* Firmware blob starts with version numbers, followed by
2914 load and start address. Remainder is the blob to be loaded
2915 contiguously from load address. We don't bother to represent
2916 the BSS/SBSS sections any more, since we were clearing the
2917 whole thing anyway. */
2918 ap->firmware_major = fw->data[0];
2919 ap->firmware_minor = fw->data[1];
2920 ap->firmware_fix = fw->data[2];
2921
2922 ap->firmware_start = be32_to_cpu(fw_data[1]);
2923 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2924 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2925 ap->name, ap->firmware_start, fw_name);
2926 ret = -EINVAL;
2927 goto out;
2928 }
2929
2930 load_addr = be32_to_cpu(fw_data[2]);
2931 if (load_addr < 0x4000 || load_addr >= 0x80000) {
2932 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2933 ap->name, load_addr, fw_name);
2934 ret = -EINVAL;
2935 goto out;
2936 }
2937
1da177e4 2938 /*
949b4254
JS		 2939 * Do not try to clear more than 512KiB or we end up seeing
2940 * funny things on NICs with only 512KiB SRAM
1da177e4
LT		 2941 */
2942 ace_clear(regs, 0x2000, 0x80000-0x2000);
949b4254
JS		 2943 ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2944 out:
2945 release_firmware(fw);
2946 return ret;
1da177e4
LT		 2947}
2948
2949
2950/*
2951 * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2952 *
2953 * Accessing the EEPROM is `interesting' to say the least - don't read
2954 * this code right after dinner.
2955 *
2956 * This is all about black magic and bit-banging the device .... I
2957 * wonder in what hospital they have put the guy who designed the i2c
2958 * specs.
2959 *
2960 * Oh yes, this is only the beginning!
2961 *
2962 * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2963 * code i2c readout code by beta testing all my hacks.
2964 */
083abbb7 2965static void eeprom_start(struct ace_regs __iomem *regs)
1da177e4
LT		 2966{
2967 u32 local;
2968
2969 readl(&regs->LocalCtrl);
2970 udelay(ACE_SHORT_DELAY);
2971 local = readl(&regs->LocalCtrl);
2972 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2973 writel(local, &regs->LocalCtrl);
2974 readl(&regs->LocalCtrl);
2975 mb();
2976 udelay(ACE_SHORT_DELAY);
2977 local |= EEPROM_CLK_OUT;
2978 writel(local, &regs->LocalCtrl);
2979 readl(&regs->LocalCtrl);
2980 mb();
2981 udelay(ACE_SHORT_DELAY);
2982 local &= ~EEPROM_DATA_OUT;
2983 writel(local, &regs->LocalCtrl);
2984 readl(&regs->LocalCtrl);
2985 mb();
2986 udelay(ACE_SHORT_DELAY);
2987 local &= ~EEPROM_CLK_OUT;
2988 writel(local, &regs->LocalCtrl);
2989 readl(&regs->LocalCtrl);
2990 mb();
2991}
2992
2993
083abbb7 2994static void eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
1da177e4
LT		 2995{
2996 short i;
2997 u32 local;
2998
2999 udelay(ACE_SHORT_DELAY);
3000 local = readl(&regs->LocalCtrl);
3001 local &= ~EEPROM_DATA_OUT;
3002 local |= EEPROM_WRITE_ENABLE;
3003 writel(local, &regs->LocalCtrl);
3004 readl(&regs->LocalCtrl);
3005 mb();
3006
3007 for (i = 0; i < 8; i++, magic <<= 1) {
3008 udelay(ACE_SHORT_DELAY);
6aa20a22 3009 if (magic & 0x80)
1da177e4
LT		 3010 local |= EEPROM_DATA_OUT;
3011 else
3012 local &= ~EEPROM_DATA_OUT;
3013 writel(local, &regs->LocalCtrl);
3014 readl(&regs->LocalCtrl);
3015 mb();
3016
3017 udelay(ACE_SHORT_DELAY);
3018 local |= EEPROM_CLK_OUT;
3019 writel(local, &regs->LocalCtrl);
3020 readl(&regs->LocalCtrl);
3021 mb();
3022 udelay(ACE_SHORT_DELAY);
3023 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3024 writel(local, &regs->LocalCtrl);
3025 readl(&regs->LocalCtrl);
3026 mb();
3027 }
3028}
3029
3030
083abbb7 3031static int eeprom_check_ack(struct ace_regs __iomem *regs)
1da177e4
LT		 3032{
3033 int state;
3034 u32 local;
3035
3036 local = readl(&regs->LocalCtrl);
3037 local &= ~EEPROM_WRITE_ENABLE;
3038 writel(local, &regs->LocalCtrl);
3039 readl(&regs->LocalCtrl);
3040 mb();
3041 udelay(ACE_LONG_DELAY);
3042 local |= EEPROM_CLK_OUT;
3043 writel(local, &regs->LocalCtrl);
3044 readl(&regs->LocalCtrl);
3045 mb();
3046 udelay(ACE_SHORT_DELAY);
3047 /* sample data in middle of high clk */
3048 state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3049 udelay(ACE_SHORT_DELAY);
3050 mb();
3051 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3052 readl(&regs->LocalCtrl);
3053 mb();
3054
3055 return state;
3056}
3057
3058
083abbb7 3059static void eeprom_stop(struct ace_regs __iomem *regs)
1da177e4
LT		 3060{
3061 u32 local;
3062
3063 udelay(ACE_SHORT_DELAY);
3064 local = readl(&regs->LocalCtrl);
3065 local |= EEPROM_WRITE_ENABLE;
3066 writel(local, &regs->LocalCtrl);
3067 readl(&regs->LocalCtrl);
3068 mb();
3069 udelay(ACE_SHORT_DELAY);
3070 local &= ~EEPROM_DATA_OUT;
3071 writel(local, &regs->LocalCtrl);
3072 readl(&regs->LocalCtrl);
3073 mb();
3074 udelay(ACE_SHORT_DELAY);
3075 local |= EEPROM_CLK_OUT;
3076 writel(local, &regs->LocalCtrl);
3077 readl(&regs->LocalCtrl);
3078 mb();
3079 udelay(ACE_SHORT_DELAY);
3080 local |= EEPROM_DATA_OUT;
3081 writel(local, &regs->LocalCtrl);
3082 readl(&regs->LocalCtrl);
3083 mb();
3084 udelay(ACE_LONG_DELAY);
3085 local &= ~EEPROM_CLK_OUT;
3086 writel(local, &regs->LocalCtrl);
3087 mb();
3088}
3089
3090
3091/*
3092 * Read a whole byte from the EEPROM.
3093 */
1dd06ae8 3094static int read_eeprom_byte(struct net_device *dev, unsigned long offset)
1da177e4
LT		 3095{
3096 struct ace_private *ap = netdev_priv(dev);
3097 struct ace_regs __iomem *regs = ap->regs;
3098 unsigned long flags;
3099 u32 local;
3100 int result = 0;
3101 short i;
3102
1da177e4
LT		 3103 /*
3104 * Don't take interrupts on this CPU will bit banging
3105 * the %#%#@$ I2C device
3106 */
3107 local_irq_save(flags);
3108
3109 eeprom_start(regs);
3110
3111 eeprom_prep(regs, EEPROM_WRITE_SELECT);
3112 if (eeprom_check_ack(regs)) {
3113 local_irq_restore(flags);
3114 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3115 result = -EIO;
3116 goto eeprom_read_error;
3117 }
3118
3119 eeprom_prep(regs, (offset >> 8) & 0xff);
3120 if (eeprom_check_ack(regs)) {
3121 local_irq_restore(flags);
3122 printk(KERN_ERR "%s: Unable to set address byte 0\n",
3123 ap->name);
3124 result = -EIO;
3125 goto eeprom_read_error;
3126 }
3127
3128 eeprom_prep(regs, offset & 0xff);
3129 if (eeprom_check_ack(regs)) {
3130 local_irq_restore(flags);
3131 printk(KERN_ERR "%s: Unable to set address byte 1\n",
3132 ap->name);
3133 result = -EIO;
3134 goto eeprom_read_error;
3135 }
3136
3137 eeprom_start(regs);
3138 eeprom_prep(regs, EEPROM_READ_SELECT);
3139 if (eeprom_check_ack(regs)) {
3140 local_irq_restore(flags);
3141 printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3142 ap->name);
3143 result = -EIO;
3144 goto eeprom_read_error;
3145 }
3146
3147 for (i = 0; i < 8; i++) {
3148 local = readl(&regs->LocalCtrl);
3149 local &= ~EEPROM_WRITE_ENABLE;
3150 writel(local, &regs->LocalCtrl);
3151 readl(&regs->LocalCtrl);
3152 udelay(ACE_LONG_DELAY);
3153 mb();
3154 local |= EEPROM_CLK_OUT;
3155 writel(local, &regs->LocalCtrl);
3156 readl(&regs->LocalCtrl);
3157 mb();
3158 udelay(ACE_SHORT_DELAY);
3159 /* sample data mid high clk */
3160 result = (result << 1) |
3161 ((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3162 udelay(ACE_SHORT_DELAY);
3163 mb();
3164 local = readl(&regs->LocalCtrl);
3165 local &= ~EEPROM_CLK_OUT;
3166 writel(local, &regs->LocalCtrl);
3167 readl(&regs->LocalCtrl);
3168 udelay(ACE_SHORT_DELAY);
3169 mb();
3170 if (i == 7) {
3171 local |= EEPROM_WRITE_ENABLE;
3172 writel(local, &regs->LocalCtrl);
3173 readl(&regs->LocalCtrl);
3174 mb();
3175 udelay(ACE_SHORT_DELAY);
3176 }
3177 }
3178
3179 local |= EEPROM_DATA_OUT;
3180 writel(local, &regs->LocalCtrl);
3181 readl(&regs->LocalCtrl);
3182 mb();
3183 udelay(ACE_SHORT_DELAY);
3184 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3185 readl(&regs->LocalCtrl);
3186 udelay(ACE_LONG_DELAY);
3187 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3188 readl(&regs->LocalCtrl);
3189 mb();
3190 udelay(ACE_SHORT_DELAY);
3191 eeprom_stop(regs);
3192
3193 local_irq_restore(flags);
3194 out:
3195 return result;
3196
3197 eeprom_read_error:
3198 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3199 ap->name, offset);
3200 goto out;
3201}
Linux kernel - Deliverables
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