[deliverable/linux.git] / drivers / net / ethernet / altera / altera_msgdma.c

/* Altera TSE SGDMA and MSGDMA Linux driver
 * Copyright (C) 2014 Altera Corporation. All rights reserved
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/netdevice.h>
#include "altera_utils.h"
#include "altera_tse.h"
#include "altera_msgdmahw.h"
#include "altera_msgdma.h"

/* No initialization work to do for MSGDMA */
int msgdma_initialize(struct altera_tse_private *priv)
{
	return 0;
}

void msgdma_uninitialize(struct altera_tse_private *priv)
{
}

void msgdma_start_rxdma(struct altera_tse_private *priv)
{
}

void msgdma_reset(struct altera_tse_private *priv)
{
	int counter;

	/* Reset Rx mSGDMA */
	csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
		msgdma_csroffs(status));
	csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
		msgdma_csroffs(control));

	counter = 0;
	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
		if (tse_bit_is_clear(priv->rx_dma_csr, msgdma_csroffs(status),
				     MSGDMA_CSR_STAT_RESETTING))
			break;
		udelay(1);
	}

	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
		netif_warn(priv, drv, priv->dev,
			   "TSE Rx mSGDMA resetting bit never cleared!\n");

	/* clear all status bits */
	csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));

	/* Reset Tx mSGDMA */
	csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
		msgdma_csroffs(status));

	csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
		msgdma_csroffs(control));

	counter = 0;
	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
		if (tse_bit_is_clear(priv->tx_dma_csr, msgdma_csroffs(status),
				     MSGDMA_CSR_STAT_RESETTING))
			break;
		udelay(1);
	}

	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
		netif_warn(priv, drv, priv->dev,
			   "TSE Tx mSGDMA resetting bit never cleared!\n");

	/* clear all status bits */
	csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
}

void msgdma_disable_rxirq(struct altera_tse_private *priv)
{
	tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control),
		      MSGDMA_CSR_CTL_GLOBAL_INTR);
}

void msgdma_enable_rxirq(struct altera_tse_private *priv)
{
	tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control),
		    MSGDMA_CSR_CTL_GLOBAL_INTR);
}

void msgdma_disable_txirq(struct altera_tse_private *priv)
{
	tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control),
		      MSGDMA_CSR_CTL_GLOBAL_INTR);
}

void msgdma_enable_txirq(struct altera_tse_private *priv)
{
	tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control),
		    MSGDMA_CSR_CTL_GLOBAL_INTR);
}

void msgdma_clear_rxirq(struct altera_tse_private *priv)
{
	csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
}

void msgdma_clear_txirq(struct altera_tse_private *priv)
{
	csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
}

/* return 0 to indicate transmit is pending */
int msgdma_tx_buffer(struct altera_tse_private *priv, struct tse_buffer *buffer)
{
	csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
		msgdma_descroffs(read_addr_lo));
	csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
		msgdma_descroffs(read_addr_hi));
	csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
	csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
	csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
	csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
	csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
		msgdma_descroffs(stride));
	csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
		msgdma_descroffs(control));
	return 0;
}

u32 msgdma_tx_completions(struct altera_tse_private *priv)
{
	u32 ready = 0;
	u32 inuse;
	u32 status;

	/* Get number of sent descriptors */
	inuse = csrrd32(priv->tx_dma_csr, msgdma_csroffs(rw_fill_level))
			& 0xffff;

	if (inuse) { /* Tx FIFO is not empty */
		ready = priv->tx_prod - priv->tx_cons - inuse - 1;
	} else {
		/* Check for buffered last packet */
		status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
		if (status & MSGDMA_CSR_STAT_BUSY)
			ready = priv->tx_prod - priv->tx_cons - 1;
		else
			ready = priv->tx_prod - priv->tx_cons;
	}
	return ready;
}

/* Put buffer to the mSGDMA RX FIFO
 */
void msgdma_add_rx_desc(struct altera_tse_private *priv,
			struct tse_buffer *rxbuffer)
{
	u32 len = priv->rx_dma_buf_sz;
	dma_addr_t dma_addr = rxbuffer->dma_addr;
	u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
			| MSGDMA_DESC_CTL_END_ON_LEN
			| MSGDMA_DESC_CTL_TR_COMP_IRQ
			| MSGDMA_DESC_CTL_EARLY_IRQ
			| MSGDMA_DESC_CTL_TR_ERR_IRQ
			| MSGDMA_DESC_CTL_GO);

	csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
	csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
	csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
		msgdma_descroffs(write_addr_lo));
	csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
		msgdma_descroffs(write_addr_hi));
	csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
	csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
	csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
	csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
}

/* status is returned on upper 16 bits,
 * length is returned in lower 16 bits
 */
u32 msgdma_rx_status(struct altera_tse_private *priv)
{
	u32 rxstatus = 0;
	u32 pktlength;
	u32 pktstatus;

	if (csrrd32(priv->rx_dma_csr, msgdma_csroffs(resp_fill_level))
	    & 0xffff) {
		pktlength = csrrd32(priv->rx_dma_resp,
				    msgdma_respoffs(bytes_transferred));
		pktstatus = csrrd32(priv->rx_dma_resp,
				    msgdma_respoffs(status));
		rxstatus = pktstatus;
		rxstatus = rxstatus << 16;
		rxstatus |= (pktlength & 0xffff);
	}
	return rxstatus;
}
Commit	Line	Data
94fb0ef4 VB	1	/* Altera TSE SGDMA and MSGDMA Linux driver
	2	* Copyright (C) 2014 Altera Corporation. All rights reserved
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License along with
	14	* this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#include <linux/netdevice.h>
	18	#include "altera_utils.h"
	19	#include "altera_tse.h"
	20	#include "altera_msgdmahw.h"
652f99ea	21	#include "altera_msgdma.h"
94fb0ef4 VB	22
	23	/* No initialization work to do for MSGDMA */
	24	int msgdma_initialize(struct altera_tse_private *priv)
	25	{
	26	return 0;
	27	}
	28
	29	void msgdma_uninitialize(struct altera_tse_private *priv)
	30	{
	31	}
	32
37c0ffaa VB	33	void msgdma_start_rxdma(struct altera_tse_private *priv)
	34	{
	35	}
	36
94fb0ef4 VB	37	void msgdma_reset(struct altera_tse_private *priv)
	38	{
	39	int counter;
94fb0ef4 VB	40
94fb0ef4 VB	41	/* Reset Rx mSGDMA */
89830580 VB	42	csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr,
	43	msgdma_csroffs(status));
	44	csrwr32(MSGDMA_CSR_CTL_RESET, priv->rx_dma_csr,
	45	msgdma_csroffs(control));
94fb0ef4 VB	46
	47	counter = 0;
	48	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
89830580	49	if (tse_bit_is_clear(priv->rx_dma_csr, msgdma_csroffs(status),
94fb0ef4 VB	50	MSGDMA_CSR_STAT_RESETTING))
	51	break;
	52	udelay(1);
	53	}
	54
	55	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
	56	netif_warn(priv, drv, priv->dev,
	57	"TSE Rx mSGDMA resetting bit never cleared!\n");
	58
	59	/* clear all status bits */
89830580	60	csrwr32(MSGDMA_CSR_STAT_MASK, priv->rx_dma_csr, msgdma_csroffs(status));
94fb0ef4 VB	61
94fb0ef4 VB	62	/* Reset Tx mSGDMA */
89830580 VB	63	csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr,
	64	msgdma_csroffs(status));
	65
	66	csrwr32(MSGDMA_CSR_CTL_RESET, priv->tx_dma_csr,
	67	msgdma_csroffs(control));
94fb0ef4 VB	68
	69	counter = 0;
	70	while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
89830580	71	if (tse_bit_is_clear(priv->tx_dma_csr, msgdma_csroffs(status),
94fb0ef4 VB	72	MSGDMA_CSR_STAT_RESETTING))
	73	break;
	74	udelay(1);
	75	}
	76
	77	if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR)
	78	netif_warn(priv, drv, priv->dev,
	79	"TSE Tx mSGDMA resetting bit never cleared!\n");
	80
	81	/* clear all status bits */
89830580	82	csrwr32(MSGDMA_CSR_STAT_MASK, priv->tx_dma_csr, msgdma_csroffs(status));
94fb0ef4 VB	83	}
	84
	85	void msgdma_disable_rxirq(struct altera_tse_private *priv)
	86	{
89830580 VB	87	tse_clear_bit(priv->rx_dma_csr, msgdma_csroffs(control),
89830580 VB	88	MSGDMA_CSR_CTL_GLOBAL_INTR);
94fb0ef4 VB	89	}
	90
	91	void msgdma_enable_rxirq(struct altera_tse_private *priv)
	92	{
89830580 VB	93	tse_set_bit(priv->rx_dma_csr, msgdma_csroffs(control),
89830580 VB	94	MSGDMA_CSR_CTL_GLOBAL_INTR);
94fb0ef4 VB	95	}
	96
	97	void msgdma_disable_txirq(struct altera_tse_private *priv)
	98	{
89830580 VB	99	tse_clear_bit(priv->tx_dma_csr, msgdma_csroffs(control),
89830580 VB	100	MSGDMA_CSR_CTL_GLOBAL_INTR);
94fb0ef4 VB	101	}
	102
	103	void msgdma_enable_txirq(struct altera_tse_private *priv)
	104	{
89830580 VB	105	tse_set_bit(priv->tx_dma_csr, msgdma_csroffs(control),
89830580 VB	106	MSGDMA_CSR_CTL_GLOBAL_INTR);
94fb0ef4 VB	107	}
	108
	109	void msgdma_clear_rxirq(struct altera_tse_private *priv)
	110	{
89830580	111	csrwr32(MSGDMA_CSR_STAT_IRQ, priv->rx_dma_csr, msgdma_csroffs(status));
94fb0ef4 VB	112	}
	113
	114	void msgdma_clear_txirq(struct altera_tse_private *priv)
	115	{
89830580	116	csrwr32(MSGDMA_CSR_STAT_IRQ, priv->tx_dma_csr, msgdma_csroffs(status));
94fb0ef4 VB	117	}
	118
	119	/* return 0 to indicate transmit is pending */
	120	int msgdma_tx_buffer(struct altera_tse_private priv, struct tse_buffer buffer)
	121	{
89830580 VB	122	csrwr32(lower_32_bits(buffer->dma_addr), priv->tx_dma_desc,
	123	msgdma_descroffs(read_addr_lo));
	124	csrwr32(upper_32_bits(buffer->dma_addr), priv->tx_dma_desc,
	125	msgdma_descroffs(read_addr_hi));
	126	csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_lo));
	127	csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(write_addr_hi));
	128	csrwr32(buffer->len, priv->tx_dma_desc, msgdma_descroffs(len));
	129	csrwr32(0, priv->tx_dma_desc, msgdma_descroffs(burst_seq_num));
	130	csrwr32(MSGDMA_DESC_TX_STRIDE, priv->tx_dma_desc,
	131	msgdma_descroffs(stride));
	132	csrwr32(MSGDMA_DESC_CTL_TX_SINGLE, priv->tx_dma_desc,
	133	msgdma_descroffs(control));
94fb0ef4 VB	134	return 0;
	135	}
	136
	137	u32 msgdma_tx_completions(struct altera_tse_private *priv)
	138	{
	139	u32 ready = 0;
	140	u32 inuse;
	141	u32 status;
94fb0ef4 VB	142
94fb0ef4 VB	143	/* Get number of sent descriptors */
89830580 VB	144	inuse = csrrd32(priv->tx_dma_csr, msgdma_csroffs(rw_fill_level))
89830580 VB	145	& 0xffff;
94fb0ef4 VB	146
	147	if (inuse) { /* Tx FIFO is not empty */
	148	ready = priv->tx_prod - priv->tx_cons - inuse - 1;
	149	} else {
	150	/* Check for buffered last packet */
89830580	151	status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
94fb0ef4 VB	152	if (status & MSGDMA_CSR_STAT_BUSY)
	153	ready = priv->tx_prod - priv->tx_cons - 1;
	154	else
	155	ready = priv->tx_prod - priv->tx_cons;
	156	}
	157	return ready;
	158	}
	159
	160	/* Put buffer to the mSGDMA RX FIFO
	161	*/
37c0ffaa	162	void msgdma_add_rx_desc(struct altera_tse_private *priv,
94fb0ef4 VB	163	struct tse_buffer *rxbuffer)
94fb0ef4 VB	164	{
94fb0ef4 VB	165	u32 len = priv->rx_dma_buf_sz;
	166	dma_addr_t dma_addr = rxbuffer->dma_addr;
	167	u32 control = (MSGDMA_DESC_CTL_END_ON_EOP
	168	\| MSGDMA_DESC_CTL_END_ON_LEN
	169	\| MSGDMA_DESC_CTL_TR_COMP_IRQ
	170	\| MSGDMA_DESC_CTL_EARLY_IRQ
	171	\| MSGDMA_DESC_CTL_TR_ERR_IRQ
	172	\| MSGDMA_DESC_CTL_GO);
	173
89830580 VB	174	csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_lo));
	175	csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(read_addr_hi));
	176	csrwr32(lower_32_bits(dma_addr), priv->rx_dma_desc,
	177	msgdma_descroffs(write_addr_lo));
	178	csrwr32(upper_32_bits(dma_addr), priv->rx_dma_desc,
	179	msgdma_descroffs(write_addr_hi));
	180	csrwr32(len, priv->rx_dma_desc, msgdma_descroffs(len));
	181	csrwr32(0, priv->rx_dma_desc, msgdma_descroffs(burst_seq_num));
	182	csrwr32(0x00010001, priv->rx_dma_desc, msgdma_descroffs(stride));
	183	csrwr32(control, priv->rx_dma_desc, msgdma_descroffs(control));
94fb0ef4 VB	184	}
	185
	186	/* status is returned on upper 16 bits,
	187	* length is returned in lower 16 bits
	188	*/
	189	u32 msgdma_rx_status(struct altera_tse_private *priv)
	190	{
	191	u32 rxstatus = 0;
	192	u32 pktlength;
	193	u32 pktstatus;
89830580 VB	194
	195	if (csrrd32(priv->rx_dma_csr, msgdma_csroffs(resp_fill_level))
	196	& 0xffff) {
	197	pktlength = csrrd32(priv->rx_dma_resp,
	198	msgdma_respoffs(bytes_transferred));
	199	pktstatus = csrrd32(priv->rx_dma_resp,
	200	msgdma_respoffs(status));
94fb0ef4 VB	201	rxstatus = pktstatus;
	202	rxstatus = rxstatus << 16;
	203	rxstatus \|= (pktlength & 0xffff);
	204	}
	205	return rxstatus;
	206	}