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rtnetlink: wait for unregistering devices in rtnl_link_unregister()
[deliverable/linux.git] / drivers / net / ethernet / altera / altera_tse_main.c
CommitLineData
bbd2190c
VB		 1/* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
3 *
4 * Contributors:
5 * Dalon Westergreen
6 * Thomas Chou
7 * Ian Abbott
8 * Yuriy Kozlov
9 * Tobias Klauser
10 * Andriy Smolskyy
11 * Roman Bulgakov
12 * Dmytro Mytarchuk
13 * Matthew Gerlach
14 *
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
21 *
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
25 * more details.
26 *
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31#include <linux/atomic.h>
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/if_vlan.h>
35#include <linux/init.h>
36#include <linux/interrupt.h>
37#include <linux/io.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/of_device.h>
42#include <linux/of_mdio.h>
43#include <linux/of_net.h>
44#include <linux/of_platform.h>
45#include <linux/phy.h>
46#include <linux/platform_device.h>
47#include <linux/skbuff.h>
48#include <asm/cacheflush.h>
49
50#include "altera_utils.h"
51#include "altera_tse.h"
52#include "altera_sgdma.h"
53#include "altera_msgdma.h"
54
55static atomic_t instance_count = ATOMIC_INIT(~0);
56/* Module parameters */
57static int debug = -1;
58module_param(debug, int, S_IRUGO | S_IWUSR);
59MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
60
61static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
62 NETIF_MSG_LINK | NETIF_MSG_IFUP |
63 NETIF_MSG_IFDOWN);
64
65#define RX_DESCRIPTORS 64
66static int dma_rx_num = RX_DESCRIPTORS;
67module_param(dma_rx_num, int, S_IRUGO | S_IWUSR);
68MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
69
70#define TX_DESCRIPTORS 64
71static int dma_tx_num = TX_DESCRIPTORS;
72module_param(dma_tx_num, int, S_IRUGO | S_IWUSR);
73MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
74
75
76#define POLL_PHY (-1)
77
78/* Make sure DMA buffer size is larger than the max frame size
79 * plus some alignment offset and a VLAN header. If the max frame size is
80 * 1518, a VLAN header would be additional 4 bytes and additional
81 * headroom for alignment is 2 bytes, 2048 is just fine.
82 */
83#define ALTERA_RXDMABUFFER_SIZE 2048
84
85/* Allow network stack to resume queueing packets after we've
86 * finished transmitting at least 1/4 of the packets in the queue.
87 */
88#define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
89
90#define TXQUEUESTOP_THRESHHOLD 2
91
92static struct of_device_id altera_tse_ids[];
93
94static inline u32 tse_tx_avail(struct altera_tse_private *priv)
95{
96 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
97}
98
99/* MDIO specific functions
100 */
101static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
102{
103 struct altera_tse_mac *mac = (struct altera_tse_mac *)bus->priv;
104 unsigned int *mdio_regs = (unsigned int *)&mac->mdio_phy0;
105 u32 data;
106
107 /* set MDIO address */
108 iowrite32((mii_id & 0x1f), &mac->mdio_phy0_addr);
109
110 /* get the data */
111 data = ioread32(&mdio_regs[regnum]) & 0xffff;
112 return data;
113}
114
115static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
116 u16 value)
117{
118 struct altera_tse_mac *mac = (struct altera_tse_mac *)bus->priv;
119 unsigned int *mdio_regs = (unsigned int *)&mac->mdio_phy0;
120
121 /* set MDIO address */
122 iowrite32((mii_id & 0x1f), &mac->mdio_phy0_addr);
123
124 /* write the data */
125 iowrite32((u32) value, &mdio_regs[regnum]);
126 return 0;
127}
128
129static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
130{
131 struct altera_tse_private *priv = netdev_priv(dev);
132 int ret;
133 int i;
134 struct device_node *mdio_node = NULL;
135 struct mii_bus *mdio = NULL;
136 struct device_node *child_node = NULL;
137
138 for_each_child_of_node(priv->device->of_node, child_node) {
139 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
140 mdio_node = child_node;
141 break;
142 }
143 }
144
145 if (mdio_node) {
146 netdev_dbg(dev, "FOUND MDIO subnode\n");
147 } else {
148 netdev_dbg(dev, "NO MDIO subnode\n");
149 return 0;
150 }
151
152 mdio = mdiobus_alloc();
153 if (mdio == NULL) {
154 netdev_err(dev, "Error allocating MDIO bus\n");
155 return -ENOMEM;
156 }
157
158 mdio->name = ALTERA_TSE_RESOURCE_NAME;
159 mdio->read = &altera_tse_mdio_read;
160 mdio->write = &altera_tse_mdio_write;
161 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
162
163 mdio->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
164 if (mdio->irq == NULL) {
165 ret = -ENOMEM;
166 goto out_free_mdio;
167 }
168 for (i = 0; i < PHY_MAX_ADDR; i++)
169 mdio->irq[i] = PHY_POLL;
170
171 mdio->priv = priv->mac_dev;
172 mdio->parent = priv->device;
173
174 ret = of_mdiobus_register(mdio, mdio_node);
175 if (ret != 0) {
176 netdev_err(dev, "Cannot register MDIO bus %s\n",
177 mdio->id);
178 goto out_free_mdio_irq;
179 }
180
181 if (netif_msg_drv(priv))
182 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
183
184 priv->mdio = mdio;
185 return 0;
186out_free_mdio_irq:
187 kfree(mdio->irq);
188out_free_mdio:
189 mdiobus_free(mdio);
190 mdio = NULL;
191 return ret;
192}
193
194static void altera_tse_mdio_destroy(struct net_device *dev)
195{
196 struct altera_tse_private *priv = netdev_priv(dev);
197
198 if (priv->mdio == NULL)
199 return;
200
201 if (netif_msg_drv(priv))
202 netdev_info(dev, "MDIO bus %s: removed\n",
203 priv->mdio->id);
204
205 mdiobus_unregister(priv->mdio);
206 kfree(priv->mdio->irq);
207 mdiobus_free(priv->mdio);
208 priv->mdio = NULL;
209}
210
211static int tse_init_rx_buffer(struct altera_tse_private *priv,
212 struct tse_buffer *rxbuffer, int len)
213{
214 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
215 if (!rxbuffer->skb)
216 return -ENOMEM;
217
218 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
219 len,
220 DMA_FROM_DEVICE);
221
222 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
223 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
224 dev_kfree_skb_any(rxbuffer->skb);
225 return -EINVAL;
226 }
37c0ffaa 227 rxbuffer->dma_addr &= (dma_addr_t)~3;
bbd2190c
VB		 228 rxbuffer->len = len;
229 return 0;
230}
231
232static void tse_free_rx_buffer(struct altera_tse_private *priv,
233 struct tse_buffer *rxbuffer)
234{
235 struct sk_buff *skb = rxbuffer->skb;
236 dma_addr_t dma_addr = rxbuffer->dma_addr;
237
238 if (skb != NULL) {
239 if (dma_addr)
240 dma_unmap_single(priv->device, dma_addr,
241 rxbuffer->len,
242 DMA_FROM_DEVICE);
243 dev_kfree_skb_any(skb);
244 rxbuffer->skb = NULL;
245 rxbuffer->dma_addr = 0;
246 }
247}
248
249/* Unmap and free Tx buffer resources
250 */
251static void tse_free_tx_buffer(struct altera_tse_private *priv,
252 struct tse_buffer *buffer)
253{
254 if (buffer->dma_addr) {
255 if (buffer->mapped_as_page)
256 dma_unmap_page(priv->device, buffer->dma_addr,
257 buffer->len, DMA_TO_DEVICE);
258 else
259 dma_unmap_single(priv->device, buffer->dma_addr,
260 buffer->len, DMA_TO_DEVICE);
261 buffer->dma_addr = 0;
262 }
263 if (buffer->skb) {
264 dev_kfree_skb_any(buffer->skb);
265 buffer->skb = NULL;
266 }
267}
268
269static int alloc_init_skbufs(struct altera_tse_private *priv)
270{
271 unsigned int rx_descs = priv->rx_ring_size;
272 unsigned int tx_descs = priv->tx_ring_size;
273 int ret = -ENOMEM;
274 int i;
275
276 /* Create Rx ring buffer */
277 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
278 GFP_KERNEL);
279 if (!priv->rx_ring)
280 goto err_rx_ring;
281
282 /* Create Tx ring buffer */
283 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
284 GFP_KERNEL);
285 if (!priv->tx_ring)
286 goto err_tx_ring;
287
288 priv->tx_cons = 0;
289 priv->tx_prod = 0;
290
291 /* Init Rx ring */
292 for (i = 0; i < rx_descs; i++) {
293 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
294 priv->rx_dma_buf_sz);
295 if (ret)
296 goto err_init_rx_buffers;
297 }
298
299 priv->rx_cons = 0;
300 priv->rx_prod = 0;
301
302 return 0;
303err_init_rx_buffers:
304 while (--i >= 0)
305 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
306 kfree(priv->tx_ring);
307err_tx_ring:
308 kfree(priv->rx_ring);
309err_rx_ring:
310 return ret;
311}
312
313static void free_skbufs(struct net_device *dev)
314{
315 struct altera_tse_private *priv = netdev_priv(dev);
316 unsigned int rx_descs = priv->rx_ring_size;
317 unsigned int tx_descs = priv->tx_ring_size;
318 int i;
319
320 /* Release the DMA TX/RX socket buffers */
321 for (i = 0; i < rx_descs; i++)
322 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
323 for (i = 0; i < tx_descs; i++)
324 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
325
326
327 kfree(priv->tx_ring);
328}
329
330/* Reallocate the skb for the reception process
331 */
332static inline void tse_rx_refill(struct altera_tse_private *priv)
333{
334 unsigned int rxsize = priv->rx_ring_size;
335 unsigned int entry;
336 int ret;
337
338 for (; priv->rx_cons - priv->rx_prod > 0;
339 priv->rx_prod++) {
340 entry = priv->rx_prod % rxsize;
341 if (likely(priv->rx_ring[entry].skb == NULL)) {
342 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
343 priv->rx_dma_buf_sz);
344 if (unlikely(ret != 0))
345 break;
346 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
347 }
348 }
349}
350
351/* Pull out the VLAN tag and fix up the packet
352 */
353static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
354{
355 struct ethhdr *eth_hdr;
356 u16 vid;
357 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
358 !__vlan_get_tag(skb, &vid)) {
359 eth_hdr = (struct ethhdr *)skb->data;
360 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
361 skb_pull(skb, VLAN_HLEN);
362 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
363 }
364}
365
366/* Receive a packet: retrieve and pass over to upper levels
367 */
368static int tse_rx(struct altera_tse_private *priv, int limit)
369{
370 unsigned int count = 0;
371 unsigned int next_entry;
372 struct sk_buff *skb;
373 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
374 u32 rxstatus;
375 u16 pktlength;
376 u16 pktstatus;
377
378 while ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0) {
379 pktstatus = rxstatus >> 16;
380 pktlength = rxstatus & 0xffff;
381
382 if ((pktstatus & 0xFF) || (pktlength == 0))
383 netdev_err(priv->dev,
384 "RCV pktstatus %08X pktlength %08X\n",
385 pktstatus, pktlength);
386
387 count++;
388 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
389
390 skb = priv->rx_ring[entry].skb;
391 if (unlikely(!skb)) {
392 netdev_err(priv->dev,
393 "%s: Inconsistent Rx descriptor chain\n",
394 __func__);
395 priv->dev->stats.rx_dropped++;
396 break;
397 }
398 priv->rx_ring[entry].skb = NULL;
399
400 skb_put(skb, pktlength);
401
402 /* make cache consistent with receive packet buffer */
403 dma_sync_single_for_cpu(priv->device,
404 priv->rx_ring[entry].dma_addr,
405 priv->rx_ring[entry].len,
406 DMA_FROM_DEVICE);
407
408 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
409 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
410
411 if (netif_msg_pktdata(priv)) {
412 netdev_info(priv->dev, "frame received %d bytes\n",
413 pktlength);
414 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
415 16, 1, skb->data, pktlength, true);
416 }
417
418 tse_rx_vlan(priv->dev, skb);
419
420 skb->protocol = eth_type_trans(skb, priv->dev);
421 skb_checksum_none_assert(skb);
422
423 napi_gro_receive(&priv->napi, skb);
424
425 priv->dev->stats.rx_packets++;
426 priv->dev->stats.rx_bytes += pktlength;
427
428 entry = next_entry;
37c0ffaa
VB		 429
430 tse_rx_refill(priv);
bbd2190c
VB		 431 }
432
bbd2190c
VB		 433 return count;
434}
435
436/* Reclaim resources after transmission completes
437 */
438static int tse_tx_complete(struct altera_tse_private *priv)
439{
440 unsigned int txsize = priv->tx_ring_size;
441 u32 ready;
442 unsigned int entry;
443 struct tse_buffer *tx_buff;
444 int txcomplete = 0;
445
446 spin_lock(&priv->tx_lock);
447
448 ready = priv->dmaops->tx_completions(priv);
449
450 /* Free sent buffers */
451 while (ready && (priv->tx_cons != priv->tx_prod)) {
452 entry = priv->tx_cons % txsize;
453 tx_buff = &priv->tx_ring[entry];
454
455 if (netif_msg_tx_done(priv))
456 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
457 __func__, priv->tx_prod, priv->tx_cons);
458
459 if (likely(tx_buff->skb))
460 priv->dev->stats.tx_packets++;
461
462 tse_free_tx_buffer(priv, tx_buff);
463 priv->tx_cons++;
464
465 txcomplete++;
466 ready--;
467 }
468
469 if (unlikely(netif_queue_stopped(priv->dev) &&
470 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
471 netif_tx_lock(priv->dev);
472 if (netif_queue_stopped(priv->dev) &&
473 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
474 if (netif_msg_tx_done(priv))
475 netdev_dbg(priv->dev, "%s: restart transmit\n",
476 __func__);
477 netif_wake_queue(priv->dev);
478 }
479 netif_tx_unlock(priv->dev);
480 }
481
482 spin_unlock(&priv->tx_lock);
483 return txcomplete;
484}
485
486/* NAPI polling function
487 */
488static int tse_poll(struct napi_struct *napi, int budget)
489{
490 struct altera_tse_private *priv =
491 container_of(napi, struct altera_tse_private, napi);
492 int rxcomplete = 0;
493 int txcomplete = 0;
494 unsigned long int flags;
495
496 txcomplete = tse_tx_complete(priv);
497
498 rxcomplete = tse_rx(priv, budget);
499
500 if (rxcomplete >= budget || txcomplete > 0)
501 return rxcomplete;
502
503 napi_gro_flush(napi, false);
504 __napi_complete(napi);
505
506 netdev_dbg(priv->dev,
507 "NAPI Complete, did %d packets with budget %d\n",
508 txcomplete+rxcomplete, budget);
509
510 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
511 priv->dmaops->enable_rxirq(priv);
512 priv->dmaops->enable_txirq(priv);
513 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
514 return rxcomplete + txcomplete;
515}
516
517/* DMA TX & RX FIFO interrupt routing
518 */
519static irqreturn_t altera_isr(int irq, void *dev_id)
520{
521 struct net_device *dev = dev_id;
522 struct altera_tse_private *priv;
523 unsigned long int flags;
524
bbd2190c
VB		 525 if (unlikely(!dev)) {
526 pr_err("%s: invalid dev pointer\n", __func__);
527 return IRQ_NONE;
528 }
529 priv = netdev_priv(dev);
530
531 /* turn off desc irqs and enable napi rx */
532 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
533
534 if (likely(napi_schedule_prep(&priv->napi))) {
535 priv->dmaops->disable_rxirq(priv);
536 priv->dmaops->disable_txirq(priv);
537 __napi_schedule(&priv->napi);
538 }
539
540 /* reset IRQs */
541 priv->dmaops->clear_rxirq(priv);
542 priv->dmaops->clear_txirq(priv);
543
544 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
545
546 return IRQ_HANDLED;
547}
548
549/* Transmit a packet (called by the kernel). Dispatches
550 * either the SGDMA method for transmitting or the
551 * MSGDMA method, assumes no scatter/gather support,
552 * implying an assumption that there's only one
553 * physically contiguous fragment starting at
554 * skb->data, for length of skb_headlen(skb).
555 */
556static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
557{
558 struct altera_tse_private *priv = netdev_priv(dev);
559 unsigned int txsize = priv->tx_ring_size;
560 unsigned int entry;
561 struct tse_buffer *buffer = NULL;
562 int nfrags = skb_shinfo(skb)->nr_frags;
563 unsigned int nopaged_len = skb_headlen(skb);
564 enum netdev_tx ret = NETDEV_TX_OK;
565 dma_addr_t dma_addr;
566 int txcomplete = 0;
567
568 spin_lock_bh(&priv->tx_lock);
569
570 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
571 if (!netif_queue_stopped(dev)) {
572 netif_stop_queue(dev);
573 /* This is a hard error, log it. */
574 netdev_err(priv->dev,
575 "%s: Tx list full when queue awake\n",
576 __func__);
577 }
578 ret = NETDEV_TX_BUSY;
579 goto out;
580 }
581
582 /* Map the first skb fragment */
583 entry = priv->tx_prod % txsize;
584 buffer = &priv->tx_ring[entry];
585
586 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
587 DMA_TO_DEVICE);
588 if (dma_mapping_error(priv->device, dma_addr)) {
589 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
590 ret = NETDEV_TX_OK;
591 goto out;
592 }
593
594 buffer->skb = skb;
595 buffer->dma_addr = dma_addr;
596 buffer->len = nopaged_len;
597
598 /* Push data out of the cache hierarchy into main memory */
599 dma_sync_single_for_device(priv->device, buffer->dma_addr,
600 buffer->len, DMA_TO_DEVICE);
601
602 txcomplete = priv->dmaops->tx_buffer(priv, buffer);
603
604 skb_tx_timestamp(skb);
605
606 priv->tx_prod++;
607 dev->stats.tx_bytes += skb->len;
608
609 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
610 if (netif_msg_hw(priv))
611 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
612 __func__);
613 netif_stop_queue(dev);
614 }
615
616out:
617 spin_unlock_bh(&priv->tx_lock);
618
619 return ret;
620}
621
622/* Called every time the controller might need to be made
623 * aware of new link state. The PHY code conveys this
624 * information through variables in the phydev structure, and this
625 * function converts those variables into the appropriate
626 * register values, and can bring down the device if needed.
627 */
628static void altera_tse_adjust_link(struct net_device *dev)
629{
630 struct altera_tse_private *priv = netdev_priv(dev);
631 struct phy_device *phydev = priv->phydev;
632 int new_state = 0;
633
634 /* only change config if there is a link */
635 spin_lock(&priv->mac_cfg_lock);
636 if (phydev->link) {
637 /* Read old config */
638 u32 cfg_reg = ioread32(&priv->mac_dev->command_config);
639
640 /* Check duplex */
641 if (phydev->duplex != priv->oldduplex) {
642 new_state = 1;
643 if (!(phydev->duplex))
644 cfg_reg |= MAC_CMDCFG_HD_ENA;
645 else
646 cfg_reg &= ~MAC_CMDCFG_HD_ENA;
647
648 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n",
649 dev->name, phydev->duplex);
650
651 priv->oldduplex = phydev->duplex;
652 }
653
654 /* Check speed */
655 if (phydev->speed != priv->oldspeed) {
656 new_state = 1;
657 switch (phydev->speed) {
658 case 1000:
659 cfg_reg |= MAC_CMDCFG_ETH_SPEED;
660 cfg_reg &= ~MAC_CMDCFG_ENA_10;
661 break;
662 case 100:
663 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
664 cfg_reg &= ~MAC_CMDCFG_ENA_10;
665 break;
666 case 10:
667 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
668 cfg_reg |= MAC_CMDCFG_ENA_10;
669 break;
670 default:
671 if (netif_msg_link(priv))
672 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n",
673 phydev->speed);
674 break;
675 }
676 priv->oldspeed = phydev->speed;
677 }
678 iowrite32(cfg_reg, &priv->mac_dev->command_config);
679
680 if (!priv->oldlink) {
681 new_state = 1;
682 priv->oldlink = 1;
683 }
684 } else if (priv->oldlink) {
685 new_state = 1;
686 priv->oldlink = 0;
687 priv->oldspeed = 0;
688 priv->oldduplex = -1;
689 }
690
691 if (new_state && netif_msg_link(priv))
692 phy_print_status(phydev);
693
694 spin_unlock(&priv->mac_cfg_lock);
695}
696static struct phy_device *connect_local_phy(struct net_device *dev)
697{
698 struct altera_tse_private *priv = netdev_priv(dev);
699 struct phy_device *phydev = NULL;
700 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
701 int ret;
702
703 if (priv->phy_addr != POLL_PHY) {
704 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
705 priv->mdio->id, priv->phy_addr);
706
707 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt);
708
709 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link,
710 priv->phy_iface);
711 if (IS_ERR(phydev))
712 netdev_err(dev, "Could not attach to PHY\n");
713
714 } else {
715 phydev = phy_find_first(priv->mdio);
716 if (phydev == NULL) {
717 netdev_err(dev, "No PHY found\n");
718 return phydev;
719 }
720
721 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link,
722 priv->phy_iface);
723 if (ret != 0) {
724 netdev_err(dev, "Could not attach to PHY\n");
725 phydev = NULL;
726 }
727 }
728 return phydev;
729}
730
731/* Initialize driver's PHY state, and attach to the PHY
732 */
733static int init_phy(struct net_device *dev)
734{
735 struct altera_tse_private *priv = netdev_priv(dev);
736 struct phy_device *phydev;
737 struct device_node *phynode;
738
739 priv->oldlink = 0;
740 priv->oldspeed = 0;
741 priv->oldduplex = -1;
742
743 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0);
744
745 if (!phynode) {
746 netdev_dbg(dev, "no phy-handle found\n");
747 if (!priv->mdio) {
748 netdev_err(dev,
749 "No phy-handle nor local mdio specified\n");
750 return -ENODEV;
751 }
752 phydev = connect_local_phy(dev);
753 } else {
754 netdev_dbg(dev, "phy-handle found\n");
755 phydev = of_phy_connect(dev, phynode,
756 &altera_tse_adjust_link, 0, priv->phy_iface);
757 }
758
759 if (!phydev) {
760 netdev_err(dev, "Could not find the PHY\n");
761 return -ENODEV;
762 }
763
764 /* Stop Advertising 1000BASE Capability if interface is not GMII
765 * Note: Checkpatch throws CHECKs for the camel case defines below,
766 * it's ok to ignore.
767 */
768 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) ||
769 (priv->phy_iface == PHY_INTERFACE_MODE_RMII))
770 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
771 SUPPORTED_1000baseT_Full);
772
773 /* Broken HW is sometimes missing the pull-up resistor on the
774 * MDIO line, which results in reads to non-existent devices returning
775 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
776 * device as well.
777 * Note: phydev->phy_id is the result of reading the UID PHY registers.
778 */
779 if (phydev->phy_id == 0) {
780 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id);
781 phy_disconnect(phydev);
782 return -ENODEV;
783 }
784
785 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n",
786 phydev->addr, phydev->phy_id, phydev->link);
787
788 priv->phydev = phydev;
789 return 0;
790}
791
792static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
793{
794 struct altera_tse_mac *mac = priv->mac_dev;
795 u32 msb;
796 u32 lsb;
797
798 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
799 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
800
801 /* Set primary MAC address */
802 iowrite32(msb, &mac->mac_addr_0);
803 iowrite32(lsb, &mac->mac_addr_1);
804}
805
806/* MAC software reset.
807 * When reset is triggered, the MAC function completes the current
808 * transmission or reception, and subsequently disables the transmit and
809 * receive logic, flushes the receive FIFO buffer, and resets the statistics
810 * counters.
811 */
812static int reset_mac(struct altera_tse_private *priv)
813{
814 void __iomem *cmd_cfg_reg = &priv->mac_dev->command_config;
815 int counter;
816 u32 dat;
817
818 dat = ioread32(cmd_cfg_reg);
819 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
820 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
821 iowrite32(dat, cmd_cfg_reg);
822
823 counter = 0;
824 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
825 if (tse_bit_is_clear(cmd_cfg_reg, MAC_CMDCFG_SW_RESET))
826 break;
827 udelay(1);
828 }
829
830 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
831 dat = ioread32(cmd_cfg_reg);
832 dat &= ~MAC_CMDCFG_SW_RESET;
833 iowrite32(dat, cmd_cfg_reg);
834 return -1;
835 }
836 return 0;
837}
838
839/* Initialize MAC core registers
840*/
841static int init_mac(struct altera_tse_private *priv)
842{
843 struct altera_tse_mac *mac = priv->mac_dev;
844 unsigned int cmd = 0;
845 u32 frm_length;
846
847 /* Setup Rx FIFO */
848 iowrite32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
849 &mac->rx_section_empty);
850 iowrite32(ALTERA_TSE_RX_SECTION_FULL, &mac->rx_section_full);
851 iowrite32(ALTERA_TSE_RX_ALMOST_EMPTY, &mac->rx_almost_empty);
852 iowrite32(ALTERA_TSE_RX_ALMOST_FULL, &mac->rx_almost_full);
853
854 /* Setup Tx FIFO */
855 iowrite32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
856 &mac->tx_section_empty);
857 iowrite32(ALTERA_TSE_TX_SECTION_FULL, &mac->tx_section_full);
858 iowrite32(ALTERA_TSE_TX_ALMOST_EMPTY, &mac->tx_almost_empty);
859 iowrite32(ALTERA_TSE_TX_ALMOST_FULL, &mac->tx_almost_full);
860
861 /* MAC Address Configuration */
862 tse_update_mac_addr(priv, priv->dev->dev_addr);
863
864 /* MAC Function Configuration */
865 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
866 iowrite32(frm_length, &mac->frm_length);
867 iowrite32(ALTERA_TSE_TX_IPG_LENGTH, &mac->tx_ipg_length);
868
869 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
870 * start address
871 */
37c0ffaa 872 tse_set_bit(&mac->rx_cmd_stat, ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
bbd2190c
VB		 873 tse_clear_bit(&mac->tx_cmd_stat, ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
874 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
875
876 /* Set the MAC options */
877 cmd = ioread32(&mac->command_config);
37c0ffaa 878 cmd &= ~MAC_CMDCFG_PAD_EN; /* No padding Removal on Receive */
bbd2190c
VB		 879 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
880 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
881 * with CRC errors
882 */
883 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
884 cmd &= ~MAC_CMDCFG_TX_ENA;
885 cmd &= ~MAC_CMDCFG_RX_ENA;
37c0ffaa
VB		 886
887 /* Default speed and duplex setting, full/100 */
888 cmd &= ~MAC_CMDCFG_HD_ENA;
889 cmd &= ~MAC_CMDCFG_ETH_SPEED;
890 cmd &= ~MAC_CMDCFG_ENA_10;
891
bbd2190c
VB		 892 iowrite32(cmd, &mac->command_config);
893
5aec4ee3
VB		 894 iowrite32(ALTERA_TSE_PAUSE_QUANTA, &mac->pause_quanta);
895
bbd2190c
VB		 896 if (netif_msg_hw(priv))
897 dev_dbg(priv->device,
898 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
899
900 return 0;
901}
902
903/* Start/stop MAC transmission logic
904 */
905static void tse_set_mac(struct altera_tse_private *priv, bool enable)
906{
907 struct altera_tse_mac *mac = priv->mac_dev;
908 u32 value = ioread32(&mac->command_config);
909
910 if (enable)
911 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
912 else
913 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
914
915 iowrite32(value, &mac->command_config);
916}
917
918/* Change the MTU
919 */
920static int tse_change_mtu(struct net_device *dev, int new_mtu)
921{
922 struct altera_tse_private *priv = netdev_priv(dev);
923 unsigned int max_mtu = priv->max_mtu;
924 unsigned int min_mtu = ETH_ZLEN + ETH_FCS_LEN;
925
926 if (netif_running(dev)) {
927 netdev_err(dev, "must be stopped to change its MTU\n");
928 return -EBUSY;
929 }
930
931 if ((new_mtu < min_mtu) || (new_mtu > max_mtu)) {
932 netdev_err(dev, "invalid MTU, max MTU is: %u\n", max_mtu);
933 return -EINVAL;
934 }
935
936 dev->mtu = new_mtu;
937 netdev_update_features(dev);
938
939 return 0;
940}
941
942static void altera_tse_set_mcfilter(struct net_device *dev)
943{
944 struct altera_tse_private *priv = netdev_priv(dev);
41ced615 945 struct altera_tse_mac *mac = priv->mac_dev;
bbd2190c
VB		 946 int i;
947 struct netdev_hw_addr *ha;
948
949 /* clear the hash filter */
950 for (i = 0; i < 64; i++)
951 iowrite32(0, &(mac->hash_table[i]));
952
953 netdev_for_each_mc_addr(ha, dev) {
954 unsigned int hash = 0;
955 int mac_octet;
956
957 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
958 unsigned char xor_bit = 0;
959 unsigned char octet = ha->addr[mac_octet];
960 unsigned int bitshift;
961
962 for (bitshift = 0; bitshift < 8; bitshift++)
963 xor_bit ^= ((octet >> bitshift) & 0x01);
964
965 hash = (hash << 1) | xor_bit;
966 }
967 iowrite32(1, &(mac->hash_table[hash]));
968 }
969}
970
971
972static void altera_tse_set_mcfilterall(struct net_device *dev)
973{
974 struct altera_tse_private *priv = netdev_priv(dev);
41ced615 975 struct altera_tse_mac *mac = priv->mac_dev;
bbd2190c
VB		 976 int i;
977
978 /* set the hash filter */
979 for (i = 0; i < 64; i++)
980 iowrite32(1, &(mac->hash_table[i]));
981}
982
983/* Set or clear the multicast filter for this adaptor
984 */
985static void tse_set_rx_mode_hashfilter(struct net_device *dev)
986{
987 struct altera_tse_private *priv = netdev_priv(dev);
988 struct altera_tse_mac *mac = priv->mac_dev;
989
990 spin_lock(&priv->mac_cfg_lock);
991
992 if (dev->flags & IFF_PROMISC)
993 tse_set_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN);
994
995 if (dev->flags & IFF_ALLMULTI)
996 altera_tse_set_mcfilterall(dev);
997 else
998 altera_tse_set_mcfilter(dev);
999
1000 spin_unlock(&priv->mac_cfg_lock);
1001}
1002
1003/* Set or clear the multicast filter for this adaptor
1004 */
1005static void tse_set_rx_mode(struct net_device *dev)
1006{
1007 struct altera_tse_private *priv = netdev_priv(dev);
1008 struct altera_tse_mac *mac = priv->mac_dev;
1009
1010 spin_lock(&priv->mac_cfg_lock);
1011
1012 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
1013 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
1014 tse_set_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN);
1015 else
1016 tse_clear_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN);
1017
1018 spin_unlock(&priv->mac_cfg_lock);
1019}
1020
1021/* Open and initialize the interface
1022 */
1023static int tse_open(struct net_device *dev)
1024{
1025 struct altera_tse_private *priv = netdev_priv(dev);
1026 int ret = 0;
1027 int i;
1028 unsigned long int flags;
1029
1030 /* Reset and configure TSE MAC and probe associated PHY */
1031 ret = priv->dmaops->init_dma(priv);
1032 if (ret != 0) {
1033 netdev_err(dev, "Cannot initialize DMA\n");
1034 goto phy_error;
1035 }
1036
1037 if (netif_msg_ifup(priv))
1038 netdev_warn(dev, "device MAC address %pM\n",
1039 dev->dev_addr);
1040
1041 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
1042 netdev_warn(dev, "TSE revision %x\n", priv->revision);
1043
1044 spin_lock(&priv->mac_cfg_lock);
1045 ret = reset_mac(priv);
1046 if (ret)
1047 netdev_err(dev, "Cannot reset MAC core (error: %d)\n", ret);
1048
1049 ret = init_mac(priv);
1050 spin_unlock(&priv->mac_cfg_lock);
1051 if (ret) {
1052 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
1053 goto alloc_skbuf_error;
1054 }
1055
1056 priv->dmaops->reset_dma(priv);
1057
1058 /* Create and initialize the TX/RX descriptors chains. */
1059 priv->rx_ring_size = dma_rx_num;
1060 priv->tx_ring_size = dma_tx_num;
1061 ret = alloc_init_skbufs(priv);
1062 if (ret) {
1063 netdev_err(dev, "DMA descriptors initialization failed\n");
1064 goto alloc_skbuf_error;
1065 }
1066
1067
1068 /* Register RX interrupt */
1069 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
1070 dev->name, dev);
1071 if (ret) {
1072 netdev_err(dev, "Unable to register RX interrupt %d\n",
1073 priv->rx_irq);
1074 goto init_error;
1075 }
1076
1077 /* Register TX interrupt */
1078 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
1079 dev->name, dev);
1080 if (ret) {
1081 netdev_err(dev, "Unable to register TX interrupt %d\n",
1082 priv->tx_irq);
1083 goto tx_request_irq_error;
1084 }
1085
1086 /* Enable DMA interrupts */
1087 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1088 priv->dmaops->enable_rxirq(priv);
1089 priv->dmaops->enable_txirq(priv);
1090
1091 /* Setup RX descriptor chain */
1092 for (i = 0; i < priv->rx_ring_size; i++)
1093 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
1094
1095 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1096
bbd2190c
VB		 1097 if (priv->phydev)
1098 phy_start(priv->phydev);
1099
1100 napi_enable(&priv->napi);
1101 netif_start_queue(dev);
1102
37c0ffaa
VB		 1103 priv->dmaops->start_rxdma(priv);
1104
1105 /* Start MAC Rx/Tx */
1106 spin_lock(&priv->mac_cfg_lock);
1107 tse_set_mac(priv, true);
1108 spin_unlock(&priv->mac_cfg_lock);
1109
bbd2190c
VB		 1110 return 0;
1111
1112tx_request_irq_error:
1113 free_irq(priv->rx_irq, dev);
1114init_error:
1115 free_skbufs(dev);
1116alloc_skbuf_error:
1117 if (priv->phydev) {
1118 phy_disconnect(priv->phydev);
1119 priv->phydev = NULL;
1120 }
1121phy_error:
1122 return ret;
1123}
1124
1125/* Stop TSE MAC interface and put the device in an inactive state
1126 */
1127static int tse_shutdown(struct net_device *dev)
1128{
1129 struct altera_tse_private *priv = netdev_priv(dev);
1130 int ret;
1131 unsigned long int flags;
1132
1133 /* Stop and disconnect the PHY */
1134 if (priv->phydev) {
1135 phy_stop(priv->phydev);
1136 phy_disconnect(priv->phydev);
1137 priv->phydev = NULL;
1138 }
1139
1140 netif_stop_queue(dev);
1141 napi_disable(&priv->napi);
1142
1143 /* Disable DMA interrupts */
1144 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1145 priv->dmaops->disable_rxirq(priv);
1146 priv->dmaops->disable_txirq(priv);
1147 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1148
1149 /* Free the IRQ lines */
1150 free_irq(priv->rx_irq, dev);
1151 free_irq(priv->tx_irq, dev);
1152
1153 /* disable and reset the MAC, empties fifo */
1154 spin_lock(&priv->mac_cfg_lock);
1155 spin_lock(&priv->tx_lock);
1156
1157 ret = reset_mac(priv);
1158 if (ret)
1159 netdev_err(dev, "Cannot reset MAC core (error: %d)\n", ret);
1160 priv->dmaops->reset_dma(priv);
1161 free_skbufs(dev);
1162
1163 spin_unlock(&priv->tx_lock);
1164 spin_unlock(&priv->mac_cfg_lock);
1165
1166 priv->dmaops->uninit_dma(priv);
1167
1168 return 0;
1169}
1170
1171static struct net_device_ops altera_tse_netdev_ops = {
1172 .ndo_open = tse_open,
1173 .ndo_stop = tse_shutdown,
1174 .ndo_start_xmit = tse_start_xmit,
1175 .ndo_set_mac_address = eth_mac_addr,
1176 .ndo_set_rx_mode = tse_set_rx_mode,
1177 .ndo_change_mtu = tse_change_mtu,
1178 .ndo_validate_addr = eth_validate_addr,
1179};
1180
bbd2190c
VB		 1181static int request_and_map(struct platform_device *pdev, const char *name,
1182 struct resource **res, void __iomem **ptr)
1183{
1184 struct resource *region;
1185 struct device *device = &pdev->dev;
1186
1187 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1188 if (*res == NULL) {
1189 dev_err(device, "resource %s not defined\n", name);
1190 return -ENODEV;
1191 }
1192
1193 region = devm_request_mem_region(device, (*res)->start,
1194 resource_size(*res), dev_name(device));
1195 if (region == NULL) {
1196 dev_err(device, "unable to request %s\n", name);
1197 return -EBUSY;
1198 }
1199
1200 *ptr = devm_ioremap_nocache(device, region->start,
1201 resource_size(region));
1202 if (*ptr == NULL) {
1203 dev_err(device, "ioremap_nocache of %s failed!", name);
1204 return -ENOMEM;
1205 }
1206
1207 return 0;
1208}
1209
1210/* Probe Altera TSE MAC device
1211 */
1212static int altera_tse_probe(struct platform_device *pdev)
1213{
1214 struct net_device *ndev;
1215 int ret = -ENODEV;
1216 struct resource *control_port;
1217 struct resource *dma_res;
1218 struct altera_tse_private *priv;
1219 const unsigned char *macaddr;
1220 struct device_node *np = pdev->dev.of_node;
1221 void __iomem *descmap;
1222 const struct of_device_id *of_id = NULL;
1223
1224 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1225 if (!ndev) {
1226 dev_err(&pdev->dev, "Could not allocate network device\n");
1227 return -ENODEV;
1228 }
1229
1230 SET_NETDEV_DEV(ndev, &pdev->dev);
1231
1232 priv = netdev_priv(ndev);
1233 priv->device = &pdev->dev;
1234 priv->dev = ndev;
1235 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1236
1237 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1238
1239 if (of_id)
1240 priv->dmaops = (struct altera_dmaops *)of_id->data;
1241
1242
1243 if (priv->dmaops &&
1244 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1245 /* Get the mapped address to the SGDMA descriptor memory */
1246 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1247 if (ret)
a7642009 1248 goto err_free_netdev;
bbd2190c
VB		 1249
1250 /* Start of that memory is for transmit descriptors */
1251 priv->tx_dma_desc = descmap;
1252
1253 /* First half is for tx descriptors, other half for tx */
1254 priv->txdescmem = resource_size(dma_res)/2;
1255
1256 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1257
1258 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1259 priv->txdescmem));
1260 priv->rxdescmem = resource_size(dma_res)/2;
1261 priv->rxdescmem_busaddr = dma_res->start;
1262 priv->rxdescmem_busaddr += priv->txdescmem;
1263
1264 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1265 dev_dbg(priv->device,
1266 "SGDMA bus addresses greater than 32-bits\n");
a7642009 1267 goto err_free_netdev;
bbd2190c
VB		 1268 }
1269 if (upper_32_bits(priv->txdescmem_busaddr)) {
1270 dev_dbg(priv->device,
1271 "SGDMA bus addresses greater than 32-bits\n");
a7642009 1272 goto err_free_netdev;
bbd2190c
VB		 1273 }
1274 } else if (priv->dmaops &&
1275 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1276 ret = request_and_map(pdev, "rx_resp", &dma_res,
1277 &priv->rx_dma_resp);
1278 if (ret)
a7642009 1279 goto err_free_netdev;
bbd2190c
VB		 1280
1281 ret = request_and_map(pdev, "tx_desc", &dma_res,
1282 &priv->tx_dma_desc);
1283 if (ret)
a7642009 1284 goto err_free_netdev;
bbd2190c
VB		 1285
1286 priv->txdescmem = resource_size(dma_res);
1287 priv->txdescmem_busaddr = dma_res->start;
1288
1289 ret = request_and_map(pdev, "rx_desc", &dma_res,
1290 &priv->rx_dma_desc);
1291 if (ret)
a7642009 1292 goto err_free_netdev;
bbd2190c
VB		 1293
1294 priv->rxdescmem = resource_size(dma_res);
1295 priv->rxdescmem_busaddr = dma_res->start;
1296
1297 } else {
a7642009 1298 goto err_free_netdev;
bbd2190c
VB		 1299 }
1300
1301 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask)))
1302 dma_set_coherent_mask(priv->device,
1303 DMA_BIT_MASK(priv->dmaops->dmamask));
1304 else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32)))
1305 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1306 else
a7642009 1307 goto err_free_netdev;
bbd2190c
VB		 1308
1309 /* MAC address space */
1310 ret = request_and_map(pdev, "control_port", &control_port,
1311 (void __iomem **)&priv->mac_dev);
1312 if (ret)
a7642009 1313 goto err_free_netdev;
bbd2190c
VB		 1314
1315 /* xSGDMA Rx Dispatcher address space */
1316 ret = request_and_map(pdev, "rx_csr", &dma_res,
1317 &priv->rx_dma_csr);
1318 if (ret)
a7642009 1319 goto err_free_netdev;
bbd2190c
VB		 1320
1321
1322 /* xSGDMA Tx Dispatcher address space */
1323 ret = request_and_map(pdev, "tx_csr", &dma_res,
1324 &priv->tx_dma_csr);
1325 if (ret)
a7642009 1326 goto err_free_netdev;
bbd2190c
VB		 1327
1328
1329 /* Rx IRQ */
1330 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1331 if (priv->rx_irq == -ENXIO) {
1332 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1333 ret = -ENXIO;
a7642009 1334 goto err_free_netdev;
bbd2190c
VB		 1335 }
1336
1337 /* Tx IRQ */
1338 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1339 if (priv->tx_irq == -ENXIO) {
1340 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1341 ret = -ENXIO;
a7642009 1342 goto err_free_netdev;
bbd2190c
VB		 1343 }
1344
1345 /* get FIFO depths from device tree */
1346 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1347 &priv->rx_fifo_depth)) {
1348 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1349 ret = -ENXIO;
a7642009 1350 goto err_free_netdev;
bbd2190c
VB		 1351 }
1352
1353 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1354 &priv->rx_fifo_depth)) {
1355 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1356 ret = -ENXIO;
a7642009 1357 goto err_free_netdev;
bbd2190c
VB		 1358 }
1359
1360 /* get hash filter settings for this instance */
1361 priv->hash_filter =
1362 of_property_read_bool(pdev->dev.of_node,
1363 "altr,has-hash-multicast-filter");
1364
1365 /* get supplemental address settings for this instance */
1366 priv->added_unicast =
1367 of_property_read_bool(pdev->dev.of_node,
1368 "altr,has-supplementary-unicast");
1369
1370 /* Max MTU is 1500, ETH_DATA_LEN */
1371 priv->max_mtu = ETH_DATA_LEN;
1372
1373 /* Get the max mtu from the device tree. Note that the
1374 * "max-frame-size" parameter is actually max mtu. Definition
1375 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1376 */
1377 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1378 &priv->max_mtu);
1379
1380 /* The DMA buffer size already accounts for an alignment bias
1381 * to avoid unaligned access exceptions for the NIOS processor,
1382 */
1383 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1384
1385 /* get default MAC address from device tree */
1386 macaddr = of_get_mac_address(pdev->dev.of_node);
1387 if (macaddr)
1388 ether_addr_copy(ndev->dev_addr, macaddr);
1389 else
1390 eth_hw_addr_random(ndev);
1391
1392 priv->phy_iface = of_get_phy_mode(np);
1393
1394 /* try to get PHY address from device tree, use PHY autodetection if
1395 * no valid address is given
1396 */
1397 if (of_property_read_u32(pdev->dev.of_node, "phy-addr",
1398 &priv->phy_addr)) {
1399 priv->phy_addr = POLL_PHY;
1400 }
1401
1402 if (!((priv->phy_addr == POLL_PHY) ||
1403 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
1404 dev_err(&pdev->dev, "invalid phy-addr specified %d\n",
1405 priv->phy_addr);
a7642009 1406 goto err_free_netdev;
bbd2190c
VB		 1407 }
1408
1409 /* Create/attach to MDIO bus */
1410 ret = altera_tse_mdio_create(ndev,
1411 atomic_add_return(1, &instance_count));
1412
1413 if (ret)
a7642009 1414 goto err_free_netdev;
bbd2190c
VB		 1415
1416 /* initialize netdev */
1417 ether_setup(ndev);
1418 ndev->mem_start = control_port->start;
1419 ndev->mem_end = control_port->end;
1420 ndev->netdev_ops = &altera_tse_netdev_ops;
1421 altera_tse_set_ethtool_ops(ndev);
1422
1423 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1424
1425 if (priv->hash_filter)
1426 altera_tse_netdev_ops.ndo_set_rx_mode =
1427 tse_set_rx_mode_hashfilter;
1428
1429 /* Scatter/gather IO is not supported,
1430 * so it is turned off
1431 */
1432 ndev->hw_features &= ~NETIF_F_SG;
1433 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1434
1435 /* VLAN offloading of tagging, stripping and filtering is not
1436 * supported by hardware, but driver will accommodate the
1437 * extra 4-byte VLAN tag for processing by upper layers
1438 */
1439 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1440
1441 /* setup NAPI interface */
1442 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT);
1443
1444 spin_lock_init(&priv->mac_cfg_lock);
1445 spin_lock_init(&priv->tx_lock);
1446 spin_lock_init(&priv->rxdma_irq_lock);
1447
1448 ret = register_netdev(ndev);
1449 if (ret) {
1450 dev_err(&pdev->dev, "failed to register TSE net device\n");
a7642009 1451 goto err_register_netdev;
bbd2190c
VB		 1452 }
1453
1454 platform_set_drvdata(pdev, ndev);
1455
1456 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1457
1458 if (netif_msg_probe(priv))
1459 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1460 (priv->revision >> 8) & 0xff,
1461 priv->revision & 0xff,
1462 (unsigned long) control_port->start, priv->rx_irq,
1463 priv->tx_irq);
1464
1465 ret = init_phy(ndev);
1466 if (ret != 0) {
1467 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
a7642009 1468 goto err_init_phy;
bbd2190c
VB		 1469 }
1470 return 0;
1471
a7642009
VB		 1472err_init_phy:
1473 unregister_netdev(ndev);
1474err_register_netdev:
1475 netif_napi_del(&priv->napi);
bbd2190c 1476 altera_tse_mdio_destroy(ndev);
a7642009 1477err_free_netdev:
bbd2190c
VB		 1478 free_netdev(ndev);
1479 return ret;
1480}
1481
1482/* Remove Altera TSE MAC device
1483 */
1484static int altera_tse_remove(struct platform_device *pdev)
1485{
1486 struct net_device *ndev = platform_get_drvdata(pdev);
1487
1488 platform_set_drvdata(pdev, NULL);
1489 altera_tse_mdio_destroy(ndev);
1490 unregister_netdev(ndev);
1491 free_netdev(ndev);
1492
1493 return 0;
1494}
1495
1496struct altera_dmaops altera_dtype_sgdma = {
1497 .altera_dtype = ALTERA_DTYPE_SGDMA,
1498 .dmamask = 32,
1499 .reset_dma = sgdma_reset,
1500 .enable_txirq = sgdma_enable_txirq,
1501 .enable_rxirq = sgdma_enable_rxirq,
1502 .disable_txirq = sgdma_disable_txirq,
1503 .disable_rxirq = sgdma_disable_rxirq,
1504 .clear_txirq = sgdma_clear_txirq,
1505 .clear_rxirq = sgdma_clear_rxirq,
1506 .tx_buffer = sgdma_tx_buffer,
1507 .tx_completions = sgdma_tx_completions,
1508 .add_rx_desc = sgdma_add_rx_desc,
1509 .get_rx_status = sgdma_rx_status,
1510 .init_dma = sgdma_initialize,
1511 .uninit_dma = sgdma_uninitialize,
37c0ffaa 1512 .start_rxdma = sgdma_start_rxdma,
bbd2190c
VB		 1513};
1514
1515struct altera_dmaops altera_dtype_msgdma = {
1516 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1517 .dmamask = 64,
1518 .reset_dma = msgdma_reset,
1519 .enable_txirq = msgdma_enable_txirq,
1520 .enable_rxirq = msgdma_enable_rxirq,
1521 .disable_txirq = msgdma_disable_txirq,
1522 .disable_rxirq = msgdma_disable_rxirq,
1523 .clear_txirq = msgdma_clear_txirq,
1524 .clear_rxirq = msgdma_clear_rxirq,
1525 .tx_buffer = msgdma_tx_buffer,
1526 .tx_completions = msgdma_tx_completions,
1527 .add_rx_desc = msgdma_add_rx_desc,
1528 .get_rx_status = msgdma_rx_status,
1529 .init_dma = msgdma_initialize,
1530 .uninit_dma = msgdma_uninitialize,
37c0ffaa 1531 .start_rxdma = msgdma_start_rxdma,
bbd2190c
VB		 1532};
1533
1534static struct of_device_id altera_tse_ids[] = {
1535 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1536 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1537 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1538 {},
1539};
1540MODULE_DEVICE_TABLE(of, altera_tse_ids);
1541
1542static struct platform_driver altera_tse_driver = {
1543 .probe = altera_tse_probe,
1544 .remove = altera_tse_remove,
1545 .suspend = NULL,
1546 .resume = NULL,
1547 .driver = {
1548 .name = ALTERA_TSE_RESOURCE_NAME,
1549 .owner = THIS_MODULE,
1550 .of_match_table = altera_tse_ids,
1551 },
1552};
1553
1554module_platform_driver(altera_tse_driver);
1555
1556MODULE_AUTHOR("Altera Corporation");
1557MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1558MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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