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Merge branch 'bnx2x-net'
[deliverable/linux.git] / drivers / net / ethernet / altera / altera_tse_main.c
CommitLineData
bbd2190c
VB		 1/* Altera Triple-Speed Ethernet MAC driver
2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
3 *
4 * Contributors:
5 * Dalon Westergreen
6 * Thomas Chou
7 * Ian Abbott
8 * Yuriy Kozlov
9 * Tobias Klauser
10 * Andriy Smolskyy
11 * Roman Bulgakov
12 * Dmytro Mytarchuk
13 * Matthew Gerlach
14 *
15 * Original driver contributed by SLS.
16 * Major updates contributed by GlobalLogic
17 *
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms and conditions of the GNU General Public License,
20 * version 2, as published by the Free Software Foundation.
21 *
22 * This program is distributed in the hope it will be useful, but WITHOUT
23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
25 * more details.
26 *
27 * You should have received a copy of the GNU General Public License along with
28 * this program. If not, see <http://www.gnu.org/licenses/>.
29 */
30
31#include <linux/atomic.h>
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/if_vlan.h>
35#include <linux/init.h>
36#include <linux/interrupt.h>
37#include <linux/io.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/of_device.h>
42#include <linux/of_mdio.h>
43#include <linux/of_net.h>
44#include <linux/of_platform.h>
45#include <linux/phy.h>
46#include <linux/platform_device.h>
47#include <linux/skbuff.h>
48#include <asm/cacheflush.h>
49
50#include "altera_utils.h"
51#include "altera_tse.h"
52#include "altera_sgdma.h"
53#include "altera_msgdma.h"
54
55static atomic_t instance_count = ATOMIC_INIT(~0);
56/* Module parameters */
57static int debug = -1;
58module_param(debug, int, S_IRUGO | S_IWUSR);
59MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
60
61static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
62 NETIF_MSG_LINK | NETIF_MSG_IFUP |
63 NETIF_MSG_IFDOWN);
64
65#define RX_DESCRIPTORS 64
66static int dma_rx_num = RX_DESCRIPTORS;
67module_param(dma_rx_num, int, S_IRUGO | S_IWUSR);
68MODULE_PARM_DESC(dma_rx_num, "Number of descriptors in the RX list");
69
70#define TX_DESCRIPTORS 64
71static int dma_tx_num = TX_DESCRIPTORS;
72module_param(dma_tx_num, int, S_IRUGO | S_IWUSR);
73MODULE_PARM_DESC(dma_tx_num, "Number of descriptors in the TX list");
74
75
76#define POLL_PHY (-1)
77
78/* Make sure DMA buffer size is larger than the max frame size
79 * plus some alignment offset and a VLAN header. If the max frame size is
80 * 1518, a VLAN header would be additional 4 bytes and additional
81 * headroom for alignment is 2 bytes, 2048 is just fine.
82 */
83#define ALTERA_RXDMABUFFER_SIZE 2048
84
85/* Allow network stack to resume queueing packets after we've
86 * finished transmitting at least 1/4 of the packets in the queue.
87 */
88#define TSE_TX_THRESH(x) (x->tx_ring_size / 4)
89
90#define TXQUEUESTOP_THRESHHOLD 2
91
92static struct of_device_id altera_tse_ids[];
93
94static inline u32 tse_tx_avail(struct altera_tse_private *priv)
95{
96 return priv->tx_cons + priv->tx_ring_size - priv->tx_prod - 1;
97}
98
99/* MDIO specific functions
100 */
101static int altera_tse_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
102{
103 struct altera_tse_mac *mac = (struct altera_tse_mac *)bus->priv;
104 unsigned int *mdio_regs = (unsigned int *)&mac->mdio_phy0;
105 u32 data;
106
107 /* set MDIO address */
108 iowrite32((mii_id & 0x1f), &mac->mdio_phy0_addr);
109
110 /* get the data */
111 data = ioread32(&mdio_regs[regnum]) & 0xffff;
112 return data;
113}
114
115static int altera_tse_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
116 u16 value)
117{
118 struct altera_tse_mac *mac = (struct altera_tse_mac *)bus->priv;
119 unsigned int *mdio_regs = (unsigned int *)&mac->mdio_phy0;
120
121 /* set MDIO address */
122 iowrite32((mii_id & 0x1f), &mac->mdio_phy0_addr);
123
124 /* write the data */
125 iowrite32((u32) value, &mdio_regs[regnum]);
126 return 0;
127}
128
129static int altera_tse_mdio_create(struct net_device *dev, unsigned int id)
130{
131 struct altera_tse_private *priv = netdev_priv(dev);
132 int ret;
133 int i;
134 struct device_node *mdio_node = NULL;
135 struct mii_bus *mdio = NULL;
136 struct device_node *child_node = NULL;
137
138 for_each_child_of_node(priv->device->of_node, child_node) {
139 if (of_device_is_compatible(child_node, "altr,tse-mdio")) {
140 mdio_node = child_node;
141 break;
142 }
143 }
144
145 if (mdio_node) {
146 netdev_dbg(dev, "FOUND MDIO subnode\n");
147 } else {
148 netdev_dbg(dev, "NO MDIO subnode\n");
149 return 0;
150 }
151
152 mdio = mdiobus_alloc();
153 if (mdio == NULL) {
154 netdev_err(dev, "Error allocating MDIO bus\n");
155 return -ENOMEM;
156 }
157
158 mdio->name = ALTERA_TSE_RESOURCE_NAME;
159 mdio->read = &altera_tse_mdio_read;
160 mdio->write = &altera_tse_mdio_write;
161 snprintf(mdio->id, MII_BUS_ID_SIZE, "%s-%u", mdio->name, id);
162
163 mdio->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
164 if (mdio->irq == NULL) {
165 ret = -ENOMEM;
166 goto out_free_mdio;
167 }
168 for (i = 0; i < PHY_MAX_ADDR; i++)
169 mdio->irq[i] = PHY_POLL;
170
171 mdio->priv = priv->mac_dev;
172 mdio->parent = priv->device;
173
174 ret = of_mdiobus_register(mdio, mdio_node);
175 if (ret != 0) {
176 netdev_err(dev, "Cannot register MDIO bus %s\n",
177 mdio->id);
178 goto out_free_mdio_irq;
179 }
180
181 if (netif_msg_drv(priv))
182 netdev_info(dev, "MDIO bus %s: created\n", mdio->id);
183
184 priv->mdio = mdio;
185 return 0;
186out_free_mdio_irq:
187 kfree(mdio->irq);
188out_free_mdio:
189 mdiobus_free(mdio);
190 mdio = NULL;
191 return ret;
192}
193
194static void altera_tse_mdio_destroy(struct net_device *dev)
195{
196 struct altera_tse_private *priv = netdev_priv(dev);
197
198 if (priv->mdio == NULL)
199 return;
200
201 if (netif_msg_drv(priv))
202 netdev_info(dev, "MDIO bus %s: removed\n",
203 priv->mdio->id);
204
205 mdiobus_unregister(priv->mdio);
206 kfree(priv->mdio->irq);
207 mdiobus_free(priv->mdio);
208 priv->mdio = NULL;
209}
210
211static int tse_init_rx_buffer(struct altera_tse_private *priv,
212 struct tse_buffer *rxbuffer, int len)
213{
214 rxbuffer->skb = netdev_alloc_skb_ip_align(priv->dev, len);
215 if (!rxbuffer->skb)
216 return -ENOMEM;
217
218 rxbuffer->dma_addr = dma_map_single(priv->device, rxbuffer->skb->data,
219 len,
220 DMA_FROM_DEVICE);
221
222 if (dma_mapping_error(priv->device, rxbuffer->dma_addr)) {
223 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
224 dev_kfree_skb_any(rxbuffer->skb);
225 return -EINVAL;
226 }
227 rxbuffer->len = len;
228 return 0;
229}
230
231static void tse_free_rx_buffer(struct altera_tse_private *priv,
232 struct tse_buffer *rxbuffer)
233{
234 struct sk_buff *skb = rxbuffer->skb;
235 dma_addr_t dma_addr = rxbuffer->dma_addr;
236
237 if (skb != NULL) {
238 if (dma_addr)
239 dma_unmap_single(priv->device, dma_addr,
240 rxbuffer->len,
241 DMA_FROM_DEVICE);
242 dev_kfree_skb_any(skb);
243 rxbuffer->skb = NULL;
244 rxbuffer->dma_addr = 0;
245 }
246}
247
248/* Unmap and free Tx buffer resources
249 */
250static void tse_free_tx_buffer(struct altera_tse_private *priv,
251 struct tse_buffer *buffer)
252{
253 if (buffer->dma_addr) {
254 if (buffer->mapped_as_page)
255 dma_unmap_page(priv->device, buffer->dma_addr,
256 buffer->len, DMA_TO_DEVICE);
257 else
258 dma_unmap_single(priv->device, buffer->dma_addr,
259 buffer->len, DMA_TO_DEVICE);
260 buffer->dma_addr = 0;
261 }
262 if (buffer->skb) {
263 dev_kfree_skb_any(buffer->skb);
264 buffer->skb = NULL;
265 }
266}
267
268static int alloc_init_skbufs(struct altera_tse_private *priv)
269{
270 unsigned int rx_descs = priv->rx_ring_size;
271 unsigned int tx_descs = priv->tx_ring_size;
272 int ret = -ENOMEM;
273 int i;
274
275 /* Create Rx ring buffer */
276 priv->rx_ring = kcalloc(rx_descs, sizeof(struct tse_buffer),
277 GFP_KERNEL);
278 if (!priv->rx_ring)
279 goto err_rx_ring;
280
281 /* Create Tx ring buffer */
282 priv->tx_ring = kcalloc(tx_descs, sizeof(struct tse_buffer),
283 GFP_KERNEL);
284 if (!priv->tx_ring)
285 goto err_tx_ring;
286
287 priv->tx_cons = 0;
288 priv->tx_prod = 0;
289
290 /* Init Rx ring */
291 for (i = 0; i < rx_descs; i++) {
292 ret = tse_init_rx_buffer(priv, &priv->rx_ring[i],
293 priv->rx_dma_buf_sz);
294 if (ret)
295 goto err_init_rx_buffers;
296 }
297
298 priv->rx_cons = 0;
299 priv->rx_prod = 0;
300
301 return 0;
302err_init_rx_buffers:
303 while (--i >= 0)
304 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
305 kfree(priv->tx_ring);
306err_tx_ring:
307 kfree(priv->rx_ring);
308err_rx_ring:
309 return ret;
310}
311
312static void free_skbufs(struct net_device *dev)
313{
314 struct altera_tse_private *priv = netdev_priv(dev);
315 unsigned int rx_descs = priv->rx_ring_size;
316 unsigned int tx_descs = priv->tx_ring_size;
317 int i;
318
319 /* Release the DMA TX/RX socket buffers */
320 for (i = 0; i < rx_descs; i++)
321 tse_free_rx_buffer(priv, &priv->rx_ring[i]);
322 for (i = 0; i < tx_descs; i++)
323 tse_free_tx_buffer(priv, &priv->tx_ring[i]);
324
325
326 kfree(priv->tx_ring);
327}
328
329/* Reallocate the skb for the reception process
330 */
331static inline void tse_rx_refill(struct altera_tse_private *priv)
332{
333 unsigned int rxsize = priv->rx_ring_size;
334 unsigned int entry;
335 int ret;
336
337 for (; priv->rx_cons - priv->rx_prod > 0;
338 priv->rx_prod++) {
339 entry = priv->rx_prod % rxsize;
340 if (likely(priv->rx_ring[entry].skb == NULL)) {
341 ret = tse_init_rx_buffer(priv, &priv->rx_ring[entry],
342 priv->rx_dma_buf_sz);
343 if (unlikely(ret != 0))
344 break;
345 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[entry]);
346 }
347 }
348}
349
350/* Pull out the VLAN tag and fix up the packet
351 */
352static inline void tse_rx_vlan(struct net_device *dev, struct sk_buff *skb)
353{
354 struct ethhdr *eth_hdr;
355 u16 vid;
356 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
357 !__vlan_get_tag(skb, &vid)) {
358 eth_hdr = (struct ethhdr *)skb->data;
359 memmove(skb->data + VLAN_HLEN, eth_hdr, ETH_ALEN * 2);
360 skb_pull(skb, VLAN_HLEN);
361 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
362 }
363}
364
365/* Receive a packet: retrieve and pass over to upper levels
366 */
367static int tse_rx(struct altera_tse_private *priv, int limit)
368{
369 unsigned int count = 0;
370 unsigned int next_entry;
371 struct sk_buff *skb;
372 unsigned int entry = priv->rx_cons % priv->rx_ring_size;
373 u32 rxstatus;
374 u16 pktlength;
375 u16 pktstatus;
376
377 while ((rxstatus = priv->dmaops->get_rx_status(priv)) != 0) {
378 pktstatus = rxstatus >> 16;
379 pktlength = rxstatus & 0xffff;
380
381 if ((pktstatus & 0xFF) || (pktlength == 0))
382 netdev_err(priv->dev,
383 "RCV pktstatus %08X pktlength %08X\n",
384 pktstatus, pktlength);
385
386 count++;
387 next_entry = (++priv->rx_cons) % priv->rx_ring_size;
388
389 skb = priv->rx_ring[entry].skb;
390 if (unlikely(!skb)) {
391 netdev_err(priv->dev,
392 "%s: Inconsistent Rx descriptor chain\n",
393 __func__);
394 priv->dev->stats.rx_dropped++;
395 break;
396 }
397 priv->rx_ring[entry].skb = NULL;
398
399 skb_put(skb, pktlength);
400
401 /* make cache consistent with receive packet buffer */
402 dma_sync_single_for_cpu(priv->device,
403 priv->rx_ring[entry].dma_addr,
404 priv->rx_ring[entry].len,
405 DMA_FROM_DEVICE);
406
407 dma_unmap_single(priv->device, priv->rx_ring[entry].dma_addr,
408 priv->rx_ring[entry].len, DMA_FROM_DEVICE);
409
410 if (netif_msg_pktdata(priv)) {
411 netdev_info(priv->dev, "frame received %d bytes\n",
412 pktlength);
413 print_hex_dump(KERN_ERR, "data: ", DUMP_PREFIX_OFFSET,
414 16, 1, skb->data, pktlength, true);
415 }
416
417 tse_rx_vlan(priv->dev, skb);
418
419 skb->protocol = eth_type_trans(skb, priv->dev);
420 skb_checksum_none_assert(skb);
421
422 napi_gro_receive(&priv->napi, skb);
423
424 priv->dev->stats.rx_packets++;
425 priv->dev->stats.rx_bytes += pktlength;
426
427 entry = next_entry;
428 }
429
430 tse_rx_refill(priv);
431 return count;
432}
433
434/* Reclaim resources after transmission completes
435 */
436static int tse_tx_complete(struct altera_tse_private *priv)
437{
438 unsigned int txsize = priv->tx_ring_size;
439 u32 ready;
440 unsigned int entry;
441 struct tse_buffer *tx_buff;
442 int txcomplete = 0;
443
444 spin_lock(&priv->tx_lock);
445
446 ready = priv->dmaops->tx_completions(priv);
447
448 /* Free sent buffers */
449 while (ready && (priv->tx_cons != priv->tx_prod)) {
450 entry = priv->tx_cons % txsize;
451 tx_buff = &priv->tx_ring[entry];
452
453 if (netif_msg_tx_done(priv))
454 netdev_dbg(priv->dev, "%s: curr %d, dirty %d\n",
455 __func__, priv->tx_prod, priv->tx_cons);
456
457 if (likely(tx_buff->skb))
458 priv->dev->stats.tx_packets++;
459
460 tse_free_tx_buffer(priv, tx_buff);
461 priv->tx_cons++;
462
463 txcomplete++;
464 ready--;
465 }
466
467 if (unlikely(netif_queue_stopped(priv->dev) &&
468 tse_tx_avail(priv) > TSE_TX_THRESH(priv))) {
469 netif_tx_lock(priv->dev);
470 if (netif_queue_stopped(priv->dev) &&
471 tse_tx_avail(priv) > TSE_TX_THRESH(priv)) {
472 if (netif_msg_tx_done(priv))
473 netdev_dbg(priv->dev, "%s: restart transmit\n",
474 __func__);
475 netif_wake_queue(priv->dev);
476 }
477 netif_tx_unlock(priv->dev);
478 }
479
480 spin_unlock(&priv->tx_lock);
481 return txcomplete;
482}
483
484/* NAPI polling function
485 */
486static int tse_poll(struct napi_struct *napi, int budget)
487{
488 struct altera_tse_private *priv =
489 container_of(napi, struct altera_tse_private, napi);
490 int rxcomplete = 0;
491 int txcomplete = 0;
492 unsigned long int flags;
493
494 txcomplete = tse_tx_complete(priv);
495
496 rxcomplete = tse_rx(priv, budget);
497
498 if (rxcomplete >= budget || txcomplete > 0)
499 return rxcomplete;
500
501 napi_gro_flush(napi, false);
502 __napi_complete(napi);
503
504 netdev_dbg(priv->dev,
505 "NAPI Complete, did %d packets with budget %d\n",
506 txcomplete+rxcomplete, budget);
507
508 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
509 priv->dmaops->enable_rxirq(priv);
510 priv->dmaops->enable_txirq(priv);
511 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
512 return rxcomplete + txcomplete;
513}
514
515/* DMA TX & RX FIFO interrupt routing
516 */
517static irqreturn_t altera_isr(int irq, void *dev_id)
518{
519 struct net_device *dev = dev_id;
520 struct altera_tse_private *priv;
521 unsigned long int flags;
522
523
524 if (unlikely(!dev)) {
525 pr_err("%s: invalid dev pointer\n", __func__);
526 return IRQ_NONE;
527 }
528 priv = netdev_priv(dev);
529
530 /* turn off desc irqs and enable napi rx */
531 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
532
533 if (likely(napi_schedule_prep(&priv->napi))) {
534 priv->dmaops->disable_rxirq(priv);
535 priv->dmaops->disable_txirq(priv);
536 __napi_schedule(&priv->napi);
537 }
538
539 /* reset IRQs */
540 priv->dmaops->clear_rxirq(priv);
541 priv->dmaops->clear_txirq(priv);
542
543 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
544
545 return IRQ_HANDLED;
546}
547
548/* Transmit a packet (called by the kernel). Dispatches
549 * either the SGDMA method for transmitting or the
550 * MSGDMA method, assumes no scatter/gather support,
551 * implying an assumption that there's only one
552 * physically contiguous fragment starting at
553 * skb->data, for length of skb_headlen(skb).
554 */
555static int tse_start_xmit(struct sk_buff *skb, struct net_device *dev)
556{
557 struct altera_tse_private *priv = netdev_priv(dev);
558 unsigned int txsize = priv->tx_ring_size;
559 unsigned int entry;
560 struct tse_buffer *buffer = NULL;
561 int nfrags = skb_shinfo(skb)->nr_frags;
562 unsigned int nopaged_len = skb_headlen(skb);
563 enum netdev_tx ret = NETDEV_TX_OK;
564 dma_addr_t dma_addr;
565 int txcomplete = 0;
566
567 spin_lock_bh(&priv->tx_lock);
568
569 if (unlikely(tse_tx_avail(priv) < nfrags + 1)) {
570 if (!netif_queue_stopped(dev)) {
571 netif_stop_queue(dev);
572 /* This is a hard error, log it. */
573 netdev_err(priv->dev,
574 "%s: Tx list full when queue awake\n",
575 __func__);
576 }
577 ret = NETDEV_TX_BUSY;
578 goto out;
579 }
580
581 /* Map the first skb fragment */
582 entry = priv->tx_prod % txsize;
583 buffer = &priv->tx_ring[entry];
584
585 dma_addr = dma_map_single(priv->device, skb->data, nopaged_len,
586 DMA_TO_DEVICE);
587 if (dma_mapping_error(priv->device, dma_addr)) {
588 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
589 ret = NETDEV_TX_OK;
590 goto out;
591 }
592
593 buffer->skb = skb;
594 buffer->dma_addr = dma_addr;
595 buffer->len = nopaged_len;
596
597 /* Push data out of the cache hierarchy into main memory */
598 dma_sync_single_for_device(priv->device, buffer->dma_addr,
599 buffer->len, DMA_TO_DEVICE);
600
601 txcomplete = priv->dmaops->tx_buffer(priv, buffer);
602
603 skb_tx_timestamp(skb);
604
605 priv->tx_prod++;
606 dev->stats.tx_bytes += skb->len;
607
608 if (unlikely(tse_tx_avail(priv) <= TXQUEUESTOP_THRESHHOLD)) {
609 if (netif_msg_hw(priv))
610 netdev_dbg(priv->dev, "%s: stop transmitted packets\n",
611 __func__);
612 netif_stop_queue(dev);
613 }
614
615out:
616 spin_unlock_bh(&priv->tx_lock);
617
618 return ret;
619}
620
621/* Called every time the controller might need to be made
622 * aware of new link state. The PHY code conveys this
623 * information through variables in the phydev structure, and this
624 * function converts those variables into the appropriate
625 * register values, and can bring down the device if needed.
626 */
627static void altera_tse_adjust_link(struct net_device *dev)
628{
629 struct altera_tse_private *priv = netdev_priv(dev);
630 struct phy_device *phydev = priv->phydev;
631 int new_state = 0;
632
633 /* only change config if there is a link */
634 spin_lock(&priv->mac_cfg_lock);
635 if (phydev->link) {
636 /* Read old config */
637 u32 cfg_reg = ioread32(&priv->mac_dev->command_config);
638
639 /* Check duplex */
640 if (phydev->duplex != priv->oldduplex) {
641 new_state = 1;
642 if (!(phydev->duplex))
643 cfg_reg |= MAC_CMDCFG_HD_ENA;
644 else
645 cfg_reg &= ~MAC_CMDCFG_HD_ENA;
646
647 netdev_dbg(priv->dev, "%s: Link duplex = 0x%x\n",
648 dev->name, phydev->duplex);
649
650 priv->oldduplex = phydev->duplex;
651 }
652
653 /* Check speed */
654 if (phydev->speed != priv->oldspeed) {
655 new_state = 1;
656 switch (phydev->speed) {
657 case 1000:
658 cfg_reg |= MAC_CMDCFG_ETH_SPEED;
659 cfg_reg &= ~MAC_CMDCFG_ENA_10;
660 break;
661 case 100:
662 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
663 cfg_reg &= ~MAC_CMDCFG_ENA_10;
664 break;
665 case 10:
666 cfg_reg &= ~MAC_CMDCFG_ETH_SPEED;
667 cfg_reg |= MAC_CMDCFG_ENA_10;
668 break;
669 default:
670 if (netif_msg_link(priv))
671 netdev_warn(dev, "Speed (%d) is not 10/100/1000!\n",
672 phydev->speed);
673 break;
674 }
675 priv->oldspeed = phydev->speed;
676 }
677 iowrite32(cfg_reg, &priv->mac_dev->command_config);
678
679 if (!priv->oldlink) {
680 new_state = 1;
681 priv->oldlink = 1;
682 }
683 } else if (priv->oldlink) {
684 new_state = 1;
685 priv->oldlink = 0;
686 priv->oldspeed = 0;
687 priv->oldduplex = -1;
688 }
689
690 if (new_state && netif_msg_link(priv))
691 phy_print_status(phydev);
692
693 spin_unlock(&priv->mac_cfg_lock);
694}
695static struct phy_device *connect_local_phy(struct net_device *dev)
696{
697 struct altera_tse_private *priv = netdev_priv(dev);
698 struct phy_device *phydev = NULL;
699 char phy_id_fmt[MII_BUS_ID_SIZE + 3];
700 int ret;
701
702 if (priv->phy_addr != POLL_PHY) {
703 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT,
704 priv->mdio->id, priv->phy_addr);
705
706 netdev_dbg(dev, "trying to attach to %s\n", phy_id_fmt);
707
708 phydev = phy_connect(dev, phy_id_fmt, &altera_tse_adjust_link,
709 priv->phy_iface);
710 if (IS_ERR(phydev))
711 netdev_err(dev, "Could not attach to PHY\n");
712
713 } else {
714 phydev = phy_find_first(priv->mdio);
715 if (phydev == NULL) {
716 netdev_err(dev, "No PHY found\n");
717 return phydev;
718 }
719
720 ret = phy_connect_direct(dev, phydev, &altera_tse_adjust_link,
721 priv->phy_iface);
722 if (ret != 0) {
723 netdev_err(dev, "Could not attach to PHY\n");
724 phydev = NULL;
725 }
726 }
727 return phydev;
728}
729
730/* Initialize driver's PHY state, and attach to the PHY
731 */
732static int init_phy(struct net_device *dev)
733{
734 struct altera_tse_private *priv = netdev_priv(dev);
735 struct phy_device *phydev;
736 struct device_node *phynode;
737
738 priv->oldlink = 0;
739 priv->oldspeed = 0;
740 priv->oldduplex = -1;
741
742 phynode = of_parse_phandle(priv->device->of_node, "phy-handle", 0);
743
744 if (!phynode) {
745 netdev_dbg(dev, "no phy-handle found\n");
746 if (!priv->mdio) {
747 netdev_err(dev,
748 "No phy-handle nor local mdio specified\n");
749 return -ENODEV;
750 }
751 phydev = connect_local_phy(dev);
752 } else {
753 netdev_dbg(dev, "phy-handle found\n");
754 phydev = of_phy_connect(dev, phynode,
755 &altera_tse_adjust_link, 0, priv->phy_iface);
756 }
757
758 if (!phydev) {
759 netdev_err(dev, "Could not find the PHY\n");
760 return -ENODEV;
761 }
762
763 /* Stop Advertising 1000BASE Capability if interface is not GMII
764 * Note: Checkpatch throws CHECKs for the camel case defines below,
765 * it's ok to ignore.
766 */
767 if ((priv->phy_iface == PHY_INTERFACE_MODE_MII) ||
768 (priv->phy_iface == PHY_INTERFACE_MODE_RMII))
769 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
770 SUPPORTED_1000baseT_Full);
771
772 /* Broken HW is sometimes missing the pull-up resistor on the
773 * MDIO line, which results in reads to non-existent devices returning
774 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
775 * device as well.
776 * Note: phydev->phy_id is the result of reading the UID PHY registers.
777 */
778 if (phydev->phy_id == 0) {
779 netdev_err(dev, "Bad PHY UID 0x%08x\n", phydev->phy_id);
780 phy_disconnect(phydev);
781 return -ENODEV;
782 }
783
784 netdev_dbg(dev, "attached to PHY %d UID 0x%08x Link = %d\n",
785 phydev->addr, phydev->phy_id, phydev->link);
786
787 priv->phydev = phydev;
788 return 0;
789}
790
791static void tse_update_mac_addr(struct altera_tse_private *priv, u8 *addr)
792{
793 struct altera_tse_mac *mac = priv->mac_dev;
794 u32 msb;
795 u32 lsb;
796
797 msb = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
798 lsb = ((addr[5] << 8) | addr[4]) & 0xffff;
799
800 /* Set primary MAC address */
801 iowrite32(msb, &mac->mac_addr_0);
802 iowrite32(lsb, &mac->mac_addr_1);
803}
804
805/* MAC software reset.
806 * When reset is triggered, the MAC function completes the current
807 * transmission or reception, and subsequently disables the transmit and
808 * receive logic, flushes the receive FIFO buffer, and resets the statistics
809 * counters.
810 */
811static int reset_mac(struct altera_tse_private *priv)
812{
813 void __iomem *cmd_cfg_reg = &priv->mac_dev->command_config;
814 int counter;
815 u32 dat;
816
817 dat = ioread32(cmd_cfg_reg);
818 dat &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
819 dat |= MAC_CMDCFG_SW_RESET | MAC_CMDCFG_CNT_RESET;
820 iowrite32(dat, cmd_cfg_reg);
821
822 counter = 0;
823 while (counter++ < ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
824 if (tse_bit_is_clear(cmd_cfg_reg, MAC_CMDCFG_SW_RESET))
825 break;
826 udelay(1);
827 }
828
829 if (counter >= ALTERA_TSE_SW_RESET_WATCHDOG_CNTR) {
830 dat = ioread32(cmd_cfg_reg);
831 dat &= ~MAC_CMDCFG_SW_RESET;
832 iowrite32(dat, cmd_cfg_reg);
833 return -1;
834 }
835 return 0;
836}
837
838/* Initialize MAC core registers
839*/
840static int init_mac(struct altera_tse_private *priv)
841{
842 struct altera_tse_mac *mac = priv->mac_dev;
843 unsigned int cmd = 0;
844 u32 frm_length;
845
846 /* Setup Rx FIFO */
847 iowrite32(priv->rx_fifo_depth - ALTERA_TSE_RX_SECTION_EMPTY,
848 &mac->rx_section_empty);
849 iowrite32(ALTERA_TSE_RX_SECTION_FULL, &mac->rx_section_full);
850 iowrite32(ALTERA_TSE_RX_ALMOST_EMPTY, &mac->rx_almost_empty);
851 iowrite32(ALTERA_TSE_RX_ALMOST_FULL, &mac->rx_almost_full);
852
853 /* Setup Tx FIFO */
854 iowrite32(priv->tx_fifo_depth - ALTERA_TSE_TX_SECTION_EMPTY,
855 &mac->tx_section_empty);
856 iowrite32(ALTERA_TSE_TX_SECTION_FULL, &mac->tx_section_full);
857 iowrite32(ALTERA_TSE_TX_ALMOST_EMPTY, &mac->tx_almost_empty);
858 iowrite32(ALTERA_TSE_TX_ALMOST_FULL, &mac->tx_almost_full);
859
860 /* MAC Address Configuration */
861 tse_update_mac_addr(priv, priv->dev->dev_addr);
862
863 /* MAC Function Configuration */
864 frm_length = ETH_HLEN + priv->dev->mtu + ETH_FCS_LEN;
865 iowrite32(frm_length, &mac->frm_length);
866 iowrite32(ALTERA_TSE_TX_IPG_LENGTH, &mac->tx_ipg_length);
867
868 /* Disable RX/TX shift 16 for alignment of all received frames on 16-bit
869 * start address
870 */
871 tse_clear_bit(&mac->rx_cmd_stat, ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16);
872 tse_clear_bit(&mac->tx_cmd_stat, ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 |
873 ALTERA_TSE_TX_CMD_STAT_OMIT_CRC);
874
875 /* Set the MAC options */
876 cmd = ioread32(&mac->command_config);
877 cmd |= MAC_CMDCFG_PAD_EN; /* Padding Removal on Receive */
878 cmd &= ~MAC_CMDCFG_CRC_FWD; /* CRC Removal */
879 cmd |= MAC_CMDCFG_RX_ERR_DISC; /* Automatically discard frames
880 * with CRC errors
881 */
882 cmd |= MAC_CMDCFG_CNTL_FRM_ENA;
883 cmd &= ~MAC_CMDCFG_TX_ENA;
884 cmd &= ~MAC_CMDCFG_RX_ENA;
885 iowrite32(cmd, &mac->command_config);
886
887 if (netif_msg_hw(priv))
888 dev_dbg(priv->device,
889 "MAC post-initialization: CMD_CONFIG = 0x%08x\n", cmd);
890
891 return 0;
892}
893
894/* Start/stop MAC transmission logic
895 */
896static void tse_set_mac(struct altera_tse_private *priv, bool enable)
897{
898 struct altera_tse_mac *mac = priv->mac_dev;
899 u32 value = ioread32(&mac->command_config);
900
901 if (enable)
902 value |= MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA;
903 else
904 value &= ~(MAC_CMDCFG_TX_ENA | MAC_CMDCFG_RX_ENA);
905
906 iowrite32(value, &mac->command_config);
907}
908
909/* Change the MTU
910 */
911static int tse_change_mtu(struct net_device *dev, int new_mtu)
912{
913 struct altera_tse_private *priv = netdev_priv(dev);
914 unsigned int max_mtu = priv->max_mtu;
915 unsigned int min_mtu = ETH_ZLEN + ETH_FCS_LEN;
916
917 if (netif_running(dev)) {
918 netdev_err(dev, "must be stopped to change its MTU\n");
919 return -EBUSY;
920 }
921
922 if ((new_mtu < min_mtu) || (new_mtu > max_mtu)) {
923 netdev_err(dev, "invalid MTU, max MTU is: %u\n", max_mtu);
924 return -EINVAL;
925 }
926
927 dev->mtu = new_mtu;
928 netdev_update_features(dev);
929
930 return 0;
931}
932
933static void altera_tse_set_mcfilter(struct net_device *dev)
934{
935 struct altera_tse_private *priv = netdev_priv(dev);
41ced615 936 struct altera_tse_mac *mac = priv->mac_dev;
bbd2190c
VB		 937 int i;
938 struct netdev_hw_addr *ha;
939
940 /* clear the hash filter */
941 for (i = 0; i < 64; i++)
942 iowrite32(0, &(mac->hash_table[i]));
943
944 netdev_for_each_mc_addr(ha, dev) {
945 unsigned int hash = 0;
946 int mac_octet;
947
948 for (mac_octet = 5; mac_octet >= 0; mac_octet--) {
949 unsigned char xor_bit = 0;
950 unsigned char octet = ha->addr[mac_octet];
951 unsigned int bitshift;
952
953 for (bitshift = 0; bitshift < 8; bitshift++)
954 xor_bit ^= ((octet >> bitshift) & 0x01);
955
956 hash = (hash << 1) | xor_bit;
957 }
958 iowrite32(1, &(mac->hash_table[hash]));
959 }
960}
961
962
963static void altera_tse_set_mcfilterall(struct net_device *dev)
964{
965 struct altera_tse_private *priv = netdev_priv(dev);
41ced615 966 struct altera_tse_mac *mac = priv->mac_dev;
bbd2190c
VB		 967 int i;
968
969 /* set the hash filter */
970 for (i = 0; i < 64; i++)
971 iowrite32(1, &(mac->hash_table[i]));
972}
973
974/* Set or clear the multicast filter for this adaptor
975 */
976static void tse_set_rx_mode_hashfilter(struct net_device *dev)
977{
978 struct altera_tse_private *priv = netdev_priv(dev);
979 struct altera_tse_mac *mac = priv->mac_dev;
980
981 spin_lock(&priv->mac_cfg_lock);
982
983 if (dev->flags & IFF_PROMISC)
984 tse_set_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN);
985
986 if (dev->flags & IFF_ALLMULTI)
987 altera_tse_set_mcfilterall(dev);
988 else
989 altera_tse_set_mcfilter(dev);
990
991 spin_unlock(&priv->mac_cfg_lock);
992}
993
994/* Set or clear the multicast filter for this adaptor
995 */
996static void tse_set_rx_mode(struct net_device *dev)
997{
998 struct altera_tse_private *priv = netdev_priv(dev);
999 struct altera_tse_mac *mac = priv->mac_dev;
1000
1001 spin_lock(&priv->mac_cfg_lock);
1002
1003 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI) ||
1004 !netdev_mc_empty(dev) || !netdev_uc_empty(dev))
1005 tse_set_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN);
1006 else
1007 tse_clear_bit(&mac->command_config, MAC_CMDCFG_PROMIS_EN);
1008
1009 spin_unlock(&priv->mac_cfg_lock);
1010}
1011
1012/* Open and initialize the interface
1013 */
1014static int tse_open(struct net_device *dev)
1015{
1016 struct altera_tse_private *priv = netdev_priv(dev);
1017 int ret = 0;
1018 int i;
1019 unsigned long int flags;
1020
1021 /* Reset and configure TSE MAC and probe associated PHY */
1022 ret = priv->dmaops->init_dma(priv);
1023 if (ret != 0) {
1024 netdev_err(dev, "Cannot initialize DMA\n");
1025 goto phy_error;
1026 }
1027
1028 if (netif_msg_ifup(priv))
1029 netdev_warn(dev, "device MAC address %pM\n",
1030 dev->dev_addr);
1031
1032 if ((priv->revision < 0xd00) || (priv->revision > 0xe00))
1033 netdev_warn(dev, "TSE revision %x\n", priv->revision);
1034
1035 spin_lock(&priv->mac_cfg_lock);
1036 ret = reset_mac(priv);
1037 if (ret)
1038 netdev_err(dev, "Cannot reset MAC core (error: %d)\n", ret);
1039
1040 ret = init_mac(priv);
1041 spin_unlock(&priv->mac_cfg_lock);
1042 if (ret) {
1043 netdev_err(dev, "Cannot init MAC core (error: %d)\n", ret);
1044 goto alloc_skbuf_error;
1045 }
1046
1047 priv->dmaops->reset_dma(priv);
1048
1049 /* Create and initialize the TX/RX descriptors chains. */
1050 priv->rx_ring_size = dma_rx_num;
1051 priv->tx_ring_size = dma_tx_num;
1052 ret = alloc_init_skbufs(priv);
1053 if (ret) {
1054 netdev_err(dev, "DMA descriptors initialization failed\n");
1055 goto alloc_skbuf_error;
1056 }
1057
1058
1059 /* Register RX interrupt */
1060 ret = request_irq(priv->rx_irq, altera_isr, IRQF_SHARED,
1061 dev->name, dev);
1062 if (ret) {
1063 netdev_err(dev, "Unable to register RX interrupt %d\n",
1064 priv->rx_irq);
1065 goto init_error;
1066 }
1067
1068 /* Register TX interrupt */
1069 ret = request_irq(priv->tx_irq, altera_isr, IRQF_SHARED,
1070 dev->name, dev);
1071 if (ret) {
1072 netdev_err(dev, "Unable to register TX interrupt %d\n",
1073 priv->tx_irq);
1074 goto tx_request_irq_error;
1075 }
1076
1077 /* Enable DMA interrupts */
1078 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1079 priv->dmaops->enable_rxirq(priv);
1080 priv->dmaops->enable_txirq(priv);
1081
1082 /* Setup RX descriptor chain */
1083 for (i = 0; i < priv->rx_ring_size; i++)
1084 priv->dmaops->add_rx_desc(priv, &priv->rx_ring[i]);
1085
1086 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1087
1088 /* Start MAC Rx/Tx */
1089 spin_lock(&priv->mac_cfg_lock);
1090 tse_set_mac(priv, true);
1091 spin_unlock(&priv->mac_cfg_lock);
1092
1093 if (priv->phydev)
1094 phy_start(priv->phydev);
1095
1096 napi_enable(&priv->napi);
1097 netif_start_queue(dev);
1098
1099 return 0;
1100
1101tx_request_irq_error:
1102 free_irq(priv->rx_irq, dev);
1103init_error:
1104 free_skbufs(dev);
1105alloc_skbuf_error:
1106 if (priv->phydev) {
1107 phy_disconnect(priv->phydev);
1108 priv->phydev = NULL;
1109 }
1110phy_error:
1111 return ret;
1112}
1113
1114/* Stop TSE MAC interface and put the device in an inactive state
1115 */
1116static int tse_shutdown(struct net_device *dev)
1117{
1118 struct altera_tse_private *priv = netdev_priv(dev);
1119 int ret;
1120 unsigned long int flags;
1121
1122 /* Stop and disconnect the PHY */
1123 if (priv->phydev) {
1124 phy_stop(priv->phydev);
1125 phy_disconnect(priv->phydev);
1126 priv->phydev = NULL;
1127 }
1128
1129 netif_stop_queue(dev);
1130 napi_disable(&priv->napi);
1131
1132 /* Disable DMA interrupts */
1133 spin_lock_irqsave(&priv->rxdma_irq_lock, flags);
1134 priv->dmaops->disable_rxirq(priv);
1135 priv->dmaops->disable_txirq(priv);
1136 spin_unlock_irqrestore(&priv->rxdma_irq_lock, flags);
1137
1138 /* Free the IRQ lines */
1139 free_irq(priv->rx_irq, dev);
1140 free_irq(priv->tx_irq, dev);
1141
1142 /* disable and reset the MAC, empties fifo */
1143 spin_lock(&priv->mac_cfg_lock);
1144 spin_lock(&priv->tx_lock);
1145
1146 ret = reset_mac(priv);
1147 if (ret)
1148 netdev_err(dev, "Cannot reset MAC core (error: %d)\n", ret);
1149 priv->dmaops->reset_dma(priv);
1150 free_skbufs(dev);
1151
1152 spin_unlock(&priv->tx_lock);
1153 spin_unlock(&priv->mac_cfg_lock);
1154
1155 priv->dmaops->uninit_dma(priv);
1156
1157 return 0;
1158}
1159
1160static struct net_device_ops altera_tse_netdev_ops = {
1161 .ndo_open = tse_open,
1162 .ndo_stop = tse_shutdown,
1163 .ndo_start_xmit = tse_start_xmit,
1164 .ndo_set_mac_address = eth_mac_addr,
1165 .ndo_set_rx_mode = tse_set_rx_mode,
1166 .ndo_change_mtu = tse_change_mtu,
1167 .ndo_validate_addr = eth_validate_addr,
1168};
1169
1170
1171static int request_and_map(struct platform_device *pdev, const char *name,
1172 struct resource **res, void __iomem **ptr)
1173{
1174 struct resource *region;
1175 struct device *device = &pdev->dev;
1176
1177 *res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
1178 if (*res == NULL) {
1179 dev_err(device, "resource %s not defined\n", name);
1180 return -ENODEV;
1181 }
1182
1183 region = devm_request_mem_region(device, (*res)->start,
1184 resource_size(*res), dev_name(device));
1185 if (region == NULL) {
1186 dev_err(device, "unable to request %s\n", name);
1187 return -EBUSY;
1188 }
1189
1190 *ptr = devm_ioremap_nocache(device, region->start,
1191 resource_size(region));
1192 if (*ptr == NULL) {
1193 dev_err(device, "ioremap_nocache of %s failed!", name);
1194 return -ENOMEM;
1195 }
1196
1197 return 0;
1198}
1199
1200/* Probe Altera TSE MAC device
1201 */
1202static int altera_tse_probe(struct platform_device *pdev)
1203{
1204 struct net_device *ndev;
1205 int ret = -ENODEV;
1206 struct resource *control_port;
1207 struct resource *dma_res;
1208 struct altera_tse_private *priv;
1209 const unsigned char *macaddr;
1210 struct device_node *np = pdev->dev.of_node;
1211 void __iomem *descmap;
1212 const struct of_device_id *of_id = NULL;
1213
1214 ndev = alloc_etherdev(sizeof(struct altera_tse_private));
1215 if (!ndev) {
1216 dev_err(&pdev->dev, "Could not allocate network device\n");
1217 return -ENODEV;
1218 }
1219
1220 SET_NETDEV_DEV(ndev, &pdev->dev);
1221
1222 priv = netdev_priv(ndev);
1223 priv->device = &pdev->dev;
1224 priv->dev = ndev;
1225 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1226
1227 of_id = of_match_device(altera_tse_ids, &pdev->dev);
1228
1229 if (of_id)
1230 priv->dmaops = (struct altera_dmaops *)of_id->data;
1231
1232
1233 if (priv->dmaops &&
1234 priv->dmaops->altera_dtype == ALTERA_DTYPE_SGDMA) {
1235 /* Get the mapped address to the SGDMA descriptor memory */
1236 ret = request_and_map(pdev, "s1", &dma_res, &descmap);
1237 if (ret)
1238 goto out_free;
1239
1240 /* Start of that memory is for transmit descriptors */
1241 priv->tx_dma_desc = descmap;
1242
1243 /* First half is for tx descriptors, other half for tx */
1244 priv->txdescmem = resource_size(dma_res)/2;
1245
1246 priv->txdescmem_busaddr = (dma_addr_t)dma_res->start;
1247
1248 priv->rx_dma_desc = (void __iomem *)((uintptr_t)(descmap +
1249 priv->txdescmem));
1250 priv->rxdescmem = resource_size(dma_res)/2;
1251 priv->rxdescmem_busaddr = dma_res->start;
1252 priv->rxdescmem_busaddr += priv->txdescmem;
1253
1254 if (upper_32_bits(priv->rxdescmem_busaddr)) {
1255 dev_dbg(priv->device,
1256 "SGDMA bus addresses greater than 32-bits\n");
1257 goto out_free;
1258 }
1259 if (upper_32_bits(priv->txdescmem_busaddr)) {
1260 dev_dbg(priv->device,
1261 "SGDMA bus addresses greater than 32-bits\n");
1262 goto out_free;
1263 }
1264 } else if (priv->dmaops &&
1265 priv->dmaops->altera_dtype == ALTERA_DTYPE_MSGDMA) {
1266 ret = request_and_map(pdev, "rx_resp", &dma_res,
1267 &priv->rx_dma_resp);
1268 if (ret)
1269 goto out_free;
1270
1271 ret = request_and_map(pdev, "tx_desc", &dma_res,
1272 &priv->tx_dma_desc);
1273 if (ret)
1274 goto out_free;
1275
1276 priv->txdescmem = resource_size(dma_res);
1277 priv->txdescmem_busaddr = dma_res->start;
1278
1279 ret = request_and_map(pdev, "rx_desc", &dma_res,
1280 &priv->rx_dma_desc);
1281 if (ret)
1282 goto out_free;
1283
1284 priv->rxdescmem = resource_size(dma_res);
1285 priv->rxdescmem_busaddr = dma_res->start;
1286
1287 } else {
1288 goto out_free;
1289 }
1290
1291 if (!dma_set_mask(priv->device, DMA_BIT_MASK(priv->dmaops->dmamask)))
1292 dma_set_coherent_mask(priv->device,
1293 DMA_BIT_MASK(priv->dmaops->dmamask));
1294 else if (!dma_set_mask(priv->device, DMA_BIT_MASK(32)))
1295 dma_set_coherent_mask(priv->device, DMA_BIT_MASK(32));
1296 else
1297 goto out_free;
1298
1299 /* MAC address space */
1300 ret = request_and_map(pdev, "control_port", &control_port,
1301 (void __iomem **)&priv->mac_dev);
1302 if (ret)
1303 goto out_free;
1304
1305 /* xSGDMA Rx Dispatcher address space */
1306 ret = request_and_map(pdev, "rx_csr", &dma_res,
1307 &priv->rx_dma_csr);
1308 if (ret)
1309 goto out_free;
1310
1311
1312 /* xSGDMA Tx Dispatcher address space */
1313 ret = request_and_map(pdev, "tx_csr", &dma_res,
1314 &priv->tx_dma_csr);
1315 if (ret)
1316 goto out_free;
1317
1318
1319 /* Rx IRQ */
1320 priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq");
1321 if (priv->rx_irq == -ENXIO) {
1322 dev_err(&pdev->dev, "cannot obtain Rx IRQ\n");
1323 ret = -ENXIO;
1324 goto out_free;
1325 }
1326
1327 /* Tx IRQ */
1328 priv->tx_irq = platform_get_irq_byname(pdev, "tx_irq");
1329 if (priv->tx_irq == -ENXIO) {
1330 dev_err(&pdev->dev, "cannot obtain Tx IRQ\n");
1331 ret = -ENXIO;
1332 goto out_free;
1333 }
1334
1335 /* get FIFO depths from device tree */
1336 if (of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
1337 &priv->rx_fifo_depth)) {
1338 dev_err(&pdev->dev, "cannot obtain rx-fifo-depth\n");
1339 ret = -ENXIO;
1340 goto out_free;
1341 }
1342
1343 if (of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
1344 &priv->rx_fifo_depth)) {
1345 dev_err(&pdev->dev, "cannot obtain tx-fifo-depth\n");
1346 ret = -ENXIO;
1347 goto out_free;
1348 }
1349
1350 /* get hash filter settings for this instance */
1351 priv->hash_filter =
1352 of_property_read_bool(pdev->dev.of_node,
1353 "altr,has-hash-multicast-filter");
1354
1355 /* get supplemental address settings for this instance */
1356 priv->added_unicast =
1357 of_property_read_bool(pdev->dev.of_node,
1358 "altr,has-supplementary-unicast");
1359
1360 /* Max MTU is 1500, ETH_DATA_LEN */
1361 priv->max_mtu = ETH_DATA_LEN;
1362
1363 /* Get the max mtu from the device tree. Note that the
1364 * "max-frame-size" parameter is actually max mtu. Definition
1365 * in the ePAPR v1.1 spec and usage differ, so go with usage.
1366 */
1367 of_property_read_u32(pdev->dev.of_node, "max-frame-size",
1368 &priv->max_mtu);
1369
1370 /* The DMA buffer size already accounts for an alignment bias
1371 * to avoid unaligned access exceptions for the NIOS processor,
1372 */
1373 priv->rx_dma_buf_sz = ALTERA_RXDMABUFFER_SIZE;
1374
1375 /* get default MAC address from device tree */
1376 macaddr = of_get_mac_address(pdev->dev.of_node);
1377 if (macaddr)
1378 ether_addr_copy(ndev->dev_addr, macaddr);
1379 else
1380 eth_hw_addr_random(ndev);
1381
1382 priv->phy_iface = of_get_phy_mode(np);
1383
1384 /* try to get PHY address from device tree, use PHY autodetection if
1385 * no valid address is given
1386 */
1387 if (of_property_read_u32(pdev->dev.of_node, "phy-addr",
1388 &priv->phy_addr)) {
1389 priv->phy_addr = POLL_PHY;
1390 }
1391
1392 if (!((priv->phy_addr == POLL_PHY) ||
1393 ((priv->phy_addr >= 0) && (priv->phy_addr < PHY_MAX_ADDR)))) {
1394 dev_err(&pdev->dev, "invalid phy-addr specified %d\n",
1395 priv->phy_addr);
1396 goto out_free;
1397 }
1398
1399 /* Create/attach to MDIO bus */
1400 ret = altera_tse_mdio_create(ndev,
1401 atomic_add_return(1, &instance_count));
1402
1403 if (ret)
1404 goto out_free;
1405
1406 /* initialize netdev */
1407 ether_setup(ndev);
1408 ndev->mem_start = control_port->start;
1409 ndev->mem_end = control_port->end;
1410 ndev->netdev_ops = &altera_tse_netdev_ops;
1411 altera_tse_set_ethtool_ops(ndev);
1412
1413 altera_tse_netdev_ops.ndo_set_rx_mode = tse_set_rx_mode;
1414
1415 if (priv->hash_filter)
1416 altera_tse_netdev_ops.ndo_set_rx_mode =
1417 tse_set_rx_mode_hashfilter;
1418
1419 /* Scatter/gather IO is not supported,
1420 * so it is turned off
1421 */
1422 ndev->hw_features &= ~NETIF_F_SG;
1423 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1424
1425 /* VLAN offloading of tagging, stripping and filtering is not
1426 * supported by hardware, but driver will accommodate the
1427 * extra 4-byte VLAN tag for processing by upper layers
1428 */
1429 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1430
1431 /* setup NAPI interface */
1432 netif_napi_add(ndev, &priv->napi, tse_poll, NAPI_POLL_WEIGHT);
1433
1434 spin_lock_init(&priv->mac_cfg_lock);
1435 spin_lock_init(&priv->tx_lock);
1436 spin_lock_init(&priv->rxdma_irq_lock);
1437
1438 ret = register_netdev(ndev);
1439 if (ret) {
1440 dev_err(&pdev->dev, "failed to register TSE net device\n");
1441 goto out_free_mdio;
1442 }
1443
1444 platform_set_drvdata(pdev, ndev);
1445
1446 priv->revision = ioread32(&priv->mac_dev->megacore_revision);
1447
1448 if (netif_msg_probe(priv))
1449 dev_info(&pdev->dev, "Altera TSE MAC version %d.%d at 0x%08lx irq %d/%d\n",
1450 (priv->revision >> 8) & 0xff,
1451 priv->revision & 0xff,
1452 (unsigned long) control_port->start, priv->rx_irq,
1453 priv->tx_irq);
1454
1455 ret = init_phy(ndev);
1456 if (ret != 0) {
1457 netdev_err(ndev, "Cannot attach to PHY (error: %d)\n", ret);
1458 goto out_free_mdio;
1459 }
1460 return 0;
1461
1462out_free_mdio:
1463 altera_tse_mdio_destroy(ndev);
1464out_free:
1465 free_netdev(ndev);
1466 return ret;
1467}
1468
1469/* Remove Altera TSE MAC device
1470 */
1471static int altera_tse_remove(struct platform_device *pdev)
1472{
1473 struct net_device *ndev = platform_get_drvdata(pdev);
1474
1475 platform_set_drvdata(pdev, NULL);
1476 altera_tse_mdio_destroy(ndev);
1477 unregister_netdev(ndev);
1478 free_netdev(ndev);
1479
1480 return 0;
1481}
1482
1483struct altera_dmaops altera_dtype_sgdma = {
1484 .altera_dtype = ALTERA_DTYPE_SGDMA,
1485 .dmamask = 32,
1486 .reset_dma = sgdma_reset,
1487 .enable_txirq = sgdma_enable_txirq,
1488 .enable_rxirq = sgdma_enable_rxirq,
1489 .disable_txirq = sgdma_disable_txirq,
1490 .disable_rxirq = sgdma_disable_rxirq,
1491 .clear_txirq = sgdma_clear_txirq,
1492 .clear_rxirq = sgdma_clear_rxirq,
1493 .tx_buffer = sgdma_tx_buffer,
1494 .tx_completions = sgdma_tx_completions,
1495 .add_rx_desc = sgdma_add_rx_desc,
1496 .get_rx_status = sgdma_rx_status,
1497 .init_dma = sgdma_initialize,
1498 .uninit_dma = sgdma_uninitialize,
1499};
1500
1501struct altera_dmaops altera_dtype_msgdma = {
1502 .altera_dtype = ALTERA_DTYPE_MSGDMA,
1503 .dmamask = 64,
1504 .reset_dma = msgdma_reset,
1505 .enable_txirq = msgdma_enable_txirq,
1506 .enable_rxirq = msgdma_enable_rxirq,
1507 .disable_txirq = msgdma_disable_txirq,
1508 .disable_rxirq = msgdma_disable_rxirq,
1509 .clear_txirq = msgdma_clear_txirq,
1510 .clear_rxirq = msgdma_clear_rxirq,
1511 .tx_buffer = msgdma_tx_buffer,
1512 .tx_completions = msgdma_tx_completions,
1513 .add_rx_desc = msgdma_add_rx_desc,
1514 .get_rx_status = msgdma_rx_status,
1515 .init_dma = msgdma_initialize,
1516 .uninit_dma = msgdma_uninitialize,
1517};
1518
1519static struct of_device_id altera_tse_ids[] = {
1520 { .compatible = "altr,tse-msgdma-1.0", .data = &altera_dtype_msgdma, },
1521 { .compatible = "altr,tse-1.0", .data = &altera_dtype_sgdma, },
1522 { .compatible = "ALTR,tse-1.0", .data = &altera_dtype_sgdma, },
1523 {},
1524};
1525MODULE_DEVICE_TABLE(of, altera_tse_ids);
1526
1527static struct platform_driver altera_tse_driver = {
1528 .probe = altera_tse_probe,
1529 .remove = altera_tse_remove,
1530 .suspend = NULL,
1531 .resume = NULL,
1532 .driver = {
1533 .name = ALTERA_TSE_RESOURCE_NAME,
1534 .owner = THIS_MODULE,
1535 .of_match_table = altera_tse_ids,
1536 },
1537};
1538
1539module_platform_driver(altera_tse_driver);
1540
1541MODULE_AUTHOR("Altera Corporation");
1542MODULE_DESCRIPTION("Altera Triple Speed Ethernet MAC driver");
1543MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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