Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver | |
4 | * | |
89be0501 | 5 | * Copyright 2001-2003, 2006 MontaVista Software Inc. |
1da177e4 LT |
6 | * Copyright 2002 TimeSys Corp. |
7 | * Added ethtool/mii-tool support, | |
8 | * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> | |
6aa20a22 JG |
9 | * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de |
10 | * or riemer@riemer-nt.de: fixed the link beat detection with | |
1da177e4 | 11 | * ioctls (SIOCGMIIPHY) |
0638dec0 HVR |
12 | * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> |
13 | * converted to use linux-2.6.x's PHY framework | |
14 | * | |
1da177e4 | 15 | * Author: MontaVista Software, Inc. |
ec7eabdd | 16 | * ppopov@mvista.com or source@mvista.com |
1da177e4 LT |
17 | * |
18 | * ######################################################################## | |
19 | * | |
20 | * This program is free software; you can distribute it and/or modify it | |
21 | * under the terms of the GNU General Public License (Version 2) as | |
22 | * published by the Free Software Foundation. | |
23 | * | |
24 | * This program is distributed in the hope it will be useful, but WITHOUT | |
25 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
26 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
27 | * for more details. | |
28 | * | |
29 | * You should have received a copy of the GNU General Public License along | |
0ab75ae8 | 30 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
31 | * |
32 | * ######################################################################## | |
33 | * | |
6aa20a22 | 34 | * |
1da177e4 | 35 | */ |
215e17be FF |
36 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
37 | ||
bc36b428 | 38 | #include <linux/capability.h> |
d791c2bd | 39 | #include <linux/dma-mapping.h> |
1da177e4 LT |
40 | #include <linux/module.h> |
41 | #include <linux/kernel.h> | |
1da177e4 LT |
42 | #include <linux/string.h> |
43 | #include <linux/timer.h> | |
44 | #include <linux/errno.h> | |
45 | #include <linux/in.h> | |
46 | #include <linux/ioport.h> | |
47 | #include <linux/bitops.h> | |
48 | #include <linux/slab.h> | |
49 | #include <linux/interrupt.h> | |
1da177e4 LT |
50 | #include <linux/netdevice.h> |
51 | #include <linux/etherdevice.h> | |
52 | #include <linux/ethtool.h> | |
53 | #include <linux/mii.h> | |
54 | #include <linux/skbuff.h> | |
55 | #include <linux/delay.h> | |
8cd35da0 | 56 | #include <linux/crc32.h> |
0638dec0 | 57 | #include <linux/phy.h> |
bd2302c2 | 58 | #include <linux/platform_device.h> |
49a42c08 FF |
59 | #include <linux/cpu.h> |
60 | #include <linux/io.h> | |
25b31cb1 | 61 | |
1da177e4 LT |
62 | #include <asm/mipsregs.h> |
63 | #include <asm/irq.h> | |
1da177e4 LT |
64 | #include <asm/processor.h> |
65 | ||
25b31cb1 | 66 | #include <au1000.h> |
bd2302c2 | 67 | #include <au1xxx_eth.h> |
25b31cb1 YY |
68 | #include <prom.h> |
69 | ||
1da177e4 LT |
70 | #include "au1000_eth.h" |
71 | ||
72 | #ifdef AU1000_ETH_DEBUG | |
73 | static int au1000_debug = 5; | |
74 | #else | |
75 | static int au1000_debug = 3; | |
76 | #endif | |
77 | ||
7cd2e6e3 FF |
78 | #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ |
79 | NETIF_MSG_PROBE | \ | |
80 | NETIF_MSG_LINK) | |
81 | ||
89be0501 | 82 | #define DRV_NAME "au1000_eth" |
8020eb82 | 83 | #define DRV_VERSION "1.7" |
1da177e4 LT |
84 | #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" |
85 | #define DRV_DESC "Au1xxx on-chip Ethernet driver" | |
86 | ||
87 | MODULE_AUTHOR(DRV_AUTHOR); | |
88 | MODULE_DESCRIPTION(DRV_DESC); | |
89 | MODULE_LICENSE("GPL"); | |
13130c7a | 90 | MODULE_VERSION(DRV_VERSION); |
1da177e4 | 91 | |
fb1a7602 ML |
92 | /* AU1000 MAC registers and bits */ |
93 | #define MAC_CONTROL 0x0 | |
94 | # define MAC_RX_ENABLE (1 << 2) | |
95 | # define MAC_TX_ENABLE (1 << 3) | |
96 | # define MAC_DEF_CHECK (1 << 5) | |
97 | # define MAC_SET_BL(X) (((X) & 0x3) << 6) | |
98 | # define MAC_AUTO_PAD (1 << 8) | |
99 | # define MAC_DISABLE_RETRY (1 << 10) | |
100 | # define MAC_DISABLE_BCAST (1 << 11) | |
101 | # define MAC_LATE_COL (1 << 12) | |
102 | # define MAC_HASH_MODE (1 << 13) | |
103 | # define MAC_HASH_ONLY (1 << 15) | |
104 | # define MAC_PASS_ALL (1 << 16) | |
105 | # define MAC_INVERSE_FILTER (1 << 17) | |
106 | # define MAC_PROMISCUOUS (1 << 18) | |
107 | # define MAC_PASS_ALL_MULTI (1 << 19) | |
108 | # define MAC_FULL_DUPLEX (1 << 20) | |
109 | # define MAC_NORMAL_MODE 0 | |
110 | # define MAC_INT_LOOPBACK (1 << 21) | |
111 | # define MAC_EXT_LOOPBACK (1 << 22) | |
112 | # define MAC_DISABLE_RX_OWN (1 << 23) | |
113 | # define MAC_BIG_ENDIAN (1 << 30) | |
114 | # define MAC_RX_ALL (1 << 31) | |
115 | #define MAC_ADDRESS_HIGH 0x4 | |
116 | #define MAC_ADDRESS_LOW 0x8 | |
117 | #define MAC_MCAST_HIGH 0xC | |
118 | #define MAC_MCAST_LOW 0x10 | |
119 | #define MAC_MII_CNTRL 0x14 | |
120 | # define MAC_MII_BUSY (1 << 0) | |
121 | # define MAC_MII_READ 0 | |
122 | # define MAC_MII_WRITE (1 << 1) | |
123 | # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) | |
124 | # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) | |
125 | #define MAC_MII_DATA 0x18 | |
126 | #define MAC_FLOW_CNTRL 0x1C | |
127 | # define MAC_FLOW_CNTRL_BUSY (1 << 0) | |
128 | # define MAC_FLOW_CNTRL_ENABLE (1 << 1) | |
129 | # define MAC_PASS_CONTROL (1 << 2) | |
130 | # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) | |
131 | #define MAC_VLAN1_TAG 0x20 | |
132 | #define MAC_VLAN2_TAG 0x24 | |
133 | ||
134 | /* Ethernet Controller Enable */ | |
135 | # define MAC_EN_CLOCK_ENABLE (1 << 0) | |
136 | # define MAC_EN_RESET0 (1 << 1) | |
137 | # define MAC_EN_TOSS (0 << 2) | |
138 | # define MAC_EN_CACHEABLE (1 << 3) | |
139 | # define MAC_EN_RESET1 (1 << 4) | |
140 | # define MAC_EN_RESET2 (1 << 5) | |
141 | # define MAC_DMA_RESET (1 << 6) | |
142 | ||
143 | /* Ethernet Controller DMA Channels */ | |
144 | /* offsets from MAC_TX_RING_ADDR address */ | |
145 | #define MAC_TX_BUFF0_STATUS 0x0 | |
146 | # define TX_FRAME_ABORTED (1 << 0) | |
147 | # define TX_JAB_TIMEOUT (1 << 1) | |
148 | # define TX_NO_CARRIER (1 << 2) | |
149 | # define TX_LOSS_CARRIER (1 << 3) | |
150 | # define TX_EXC_DEF (1 << 4) | |
151 | # define TX_LATE_COLL_ABORT (1 << 5) | |
152 | # define TX_EXC_COLL (1 << 6) | |
153 | # define TX_UNDERRUN (1 << 7) | |
154 | # define TX_DEFERRED (1 << 8) | |
155 | # define TX_LATE_COLL (1 << 9) | |
156 | # define TX_COLL_CNT_MASK (0xF << 10) | |
157 | # define TX_PKT_RETRY (1 << 31) | |
158 | #define MAC_TX_BUFF0_ADDR 0x4 | |
159 | # define TX_DMA_ENABLE (1 << 0) | |
160 | # define TX_T_DONE (1 << 1) | |
161 | # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | |
162 | #define MAC_TX_BUFF0_LEN 0x8 | |
163 | #define MAC_TX_BUFF1_STATUS 0x10 | |
164 | #define MAC_TX_BUFF1_ADDR 0x14 | |
165 | #define MAC_TX_BUFF1_LEN 0x18 | |
166 | #define MAC_TX_BUFF2_STATUS 0x20 | |
167 | #define MAC_TX_BUFF2_ADDR 0x24 | |
168 | #define MAC_TX_BUFF2_LEN 0x28 | |
169 | #define MAC_TX_BUFF3_STATUS 0x30 | |
170 | #define MAC_TX_BUFF3_ADDR 0x34 | |
171 | #define MAC_TX_BUFF3_LEN 0x38 | |
172 | ||
173 | /* offsets from MAC_RX_RING_ADDR */ | |
174 | #define MAC_RX_BUFF0_STATUS 0x0 | |
175 | # define RX_FRAME_LEN_MASK 0x3fff | |
176 | # define RX_WDOG_TIMER (1 << 14) | |
177 | # define RX_RUNT (1 << 15) | |
178 | # define RX_OVERLEN (1 << 16) | |
179 | # define RX_COLL (1 << 17) | |
180 | # define RX_ETHER (1 << 18) | |
181 | # define RX_MII_ERROR (1 << 19) | |
182 | # define RX_DRIBBLING (1 << 20) | |
183 | # define RX_CRC_ERROR (1 << 21) | |
184 | # define RX_VLAN1 (1 << 22) | |
185 | # define RX_VLAN2 (1 << 23) | |
186 | # define RX_LEN_ERROR (1 << 24) | |
187 | # define RX_CNTRL_FRAME (1 << 25) | |
188 | # define RX_U_CNTRL_FRAME (1 << 26) | |
189 | # define RX_MCAST_FRAME (1 << 27) | |
190 | # define RX_BCAST_FRAME (1 << 28) | |
191 | # define RX_FILTER_FAIL (1 << 29) | |
192 | # define RX_PACKET_FILTER (1 << 30) | |
193 | # define RX_MISSED_FRAME (1 << 31) | |
194 | ||
195 | # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ | |
196 | RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ | |
197 | RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) | |
198 | #define MAC_RX_BUFF0_ADDR 0x4 | |
199 | # define RX_DMA_ENABLE (1 << 0) | |
200 | # define RX_T_DONE (1 << 1) | |
201 | # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) | |
202 | # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) | |
203 | #define MAC_RX_BUFF1_STATUS 0x10 | |
204 | #define MAC_RX_BUFF1_ADDR 0x14 | |
205 | #define MAC_RX_BUFF2_STATUS 0x20 | |
206 | #define MAC_RX_BUFF2_ADDR 0x24 | |
207 | #define MAC_RX_BUFF3_STATUS 0x30 | |
208 | #define MAC_RX_BUFF3_ADDR 0x34 | |
209 | ||
1da177e4 LT |
210 | /* |
211 | * Theory of operation | |
212 | * | |
6aa20a22 JG |
213 | * The Au1000 MACs use a simple rx and tx descriptor ring scheme. |
214 | * There are four receive and four transmit descriptors. These | |
215 | * descriptors are not in memory; rather, they are just a set of | |
1da177e4 LT |
216 | * hardware registers. |
217 | * | |
218 | * Since the Au1000 has a coherent data cache, the receive and | |
6aa20a22 | 219 | * transmit buffers are allocated from the KSEG0 segment. The |
1da177e4 LT |
220 | * hardware registers, however, are still mapped at KSEG1 to |
221 | * make sure there's no out-of-order writes, and that all writes | |
222 | * complete immediately. | |
223 | */ | |
224 | ||
0638dec0 HVR |
225 | /* |
226 | * board-specific configurations | |
227 | * | |
228 | * PHY detection algorithm | |
229 | * | |
bd2302c2 | 230 | * If phy_static_config is undefined, the PHY setup is |
0638dec0 HVR |
231 | * autodetected: |
232 | * | |
233 | * mii_probe() first searches the current MAC's MII bus for a PHY, | |
bd2302c2 | 234 | * selecting the first (or last, if phy_search_highest_addr is |
0638dec0 HVR |
235 | * defined) PHY address not already claimed by another netdev. |
236 | * | |
237 | * If nothing was found that way when searching for the 2nd ethernet | |
bd2302c2 | 238 | * controller's PHY and phy1_search_mac0 is defined, then |
0638dec0 HVR |
239 | * the first MII bus is searched as well for an unclaimed PHY; this is |
240 | * needed in case of a dual-PHY accessible only through the MAC0's MII | |
241 | * bus. | |
242 | * | |
243 | * Finally, if no PHY is found, then the corresponding ethernet | |
244 | * controller is not registered to the network subsystem. | |
1da177e4 LT |
245 | */ |
246 | ||
bd2302c2 | 247 | /* autodetection defaults: phy1_search_mac0 */ |
1da177e4 | 248 | |
0638dec0 HVR |
249 | /* static PHY setup |
250 | * | |
251 | * most boards PHY setup should be detectable properly with the | |
252 | * autodetection algorithm in mii_probe(), but in some cases (e.g. if | |
253 | * you have a switch attached, or want to use the PHY's interrupt | |
254 | * notification capabilities) you can provide a static PHY | |
255 | * configuration here | |
256 | * | |
257 | * IRQs may only be set, if a PHY address was configured | |
258 | * If a PHY address is given, also a bus id is required to be set | |
259 | * | |
260 | * ps: make sure the used irqs are configured properly in the board | |
261 | * specific irq-map | |
262 | */ | |
1da177e4 | 263 | |
eb049630 | 264 | static void au1000_enable_mac(struct net_device *dev, int force_reset) |
5ef3041e FF |
265 | { |
266 | unsigned long flags; | |
267 | struct au1000_private *aup = netdev_priv(dev); | |
268 | ||
269 | spin_lock_irqsave(&aup->lock, flags); | |
270 | ||
ec7eabdd | 271 | if (force_reset || (!aup->mac_enabled)) { |
462ca99c | 272 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
5ef3041e | 273 | au_sync_delay(2); |
d0e7cb5d | 274 | writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 |
462ca99c | 275 | | MAC_EN_CLOCK_ENABLE), aup->enable); |
5ef3041e FF |
276 | au_sync_delay(2); |
277 | ||
278 | aup->mac_enabled = 1; | |
279 | } | |
280 | ||
281 | spin_unlock_irqrestore(&aup->lock, flags); | |
282 | } | |
283 | ||
0638dec0 HVR |
284 | /* |
285 | * MII operations | |
286 | */ | |
1210dde7 | 287 | static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) |
1da177e4 | 288 | { |
454d7c9b | 289 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d FF |
290 | u32 *const mii_control_reg = &aup->mac->mii_control; |
291 | u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
292 | u32 timedout = 20; |
293 | u32 mii_control; | |
294 | ||
d0e7cb5d | 295 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
296 | mdelay(1); |
297 | if (--timedout == 0) { | |
5368c726 | 298 | netdev_err(dev, "read_MII busy timeout!!\n"); |
1da177e4 LT |
299 | return -1; |
300 | } | |
301 | } | |
302 | ||
6aa20a22 | 303 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 304 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; |
1da177e4 | 305 | |
d0e7cb5d | 306 | writel(mii_control, mii_control_reg); |
1da177e4 LT |
307 | |
308 | timedout = 20; | |
d0e7cb5d | 309 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
310 | mdelay(1); |
311 | if (--timedout == 0) { | |
5368c726 | 312 | netdev_err(dev, "mdio_read busy timeout!!\n"); |
1da177e4 LT |
313 | return -1; |
314 | } | |
315 | } | |
d0e7cb5d | 316 | return readl(mii_data_reg); |
1da177e4 LT |
317 | } |
318 | ||
1210dde7 AB |
319 | static void au1000_mdio_write(struct net_device *dev, int phy_addr, |
320 | int reg, u16 value) | |
1da177e4 | 321 | { |
454d7c9b | 322 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d FF |
323 | u32 *const mii_control_reg = &aup->mac->mii_control; |
324 | u32 *const mii_data_reg = &aup->mac->mii_data; | |
1da177e4 LT |
325 | u32 timedout = 20; |
326 | u32 mii_control; | |
327 | ||
d0e7cb5d | 328 | while (readl(mii_control_reg) & MAC_MII_BUSY) { |
1da177e4 LT |
329 | mdelay(1); |
330 | if (--timedout == 0) { | |
5368c726 | 331 | netdev_err(dev, "mdio_write busy timeout!!\n"); |
1da177e4 LT |
332 | return; |
333 | } | |
334 | } | |
335 | ||
6aa20a22 | 336 | mii_control = MAC_SET_MII_SELECT_REG(reg) | |
0638dec0 | 337 | MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; |
1da177e4 | 338 | |
d0e7cb5d FF |
339 | writel(value, mii_data_reg); |
340 | writel(mii_control, mii_control_reg); | |
1da177e4 LT |
341 | } |
342 | ||
1210dde7 | 343 | static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) |
0638dec0 HVR |
344 | { |
345 | /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does | |
dc99839c FF |
346 | * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) |
347 | */ | |
0638dec0 HVR |
348 | struct net_device *const dev = bus->priv; |
349 | ||
dc99839c FF |
350 | /* make sure the MAC associated with this |
351 | * mii_bus is enabled | |
352 | */ | |
353 | au1000_enable_mac(dev, 0); | |
354 | ||
1210dde7 | 355 | return au1000_mdio_read(dev, phy_addr, regnum); |
0638dec0 | 356 | } |
1da177e4 | 357 | |
1210dde7 AB |
358 | static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, |
359 | u16 value) | |
1da177e4 | 360 | { |
0638dec0 | 361 | struct net_device *const dev = bus->priv; |
1da177e4 | 362 | |
dc99839c FF |
363 | /* make sure the MAC associated with this |
364 | * mii_bus is enabled | |
365 | */ | |
366 | au1000_enable_mac(dev, 0); | |
367 | ||
1210dde7 | 368 | au1000_mdio_write(dev, phy_addr, regnum, value); |
0638dec0 | 369 | return 0; |
1da177e4 LT |
370 | } |
371 | ||
1210dde7 | 372 | static int au1000_mdiobus_reset(struct mii_bus *bus) |
1da177e4 | 373 | { |
0638dec0 | 374 | struct net_device *const dev = bus->priv; |
1da177e4 | 375 | |
dc99839c FF |
376 | /* make sure the MAC associated with this |
377 | * mii_bus is enabled | |
378 | */ | |
379 | au1000_enable_mac(dev, 0); | |
380 | ||
0638dec0 HVR |
381 | return 0; |
382 | } | |
1da177e4 | 383 | |
eb049630 | 384 | static void au1000_hard_stop(struct net_device *dev) |
5ef3041e FF |
385 | { |
386 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 387 | u32 reg; |
5ef3041e | 388 | |
5368c726 | 389 | netif_dbg(aup, drv, dev, "hard stop\n"); |
5ef3041e | 390 | |
d0e7cb5d FF |
391 | reg = readl(&aup->mac->control); |
392 | reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); | |
393 | writel(reg, &aup->mac->control); | |
5ef3041e FF |
394 | au_sync_delay(10); |
395 | } | |
396 | ||
eb049630 | 397 | static void au1000_enable_rx_tx(struct net_device *dev) |
5ef3041e FF |
398 | { |
399 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 400 | u32 reg; |
5ef3041e | 401 | |
5368c726 | 402 | netif_dbg(aup, hw, dev, "enable_rx_tx\n"); |
5ef3041e | 403 | |
d0e7cb5d FF |
404 | reg = readl(&aup->mac->control); |
405 | reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); | |
406 | writel(reg, &aup->mac->control); | |
5ef3041e FF |
407 | au_sync_delay(10); |
408 | } | |
409 | ||
410 | static void | |
411 | au1000_adjust_link(struct net_device *dev) | |
412 | { | |
413 | struct au1000_private *aup = netdev_priv(dev); | |
414 | struct phy_device *phydev = aup->phy_dev; | |
415 | unsigned long flags; | |
d0e7cb5d | 416 | u32 reg; |
5ef3041e FF |
417 | |
418 | int status_change = 0; | |
419 | ||
420 | BUG_ON(!aup->phy_dev); | |
421 | ||
422 | spin_lock_irqsave(&aup->lock, flags); | |
423 | ||
424 | if (phydev->link && (aup->old_speed != phydev->speed)) { | |
2cc3c6b1 | 425 | /* speed changed */ |
5ef3041e | 426 | |
2cc3c6b1 | 427 | switch (phydev->speed) { |
5ef3041e FF |
428 | case SPEED_10: |
429 | case SPEED_100: | |
430 | break; | |
431 | default: | |
5368c726 FF |
432 | netdev_warn(dev, "Speed (%d) is not 10/100 ???\n", |
433 | phydev->speed); | |
5ef3041e FF |
434 | break; |
435 | } | |
436 | ||
437 | aup->old_speed = phydev->speed; | |
438 | ||
439 | status_change = 1; | |
440 | } | |
441 | ||
442 | if (phydev->link && (aup->old_duplex != phydev->duplex)) { | |
2cc3c6b1 | 443 | /* duplex mode changed */ |
5ef3041e FF |
444 | |
445 | /* switching duplex mode requires to disable rx and tx! */ | |
eb049630 | 446 | au1000_hard_stop(dev); |
5ef3041e | 447 | |
d0e7cb5d FF |
448 | reg = readl(&aup->mac->control); |
449 | if (DUPLEX_FULL == phydev->duplex) { | |
450 | reg |= MAC_FULL_DUPLEX; | |
451 | reg &= ~MAC_DISABLE_RX_OWN; | |
452 | } else { | |
453 | reg &= ~MAC_FULL_DUPLEX; | |
454 | reg |= MAC_DISABLE_RX_OWN; | |
455 | } | |
456 | writel(reg, &aup->mac->control); | |
5ef3041e FF |
457 | au_sync_delay(1); |
458 | ||
eb049630 | 459 | au1000_enable_rx_tx(dev); |
5ef3041e FF |
460 | aup->old_duplex = phydev->duplex; |
461 | ||
462 | status_change = 1; | |
463 | } | |
464 | ||
2cc3c6b1 FF |
465 | if (phydev->link != aup->old_link) { |
466 | /* link state changed */ | |
5ef3041e FF |
467 | |
468 | if (!phydev->link) { | |
469 | /* link went down */ | |
470 | aup->old_speed = 0; | |
471 | aup->old_duplex = -1; | |
472 | } | |
473 | ||
474 | aup->old_link = phydev->link; | |
475 | status_change = 1; | |
476 | } | |
477 | ||
478 | spin_unlock_irqrestore(&aup->lock, flags); | |
479 | ||
480 | if (status_change) { | |
481 | if (phydev->link) | |
5368c726 FF |
482 | netdev_info(dev, "link up (%d/%s)\n", |
483 | phydev->speed, | |
5ef3041e FF |
484 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); |
485 | else | |
5368c726 | 486 | netdev_info(dev, "link down\n"); |
5ef3041e FF |
487 | } |
488 | } | |
489 | ||
ec7eabdd | 490 | static int au1000_mii_probe(struct net_device *dev) |
0638dec0 | 491 | { |
454d7c9b | 492 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 | 493 | struct phy_device *phydev = NULL; |
18b8e15b | 494 | int phy_addr; |
0638dec0 | 495 | |
bd2302c2 FF |
496 | if (aup->phy_static_config) { |
497 | BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); | |
0638dec0 | 498 | |
bd2302c2 FF |
499 | if (aup->phy_addr) |
500 | phydev = aup->mii_bus->phy_map[aup->phy_addr]; | |
501 | else | |
5368c726 | 502 | netdev_info(dev, "using PHY-less setup\n"); |
0638dec0 | 503 | return 0; |
18b8e15b | 504 | } |
0638dec0 | 505 | |
18b8e15b | 506 | /* find the first (lowest address) PHY |
dc99839c FF |
507 | * on the current MAC's MII bus |
508 | */ | |
18b8e15b FF |
509 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) |
510 | if (aup->mii_bus->phy_map[phy_addr]) { | |
511 | phydev = aup->mii_bus->phy_map[phy_addr]; | |
512 | if (!aup->phy_search_highest_addr) | |
513 | /* break out with first one found */ | |
514 | break; | |
515 | } | |
0638dec0 | 516 | |
18b8e15b FF |
517 | if (aup->phy1_search_mac0) { |
518 | /* try harder to find a PHY */ | |
519 | if (!phydev && (aup->mac_id == 1)) { | |
520 | /* no PHY found, maybe we have a dual PHY? */ | |
521 | dev_info(&dev->dev, ": no PHY found on MAC1, " | |
522 | "let's see if it's attached to MAC0...\n"); | |
523 | ||
524 | /* find the first (lowest address) non-attached | |
525 | * PHY on the MAC0 MII bus | |
526 | */ | |
527 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | |
528 | struct phy_device *const tmp_phydev = | |
529 | aup->mii_bus->phy_map[phy_addr]; | |
530 | ||
531 | if (aup->mac_id == 1) | |
532 | break; | |
533 | ||
534 | /* no PHY here... */ | |
535 | if (!tmp_phydev) | |
536 | continue; | |
537 | ||
538 | /* already claimed by MAC0 */ | |
539 | if (tmp_phydev->attached_dev) | |
540 | continue; | |
541 | ||
542 | phydev = tmp_phydev; | |
543 | break; /* found it */ | |
bd2302c2 | 544 | } |
1da177e4 LT |
545 | } |
546 | } | |
1da177e4 | 547 | |
0638dec0 | 548 | if (!phydev) { |
5368c726 | 549 | netdev_err(dev, "no PHY found\n"); |
1da177e4 LT |
550 | return -1; |
551 | } | |
552 | ||
0638dec0 | 553 | /* now we are supposed to have a proper phydev, to attach to... */ |
0638dec0 HVR |
554 | BUG_ON(phydev->attached_dev); |
555 | ||
f9a8f83b FF |
556 | phydev = phy_connect(dev, dev_name(&phydev->dev), |
557 | &au1000_adjust_link, PHY_INTERFACE_MODE_MII); | |
0638dec0 HVR |
558 | |
559 | if (IS_ERR(phydev)) { | |
5368c726 | 560 | netdev_err(dev, "Could not attach to PHY\n"); |
0638dec0 HVR |
561 | return PTR_ERR(phydev); |
562 | } | |
563 | ||
564 | /* mask with MAC supported features */ | |
565 | phydev->supported &= (SUPPORTED_10baseT_Half | |
566 | | SUPPORTED_10baseT_Full | |
567 | | SUPPORTED_100baseT_Half | |
568 | | SUPPORTED_100baseT_Full | |
569 | | SUPPORTED_Autoneg | |
570 | /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ | |
571 | | SUPPORTED_MII | |
572 | | SUPPORTED_TP); | |
573 | ||
574 | phydev->advertising = phydev->supported; | |
575 | ||
576 | aup->old_link = 0; | |
577 | aup->old_speed = 0; | |
578 | aup->old_duplex = -1; | |
579 | aup->phy_dev = phydev; | |
580 | ||
5368c726 FF |
581 | netdev_info(dev, "attached PHY driver [%s] " |
582 | "(mii_bus:phy_addr=%s, irq=%d)\n", | |
db1d7bf7 | 583 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); |
1da177e4 LT |
584 | |
585 | return 0; | |
586 | } | |
587 | ||
588 | ||
589 | /* | |
590 | * Buffer allocation/deallocation routines. The buffer descriptor returned | |
6aa20a22 | 591 | * has the virtual and dma address of a buffer suitable for |
1da177e4 LT |
592 | * both, receive and transmit operations. |
593 | */ | |
3441592b | 594 | static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup) |
1da177e4 | 595 | { |
3441592b | 596 | struct db_dest *pDB; |
1da177e4 LT |
597 | pDB = aup->pDBfree; |
598 | ||
ec7eabdd | 599 | if (pDB) |
1da177e4 | 600 | aup->pDBfree = pDB->pnext; |
ec7eabdd | 601 | |
1da177e4 LT |
602 | return pDB; |
603 | } | |
604 | ||
3441592b | 605 | void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB) |
1da177e4 | 606 | { |
3441592b | 607 | struct db_dest *pDBfree = aup->pDBfree; |
1da177e4 LT |
608 | if (pDBfree) |
609 | pDBfree->pnext = pDB; | |
610 | aup->pDBfree = pDB; | |
611 | } | |
612 | ||
eb049630 | 613 | static void au1000_reset_mac_unlocked(struct net_device *dev) |
0638dec0 | 614 | { |
454d7c9b | 615 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
616 | int i; |
617 | ||
eb049630 | 618 | au1000_hard_stop(dev); |
0638dec0 | 619 | |
462ca99c | 620 | writel(MAC_EN_CLOCK_ENABLE, aup->enable); |
0638dec0 | 621 | au_sync_delay(2); |
462ca99c | 622 | writel(0, aup->enable); |
0638dec0 HVR |
623 | au_sync_delay(2); |
624 | ||
1da177e4 LT |
625 | aup->tx_full = 0; |
626 | for (i = 0; i < NUM_RX_DMA; i++) { | |
627 | /* reset control bits */ | |
628 | aup->rx_dma_ring[i]->buff_stat &= ~0xf; | |
629 | } | |
630 | for (i = 0; i < NUM_TX_DMA; i++) { | |
631 | /* reset control bits */ | |
632 | aup->tx_dma_ring[i]->buff_stat &= ~0xf; | |
633 | } | |
0638dec0 HVR |
634 | |
635 | aup->mac_enabled = 0; | |
636 | ||
1da177e4 LT |
637 | } |
638 | ||
eb049630 | 639 | static void au1000_reset_mac(struct net_device *dev) |
0638dec0 | 640 | { |
454d7c9b | 641 | struct au1000_private *const aup = netdev_priv(dev); |
0638dec0 HVR |
642 | unsigned long flags; |
643 | ||
5368c726 FF |
644 | netif_dbg(aup, hw, dev, "reset mac, aup %x\n", |
645 | (unsigned)aup); | |
0638dec0 HVR |
646 | |
647 | spin_lock_irqsave(&aup->lock, flags); | |
648 | ||
ec7eabdd | 649 | au1000_reset_mac_unlocked(dev); |
0638dec0 HVR |
650 | |
651 | spin_unlock_irqrestore(&aup->lock, flags); | |
652 | } | |
1da177e4 | 653 | |
6aa20a22 | 654 | /* |
1da177e4 LT |
655 | * Setup the receive and transmit "rings". These pointers are the addresses |
656 | * of the rx and tx MAC DMA registers so they are fixed by the hardware -- | |
657 | * these are not descriptors sitting in memory. | |
658 | */ | |
6aa20a22 | 659 | static void |
553737aa | 660 | au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base) |
1da177e4 LT |
661 | { |
662 | int i; | |
663 | ||
664 | for (i = 0; i < NUM_RX_DMA; i++) { | |
553737aa ML |
665 | aup->rx_dma_ring[i] = (struct rx_dma *) |
666 | (tx_base + 0x100 + sizeof(struct rx_dma) * i); | |
1da177e4 LT |
667 | } |
668 | for (i = 0; i < NUM_TX_DMA; i++) { | |
553737aa ML |
669 | aup->tx_dma_ring[i] = (struct tx_dma *) |
670 | (tx_base + sizeof(struct tx_dma) * i); | |
1da177e4 LT |
671 | } |
672 | } | |
673 | ||
0638dec0 HVR |
674 | /* |
675 | * ethtool operations | |
676 | */ | |
1da177e4 | 677 | |
0638dec0 | 678 | static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 679 | { |
454d7c9b | 680 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 681 | |
0638dec0 HVR |
682 | if (aup->phy_dev) |
683 | return phy_ethtool_gset(aup->phy_dev, cmd); | |
1da177e4 | 684 | |
0638dec0 | 685 | return -EINVAL; |
1da177e4 LT |
686 | } |
687 | ||
0638dec0 | 688 | static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 | 689 | { |
454d7c9b | 690 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 691 | |
0638dec0 HVR |
692 | if (!capable(CAP_NET_ADMIN)) |
693 | return -EPERM; | |
1da177e4 | 694 | |
0638dec0 HVR |
695 | if (aup->phy_dev) |
696 | return phy_ethtool_sset(aup->phy_dev, cmd); | |
1da177e4 | 697 | |
0638dec0 | 698 | return -EINVAL; |
1da177e4 LT |
699 | } |
700 | ||
701 | static void | |
702 | au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
703 | { | |
454d7c9b | 704 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 705 | |
7826d43f JP |
706 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
707 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
708 | snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME, | |
709 | aup->mac_id); | |
1da177e4 LT |
710 | info->regdump_len = 0; |
711 | } | |
712 | ||
7cd2e6e3 FF |
713 | static void au1000_set_msglevel(struct net_device *dev, u32 value) |
714 | { | |
715 | struct au1000_private *aup = netdev_priv(dev); | |
716 | aup->msg_enable = value; | |
717 | } | |
718 | ||
719 | static u32 au1000_get_msglevel(struct net_device *dev) | |
720 | { | |
721 | struct au1000_private *aup = netdev_priv(dev); | |
722 | return aup->msg_enable; | |
723 | } | |
724 | ||
7282d491 | 725 | static const struct ethtool_ops au1000_ethtool_ops = { |
1da177e4 LT |
726 | .get_settings = au1000_get_settings, |
727 | .set_settings = au1000_set_settings, | |
728 | .get_drvinfo = au1000_get_drvinfo, | |
0638dec0 | 729 | .get_link = ethtool_op_get_link, |
7cd2e6e3 FF |
730 | .get_msglevel = au1000_get_msglevel, |
731 | .set_msglevel = au1000_set_msglevel, | |
1da177e4 LT |
732 | }; |
733 | ||
5ef3041e FF |
734 | |
735 | /* | |
736 | * Initialize the interface. | |
737 | * | |
738 | * When the device powers up, the clocks are disabled and the | |
739 | * mac is in reset state. When the interface is closed, we | |
740 | * do the same -- reset the device and disable the clocks to | |
741 | * conserve power. Thus, whenever au1000_init() is called, | |
742 | * the device should already be in reset state. | |
743 | */ | |
744 | static int au1000_init(struct net_device *dev) | |
1da177e4 | 745 | { |
5ef3041e FF |
746 | struct au1000_private *aup = netdev_priv(dev); |
747 | unsigned long flags; | |
748 | int i; | |
749 | u32 control; | |
89be0501 | 750 | |
5368c726 | 751 | netif_dbg(aup, hw, dev, "au1000_init\n"); |
1da177e4 | 752 | |
5ef3041e | 753 | /* bring the device out of reset */ |
eb049630 | 754 | au1000_enable_mac(dev, 1); |
89be0501 | 755 | |
5ef3041e | 756 | spin_lock_irqsave(&aup->lock, flags); |
1da177e4 | 757 | |
d0e7cb5d | 758 | writel(0, &aup->mac->control); |
5ef3041e FF |
759 | aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; |
760 | aup->tx_tail = aup->tx_head; | |
761 | aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; | |
1da177e4 | 762 | |
d0e7cb5d FF |
763 | writel(dev->dev_addr[5]<<8 | dev->dev_addr[4], |
764 | &aup->mac->mac_addr_high); | |
765 | writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | | |
766 | dev->dev_addr[1]<<8 | dev->dev_addr[0], | |
767 | &aup->mac->mac_addr_low); | |
5ef3041e | 768 | |
18b8e15b | 769 | |
ec7eabdd | 770 | for (i = 0; i < NUM_RX_DMA; i++) |
5ef3041e | 771 | aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; |
ec7eabdd | 772 | |
5ef3041e | 773 | au_sync(); |
1da177e4 | 774 | |
5ef3041e FF |
775 | control = MAC_RX_ENABLE | MAC_TX_ENABLE; |
776 | #ifndef CONFIG_CPU_LITTLE_ENDIAN | |
777 | control |= MAC_BIG_ENDIAN; | |
778 | #endif | |
779 | if (aup->phy_dev) { | |
780 | if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex)) | |
781 | control |= MAC_FULL_DUPLEX; | |
782 | else | |
783 | control |= MAC_DISABLE_RX_OWN; | |
784 | } else { /* PHY-less op, assume full-duplex */ | |
785 | control |= MAC_FULL_DUPLEX; | |
1da177e4 LT |
786 | } |
787 | ||
d0e7cb5d FF |
788 | writel(control, &aup->mac->control); |
789 | writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ | |
5ef3041e | 790 | au_sync(); |
1da177e4 | 791 | |
5ef3041e FF |
792 | spin_unlock_irqrestore(&aup->lock, flags); |
793 | return 0; | |
794 | } | |
1da177e4 | 795 | |
eb049630 | 796 | static inline void au1000_update_rx_stats(struct net_device *dev, u32 status) |
5ef3041e | 797 | { |
5ef3041e | 798 | struct net_device_stats *ps = &dev->stats; |
1da177e4 | 799 | |
5ef3041e FF |
800 | ps->rx_packets++; |
801 | if (status & RX_MCAST_FRAME) | |
802 | ps->multicast++; | |
1da177e4 | 803 | |
5ef3041e FF |
804 | if (status & RX_ERROR) { |
805 | ps->rx_errors++; | |
806 | if (status & RX_MISSED_FRAME) | |
807 | ps->rx_missed_errors++; | |
4989ccb2 | 808 | if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) |
5ef3041e FF |
809 | ps->rx_length_errors++; |
810 | if (status & RX_CRC_ERROR) | |
811 | ps->rx_crc_errors++; | |
812 | if (status & RX_COLL) | |
813 | ps->collisions++; | |
2cc3c6b1 | 814 | } else |
5ef3041e | 815 | ps->rx_bytes += status & RX_FRAME_LEN_MASK; |
298cf9be | 816 | |
1da177e4 LT |
817 | } |
818 | ||
6aa20a22 | 819 | /* |
5ef3041e | 820 | * Au1000 receive routine. |
1da177e4 | 821 | */ |
5ef3041e | 822 | static int au1000_rx(struct net_device *dev) |
1da177e4 | 823 | { |
454d7c9b | 824 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 825 | struct sk_buff *skb; |
d0e7cb5d | 826 | struct rx_dma *prxd; |
5ef3041e | 827 | u32 buff_stat, status; |
3441592b | 828 | struct db_dest *pDB; |
5ef3041e | 829 | u32 frmlen; |
1da177e4 | 830 | |
5368c726 | 831 | netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head); |
1da177e4 | 832 | |
5ef3041e FF |
833 | prxd = aup->rx_dma_ring[aup->rx_head]; |
834 | buff_stat = prxd->buff_stat; | |
835 | while (buff_stat & RX_T_DONE) { | |
836 | status = prxd->status; | |
837 | pDB = aup->rx_db_inuse[aup->rx_head]; | |
eb049630 | 838 | au1000_update_rx_stats(dev, status); |
5ef3041e | 839 | if (!(status & RX_ERROR)) { |
1da177e4 | 840 | |
5ef3041e FF |
841 | /* good frame */ |
842 | frmlen = (status & RX_FRAME_LEN_MASK); | |
843 | frmlen -= 4; /* Remove FCS */ | |
1d266430 | 844 | skb = netdev_alloc_skb(dev, frmlen + 2); |
5ef3041e | 845 | if (skb == NULL) { |
5ef3041e FF |
846 | dev->stats.rx_dropped++; |
847 | continue; | |
848 | } | |
849 | skb_reserve(skb, 2); /* 16 byte IP header align */ | |
850 | skb_copy_to_linear_data(skb, | |
851 | (unsigned char *)pDB->vaddr, frmlen); | |
852 | skb_put(skb, frmlen); | |
853 | skb->protocol = eth_type_trans(skb, dev); | |
854 | netif_rx(skb); /* pass the packet to upper layers */ | |
2cc3c6b1 | 855 | } else { |
5ef3041e | 856 | if (au1000_debug > 4) { |
215e17be | 857 | pr_err("rx_error(s):"); |
5ef3041e | 858 | if (status & RX_MISSED_FRAME) |
215e17be | 859 | pr_cont(" miss"); |
5ef3041e | 860 | if (status & RX_WDOG_TIMER) |
215e17be | 861 | pr_cont(" wdog"); |
5ef3041e | 862 | if (status & RX_RUNT) |
215e17be | 863 | pr_cont(" runt"); |
5ef3041e | 864 | if (status & RX_OVERLEN) |
215e17be | 865 | pr_cont(" overlen"); |
5ef3041e | 866 | if (status & RX_COLL) |
215e17be | 867 | pr_cont(" coll"); |
5ef3041e | 868 | if (status & RX_MII_ERROR) |
215e17be | 869 | pr_cont(" mii error"); |
5ef3041e | 870 | if (status & RX_CRC_ERROR) |
215e17be | 871 | pr_cont(" crc error"); |
5ef3041e | 872 | if (status & RX_LEN_ERROR) |
215e17be | 873 | pr_cont(" len error"); |
5ef3041e | 874 | if (status & RX_U_CNTRL_FRAME) |
215e17be FF |
875 | pr_cont(" u control frame"); |
876 | pr_cont("\n"); | |
5ef3041e FF |
877 | } |
878 | } | |
879 | prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); | |
880 | aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); | |
881 | au_sync(); | |
1da177e4 | 882 | |
5ef3041e FF |
883 | /* next descriptor */ |
884 | prxd = aup->rx_dma_ring[aup->rx_head]; | |
885 | buff_stat = prxd->buff_stat; | |
1da177e4 | 886 | } |
1da177e4 LT |
887 | return 0; |
888 | } | |
889 | ||
eb049630 | 890 | static void au1000_update_tx_stats(struct net_device *dev, u32 status) |
1da177e4 | 891 | { |
454d7c9b | 892 | struct au1000_private *aup = netdev_priv(dev); |
5ef3041e | 893 | struct net_device_stats *ps = &dev->stats; |
0638dec0 | 894 | |
5ef3041e FF |
895 | if (status & TX_FRAME_ABORTED) { |
896 | if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) { | |
897 | if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { | |
898 | /* any other tx errors are only valid | |
dc99839c FF |
899 | * in half duplex mode |
900 | */ | |
5ef3041e FF |
901 | ps->tx_errors++; |
902 | ps->tx_aborted_errors++; | |
903 | } | |
2cc3c6b1 | 904 | } else { |
5ef3041e FF |
905 | ps->tx_errors++; |
906 | ps->tx_aborted_errors++; | |
907 | if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) | |
908 | ps->tx_carrier_errors++; | |
909 | } | |
910 | } | |
911 | } | |
0638dec0 | 912 | |
5ef3041e FF |
913 | /* |
914 | * Called from the interrupt service routine to acknowledge | |
915 | * the TX DONE bits. This is a must if the irq is setup as | |
916 | * edge triggered. | |
917 | */ | |
918 | static void au1000_tx_ack(struct net_device *dev) | |
919 | { | |
920 | struct au1000_private *aup = netdev_priv(dev); | |
d0e7cb5d | 921 | struct tx_dma *ptxd; |
0638dec0 | 922 | |
5ef3041e | 923 | ptxd = aup->tx_dma_ring[aup->tx_tail]; |
0638dec0 | 924 | |
5ef3041e | 925 | while (ptxd->buff_stat & TX_T_DONE) { |
eb049630 | 926 | au1000_update_tx_stats(dev, ptxd->status); |
5ef3041e FF |
927 | ptxd->buff_stat &= ~TX_T_DONE; |
928 | ptxd->len = 0; | |
929 | au_sync(); | |
0638dec0 | 930 | |
5ef3041e FF |
931 | aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); |
932 | ptxd = aup->tx_dma_ring[aup->tx_tail]; | |
0638dec0 | 933 | |
5ef3041e FF |
934 | if (aup->tx_full) { |
935 | aup->tx_full = 0; | |
936 | netif_wake_queue(dev); | |
937 | } | |
1da177e4 | 938 | } |
5ef3041e | 939 | } |
1da177e4 | 940 | |
5ef3041e FF |
941 | /* |
942 | * Au1000 interrupt service routine. | |
943 | */ | |
944 | static irqreturn_t au1000_interrupt(int irq, void *dev_id) | |
945 | { | |
946 | struct net_device *dev = dev_id; | |
1da177e4 | 947 | |
5ef3041e FF |
948 | /* Handle RX interrupts first to minimize chance of overrun */ |
949 | ||
950 | au1000_rx(dev); | |
951 | au1000_tx_ack(dev); | |
952 | return IRQ_RETVAL(1); | |
1da177e4 LT |
953 | } |
954 | ||
955 | static int au1000_open(struct net_device *dev) | |
956 | { | |
957 | int retval; | |
454d7c9b | 958 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 959 | |
5368c726 | 960 | netif_dbg(aup, drv, dev, "open: dev=%p\n", dev); |
1da177e4 | 961 | |
2cc3c6b1 FF |
962 | retval = request_irq(dev->irq, au1000_interrupt, 0, |
963 | dev->name, dev); | |
964 | if (retval) { | |
5368c726 | 965 | netdev_err(dev, "unable to get IRQ %d\n", dev->irq); |
0638dec0 HVR |
966 | return retval; |
967 | } | |
968 | ||
2cc3c6b1 FF |
969 | retval = au1000_init(dev); |
970 | if (retval) { | |
5368c726 | 971 | netdev_err(dev, "error in au1000_init\n"); |
1da177e4 LT |
972 | free_irq(dev->irq, dev); |
973 | return retval; | |
974 | } | |
1da177e4 | 975 | |
0638dec0 HVR |
976 | if (aup->phy_dev) { |
977 | /* cause the PHY state machine to schedule a link state check */ | |
978 | aup->phy_dev->state = PHY_CHANGELINK; | |
979 | phy_start(aup->phy_dev); | |
1da177e4 LT |
980 | } |
981 | ||
0638dec0 | 982 | netif_start_queue(dev); |
1da177e4 | 983 | |
5368c726 | 984 | netif_dbg(aup, drv, dev, "open: Initialization done.\n"); |
1da177e4 LT |
985 | |
986 | return 0; | |
987 | } | |
988 | ||
989 | static int au1000_close(struct net_device *dev) | |
990 | { | |
0638dec0 | 991 | unsigned long flags; |
454d7c9b | 992 | struct au1000_private *const aup = netdev_priv(dev); |
1da177e4 | 993 | |
5368c726 | 994 | netif_dbg(aup, drv, dev, "close: dev=%p\n", dev); |
1da177e4 | 995 | |
0638dec0 HVR |
996 | if (aup->phy_dev) |
997 | phy_stop(aup->phy_dev); | |
1da177e4 LT |
998 | |
999 | spin_lock_irqsave(&aup->lock, flags); | |
0638dec0 | 1000 | |
ec7eabdd | 1001 | au1000_reset_mac_unlocked(dev); |
0638dec0 | 1002 | |
1da177e4 LT |
1003 | /* stop the device */ |
1004 | netif_stop_queue(dev); | |
1005 | ||
1006 | /* disable the interrupt */ | |
1007 | free_irq(dev->irq, dev); | |
1008 | spin_unlock_irqrestore(&aup->lock, flags); | |
1009 | ||
1010 | return 0; | |
1011 | } | |
1012 | ||
1da177e4 LT |
1013 | /* |
1014 | * Au1000 transmit routine. | |
1015 | */ | |
61357325 | 1016 | static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) |
1da177e4 | 1017 | { |
454d7c9b | 1018 | struct au1000_private *aup = netdev_priv(dev); |
09f75cd7 | 1019 | struct net_device_stats *ps = &dev->stats; |
d0e7cb5d | 1020 | struct tx_dma *ptxd; |
1da177e4 | 1021 | u32 buff_stat; |
3441592b | 1022 | struct db_dest *pDB; |
1da177e4 LT |
1023 | int i; |
1024 | ||
5368c726 FF |
1025 | netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n", |
1026 | (unsigned)aup, skb->len, | |
1da177e4 LT |
1027 | skb->data, aup->tx_head); |
1028 | ||
1029 | ptxd = aup->tx_dma_ring[aup->tx_head]; | |
1030 | buff_stat = ptxd->buff_stat; | |
1031 | if (buff_stat & TX_DMA_ENABLE) { | |
1032 | /* We've wrapped around and the transmitter is still busy */ | |
1033 | netif_stop_queue(dev); | |
1034 | aup->tx_full = 1; | |
5b548140 | 1035 | return NETDEV_TX_BUSY; |
2cc3c6b1 | 1036 | } else if (buff_stat & TX_T_DONE) { |
eb049630 | 1037 | au1000_update_tx_stats(dev, ptxd->status); |
1da177e4 LT |
1038 | ptxd->len = 0; |
1039 | } | |
1040 | ||
1041 | if (aup->tx_full) { | |
1042 | aup->tx_full = 0; | |
1043 | netif_wake_queue(dev); | |
1044 | } | |
1045 | ||
1046 | pDB = aup->tx_db_inuse[aup->tx_head]; | |
bd2302c2 | 1047 | skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); |
1da177e4 | 1048 | if (skb->len < ETH_ZLEN) { |
ec7eabdd | 1049 | for (i = skb->len; i < ETH_ZLEN; i++) |
1da177e4 | 1050 | ((char *)pDB->vaddr)[i] = 0; |
ec7eabdd | 1051 | |
1da177e4 | 1052 | ptxd->len = ETH_ZLEN; |
2cc3c6b1 | 1053 | } else |
5ef3041e | 1054 | ptxd->len = skb->len; |
1da177e4 | 1055 | |
5ef3041e FF |
1056 | ps->tx_packets++; |
1057 | ps->tx_bytes += ptxd->len; | |
1da177e4 | 1058 | |
5ef3041e FF |
1059 | ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; |
1060 | au_sync(); | |
1061 | dev_kfree_skb(skb); | |
1062 | aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); | |
6ed10654 | 1063 | return NETDEV_TX_OK; |
1da177e4 LT |
1064 | } |
1065 | ||
1da177e4 LT |
1066 | /* |
1067 | * The Tx ring has been full longer than the watchdog timeout | |
1068 | * value. The transmitter must be hung? | |
1069 | */ | |
1070 | static void au1000_tx_timeout(struct net_device *dev) | |
1071 | { | |
5368c726 | 1072 | netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev); |
eb049630 | 1073 | au1000_reset_mac(dev); |
1da177e4 | 1074 | au1000_init(dev); |
1ae5dc34 | 1075 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1da177e4 LT |
1076 | netif_wake_queue(dev); |
1077 | } | |
1078 | ||
d9a92cee | 1079 | static void au1000_multicast_list(struct net_device *dev) |
1da177e4 | 1080 | { |
454d7c9b | 1081 | struct au1000_private *aup = netdev_priv(dev); |
d0e7cb5d | 1082 | u32 reg; |
1da177e4 | 1083 | |
18b8e15b | 1084 | netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); |
d0e7cb5d | 1085 | reg = readl(&aup->mac->control); |
1da177e4 | 1086 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ |
d0e7cb5d | 1087 | reg |= MAC_PROMISCUOUS; |
1da177e4 | 1088 | } else if ((dev->flags & IFF_ALLMULTI) || |
4cd24eaf | 1089 | netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { |
d0e7cb5d FF |
1090 | reg |= MAC_PASS_ALL_MULTI; |
1091 | reg &= ~MAC_PROMISCUOUS; | |
5368c726 | 1092 | netdev_info(dev, "Pass all multicast\n"); |
1da177e4 | 1093 | } else { |
22bedad3 | 1094 | struct netdev_hw_addr *ha; |
1da177e4 LT |
1095 | u32 mc_filter[2]; /* Multicast hash filter */ |
1096 | ||
1097 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
1098 | netdev_for_each_mc_addr(ha, dev) |
1099 | set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, | |
1da177e4 | 1100 | (long *)mc_filter); |
d0e7cb5d FF |
1101 | writel(mc_filter[1], &aup->mac->multi_hash_high); |
1102 | writel(mc_filter[0], &aup->mac->multi_hash_low); | |
1103 | reg &= ~MAC_PROMISCUOUS; | |
1104 | reg |= MAC_HASH_MODE; | |
1da177e4 | 1105 | } |
d0e7cb5d | 1106 | writel(reg, &aup->mac->control); |
1da177e4 LT |
1107 | } |
1108 | ||
1da177e4 LT |
1109 | static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) |
1110 | { | |
454d7c9b | 1111 | struct au1000_private *aup = netdev_priv(dev); |
1da177e4 | 1112 | |
2cc3c6b1 FF |
1113 | if (!netif_running(dev)) |
1114 | return -EINVAL; | |
1da177e4 | 1115 | |
2cc3c6b1 FF |
1116 | if (!aup->phy_dev) |
1117 | return -EINVAL; /* PHY not controllable */ | |
1da177e4 | 1118 | |
28b04113 | 1119 | return phy_mii_ioctl(aup->phy_dev, rq, cmd); |
1da177e4 LT |
1120 | } |
1121 | ||
d9a92cee AB |
1122 | static const struct net_device_ops au1000_netdev_ops = { |
1123 | .ndo_open = au1000_open, | |
1124 | .ndo_stop = au1000_close, | |
1125 | .ndo_start_xmit = au1000_tx, | |
afc4b13d | 1126 | .ndo_set_rx_mode = au1000_multicast_list, |
d9a92cee AB |
1127 | .ndo_do_ioctl = au1000_ioctl, |
1128 | .ndo_tx_timeout = au1000_tx_timeout, | |
1129 | .ndo_set_mac_address = eth_mac_addr, | |
1130 | .ndo_validate_addr = eth_validate_addr, | |
1131 | .ndo_change_mtu = eth_change_mtu, | |
1132 | }; | |
1133 | ||
0cb0568d | 1134 | static int au1000_probe(struct platform_device *pdev) |
5ef3041e | 1135 | { |
2cc3c6b1 | 1136 | static unsigned version_printed; |
5ef3041e | 1137 | struct au1000_private *aup = NULL; |
bd2302c2 | 1138 | struct au1000_eth_platform_data *pd; |
5ef3041e | 1139 | struct net_device *dev = NULL; |
3441592b | 1140 | struct db_dest *pDB, *pDBfree; |
bd2302c2 | 1141 | int irq, i, err = 0; |
553737aa | 1142 | struct resource *base, *macen, *macdma; |
5ef3041e | 1143 | |
bd2302c2 FF |
1144 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1145 | if (!base) { | |
5368c726 | 1146 | dev_err(&pdev->dev, "failed to retrieve base register\n"); |
bd2302c2 FF |
1147 | err = -ENODEV; |
1148 | goto out; | |
1149 | } | |
5ef3041e | 1150 | |
bd2302c2 FF |
1151 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
1152 | if (!macen) { | |
5368c726 | 1153 | dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n"); |
bd2302c2 FF |
1154 | err = -ENODEV; |
1155 | goto out; | |
1156 | } | |
5ef3041e | 1157 | |
bd2302c2 FF |
1158 | irq = platform_get_irq(pdev, 0); |
1159 | if (irq < 0) { | |
5368c726 | 1160 | dev_err(&pdev->dev, "failed to retrieve IRQ\n"); |
bd2302c2 FF |
1161 | err = -ENODEV; |
1162 | goto out; | |
1163 | } | |
5ef3041e | 1164 | |
553737aa ML |
1165 | macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
1166 | if (!macdma) { | |
1167 | dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n"); | |
1168 | err = -ENODEV; | |
1169 | goto out; | |
1170 | } | |
1171 | ||
18b8e15b FF |
1172 | if (!request_mem_region(base->start, resource_size(base), |
1173 | pdev->name)) { | |
5368c726 | 1174 | dev_err(&pdev->dev, "failed to request memory region for base registers\n"); |
bd2302c2 FF |
1175 | err = -ENXIO; |
1176 | goto out; | |
1177 | } | |
1178 | ||
18b8e15b FF |
1179 | if (!request_mem_region(macen->start, resource_size(macen), |
1180 | pdev->name)) { | |
5368c726 | 1181 | dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n"); |
bd2302c2 FF |
1182 | err = -ENXIO; |
1183 | goto err_request; | |
1184 | } | |
5ef3041e | 1185 | |
553737aa ML |
1186 | if (!request_mem_region(macdma->start, resource_size(macdma), |
1187 | pdev->name)) { | |
1188 | dev_err(&pdev->dev, "failed to request MACDMA memory region\n"); | |
1189 | err = -ENXIO; | |
1190 | goto err_macdma; | |
1191 | } | |
1192 | ||
5ef3041e FF |
1193 | dev = alloc_etherdev(sizeof(struct au1000_private)); |
1194 | if (!dev) { | |
bd2302c2 FF |
1195 | err = -ENOMEM; |
1196 | goto err_alloc; | |
5ef3041e FF |
1197 | } |
1198 | ||
bd2302c2 FF |
1199 | SET_NETDEV_DEV(dev, &pdev->dev); |
1200 | platform_set_drvdata(pdev, dev); | |
5ef3041e FF |
1201 | aup = netdev_priv(dev); |
1202 | ||
1203 | spin_lock_init(&aup->lock); | |
18b8e15b FF |
1204 | aup->msg_enable = (au1000_debug < 4 ? |
1205 | AU1000_DEF_MSG_ENABLE : au1000_debug); | |
5ef3041e | 1206 | |
dc99839c FF |
1207 | /* Allocate the data buffers |
1208 | * Snooping works fine with eth on all au1xxx | |
1209 | */ | |
5ef3041e FF |
1210 | aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE * |
1211 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1212 | &aup->dma_addr, 0); | |
1213 | if (!aup->vaddr) { | |
5368c726 | 1214 | dev_err(&pdev->dev, "failed to allocate data buffers\n"); |
bd2302c2 FF |
1215 | err = -ENOMEM; |
1216 | goto err_vaddr; | |
5ef3041e FF |
1217 | } |
1218 | ||
1219 | /* aup->mac is the base address of the MAC's registers */ | |
d0e7cb5d | 1220 | aup->mac = (struct mac_reg *) |
18b8e15b | 1221 | ioremap_nocache(base->start, resource_size(base)); |
bd2302c2 | 1222 | if (!aup->mac) { |
5368c726 | 1223 | dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); |
bd2302c2 FF |
1224 | err = -ENXIO; |
1225 | goto err_remap1; | |
1226 | } | |
5ef3041e | 1227 | |
ec7eabdd | 1228 | /* Setup some variables for quick register address access */ |
d0e7cb5d | 1229 | aup->enable = (u32 *)ioremap_nocache(macen->start, |
18b8e15b | 1230 | resource_size(macen)); |
bd2302c2 | 1231 | if (!aup->enable) { |
5368c726 | 1232 | dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); |
bd2302c2 FF |
1233 | err = -ENXIO; |
1234 | goto err_remap2; | |
1235 | } | |
1236 | aup->mac_id = pdev->id; | |
5ef3041e | 1237 | |
553737aa ML |
1238 | aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma)); |
1239 | if (!aup->macdma) { | |
1240 | dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n"); | |
1241 | err = -ENXIO; | |
1242 | goto err_remap3; | |
1243 | } | |
1244 | ||
1245 | au1000_setup_hw_rings(aup, aup->macdma); | |
5ef3041e | 1246 | |
462ca99c | 1247 | writel(0, aup->enable); |
5ef3041e FF |
1248 | aup->mac_enabled = 0; |
1249 | ||
1fc2c469 | 1250 | pd = dev_get_platdata(&pdev->dev); |
bd2302c2 | 1251 | if (!pd) { |
18b8e15b FF |
1252 | dev_info(&pdev->dev, "no platform_data passed," |
1253 | " PHY search on MAC0\n"); | |
bd2302c2 FF |
1254 | aup->phy1_search_mac0 = 1; |
1255 | } else { | |
7718f2c2 | 1256 | if (is_valid_ether_addr(pd->mac)) { |
d458cdf7 | 1257 | memcpy(dev->dev_addr, pd->mac, ETH_ALEN); |
7718f2c2 DK |
1258 | } else { |
1259 | /* Set a random MAC since no valid provided by platform_data. */ | |
1260 | eth_hw_addr_random(dev); | |
1261 | } | |
f6673653 | 1262 | |
bd2302c2 FF |
1263 | aup->phy_static_config = pd->phy_static_config; |
1264 | aup->phy_search_highest_addr = pd->phy_search_highest_addr; | |
1265 | aup->phy1_search_mac0 = pd->phy1_search_mac0; | |
1266 | aup->phy_addr = pd->phy_addr; | |
1267 | aup->phy_busid = pd->phy_busid; | |
1268 | aup->phy_irq = pd->phy_irq; | |
1269 | } | |
1270 | ||
1271 | if (aup->phy_busid && aup->phy_busid > 0) { | |
18b8e15b | 1272 | dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n"); |
bd2302c2 FF |
1273 | err = -ENODEV; |
1274 | goto err_mdiobus_alloc; | |
1275 | } | |
1276 | ||
5ef3041e | 1277 | aup->mii_bus = mdiobus_alloc(); |
bd2302c2 | 1278 | if (aup->mii_bus == NULL) { |
5368c726 | 1279 | dev_err(&pdev->dev, "failed to allocate mdiobus structure\n"); |
bd2302c2 FF |
1280 | err = -ENOMEM; |
1281 | goto err_mdiobus_alloc; | |
1282 | } | |
5ef3041e FF |
1283 | |
1284 | aup->mii_bus->priv = dev; | |
1285 | aup->mii_bus->read = au1000_mdiobus_read; | |
1286 | aup->mii_bus->write = au1000_mdiobus_write; | |
1287 | aup->mii_bus->reset = au1000_mdiobus_reset; | |
1288 | aup->mii_bus->name = "au1000_eth_mii"; | |
f74299b6 FF |
1289 | snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
1290 | pdev->name, aup->mac_id); | |
5ef3041e | 1291 | aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); |
69129920 PST |
1292 | if (aup->mii_bus->irq == NULL) { |
1293 | err = -ENOMEM; | |
dcbfef82 | 1294 | goto err_out; |
69129920 | 1295 | } |
dcbfef82 | 1296 | |
2cc3c6b1 | 1297 | for (i = 0; i < PHY_MAX_ADDR; ++i) |
5ef3041e | 1298 | aup->mii_bus->irq[i] = PHY_POLL; |
5ef3041e | 1299 | /* if known, set corresponding PHY IRQs */ |
bd2302c2 FF |
1300 | if (aup->phy_static_config) |
1301 | if (aup->phy_irq && aup->phy_busid == aup->mac_id) | |
1302 | aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; | |
1303 | ||
1304 | err = mdiobus_register(aup->mii_bus); | |
1305 | if (err) { | |
5368c726 | 1306 | dev_err(&pdev->dev, "failed to register MDIO bus\n"); |
bd2302c2 FF |
1307 | goto err_mdiobus_reg; |
1308 | } | |
5ef3041e | 1309 | |
69129920 PST |
1310 | err = au1000_mii_probe(dev); |
1311 | if (err != 0) | |
5ef3041e | 1312 | goto err_out; |
5ef3041e FF |
1313 | |
1314 | pDBfree = NULL; | |
1315 | /* setup the data buffer descriptors and attach a buffer to each one */ | |
1316 | pDB = aup->db; | |
1317 | for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { | |
1318 | pDB->pnext = pDBfree; | |
1319 | pDBfree = pDB; | |
1320 | pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); | |
1321 | pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); | |
1322 | pDB++; | |
1323 | } | |
1324 | aup->pDBfree = pDBfree; | |
1325 | ||
69129920 | 1326 | err = -ENODEV; |
5ef3041e | 1327 | for (i = 0; i < NUM_RX_DMA; i++) { |
eb049630 | 1328 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1329 | if (!pDB) |
5ef3041e | 1330 | goto err_out; |
ec7eabdd | 1331 | |
5ef3041e FF |
1332 | aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1333 | aup->rx_db_inuse[i] = pDB; | |
1334 | } | |
69129920 PST |
1335 | |
1336 | err = -ENODEV; | |
5ef3041e | 1337 | for (i = 0; i < NUM_TX_DMA; i++) { |
eb049630 | 1338 | pDB = au1000_GetFreeDB(aup); |
ec7eabdd | 1339 | if (!pDB) |
5ef3041e | 1340 | goto err_out; |
ec7eabdd | 1341 | |
5ef3041e FF |
1342 | aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; |
1343 | aup->tx_dma_ring[i]->len = 0; | |
1344 | aup->tx_db_inuse[i] = pDB; | |
1345 | } | |
1346 | ||
bd2302c2 FF |
1347 | dev->base_addr = base->start; |
1348 | dev->irq = irq; | |
1349 | dev->netdev_ops = &au1000_netdev_ops; | |
7ad24ea4 | 1350 | dev->ethtool_ops = &au1000_ethtool_ops; |
bd2302c2 FF |
1351 | dev->watchdog_timeo = ETH_TX_TIMEOUT; |
1352 | ||
5ef3041e FF |
1353 | /* |
1354 | * The boot code uses the ethernet controller, so reset it to start | |
1355 | * fresh. au1000_init() expects that the device is in reset state. | |
1356 | */ | |
eb049630 | 1357 | au1000_reset_mac(dev); |
5ef3041e | 1358 | |
bd2302c2 FF |
1359 | err = register_netdev(dev); |
1360 | if (err) { | |
5368c726 | 1361 | netdev_err(dev, "Cannot register net device, aborting.\n"); |
bd2302c2 FF |
1362 | goto err_out; |
1363 | } | |
1364 | ||
5368c726 FF |
1365 | netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n", |
1366 | (unsigned long)base->start, irq); | |
bd2302c2 | 1367 | if (version_printed++ == 0) |
215e17be FF |
1368 | pr_info("%s version %s %s\n", |
1369 | DRV_NAME, DRV_VERSION, DRV_AUTHOR); | |
bd2302c2 FF |
1370 | |
1371 | return 0; | |
5ef3041e FF |
1372 | |
1373 | err_out: | |
bd2302c2 | 1374 | if (aup->mii_bus != NULL) |
5ef3041e | 1375 | mdiobus_unregister(aup->mii_bus); |
5ef3041e FF |
1376 | |
1377 | /* here we should have a valid dev plus aup-> register addresses | |
dc99839c FF |
1378 | * so we can reset the mac properly. |
1379 | */ | |
eb049630 | 1380 | au1000_reset_mac(dev); |
5ef3041e FF |
1381 | |
1382 | for (i = 0; i < NUM_RX_DMA; i++) { | |
1383 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1384 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
5ef3041e FF |
1385 | } |
1386 | for (i = 0; i < NUM_TX_DMA; i++) { | |
1387 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1388 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
5ef3041e | 1389 | } |
bd2302c2 FF |
1390 | err_mdiobus_reg: |
1391 | mdiobus_free(aup->mii_bus); | |
1392 | err_mdiobus_alloc: | |
553737aa ML |
1393 | iounmap(aup->macdma); |
1394 | err_remap3: | |
bd2302c2 FF |
1395 | iounmap(aup->enable); |
1396 | err_remap2: | |
1397 | iounmap(aup->mac); | |
1398 | err_remap1: | |
5ef3041e FF |
1399 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), |
1400 | (void *)aup->vaddr, aup->dma_addr); | |
bd2302c2 | 1401 | err_vaddr: |
5ef3041e | 1402 | free_netdev(dev); |
bd2302c2 | 1403 | err_alloc: |
553737aa ML |
1404 | release_mem_region(macdma->start, resource_size(macdma)); |
1405 | err_macdma: | |
bd2302c2 FF |
1406 | release_mem_region(macen->start, resource_size(macen)); |
1407 | err_request: | |
1408 | release_mem_region(base->start, resource_size(base)); | |
1409 | out: | |
1410 | return err; | |
5ef3041e FF |
1411 | } |
1412 | ||
0cb0568d | 1413 | static int au1000_remove(struct platform_device *pdev) |
5ef3041e | 1414 | { |
bd2302c2 FF |
1415 | struct net_device *dev = platform_get_drvdata(pdev); |
1416 | struct au1000_private *aup = netdev_priv(dev); | |
1417 | int i; | |
1418 | struct resource *base, *macen; | |
5ef3041e | 1419 | |
bd2302c2 FF |
1420 | unregister_netdev(dev); |
1421 | mdiobus_unregister(aup->mii_bus); | |
1422 | mdiobus_free(aup->mii_bus); | |
1423 | ||
1424 | for (i = 0; i < NUM_RX_DMA; i++) | |
1425 | if (aup->rx_db_inuse[i]) | |
eb049630 | 1426 | au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); |
bd2302c2 FF |
1427 | |
1428 | for (i = 0; i < NUM_TX_DMA; i++) | |
1429 | if (aup->tx_db_inuse[i]) | |
eb049630 | 1430 | au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); |
bd2302c2 FF |
1431 | |
1432 | dma_free_noncoherent(NULL, MAX_BUF_SIZE * | |
1433 | (NUM_TX_BUFFS + NUM_RX_BUFFS), | |
1434 | (void *)aup->vaddr, aup->dma_addr); | |
1435 | ||
553737aa | 1436 | iounmap(aup->macdma); |
bd2302c2 FF |
1437 | iounmap(aup->mac); |
1438 | iounmap(aup->enable); | |
1439 | ||
553737aa ML |
1440 | base = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
1441 | release_mem_region(base->start, resource_size(base)); | |
1442 | ||
bd2302c2 FF |
1443 | base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1444 | release_mem_region(base->start, resource_size(base)); | |
1445 | ||
1446 | macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1447 | release_mem_region(macen->start, resource_size(macen)); | |
1448 | ||
1449 | free_netdev(dev); | |
5ef3041e | 1450 | |
5ef3041e FF |
1451 | return 0; |
1452 | } | |
1453 | ||
bd2302c2 FF |
1454 | static struct platform_driver au1000_eth_driver = { |
1455 | .probe = au1000_probe, | |
0cb0568d | 1456 | .remove = au1000_remove, |
bd2302c2 FF |
1457 | .driver = { |
1458 | .name = "au1000-eth", | |
1459 | .owner = THIS_MODULE, | |
1460 | }, | |
1461 | }; | |
bd2302c2 | 1462 | |
db62f684 | 1463 | module_platform_driver(au1000_eth_driver); |
5ef3041e | 1464 | |
db62f684 | 1465 | MODULE_ALIAS("platform:au1000-eth"); |