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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Alchemy Au1x00 ethernet driver include file | |
4 | * | |
5 | * Author: Pete Popov <ppopov@mvista.com> | |
6 | * | |
7 | * Copyright 2001 MontaVista Software Inc. | |
8 | * | |
9 | * ######################################################################## | |
10 | * | |
11 | * This program is free software; you can distribute it and/or modify it | |
12 | * under the terms of the GNU General Public License (Version 2) as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope it will be useful, but WITHOUT | |
16 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | * for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
0ab75ae8 | 21 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
1da177e4 LT |
22 | * |
23 | * ######################################################################## | |
24 | * | |
6aa20a22 | 25 | * |
1da177e4 LT |
26 | */ |
27 | ||
28 | ||
29 | #define MAC_IOSIZE 0x10000 | |
30 | #define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */ | |
31 | #define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */ | |
32 | ||
33 | #define NUM_RX_BUFFS 4 | |
34 | #define NUM_TX_BUFFS 4 | |
35 | #define MAX_BUF_SIZE 2048 | |
36 | ||
2cc3c6b1 | 37 | #define ETH_TX_TIMEOUT (HZ/4) |
1da177e4 LT |
38 | #define MAC_MIN_PKT_SIZE 64 |
39 | ||
40 | #define MULTICAST_FILTER_LIMIT 64 | |
41 | ||
6aa20a22 JG |
42 | /* |
43 | * Data Buffer Descriptor. Data buffers must be aligned on 32 byte | |
1da177e4 LT |
44 | * boundary for both, receive and transmit. |
45 | */ | |
3441592b | 46 | struct db_dest { |
1da177e4 | 47 | struct db_dest *pnext; |
d0e7cb5d | 48 | u32 *vaddr; |
1da177e4 | 49 | dma_addr_t dma_addr; |
3441592b | 50 | }; |
1da177e4 LT |
51 | |
52 | /* | |
6aa20a22 | 53 | * The transmit and receive descriptors are memory |
1da177e4 LT |
54 | * mapped registers. |
55 | */ | |
3441592b | 56 | struct tx_dma { |
1da177e4 LT |
57 | u32 status; |
58 | u32 buff_stat; | |
59 | u32 len; | |
60 | u32 pad; | |
3441592b | 61 | }; |
1da177e4 | 62 | |
3441592b | 63 | struct rx_dma { |
1da177e4 LT |
64 | u32 status; |
65 | u32 buff_stat; | |
66 | u32 pad[2]; | |
3441592b | 67 | }; |
1da177e4 LT |
68 | |
69 | ||
70 | /* | |
71 | * MAC control registers, memory mapped. | |
72 | */ | |
3441592b | 73 | struct mac_reg { |
1da177e4 LT |
74 | u32 control; |
75 | u32 mac_addr_high; | |
76 | u32 mac_addr_low; | |
77 | u32 multi_hash_high; | |
78 | u32 multi_hash_low; | |
79 | u32 mii_control; | |
80 | u32 mii_data; | |
81 | u32 flow_control; | |
82 | u32 vlan1_tag; | |
83 | u32 vlan2_tag; | |
3441592b | 84 | }; |
1da177e4 LT |
85 | |
86 | ||
87 | struct au1000_private { | |
3441592b FF |
88 | struct db_dest *pDBfree; |
89 | struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS]; | |
d0e7cb5d FF |
90 | struct rx_dma *rx_dma_ring[NUM_RX_DMA]; |
91 | struct tx_dma *tx_dma_ring[NUM_TX_DMA]; | |
3441592b FF |
92 | struct db_dest *rx_db_inuse[NUM_RX_DMA]; |
93 | struct db_dest *tx_db_inuse[NUM_TX_DMA]; | |
1da177e4 LT |
94 | u32 rx_head; |
95 | u32 tx_head; | |
96 | u32 tx_tail; | |
97 | u32 tx_full; | |
98 | ||
99 | int mac_id; | |
0638dec0 | 100 | |
18b8e15b | 101 | int mac_enabled; /* whether MAC is currently enabled and running |
dc99839c FF |
102 | * (req. for mdio) |
103 | */ | |
0638dec0 HVR |
104 | |
105 | int old_link; /* used by au1000_adjust_link */ | |
106 | int old_speed; | |
107 | int old_duplex; | |
108 | ||
109 | struct phy_device *phy_dev; | |
298cf9be | 110 | struct mii_bus *mii_bus; |
6aa20a22 | 111 | |
bd2302c2 FF |
112 | /* PHY configuration */ |
113 | int phy_static_config; | |
114 | int phy_search_highest_addr; | |
115 | int phy1_search_mac0; | |
116 | ||
117 | int phy_addr; | |
118 | int phy_busid; | |
119 | int phy_irq; | |
120 | ||
18b8e15b | 121 | /* These variables are just for quick access |
dc99839c FF |
122 | * to certain regs addresses. |
123 | */ | |
d0e7cb5d FF |
124 | struct mac_reg *mac; /* mac registers */ |
125 | u32 *enable; /* address of MAC Enable Register */ | |
553737aa | 126 | void __iomem *macdma; /* base of MAC DMA port */ |
1da177e4 LT |
127 | u32 vaddr; /* virtual address of rx/tx buffers */ |
128 | dma_addr_t dma_addr; /* dma address of rx/tx buffers */ | |
129 | ||
1da177e4 | 130 | spinlock_t lock; /* Serialise access to device */ |
7cd2e6e3 FF |
131 | |
132 | u32 msg_enable; | |
1da177e4 | 133 | }; |