[deliverable/linux.git] / drivers / net / ethernet / amd / au1000_eth.h

/*
 *
 * Alchemy Au1x00 ethernet driver include file
 *
 * Author: Pete Popov <ppopov@mvista.com>
 *
 * Copyright 2001 MontaVista Software Inc.
 *
 * ########################################################################
 *
 *  This program is free software; you can distribute it and/or modify it
 *  under the terms of the GNU General Public License (Version 2) as
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 *  for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * ########################################################################
 *
 *
 */


#define MAC_IOSIZE 0x10000
#define NUM_RX_DMA 4       /* Au1x00 has 4 rx hardware descriptors */
#define NUM_TX_DMA 4       /* Au1x00 has 4 tx hardware descriptors */

#define NUM_RX_BUFFS 4
#define NUM_TX_BUFFS 4
#define MAX_BUF_SIZE 2048

#define ETH_TX_TIMEOUT (HZ/4)
#define MAC_MIN_PKT_SIZE 64

#define MULTICAST_FILTER_LIMIT 64

/*
 * Data Buffer Descriptor. Data buffers must be aligned on 32 byte
 * boundary for both, receive and transmit.
 */
struct db_dest {
	struct db_dest *pnext;
	u32 *vaddr;
	dma_addr_t dma_addr;
};

/*
 * The transmit and receive descriptors are memory
 * mapped registers.
 */
struct tx_dma {
	u32 status;
	u32 buff_stat;
	u32 len;
	u32 pad;
};

struct rx_dma {
	u32 status;
	u32 buff_stat;
	u32 pad[2];
};


/*
 * MAC control registers, memory mapped.
 */
struct mac_reg {
	u32 control;
	u32 mac_addr_high;
	u32 mac_addr_low;
	u32 multi_hash_high;
	u32 multi_hash_low;
	u32 mii_control;
	u32 mii_data;
	u32 flow_control;
	u32 vlan1_tag;
	u32 vlan2_tag;
};


struct au1000_private {
	struct db_dest *pDBfree;
	struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS];
	struct rx_dma *rx_dma_ring[NUM_RX_DMA];
	struct tx_dma *tx_dma_ring[NUM_TX_DMA];
	struct db_dest *rx_db_inuse[NUM_RX_DMA];
	struct db_dest *tx_db_inuse[NUM_TX_DMA];
	u32 rx_head;
	u32 tx_head;
	u32 tx_tail;
	u32 tx_full;

	int mac_id;

	int mac_enabled;       /* whether MAC is currently enabled and running
				* (req. for mdio)
				*/

	int old_link;          /* used by au1000_adjust_link */
	int old_speed;
	int old_duplex;

	struct phy_device *phy_dev;
	struct mii_bus *mii_bus;

	/* PHY configuration */
	int phy_static_config;
	int phy_search_highest_addr;
	int phy1_search_mac0;

	int phy_addr;
	int phy_busid;
	int phy_irq;

	/* These variables are just for quick access
	 * to certain regs addresses.
	 */
	struct mac_reg *mac;  /* mac registers                      */
	u32 *enable;     /* address of MAC Enable Register     */
	void __iomem *macdma;	/* base of MAC DMA port */
	u32 vaddr;                /* virtual address of rx/tx buffers   */
	dma_addr_t dma_addr;      /* dma address of rx/tx buffers       */

	spinlock_t lock;       /* Serialise access to device */

	u32 msg_enable;
};
Commit	Line	Data
1da177e4 LT	1	/*
	2	*
	3	* Alchemy Au1x00 ethernet driver include file
	4	*
	5	* Author: Pete Popov <ppopov@mvista.com>
	6	*
	7	* Copyright 2001 MontaVista Software Inc.
	8	*
	9	* ########################################################################
	10	*
	11	* This program is free software; you can distribute it and/or modify it
	12	* under the terms of the GNU General Public License (Version 2) as
	13	* published by the Free Software Foundation.
	14	*
	15	* This program is distributed in the hope it will be useful, but WITHOUT
	16	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	17	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	18	* for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License along
0ab75ae8	21	* with this program; if not, see <http://www.gnu.org/licenses/>.
1da177e4 LT	22	*
	23	* ########################################################################
	24	*
6aa20a22	25	*
1da177e4 LT	26	*/
	27
	28
	29	#define MAC_IOSIZE 0x10000
	30	#define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
	31	#define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
	32
	33	#define NUM_RX_BUFFS 4
	34	#define NUM_TX_BUFFS 4
	35	#define MAX_BUF_SIZE 2048
	36
2cc3c6b1	37	#define ETH_TX_TIMEOUT (HZ/4)
1da177e4 LT	38	#define MAC_MIN_PKT_SIZE 64
	39
	40	#define MULTICAST_FILTER_LIMIT 64
	41
6aa20a22 JG	42	/*
6aa20a22 JG	43	* Data Buffer Descriptor. Data buffers must be aligned on 32 byte
1da177e4 LT	44	* boundary for both, receive and transmit.
1da177e4 LT	45	*/
3441592b	46	struct db_dest {
1da177e4	47	struct db_dest *pnext;
d0e7cb5d	48	u32 *vaddr;
1da177e4	49	dma_addr_t dma_addr;
3441592b	50	};
1da177e4 LT	51
1da177e4 LT	52	/*
6aa20a22	53	* The transmit and receive descriptors are memory
1da177e4 LT	54	* mapped registers.
1da177e4 LT	55	*/
3441592b	56	struct tx_dma {
1da177e4 LT	57	u32 status;
	58	u32 buff_stat;
	59	u32 len;
	60	u32 pad;
3441592b	61	};
1da177e4	62
3441592b	63	struct rx_dma {
1da177e4 LT	64	u32 status;
	65	u32 buff_stat;
	66	u32 pad[2];
3441592b	67	};
1da177e4 LT	68
	69
	70	/*
	71	* MAC control registers, memory mapped.
	72	*/
3441592b	73	struct mac_reg {
1da177e4 LT	74	u32 control;
	75	u32 mac_addr_high;
	76	u32 mac_addr_low;
	77	u32 multi_hash_high;
	78	u32 multi_hash_low;
	79	u32 mii_control;
	80	u32 mii_data;
	81	u32 flow_control;
	82	u32 vlan1_tag;
	83	u32 vlan2_tag;
3441592b	84	};
1da177e4 LT	85
	86
	87	struct au1000_private {
3441592b FF	88	struct db_dest *pDBfree;
3441592b FF	89	struct db_dest db[NUM_RX_BUFFS+NUM_TX_BUFFS];
d0e7cb5d FF	90	struct rx_dma *rx_dma_ring[NUM_RX_DMA];
d0e7cb5d FF	91	struct tx_dma *tx_dma_ring[NUM_TX_DMA];
3441592b FF	92	struct db_dest *rx_db_inuse[NUM_RX_DMA];
3441592b FF	93	struct db_dest *tx_db_inuse[NUM_TX_DMA];
1da177e4 LT	94	u32 rx_head;
	95	u32 tx_head;
	96	u32 tx_tail;
	97	u32 tx_full;
	98
	99	int mac_id;
0638dec0	100
18b8e15b	101	int mac_enabled; /* whether MAC is currently enabled and running
dc99839c FF	102	* (req. for mdio)
dc99839c FF	103	*/
0638dec0 HVR	104
	105	int old_link; /* used by au1000_adjust_link */
	106	int old_speed;
	107	int old_duplex;
	108
	109	struct phy_device *phy_dev;
298cf9be	110	struct mii_bus *mii_bus;
6aa20a22	111
bd2302c2 FF	112	/* PHY configuration */
	113	int phy_static_config;
	114	int phy_search_highest_addr;
	115	int phy1_search_mac0;
	116
	117	int phy_addr;
	118	int phy_busid;
	119	int phy_irq;
	120
18b8e15b	121	/* These variables are just for quick access
dc99839c FF	122	* to certain regs addresses.
dc99839c FF	123	*/
d0e7cb5d FF	124	struct mac_reg mac; / mac registers */
d0e7cb5d FF	125	u32 enable; / address of MAC Enable Register */
553737aa	126	void __iomem macdma; / base of MAC DMA port */
1da177e4 LT	127	u32 vaddr; /* virtual address of rx/tx buffers */
	128	dma_addr_t dma_addr; /* dma address of rx/tx buffers */
	129
1da177e4	130	spinlock_t lock; /* Serialise access to device */
7cd2e6e3 FF	131
7cd2e6e3 FF	132	u32 msg_enable;
1da177e4	133	};