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Merge branch 'for-davem' into for-next
[deliverable/linux.git] / drivers / net / ethernet / amd / xgbe / xgbe-dev.c
CommitLineData
c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#include <linux/phy.h>
c3152d47 118#include <linux/mdio.h>
c5aa9e3b 119#include <linux/clk.h>
801c62d9 120#include <linux/bitrev.h>
b85e4d89 121#include <linux/crc32.h>
c5aa9e3b
LT		 122
123#include "xgbe.h"
124#include "xgbe-common.h"
125
c5aa9e3b
LT		 126static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
127 unsigned int usec)
128{
129 unsigned long rate;
130 unsigned int ret;
131
132 DBGPR("-->xgbe_usec_to_riwt\n");
133
82a19035 134 rate = pdata->sysclk_rate;
c5aa9e3b
LT		 135
136 /*
137 * Convert the input usec value to the watchdog timer value. Each
138 * watchdog timer value is equivalent to 256 clock cycles.
139 * Calculate the required value as:
140 * ( usec * ( system_clock_mhz / 10^6 ) / 256
141 */
142 ret = (usec * (rate / 1000000)) / 256;
143
144 DBGPR("<--xgbe_usec_to_riwt\n");
145
146 return ret;
147}
148
149static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
150 unsigned int riwt)
151{
152 unsigned long rate;
153 unsigned int ret;
154
155 DBGPR("-->xgbe_riwt_to_usec\n");
156
82a19035 157 rate = pdata->sysclk_rate;
c5aa9e3b
LT		 158
159 /*
160 * Convert the input watchdog timer value to the usec value. Each
161 * watchdog timer value is equivalent to 256 clock cycles.
162 * Calculate the required value as:
163 * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
164 */
165 ret = (riwt * 256) / (rate / 1000000);
166
167 DBGPR("<--xgbe_riwt_to_usec\n");
168
169 return ret;
170}
171
172static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
173{
174 struct xgbe_channel *channel;
175 unsigned int i;
176
177 channel = pdata->channel;
178 for (i = 0; i < pdata->channel_count; i++, channel++)
179 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
180 pdata->pblx8);
181
182 return 0;
183}
184
185static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
186{
187 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
188}
189
190static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
191{
192 struct xgbe_channel *channel;
193 unsigned int i;
194
195 channel = pdata->channel;
196 for (i = 0; i < pdata->channel_count; i++, channel++) {
197 if (!channel->tx_ring)
198 break;
199
200 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
201 pdata->tx_pbl);
202 }
203
204 return 0;
205}
206
207static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
208{
209 return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
210}
211
212static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
213{
214 struct xgbe_channel *channel;
215 unsigned int i;
216
217 channel = pdata->channel;
218 for (i = 0; i < pdata->channel_count; i++, channel++) {
219 if (!channel->rx_ring)
220 break;
221
222 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
223 pdata->rx_pbl);
224 }
225
226 return 0;
227}
228
229static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
230{
231 struct xgbe_channel *channel;
232 unsigned int i;
233
234 channel = pdata->channel;
235 for (i = 0; i < pdata->channel_count; i++, channel++) {
236 if (!channel->tx_ring)
237 break;
238
239 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
240 pdata->tx_osp_mode);
241 }
242
243 return 0;
244}
245
246static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
247{
248 unsigned int i;
249
853eb16b 250 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 251 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
252
253 return 0;
254}
255
256static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
257{
258 unsigned int i;
259
853eb16b 260 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 261 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
262
263 return 0;
264}
265
266static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
267 unsigned int val)
268{
269 unsigned int i;
270
853eb16b 271 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 272 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
273
274 return 0;
275}
276
277static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
278 unsigned int val)
279{
280 unsigned int i;
281
853eb16b 282 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 283 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
284
285 return 0;
286}
287
288static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
289{
290 struct xgbe_channel *channel;
291 unsigned int i;
292
293 channel = pdata->channel;
294 for (i = 0; i < pdata->channel_count; i++, channel++) {
295 if (!channel->rx_ring)
296 break;
297
298 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
299 pdata->rx_riwt);
300 }
301
302 return 0;
303}
304
305static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
306{
307 return 0;
308}
309
310static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
311{
312 struct xgbe_channel *channel;
313 unsigned int i;
314
315 channel = pdata->channel;
316 for (i = 0; i < pdata->channel_count; i++, channel++) {
317 if (!channel->rx_ring)
318 break;
319
320 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
321 pdata->rx_buf_size);
322 }
323}
324
325static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
326{
327 struct xgbe_channel *channel;
328 unsigned int i;
329
330 channel = pdata->channel;
331 for (i = 0; i < pdata->channel_count; i++, channel++) {
332 if (!channel->tx_ring)
333 break;
334
335 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
336 }
337}
338
174fd259
LT		 339static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
340{
341 struct xgbe_channel *channel;
342 unsigned int i;
343
344 channel = pdata->channel;
345 for (i = 0; i < pdata->channel_count; i++, channel++) {
346 if (!channel->rx_ring)
347 break;
348
349 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);
350 }
351
352 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
353}
354
5b9dfe29
LT		 355static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
356 unsigned int index, unsigned int val)
357{
358 unsigned int wait;
359 int ret = 0;
360
361 mutex_lock(&pdata->rss_mutex);
362
363 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
364 ret = -EBUSY;
365 goto unlock;
366 }
367
368 XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
369
370 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
371 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
372 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
373 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
374
375 wait = 1000;
376 while (wait--) {
377 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
378 goto unlock;
379
380 usleep_range(1000, 1500);
381 }
382
383 ret = -EBUSY;
384
385unlock:
386 mutex_unlock(&pdata->rss_mutex);
387
388 return ret;
389}
390
391static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
392{
393 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
394 unsigned int *key = (unsigned int *)&pdata->rss_key;
395 int ret;
396
397 while (key_regs--) {
398 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
399 key_regs, *key++);
400 if (ret)
401 return ret;
402 }
403
404 return 0;
405}
406
407static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
408{
409 unsigned int i;
410 int ret;
411
412 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
413 ret = xgbe_write_rss_reg(pdata,
414 XGBE_RSS_LOOKUP_TABLE_TYPE, i,
415 pdata->rss_table[i]);
416 if (ret)
417 return ret;
418 }
419
420 return 0;
421}
422
f6ac8628
LT		 423static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
424{
425 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
426
427 return xgbe_write_rss_hash_key(pdata);
428}
429
430static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
431 const u32 *table)
432{
433 unsigned int i;
434
435 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
436 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
437
438 return xgbe_write_rss_lookup_table(pdata);
439}
440
5b9dfe29
LT		 441static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
442{
443 int ret;
444
445 if (!pdata->hw_feat.rss)
446 return -EOPNOTSUPP;
447
448 /* Program the hash key */
449 ret = xgbe_write_rss_hash_key(pdata);
450 if (ret)
451 return ret;
452
453 /* Program the lookup table */
454 ret = xgbe_write_rss_lookup_table(pdata);
455 if (ret)
456 return ret;
457
458 /* Set the RSS options */
459 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
460
461 /* Enable RSS */
462 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
463
464 return 0;
465}
466
467static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
468{
469 if (!pdata->hw_feat.rss)
470 return -EOPNOTSUPP;
471
472 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
473
474 return 0;
475}
476
477static void xgbe_config_rss(struct xgbe_prv_data *pdata)
478{
479 int ret;
480
481 if (!pdata->hw_feat.rss)
482 return;
483
484 if (pdata->netdev->features & NETIF_F_RXHASH)
485 ret = xgbe_enable_rss(pdata);
486 else
487 ret = xgbe_disable_rss(pdata);
488
489 if (ret)
490 netdev_err(pdata->netdev,
491 "error configuring RSS, RSS disabled\n");
492}
493
c5aa9e3b
LT		 494static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
495{
496 unsigned int max_q_count, q_count;
497 unsigned int reg, reg_val;
498 unsigned int i;
499
500 /* Clear MTL flow control */
853eb16b 501 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 502 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
503
504 /* Clear MAC flow control */
505 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
9fc69aff 506 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
c5aa9e3b
LT		 507 reg = MAC_Q0TFCR;
508 for (i = 0; i < q_count; i++) {
509 reg_val = XGMAC_IOREAD(pdata, reg);
510 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
511 XGMAC_IOWRITE(pdata, reg, reg_val);
512
513 reg += MAC_QTFCR_INC;
514 }
515
516 return 0;
517}
518
519static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
520{
521 unsigned int max_q_count, q_count;
522 unsigned int reg, reg_val;
523 unsigned int i;
524
525 /* Set MTL flow control */
853eb16b 526 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 527 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
528
529 /* Set MAC flow control */
530 max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
9fc69aff 531 q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
c5aa9e3b
LT		 532 reg = MAC_Q0TFCR;
533 for (i = 0; i < q_count; i++) {
534 reg_val = XGMAC_IOREAD(pdata, reg);
535
536 /* Enable transmit flow control */
537 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
538 /* Set pause time */
539 XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
540
541 XGMAC_IOWRITE(pdata, reg, reg_val);
542
543 reg += MAC_QTFCR_INC;
544 }
545
546 return 0;
547}
548
549static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
550{
551 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
552
553 return 0;
554}
555
556static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
557{
558 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
559
560 return 0;
561}
562
563static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
564{
fca2d994
LT		 565 struct ieee_pfc *pfc = pdata->pfc;
566
567 if (pdata->tx_pause || (pfc && pfc->pfc_en))
c5aa9e3b
LT		 568 xgbe_enable_tx_flow_control(pdata);
569 else
570 xgbe_disable_tx_flow_control(pdata);
571
572 return 0;
573}
574
575static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
576{
fca2d994
LT		 577 struct ieee_pfc *pfc = pdata->pfc;
578
579 if (pdata->rx_pause || (pfc && pfc->pfc_en))
c5aa9e3b
LT		 580 xgbe_enable_rx_flow_control(pdata);
581 else
582 xgbe_disable_rx_flow_control(pdata);
583
584 return 0;
585}
586
587static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
588{
fca2d994
LT		 589 struct ieee_pfc *pfc = pdata->pfc;
590
c5aa9e3b
LT		 591 xgbe_config_tx_flow_control(pdata);
592 xgbe_config_rx_flow_control(pdata);
fca2d994
LT		 593
594 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
595 (pfc && pfc->pfc_en) ? 1 : 0);
c5aa9e3b
LT		 596}
597
598static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
599{
600 struct xgbe_channel *channel;
601 unsigned int dma_ch_isr, dma_ch_ier;
602 unsigned int i;
603
604 channel = pdata->channel;
605 for (i = 0; i < pdata->channel_count; i++, channel++) {
606 /* Clear all the interrupts which are set */
607 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
608 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
609
610 /* Clear all interrupt enable bits */
611 dma_ch_ier = 0;
612
613 /* Enable following interrupts
614 * NIE - Normal Interrupt Summary Enable
615 * AIE - Abnormal Interrupt Summary Enable
616 * FBEE - Fatal Bus Error Enable
617 */
618 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
619 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
620 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
621
622 if (channel->tx_ring) {
623 /* Enable the following Tx interrupts
9227dc5e
LT		 624 * TIE - Transmit Interrupt Enable (unless using
625 * per channel interrupts)
c5aa9e3b 626 */
9227dc5e
LT		 627 if (!pdata->per_channel_irq)
628 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
c5aa9e3b
LT		 629 }
630 if (channel->rx_ring) {
631 /* Enable following Rx interrupts
632 * RBUE - Receive Buffer Unavailable Enable
9227dc5e
LT		 633 * RIE - Receive Interrupt Enable (unless using
634 * per channel interrupts)
c5aa9e3b
LT		 635 */
636 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
9227dc5e
LT		 637 if (!pdata->per_channel_irq)
638 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
c5aa9e3b
LT		 639 }
640
641 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
642 }
643}
644
645static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
646{
647 unsigned int mtl_q_isr;
648 unsigned int q_count, i;
649
650 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
651 for (i = 0; i < q_count; i++) {
652 /* Clear all the interrupts which are set */
653 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
654 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
655
656 /* No MTL interrupts to be enabled */
91f87345 657 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
c5aa9e3b
LT		 658 }
659}
660
661static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
662{
23e4eef7
LT		 663 unsigned int mac_ier = 0;
664
665 /* Enable Timestamp interrupt */
666 XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
667
668 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
c5aa9e3b
LT		 669
670 /* Enable all counter interrupts */
a3ba7c98
LT		 671 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
672 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
c5aa9e3b
LT		 673}
674
675static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
676{
c3152d47
LT		 677 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3)
678 return 0;
679
c5aa9e3b
LT		 680 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
681
682 return 0;
683}
684
685static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
686{
c3152d47
LT		 687 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2)
688 return 0;
689
c5aa9e3b
LT		 690 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
691
692 return 0;
693}
694
695static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
696{
c3152d47
LT		 697 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0)
698 return 0;
699
c5aa9e3b
LT		 700 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
701
702 return 0;
703}
704
705static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
706 unsigned int enable)
707{
708 unsigned int val = enable ? 1 : 0;
709
710 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
711 return 0;
712
713 DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving");
714 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
715
716 return 0;
717}
718
719static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
720 unsigned int enable)
721{
722 unsigned int val = enable ? 1 : 0;
723
724 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
725 return 0;
726
727 DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving");
728 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
729
730 return 0;
731}
732
b85e4d89
LT		 733static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
734 struct netdev_hw_addr *ha, unsigned int *mac_reg)
c5aa9e3b 735{
c5aa9e3b
LT		 736 unsigned int mac_addr_hi, mac_addr_lo;
737 u8 *mac_addr;
c5aa9e3b 738
b85e4d89
LT		 739 mac_addr_lo = 0;
740 mac_addr_hi = 0;
c5aa9e3b 741
b85e4d89 742 if (ha) {
c5aa9e3b
LT		 743 mac_addr = (u8 *)&mac_addr_lo;
744 mac_addr[0] = ha->addr[0];
745 mac_addr[1] = ha->addr[1];
746 mac_addr[2] = ha->addr[2];
747 mac_addr[3] = ha->addr[3];
748 mac_addr = (u8 *)&mac_addr_hi;
749 mac_addr[0] = ha->addr[4];
750 mac_addr[1] = ha->addr[5];
751
b85e4d89
LT		 752 DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr,
753 *mac_reg);
c5aa9e3b
LT		 754
755 XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
b85e4d89 756 }
c5aa9e3b 757
b85e4d89
LT		 758 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
759 *mac_reg += MAC_MACA_INC;
760 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
761 *mac_reg += MAC_MACA_INC;
762}
c5aa9e3b 763
b85e4d89
LT		 764static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
765{
766 struct net_device *netdev = pdata->netdev;
767 struct netdev_hw_addr *ha;
768 unsigned int mac_reg;
769 unsigned int addn_macs;
770
771 mac_reg = MAC_MACA1HR;
772 addn_macs = pdata->hw_feat.addn_mac;
c5aa9e3b 773
b85e4d89
LT		 774 if (netdev_uc_count(netdev) > addn_macs) {
775 xgbe_set_promiscuous_mode(pdata, 1);
776 } else {
777 netdev_for_each_uc_addr(ha, netdev) {
778 xgbe_set_mac_reg(pdata, ha, &mac_reg);
779 addn_macs--;
780 }
781
782 if (netdev_mc_count(netdev) > addn_macs) {
783 xgbe_set_all_multicast_mode(pdata, 1);
784 } else {
785 netdev_for_each_mc_addr(ha, netdev) {
786 xgbe_set_mac_reg(pdata, ha, &mac_reg);
787 addn_macs--;
788 }
c5aa9e3b
LT		 789 }
790 }
791
792 /* Clear remaining additional MAC address entries */
b85e4d89
LT		 793 while (addn_macs--)
794 xgbe_set_mac_reg(pdata, NULL, &mac_reg);
795}
796
797static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
798{
799 struct net_device *netdev = pdata->netdev;
800 struct netdev_hw_addr *ha;
801 unsigned int hash_reg;
802 unsigned int hash_table_shift, hash_table_count;
803 u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
804 u32 crc;
805 unsigned int i;
806
807 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
808 hash_table_count = pdata->hw_feat.hash_table_size / 32;
809 memset(hash_table, 0, sizeof(hash_table));
810
811 /* Build the MAC Hash Table register values */
812 netdev_for_each_uc_addr(ha, netdev) {
813 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
814 crc >>= hash_table_shift;
815 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
816 }
817
818 netdev_for_each_mc_addr(ha, netdev) {
819 crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
820 crc >>= hash_table_shift;
821 hash_table[crc >> 5] |= (1 << (crc & 0x1f));
c5aa9e3b
LT		 822 }
823
b85e4d89
LT		 824 /* Set the MAC Hash Table registers */
825 hash_reg = MAC_HTR0;
826 for (i = 0; i < hash_table_count; i++) {
827 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
828 hash_reg += MAC_HTR_INC;
829 }
830}
831
832static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
833{
834 if (pdata->hw_feat.hash_table_size)
835 xgbe_set_mac_hash_table(pdata);
836 else
837 xgbe_set_mac_addn_addrs(pdata);
838
c5aa9e3b
LT		 839 return 0;
840}
841
842static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
843{
844 unsigned int mac_addr_hi, mac_addr_lo;
845
846 mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
847 mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
848 (addr[1] << 8) | (addr[0] << 0);
849
850 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
851 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
852
853 return 0;
854}
855
856static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
857 int mmd_reg)
858{
859 unsigned int mmd_address;
860 int mmd_data;
861
862 if (mmd_reg & MII_ADDR_C45)
863 mmd_address = mmd_reg & ~MII_ADDR_C45;
864 else
865 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
866
867 /* The PCS registers are accessed using mmio. The underlying APB3
868 * management interface uses indirect addressing to access the MMD
869 * register sets. This requires accessing of the PCS register in two
870 * phases, an address phase and a data phase.
871 *
872 * The mmio interface is based on 32-bit offsets and values. All
873 * register offsets must therefore be adjusted by left shifting the
874 * offset 2 bits and reading 32 bits of data.
875 */
876 mutex_lock(&pdata->xpcs_mutex);
877 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
878 mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
879 mutex_unlock(&pdata->xpcs_mutex);
880
881 return mmd_data;
882}
883
884static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
885 int mmd_reg, int mmd_data)
886{
887 unsigned int mmd_address;
888
889 if (mmd_reg & MII_ADDR_C45)
890 mmd_address = mmd_reg & ~MII_ADDR_C45;
891 else
892 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
893
c3152d47
LT		 894 /* If the PCS is changing modes, match the MAC speed to it */
895 if (((mmd_address >> 16) == MDIO_MMD_PCS) &&
896 ((mmd_address & 0xffff) == MDIO_CTRL2)) {
897 struct phy_device *phydev = pdata->phydev;
898
899 if (mmd_data & MDIO_PCS_CTRL2_TYPE) {
900 /* KX mode */
901 if (phydev->supported & SUPPORTED_1000baseKX_Full)
902 xgbe_set_gmii_speed(pdata);
903 else
904 xgbe_set_gmii_2500_speed(pdata);
905 } else {
906 /* KR mode */
907 xgbe_set_xgmii_speed(pdata);
908 }
909 }
910
c5aa9e3b
LT		 911 /* The PCS registers are accessed using mmio. The underlying APB3
912 * management interface uses indirect addressing to access the MMD
913 * register sets. This requires accessing of the PCS register in two
914 * phases, an address phase and a data phase.
915 *
916 * The mmio interface is based on 32-bit offsets and values. All
917 * register offsets must therefore be adjusted by left shifting the
918 * offset 2 bits and reading 32 bits of data.
919 */
920 mutex_lock(&pdata->xpcs_mutex);
921 XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
922 XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
923 mutex_unlock(&pdata->xpcs_mutex);
924}
925
926static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
927{
928 return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
929}
930
931static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
932{
933 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
934
935 return 0;
936}
937
938static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
939{
940 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
941
942 return 0;
943}
944
945static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
946{
947 /* Put the VLAN tag in the Rx descriptor */
948 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
949
950 /* Don't check the VLAN type */
951 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
952
953 /* Check only C-TAG (0x8100) packets */
954 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
955
956 /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
957 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
958
959 /* Enable VLAN tag stripping */
960 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
961
962 return 0;
963}
964
965static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
966{
967 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
968
969 return 0;
970}
971
801c62d9
LT		 972static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
973{
974 /* Enable VLAN filtering */
975 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
976
977 /* Enable VLAN Hash Table filtering */
978 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
979
980 /* Disable VLAN tag inverse matching */
981 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
982
983 /* Only filter on the lower 12-bits of the VLAN tag */
984 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
985
986 /* In order for the VLAN Hash Table filtering to be effective,
987 * the VLAN tag identifier in the VLAN Tag Register must not
988 * be zero. Set the VLAN tag identifier to "1" to enable the
989 * VLAN Hash Table filtering. This implies that a VLAN tag of
990 * 1 will always pass filtering.
991 */
992 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
993
994 return 0;
995}
996
997static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
998{
999 /* Disable VLAN filtering */
1000 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
1001
1002 return 0;
1003}
1004
1005#ifndef CRCPOLY_LE
1006#define CRCPOLY_LE 0xedb88320
1007#endif
1008static u32 xgbe_vid_crc32_le(__le16 vid_le)
1009{
1010 u32 poly = CRCPOLY_LE;
1011 u32 crc = ~0;
1012 u32 temp = 0;
1013 unsigned char *data = (unsigned char *)&vid_le;
1014 unsigned char data_byte = 0;
1015 int i, bits;
1016
1017 bits = get_bitmask_order(VLAN_VID_MASK);
1018 for (i = 0; i < bits; i++) {
1019 if ((i % 8) == 0)
1020 data_byte = data[i / 8];
1021
1022 temp = ((crc & 1) ^ data_byte) & 1;
1023 crc >>= 1;
1024 data_byte >>= 1;
1025
1026 if (temp)
1027 crc ^= poly;
1028 }
1029
1030 return crc;
1031}
1032
1033static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
1034{
1035 u32 crc;
1036 u16 vid;
1037 __le16 vid_le;
1038 u16 vlan_hash_table = 0;
1039
1040 /* Generate the VLAN Hash Table value */
1041 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
1042 /* Get the CRC32 value of the VLAN ID */
1043 vid_le = cpu_to_le16(vid);
1044 crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
1045
1046 vlan_hash_table |= (1 << crc);
1047 }
1048
1049 /* Set the VLAN Hash Table filtering register */
1050 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
1051
1052 return 0;
1053}
1054
c5aa9e3b
LT		 1055static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
1056{
1057 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1058
1059 /* Reset the Tx descriptor
1060 * Set buffer 1 (lo) address to zero
1061 * Set buffer 1 (hi) address to zero
1062 * Reset all other control bits (IC, TTSE, B2L & B1L)
1063 * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
1064 */
1065 rdesc->desc0 = 0;
1066 rdesc->desc1 = 0;
1067 rdesc->desc2 = 0;
1068 rdesc->desc3 = 0;
08dcc47c
LT		 1069
1070 /* Make sure ownership is written to the descriptor */
ceb8f6be 1071 dma_wmb();
c5aa9e3b
LT		 1072}
1073
1074static void xgbe_tx_desc_init(struct xgbe_channel *channel)
1075{
1076 struct xgbe_ring *ring = channel->tx_ring;
1077 struct xgbe_ring_data *rdata;
c5aa9e3b
LT		 1078 int i;
1079 int start_index = ring->cur;
1080
1081 DBGPR("-->tx_desc_init\n");
1082
1083 /* Initialze all descriptors */
1084 for (i = 0; i < ring->rdesc_count; i++) {
d0a8ba6c 1085 rdata = XGBE_GET_DESC_DATA(ring, i);
c5aa9e3b 1086
08dcc47c
LT		 1087 /* Initialize Tx descriptor */
1088 xgbe_tx_desc_reset(rdata);
1089 }
c5aa9e3b
LT		 1090
1091 /* Update the total number of Tx descriptors */
1092 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
1093
1094 /* Update the starting address of descriptor ring */
d0a8ba6c 1095 rdata = XGBE_GET_DESC_DATA(ring, start_index);
c5aa9e3b
LT		 1096 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
1097 upper_32_bits(rdata->rdesc_dma));
1098 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
1099 lower_32_bits(rdata->rdesc_dma));
1100
1101 DBGPR("<--tx_desc_init\n");
1102}
1103
1104static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata)
1105{
1106 struct xgbe_ring_desc *rdesc = rdata->rdesc;
1107
1108 /* Reset the Rx descriptor
174fd259
LT		 1109 * Set buffer 1 (lo) address to header dma address (lo)
1110 * Set buffer 1 (hi) address to header dma address (hi)
1111 * Set buffer 2 (lo) address to buffer dma address (lo)
1112 * Set buffer 2 (hi) address to buffer dma address (hi) and
1113 * set control bits OWN and INTE
c5aa9e3b 1114 */
c9f140eb
LT		 1115 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->rx.hdr.dma));
1116 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->rx.hdr.dma));
1117 rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->rx.buf.dma));
1118 rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->rx.buf.dma));
c5aa9e3b 1119
174fd259
LT		 1120 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE,
1121 rdata->interrupt ? 1 : 0);
c5aa9e3b
LT		 1122
1123 /* Since the Rx DMA engine is likely running, make sure everything
1124 * is written to the descriptor(s) before setting the OWN bit
1125 * for the descriptor
1126 */
ceb8f6be 1127 dma_wmb();
c5aa9e3b
LT		 1128
1129 XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
1130
1131 /* Make sure ownership is written to the descriptor */
ceb8f6be 1132 dma_wmb();
c5aa9e3b
LT		 1133}
1134
1135static void xgbe_rx_desc_init(struct xgbe_channel *channel)
1136{
1137 struct xgbe_prv_data *pdata = channel->pdata;
1138 struct xgbe_ring *ring = channel->rx_ring;
1139 struct xgbe_ring_data *rdata;
c5aa9e3b
LT		 1140 unsigned int start_index = ring->cur;
1141 unsigned int rx_coalesce, rx_frames;
1142 unsigned int i;
1143
1144 DBGPR("-->rx_desc_init\n");
1145
1146 rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0;
1147 rx_frames = pdata->rx_frames;
1148
1149 /* Initialize all descriptors */
1150 for (i = 0; i < ring->rdesc_count; i++) {
d0a8ba6c 1151 rdata = XGBE_GET_DESC_DATA(ring, i);
08dcc47c
LT		 1152
1153 /* Set interrupt on completion bit as appropriate */
1154 if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames)))
c5aa9e3b 1155 rdata->interrupt = 0;
08dcc47c
LT		 1156 else
1157 rdata->interrupt = 1;
c5aa9e3b 1158
08dcc47c
LT		 1159 /* Initialize Rx descriptor */
1160 xgbe_rx_desc_reset(rdata);
1161 }
c5aa9e3b
LT		 1162
1163 /* Update the total number of Rx descriptors */
1164 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
1165
1166 /* Update the starting address of descriptor ring */
d0a8ba6c 1167 rdata = XGBE_GET_DESC_DATA(ring, start_index);
c5aa9e3b
LT		 1168 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
1169 upper_32_bits(rdata->rdesc_dma));
1170 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
1171 lower_32_bits(rdata->rdesc_dma));
1172
1173 /* Update the Rx Descriptor Tail Pointer */
d0a8ba6c 1174 rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
c5aa9e3b
LT		 1175 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
1176 lower_32_bits(rdata->rdesc_dma));
1177
1178 DBGPR("<--rx_desc_init\n");
1179}
1180
23e4eef7
LT		 1181static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1182 unsigned int addend)
1183{
1184 /* Set the addend register value and tell the device */
1185 XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1186 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1187
1188 /* Wait for addend update to complete */
1189 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1190 udelay(5);
1191}
1192
1193static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1194 unsigned int nsec)
1195{
1196 /* Set the time values and tell the device */
1197 XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1198 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1199 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1200
1201 /* Wait for time update to complete */
1202 while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1203 udelay(5);
1204}
1205
1206static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1207{
1208 u64 nsec;
1209
1210 nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1211 nsec *= NSEC_PER_SEC;
1212 nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1213
1214 return nsec;
1215}
1216
1217static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1218{
1219 unsigned int tx_snr;
1220 u64 nsec;
1221
1222 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1223 if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1224 return 0;
1225
1226 nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
1227 nsec *= NSEC_PER_SEC;
1228 nsec += tx_snr;
1229
1230 return nsec;
1231}
1232
1233static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1234 struct xgbe_ring_desc *rdesc)
1235{
1236 u64 nsec;
1237
1238 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1239 !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1240 nsec = le32_to_cpu(rdesc->desc1);
1241 nsec <<= 32;
1242 nsec |= le32_to_cpu(rdesc->desc0);
1243 if (nsec != 0xffffffffffffffffULL) {
1244 packet->rx_tstamp = nsec;
1245 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1246 RX_TSTAMP, 1);
1247 }
1248 }
1249}
1250
1251static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1252 unsigned int mac_tscr)
1253{
1254 /* Set one nano-second accuracy */
1255 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1256
1257 /* Set fine timestamp update */
1258 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1259
1260 /* Overwrite earlier timestamps */
1261 XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1262
1263 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1264
1265 /* Exit if timestamping is not enabled */
1266 if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1267 return 0;
1268
1269 /* Initialize time registers */
1270 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1271 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1272 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1273 xgbe_set_tstamp_time(pdata, 0, 0);
1274
1275 /* Initialize the timecounter */
1276 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1277 ktime_to_ns(ktime_get_real()));
1278
1279 return 0;
1280}
1281
fca2d994
LT		 1282static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
1283{
1284 struct ieee_ets *ets = pdata->ets;
1285 unsigned int total_weight, min_weight, weight;
1286 unsigned int i;
1287
1288 if (!ets)
1289 return;
1290
1291 /* Set Tx to deficit weighted round robin scheduling algorithm (when
1292 * traffic class is using ETS algorithm)
1293 */
1294 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
1295
1296 /* Set Traffic Class algorithms */
1297 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
1298 min_weight = total_weight / 100;
1299 if (!min_weight)
1300 min_weight = 1;
1301
1302 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1303 switch (ets->tc_tsa[i]) {
1304 case IEEE_8021QAZ_TSA_STRICT:
1305 DBGPR(" TC%u using SP\n", i);
1306 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1307 MTL_TSA_SP);
1308 break;
1309 case IEEE_8021QAZ_TSA_ETS:
1310 weight = total_weight * ets->tc_tx_bw[i] / 100;
1311 weight = clamp(weight, min_weight, total_weight);
1312
1313 DBGPR(" TC%u using DWRR (weight %u)\n", i, weight);
1314 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1315 MTL_TSA_ETS);
1316 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
1317 weight);
1318 break;
1319 }
1320 }
1321}
1322
1323static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
1324{
1325 struct ieee_pfc *pfc = pdata->pfc;
1326 struct ieee_ets *ets = pdata->ets;
1327 unsigned int mask, reg, reg_val;
1328 unsigned int tc, prio;
1329
1330 if (!pfc || !ets)
1331 return;
1332
1333 for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
1334 mask = 0;
1335 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
1336 if ((pfc->pfc_en & (1 << prio)) &&
1337 (ets->prio_tc[prio] == tc))
1338 mask |= (1 << prio);
1339 }
1340 mask &= 0xff;
1341
1342 DBGPR(" TC%u PFC mask=%#x\n", tc, mask);
1343 reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
1344 reg_val = XGMAC_IOREAD(pdata, reg);
1345
1346 reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1347 reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
1348
1349 XGMAC_IOWRITE(pdata, reg, reg_val);
1350 }
1351
1352 xgbe_config_flow_control(pdata);
1353}
1354
16958a2b
LT		 1355static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1356 struct xgbe_ring *ring)
1357{
1358 struct xgbe_prv_data *pdata = channel->pdata;
1359 struct xgbe_ring_data *rdata;
1360
ceb8f6be
LT		 1361 /* Make sure everything is written before the register write */
1362 wmb();
1363
16958a2b
LT		 1364 /* Issue a poll command to Tx DMA by writing address
1365 * of next immediate free descriptor */
1366 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
1367 XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
1368 lower_32_bits(rdata->rdesc_dma));
1369
c635eaac 1370 /* Start the Tx timer */
16958a2b
LT		 1371 if (pdata->tx_usecs && !channel->tx_timer_active) {
1372 channel->tx_timer_active = 1;
c635eaac
LT		 1373 mod_timer(&channel->tx_timer,
1374 jiffies + usecs_to_jiffies(pdata->tx_usecs));
16958a2b
LT		 1375 }
1376
1377 ring->tx.xmit_more = 0;
1378}
1379
a9d41981 1380static void xgbe_dev_xmit(struct xgbe_channel *channel)
c5aa9e3b
LT		 1381{
1382 struct xgbe_prv_data *pdata = channel->pdata;
1383 struct xgbe_ring *ring = channel->tx_ring;
1384 struct xgbe_ring_data *rdata;
1385 struct xgbe_ring_desc *rdesc;
1386 struct xgbe_packet_data *packet = &ring->packet_data;
1387 unsigned int csum, tso, vlan;
1388 unsigned int tso_context, vlan_context;
eb79e640 1389 unsigned int tx_set_ic;
c5aa9e3b 1390 int start_index = ring->cur;
a83ef427 1391 int cur_index = ring->cur;
c5aa9e3b
LT		 1392 int i;
1393
a9d41981 1394 DBGPR("-->xgbe_dev_xmit\n");
c5aa9e3b
LT		 1395
1396 csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1397 CSUM_ENABLE);
1398 tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1399 TSO_ENABLE);
1400 vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
1401 VLAN_CTAG);
1402
1403 if (tso && (packet->mss != ring->tx.cur_mss))
1404 tso_context = 1;
1405 else
1406 tso_context = 0;
1407
1408 if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
1409 vlan_context = 1;
1410 else
1411 vlan_context = 0;
1412
eb79e640
LT		 1413 /* Determine if an interrupt should be generated for this Tx:
1414 * Interrupt:
1415 * - Tx frame count exceeds the frame count setting
1416 * - Addition of Tx frame count to the frame count since the
1417 * last interrupt was set exceeds the frame count setting
1418 * No interrupt:
1419 * - No frame count setting specified (ethtool -C ethX tx-frames 0)
1420 * - Addition of Tx frame count to the frame count since the
1421 * last interrupt was set does not exceed the frame count setting
1422 */
1423 ring->coalesce_count += packet->tx_packets;
1424 if (!pdata->tx_frames)
1425 tx_set_ic = 0;
1426 else if (packet->tx_packets > pdata->tx_frames)
1427 tx_set_ic = 1;
1428 else if ((ring->coalesce_count % pdata->tx_frames) <
1429 packet->tx_packets)
1430 tx_set_ic = 1;
1431 else
1432 tx_set_ic = 0;
c5aa9e3b 1433
a83ef427 1434 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
c5aa9e3b
LT		 1435 rdesc = rdata->rdesc;
1436
1437 /* Create a context descriptor if this is a TSO packet */
1438 if (tso_context || vlan_context) {
1439 if (tso_context) {
1440 DBGPR(" TSO context descriptor, mss=%u\n",
1441 packet->mss);
1442
1443 /* Set the MSS size */
1444 XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
1445 MSS, packet->mss);
1446
1447 /* Mark it as a CONTEXT descriptor */
1448 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1449 CTXT, 1);
1450
1451 /* Indicate this descriptor contains the MSS */
1452 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1453 TCMSSV, 1);
1454
1455 ring->tx.cur_mss = packet->mss;
1456 }
1457
1458 if (vlan_context) {
1459 DBGPR(" VLAN context descriptor, ctag=%u\n",
1460 packet->vlan_ctag);
1461
1462 /* Mark it as a CONTEXT descriptor */
1463 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1464 CTXT, 1);
1465
1466 /* Set the VLAN tag */
1467 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1468 VT, packet->vlan_ctag);
1469
1470 /* Indicate this descriptor contains the VLAN tag */
1471 XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
1472 VLTV, 1);
1473
1474 ring->tx.cur_vlan_ctag = packet->vlan_ctag;
1475 }
1476
a83ef427
LT		 1477 cur_index++;
1478 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
c5aa9e3b
LT		 1479 rdesc = rdata->rdesc;
1480 }
1481
1482 /* Update buffer address (for TSO this is the header) */
1483 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1484 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1485
1486 /* Update the buffer length */
1487 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1488 rdata->skb_dma_len);
1489
1490 /* VLAN tag insertion check */
1491 if (vlan)
1492 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
1493 TX_NORMAL_DESC2_VLAN_INSERT);
1494
23e4eef7
LT		 1495 /* Timestamp enablement check */
1496 if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
1497 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
1498
c5aa9e3b
LT		 1499 /* Mark it as First Descriptor */
1500 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
1501
1502 /* Mark it as a NORMAL descriptor */
1503 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1504
1505 /* Set OWN bit if not the first descriptor */
a83ef427 1506 if (cur_index != start_index)
c5aa9e3b
LT		 1507 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1508
1509 if (tso) {
1510 /* Enable TSO */
1511 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
1512 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
1513 packet->tcp_payload_len);
1514 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
1515 packet->tcp_header_len / 4);
1516 } else {
1517 /* Enable CRC and Pad Insertion */
1518 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
1519
1520 /* Enable HW CSUM */
1521 if (csum)
1522 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1523 CIC, 0x3);
1524
1525 /* Set the total length to be transmitted */
1526 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
1527 packet->length);
1528 }
1529
a83ef427
LT		 1530 for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
1531 cur_index++;
1532 rdata = XGBE_GET_DESC_DATA(ring, cur_index);
c5aa9e3b
LT		 1533 rdesc = rdata->rdesc;
1534
1535 /* Update buffer address */
1536 rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
1537 rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
1538
1539 /* Update the buffer length */
1540 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
1541 rdata->skb_dma_len);
1542
c5aa9e3b
LT		 1543 /* Set OWN bit */
1544 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1545
1546 /* Mark it as NORMAL descriptor */
1547 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
1548
1549 /* Enable HW CSUM */
1550 if (csum)
1551 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
1552 CIC, 0x3);
1553 }
1554
1555 /* Set LAST bit for the last descriptor */
1556 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
1557
eb79e640
LT		 1558 /* Set IC bit based on Tx coalescing settings */
1559 if (tx_set_ic)
1560 XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
1561
5fb4b86a
LT		 1562 /* Save the Tx info to report back during cleanup */
1563 rdata->tx.packets = packet->tx_packets;
1564 rdata->tx.bytes = packet->tx_bytes;
1565
c5aa9e3b
LT		 1566 /* In case the Tx DMA engine is running, make sure everything
1567 * is written to the descriptor(s) before setting the OWN bit
1568 * for the first descriptor
1569 */
ceb8f6be 1570 dma_wmb();
c5aa9e3b
LT		 1571
1572 /* Set OWN bit for the first descriptor */
d0a8ba6c 1573 rdata = XGBE_GET_DESC_DATA(ring, start_index);
c5aa9e3b
LT		 1574 rdesc = rdata->rdesc;
1575 XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
1576
1577#ifdef XGMAC_ENABLE_TX_DESC_DUMP
1578 xgbe_dump_tx_desc(ring, start_index, packet->rdesc_count, 1);
1579#endif
1580
1581 /* Make sure ownership is written to the descriptor */
ceb8f6be 1582 dma_wmb();
c5aa9e3b 1583
a83ef427 1584 ring->cur = cur_index + 1;
16958a2b
LT		 1585 if (!packet->skb->xmit_more ||
1586 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
1587 channel->queue_index)))
1588 xgbe_tx_start_xmit(channel, ring);
1589 else
1590 ring->tx.xmit_more = 1;
c5aa9e3b
LT		 1591
1592 DBGPR(" %s: descriptors %u to %u written\n",
1593 channel->name, start_index & (ring->rdesc_count - 1),
1594 (ring->cur - 1) & (ring->rdesc_count - 1));
1595
a9d41981 1596 DBGPR("<--xgbe_dev_xmit\n");
c5aa9e3b
LT		 1597}
1598
1599static int xgbe_dev_read(struct xgbe_channel *channel)
1600{
1601 struct xgbe_ring *ring = channel->rx_ring;
1602 struct xgbe_ring_data *rdata;
1603 struct xgbe_ring_desc *rdesc;
1604 struct xgbe_packet_data *packet = &ring->packet_data;
c52e9c63 1605 struct net_device *netdev = channel->pdata->netdev;
5b9dfe29 1606 unsigned int err, etlt, l34t;
c5aa9e3b
LT		 1607
1608 DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
1609
d0a8ba6c 1610 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
c5aa9e3b
LT		 1611 rdesc = rdata->rdesc;
1612
1613 /* Check for data availability */
1614 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
1615 return 1;
1616
5449e271 1617 /* Make sure descriptor fields are read after reading the OWN bit */
ceb8f6be 1618 dma_rmb();
5449e271 1619
c5aa9e3b
LT		 1620#ifdef XGMAC_ENABLE_RX_DESC_DUMP
1621 xgbe_dump_rx_desc(ring, rdesc, ring->cur);
1622#endif
1623
23e4eef7
LT		 1624 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
1625 /* Timestamp Context Descriptor */
1626 xgbe_get_rx_tstamp(packet, rdesc);
1627
1628 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1629 CONTEXT, 1);
1630 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1631 CONTEXT_NEXT, 0);
1632 return 0;
1633 }
1634
1635 /* Normal Descriptor, be sure Context Descriptor bit is off */
1636 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
1637
1638 /* Indicate if a Context Descriptor is next */
1639 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
1640 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1641 CONTEXT_NEXT, 1);
1642
174fd259
LT		 1643 /* Get the header length */
1644 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD))
c9f140eb
LT		 1645 rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
1646 RX_NORMAL_DESC2, HL);
174fd259 1647
5b9dfe29
LT		 1648 /* Get the RSS hash */
1649 if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
1650 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1651 RSS_HASH, 1);
1652
1653 packet->rss_hash = le32_to_cpu(rdesc->desc1);
1654
1655 l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
1656 switch (l34t) {
1657 case RX_DESC3_L34T_IPV4_TCP:
1658 case RX_DESC3_L34T_IPV4_UDP:
1659 case RX_DESC3_L34T_IPV6_TCP:
1660 case RX_DESC3_L34T_IPV6_UDP:
1661 packet->rss_hash_type = PKT_HASH_TYPE_L4;
b6267d3e 1662 break;
5b9dfe29
LT		 1663 default:
1664 packet->rss_hash_type = PKT_HASH_TYPE_L3;
1665 }
1666 }
1667
c5aa9e3b 1668 /* Get the packet length */
c9f140eb 1669 rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
c5aa9e3b
LT		 1670
1671 if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
1672 /* Not all the data has been transferred for this packet */
1673 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1674 INCOMPLETE, 1);
1675 return 0;
1676 }
1677
1678 /* This is the last of the data for this packet */
1679 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1680 INCOMPLETE, 0);
1681
1682 /* Set checksum done indicator as appropriate */
1683 if (channel->pdata->netdev->features & NETIF_F_RXCSUM)
1684 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1685 CSUM_DONE, 1);
1686
1687 /* Check for errors (only valid in last descriptor) */
1688 err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
1689 etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
1690 DBGPR(" err=%u, etlt=%#x\n", err, etlt);
1691
7bba35bd
LT		 1692 if (!err || !etlt) {
1693 /* No error if err is 0 or etlt is 0 */
c52e9c63
LT		 1694 if ((etlt == 0x09) &&
1695 (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
c5aa9e3b
LT		 1696 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1697 VLAN_CTAG, 1);
1698 packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
1699 RX_NORMAL_DESC0,
1700 OVT);
1701 DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag);
1702 }
1703 } else {
1704 if ((etlt == 0x05) || (etlt == 0x06))
1705 XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1706 CSUM_DONE, 0);
1707 else
1708 XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
1709 FRAME, 1);
1710 }
1711
1712 DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
1713 ring->cur & (ring->rdesc_count - 1), ring->cur);
1714
1715 return 0;
1716}
1717
1718static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
1719{
1720 /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
1721 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
1722}
1723
1724static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
1725{
1726 /* Rx and Tx share LD bit, so check TDES3.LD bit */
1727 return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
1728}
1729
9867e8fb
LT		 1730static int xgbe_enable_int(struct xgbe_channel *channel,
1731 enum xgbe_int int_id)
c5aa9e3b
LT		 1732{
1733 unsigned int dma_ch_ier;
1734
9867e8fb 1735 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
c5aa9e3b 1736
c5aa9e3b 1737 switch (int_id) {
c5aa9e3b 1738 case XGMAC_INT_DMA_CH_SR_TI:
9867e8fb 1739 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
c5aa9e3b
LT		 1740 break;
1741 case XGMAC_INT_DMA_CH_SR_TPS:
9867e8fb 1742 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
c5aa9e3b
LT		 1743 break;
1744 case XGMAC_INT_DMA_CH_SR_TBU:
9867e8fb 1745 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
c5aa9e3b
LT		 1746 break;
1747 case XGMAC_INT_DMA_CH_SR_RI:
9867e8fb 1748 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
c5aa9e3b
LT		 1749 break;
1750 case XGMAC_INT_DMA_CH_SR_RBU:
9867e8fb 1751 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
c5aa9e3b
LT		 1752 break;
1753 case XGMAC_INT_DMA_CH_SR_RPS:
9867e8fb
LT		 1754 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
1755 break;
1756 case XGMAC_INT_DMA_CH_SR_TI_RI:
1757 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
1758 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
c5aa9e3b
LT		 1759 break;
1760 case XGMAC_INT_DMA_CH_SR_FBE:
9867e8fb 1761 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
c5aa9e3b
LT		 1762 break;
1763 case XGMAC_INT_DMA_ALL:
9867e8fb 1764 dma_ch_ier |= channel->saved_ier;
c5aa9e3b
LT		 1765 break;
1766 default:
1767 return -1;
1768 }
1769
9867e8fb
LT		 1770 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1771
c5aa9e3b
LT		 1772 return 0;
1773}
1774
1775static int xgbe_disable_int(struct xgbe_channel *channel,
1776 enum xgbe_int int_id)
1777{
1778 unsigned int dma_ch_ier;
1779
9867e8fb
LT		 1780 dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
1781
c5aa9e3b 1782 switch (int_id) {
c5aa9e3b 1783 case XGMAC_INT_DMA_CH_SR_TI:
9867e8fb 1784 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
c5aa9e3b
LT		 1785 break;
1786 case XGMAC_INT_DMA_CH_SR_TPS:
9867e8fb 1787 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
c5aa9e3b
LT		 1788 break;
1789 case XGMAC_INT_DMA_CH_SR_TBU:
9867e8fb 1790 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
c5aa9e3b
LT		 1791 break;
1792 case XGMAC_INT_DMA_CH_SR_RI:
9867e8fb 1793 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
c5aa9e3b
LT		 1794 break;
1795 case XGMAC_INT_DMA_CH_SR_RBU:
9867e8fb 1796 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
c5aa9e3b
LT		 1797 break;
1798 case XGMAC_INT_DMA_CH_SR_RPS:
9867e8fb
LT		 1799 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
1800 break;
1801 case XGMAC_INT_DMA_CH_SR_TI_RI:
1802 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
1803 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
c5aa9e3b
LT		 1804 break;
1805 case XGMAC_INT_DMA_CH_SR_FBE:
9867e8fb 1806 XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
c5aa9e3b
LT		 1807 break;
1808 case XGMAC_INT_DMA_ALL:
9867e8fb 1809 channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
d0a8ba6c 1810 dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
c5aa9e3b
LT		 1811 break;
1812 default:
1813 return -1;
1814 }
1815
9867e8fb
LT		 1816 XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
1817
c5aa9e3b
LT		 1818 return 0;
1819}
1820
1821static int xgbe_exit(struct xgbe_prv_data *pdata)
1822{
1823 unsigned int count = 2000;
1824
1825 DBGPR("-->xgbe_exit\n");
1826
1827 /* Issue a software reset */
1828 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
1829 usleep_range(10, 15);
1830
1831 /* Poll Until Poll Condition */
1832 while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
1833 usleep_range(500, 600);
1834
1835 if (!count)
1836 return -EBUSY;
1837
1838 DBGPR("<--xgbe_exit\n");
1839
1840 return 0;
1841}
1842
1843static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
1844{
1845 unsigned int i, count;
1846
a9a4a2d9
LT		 1847 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
1848 return 0;
1849
853eb16b 1850 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 1851 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
1852
1853 /* Poll Until Poll Condition */
853eb16b 1854 for (i = 0; i < pdata->tx_q_count; i++) {
c5aa9e3b
LT		 1855 count = 2000;
1856 while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
1857 MTL_Q_TQOMR, FTQ))
1858 usleep_range(500, 600);
1859
1860 if (!count)
1861 return -EBUSY;
1862 }
1863
1864 return 0;
1865}
1866
1867static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
1868{
1869 /* Set enhanced addressing mode */
1870 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
1871
1872 /* Set the System Bus mode */
1873 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
9867e8fb 1874 XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
c5aa9e3b
LT		 1875}
1876
1877static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
1878{
1879 unsigned int arcache, awcache;
1880
1881 arcache = 0;
cfa50c78
LT		 1882 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
1883 XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
1884 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
1885 XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
1886 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
1887 XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
c5aa9e3b
LT		 1888 XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
1889
1890 awcache = 0;
cfa50c78
LT		 1891 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
1892 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
1893 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
1894 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
1895 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
1896 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
1897 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
1898 XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
c5aa9e3b
LT		 1899 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
1900}
1901
1902static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
1903{
1904 unsigned int i;
1905
fca2d994 1906 /* Set Tx to weighted round robin scheduling algorithm */
c5aa9e3b
LT		 1907 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
1908
fca2d994
LT		 1909 /* Set Tx traffic classes to use WRR algorithm with equal weights */
1910 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
1911 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
1912 MTL_TSA_ETS);
1913 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
1914 }
c5aa9e3b
LT		 1915
1916 /* Set Rx to strict priority algorithm */
1917 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
1918}
1919
f076f453
LT		 1920static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,
1921 unsigned int queue_count)
c5aa9e3b
LT		 1922{
1923 unsigned int q_fifo_size = 0;
1924 enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1925
1926 /* Calculate Tx/Rx fifo share per queue */
1927 switch (fifo_size) {
1928 case 0:
d0a8ba6c 1929 q_fifo_size = XGBE_FIFO_SIZE_B(128);
c5aa9e3b
LT		 1930 break;
1931 case 1:
d0a8ba6c 1932 q_fifo_size = XGBE_FIFO_SIZE_B(256);
c5aa9e3b
LT		 1933 break;
1934 case 2:
d0a8ba6c 1935 q_fifo_size = XGBE_FIFO_SIZE_B(512);
c5aa9e3b
LT		 1936 break;
1937 case 3:
d0a8ba6c 1938 q_fifo_size = XGBE_FIFO_SIZE_KB(1);
c5aa9e3b
LT		 1939 break;
1940 case 4:
d0a8ba6c 1941 q_fifo_size = XGBE_FIFO_SIZE_KB(2);
c5aa9e3b
LT		 1942 break;
1943 case 5:
d0a8ba6c 1944 q_fifo_size = XGBE_FIFO_SIZE_KB(4);
c5aa9e3b
LT		 1945 break;
1946 case 6:
d0a8ba6c 1947 q_fifo_size = XGBE_FIFO_SIZE_KB(8);
c5aa9e3b
LT		 1948 break;
1949 case 7:
d0a8ba6c 1950 q_fifo_size = XGBE_FIFO_SIZE_KB(16);
c5aa9e3b
LT		 1951 break;
1952 case 8:
d0a8ba6c 1953 q_fifo_size = XGBE_FIFO_SIZE_KB(32);
c5aa9e3b
LT		 1954 break;
1955 case 9:
d0a8ba6c 1956 q_fifo_size = XGBE_FIFO_SIZE_KB(64);
c5aa9e3b
LT		 1957 break;
1958 case 10:
d0a8ba6c 1959 q_fifo_size = XGBE_FIFO_SIZE_KB(128);
c5aa9e3b
LT		 1960 break;
1961 case 11:
d0a8ba6c 1962 q_fifo_size = XGBE_FIFO_SIZE_KB(256);
c5aa9e3b
LT		 1963 break;
1964 }
f076f453
LT		 1965
1966 /* The configured value is not the actual amount of fifo RAM */
1967 q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);
1968
c5aa9e3b
LT		 1969 q_fifo_size = q_fifo_size / queue_count;
1970
1971 /* Set the queue fifo size programmable value */
d0a8ba6c 1972 if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
c5aa9e3b 1973 p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
d0a8ba6c 1974 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
c5aa9e3b 1975 p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
d0a8ba6c 1976 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
c5aa9e3b 1977 p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
d0a8ba6c 1978 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
c5aa9e3b 1979 p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
d0a8ba6c 1980 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
c5aa9e3b 1981 p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
d0a8ba6c 1982 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
c5aa9e3b 1983 p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
d0a8ba6c 1984 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
c5aa9e3b 1985 p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
d0a8ba6c 1986 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
c5aa9e3b 1987 p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
d0a8ba6c 1988 else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
c5aa9e3b 1989 p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
d0a8ba6c 1990 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
c5aa9e3b 1991 p_fifo = XGMAC_MTL_FIFO_SIZE_512;
d0a8ba6c 1992 else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
c5aa9e3b
LT		 1993 p_fifo = XGMAC_MTL_FIFO_SIZE_256;
1994
1995 return p_fifo;
1996}
1997
1998static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
1999{
2000 enum xgbe_mtl_fifo_size fifo_size;
2001 unsigned int i;
2002
2003 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
853eb16b 2004 pdata->tx_q_count);
c5aa9e3b 2005
853eb16b 2006 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 2007 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
2008
600c8811
LT		 2009 netdev_notice(pdata->netdev,
2010 "%d Tx hardware queues, %d byte fifo per queue\n",
853eb16b 2011 pdata->tx_q_count, ((fifo_size + 1) * 256));
c5aa9e3b
LT		 2012}
2013
2014static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
2015{
2016 enum xgbe_mtl_fifo_size fifo_size;
2017 unsigned int i;
2018
2019 fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
853eb16b 2020 pdata->rx_q_count);
c5aa9e3b 2021
853eb16b 2022 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 2023 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
2024
600c8811
LT		 2025 netdev_notice(pdata->netdev,
2026 "%d Rx hardware queues, %d byte fifo per queue\n",
853eb16b 2027 pdata->rx_q_count, ((fifo_size + 1) * 256));
c5aa9e3b
LT		 2028}
2029
fca2d994 2030static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
c5aa9e3b 2031{
fca2d994
LT		 2032 unsigned int qptc, qptc_extra, queue;
2033 unsigned int prio_queues;
2034 unsigned int ppq, ppq_extra, prio;
2035 unsigned int mask;
2036 unsigned int i, j, reg, reg_val;
2037
2038 /* Map the MTL Tx Queues to Traffic Classes
2039 * Note: Tx Queues >= Traffic Classes
2040 */
2041 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
2042 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
2043
2044 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
2045 for (j = 0; j < qptc; j++) {
2046 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
2047 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2048 Q2TCMAP, i);
2049 pdata->q2tc_map[queue++] = i;
2050 }
2051
2052 if (i < qptc_extra) {
2053 DBGPR(" TXq%u mapped to TC%u\n", queue, i);
2054 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
2055 Q2TCMAP, i);
2056 pdata->q2tc_map[queue++] = i;
2057 }
2058 }
2059
2060 /* Map the 8 VLAN priority values to available MTL Rx queues */
2061 prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
2062 pdata->rx_q_count);
2063 ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
2064 ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
2065
2066 reg = MAC_RQC2R;
2067 reg_val = 0;
2068 for (i = 0, prio = 0; i < prio_queues;) {
2069 mask = 0;
2070 for (j = 0; j < ppq; j++) {
2071 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
2072 mask |= (1 << prio);
2073 pdata->prio2q_map[prio++] = i;
2074 }
2075
2076 if (i < ppq_extra) {
2077 DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
2078 mask |= (1 << prio);
2079 pdata->prio2q_map[prio++] = i;
2080 }
2081
2082 reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
2083
2084 if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
2085 continue;
2086
2087 XGMAC_IOWRITE(pdata, reg, reg_val);
2088 reg += MAC_RQC2_INC;
2089 reg_val = 0;
2090 }
c5aa9e3b
LT		 2091
2092 /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
2093 reg = MTL_RQDCM0R;
2094 reg_val = 0;
fca2d994 2095 for (i = 0; i < pdata->rx_q_count;) {
c5aa9e3b
LT		 2096 reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
2097
fca2d994 2098 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
c5aa9e3b
LT		 2099 continue;
2100
2101 XGMAC_IOWRITE(pdata, reg, reg_val);
2102
2103 reg += MTL_RQDCM_INC;
2104 reg_val = 0;
2105 }
2106}
2107
2108static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
2109{
2110 unsigned int i;
2111
853eb16b 2112 for (i = 0; i < pdata->rx_q_count; i++) {
c5aa9e3b 2113 /* Activate flow control when less than 4k left in fifo */
e2a2729a 2114 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, 2);
c5aa9e3b
LT		 2115
2116 /* De-activate flow control when more than 6k left in fifo */
e2a2729a 2117 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, 4);
c5aa9e3b
LT		 2118 }
2119}
2120
2121static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
2122{
2123 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
b85e4d89
LT		 2124
2125 /* Filtering is done using perfect filtering and hash filtering */
2126 if (pdata->hw_feat.hash_table_size) {
2127 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
2128 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
2129 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
2130 }
c5aa9e3b
LT		 2131}
2132
2133static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
2134{
2135 unsigned int val;
2136
2137 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
2138
2139 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
2140}
2141
916102c6
LT		 2142static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
2143{
2144 switch (pdata->phy_speed) {
2145 case SPEED_10000:
2146 xgbe_set_xgmii_speed(pdata);
2147 break;
2148
2149 case SPEED_2500:
2150 xgbe_set_gmii_2500_speed(pdata);
2151 break;
2152
2153 case SPEED_1000:
2154 xgbe_set_gmii_speed(pdata);
2155 break;
2156 }
2157}
2158
c5aa9e3b
LT		 2159static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
2160{
2161 if (pdata->netdev->features & NETIF_F_RXCSUM)
2162 xgbe_enable_rx_csum(pdata);
2163 else
2164 xgbe_disable_rx_csum(pdata);
2165}
2166
2167static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
2168{
6e5eed04
LT		 2169 /* Indicate that VLAN Tx CTAGs come from context descriptors */
2170 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
2171 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
2172
801c62d9
LT		 2173 /* Set the current VLAN Hash Table register value */
2174 xgbe_update_vlan_hash_table(pdata);
2175
2176 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
2177 xgbe_enable_rx_vlan_filtering(pdata);
2178 else
2179 xgbe_disable_rx_vlan_filtering(pdata);
2180
c5aa9e3b
LT		 2181 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2182 xgbe_enable_rx_vlan_stripping(pdata);
2183 else
2184 xgbe_disable_rx_vlan_stripping(pdata);
2185}
2186
60265108
LT		 2187static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
2188{
2189 bool read_hi;
2190 u64 val;
2191
2192 switch (reg_lo) {
2193 /* These registers are always 64 bit */
2194 case MMC_TXOCTETCOUNT_GB_LO:
2195 case MMC_TXOCTETCOUNT_G_LO:
2196 case MMC_RXOCTETCOUNT_GB_LO:
2197 case MMC_RXOCTETCOUNT_G_LO:
2198 read_hi = true;
2199 break;
2200
2201 default:
2202 read_hi = false;
2203 };
2204
2205 val = XGMAC_IOREAD(pdata, reg_lo);
2206
2207 if (read_hi)
2208 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
2209
2210 return val;
2211}
2212
c5aa9e3b
LT		 2213static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
2214{
2215 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2216 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
2217
2218 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
2219 stats->txoctetcount_gb +=
60265108 2220 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
c5aa9e3b
LT		 2221
2222 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
2223 stats->txframecount_gb +=
60265108 2224 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
c5aa9e3b
LT		 2225
2226 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
2227 stats->txbroadcastframes_g +=
60265108 2228 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
c5aa9e3b
LT		 2229
2230 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
2231 stats->txmulticastframes_g +=
60265108 2232 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
c5aa9e3b
LT		 2233
2234 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
2235 stats->tx64octets_gb +=
60265108 2236 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
c5aa9e3b
LT		 2237
2238 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
2239 stats->tx65to127octets_gb +=
60265108 2240 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
c5aa9e3b
LT		 2241
2242 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
2243 stats->tx128to255octets_gb +=
60265108 2244 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
c5aa9e3b
LT		 2245
2246 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
2247 stats->tx256to511octets_gb +=
60265108 2248 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
c5aa9e3b
LT		 2249
2250 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
2251 stats->tx512to1023octets_gb +=
60265108 2252 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
c5aa9e3b
LT		 2253
2254 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
2255 stats->tx1024tomaxoctets_gb +=
60265108 2256 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
c5aa9e3b
LT		 2257
2258 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
2259 stats->txunicastframes_gb +=
60265108 2260 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
c5aa9e3b
LT		 2261
2262 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
2263 stats->txmulticastframes_gb +=
60265108 2264 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
c5aa9e3b
LT		 2265
2266 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
2267 stats->txbroadcastframes_g +=
60265108 2268 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
c5aa9e3b
LT		 2269
2270 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
2271 stats->txunderflowerror +=
60265108 2272 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
c5aa9e3b
LT		 2273
2274 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
2275 stats->txoctetcount_g +=
60265108 2276 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
c5aa9e3b
LT		 2277
2278 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
2279 stats->txframecount_g +=
60265108 2280 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
c5aa9e3b
LT		 2281
2282 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
2283 stats->txpauseframes +=
60265108 2284 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
c5aa9e3b
LT		 2285
2286 if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
2287 stats->txvlanframes_g +=
60265108 2288 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
c5aa9e3b
LT		 2289}
2290
2291static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
2292{
2293 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2294 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
2295
2296 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
2297 stats->rxframecount_gb +=
60265108 2298 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
c5aa9e3b
LT		 2299
2300 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
2301 stats->rxoctetcount_gb +=
60265108 2302 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
c5aa9e3b
LT		 2303
2304 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
2305 stats->rxoctetcount_g +=
60265108 2306 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
c5aa9e3b
LT		 2307
2308 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
2309 stats->rxbroadcastframes_g +=
60265108 2310 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
c5aa9e3b
LT		 2311
2312 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
2313 stats->rxmulticastframes_g +=
60265108 2314 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
c5aa9e3b
LT		 2315
2316 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
2317 stats->rxcrcerror +=
60265108 2318 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
c5aa9e3b
LT		 2319
2320 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
2321 stats->rxrunterror +=
60265108 2322 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
c5aa9e3b
LT		 2323
2324 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
2325 stats->rxjabbererror +=
60265108 2326 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
c5aa9e3b
LT		 2327
2328 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
2329 stats->rxundersize_g +=
60265108 2330 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
c5aa9e3b
LT		 2331
2332 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
2333 stats->rxoversize_g +=
60265108 2334 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
c5aa9e3b
LT		 2335
2336 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
2337 stats->rx64octets_gb +=
60265108 2338 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
c5aa9e3b
LT		 2339
2340 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
2341 stats->rx65to127octets_gb +=
60265108 2342 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
c5aa9e3b
LT		 2343
2344 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
2345 stats->rx128to255octets_gb +=
60265108 2346 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
c5aa9e3b
LT		 2347
2348 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
2349 stats->rx256to511octets_gb +=
60265108 2350 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
c5aa9e3b
LT		 2351
2352 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
2353 stats->rx512to1023octets_gb +=
60265108 2354 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
c5aa9e3b
LT		 2355
2356 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
2357 stats->rx1024tomaxoctets_gb +=
60265108 2358 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
c5aa9e3b
LT		 2359
2360 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
2361 stats->rxunicastframes_g +=
60265108 2362 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
c5aa9e3b
LT		 2363
2364 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
2365 stats->rxlengtherror +=
60265108 2366 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
c5aa9e3b
LT		 2367
2368 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
2369 stats->rxoutofrangetype +=
60265108 2370 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
c5aa9e3b
LT		 2371
2372 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
2373 stats->rxpauseframes +=
60265108 2374 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
c5aa9e3b
LT		 2375
2376 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
2377 stats->rxfifooverflow +=
60265108 2378 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
c5aa9e3b
LT		 2379
2380 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
2381 stats->rxvlanframes_gb +=
60265108 2382 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
c5aa9e3b
LT		 2383
2384 if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
2385 stats->rxwatchdogerror +=
60265108 2386 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
c5aa9e3b
LT		 2387}
2388
2389static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
2390{
2391 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
2392
2393 /* Freeze counters */
2394 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
2395
2396 stats->txoctetcount_gb +=
60265108 2397 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
c5aa9e3b
LT		 2398
2399 stats->txframecount_gb +=
60265108 2400 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
c5aa9e3b
LT		 2401
2402 stats->txbroadcastframes_g +=
60265108 2403 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
c5aa9e3b
LT		 2404
2405 stats->txmulticastframes_g +=
60265108 2406 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
c5aa9e3b
LT		 2407
2408 stats->tx64octets_gb +=
60265108 2409 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
c5aa9e3b
LT		 2410
2411 stats->tx65to127octets_gb +=
60265108 2412 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
c5aa9e3b
LT		 2413
2414 stats->tx128to255octets_gb +=
60265108 2415 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
c5aa9e3b
LT		 2416
2417 stats->tx256to511octets_gb +=
60265108 2418 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
c5aa9e3b
LT		 2419
2420 stats->tx512to1023octets_gb +=
60265108 2421 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
c5aa9e3b
LT		 2422
2423 stats->tx1024tomaxoctets_gb +=
60265108 2424 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
c5aa9e3b
LT		 2425
2426 stats->txunicastframes_gb +=
60265108 2427 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
c5aa9e3b
LT		 2428
2429 stats->txmulticastframes_gb +=
60265108 2430 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
c5aa9e3b
LT		 2431
2432 stats->txbroadcastframes_g +=
60265108 2433 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
c5aa9e3b
LT		 2434
2435 stats->txunderflowerror +=
60265108 2436 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
c5aa9e3b
LT		 2437
2438 stats->txoctetcount_g +=
60265108 2439 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
c5aa9e3b
LT		 2440
2441 stats->txframecount_g +=
60265108 2442 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
c5aa9e3b
LT		 2443
2444 stats->txpauseframes +=
60265108 2445 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
c5aa9e3b
LT		 2446
2447 stats->txvlanframes_g +=
60265108 2448 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
c5aa9e3b
LT		 2449
2450 stats->rxframecount_gb +=
60265108 2451 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
c5aa9e3b
LT		 2452
2453 stats->rxoctetcount_gb +=
60265108 2454 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
c5aa9e3b
LT		 2455
2456 stats->rxoctetcount_g +=
60265108 2457 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
c5aa9e3b
LT		 2458
2459 stats->rxbroadcastframes_g +=
60265108 2460 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
c5aa9e3b
LT		 2461
2462 stats->rxmulticastframes_g +=
60265108 2463 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
c5aa9e3b
LT		 2464
2465 stats->rxcrcerror +=
60265108 2466 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
c5aa9e3b
LT		 2467
2468 stats->rxrunterror +=
60265108 2469 xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
c5aa9e3b
LT		 2470
2471 stats->rxjabbererror +=
60265108 2472 xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
c5aa9e3b
LT		 2473
2474 stats->rxundersize_g +=
60265108 2475 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
c5aa9e3b
LT		 2476
2477 stats->rxoversize_g +=
60265108 2478 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
c5aa9e3b
LT		 2479
2480 stats->rx64octets_gb +=
60265108 2481 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
c5aa9e3b
LT		 2482
2483 stats->rx65to127octets_gb +=
60265108 2484 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
c5aa9e3b
LT		 2485
2486 stats->rx128to255octets_gb +=
60265108 2487 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
c5aa9e3b
LT		 2488
2489 stats->rx256to511octets_gb +=
60265108 2490 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
c5aa9e3b
LT		 2491
2492 stats->rx512to1023octets_gb +=
60265108 2493 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
c5aa9e3b
LT		 2494
2495 stats->rx1024tomaxoctets_gb +=
60265108 2496 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
c5aa9e3b
LT		 2497
2498 stats->rxunicastframes_g +=
60265108 2499 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
c5aa9e3b
LT		 2500
2501 stats->rxlengtherror +=
60265108 2502 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
c5aa9e3b
LT		 2503
2504 stats->rxoutofrangetype +=
60265108 2505 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
c5aa9e3b
LT		 2506
2507 stats->rxpauseframes +=
60265108 2508 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
c5aa9e3b
LT		 2509
2510 stats->rxfifooverflow +=
60265108 2511 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
c5aa9e3b
LT		 2512
2513 stats->rxvlanframes_gb +=
60265108 2514 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
c5aa9e3b
LT		 2515
2516 stats->rxwatchdogerror +=
60265108 2517 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
c5aa9e3b
LT		 2518
2519 /* Un-freeze counters */
2520 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
2521}
2522
2523static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
2524{
2525 /* Set counters to reset on read */
2526 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
2527
2528 /* Reset the counters */
2529 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
2530}
2531
16edd34e
LT		 2532static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
2533 struct xgbe_channel *channel)
2534{
2535 unsigned int tx_dsr, tx_pos, tx_qidx;
2536 unsigned int tx_status;
2537 unsigned long tx_timeout;
2538
2539 /* Calculate the status register to read and the position within */
2540 if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
2541 tx_dsr = DMA_DSR0;
2542 tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) +
2543 DMA_DSR0_TPS_START;
2544 } else {
2545 tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
2546
2547 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
2548 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
2549 DMA_DSRX_TPS_START;
2550 }
2551
2552 /* The Tx engine cannot be stopped if it is actively processing
2553 * descriptors. Wait for the Tx engine to enter the stopped or
2554 * suspended state. Don't wait forever though...
2555 */
2556 tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
2557 while (time_before(jiffies, tx_timeout)) {
2558 tx_status = XGMAC_IOREAD(pdata, tx_dsr);
2559 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
2560 if ((tx_status == DMA_TPS_STOPPED) ||
2561 (tx_status == DMA_TPS_SUSPENDED))
2562 break;
2563
2564 usleep_range(500, 1000);
2565 }
2566
2567 if (!time_before(jiffies, tx_timeout))
2568 netdev_info(pdata->netdev,
2569 "timed out waiting for Tx DMA channel %u to stop\n",
2570 channel->queue_index);
2571}
2572
c5aa9e3b
LT		 2573static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
2574{
2575 struct xgbe_channel *channel;
2576 unsigned int i;
2577
2578 /* Enable each Tx DMA channel */
2579 channel = pdata->channel;
2580 for (i = 0; i < pdata->channel_count; i++, channel++) {
2581 if (!channel->tx_ring)
2582 break;
2583
2584 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2585 }
2586
2587 /* Enable each Tx queue */
853eb16b 2588 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 2589 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
2590 MTL_Q_ENABLED);
2591
2592 /* Enable MAC Tx */
2593 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2594}
2595
2596static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
2597{
2598 struct xgbe_channel *channel;
2599 unsigned int i;
2600
16edd34e
LT		 2601 /* Prepare for Tx DMA channel stop */
2602 channel = pdata->channel;
2603 for (i = 0; i < pdata->channel_count; i++, channel++) {
2604 if (!channel->tx_ring)
2605 break;
2606
2607 xgbe_prepare_tx_stop(pdata, channel);
2608 }
2609
c5aa9e3b
LT		 2610 /* Disable MAC Tx */
2611 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2612
2613 /* Disable each Tx queue */
853eb16b 2614 for (i = 0; i < pdata->tx_q_count; i++)
c5aa9e3b
LT		 2615 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
2616
2617 /* Disable each Tx DMA channel */
2618 channel = pdata->channel;
2619 for (i = 0; i < pdata->channel_count; i++, channel++) {
2620 if (!channel->tx_ring)
2621 break;
2622
2623 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2624 }
2625}
2626
2627static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
2628{
2629 struct xgbe_channel *channel;
2630 unsigned int reg_val, i;
2631
2632 /* Enable each Rx DMA channel */
2633 channel = pdata->channel;
2634 for (i = 0; i < pdata->channel_count; i++, channel++) {
2635 if (!channel->rx_ring)
2636 break;
2637
2638 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2639 }
2640
2641 /* Enable each Rx queue */
2642 reg_val = 0;
853eb16b 2643 for (i = 0; i < pdata->rx_q_count; i++)
c5aa9e3b
LT		 2644 reg_val |= (0x02 << (i << 1));
2645 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
2646
2647 /* Enable MAC Rx */
2648 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
2649 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
2650 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
2651 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
2652}
2653
2654static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
2655{
2656 struct xgbe_channel *channel;
2657 unsigned int i;
2658
2659 /* Disable MAC Rx */
2660 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
2661 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
2662 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
2663 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
2664
2665 /* Disable each Rx queue */
2666 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
2667
2668 /* Disable each Rx DMA channel */
2669 channel = pdata->channel;
2670 for (i = 0; i < pdata->channel_count; i++, channel++) {
2671 if (!channel->rx_ring)
2672 break;
2673
2674 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2675 }
2676}
2677
2678static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
2679{
2680 struct xgbe_channel *channel;
2681 unsigned int i;
2682
2683 /* Enable each Tx DMA channel */
2684 channel = pdata->channel;
2685 for (i = 0; i < pdata->channel_count; i++, channel++) {
2686 if (!channel->tx_ring)
2687 break;
2688
2689 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
2690 }
2691
2692 /* Enable MAC Tx */
2693 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
2694}
2695
2696static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
2697{
2698 struct xgbe_channel *channel;
2699 unsigned int i;
2700
16edd34e
LT		 2701 /* Prepare for Tx DMA channel stop */
2702 channel = pdata->channel;
2703 for (i = 0; i < pdata->channel_count; i++, channel++) {
2704 if (!channel->tx_ring)
2705 break;
2706
2707 xgbe_prepare_tx_stop(pdata, channel);
2708 }
2709
c5aa9e3b
LT		 2710 /* Disable MAC Tx */
2711 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
2712
2713 /* Disable each Tx DMA channel */
2714 channel = pdata->channel;
2715 for (i = 0; i < pdata->channel_count; i++, channel++) {
2716 if (!channel->tx_ring)
2717 break;
2718
2719 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
2720 }
2721}
2722
2723static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
2724{
2725 struct xgbe_channel *channel;
2726 unsigned int i;
2727
2728 /* Enable each Rx DMA channel */
2729 channel = pdata->channel;
2730 for (i = 0; i < pdata->channel_count; i++, channel++) {
2731 if (!channel->rx_ring)
2732 break;
2733
2734 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
2735 }
2736}
2737
2738static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
2739{
2740 struct xgbe_channel *channel;
2741 unsigned int i;
2742
2743 /* Disable each Rx DMA channel */
2744 channel = pdata->channel;
2745 for (i = 0; i < pdata->channel_count; i++, channel++) {
2746 if (!channel->rx_ring)
2747 break;
2748
2749 XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
2750 }
2751}
2752
2753static int xgbe_init(struct xgbe_prv_data *pdata)
2754{
2755 struct xgbe_desc_if *desc_if = &pdata->desc_if;
2756 int ret;
2757
2758 DBGPR("-->xgbe_init\n");
2759
2760 /* Flush Tx queues */
2761 ret = xgbe_flush_tx_queues(pdata);
2762 if (ret)
2763 return ret;
2764
2765 /*
2766 * Initialize DMA related features
2767 */
2768 xgbe_config_dma_bus(pdata);
2769 xgbe_config_dma_cache(pdata);
2770 xgbe_config_osp_mode(pdata);
2771 xgbe_config_pblx8(pdata);
2772 xgbe_config_tx_pbl_val(pdata);
2773 xgbe_config_rx_pbl_val(pdata);
2774 xgbe_config_rx_coalesce(pdata);
2775 xgbe_config_tx_coalesce(pdata);
2776 xgbe_config_rx_buffer_size(pdata);
2777 xgbe_config_tso_mode(pdata);
174fd259 2778 xgbe_config_sph_mode(pdata);
5b9dfe29 2779 xgbe_config_rss(pdata);
c5aa9e3b
LT		 2780 desc_if->wrapper_tx_desc_init(pdata);
2781 desc_if->wrapper_rx_desc_init(pdata);
2782 xgbe_enable_dma_interrupts(pdata);
2783
2784 /*
2785 * Initialize MTL related features
2786 */
2787 xgbe_config_mtl_mode(pdata);
fca2d994 2788 xgbe_config_queue_mapping(pdata);
c5aa9e3b
LT		 2789 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
2790 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
2791 xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
2792 xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
2793 xgbe_config_tx_fifo_size(pdata);
2794 xgbe_config_rx_fifo_size(pdata);
2795 xgbe_config_flow_control_threshold(pdata);
c5aa9e3b
LT		 2796 /*TODO: Error Packet and undersized good Packet forwarding enable
2797 (FEP and FUP)
2798 */
fca2d994
LT		 2799 xgbe_config_dcb_tc(pdata);
2800 xgbe_config_dcb_pfc(pdata);
c5aa9e3b
LT		 2801 xgbe_enable_mtl_interrupts(pdata);
2802
c5aa9e3b
LT		 2803 /*
2804 * Initialize MAC related features
2805 */
2806 xgbe_config_mac_address(pdata);
2807 xgbe_config_jumbo_enable(pdata);
2808 xgbe_config_flow_control(pdata);
916102c6 2809 xgbe_config_mac_speed(pdata);
c5aa9e3b
LT		 2810 xgbe_config_checksum_offload(pdata);
2811 xgbe_config_vlan_support(pdata);
2812 xgbe_config_mmc(pdata);
2813 xgbe_enable_mac_interrupts(pdata);
2814
2815 DBGPR("<--xgbe_init\n");
2816
2817 return 0;
2818}
2819
2820void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
2821{
2822 DBGPR("-->xgbe_init_function_ptrs\n");
2823
2824 hw_if->tx_complete = xgbe_tx_complete;
2825
2826 hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode;
2827 hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode;
b85e4d89 2828 hw_if->add_mac_addresses = xgbe_add_mac_addresses;
c5aa9e3b
LT		 2829 hw_if->set_mac_address = xgbe_set_mac_address;
2830
2831 hw_if->enable_rx_csum = xgbe_enable_rx_csum;
2832 hw_if->disable_rx_csum = xgbe_disable_rx_csum;
2833
2834 hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
2835 hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
801c62d9
LT		 2836 hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
2837 hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
2838 hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
c5aa9e3b
LT		 2839
2840 hw_if->read_mmd_regs = xgbe_read_mmd_regs;
2841 hw_if->write_mmd_regs = xgbe_write_mmd_regs;
2842
2843 hw_if->set_gmii_speed = xgbe_set_gmii_speed;
2844 hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
2845 hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
2846
2847 hw_if->enable_tx = xgbe_enable_tx;
2848 hw_if->disable_tx = xgbe_disable_tx;
2849 hw_if->enable_rx = xgbe_enable_rx;
2850 hw_if->disable_rx = xgbe_disable_rx;
2851
2852 hw_if->powerup_tx = xgbe_powerup_tx;
2853 hw_if->powerdown_tx = xgbe_powerdown_tx;
2854 hw_if->powerup_rx = xgbe_powerup_rx;
2855 hw_if->powerdown_rx = xgbe_powerdown_rx;
2856
a9d41981 2857 hw_if->dev_xmit = xgbe_dev_xmit;
c5aa9e3b
LT		 2858 hw_if->dev_read = xgbe_dev_read;
2859 hw_if->enable_int = xgbe_enable_int;
2860 hw_if->disable_int = xgbe_disable_int;
2861 hw_if->init = xgbe_init;
2862 hw_if->exit = xgbe_exit;
2863
2864 /* Descriptor related Sequences have to be initialized here */
2865 hw_if->tx_desc_init = xgbe_tx_desc_init;
2866 hw_if->rx_desc_init = xgbe_rx_desc_init;
2867 hw_if->tx_desc_reset = xgbe_tx_desc_reset;
2868 hw_if->rx_desc_reset = xgbe_rx_desc_reset;
2869 hw_if->is_last_desc = xgbe_is_last_desc;
2870 hw_if->is_context_desc = xgbe_is_context_desc;
16958a2b 2871 hw_if->tx_start_xmit = xgbe_tx_start_xmit;
c5aa9e3b
LT		 2872
2873 /* For FLOW ctrl */
2874 hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
2875 hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
2876
2877 /* For RX coalescing */
2878 hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
2879 hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
2880 hw_if->usec_to_riwt = xgbe_usec_to_riwt;
2881 hw_if->riwt_to_usec = xgbe_riwt_to_usec;
2882
2883 /* For RX and TX threshold config */
2884 hw_if->config_rx_threshold = xgbe_config_rx_threshold;
2885 hw_if->config_tx_threshold = xgbe_config_tx_threshold;
2886
2887 /* For RX and TX Store and Forward Mode config */
2888 hw_if->config_rsf_mode = xgbe_config_rsf_mode;
2889 hw_if->config_tsf_mode = xgbe_config_tsf_mode;
2890
2891 /* For TX DMA Operating on Second Frame config */
2892 hw_if->config_osp_mode = xgbe_config_osp_mode;
2893
2894 /* For RX and TX PBL config */
2895 hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
2896 hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
2897 hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
2898 hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
2899 hw_if->config_pblx8 = xgbe_config_pblx8;
2900
2901 /* For MMC statistics support */
2902 hw_if->tx_mmc_int = xgbe_tx_mmc_int;
2903 hw_if->rx_mmc_int = xgbe_rx_mmc_int;
2904 hw_if->read_mmc_stats = xgbe_read_mmc_stats;
2905
23e4eef7
LT		 2906 /* For PTP config */
2907 hw_if->config_tstamp = xgbe_config_tstamp;
2908 hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
2909 hw_if->set_tstamp_time = xgbe_set_tstamp_time;
2910 hw_if->get_tstamp_time = xgbe_get_tstamp_time;
2911 hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
2912
fca2d994
LT		 2913 /* For Data Center Bridging config */
2914 hw_if->config_dcb_tc = xgbe_config_dcb_tc;
2915 hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
2916
5b9dfe29
LT		 2917 /* For Receive Side Scaling */
2918 hw_if->enable_rss = xgbe_enable_rss;
2919 hw_if->disable_rss = xgbe_disable_rss;
f6ac8628
LT		 2920 hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
2921 hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
5b9dfe29 2922
c5aa9e3b
LT		 2923 DBGPR("<--xgbe_init_function_ptrs\n");
2924}
Linux kernel - Deliverables
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