Commit | Line | Data |
---|---|---|
c5aa9e3b LT |
1 | /* |
2 | * AMD 10Gb Ethernet driver | |
3 | * | |
4 | * This file is available to you under your choice of the following two | |
5 | * licenses: | |
6 | * | |
7 | * License 1: GPLv2 | |
8 | * | |
9 | * Copyright (c) 2014 Advanced Micro Devices, Inc. | |
10 | * | |
11 | * This file is free software; you may copy, redistribute and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation, either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * This file incorporates work covered by the following copyright and | |
25 | * permission notice: | |
26 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
27 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
28 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
29 | * and you. | |
30 | * | |
31 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
32 | * under any End User Software License Agreement or Agreement for Licensed | |
33 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
34 | * granted, free of charge, to any person obtaining a copy of this software | |
35 | * annotated with this license and the Software, to deal in the Software | |
36 | * without restriction, including without limitation the rights to use, | |
37 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
38 | * of the Software, and to permit persons to whom the Software is furnished | |
39 | * to do so, subject to the following conditions: | |
40 | * | |
41 | * The above copyright notice and this permission notice shall be included | |
42 | * in all copies or substantial portions of the Software. | |
43 | * | |
44 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
45 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
46 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
47 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
48 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
49 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
50 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
51 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
52 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
53 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
54 | * THE POSSIBILITY OF SUCH DAMAGE. | |
55 | * | |
56 | * | |
57 | * License 2: Modified BSD | |
58 | * | |
59 | * Copyright (c) 2014 Advanced Micro Devices, Inc. | |
60 | * All rights reserved. | |
61 | * | |
62 | * Redistribution and use in source and binary forms, with or without | |
63 | * modification, are permitted provided that the following conditions are met: | |
64 | * * Redistributions of source code must retain the above copyright | |
65 | * notice, this list of conditions and the following disclaimer. | |
66 | * * Redistributions in binary form must reproduce the above copyright | |
67 | * notice, this list of conditions and the following disclaimer in the | |
68 | * documentation and/or other materials provided with the distribution. | |
69 | * * Neither the name of Advanced Micro Devices, Inc. nor the | |
70 | * names of its contributors may be used to endorse or promote products | |
71 | * derived from this software without specific prior written permission. | |
72 | * | |
73 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
74 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
75 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
76 | * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY | |
77 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
78 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
79 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
80 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
81 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
82 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
83 | * | |
84 | * This file incorporates work covered by the following copyright and | |
85 | * permission notice: | |
86 | * The Synopsys DWC ETHER XGMAC Software Driver and documentation | |
87 | * (hereinafter "Software") is an unsupported proprietary work of Synopsys, | |
88 | * Inc. unless otherwise expressly agreed to in writing between Synopsys | |
89 | * and you. | |
90 | * | |
91 | * The Software IS NOT an item of Licensed Software or Licensed Product | |
92 | * under any End User Software License Agreement or Agreement for Licensed | |
93 | * Product with Synopsys or any supplement thereto. Permission is hereby | |
94 | * granted, free of charge, to any person obtaining a copy of this software | |
95 | * annotated with this license and the Software, to deal in the Software | |
96 | * without restriction, including without limitation the rights to use, | |
97 | * copy, modify, merge, publish, distribute, sublicense, and/or sell copies | |
98 | * of the Software, and to permit persons to whom the Software is furnished | |
99 | * to do so, subject to the following conditions: | |
100 | * | |
101 | * The above copyright notice and this permission notice shall be included | |
102 | * in all copies or substantial portions of the Software. | |
103 | * | |
104 | * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" | |
105 | * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED | |
106 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A | |
107 | * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS | |
108 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | |
109 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
110 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
111 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | |
112 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
113 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
114 | * THE POSSIBILITY OF SUCH DAMAGE. | |
115 | */ | |
116 | ||
9227dc5e | 117 | #include <linux/platform_device.h> |
c5aa9e3b LT |
118 | #include <linux/spinlock.h> |
119 | #include <linux/tcp.h> | |
120 | #include <linux/if_vlan.h> | |
c5aa9e3b LT |
121 | #include <net/busy_poll.h> |
122 | #include <linux/clk.h> | |
123 | #include <linux/if_ether.h> | |
23e4eef7 | 124 | #include <linux/net_tstamp.h> |
88131a81 | 125 | #include <linux/phy.h> |
c5aa9e3b LT |
126 | |
127 | #include "xgbe.h" | |
128 | #include "xgbe-common.h" | |
129 | ||
9227dc5e LT |
130 | static int xgbe_one_poll(struct napi_struct *, int); |
131 | static int xgbe_all_poll(struct napi_struct *, int); | |
c5aa9e3b | 132 | |
4780b7ca LT |
133 | static int xgbe_alloc_channels(struct xgbe_prv_data *pdata) |
134 | { | |
135 | struct xgbe_channel *channel_mem, *channel; | |
136 | struct xgbe_ring *tx_ring, *rx_ring; | |
137 | unsigned int count, i; | |
9227dc5e | 138 | int ret = -ENOMEM; |
4780b7ca LT |
139 | |
140 | count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); | |
141 | ||
142 | channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL); | |
143 | if (!channel_mem) | |
144 | goto err_channel; | |
145 | ||
146 | tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring), | |
147 | GFP_KERNEL); | |
148 | if (!tx_ring) | |
149 | goto err_tx_ring; | |
150 | ||
151 | rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring), | |
152 | GFP_KERNEL); | |
153 | if (!rx_ring) | |
154 | goto err_rx_ring; | |
155 | ||
156 | for (i = 0, channel = channel_mem; i < count; i++, channel++) { | |
157 | snprintf(channel->name, sizeof(channel->name), "channel-%d", i); | |
158 | channel->pdata = pdata; | |
159 | channel->queue_index = i; | |
160 | channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE + | |
161 | (DMA_CH_INC * i); | |
162 | ||
9227dc5e LT |
163 | if (pdata->per_channel_irq) { |
164 | /* Get the DMA interrupt (offset 1) */ | |
165 | ret = platform_get_irq(pdata->pdev, i + 1); | |
166 | if (ret < 0) { | |
167 | netdev_err(pdata->netdev, | |
168 | "platform_get_irq %u failed\n", | |
169 | i + 1); | |
170 | goto err_irq; | |
171 | } | |
172 | ||
173 | channel->dma_irq = ret; | |
174 | } | |
175 | ||
4780b7ca LT |
176 | if (i < pdata->tx_ring_count) { |
177 | spin_lock_init(&tx_ring->lock); | |
178 | channel->tx_ring = tx_ring++; | |
179 | } | |
180 | ||
181 | if (i < pdata->rx_ring_count) { | |
182 | spin_lock_init(&rx_ring->lock); | |
183 | channel->rx_ring = rx_ring++; | |
184 | } | |
185 | ||
34bf65df LT |
186 | netif_dbg(pdata, drv, pdata->netdev, |
187 | "%s: dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n", | |
188 | channel->name, channel->dma_regs, channel->dma_irq, | |
189 | channel->tx_ring, channel->rx_ring); | |
4780b7ca LT |
190 | } |
191 | ||
192 | pdata->channel = channel_mem; | |
193 | pdata->channel_count = count; | |
194 | ||
195 | return 0; | |
196 | ||
9227dc5e LT |
197 | err_irq: |
198 | kfree(rx_ring); | |
199 | ||
4780b7ca LT |
200 | err_rx_ring: |
201 | kfree(tx_ring); | |
202 | ||
203 | err_tx_ring: | |
204 | kfree(channel_mem); | |
205 | ||
206 | err_channel: | |
9227dc5e | 207 | return ret; |
4780b7ca LT |
208 | } |
209 | ||
210 | static void xgbe_free_channels(struct xgbe_prv_data *pdata) | |
211 | { | |
212 | if (!pdata->channel) | |
213 | return; | |
214 | ||
215 | kfree(pdata->channel->rx_ring); | |
216 | kfree(pdata->channel->tx_ring); | |
217 | kfree(pdata->channel); | |
218 | ||
219 | pdata->channel = NULL; | |
220 | pdata->channel_count = 0; | |
221 | } | |
222 | ||
c5aa9e3b LT |
223 | static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring) |
224 | { | |
225 | return (ring->rdesc_count - (ring->cur - ring->dirty)); | |
226 | } | |
227 | ||
270894e7 LT |
228 | static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring) |
229 | { | |
230 | return (ring->cur - ring->dirty); | |
231 | } | |
232 | ||
16958a2b LT |
233 | static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel, |
234 | struct xgbe_ring *ring, unsigned int count) | |
235 | { | |
236 | struct xgbe_prv_data *pdata = channel->pdata; | |
237 | ||
238 | if (count > xgbe_tx_avail_desc(ring)) { | |
34bf65df LT |
239 | netif_info(pdata, drv, pdata->netdev, |
240 | "Tx queue stopped, not enough descriptors available\n"); | |
16958a2b LT |
241 | netif_stop_subqueue(pdata->netdev, channel->queue_index); |
242 | ring->tx.queue_stopped = 1; | |
243 | ||
244 | /* If we haven't notified the hardware because of xmit_more | |
245 | * support, tell it now | |
246 | */ | |
247 | if (ring->tx.xmit_more) | |
248 | pdata->hw_if.tx_start_xmit(channel, ring); | |
249 | ||
250 | return NETDEV_TX_BUSY; | |
251 | } | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
c5aa9e3b LT |
256 | static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu) |
257 | { | |
258 | unsigned int rx_buf_size; | |
259 | ||
260 | if (mtu > XGMAC_JUMBO_PACKET_MTU) { | |
261 | netdev_alert(netdev, "MTU exceeds maximum supported value\n"); | |
262 | return -EINVAL; | |
263 | } | |
264 | ||
265 | rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
08dcc47c LT |
266 | rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE); |
267 | ||
d0a8ba6c LT |
268 | rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & |
269 | ~(XGBE_RX_BUF_ALIGN - 1); | |
c5aa9e3b LT |
270 | |
271 | return rx_buf_size; | |
272 | } | |
273 | ||
274 | static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata) | |
275 | { | |
276 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
277 | struct xgbe_channel *channel; | |
9867e8fb | 278 | enum xgbe_int int_id; |
c5aa9e3b LT |
279 | unsigned int i; |
280 | ||
281 | channel = pdata->channel; | |
282 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
9867e8fb LT |
283 | if (channel->tx_ring && channel->rx_ring) |
284 | int_id = XGMAC_INT_DMA_CH_SR_TI_RI; | |
285 | else if (channel->tx_ring) | |
286 | int_id = XGMAC_INT_DMA_CH_SR_TI; | |
287 | else if (channel->rx_ring) | |
288 | int_id = XGMAC_INT_DMA_CH_SR_RI; | |
289 | else | |
290 | continue; | |
291 | ||
292 | hw_if->enable_int(channel, int_id); | |
c5aa9e3b LT |
293 | } |
294 | } | |
295 | ||
296 | static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata) | |
297 | { | |
298 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
299 | struct xgbe_channel *channel; | |
9867e8fb | 300 | enum xgbe_int int_id; |
c5aa9e3b LT |
301 | unsigned int i; |
302 | ||
303 | channel = pdata->channel; | |
304 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
9867e8fb LT |
305 | if (channel->tx_ring && channel->rx_ring) |
306 | int_id = XGMAC_INT_DMA_CH_SR_TI_RI; | |
307 | else if (channel->tx_ring) | |
308 | int_id = XGMAC_INT_DMA_CH_SR_TI; | |
309 | else if (channel->rx_ring) | |
310 | int_id = XGMAC_INT_DMA_CH_SR_RI; | |
311 | else | |
312 | continue; | |
313 | ||
314 | hw_if->disable_int(channel, int_id); | |
c5aa9e3b LT |
315 | } |
316 | } | |
317 | ||
318 | static irqreturn_t xgbe_isr(int irq, void *data) | |
319 | { | |
320 | struct xgbe_prv_data *pdata = data; | |
321 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
322 | struct xgbe_channel *channel; | |
323 | unsigned int dma_isr, dma_ch_isr; | |
23e4eef7 | 324 | unsigned int mac_isr, mac_tssr; |
c5aa9e3b LT |
325 | unsigned int i; |
326 | ||
327 | /* The DMA interrupt status register also reports MAC and MTL | |
328 | * interrupts. So for polling mode, we just need to check for | |
329 | * this register to be non-zero | |
330 | */ | |
331 | dma_isr = XGMAC_IOREAD(pdata, DMA_ISR); | |
332 | if (!dma_isr) | |
333 | goto isr_done; | |
334 | ||
34bf65df | 335 | netif_dbg(pdata, intr, pdata->netdev, "DMA_ISR=%#010x\n", dma_isr); |
c5aa9e3b LT |
336 | |
337 | for (i = 0; i < pdata->channel_count; i++) { | |
338 | if (!(dma_isr & (1 << i))) | |
339 | continue; | |
340 | ||
341 | channel = pdata->channel + i; | |
342 | ||
343 | dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR); | |
34bf65df LT |
344 | netif_dbg(pdata, intr, pdata->netdev, "DMA_CH%u_ISR=%#010x\n", |
345 | i, dma_ch_isr); | |
c5aa9e3b | 346 | |
fd972b73 LT |
347 | /* The TI or RI interrupt bits may still be set even if using |
348 | * per channel DMA interrupts. Check to be sure those are not | |
349 | * enabled before using the private data napi structure. | |
9227dc5e | 350 | */ |
fd972b73 LT |
351 | if (!pdata->per_channel_irq && |
352 | (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) || | |
353 | XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) { | |
c5aa9e3b LT |
354 | if (napi_schedule_prep(&pdata->napi)) { |
355 | /* Disable Tx and Rx interrupts */ | |
356 | xgbe_disable_rx_tx_ints(pdata); | |
357 | ||
358 | /* Turn on polling */ | |
359 | __napi_schedule(&pdata->napi); | |
360 | } | |
361 | } | |
362 | ||
363 | /* Restart the device on a Fatal Bus Error */ | |
364 | if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE)) | |
365 | schedule_work(&pdata->restart_work); | |
366 | ||
367 | /* Clear all interrupt signals */ | |
368 | XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr); | |
369 | } | |
370 | ||
371 | if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) { | |
372 | mac_isr = XGMAC_IOREAD(pdata, MAC_ISR); | |
373 | ||
374 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS)) | |
375 | hw_if->tx_mmc_int(pdata); | |
376 | ||
377 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS)) | |
378 | hw_if->rx_mmc_int(pdata); | |
23e4eef7 LT |
379 | |
380 | if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) { | |
381 | mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR); | |
382 | ||
383 | if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) { | |
384 | /* Read Tx Timestamp to clear interrupt */ | |
385 | pdata->tx_tstamp = | |
386 | hw_if->get_tx_tstamp(pdata); | |
387 | schedule_work(&pdata->tx_tstamp_work); | |
388 | } | |
389 | } | |
c5aa9e3b LT |
390 | } |
391 | ||
c5aa9e3b LT |
392 | isr_done: |
393 | return IRQ_HANDLED; | |
394 | } | |
395 | ||
9227dc5e LT |
396 | static irqreturn_t xgbe_dma_isr(int irq, void *data) |
397 | { | |
398 | struct xgbe_channel *channel = data; | |
399 | ||
400 | /* Per channel DMA interrupts are enabled, so we use the per | |
401 | * channel napi structure and not the private data napi structure | |
402 | */ | |
403 | if (napi_schedule_prep(&channel->napi)) { | |
404 | /* Disable Tx and Rx interrupts */ | |
f9c5c62d | 405 | disable_irq_nosync(channel->dma_irq); |
9227dc5e LT |
406 | |
407 | /* Turn on polling */ | |
408 | __napi_schedule(&channel->napi); | |
409 | } | |
410 | ||
411 | return IRQ_HANDLED; | |
412 | } | |
413 | ||
c635eaac | 414 | static void xgbe_tx_timer(unsigned long data) |
c5aa9e3b | 415 | { |
c635eaac | 416 | struct xgbe_channel *channel = (struct xgbe_channel *)data; |
c5aa9e3b | 417 | struct xgbe_prv_data *pdata = channel->pdata; |
9227dc5e | 418 | struct napi_struct *napi; |
c5aa9e3b LT |
419 | |
420 | DBGPR("-->xgbe_tx_timer\n"); | |
421 | ||
9227dc5e LT |
422 | napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; |
423 | ||
9227dc5e | 424 | if (napi_schedule_prep(napi)) { |
c5aa9e3b | 425 | /* Disable Tx and Rx interrupts */ |
9227dc5e LT |
426 | if (pdata->per_channel_irq) |
427 | disable_irq(channel->dma_irq); | |
428 | else | |
429 | xgbe_disable_rx_tx_ints(pdata); | |
c5aa9e3b LT |
430 | |
431 | /* Turn on polling */ | |
9227dc5e | 432 | __napi_schedule(napi); |
c5aa9e3b LT |
433 | } |
434 | ||
435 | channel->tx_timer_active = 0; | |
436 | ||
c5aa9e3b | 437 | DBGPR("<--xgbe_tx_timer\n"); |
c5aa9e3b LT |
438 | } |
439 | ||
7c12aa08 LT |
440 | static void xgbe_service(struct work_struct *work) |
441 | { | |
442 | struct xgbe_prv_data *pdata = container_of(work, | |
443 | struct xgbe_prv_data, | |
444 | service_work); | |
445 | ||
446 | pdata->phy_if.phy_status(pdata); | |
447 | } | |
448 | ||
449 | static void xgbe_service_timer(unsigned long data) | |
450 | { | |
451 | struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data; | |
452 | ||
453 | schedule_work(&pdata->service_work); | |
454 | ||
455 | mod_timer(&pdata->service_timer, jiffies + HZ); | |
456 | } | |
457 | ||
458 | static void xgbe_init_timers(struct xgbe_prv_data *pdata) | |
c5aa9e3b LT |
459 | { |
460 | struct xgbe_channel *channel; | |
461 | unsigned int i; | |
462 | ||
7c12aa08 LT |
463 | setup_timer(&pdata->service_timer, xgbe_service_timer, |
464 | (unsigned long)pdata); | |
c5aa9e3b LT |
465 | |
466 | channel = pdata->channel; | |
467 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
468 | if (!channel->tx_ring) | |
469 | break; | |
470 | ||
c635eaac LT |
471 | setup_timer(&channel->tx_timer, xgbe_tx_timer, |
472 | (unsigned long)channel); | |
c5aa9e3b | 473 | } |
7c12aa08 | 474 | } |
c5aa9e3b | 475 | |
7c12aa08 LT |
476 | static void xgbe_start_timers(struct xgbe_prv_data *pdata) |
477 | { | |
478 | mod_timer(&pdata->service_timer, jiffies + HZ); | |
c5aa9e3b LT |
479 | } |
480 | ||
7c12aa08 | 481 | static void xgbe_stop_timers(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
482 | { |
483 | struct xgbe_channel *channel; | |
484 | unsigned int i; | |
485 | ||
7c12aa08 | 486 | del_timer_sync(&pdata->service_timer); |
c5aa9e3b LT |
487 | |
488 | channel = pdata->channel; | |
489 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
490 | if (!channel->tx_ring) | |
491 | break; | |
492 | ||
c635eaac | 493 | del_timer_sync(&channel->tx_timer); |
c5aa9e3b | 494 | } |
c5aa9e3b LT |
495 | } |
496 | ||
497 | void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata) | |
498 | { | |
499 | unsigned int mac_hfr0, mac_hfr1, mac_hfr2; | |
500 | struct xgbe_hw_features *hw_feat = &pdata->hw_feat; | |
501 | ||
502 | DBGPR("-->xgbe_get_all_hw_features\n"); | |
503 | ||
504 | mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R); | |
505 | mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R); | |
506 | mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R); | |
507 | ||
508 | memset(hw_feat, 0, sizeof(*hw_feat)); | |
509 | ||
a9a4a2d9 LT |
510 | hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); |
511 | ||
c5aa9e3b LT |
512 | /* Hardware feature register 0 */ |
513 | hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); | |
514 | hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); | |
515 | hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); | |
516 | hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); | |
517 | hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); | |
518 | hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); | |
519 | hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); | |
520 | hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); | |
521 | hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); | |
522 | hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); | |
523 | hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); | |
524 | hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, | |
525 | ADDMACADRSEL); | |
526 | hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); | |
527 | hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); | |
528 | ||
529 | /* Hardware feature register 1 */ | |
530 | hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
531 | RXFIFOSIZE); | |
532 | hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
533 | TXFIFOSIZE); | |
386d325d | 534 | hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); |
c5aa9e3b LT |
535 | hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); |
536 | hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); | |
537 | hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); | |
538 | hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); | |
cf180b8a | 539 | hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); |
fca2d994 | 540 | hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); |
c5aa9e3b LT |
541 | hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, |
542 | HASHTBLSZ); | |
543 | hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, | |
544 | L3L4FNUM); | |
545 | ||
546 | /* Hardware feature register 2 */ | |
547 | hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); | |
548 | hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); | |
549 | hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); | |
550 | hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); | |
551 | hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); | |
552 | hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM); | |
553 | ||
b85e4d89 LT |
554 | /* Translate the Hash Table size into actual number */ |
555 | switch (hw_feat->hash_table_size) { | |
556 | case 0: | |
557 | break; | |
558 | case 1: | |
559 | hw_feat->hash_table_size = 64; | |
560 | break; | |
561 | case 2: | |
562 | hw_feat->hash_table_size = 128; | |
563 | break; | |
564 | case 3: | |
565 | hw_feat->hash_table_size = 256; | |
566 | break; | |
567 | } | |
568 | ||
386d325d LT |
569 | /* Translate the address width setting into actual number */ |
570 | switch (hw_feat->dma_width) { | |
571 | case 0: | |
572 | hw_feat->dma_width = 32; | |
573 | break; | |
574 | case 1: | |
575 | hw_feat->dma_width = 40; | |
576 | break; | |
577 | case 2: | |
578 | hw_feat->dma_width = 48; | |
579 | break; | |
580 | default: | |
581 | hw_feat->dma_width = 32; | |
582 | } | |
583 | ||
211fcf6d | 584 | /* The Queue, Channel and TC counts are zero based so increment them |
c5aa9e3b LT |
585 | * to get the actual number |
586 | */ | |
587 | hw_feat->rx_q_cnt++; | |
588 | hw_feat->tx_q_cnt++; | |
589 | hw_feat->rx_ch_cnt++; | |
590 | hw_feat->tx_ch_cnt++; | |
211fcf6d | 591 | hw_feat->tc_cnt++; |
c5aa9e3b LT |
592 | |
593 | DBGPR("<--xgbe_get_all_hw_features\n"); | |
594 | } | |
595 | ||
596 | static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add) | |
597 | { | |
9227dc5e LT |
598 | struct xgbe_channel *channel; |
599 | unsigned int i; | |
600 | ||
601 | if (pdata->per_channel_irq) { | |
602 | channel = pdata->channel; | |
603 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
604 | if (add) | |
605 | netif_napi_add(pdata->netdev, &channel->napi, | |
606 | xgbe_one_poll, NAPI_POLL_WEIGHT); | |
607 | ||
608 | napi_enable(&channel->napi); | |
609 | } | |
610 | } else { | |
611 | if (add) | |
612 | netif_napi_add(pdata->netdev, &pdata->napi, | |
613 | xgbe_all_poll, NAPI_POLL_WEIGHT); | |
614 | ||
615 | napi_enable(&pdata->napi); | |
616 | } | |
c5aa9e3b LT |
617 | } |
618 | ||
ff42606e | 619 | static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del) |
c5aa9e3b | 620 | { |
9227dc5e LT |
621 | struct xgbe_channel *channel; |
622 | unsigned int i; | |
623 | ||
624 | if (pdata->per_channel_irq) { | |
625 | channel = pdata->channel; | |
626 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
627 | napi_disable(&channel->napi); | |
ff42606e | 628 | |
9227dc5e LT |
629 | if (del) |
630 | netif_napi_del(&channel->napi); | |
631 | } | |
632 | } else { | |
633 | napi_disable(&pdata->napi); | |
634 | ||
635 | if (del) | |
636 | netif_napi_del(&pdata->napi); | |
637 | } | |
c5aa9e3b LT |
638 | } |
639 | ||
c30e76a7 LT |
640 | static int xgbe_request_irqs(struct xgbe_prv_data *pdata) |
641 | { | |
642 | struct xgbe_channel *channel; | |
643 | struct net_device *netdev = pdata->netdev; | |
644 | unsigned int i; | |
645 | int ret; | |
646 | ||
647 | ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0, | |
648 | netdev->name, pdata); | |
649 | if (ret) { | |
650 | netdev_alert(netdev, "error requesting irq %d\n", | |
651 | pdata->dev_irq); | |
652 | return ret; | |
653 | } | |
654 | ||
655 | if (!pdata->per_channel_irq) | |
656 | return 0; | |
657 | ||
658 | channel = pdata->channel; | |
659 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
660 | snprintf(channel->dma_irq_name, | |
661 | sizeof(channel->dma_irq_name) - 1, | |
662 | "%s-TxRx-%u", netdev_name(netdev), | |
663 | channel->queue_index); | |
664 | ||
665 | ret = devm_request_irq(pdata->dev, channel->dma_irq, | |
666 | xgbe_dma_isr, 0, | |
667 | channel->dma_irq_name, channel); | |
668 | if (ret) { | |
669 | netdev_alert(netdev, "error requesting irq %d\n", | |
670 | channel->dma_irq); | |
671 | goto err_irq; | |
672 | } | |
673 | } | |
674 | ||
675 | return 0; | |
676 | ||
677 | err_irq: | |
678 | /* Using an unsigned int, 'i' will go to UINT_MAX and exit */ | |
679 | for (i--, channel--; i < pdata->channel_count; i--, channel--) | |
680 | devm_free_irq(pdata->dev, channel->dma_irq, channel); | |
681 | ||
682 | devm_free_irq(pdata->dev, pdata->dev_irq, pdata); | |
683 | ||
684 | return ret; | |
685 | } | |
686 | ||
687 | static void xgbe_free_irqs(struct xgbe_prv_data *pdata) | |
688 | { | |
689 | struct xgbe_channel *channel; | |
690 | unsigned int i; | |
691 | ||
692 | devm_free_irq(pdata->dev, pdata->dev_irq, pdata); | |
693 | ||
694 | if (!pdata->per_channel_irq) | |
695 | return; | |
696 | ||
697 | channel = pdata->channel; | |
698 | for (i = 0; i < pdata->channel_count; i++, channel++) | |
699 | devm_free_irq(pdata->dev, channel->dma_irq, channel); | |
700 | } | |
701 | ||
c5aa9e3b LT |
702 | void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata) |
703 | { | |
704 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
705 | ||
706 | DBGPR("-->xgbe_init_tx_coalesce\n"); | |
707 | ||
708 | pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS; | |
709 | pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES; | |
710 | ||
711 | hw_if->config_tx_coalesce(pdata); | |
712 | ||
713 | DBGPR("<--xgbe_init_tx_coalesce\n"); | |
714 | } | |
715 | ||
716 | void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata) | |
717 | { | |
718 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
719 | ||
720 | DBGPR("-->xgbe_init_rx_coalesce\n"); | |
721 | ||
722 | pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS); | |
4a57ebcc | 723 | pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS; |
c5aa9e3b LT |
724 | pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES; |
725 | ||
726 | hw_if->config_rx_coalesce(pdata); | |
727 | ||
728 | DBGPR("<--xgbe_init_rx_coalesce\n"); | |
729 | } | |
730 | ||
08dcc47c | 731 | static void xgbe_free_tx_data(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
732 | { |
733 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
734 | struct xgbe_channel *channel; | |
735 | struct xgbe_ring *ring; | |
736 | struct xgbe_ring_data *rdata; | |
737 | unsigned int i, j; | |
738 | ||
08dcc47c | 739 | DBGPR("-->xgbe_free_tx_data\n"); |
c5aa9e3b LT |
740 | |
741 | channel = pdata->channel; | |
742 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
743 | ring = channel->tx_ring; | |
744 | if (!ring) | |
745 | break; | |
746 | ||
747 | for (j = 0; j < ring->rdesc_count; j++) { | |
d0a8ba6c | 748 | rdata = XGBE_GET_DESC_DATA(ring, j); |
08dcc47c | 749 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
750 | } |
751 | } | |
752 | ||
08dcc47c | 753 | DBGPR("<--xgbe_free_tx_data\n"); |
c5aa9e3b LT |
754 | } |
755 | ||
08dcc47c | 756 | static void xgbe_free_rx_data(struct xgbe_prv_data *pdata) |
c5aa9e3b LT |
757 | { |
758 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
759 | struct xgbe_channel *channel; | |
760 | struct xgbe_ring *ring; | |
761 | struct xgbe_ring_data *rdata; | |
762 | unsigned int i, j; | |
763 | ||
08dcc47c | 764 | DBGPR("-->xgbe_free_rx_data\n"); |
c5aa9e3b LT |
765 | |
766 | channel = pdata->channel; | |
767 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
768 | ring = channel->rx_ring; | |
769 | if (!ring) | |
770 | break; | |
771 | ||
772 | for (j = 0; j < ring->rdesc_count; j++) { | |
d0a8ba6c | 773 | rdata = XGBE_GET_DESC_DATA(ring, j); |
08dcc47c | 774 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
775 | } |
776 | } | |
777 | ||
08dcc47c | 778 | DBGPR("<--xgbe_free_rx_data\n"); |
c5aa9e3b LT |
779 | } |
780 | ||
88131a81 LT |
781 | static int xgbe_phy_init(struct xgbe_prv_data *pdata) |
782 | { | |
88131a81 LT |
783 | pdata->phy_link = -1; |
784 | pdata->phy_speed = SPEED_UNKNOWN; | |
785 | pdata->phy_tx_pause = pdata->tx_pause; | |
786 | pdata->phy_rx_pause = pdata->rx_pause; | |
787 | ||
7c12aa08 | 788 | return pdata->phy_if.phy_reset(pdata); |
88131a81 LT |
789 | } |
790 | ||
c5aa9e3b LT |
791 | int xgbe_powerdown(struct net_device *netdev, unsigned int caller) |
792 | { | |
793 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
794 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
795 | unsigned long flags; | |
796 | ||
797 | DBGPR("-->xgbe_powerdown\n"); | |
798 | ||
799 | if (!netif_running(netdev) || | |
800 | (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) { | |
801 | netdev_alert(netdev, "Device is already powered down\n"); | |
802 | DBGPR("<--xgbe_powerdown\n"); | |
803 | return -EINVAL; | |
804 | } | |
805 | ||
c5aa9e3b LT |
806 | spin_lock_irqsave(&pdata->lock, flags); |
807 | ||
808 | if (caller == XGMAC_DRIVER_CONTEXT) | |
809 | netif_device_detach(netdev); | |
810 | ||
811 | netif_tx_stop_all_queues(netdev); | |
c5aa9e3b | 812 | |
7c12aa08 LT |
813 | xgbe_stop_timers(pdata); |
814 | flush_workqueue(pdata->dev_workqueue); | |
815 | ||
c5aa9e3b LT |
816 | hw_if->powerdown_tx(pdata); |
817 | hw_if->powerdown_rx(pdata); | |
818 | ||
c30e76a7 LT |
819 | xgbe_napi_disable(pdata, 0); |
820 | ||
c5aa9e3b LT |
821 | pdata->power_down = 1; |
822 | ||
823 | spin_unlock_irqrestore(&pdata->lock, flags); | |
824 | ||
825 | DBGPR("<--xgbe_powerdown\n"); | |
826 | ||
827 | return 0; | |
828 | } | |
829 | ||
830 | int xgbe_powerup(struct net_device *netdev, unsigned int caller) | |
831 | { | |
832 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
833 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
834 | unsigned long flags; | |
835 | ||
836 | DBGPR("-->xgbe_powerup\n"); | |
837 | ||
838 | if (!netif_running(netdev) || | |
839 | (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) { | |
840 | netdev_alert(netdev, "Device is already powered up\n"); | |
841 | DBGPR("<--xgbe_powerup\n"); | |
842 | return -EINVAL; | |
843 | } | |
844 | ||
845 | spin_lock_irqsave(&pdata->lock, flags); | |
846 | ||
847 | pdata->power_down = 0; | |
848 | ||
c30e76a7 LT |
849 | xgbe_napi_enable(pdata, 0); |
850 | ||
c5aa9e3b LT |
851 | hw_if->powerup_tx(pdata); |
852 | hw_if->powerup_rx(pdata); | |
853 | ||
854 | if (caller == XGMAC_DRIVER_CONTEXT) | |
855 | netif_device_attach(netdev); | |
856 | ||
c5aa9e3b LT |
857 | netif_tx_start_all_queues(netdev); |
858 | ||
7c12aa08 LT |
859 | xgbe_start_timers(pdata); |
860 | ||
c5aa9e3b LT |
861 | spin_unlock_irqrestore(&pdata->lock, flags); |
862 | ||
863 | DBGPR("<--xgbe_powerup\n"); | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
868 | static int xgbe_start(struct xgbe_prv_data *pdata) | |
869 | { | |
870 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
7c12aa08 | 871 | struct xgbe_phy_if *phy_if = &pdata->phy_if; |
c5aa9e3b | 872 | struct net_device *netdev = pdata->netdev; |
c30e76a7 | 873 | int ret; |
c5aa9e3b LT |
874 | |
875 | DBGPR("-->xgbe_start\n"); | |
876 | ||
c5aa9e3b LT |
877 | hw_if->init(pdata); |
878 | ||
7c12aa08 LT |
879 | ret = phy_if->phy_start(pdata); |
880 | if (ret) | |
881 | goto err_phy; | |
c5aa9e3b | 882 | |
c30e76a7 LT |
883 | xgbe_napi_enable(pdata, 1); |
884 | ||
885 | ret = xgbe_request_irqs(pdata); | |
886 | if (ret) | |
887 | goto err_napi; | |
888 | ||
c5aa9e3b LT |
889 | hw_if->enable_tx(pdata); |
890 | hw_if->enable_rx(pdata); | |
891 | ||
c5aa9e3b LT |
892 | netif_tx_start_all_queues(netdev); |
893 | ||
7c12aa08 LT |
894 | xgbe_start_timers(pdata); |
895 | schedule_work(&pdata->service_work); | |
896 | ||
c5aa9e3b LT |
897 | DBGPR("<--xgbe_start\n"); |
898 | ||
899 | return 0; | |
c30e76a7 LT |
900 | |
901 | err_napi: | |
902 | xgbe_napi_disable(pdata, 1); | |
903 | ||
7c12aa08 | 904 | phy_if->phy_stop(pdata); |
c30e76a7 | 905 | |
7c12aa08 | 906 | err_phy: |
c30e76a7 LT |
907 | hw_if->exit(pdata); |
908 | ||
909 | return ret; | |
c5aa9e3b LT |
910 | } |
911 | ||
912 | static void xgbe_stop(struct xgbe_prv_data *pdata) | |
913 | { | |
914 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
7c12aa08 | 915 | struct xgbe_phy_if *phy_if = &pdata->phy_if; |
5fb4b86a | 916 | struct xgbe_channel *channel; |
c5aa9e3b | 917 | struct net_device *netdev = pdata->netdev; |
5fb4b86a LT |
918 | struct netdev_queue *txq; |
919 | unsigned int i; | |
c5aa9e3b LT |
920 | |
921 | DBGPR("-->xgbe_stop\n"); | |
922 | ||
c5aa9e3b | 923 | netif_tx_stop_all_queues(netdev); |
c5aa9e3b | 924 | |
7c12aa08 LT |
925 | xgbe_stop_timers(pdata); |
926 | flush_workqueue(pdata->dev_workqueue); | |
c5aa9e3b LT |
927 | |
928 | hw_if->disable_tx(pdata); | |
929 | hw_if->disable_rx(pdata); | |
930 | ||
c30e76a7 LT |
931 | xgbe_free_irqs(pdata); |
932 | ||
933 | xgbe_napi_disable(pdata, 1); | |
934 | ||
7c12aa08 | 935 | phy_if->phy_stop(pdata); |
c30e76a7 LT |
936 | |
937 | hw_if->exit(pdata); | |
938 | ||
5fb4b86a LT |
939 | channel = pdata->channel; |
940 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
941 | if (!channel->tx_ring) | |
942 | continue; | |
943 | ||
944 | txq = netdev_get_tx_queue(netdev, channel->queue_index); | |
945 | netdev_tx_reset_queue(txq); | |
946 | } | |
947 | ||
c5aa9e3b LT |
948 | DBGPR("<--xgbe_stop\n"); |
949 | } | |
950 | ||
916102c6 | 951 | static void xgbe_restart_dev(struct xgbe_prv_data *pdata) |
c5aa9e3b | 952 | { |
c5aa9e3b LT |
953 | DBGPR("-->xgbe_restart_dev\n"); |
954 | ||
955 | /* If not running, "restart" will happen on open */ | |
956 | if (!netif_running(pdata->netdev)) | |
957 | return; | |
958 | ||
959 | xgbe_stop(pdata); | |
c5aa9e3b | 960 | |
08dcc47c LT |
961 | xgbe_free_tx_data(pdata); |
962 | xgbe_free_rx_data(pdata); | |
c5aa9e3b | 963 | |
c5aa9e3b LT |
964 | xgbe_start(pdata); |
965 | ||
966 | DBGPR("<--xgbe_restart_dev\n"); | |
967 | } | |
968 | ||
969 | static void xgbe_restart(struct work_struct *work) | |
970 | { | |
971 | struct xgbe_prv_data *pdata = container_of(work, | |
972 | struct xgbe_prv_data, | |
973 | restart_work); | |
974 | ||
975 | rtnl_lock(); | |
976 | ||
916102c6 | 977 | xgbe_restart_dev(pdata); |
c5aa9e3b LT |
978 | |
979 | rtnl_unlock(); | |
980 | } | |
981 | ||
23e4eef7 LT |
982 | static void xgbe_tx_tstamp(struct work_struct *work) |
983 | { | |
984 | struct xgbe_prv_data *pdata = container_of(work, | |
985 | struct xgbe_prv_data, | |
986 | tx_tstamp_work); | |
987 | struct skb_shared_hwtstamps hwtstamps; | |
988 | u64 nsec; | |
989 | unsigned long flags; | |
990 | ||
991 | if (pdata->tx_tstamp) { | |
992 | nsec = timecounter_cyc2time(&pdata->tstamp_tc, | |
993 | pdata->tx_tstamp); | |
994 | ||
995 | memset(&hwtstamps, 0, sizeof(hwtstamps)); | |
996 | hwtstamps.hwtstamp = ns_to_ktime(nsec); | |
997 | skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps); | |
998 | } | |
999 | ||
1000 | dev_kfree_skb_any(pdata->tx_tstamp_skb); | |
1001 | ||
1002 | spin_lock_irqsave(&pdata->tstamp_lock, flags); | |
1003 | pdata->tx_tstamp_skb = NULL; | |
1004 | spin_unlock_irqrestore(&pdata->tstamp_lock, flags); | |
1005 | } | |
1006 | ||
1007 | static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, | |
1008 | struct ifreq *ifreq) | |
1009 | { | |
1010 | if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config, | |
1011 | sizeof(pdata->tstamp_config))) | |
1012 | return -EFAULT; | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, | |
1018 | struct ifreq *ifreq) | |
1019 | { | |
1020 | struct hwtstamp_config config; | |
1021 | unsigned int mac_tscr; | |
1022 | ||
1023 | if (copy_from_user(&config, ifreq->ifr_data, sizeof(config))) | |
1024 | return -EFAULT; | |
1025 | ||
1026 | if (config.flags) | |
1027 | return -EINVAL; | |
1028 | ||
1029 | mac_tscr = 0; | |
1030 | ||
1031 | switch (config.tx_type) { | |
1032 | case HWTSTAMP_TX_OFF: | |
1033 | break; | |
1034 | ||
1035 | case HWTSTAMP_TX_ON: | |
1036 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1037 | break; | |
1038 | ||
1039 | default: | |
1040 | return -ERANGE; | |
1041 | } | |
1042 | ||
1043 | switch (config.rx_filter) { | |
1044 | case HWTSTAMP_FILTER_NONE: | |
1045 | break; | |
1046 | ||
1047 | case HWTSTAMP_FILTER_ALL: | |
1048 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1); | |
1049 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1050 | break; | |
1051 | ||
1052 | /* PTP v2, UDP, any kind of event packet */ | |
1053 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1054 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1055 | /* PTP v1, UDP, any kind of event packet */ | |
1056 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1057 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1058 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1059 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1060 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1061 | break; | |
1062 | ||
1063 | /* PTP v2, UDP, Sync packet */ | |
1064 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1065 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1066 | /* PTP v1, UDP, Sync packet */ | |
1067 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1068 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1069 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1070 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1071 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1072 | break; | |
1073 | ||
1074 | /* PTP v2, UDP, Delay_req packet */ | |
1075 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1076 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1077 | /* PTP v1, UDP, Delay_req packet */ | |
1078 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1079 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1080 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1081 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1082 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1083 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1084 | break; | |
1085 | ||
1086 | /* 802.AS1, Ethernet, any kind of event packet */ | |
1087 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1088 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1089 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1090 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1091 | break; | |
1092 | ||
1093 | /* 802.AS1, Ethernet, Sync packet */ | |
1094 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1095 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1096 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1097 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1098 | break; | |
1099 | ||
1100 | /* 802.AS1, Ethernet, Delay_req packet */ | |
1101 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1102 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1); | |
1103 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1104 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1105 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1106 | break; | |
1107 | ||
1108 | /* PTP v2/802.AS1, any layer, any kind of event packet */ | |
1109 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1110 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1111 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1112 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1113 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1114 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1); | |
1115 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1116 | break; | |
1117 | ||
1118 | /* PTP v2/802.AS1, any layer, Sync packet */ | |
1119 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1120 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1121 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1122 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1123 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1124 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1125 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1126 | break; | |
1127 | ||
1128 | /* PTP v2/802.AS1, any layer, Delay_req packet */ | |
1129 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1130 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1); | |
1131 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1); | |
1132 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1); | |
1133 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1); | |
1134 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1); | |
1135 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1); | |
1136 | XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1); | |
1137 | break; | |
1138 | ||
1139 | default: | |
1140 | return -ERANGE; | |
1141 | } | |
1142 | ||
1143 | pdata->hw_if.config_tstamp(pdata, mac_tscr); | |
1144 | ||
1145 | memcpy(&pdata->tstamp_config, &config, sizeof(config)); | |
1146 | ||
1147 | return 0; | |
1148 | } | |
1149 | ||
1150 | static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata, | |
1151 | struct sk_buff *skb, | |
1152 | struct xgbe_packet_data *packet) | |
1153 | { | |
1154 | unsigned long flags; | |
1155 | ||
1156 | if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) { | |
1157 | spin_lock_irqsave(&pdata->tstamp_lock, flags); | |
1158 | if (pdata->tx_tstamp_skb) { | |
1159 | /* Another timestamp in progress, ignore this one */ | |
1160 | XGMAC_SET_BITS(packet->attributes, | |
1161 | TX_PACKET_ATTRIBUTES, PTP, 0); | |
1162 | } else { | |
1163 | pdata->tx_tstamp_skb = skb_get(skb); | |
1164 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
1165 | } | |
1166 | spin_unlock_irqrestore(&pdata->tstamp_lock, flags); | |
1167 | } | |
1168 | ||
1169 | if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) | |
1170 | skb_tx_timestamp(skb); | |
1171 | } | |
1172 | ||
c5aa9e3b LT |
1173 | static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet) |
1174 | { | |
df8a39de JP |
1175 | if (skb_vlan_tag_present(skb)) |
1176 | packet->vlan_ctag = skb_vlan_tag_get(skb); | |
c5aa9e3b LT |
1177 | } |
1178 | ||
1179 | static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet) | |
1180 | { | |
1181 | int ret; | |
1182 | ||
1183 | if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1184 | TSO_ENABLE)) | |
1185 | return 0; | |
1186 | ||
1187 | ret = skb_cow_head(skb, 0); | |
1188 | if (ret) | |
1189 | return ret; | |
1190 | ||
1191 | packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
1192 | packet->tcp_header_len = tcp_hdrlen(skb); | |
1193 | packet->tcp_payload_len = skb->len - packet->header_len; | |
1194 | packet->mss = skb_shinfo(skb)->gso_size; | |
1195 | DBGPR(" packet->header_len=%u\n", packet->header_len); | |
1196 | DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n", | |
1197 | packet->tcp_header_len, packet->tcp_payload_len); | |
1198 | DBGPR(" packet->mss=%u\n", packet->mss); | |
1199 | ||
5fb4b86a LT |
1200 | /* Update the number of packets that will ultimately be transmitted |
1201 | * along with the extra bytes for each extra packet | |
1202 | */ | |
1203 | packet->tx_packets = skb_shinfo(skb)->gso_segs; | |
1204 | packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len; | |
1205 | ||
c5aa9e3b LT |
1206 | return 0; |
1207 | } | |
1208 | ||
1209 | static int xgbe_is_tso(struct sk_buff *skb) | |
1210 | { | |
1211 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
1212 | return 0; | |
1213 | ||
1214 | if (!skb_is_gso(skb)) | |
1215 | return 0; | |
1216 | ||
1217 | DBGPR(" TSO packet to be processed\n"); | |
1218 | ||
1219 | return 1; | |
1220 | } | |
1221 | ||
23e4eef7 LT |
1222 | static void xgbe_packet_info(struct xgbe_prv_data *pdata, |
1223 | struct xgbe_ring *ring, struct sk_buff *skb, | |
c5aa9e3b LT |
1224 | struct xgbe_packet_data *packet) |
1225 | { | |
1226 | struct skb_frag_struct *frag; | |
1227 | unsigned int context_desc; | |
1228 | unsigned int len; | |
1229 | unsigned int i; | |
1230 | ||
16958a2b LT |
1231 | packet->skb = skb; |
1232 | ||
c5aa9e3b LT |
1233 | context_desc = 0; |
1234 | packet->rdesc_count = 0; | |
1235 | ||
5fb4b86a LT |
1236 | packet->tx_packets = 1; |
1237 | packet->tx_bytes = skb->len; | |
1238 | ||
c5aa9e3b | 1239 | if (xgbe_is_tso(skb)) { |
a7beaf23 | 1240 | /* TSO requires an extra descriptor if mss is different */ |
c5aa9e3b LT |
1241 | if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) { |
1242 | context_desc = 1; | |
1243 | packet->rdesc_count++; | |
1244 | } | |
1245 | ||
a7beaf23 | 1246 | /* TSO requires an extra descriptor for TSO header */ |
c5aa9e3b LT |
1247 | packet->rdesc_count++; |
1248 | ||
1249 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1250 | TSO_ENABLE, 1); | |
1251 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1252 | CSUM_ENABLE, 1); | |
1253 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) | |
1254 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1255 | CSUM_ENABLE, 1); | |
1256 | ||
df8a39de | 1257 | if (skb_vlan_tag_present(skb)) { |
c5aa9e3b | 1258 | /* VLAN requires an extra descriptor if tag is different */ |
df8a39de | 1259 | if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag) |
c5aa9e3b LT |
1260 | /* We can share with the TSO context descriptor */ |
1261 | if (!context_desc) { | |
1262 | context_desc = 1; | |
1263 | packet->rdesc_count++; | |
1264 | } | |
1265 | ||
1266 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1267 | VLAN_CTAG, 1); | |
1268 | } | |
1269 | ||
23e4eef7 LT |
1270 | if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
1271 | (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON)) | |
1272 | XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, | |
1273 | PTP, 1); | |
1274 | ||
c5aa9e3b LT |
1275 | for (len = skb_headlen(skb); len;) { |
1276 | packet->rdesc_count++; | |
d0a8ba6c | 1277 | len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); |
c5aa9e3b LT |
1278 | } |
1279 | ||
1280 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1281 | frag = &skb_shinfo(skb)->frags[i]; | |
1282 | for (len = skb_frag_size(frag); len; ) { | |
1283 | packet->rdesc_count++; | |
d0a8ba6c | 1284 | len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE); |
c5aa9e3b LT |
1285 | } |
1286 | } | |
1287 | } | |
1288 | ||
1289 | static int xgbe_open(struct net_device *netdev) | |
1290 | { | |
1291 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
c5aa9e3b LT |
1292 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1293 | int ret; | |
1294 | ||
1295 | DBGPR("-->xgbe_open\n"); | |
1296 | ||
88131a81 LT |
1297 | /* Initialize the phy */ |
1298 | ret = xgbe_phy_init(pdata); | |
1299 | if (ret) | |
1300 | return ret; | |
1301 | ||
23e4eef7 LT |
1302 | /* Enable the clocks */ |
1303 | ret = clk_prepare_enable(pdata->sysclk); | |
c5aa9e3b | 1304 | if (ret) { |
23e4eef7 | 1305 | netdev_alert(netdev, "dma clk_prepare_enable failed\n"); |
7c12aa08 | 1306 | return ret; |
c5aa9e3b LT |
1307 | } |
1308 | ||
23e4eef7 LT |
1309 | ret = clk_prepare_enable(pdata->ptpclk); |
1310 | if (ret) { | |
1311 | netdev_alert(netdev, "ptp clk_prepare_enable failed\n"); | |
1312 | goto err_sysclk; | |
1313 | } | |
1314 | ||
c5aa9e3b LT |
1315 | /* Calculate the Rx buffer size before allocating rings */ |
1316 | ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu); | |
1317 | if (ret < 0) | |
23e4eef7 | 1318 | goto err_ptpclk; |
c5aa9e3b LT |
1319 | pdata->rx_buf_size = ret; |
1320 | ||
4780b7ca LT |
1321 | /* Allocate the channel and ring structures */ |
1322 | ret = xgbe_alloc_channels(pdata); | |
1323 | if (ret) | |
1324 | goto err_ptpclk; | |
1325 | ||
c5aa9e3b LT |
1326 | /* Allocate the ring descriptors and buffers */ |
1327 | ret = desc_if->alloc_ring_resources(pdata); | |
1328 | if (ret) | |
4780b7ca | 1329 | goto err_channels; |
c5aa9e3b | 1330 | |
7c12aa08 | 1331 | INIT_WORK(&pdata->service_work, xgbe_service); |
c5aa9e3b | 1332 | INIT_WORK(&pdata->restart_work, xgbe_restart); |
23e4eef7 | 1333 | INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp); |
7c12aa08 | 1334 | xgbe_init_timers(pdata); |
c5aa9e3b | 1335 | |
c5aa9e3b LT |
1336 | ret = xgbe_start(pdata); |
1337 | if (ret) | |
c30e76a7 | 1338 | goto err_rings; |
c5aa9e3b | 1339 | |
7c12aa08 LT |
1340 | clear_bit(XGBE_DOWN, &pdata->dev_state); |
1341 | ||
c5aa9e3b LT |
1342 | DBGPR("<--xgbe_open\n"); |
1343 | ||
1344 | return 0; | |
1345 | ||
4780b7ca | 1346 | err_rings: |
c5aa9e3b LT |
1347 | desc_if->free_ring_resources(pdata); |
1348 | ||
4780b7ca LT |
1349 | err_channels: |
1350 | xgbe_free_channels(pdata); | |
1351 | ||
23e4eef7 LT |
1352 | err_ptpclk: |
1353 | clk_disable_unprepare(pdata->ptpclk); | |
1354 | ||
1355 | err_sysclk: | |
1356 | clk_disable_unprepare(pdata->sysclk); | |
c5aa9e3b LT |
1357 | |
1358 | return ret; | |
1359 | } | |
1360 | ||
1361 | static int xgbe_close(struct net_device *netdev) | |
1362 | { | |
1363 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
c5aa9e3b LT |
1364 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1365 | ||
1366 | DBGPR("-->xgbe_close\n"); | |
1367 | ||
1368 | /* Stop the device */ | |
1369 | xgbe_stop(pdata); | |
1370 | ||
4780b7ca | 1371 | /* Free the ring descriptors and buffers */ |
c5aa9e3b LT |
1372 | desc_if->free_ring_resources(pdata); |
1373 | ||
e98c72c9 LT |
1374 | /* Free the channel and ring structures */ |
1375 | xgbe_free_channels(pdata); | |
1376 | ||
23e4eef7 LT |
1377 | /* Disable the clocks */ |
1378 | clk_disable_unprepare(pdata->ptpclk); | |
1379 | clk_disable_unprepare(pdata->sysclk); | |
c5aa9e3b | 1380 | |
7c12aa08 | 1381 | set_bit(XGBE_DOWN, &pdata->dev_state); |
88131a81 | 1382 | |
c5aa9e3b LT |
1383 | DBGPR("<--xgbe_close\n"); |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
1388 | static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev) | |
1389 | { | |
1390 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1391 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1392 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
1393 | struct xgbe_channel *channel; | |
1394 | struct xgbe_ring *ring; | |
1395 | struct xgbe_packet_data *packet; | |
5fb4b86a | 1396 | struct netdev_queue *txq; |
c5aa9e3b LT |
1397 | int ret; |
1398 | ||
1399 | DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len); | |
1400 | ||
1401 | channel = pdata->channel + skb->queue_mapping; | |
5fb4b86a | 1402 | txq = netdev_get_tx_queue(netdev, channel->queue_index); |
c5aa9e3b LT |
1403 | ring = channel->tx_ring; |
1404 | packet = &ring->packet_data; | |
1405 | ||
1406 | ret = NETDEV_TX_OK; | |
1407 | ||
c5aa9e3b | 1408 | if (skb->len == 0) { |
34bf65df LT |
1409 | netif_err(pdata, tx_err, netdev, |
1410 | "empty skb received from stack\n"); | |
c5aa9e3b LT |
1411 | dev_kfree_skb_any(skb); |
1412 | goto tx_netdev_return; | |
1413 | } | |
1414 | ||
1415 | /* Calculate preliminary packet info */ | |
1416 | memset(packet, 0, sizeof(*packet)); | |
23e4eef7 | 1417 | xgbe_packet_info(pdata, ring, skb, packet); |
c5aa9e3b LT |
1418 | |
1419 | /* Check that there are enough descriptors available */ | |
16958a2b LT |
1420 | ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count); |
1421 | if (ret) | |
c5aa9e3b | 1422 | goto tx_netdev_return; |
c5aa9e3b LT |
1423 | |
1424 | ret = xgbe_prep_tso(skb, packet); | |
1425 | if (ret) { | |
34bf65df LT |
1426 | netif_err(pdata, tx_err, netdev, |
1427 | "error processing TSO packet\n"); | |
c5aa9e3b LT |
1428 | dev_kfree_skb_any(skb); |
1429 | goto tx_netdev_return; | |
1430 | } | |
1431 | xgbe_prep_vlan(skb, packet); | |
1432 | ||
1433 | if (!desc_if->map_tx_skb(channel, skb)) { | |
1434 | dev_kfree_skb_any(skb); | |
1435 | goto tx_netdev_return; | |
1436 | } | |
1437 | ||
23e4eef7 LT |
1438 | xgbe_prep_tx_tstamp(pdata, skb, packet); |
1439 | ||
5fb4b86a LT |
1440 | /* Report on the actual number of bytes (to be) sent */ |
1441 | netdev_tx_sent_queue(txq, packet->tx_bytes); | |
1442 | ||
c5aa9e3b | 1443 | /* Configure required descriptor fields for transmission */ |
a9d41981 | 1444 | hw_if->dev_xmit(channel); |
c5aa9e3b | 1445 | |
34bf65df LT |
1446 | if (netif_msg_pktdata(pdata)) |
1447 | xgbe_print_pkt(netdev, skb, true); | |
c5aa9e3b | 1448 | |
16958a2b LT |
1449 | /* Stop the queue in advance if there may not be enough descriptors */ |
1450 | xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS); | |
1451 | ||
1452 | ret = NETDEV_TX_OK; | |
1453 | ||
c5aa9e3b | 1454 | tx_netdev_return: |
c5aa9e3b LT |
1455 | return ret; |
1456 | } | |
1457 | ||
1458 | static void xgbe_set_rx_mode(struct net_device *netdev) | |
1459 | { | |
1460 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1461 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
c5aa9e3b LT |
1462 | |
1463 | DBGPR("-->xgbe_set_rx_mode\n"); | |
1464 | ||
b876382b | 1465 | hw_if->config_rx_mode(pdata); |
c5aa9e3b LT |
1466 | |
1467 | DBGPR("<--xgbe_set_rx_mode\n"); | |
1468 | } | |
1469 | ||
1470 | static int xgbe_set_mac_address(struct net_device *netdev, void *addr) | |
1471 | { | |
1472 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1473 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1474 | struct sockaddr *saddr = addr; | |
1475 | ||
1476 | DBGPR("-->xgbe_set_mac_address\n"); | |
1477 | ||
1478 | if (!is_valid_ether_addr(saddr->sa_data)) | |
1479 | return -EADDRNOTAVAIL; | |
1480 | ||
1481 | memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len); | |
1482 | ||
1483 | hw_if->set_mac_address(pdata, netdev->dev_addr); | |
1484 | ||
1485 | DBGPR("<--xgbe_set_mac_address\n"); | |
1486 | ||
1487 | return 0; | |
1488 | } | |
1489 | ||
23e4eef7 LT |
1490 | static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd) |
1491 | { | |
1492 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1493 | int ret; | |
1494 | ||
1495 | switch (cmd) { | |
1496 | case SIOCGHWTSTAMP: | |
1497 | ret = xgbe_get_hwtstamp_settings(pdata, ifreq); | |
1498 | break; | |
1499 | ||
1500 | case SIOCSHWTSTAMP: | |
1501 | ret = xgbe_set_hwtstamp_settings(pdata, ifreq); | |
1502 | break; | |
1503 | ||
1504 | default: | |
1505 | ret = -EOPNOTSUPP; | |
1506 | } | |
1507 | ||
1508 | return ret; | |
1509 | } | |
1510 | ||
c5aa9e3b LT |
1511 | static int xgbe_change_mtu(struct net_device *netdev, int mtu) |
1512 | { | |
1513 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1514 | int ret; | |
1515 | ||
1516 | DBGPR("-->xgbe_change_mtu\n"); | |
1517 | ||
1518 | ret = xgbe_calc_rx_buf_size(netdev, mtu); | |
1519 | if (ret < 0) | |
1520 | return ret; | |
1521 | ||
1522 | pdata->rx_buf_size = ret; | |
1523 | netdev->mtu = mtu; | |
1524 | ||
916102c6 | 1525 | xgbe_restart_dev(pdata); |
c5aa9e3b LT |
1526 | |
1527 | DBGPR("<--xgbe_change_mtu\n"); | |
1528 | ||
1529 | return 0; | |
1530 | } | |
1531 | ||
a8373f1a LT |
1532 | static void xgbe_tx_timeout(struct net_device *netdev) |
1533 | { | |
1534 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1535 | ||
1536 | netdev_warn(netdev, "tx timeout, device restarting\n"); | |
1537 | schedule_work(&pdata->restart_work); | |
1538 | } | |
1539 | ||
c5aa9e3b LT |
1540 | static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev, |
1541 | struct rtnl_link_stats64 *s) | |
1542 | { | |
1543 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1544 | struct xgbe_mmc_stats *pstats = &pdata->mmc_stats; | |
1545 | ||
1546 | DBGPR("-->%s\n", __func__); | |
1547 | ||
1548 | pdata->hw_if.read_mmc_stats(pdata); | |
1549 | ||
1550 | s->rx_packets = pstats->rxframecount_gb; | |
1551 | s->rx_bytes = pstats->rxoctetcount_gb; | |
1552 | s->rx_errors = pstats->rxframecount_gb - | |
1553 | pstats->rxbroadcastframes_g - | |
1554 | pstats->rxmulticastframes_g - | |
1555 | pstats->rxunicastframes_g; | |
1556 | s->multicast = pstats->rxmulticastframes_g; | |
1557 | s->rx_length_errors = pstats->rxlengtherror; | |
1558 | s->rx_crc_errors = pstats->rxcrcerror; | |
1559 | s->rx_fifo_errors = pstats->rxfifooverflow; | |
1560 | ||
1561 | s->tx_packets = pstats->txframecount_gb; | |
1562 | s->tx_bytes = pstats->txoctetcount_gb; | |
1563 | s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g; | |
1564 | s->tx_dropped = netdev->stats.tx_dropped; | |
1565 | ||
1566 | DBGPR("<--%s\n", __func__); | |
1567 | ||
1568 | return s; | |
1569 | } | |
1570 | ||
801c62d9 LT |
1571 | static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, |
1572 | u16 vid) | |
1573 | { | |
1574 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1575 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1576 | ||
1577 | DBGPR("-->%s\n", __func__); | |
1578 | ||
1579 | set_bit(vid, pdata->active_vlans); | |
1580 | hw_if->update_vlan_hash_table(pdata); | |
1581 | ||
1582 | DBGPR("<--%s\n", __func__); | |
1583 | ||
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, | |
1588 | u16 vid) | |
1589 | { | |
1590 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1591 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1592 | ||
1593 | DBGPR("-->%s\n", __func__); | |
1594 | ||
1595 | clear_bit(vid, pdata->active_vlans); | |
1596 | hw_if->update_vlan_hash_table(pdata); | |
1597 | ||
1598 | DBGPR("<--%s\n", __func__); | |
1599 | ||
1600 | return 0; | |
1601 | } | |
1602 | ||
c5aa9e3b LT |
1603 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1604 | static void xgbe_poll_controller(struct net_device *netdev) | |
1605 | { | |
1606 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
9227dc5e LT |
1607 | struct xgbe_channel *channel; |
1608 | unsigned int i; | |
c5aa9e3b LT |
1609 | |
1610 | DBGPR("-->xgbe_poll_controller\n"); | |
1611 | ||
9227dc5e LT |
1612 | if (pdata->per_channel_irq) { |
1613 | channel = pdata->channel; | |
1614 | for (i = 0; i < pdata->channel_count; i++, channel++) | |
1615 | xgbe_dma_isr(channel->dma_irq, channel); | |
1616 | } else { | |
1617 | disable_irq(pdata->dev_irq); | |
1618 | xgbe_isr(pdata->dev_irq, pdata); | |
1619 | enable_irq(pdata->dev_irq); | |
1620 | } | |
c5aa9e3b LT |
1621 | |
1622 | DBGPR("<--xgbe_poll_controller\n"); | |
1623 | } | |
1624 | #endif /* End CONFIG_NET_POLL_CONTROLLER */ | |
1625 | ||
fca2d994 LT |
1626 | static int xgbe_setup_tc(struct net_device *netdev, u8 tc) |
1627 | { | |
1628 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1629 | unsigned int offset, queue; | |
1630 | u8 i; | |
1631 | ||
1632 | if (tc && (tc != pdata->hw_feat.tc_cnt)) | |
1633 | return -EINVAL; | |
1634 | ||
1635 | if (tc) { | |
1636 | netdev_set_num_tc(netdev, tc); | |
1637 | for (i = 0, queue = 0, offset = 0; i < tc; i++) { | |
1638 | while ((queue < pdata->tx_q_count) && | |
1639 | (pdata->q2tc_map[queue] == i)) | |
1640 | queue++; | |
1641 | ||
34bf65df LT |
1642 | netif_dbg(pdata, drv, netdev, "TC%u using TXq%u-%u\n", |
1643 | i, offset, queue - 1); | |
fca2d994 LT |
1644 | netdev_set_tc_queue(netdev, i, queue - offset, offset); |
1645 | offset = queue; | |
1646 | } | |
1647 | } else { | |
1648 | netdev_reset_tc(netdev); | |
1649 | } | |
1650 | ||
1651 | return 0; | |
1652 | } | |
1653 | ||
c5aa9e3b LT |
1654 | static int xgbe_set_features(struct net_device *netdev, |
1655 | netdev_features_t features) | |
1656 | { | |
1657 | struct xgbe_prv_data *pdata = netdev_priv(netdev); | |
1658 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
5b9dfe29 LT |
1659 | netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter; |
1660 | int ret = 0; | |
c5aa9e3b | 1661 | |
5b9dfe29 | 1662 | rxhash = pdata->netdev_features & NETIF_F_RXHASH; |
801c62d9 LT |
1663 | rxcsum = pdata->netdev_features & NETIF_F_RXCSUM; |
1664 | rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX; | |
1665 | rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER; | |
c5aa9e3b | 1666 | |
5b9dfe29 LT |
1667 | if ((features & NETIF_F_RXHASH) && !rxhash) |
1668 | ret = hw_if->enable_rss(pdata); | |
1669 | else if (!(features & NETIF_F_RXHASH) && rxhash) | |
1670 | ret = hw_if->disable_rss(pdata); | |
1671 | if (ret) | |
1672 | return ret; | |
1673 | ||
801c62d9 | 1674 | if ((features & NETIF_F_RXCSUM) && !rxcsum) |
c5aa9e3b | 1675 | hw_if->enable_rx_csum(pdata); |
801c62d9 | 1676 | else if (!(features & NETIF_F_RXCSUM) && rxcsum) |
c5aa9e3b | 1677 | hw_if->disable_rx_csum(pdata); |
c5aa9e3b | 1678 | |
801c62d9 | 1679 | if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan) |
c5aa9e3b | 1680 | hw_if->enable_rx_vlan_stripping(pdata); |
801c62d9 | 1681 | else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan) |
c5aa9e3b | 1682 | hw_if->disable_rx_vlan_stripping(pdata); |
801c62d9 LT |
1683 | |
1684 | if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter) | |
1685 | hw_if->enable_rx_vlan_filtering(pdata); | |
1686 | else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter) | |
1687 | hw_if->disable_rx_vlan_filtering(pdata); | |
c5aa9e3b LT |
1688 | |
1689 | pdata->netdev_features = features; | |
1690 | ||
1691 | DBGPR("<--xgbe_set_features\n"); | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | static const struct net_device_ops xgbe_netdev_ops = { | |
1697 | .ndo_open = xgbe_open, | |
1698 | .ndo_stop = xgbe_close, | |
1699 | .ndo_start_xmit = xgbe_xmit, | |
1700 | .ndo_set_rx_mode = xgbe_set_rx_mode, | |
1701 | .ndo_set_mac_address = xgbe_set_mac_address, | |
1702 | .ndo_validate_addr = eth_validate_addr, | |
23e4eef7 | 1703 | .ndo_do_ioctl = xgbe_ioctl, |
c5aa9e3b | 1704 | .ndo_change_mtu = xgbe_change_mtu, |
a8373f1a | 1705 | .ndo_tx_timeout = xgbe_tx_timeout, |
c5aa9e3b | 1706 | .ndo_get_stats64 = xgbe_get_stats64, |
801c62d9 LT |
1707 | .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid, |
1708 | .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid, | |
c5aa9e3b LT |
1709 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1710 | .ndo_poll_controller = xgbe_poll_controller, | |
1711 | #endif | |
fca2d994 | 1712 | .ndo_setup_tc = xgbe_setup_tc, |
c5aa9e3b LT |
1713 | .ndo_set_features = xgbe_set_features, |
1714 | }; | |
1715 | ||
1716 | struct net_device_ops *xgbe_get_netdev_ops(void) | |
1717 | { | |
1718 | return (struct net_device_ops *)&xgbe_netdev_ops; | |
1719 | } | |
1720 | ||
9867e8fb LT |
1721 | static void xgbe_rx_refresh(struct xgbe_channel *channel) |
1722 | { | |
1723 | struct xgbe_prv_data *pdata = channel->pdata; | |
270894e7 | 1724 | struct xgbe_hw_if *hw_if = &pdata->hw_if; |
9867e8fb LT |
1725 | struct xgbe_desc_if *desc_if = &pdata->desc_if; |
1726 | struct xgbe_ring *ring = channel->rx_ring; | |
1727 | struct xgbe_ring_data *rdata; | |
1728 | ||
270894e7 LT |
1729 | while (ring->dirty != ring->cur) { |
1730 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); | |
1731 | ||
1732 | /* Reset rdata values */ | |
1733 | desc_if->unmap_rdata(pdata, rdata); | |
1734 | ||
1735 | if (desc_if->map_rx_buffer(pdata, ring, rdata)) | |
1736 | break; | |
1737 | ||
8dee19e6 | 1738 | hw_if->rx_desc_reset(pdata, rdata, ring->dirty); |
270894e7 LT |
1739 | |
1740 | ring->dirty++; | |
1741 | } | |
9867e8fb | 1742 | |
ceb8f6be LT |
1743 | /* Make sure everything is written before the register write */ |
1744 | wmb(); | |
1745 | ||
9867e8fb LT |
1746 | /* Update the Rx Tail Pointer Register with address of |
1747 | * the last cleaned entry */ | |
270894e7 | 1748 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1); |
9867e8fb LT |
1749 | XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO, |
1750 | lower_32_bits(rdata->rdesc_dma)); | |
1751 | } | |
1752 | ||
7d9ca345 LT |
1753 | static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata, |
1754 | struct napi_struct *napi, | |
08dcc47c | 1755 | struct xgbe_ring_data *rdata, |
7d9ca345 | 1756 | unsigned int len) |
08dcc47c | 1757 | { |
08dcc47c LT |
1758 | struct sk_buff *skb; |
1759 | u8 *packet; | |
1760 | unsigned int copy_len; | |
1761 | ||
385565a1 | 1762 | skb = napi_alloc_skb(napi, rdata->rx.hdr.dma_len); |
08dcc47c LT |
1763 | if (!skb) |
1764 | return NULL; | |
1765 | ||
7d9ca345 LT |
1766 | /* Start with the header buffer which may contain just the header |
1767 | * or the header plus data | |
1768 | */ | |
1769 | dma_sync_single_for_cpu(pdata->dev, rdata->rx.hdr.dma, | |
1770 | rdata->rx.hdr.dma_len, DMA_FROM_DEVICE); | |
1771 | ||
c9f140eb LT |
1772 | packet = page_address(rdata->rx.hdr.pa.pages) + |
1773 | rdata->rx.hdr.pa.pages_offset; | |
7d9ca345 | 1774 | copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : len; |
c9f140eb | 1775 | copy_len = min(rdata->rx.hdr.dma_len, copy_len); |
08dcc47c LT |
1776 | skb_copy_to_linear_data(skb, packet, copy_len); |
1777 | skb_put(skb, copy_len); | |
1778 | ||
7d9ca345 LT |
1779 | len -= copy_len; |
1780 | if (len) { | |
1781 | /* Add the remaining data as a frag */ | |
1782 | dma_sync_single_for_cpu(pdata->dev, rdata->rx.buf.dma, | |
1783 | rdata->rx.buf.dma_len, DMA_FROM_DEVICE); | |
1784 | ||
1785 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, | |
1786 | rdata->rx.buf.pa.pages, | |
1787 | rdata->rx.buf.pa.pages_offset, | |
1788 | len, rdata->rx.buf.dma_len); | |
1789 | rdata->rx.buf.pa.pages = NULL; | |
1790 | } | |
08dcc47c LT |
1791 | |
1792 | return skb; | |
1793 | } | |
1794 | ||
c5aa9e3b LT |
1795 | static int xgbe_tx_poll(struct xgbe_channel *channel) |
1796 | { | |
1797 | struct xgbe_prv_data *pdata = channel->pdata; | |
1798 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
1799 | struct xgbe_desc_if *desc_if = &pdata->desc_if; | |
1800 | struct xgbe_ring *ring = channel->tx_ring; | |
1801 | struct xgbe_ring_data *rdata; | |
1802 | struct xgbe_ring_desc *rdesc; | |
1803 | struct net_device *netdev = pdata->netdev; | |
5fb4b86a | 1804 | struct netdev_queue *txq; |
c5aa9e3b | 1805 | int processed = 0; |
5fb4b86a | 1806 | unsigned int tx_packets = 0, tx_bytes = 0; |
c5aa9e3b LT |
1807 | |
1808 | DBGPR("-->xgbe_tx_poll\n"); | |
1809 | ||
1810 | /* Nothing to do if there isn't a Tx ring for this channel */ | |
1811 | if (!ring) | |
1812 | return 0; | |
1813 | ||
5fb4b86a LT |
1814 | txq = netdev_get_tx_queue(netdev, channel->queue_index); |
1815 | ||
d0a8ba6c | 1816 | while ((processed < XGBE_TX_DESC_MAX_PROC) && |
244d62be | 1817 | (ring->dirty != ring->cur)) { |
d0a8ba6c | 1818 | rdata = XGBE_GET_DESC_DATA(ring, ring->dirty); |
c5aa9e3b LT |
1819 | rdesc = rdata->rdesc; |
1820 | ||
1821 | if (!hw_if->tx_complete(rdesc)) | |
1822 | break; | |
1823 | ||
5449e271 LT |
1824 | /* Make sure descriptor fields are read after reading the OWN |
1825 | * bit */ | |
ceb8f6be | 1826 | dma_rmb(); |
5449e271 | 1827 | |
34bf65df LT |
1828 | if (netif_msg_tx_done(pdata)) |
1829 | xgbe_dump_tx_desc(pdata, ring, ring->dirty, 1, 0); | |
c5aa9e3b | 1830 | |
5fb4b86a LT |
1831 | if (hw_if->is_last_desc(rdesc)) { |
1832 | tx_packets += rdata->tx.packets; | |
1833 | tx_bytes += rdata->tx.bytes; | |
1834 | } | |
1835 | ||
c5aa9e3b | 1836 | /* Free the SKB and reset the descriptor for re-use */ |
08dcc47c | 1837 | desc_if->unmap_rdata(pdata, rdata); |
c5aa9e3b LT |
1838 | hw_if->tx_desc_reset(rdata); |
1839 | ||
1840 | processed++; | |
1841 | ring->dirty++; | |
1842 | } | |
1843 | ||
5fb4b86a | 1844 | if (!processed) |
a83ef427 | 1845 | return 0; |
5fb4b86a LT |
1846 | |
1847 | netdev_tx_completed_queue(txq, tx_packets, tx_bytes); | |
1848 | ||
c5aa9e3b | 1849 | if ((ring->tx.queue_stopped == 1) && |
d0a8ba6c | 1850 | (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) { |
c5aa9e3b | 1851 | ring->tx.queue_stopped = 0; |
5fb4b86a | 1852 | netif_tx_wake_queue(txq); |
c5aa9e3b LT |
1853 | } |
1854 | ||
1855 | DBGPR("<--xgbe_tx_poll: processed=%d\n", processed); | |
1856 | ||
c5aa9e3b LT |
1857 | return processed; |
1858 | } | |
1859 | ||
1860 | static int xgbe_rx_poll(struct xgbe_channel *channel, int budget) | |
1861 | { | |
1862 | struct xgbe_prv_data *pdata = channel->pdata; | |
1863 | struct xgbe_hw_if *hw_if = &pdata->hw_if; | |
c5aa9e3b LT |
1864 | struct xgbe_ring *ring = channel->rx_ring; |
1865 | struct xgbe_ring_data *rdata; | |
1866 | struct xgbe_packet_data *packet; | |
1867 | struct net_device *netdev = pdata->netdev; | |
9227dc5e | 1868 | struct napi_struct *napi; |
c5aa9e3b | 1869 | struct sk_buff *skb; |
23e4eef7 LT |
1870 | struct skb_shared_hwtstamps *hwtstamps; |
1871 | unsigned int incomplete, error, context_next, context; | |
7d9ca345 | 1872 | unsigned int len, rdesc_len, max_len; |
55ca6bcd LT |
1873 | unsigned int received = 0; |
1874 | int packet_count = 0; | |
c5aa9e3b LT |
1875 | |
1876 | DBGPR("-->xgbe_rx_poll: budget=%d\n", budget); | |
1877 | ||
1878 | /* Nothing to do if there isn't a Rx ring for this channel */ | |
1879 | if (!ring) | |
1880 | return 0; | |
1881 | ||
7d9ca345 LT |
1882 | incomplete = 0; |
1883 | context_next = 0; | |
1884 | ||
9227dc5e LT |
1885 | napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi; |
1886 | ||
23e4eef7 | 1887 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
c5aa9e3b | 1888 | packet = &ring->packet_data; |
55ca6bcd | 1889 | while (packet_count < budget) { |
c5aa9e3b LT |
1890 | DBGPR(" cur = %d\n", ring->cur); |
1891 | ||
23e4eef7 LT |
1892 | /* First time in loop see if we need to restore state */ |
1893 | if (!received && rdata->state_saved) { | |
23e4eef7 LT |
1894 | skb = rdata->state.skb; |
1895 | error = rdata->state.error; | |
1896 | len = rdata->state.len; | |
1897 | } else { | |
1898 | memset(packet, 0, sizeof(*packet)); | |
23e4eef7 LT |
1899 | skb = NULL; |
1900 | error = 0; | |
1901 | len = 0; | |
1902 | } | |
c5aa9e3b LT |
1903 | |
1904 | read_again: | |
23e4eef7 LT |
1905 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); |
1906 | ||
270894e7 | 1907 | if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3)) |
9867e8fb LT |
1908 | xgbe_rx_refresh(channel); |
1909 | ||
c5aa9e3b LT |
1910 | if (hw_if->dev_read(channel)) |
1911 | break; | |
1912 | ||
1913 | received++; | |
1914 | ring->cur++; | |
c5aa9e3b | 1915 | |
c5aa9e3b LT |
1916 | incomplete = XGMAC_GET_BITS(packet->attributes, |
1917 | RX_PACKET_ATTRIBUTES, | |
1918 | INCOMPLETE); | |
23e4eef7 LT |
1919 | context_next = XGMAC_GET_BITS(packet->attributes, |
1920 | RX_PACKET_ATTRIBUTES, | |
1921 | CONTEXT_NEXT); | |
1922 | context = XGMAC_GET_BITS(packet->attributes, | |
1923 | RX_PACKET_ATTRIBUTES, | |
1924 | CONTEXT); | |
c5aa9e3b LT |
1925 | |
1926 | /* Earlier error, just drain the remaining data */ | |
23e4eef7 | 1927 | if ((incomplete || context_next) && error) |
c5aa9e3b LT |
1928 | goto read_again; |
1929 | ||
1930 | if (error || packet->errors) { | |
1931 | if (packet->errors) | |
34bf65df LT |
1932 | netif_err(pdata, rx_err, netdev, |
1933 | "error in received packet\n"); | |
c5aa9e3b | 1934 | dev_kfree_skb(skb); |
55ca6bcd | 1935 | goto next_packet; |
c5aa9e3b LT |
1936 | } |
1937 | ||
23e4eef7 | 1938 | if (!context) { |
7d9ca345 LT |
1939 | /* Length is cumulative, get this descriptor's length */ |
1940 | rdesc_len = rdata->rx.len - len; | |
1941 | len += rdesc_len; | |
1942 | ||
1943 | if (rdesc_len && !skb) { | |
1944 | skb = xgbe_create_skb(pdata, napi, rdata, | |
1945 | rdesc_len); | |
1946 | if (!skb) | |
08dcc47c | 1947 | error = 1; |
7d9ca345 | 1948 | } else if (rdesc_len) { |
174fd259 | 1949 | dma_sync_single_for_cpu(pdata->dev, |
c9f140eb LT |
1950 | rdata->rx.buf.dma, |
1951 | rdata->rx.buf.dma_len, | |
174fd259 LT |
1952 | DMA_FROM_DEVICE); |
1953 | ||
1954 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, | |
c9f140eb LT |
1955 | rdata->rx.buf.pa.pages, |
1956 | rdata->rx.buf.pa.pages_offset, | |
7d9ca345 LT |
1957 | rdesc_len, |
1958 | rdata->rx.buf.dma_len); | |
c9f140eb | 1959 | rdata->rx.buf.pa.pages = NULL; |
174fd259 | 1960 | } |
c5aa9e3b | 1961 | } |
c5aa9e3b | 1962 | |
23e4eef7 | 1963 | if (incomplete || context_next) |
c5aa9e3b LT |
1964 | goto read_again; |
1965 | ||
23e4eef7 | 1966 | if (!skb) |
55ca6bcd | 1967 | goto next_packet; |
23e4eef7 | 1968 | |
c5aa9e3b LT |
1969 | /* Be sure we don't exceed the configured MTU */ |
1970 | max_len = netdev->mtu + ETH_HLEN; | |
1971 | if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && | |
1972 | (skb->protocol == htons(ETH_P_8021Q))) | |
1973 | max_len += VLAN_HLEN; | |
1974 | ||
1975 | if (skb->len > max_len) { | |
34bf65df LT |
1976 | netif_err(pdata, rx_err, netdev, |
1977 | "packet length exceeds configured MTU\n"); | |
c5aa9e3b | 1978 | dev_kfree_skb(skb); |
55ca6bcd | 1979 | goto next_packet; |
c5aa9e3b LT |
1980 | } |
1981 | ||
34bf65df LT |
1982 | if (netif_msg_pktdata(pdata)) |
1983 | xgbe_print_pkt(netdev, skb, false); | |
c5aa9e3b LT |
1984 | |
1985 | skb_checksum_none_assert(skb); | |
1986 | if (XGMAC_GET_BITS(packet->attributes, | |
1987 | RX_PACKET_ATTRIBUTES, CSUM_DONE)) | |
1988 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1989 | ||
1990 | if (XGMAC_GET_BITS(packet->attributes, | |
1991 | RX_PACKET_ATTRIBUTES, VLAN_CTAG)) | |
1992 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1993 | packet->vlan_ctag); | |
1994 | ||
23e4eef7 LT |
1995 | if (XGMAC_GET_BITS(packet->attributes, |
1996 | RX_PACKET_ATTRIBUTES, RX_TSTAMP)) { | |
1997 | u64 nsec; | |
1998 | ||
1999 | nsec = timecounter_cyc2time(&pdata->tstamp_tc, | |
2000 | packet->rx_tstamp); | |
2001 | hwtstamps = skb_hwtstamps(skb); | |
2002 | hwtstamps->hwtstamp = ns_to_ktime(nsec); | |
2003 | } | |
2004 | ||
5b9dfe29 LT |
2005 | if (XGMAC_GET_BITS(packet->attributes, |
2006 | RX_PACKET_ATTRIBUTES, RSS_HASH)) | |
2007 | skb_set_hash(skb, packet->rss_hash, | |
2008 | packet->rss_hash_type); | |
2009 | ||
c5aa9e3b LT |
2010 | skb->dev = netdev; |
2011 | skb->protocol = eth_type_trans(skb, netdev); | |
2012 | skb_record_rx_queue(skb, channel->queue_index); | |
9227dc5e | 2013 | skb_mark_napi_id(skb, napi); |
c5aa9e3b | 2014 | |
9227dc5e | 2015 | napi_gro_receive(napi, skb); |
55ca6bcd LT |
2016 | |
2017 | next_packet: | |
2018 | packet_count++; | |
c5aa9e3b LT |
2019 | } |
2020 | ||
23e4eef7 LT |
2021 | /* Check if we need to save state before leaving */ |
2022 | if (received && (incomplete || context_next)) { | |
2023 | rdata = XGBE_GET_DESC_DATA(ring, ring->cur); | |
2024 | rdata->state_saved = 1; | |
23e4eef7 LT |
2025 | rdata->state.skb = skb; |
2026 | rdata->state.len = len; | |
2027 | rdata->state.error = error; | |
2028 | } | |
2029 | ||
55ca6bcd | 2030 | DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count); |
c5aa9e3b | 2031 | |
55ca6bcd | 2032 | return packet_count; |
c5aa9e3b LT |
2033 | } |
2034 | ||
9227dc5e LT |
2035 | static int xgbe_one_poll(struct napi_struct *napi, int budget) |
2036 | { | |
2037 | struct xgbe_channel *channel = container_of(napi, struct xgbe_channel, | |
2038 | napi); | |
2039 | int processed = 0; | |
2040 | ||
2041 | DBGPR("-->xgbe_one_poll: budget=%d\n", budget); | |
2042 | ||
2043 | /* Cleanup Tx ring first */ | |
2044 | xgbe_tx_poll(channel); | |
2045 | ||
2046 | /* Process Rx ring next */ | |
2047 | processed = xgbe_rx_poll(channel, budget); | |
2048 | ||
2049 | /* If we processed everything, we are done */ | |
2050 | if (processed < budget) { | |
2051 | /* Turn off polling */ | |
2052 | napi_complete(napi); | |
2053 | ||
2054 | /* Enable Tx and Rx interrupts */ | |
2055 | enable_irq(channel->dma_irq); | |
2056 | } | |
2057 | ||
2058 | DBGPR("<--xgbe_one_poll: received = %d\n", processed); | |
2059 | ||
2060 | return processed; | |
2061 | } | |
2062 | ||
2063 | static int xgbe_all_poll(struct napi_struct *napi, int budget) | |
c5aa9e3b LT |
2064 | { |
2065 | struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data, | |
2066 | napi); | |
2067 | struct xgbe_channel *channel; | |
9867e8fb LT |
2068 | int ring_budget; |
2069 | int processed, last_processed; | |
c5aa9e3b LT |
2070 | unsigned int i; |
2071 | ||
9227dc5e | 2072 | DBGPR("-->xgbe_all_poll: budget=%d\n", budget); |
c5aa9e3b | 2073 | |
c5aa9e3b | 2074 | processed = 0; |
9867e8fb LT |
2075 | ring_budget = budget / pdata->rx_ring_count; |
2076 | do { | |
2077 | last_processed = processed; | |
2078 | ||
2079 | channel = pdata->channel; | |
2080 | for (i = 0; i < pdata->channel_count; i++, channel++) { | |
2081 | /* Cleanup Tx ring first */ | |
2082 | xgbe_tx_poll(channel); | |
2083 | ||
2084 | /* Process Rx ring next */ | |
2085 | if (ring_budget > (budget - processed)) | |
2086 | ring_budget = budget - processed; | |
2087 | processed += xgbe_rx_poll(channel, ring_budget); | |
2088 | } | |
2089 | } while ((processed < budget) && (processed != last_processed)); | |
c5aa9e3b LT |
2090 | |
2091 | /* If we processed everything, we are done */ | |
2092 | if (processed < budget) { | |
2093 | /* Turn off polling */ | |
2094 | napi_complete(napi); | |
2095 | ||
2096 | /* Enable Tx and Rx interrupts */ | |
2097 | xgbe_enable_rx_tx_ints(pdata); | |
2098 | } | |
2099 | ||
9227dc5e | 2100 | DBGPR("<--xgbe_all_poll: received = %d\n", processed); |
c5aa9e3b LT |
2101 | |
2102 | return processed; | |
2103 | } | |
2104 | ||
34bf65df LT |
2105 | void xgbe_dump_tx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, |
2106 | unsigned int idx, unsigned int count, unsigned int flag) | |
c5aa9e3b LT |
2107 | { |
2108 | struct xgbe_ring_data *rdata; | |
2109 | struct xgbe_ring_desc *rdesc; | |
2110 | ||
2111 | while (count--) { | |
d0a8ba6c | 2112 | rdata = XGBE_GET_DESC_DATA(ring, idx); |
c5aa9e3b | 2113 | rdesc = rdata->rdesc; |
34bf65df LT |
2114 | netdev_dbg(pdata->netdev, |
2115 | "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, | |
2116 | (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", | |
2117 | le32_to_cpu(rdesc->desc0), | |
2118 | le32_to_cpu(rdesc->desc1), | |
2119 | le32_to_cpu(rdesc->desc2), | |
2120 | le32_to_cpu(rdesc->desc3)); | |
c5aa9e3b LT |
2121 | idx++; |
2122 | } | |
2123 | } | |
2124 | ||
34bf65df | 2125 | void xgbe_dump_rx_desc(struct xgbe_prv_data *pdata, struct xgbe_ring *ring, |
c5aa9e3b LT |
2126 | unsigned int idx) |
2127 | { | |
34bf65df LT |
2128 | struct xgbe_ring_data *rdata; |
2129 | struct xgbe_ring_desc *rdesc; | |
2130 | ||
2131 | rdata = XGBE_GET_DESC_DATA(ring, idx); | |
2132 | rdesc = rdata->rdesc; | |
2133 | netdev_dbg(pdata->netdev, | |
2134 | "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", | |
2135 | idx, le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1), | |
2136 | le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3)); | |
c5aa9e3b LT |
2137 | } |
2138 | ||
2139 | void xgbe_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx) | |
2140 | { | |
2141 | struct ethhdr *eth = (struct ethhdr *)skb->data; | |
2142 | unsigned char *buf = skb->data; | |
2143 | unsigned char buffer[128]; | |
2144 | unsigned int i, j; | |
2145 | ||
34bf65df | 2146 | netdev_dbg(netdev, "\n************** SKB dump ****************\n"); |
c5aa9e3b | 2147 | |
34bf65df LT |
2148 | netdev_dbg(netdev, "%s packet of %d bytes\n", |
2149 | (tx_rx ? "TX" : "RX"), skb->len); | |
c5aa9e3b | 2150 | |
34bf65df LT |
2151 | netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); |
2152 | netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); | |
2153 | netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); | |
c5aa9e3b LT |
2154 | |
2155 | for (i = 0, j = 0; i < skb->len;) { | |
2156 | j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", | |
2157 | buf[i++]); | |
2158 | ||
2159 | if ((i % 32) == 0) { | |
34bf65df | 2160 | netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer); |
c5aa9e3b LT |
2161 | j = 0; |
2162 | } else if ((i % 16) == 0) { | |
2163 | buffer[j++] = ' '; | |
2164 | buffer[j++] = ' '; | |
2165 | } else if ((i % 4) == 0) { | |
2166 | buffer[j++] = ' '; | |
2167 | } | |
2168 | } | |
2169 | if (i % 32) | |
34bf65df | 2170 | netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer); |
c5aa9e3b | 2171 | |
34bf65df | 2172 | netdev_dbg(netdev, "\n************** SKB dump ****************\n"); |
c5aa9e3b | 2173 | } |