Commit | Line | Data |
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452c1ce2 CS |
1 | /* |
2 | * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved. | |
3 | * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com> | |
4 | * | |
5 | * Derived from Intel e1000 driver | |
6 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the Free | |
10 | * Software Foundation; either version 2 of the License, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
14 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
16 | * more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along with | |
19 | * this program; if not, write to the Free Software Foundation, Inc., 59 | |
20 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
21 | */ | |
22 | ||
60063497 | 23 | #include <linux/atomic.h> |
452c1ce2 CS |
24 | #include <linux/crc32.h> |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/ethtool.h> | |
28 | #include <linux/hardirq.h> | |
29 | #include <linux/if_vlan.h> | |
30 | #include <linux/in.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/ip.h> | |
33 | #include <linux/irqflags.h> | |
34 | #include <linux/irqreturn.h> | |
35 | #include <linux/mii.h> | |
36 | #include <linux/net.h> | |
37 | #include <linux/netdevice.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/pci_ids.h> | |
40 | #include <linux/pm.h> | |
41 | #include <linux/skbuff.h> | |
5a0e3ad6 | 42 | #include <linux/slab.h> |
452c1ce2 CS |
43 | #include <linux/spinlock.h> |
44 | #include <linux/string.h> | |
45 | #include <linux/tcp.h> | |
46 | #include <linux/timer.h> | |
47 | #include <linux/types.h> | |
48 | #include <linux/workqueue.h> | |
49 | ||
50 | #include "atl2.h" | |
51 | ||
52 | #define ATL2_DRV_VERSION "2.2.3" | |
53 | ||
f27e21a8 | 54 | static const char atl2_driver_name[] = "atl2"; |
452c1ce2 | 55 | static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver"; |
f27e21a8 SH |
56 | static const char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation."; |
57 | static const char atl2_driver_version[] = ATL2_DRV_VERSION; | |
dffe278f | 58 | static const struct ethtool_ops atl2_ethtool_ops; |
452c1ce2 CS |
59 | |
60 | MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>"); | |
61 | MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver"); | |
62 | MODULE_LICENSE("GPL"); | |
63 | MODULE_VERSION(ATL2_DRV_VERSION); | |
64 | ||
65 | /* | |
66 | * atl2_pci_tbl - PCI Device ID Table | |
67 | */ | |
9baa3c34 | 68 | static const struct pci_device_id atl2_pci_tbl[] = { |
452c1ce2 CS |
69 | {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)}, |
70 | /* required last entry */ | |
71 | {0,} | |
72 | }; | |
73 | MODULE_DEVICE_TABLE(pci, atl2_pci_tbl); | |
74 | ||
452c1ce2 CS |
75 | static void atl2_check_options(struct atl2_adapter *adapter); |
76 | ||
49ce9c2c | 77 | /** |
452c1ce2 CS |
78 | * atl2_sw_init - Initialize general software structures (struct atl2_adapter) |
79 | * @adapter: board private structure to initialize | |
80 | * | |
81 | * atl2_sw_init initializes the Adapter private data structure. | |
82 | * Fields are initialized based on PCI device information and | |
83 | * OS network device settings (MTU size). | |
84 | */ | |
093d369d | 85 | static int atl2_sw_init(struct atl2_adapter *adapter) |
452c1ce2 CS |
86 | { |
87 | struct atl2_hw *hw = &adapter->hw; | |
88 | struct pci_dev *pdev = adapter->pdev; | |
89 | ||
90 | /* PCI config space info */ | |
91 | hw->vendor_id = pdev->vendor; | |
92 | hw->device_id = pdev->device; | |
93 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
94 | hw->subsystem_id = pdev->subsystem_device; | |
ff938e43 | 95 | hw->revision_id = pdev->revision; |
452c1ce2 | 96 | |
452c1ce2 CS |
97 | pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word); |
98 | ||
99 | adapter->wol = 0; | |
100 | adapter->ict = 50000; /* ~100ms */ | |
101 | adapter->link_speed = SPEED_0; /* hardware init */ | |
102 | adapter->link_duplex = FULL_DUPLEX; | |
103 | ||
104 | hw->phy_configured = false; | |
105 | hw->preamble_len = 7; | |
106 | hw->ipgt = 0x60; | |
107 | hw->min_ifg = 0x50; | |
108 | hw->ipgr1 = 0x40; | |
109 | hw->ipgr2 = 0x60; | |
110 | hw->retry_buf = 2; | |
111 | hw->max_retry = 0xf; | |
112 | hw->lcol = 0x37; | |
113 | hw->jam_ipg = 7; | |
114 | hw->fc_rxd_hi = 0; | |
115 | hw->fc_rxd_lo = 0; | |
116 | hw->max_frame_size = adapter->netdev->mtu; | |
117 | ||
118 | spin_lock_init(&adapter->stats_lock); | |
452c1ce2 CS |
119 | |
120 | set_bit(__ATL2_DOWN, &adapter->flags); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
49ce9c2c | 125 | /** |
452c1ce2 CS |
126 | * atl2_set_multi - Multicast and Promiscuous mode set |
127 | * @netdev: network interface device structure | |
128 | * | |
129 | * The set_multi entry point is called whenever the multicast address | |
130 | * list or the network interface flags are updated. This routine is | |
131 | * responsible for configuring the hardware for proper multicast, | |
132 | * promiscuous mode, and all-multi behavior. | |
133 | */ | |
134 | static void atl2_set_multi(struct net_device *netdev) | |
135 | { | |
136 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
137 | struct atl2_hw *hw = &adapter->hw; | |
22bedad3 | 138 | struct netdev_hw_addr *ha; |
452c1ce2 CS |
139 | u32 rctl; |
140 | u32 hash_value; | |
141 | ||
142 | /* Check for Promiscuous and All Multicast modes */ | |
143 | rctl = ATL2_READ_REG(hw, REG_MAC_CTRL); | |
144 | ||
145 | if (netdev->flags & IFF_PROMISC) { | |
146 | rctl |= MAC_CTRL_PROMIS_EN; | |
147 | } else if (netdev->flags & IFF_ALLMULTI) { | |
148 | rctl |= MAC_CTRL_MC_ALL_EN; | |
149 | rctl &= ~MAC_CTRL_PROMIS_EN; | |
150 | } else | |
151 | rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN); | |
152 | ||
153 | ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl); | |
154 | ||
155 | /* clear the old settings from the multicast hash table */ | |
156 | ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); | |
157 | ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); | |
158 | ||
159 | /* comoute mc addresses' hash value ,and put it into hash table */ | |
22bedad3 JP |
160 | netdev_for_each_mc_addr(ha, netdev) { |
161 | hash_value = atl2_hash_mc_addr(hw, ha->addr); | |
452c1ce2 CS |
162 | atl2_hash_set(hw, hash_value); |
163 | } | |
164 | } | |
165 | ||
166 | static void init_ring_ptrs(struct atl2_adapter *adapter) | |
167 | { | |
168 | /* Read / Write Ptr Initialize: */ | |
169 | adapter->txd_write_ptr = 0; | |
170 | atomic_set(&adapter->txd_read_ptr, 0); | |
171 | ||
172 | adapter->rxd_read_ptr = 0; | |
173 | adapter->rxd_write_ptr = 0; | |
174 | ||
175 | atomic_set(&adapter->txs_write_ptr, 0); | |
176 | adapter->txs_next_clear = 0; | |
177 | } | |
178 | ||
49ce9c2c | 179 | /** |
452c1ce2 CS |
180 | * atl2_configure - Configure Transmit&Receive Unit after Reset |
181 | * @adapter: board private structure | |
182 | * | |
183 | * Configure the Tx /Rx unit of the MAC after a reset. | |
184 | */ | |
185 | static int atl2_configure(struct atl2_adapter *adapter) | |
186 | { | |
187 | struct atl2_hw *hw = &adapter->hw; | |
188 | u32 value; | |
189 | ||
190 | /* clear interrupt status */ | |
191 | ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff); | |
192 | ||
193 | /* set MAC Address */ | |
194 | value = (((u32)hw->mac_addr[2]) << 24) | | |
195 | (((u32)hw->mac_addr[3]) << 16) | | |
196 | (((u32)hw->mac_addr[4]) << 8) | | |
197 | (((u32)hw->mac_addr[5])); | |
198 | ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value); | |
199 | value = (((u32)hw->mac_addr[0]) << 8) | | |
200 | (((u32)hw->mac_addr[1])); | |
201 | ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value); | |
202 | ||
203 | /* HI base address */ | |
204 | ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, | |
205 | (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32)); | |
206 | ||
207 | /* LO base address */ | |
208 | ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO, | |
209 | (u32)(adapter->txd_dma & 0x00000000ffffffffULL)); | |
210 | ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO, | |
211 | (u32)(adapter->txs_dma & 0x00000000ffffffffULL)); | |
212 | ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO, | |
213 | (u32)(adapter->rxd_dma & 0x00000000ffffffffULL)); | |
214 | ||
215 | /* element count */ | |
216 | ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4)); | |
217 | ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size); | |
218 | ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size); | |
219 | ||
220 | /* config Internal SRAM */ | |
221 | /* | |
222 | ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end); | |
223 | ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end); | |
224 | */ | |
225 | ||
226 | /* config IPG/IFG */ | |
227 | value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) << | |
228 | MAC_IPG_IFG_IPGT_SHIFT) | | |
229 | (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) << | |
230 | MAC_IPG_IFG_MIFG_SHIFT) | | |
231 | (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) << | |
232 | MAC_IPG_IFG_IPGR1_SHIFT)| | |
233 | (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) << | |
234 | MAC_IPG_IFG_IPGR2_SHIFT); | |
235 | ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value); | |
236 | ||
237 | /* config Half-Duplex Control */ | |
238 | value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | | |
239 | (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) << | |
240 | MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) | | |
241 | MAC_HALF_DUPLX_CTRL_EXC_DEF_EN | | |
242 | (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) | | |
243 | (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) << | |
244 | MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT); | |
245 | ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value); | |
246 | ||
247 | /* set Interrupt Moderator Timer */ | |
248 | ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt); | |
249 | ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN); | |
250 | ||
251 | /* set Interrupt Clear Timer */ | |
252 | ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict); | |
253 | ||
254 | /* set MTU */ | |
255 | ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu + | |
256 | ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE); | |
257 | ||
258 | /* 1590 */ | |
259 | ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177); | |
260 | ||
261 | /* flow control */ | |
262 | ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi); | |
263 | ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo); | |
264 | ||
265 | /* Init mailbox */ | |
266 | ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr); | |
267 | ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr); | |
268 | ||
269 | /* enable DMA read/write */ | |
270 | ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN); | |
271 | ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN); | |
272 | ||
273 | value = ATL2_READ_REG(&adapter->hw, REG_ISR); | |
274 | if ((value & ISR_PHY_LINKDOWN) != 0) | |
275 | value = 1; /* config failed */ | |
276 | else | |
277 | value = 0; | |
278 | ||
279 | /* clear all interrupt status */ | |
280 | ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff); | |
281 | ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); | |
282 | return value; | |
283 | } | |
284 | ||
49ce9c2c | 285 | /** |
452c1ce2 CS |
286 | * atl2_setup_ring_resources - allocate Tx / RX descriptor resources |
287 | * @adapter: board private structure | |
288 | * | |
289 | * Return 0 on success, negative on failure | |
290 | */ | |
291 | static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter) | |
292 | { | |
293 | struct pci_dev *pdev = adapter->pdev; | |
294 | int size; | |
295 | u8 offset = 0; | |
296 | ||
297 | /* real ring DMA buffer */ | |
298 | adapter->ring_size = size = | |
299 | adapter->txd_ring_size * 1 + 7 + /* dword align */ | |
300 | adapter->txs_ring_size * 4 + 7 + /* dword align */ | |
301 | adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */ | |
302 | ||
303 | adapter->ring_vir_addr = pci_alloc_consistent(pdev, size, | |
304 | &adapter->ring_dma); | |
305 | if (!adapter->ring_vir_addr) | |
306 | return -ENOMEM; | |
307 | memset(adapter->ring_vir_addr, 0, adapter->ring_size); | |
308 | ||
309 | /* Init TXD Ring */ | |
310 | adapter->txd_dma = adapter->ring_dma ; | |
311 | offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0; | |
312 | adapter->txd_dma += offset; | |
43d620c8 | 313 | adapter->txd_ring = adapter->ring_vir_addr + offset; |
452c1ce2 CS |
314 | |
315 | /* Init TXS Ring */ | |
316 | adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size; | |
317 | offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0; | |
318 | adapter->txs_dma += offset; | |
319 | adapter->txs_ring = (struct tx_pkt_status *) | |
320 | (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset)); | |
321 | ||
322 | /* Init RXD Ring */ | |
323 | adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4; | |
324 | offset = (adapter->rxd_dma & 127) ? | |
325 | (128 - (adapter->rxd_dma & 127)) : 0; | |
326 | if (offset > 7) | |
327 | offset -= 8; | |
328 | else | |
329 | offset += (128 - 8); | |
330 | ||
331 | adapter->rxd_dma += offset; | |
332 | adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) + | |
333 | (adapter->txs_ring_size * 4 + offset)); | |
334 | ||
335 | /* | |
336 | * Read / Write Ptr Initialize: | |
337 | * init_ring_ptrs(adapter); | |
338 | */ | |
339 | return 0; | |
340 | } | |
341 | ||
49ce9c2c | 342 | /** |
452c1ce2 CS |
343 | * atl2_irq_enable - Enable default interrupt generation settings |
344 | * @adapter: board private structure | |
345 | */ | |
346 | static inline void atl2_irq_enable(struct atl2_adapter *adapter) | |
347 | { | |
348 | ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK); | |
349 | ATL2_WRITE_FLUSH(&adapter->hw); | |
350 | } | |
351 | ||
49ce9c2c | 352 | /** |
452c1ce2 CS |
353 | * atl2_irq_disable - Mask off interrupt generation on the NIC |
354 | * @adapter: board private structure | |
355 | */ | |
356 | static inline void atl2_irq_disable(struct atl2_adapter *adapter) | |
357 | { | |
358 | ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0); | |
359 | ATL2_WRITE_FLUSH(&adapter->hw); | |
360 | synchronize_irq(adapter->pdev->irq); | |
361 | } | |
362 | ||
c8f44aff | 363 | static void __atl2_vlan_mode(netdev_features_t features, u32 *ctrl) |
dc437974 | 364 | { |
f646968f | 365 | if (features & NETIF_F_HW_VLAN_CTAG_RX) { |
dc437974 JP |
366 | /* enable VLAN tag insert/strip */ |
367 | *ctrl |= MAC_CTRL_RMV_VLAN; | |
368 | } else { | |
369 | /* disable VLAN tag insert/strip */ | |
370 | *ctrl &= ~MAC_CTRL_RMV_VLAN; | |
371 | } | |
372 | } | |
373 | ||
c8f44aff MM |
374 | static void atl2_vlan_mode(struct net_device *netdev, |
375 | netdev_features_t features) | |
452c1ce2 CS |
376 | { |
377 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
378 | u32 ctrl; | |
379 | ||
380 | atl2_irq_disable(adapter); | |
452c1ce2 | 381 | |
dc437974 JP |
382 | ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL); |
383 | __atl2_vlan_mode(features, &ctrl); | |
384 | ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl); | |
452c1ce2 CS |
385 | |
386 | atl2_irq_enable(adapter); | |
387 | } | |
388 | ||
389 | static void atl2_restore_vlan(struct atl2_adapter *adapter) | |
390 | { | |
dc437974 JP |
391 | atl2_vlan_mode(adapter->netdev, adapter->netdev->features); |
392 | } | |
393 | ||
c8f44aff MM |
394 | static netdev_features_t atl2_fix_features(struct net_device *netdev, |
395 | netdev_features_t features) | |
dc437974 JP |
396 | { |
397 | /* | |
398 | * Since there is no support for separate rx/tx vlan accel | |
399 | * enable/disable make sure tx flag is always in same state as rx. | |
400 | */ | |
f646968f PM |
401 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
402 | features |= NETIF_F_HW_VLAN_CTAG_TX; | |
dc437974 | 403 | else |
f646968f | 404 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; |
dc437974 JP |
405 | |
406 | return features; | |
407 | } | |
408 | ||
c8f44aff MM |
409 | static int atl2_set_features(struct net_device *netdev, |
410 | netdev_features_t features) | |
dc437974 | 411 | { |
c8f44aff | 412 | netdev_features_t changed = netdev->features ^ features; |
dc437974 | 413 | |
f646968f | 414 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) |
dc437974 JP |
415 | atl2_vlan_mode(netdev, features); |
416 | ||
417 | return 0; | |
452c1ce2 | 418 | } |
452c1ce2 CS |
419 | |
420 | static void atl2_intr_rx(struct atl2_adapter *adapter) | |
421 | { | |
422 | struct net_device *netdev = adapter->netdev; | |
423 | struct rx_desc *rxd; | |
424 | struct sk_buff *skb; | |
425 | ||
426 | do { | |
427 | rxd = adapter->rxd_ring+adapter->rxd_write_ptr; | |
428 | if (!rxd->status.update) | |
429 | break; /* end of tx */ | |
430 | ||
431 | /* clear this flag at once */ | |
432 | rxd->status.update = 0; | |
433 | ||
434 | if (rxd->status.ok && rxd->status.pkt_size >= 60) { | |
435 | int rx_size = (int)(rxd->status.pkt_size - 4); | |
436 | /* alloc new buffer */ | |
89d71a66 | 437 | skb = netdev_alloc_skb_ip_align(netdev, rx_size); |
452c1ce2 | 438 | if (NULL == skb) { |
452c1ce2 CS |
439 | /* |
440 | * Check that some rx space is free. If not, | |
441 | * free one and mark stats->rx_dropped++. | |
442 | */ | |
02e71731 | 443 | netdev->stats.rx_dropped++; |
452c1ce2 CS |
444 | break; |
445 | } | |
452c1ce2 CS |
446 | memcpy(skb->data, rxd->packet, rx_size); |
447 | skb_put(skb, rx_size); | |
448 | skb->protocol = eth_type_trans(skb, netdev); | |
dc437974 | 449 | if (rxd->status.vlan) { |
452c1ce2 CS |
450 | u16 vlan_tag = (rxd->status.vtag>>4) | |
451 | ((rxd->status.vtag&7) << 13) | | |
452 | ((rxd->status.vtag&8) << 9); | |
dc437974 | 453 | |
86a9bad3 | 454 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); |
dc437974 | 455 | } |
452c1ce2 | 456 | netif_rx(skb); |
02e71731 SH |
457 | netdev->stats.rx_bytes += rx_size; |
458 | netdev->stats.rx_packets++; | |
452c1ce2 | 459 | } else { |
02e71731 | 460 | netdev->stats.rx_errors++; |
452c1ce2 CS |
461 | |
462 | if (rxd->status.ok && rxd->status.pkt_size <= 60) | |
02e71731 | 463 | netdev->stats.rx_length_errors++; |
452c1ce2 | 464 | if (rxd->status.mcast) |
02e71731 | 465 | netdev->stats.multicast++; |
452c1ce2 | 466 | if (rxd->status.crc) |
02e71731 | 467 | netdev->stats.rx_crc_errors++; |
452c1ce2 | 468 | if (rxd->status.align) |
02e71731 | 469 | netdev->stats.rx_frame_errors++; |
452c1ce2 CS |
470 | } |
471 | ||
472 | /* advance write ptr */ | |
473 | if (++adapter->rxd_write_ptr == adapter->rxd_ring_size) | |
474 | adapter->rxd_write_ptr = 0; | |
475 | } while (1); | |
476 | ||
477 | /* update mailbox? */ | |
478 | adapter->rxd_read_ptr = adapter->rxd_write_ptr; | |
479 | ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr); | |
480 | } | |
481 | ||
482 | static void atl2_intr_tx(struct atl2_adapter *adapter) | |
483 | { | |
02e71731 | 484 | struct net_device *netdev = adapter->netdev; |
452c1ce2 CS |
485 | u32 txd_read_ptr; |
486 | u32 txs_write_ptr; | |
487 | struct tx_pkt_status *txs; | |
488 | struct tx_pkt_header *txph; | |
489 | int free_hole = 0; | |
490 | ||
491 | do { | |
492 | txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); | |
493 | txs = adapter->txs_ring + txs_write_ptr; | |
494 | if (!txs->update) | |
495 | break; /* tx stop here */ | |
496 | ||
497 | free_hole = 1; | |
498 | txs->update = 0; | |
499 | ||
500 | if (++txs_write_ptr == adapter->txs_ring_size) | |
501 | txs_write_ptr = 0; | |
502 | atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr); | |
503 | ||
504 | txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr); | |
505 | txph = (struct tx_pkt_header *) | |
506 | (((u8 *)adapter->txd_ring) + txd_read_ptr); | |
507 | ||
508 | if (txph->pkt_size != txs->pkt_size) { | |
509 | struct tx_pkt_status *old_txs = txs; | |
510 | printk(KERN_WARNING | |
511 | "%s: txs packet size not consistent with txd" | |
512 | " txd_:0x%08x, txs_:0x%08x!\n", | |
513 | adapter->netdev->name, | |
514 | *(u32 *)txph, *(u32 *)txs); | |
515 | printk(KERN_WARNING | |
516 | "txd read ptr: 0x%x\n", | |
517 | txd_read_ptr); | |
518 | txs = adapter->txs_ring + txs_write_ptr; | |
519 | printk(KERN_WARNING | |
520 | "txs-behind:0x%08x\n", | |
521 | *(u32 *)txs); | |
522 | if (txs_write_ptr < 2) { | |
523 | txs = adapter->txs_ring + | |
524 | (adapter->txs_ring_size + | |
525 | txs_write_ptr - 2); | |
526 | } else { | |
527 | txs = adapter->txs_ring + (txs_write_ptr - 2); | |
528 | } | |
529 | printk(KERN_WARNING | |
530 | "txs-before:0x%08x\n", | |
531 | *(u32 *)txs); | |
532 | txs = old_txs; | |
533 | } | |
534 | ||
535 | /* 4for TPH */ | |
536 | txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3); | |
537 | if (txd_read_ptr >= adapter->txd_ring_size) | |
538 | txd_read_ptr -= adapter->txd_ring_size; | |
539 | ||
540 | atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr); | |
541 | ||
542 | /* tx statistics: */ | |
e2f092ff | 543 | if (txs->ok) { |
02e71731 SH |
544 | netdev->stats.tx_bytes += txs->pkt_size; |
545 | netdev->stats.tx_packets++; | |
e2f092ff | 546 | } |
452c1ce2 | 547 | else |
02e71731 | 548 | netdev->stats.tx_errors++; |
452c1ce2 CS |
549 | |
550 | if (txs->defer) | |
02e71731 | 551 | netdev->stats.collisions++; |
452c1ce2 | 552 | if (txs->abort_col) |
02e71731 | 553 | netdev->stats.tx_aborted_errors++; |
452c1ce2 | 554 | if (txs->late_col) |
02e71731 | 555 | netdev->stats.tx_window_errors++; |
452c1ce2 | 556 | if (txs->underun) |
02e71731 | 557 | netdev->stats.tx_fifo_errors++; |
452c1ce2 CS |
558 | } while (1); |
559 | ||
560 | if (free_hole) { | |
561 | if (netif_queue_stopped(adapter->netdev) && | |
562 | netif_carrier_ok(adapter->netdev)) | |
563 | netif_wake_queue(adapter->netdev); | |
564 | } | |
565 | } | |
566 | ||
567 | static void atl2_check_for_link(struct atl2_adapter *adapter) | |
568 | { | |
569 | struct net_device *netdev = adapter->netdev; | |
570 | u16 phy_data = 0; | |
571 | ||
572 | spin_lock(&adapter->stats_lock); | |
573 | atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); | |
574 | atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data); | |
575 | spin_unlock(&adapter->stats_lock); | |
576 | ||
577 | /* notify upper layer link down ASAP */ | |
578 | if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */ | |
579 | if (netif_carrier_ok(netdev)) { /* old link state: Up */ | |
580 | printk(KERN_INFO "%s: %s NIC Link is Down\n", | |
581 | atl2_driver_name, netdev->name); | |
582 | adapter->link_speed = SPEED_0; | |
583 | netif_carrier_off(netdev); | |
584 | netif_stop_queue(netdev); | |
585 | } | |
586 | } | |
587 | schedule_work(&adapter->link_chg_task); | |
588 | } | |
589 | ||
590 | static inline void atl2_clear_phy_int(struct atl2_adapter *adapter) | |
591 | { | |
592 | u16 phy_data; | |
593 | spin_lock(&adapter->stats_lock); | |
594 | atl2_read_phy_reg(&adapter->hw, 19, &phy_data); | |
595 | spin_unlock(&adapter->stats_lock); | |
596 | } | |
597 | ||
49ce9c2c | 598 | /** |
452c1ce2 CS |
599 | * atl2_intr - Interrupt Handler |
600 | * @irq: interrupt number | |
601 | * @data: pointer to a network interface device structure | |
452c1ce2 CS |
602 | */ |
603 | static irqreturn_t atl2_intr(int irq, void *data) | |
604 | { | |
605 | struct atl2_adapter *adapter = netdev_priv(data); | |
606 | struct atl2_hw *hw = &adapter->hw; | |
607 | u32 status; | |
608 | ||
609 | status = ATL2_READ_REG(hw, REG_ISR); | |
610 | if (0 == status) | |
611 | return IRQ_NONE; | |
612 | ||
613 | /* link event */ | |
614 | if (status & ISR_PHY) | |
615 | atl2_clear_phy_int(adapter); | |
616 | ||
617 | /* clear ISR status, and Enable CMB DMA/Disable Interrupt */ | |
618 | ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT); | |
619 | ||
620 | /* check if PCIE PHY Link down */ | |
621 | if (status & ISR_PHY_LINKDOWN) { | |
622 | if (netif_running(adapter->netdev)) { /* reset MAC */ | |
623 | ATL2_WRITE_REG(hw, REG_ISR, 0); | |
624 | ATL2_WRITE_REG(hw, REG_IMR, 0); | |
625 | ATL2_WRITE_FLUSH(hw); | |
626 | schedule_work(&adapter->reset_task); | |
627 | return IRQ_HANDLED; | |
628 | } | |
629 | } | |
630 | ||
631 | /* check if DMA read/write error? */ | |
632 | if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) { | |
633 | ATL2_WRITE_REG(hw, REG_ISR, 0); | |
634 | ATL2_WRITE_REG(hw, REG_IMR, 0); | |
635 | ATL2_WRITE_FLUSH(hw); | |
636 | schedule_work(&adapter->reset_task); | |
637 | return IRQ_HANDLED; | |
638 | } | |
639 | ||
640 | /* link event */ | |
641 | if (status & (ISR_PHY | ISR_MANUAL)) { | |
02e71731 | 642 | adapter->netdev->stats.tx_carrier_errors++; |
452c1ce2 CS |
643 | atl2_check_for_link(adapter); |
644 | } | |
645 | ||
646 | /* transmit event */ | |
647 | if (status & ISR_TX_EVENT) | |
648 | atl2_intr_tx(adapter); | |
649 | ||
650 | /* rx exception */ | |
651 | if (status & ISR_RX_EVENT) | |
652 | atl2_intr_rx(adapter); | |
653 | ||
654 | /* re-enable Interrupt */ | |
655 | ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0); | |
656 | return IRQ_HANDLED; | |
657 | } | |
658 | ||
659 | static int atl2_request_irq(struct atl2_adapter *adapter) | |
660 | { | |
661 | struct net_device *netdev = adapter->netdev; | |
662 | int flags, err = 0; | |
663 | ||
664 | flags = IRQF_SHARED; | |
452c1ce2 CS |
665 | adapter->have_msi = true; |
666 | err = pci_enable_msi(adapter->pdev); | |
667 | if (err) | |
668 | adapter->have_msi = false; | |
669 | ||
670 | if (adapter->have_msi) | |
671 | flags &= ~IRQF_SHARED; | |
452c1ce2 | 672 | |
a0607fd3 | 673 | return request_irq(adapter->pdev->irq, atl2_intr, flags, netdev->name, |
452c1ce2 CS |
674 | netdev); |
675 | } | |
676 | ||
49ce9c2c | 677 | /** |
452c1ce2 CS |
678 | * atl2_free_ring_resources - Free Tx / RX descriptor Resources |
679 | * @adapter: board private structure | |
680 | * | |
681 | * Free all transmit software resources | |
682 | */ | |
683 | static void atl2_free_ring_resources(struct atl2_adapter *adapter) | |
684 | { | |
685 | struct pci_dev *pdev = adapter->pdev; | |
686 | pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr, | |
687 | adapter->ring_dma); | |
688 | } | |
689 | ||
49ce9c2c | 690 | /** |
452c1ce2 CS |
691 | * atl2_open - Called when a network interface is made active |
692 | * @netdev: network interface device structure | |
693 | * | |
694 | * Returns 0 on success, negative value on failure | |
695 | * | |
696 | * The open entry point is called when a network interface is made | |
697 | * active by the system (IFF_UP). At this point all resources needed | |
698 | * for transmit and receive operations are allocated, the interrupt | |
699 | * handler is registered with the OS, the watchdog timer is started, | |
700 | * and the stack is notified that the interface is ready. | |
701 | */ | |
702 | static int atl2_open(struct net_device *netdev) | |
703 | { | |
704 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
705 | int err; | |
706 | u32 val; | |
707 | ||
708 | /* disallow open during test */ | |
709 | if (test_bit(__ATL2_TESTING, &adapter->flags)) | |
710 | return -EBUSY; | |
711 | ||
712 | /* allocate transmit descriptors */ | |
713 | err = atl2_setup_ring_resources(adapter); | |
714 | if (err) | |
715 | return err; | |
716 | ||
717 | err = atl2_init_hw(&adapter->hw); | |
718 | if (err) { | |
719 | err = -EIO; | |
720 | goto err_init_hw; | |
721 | } | |
722 | ||
723 | /* hardware has been reset, we need to reload some things */ | |
724 | atl2_set_multi(netdev); | |
725 | init_ring_ptrs(adapter); | |
726 | ||
452c1ce2 | 727 | atl2_restore_vlan(adapter); |
452c1ce2 CS |
728 | |
729 | if (atl2_configure(adapter)) { | |
730 | err = -EIO; | |
731 | goto err_config; | |
732 | } | |
733 | ||
734 | err = atl2_request_irq(adapter); | |
735 | if (err) | |
736 | goto err_req_irq; | |
737 | ||
738 | clear_bit(__ATL2_DOWN, &adapter->flags); | |
739 | ||
e053b628 | 740 | mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 4*HZ)); |
452c1ce2 CS |
741 | |
742 | val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); | |
743 | ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, | |
744 | val | MASTER_CTRL_MANUAL_INT); | |
745 | ||
746 | atl2_irq_enable(adapter); | |
747 | ||
748 | return 0; | |
749 | ||
750 | err_init_hw: | |
751 | err_req_irq: | |
752 | err_config: | |
753 | atl2_free_ring_resources(adapter); | |
754 | atl2_reset_hw(&adapter->hw); | |
755 | ||
756 | return err; | |
757 | } | |
758 | ||
759 | static void atl2_down(struct atl2_adapter *adapter) | |
760 | { | |
761 | struct net_device *netdev = adapter->netdev; | |
762 | ||
763 | /* signal that we're down so the interrupt handler does not | |
764 | * reschedule our watchdog timer */ | |
765 | set_bit(__ATL2_DOWN, &adapter->flags); | |
766 | ||
452c1ce2 | 767 | netif_tx_disable(netdev); |
452c1ce2 CS |
768 | |
769 | /* reset MAC to disable all RX/TX */ | |
770 | atl2_reset_hw(&adapter->hw); | |
771 | msleep(1); | |
772 | ||
773 | atl2_irq_disable(adapter); | |
774 | ||
775 | del_timer_sync(&adapter->watchdog_timer); | |
776 | del_timer_sync(&adapter->phy_config_timer); | |
777 | clear_bit(0, &adapter->cfg_phy); | |
778 | ||
779 | netif_carrier_off(netdev); | |
780 | adapter->link_speed = SPEED_0; | |
781 | adapter->link_duplex = -1; | |
782 | } | |
783 | ||
784 | static void atl2_free_irq(struct atl2_adapter *adapter) | |
785 | { | |
786 | struct net_device *netdev = adapter->netdev; | |
787 | ||
788 | free_irq(adapter->pdev->irq, netdev); | |
789 | ||
790 | #ifdef CONFIG_PCI_MSI | |
791 | if (adapter->have_msi) | |
792 | pci_disable_msi(adapter->pdev); | |
793 | #endif | |
794 | } | |
795 | ||
49ce9c2c | 796 | /** |
452c1ce2 CS |
797 | * atl2_close - Disables a network interface |
798 | * @netdev: network interface device structure | |
799 | * | |
800 | * Returns 0, this is not allowed to fail | |
801 | * | |
802 | * The close entry point is called when an interface is de-activated | |
803 | * by the OS. The hardware is still under the drivers control, but | |
804 | * needs to be disabled. A global MAC reset is issued to stop the | |
805 | * hardware, and all transmit and receive resources are freed. | |
806 | */ | |
807 | static int atl2_close(struct net_device *netdev) | |
808 | { | |
809 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
810 | ||
811 | WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); | |
812 | ||
813 | atl2_down(adapter); | |
814 | atl2_free_irq(adapter); | |
815 | atl2_free_ring_resources(adapter); | |
816 | ||
817 | return 0; | |
818 | } | |
819 | ||
820 | static inline int TxsFreeUnit(struct atl2_adapter *adapter) | |
821 | { | |
822 | u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr); | |
823 | ||
824 | return (adapter->txs_next_clear >= txs_write_ptr) ? | |
825 | (int) (adapter->txs_ring_size - adapter->txs_next_clear + | |
826 | txs_write_ptr - 1) : | |
827 | (int) (txs_write_ptr - adapter->txs_next_clear - 1); | |
828 | } | |
829 | ||
830 | static inline int TxdFreeBytes(struct atl2_adapter *adapter) | |
831 | { | |
832 | u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr); | |
833 | ||
834 | return (adapter->txd_write_ptr >= txd_read_ptr) ? | |
835 | (int) (adapter->txd_ring_size - adapter->txd_write_ptr + | |
836 | txd_read_ptr - 1) : | |
837 | (int) (txd_read_ptr - adapter->txd_write_ptr - 1); | |
838 | } | |
839 | ||
61357325 SH |
840 | static netdev_tx_t atl2_xmit_frame(struct sk_buff *skb, |
841 | struct net_device *netdev) | |
452c1ce2 CS |
842 | { |
843 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
452c1ce2 CS |
844 | struct tx_pkt_header *txph; |
845 | u32 offset, copy_len; | |
846 | int txs_unused; | |
847 | int txbuf_unused; | |
848 | ||
849 | if (test_bit(__ATL2_DOWN, &adapter->flags)) { | |
850 | dev_kfree_skb_any(skb); | |
851 | return NETDEV_TX_OK; | |
852 | } | |
853 | ||
854 | if (unlikely(skb->len <= 0)) { | |
855 | dev_kfree_skb_any(skb); | |
856 | return NETDEV_TX_OK; | |
857 | } | |
858 | ||
452c1ce2 CS |
859 | txs_unused = TxsFreeUnit(adapter); |
860 | txbuf_unused = TxdFreeBytes(adapter); | |
861 | ||
862 | if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused || | |
863 | txs_unused < 1) { | |
864 | /* not enough resources */ | |
865 | netif_stop_queue(netdev); | |
452c1ce2 CS |
866 | return NETDEV_TX_BUSY; |
867 | } | |
868 | ||
869 | offset = adapter->txd_write_ptr; | |
870 | ||
871 | txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset); | |
872 | ||
873 | *(u32 *)txph = 0; | |
874 | txph->pkt_size = skb->len; | |
875 | ||
876 | offset += 4; | |
877 | if (offset >= adapter->txd_ring_size) | |
878 | offset -= adapter->txd_ring_size; | |
879 | copy_len = adapter->txd_ring_size - offset; | |
880 | if (copy_len >= skb->len) { | |
881 | memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len); | |
882 | offset += ((u32)(skb->len + 3) & ~3); | |
883 | } else { | |
884 | memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len); | |
885 | memcpy((u8 *)adapter->txd_ring, skb->data+copy_len, | |
886 | skb->len-copy_len); | |
887 | offset = ((u32)(skb->len-copy_len + 3) & ~3); | |
888 | } | |
f646968f | 889 | #ifdef NETIF_F_HW_VLAN_CTAG_TX |
eab6d18d | 890 | if (vlan_tx_tag_present(skb)) { |
452c1ce2 CS |
891 | u16 vlan_tag = vlan_tx_tag_get(skb); |
892 | vlan_tag = (vlan_tag << 4) | | |
893 | (vlan_tag >> 13) | | |
894 | ((vlan_tag >> 9) & 0x8); | |
895 | txph->ins_vlan = 1; | |
896 | txph->vlan = vlan_tag; | |
897 | } | |
898 | #endif | |
899 | if (offset >= adapter->txd_ring_size) | |
900 | offset -= adapter->txd_ring_size; | |
901 | adapter->txd_write_ptr = offset; | |
902 | ||
903 | /* clear txs before send */ | |
904 | adapter->txs_ring[adapter->txs_next_clear].update = 0; | |
905 | if (++adapter->txs_next_clear == adapter->txs_ring_size) | |
906 | adapter->txs_next_clear = 0; | |
907 | ||
908 | ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX, | |
909 | (adapter->txd_write_ptr >> 2)); | |
910 | ||
87241840 | 911 | mmiowb(); |
452c1ce2 CS |
912 | dev_kfree_skb_any(skb); |
913 | return NETDEV_TX_OK; | |
914 | } | |
915 | ||
49ce9c2c | 916 | /** |
452c1ce2 CS |
917 | * atl2_change_mtu - Change the Maximum Transfer Unit |
918 | * @netdev: network interface device structure | |
919 | * @new_mtu: new value for maximum frame size | |
920 | * | |
921 | * Returns 0 on success, negative on failure | |
922 | */ | |
923 | static int atl2_change_mtu(struct net_device *netdev, int new_mtu) | |
924 | { | |
925 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
926 | struct atl2_hw *hw = &adapter->hw; | |
927 | ||
928 | if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE))) | |
929 | return -EINVAL; | |
930 | ||
931 | /* set MTU */ | |
932 | if (hw->max_frame_size != new_mtu) { | |
933 | netdev->mtu = new_mtu; | |
934 | ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE + | |
935 | VLAN_SIZE + ETHERNET_FCS_SIZE); | |
936 | } | |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
49ce9c2c | 941 | /** |
452c1ce2 CS |
942 | * atl2_set_mac - Change the Ethernet Address of the NIC |
943 | * @netdev: network interface device structure | |
944 | * @p: pointer to an address structure | |
945 | * | |
946 | * Returns 0 on success, negative on failure | |
947 | */ | |
948 | static int atl2_set_mac(struct net_device *netdev, void *p) | |
949 | { | |
950 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
951 | struct sockaddr *addr = p; | |
952 | ||
953 | if (!is_valid_ether_addr(addr->sa_data)) | |
954 | return -EADDRNOTAVAIL; | |
955 | ||
956 | if (netif_running(netdev)) | |
957 | return -EBUSY; | |
958 | ||
959 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
960 | memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len); | |
961 | ||
962 | atl2_set_mac_addr(&adapter->hw); | |
963 | ||
964 | return 0; | |
965 | } | |
966 | ||
452c1ce2 CS |
967 | static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
968 | { | |
969 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
970 | struct mii_ioctl_data *data = if_mii(ifr); | |
971 | unsigned long flags; | |
972 | ||
973 | switch (cmd) { | |
974 | case SIOCGMIIPHY: | |
975 | data->phy_id = 0; | |
976 | break; | |
977 | case SIOCGMIIREG: | |
452c1ce2 CS |
978 | spin_lock_irqsave(&adapter->stats_lock, flags); |
979 | if (atl2_read_phy_reg(&adapter->hw, | |
980 | data->reg_num & 0x1F, &data->val_out)) { | |
981 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
982 | return -EIO; | |
983 | } | |
984 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
985 | break; | |
986 | case SIOCSMIIREG: | |
452c1ce2 CS |
987 | if (data->reg_num & ~(0x1F)) |
988 | return -EFAULT; | |
989 | spin_lock_irqsave(&adapter->stats_lock, flags); | |
990 | if (atl2_write_phy_reg(&adapter->hw, data->reg_num, | |
991 | data->val_in)) { | |
992 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
993 | return -EIO; | |
994 | } | |
995 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
996 | break; | |
997 | default: | |
998 | return -EOPNOTSUPP; | |
999 | } | |
1000 | return 0; | |
1001 | } | |
1002 | ||
452c1ce2 CS |
1003 | static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
1004 | { | |
1005 | switch (cmd) { | |
1006 | case SIOCGMIIPHY: | |
1007 | case SIOCGMIIREG: | |
1008 | case SIOCSMIIREG: | |
1009 | return atl2_mii_ioctl(netdev, ifr, cmd); | |
1010 | #ifdef ETHTOOL_OPS_COMPAT | |
1011 | case SIOCETHTOOL: | |
1012 | return ethtool_ioctl(ifr); | |
1013 | #endif | |
1014 | default: | |
1015 | return -EOPNOTSUPP; | |
1016 | } | |
1017 | } | |
1018 | ||
49ce9c2c | 1019 | /** |
452c1ce2 CS |
1020 | * atl2_tx_timeout - Respond to a Tx Hang |
1021 | * @netdev: network interface device structure | |
1022 | */ | |
1023 | static void atl2_tx_timeout(struct net_device *netdev) | |
1024 | { | |
1025 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1026 | ||
1027 | /* Do the reset outside of interrupt context */ | |
1028 | schedule_work(&adapter->reset_task); | |
1029 | } | |
1030 | ||
49ce9c2c | 1031 | /** |
452c1ce2 CS |
1032 | * atl2_watchdog - Timer Call-back |
1033 | * @data: pointer to netdev cast into an unsigned long | |
1034 | */ | |
1035 | static void atl2_watchdog(unsigned long data) | |
1036 | { | |
1037 | struct atl2_adapter *adapter = (struct atl2_adapter *) data; | |
452c1ce2 CS |
1038 | |
1039 | if (!test_bit(__ATL2_DOWN, &adapter->flags)) { | |
02e71731 SH |
1040 | u32 drop_rxd, drop_rxs; |
1041 | unsigned long flags; | |
1042 | ||
452c1ce2 CS |
1043 | spin_lock_irqsave(&adapter->stats_lock, flags); |
1044 | drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV); | |
1045 | drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV); | |
452c1ce2 CS |
1046 | spin_unlock_irqrestore(&adapter->stats_lock, flags); |
1047 | ||
02e71731 SH |
1048 | adapter->netdev->stats.rx_over_errors += drop_rxd + drop_rxs; |
1049 | ||
452c1ce2 | 1050 | /* Reset the timer */ |
e053b628 SH |
1051 | mod_timer(&adapter->watchdog_timer, |
1052 | round_jiffies(jiffies + 4 * HZ)); | |
452c1ce2 CS |
1053 | } |
1054 | } | |
1055 | ||
49ce9c2c | 1056 | /** |
452c1ce2 CS |
1057 | * atl2_phy_config - Timer Call-back |
1058 | * @data: pointer to netdev cast into an unsigned long | |
1059 | */ | |
1060 | static void atl2_phy_config(unsigned long data) | |
1061 | { | |
1062 | struct atl2_adapter *adapter = (struct atl2_adapter *) data; | |
1063 | struct atl2_hw *hw = &adapter->hw; | |
1064 | unsigned long flags; | |
1065 | ||
1066 | spin_lock_irqsave(&adapter->stats_lock, flags); | |
1067 | atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg); | |
1068 | atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN | | |
1069 | MII_CR_RESTART_AUTO_NEG); | |
1070 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1071 | clear_bit(0, &adapter->cfg_phy); | |
1072 | } | |
1073 | ||
1074 | static int atl2_up(struct atl2_adapter *adapter) | |
1075 | { | |
1076 | struct net_device *netdev = adapter->netdev; | |
1077 | int err = 0; | |
1078 | u32 val; | |
1079 | ||
1080 | /* hardware has been reset, we need to reload some things */ | |
1081 | ||
1082 | err = atl2_init_hw(&adapter->hw); | |
1083 | if (err) { | |
1084 | err = -EIO; | |
1085 | return err; | |
1086 | } | |
1087 | ||
1088 | atl2_set_multi(netdev); | |
1089 | init_ring_ptrs(adapter); | |
1090 | ||
452c1ce2 | 1091 | atl2_restore_vlan(adapter); |
452c1ce2 CS |
1092 | |
1093 | if (atl2_configure(adapter)) { | |
1094 | err = -EIO; | |
1095 | goto err_up; | |
1096 | } | |
1097 | ||
1098 | clear_bit(__ATL2_DOWN, &adapter->flags); | |
1099 | ||
1100 | val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL); | |
1101 | ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val | | |
1102 | MASTER_CTRL_MANUAL_INT); | |
1103 | ||
1104 | atl2_irq_enable(adapter); | |
1105 | ||
1106 | err_up: | |
1107 | return err; | |
1108 | } | |
1109 | ||
1110 | static void atl2_reinit_locked(struct atl2_adapter *adapter) | |
1111 | { | |
1112 | WARN_ON(in_interrupt()); | |
1113 | while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) | |
1114 | msleep(1); | |
1115 | atl2_down(adapter); | |
1116 | atl2_up(adapter); | |
1117 | clear_bit(__ATL2_RESETTING, &adapter->flags); | |
1118 | } | |
1119 | ||
1120 | static void atl2_reset_task(struct work_struct *work) | |
1121 | { | |
1122 | struct atl2_adapter *adapter; | |
1123 | adapter = container_of(work, struct atl2_adapter, reset_task); | |
1124 | ||
1125 | atl2_reinit_locked(adapter); | |
1126 | } | |
1127 | ||
1128 | static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter) | |
1129 | { | |
1130 | u32 value; | |
1131 | struct atl2_hw *hw = &adapter->hw; | |
1132 | struct net_device *netdev = adapter->netdev; | |
1133 | ||
1134 | /* Config MAC CTRL Register */ | |
1135 | value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; | |
1136 | ||
1137 | /* duplex */ | |
1138 | if (FULL_DUPLEX == adapter->link_duplex) | |
1139 | value |= MAC_CTRL_DUPLX; | |
1140 | ||
1141 | /* flow control */ | |
1142 | value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); | |
1143 | ||
1144 | /* PAD & CRC */ | |
1145 | value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | |
1146 | ||
1147 | /* preamble length */ | |
1148 | value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) << | |
1149 | MAC_CTRL_PRMLEN_SHIFT); | |
1150 | ||
1151 | /* vlan */ | |
dc437974 | 1152 | __atl2_vlan_mode(netdev->features, &value); |
452c1ce2 CS |
1153 | |
1154 | /* filter mode */ | |
1155 | value |= MAC_CTRL_BC_EN; | |
1156 | if (netdev->flags & IFF_PROMISC) | |
1157 | value |= MAC_CTRL_PROMIS_EN; | |
1158 | else if (netdev->flags & IFF_ALLMULTI) | |
1159 | value |= MAC_CTRL_MC_ALL_EN; | |
1160 | ||
1161 | /* half retry buffer */ | |
1162 | value |= (((u32)(adapter->hw.retry_buf & | |
1163 | MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT); | |
1164 | ||
1165 | ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | |
1166 | } | |
1167 | ||
1168 | static int atl2_check_link(struct atl2_adapter *adapter) | |
1169 | { | |
1170 | struct atl2_hw *hw = &adapter->hw; | |
1171 | struct net_device *netdev = adapter->netdev; | |
1172 | int ret_val; | |
1173 | u16 speed, duplex, phy_data; | |
1174 | int reconfig = 0; | |
1175 | ||
1176 | /* MII_BMSR must read twise */ | |
1177 | atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | |
1178 | atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | |
1179 | if (!(phy_data&BMSR_LSTATUS)) { /* link down */ | |
1180 | if (netif_carrier_ok(netdev)) { /* old link state: Up */ | |
1181 | u32 value; | |
1182 | /* disable rx */ | |
1183 | value = ATL2_READ_REG(hw, REG_MAC_CTRL); | |
1184 | value &= ~MAC_CTRL_RX_EN; | |
1185 | ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | |
1186 | adapter->link_speed = SPEED_0; | |
1187 | netif_carrier_off(netdev); | |
1188 | netif_stop_queue(netdev); | |
1189 | } | |
1190 | return 0; | |
1191 | } | |
1192 | ||
1193 | /* Link Up */ | |
1194 | ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); | |
1195 | if (ret_val) | |
1196 | return ret_val; | |
1197 | switch (hw->MediaType) { | |
1198 | case MEDIA_TYPE_100M_FULL: | |
1199 | if (speed != SPEED_100 || duplex != FULL_DUPLEX) | |
1200 | reconfig = 1; | |
1201 | break; | |
1202 | case MEDIA_TYPE_100M_HALF: | |
1203 | if (speed != SPEED_100 || duplex != HALF_DUPLEX) | |
1204 | reconfig = 1; | |
1205 | break; | |
1206 | case MEDIA_TYPE_10M_FULL: | |
1207 | if (speed != SPEED_10 || duplex != FULL_DUPLEX) | |
1208 | reconfig = 1; | |
1209 | break; | |
1210 | case MEDIA_TYPE_10M_HALF: | |
1211 | if (speed != SPEED_10 || duplex != HALF_DUPLEX) | |
1212 | reconfig = 1; | |
1213 | break; | |
1214 | } | |
1215 | /* link result is our setting */ | |
1216 | if (reconfig == 0) { | |
1217 | if (adapter->link_speed != speed || | |
1218 | adapter->link_duplex != duplex) { | |
1219 | adapter->link_speed = speed; | |
1220 | adapter->link_duplex = duplex; | |
1221 | atl2_setup_mac_ctrl(adapter); | |
1222 | printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n", | |
1223 | atl2_driver_name, netdev->name, | |
1224 | adapter->link_speed, | |
1225 | adapter->link_duplex == FULL_DUPLEX ? | |
1226 | "Full Duplex" : "Half Duplex"); | |
1227 | } | |
1228 | ||
1229 | if (!netif_carrier_ok(netdev)) { /* Link down -> Up */ | |
1230 | netif_carrier_on(netdev); | |
1231 | netif_wake_queue(netdev); | |
1232 | } | |
1233 | return 0; | |
1234 | } | |
1235 | ||
1236 | /* change original link status */ | |
1237 | if (netif_carrier_ok(netdev)) { | |
1238 | u32 value; | |
1239 | /* disable rx */ | |
1240 | value = ATL2_READ_REG(hw, REG_MAC_CTRL); | |
1241 | value &= ~MAC_CTRL_RX_EN; | |
1242 | ATL2_WRITE_REG(hw, REG_MAC_CTRL, value); | |
1243 | ||
1244 | adapter->link_speed = SPEED_0; | |
1245 | netif_carrier_off(netdev); | |
1246 | netif_stop_queue(netdev); | |
1247 | } | |
1248 | ||
1249 | /* auto-neg, insert timer to re-config phy | |
1250 | * (if interval smaller than 5 seconds, something strange) */ | |
1251 | if (!test_bit(__ATL2_DOWN, &adapter->flags)) { | |
1252 | if (!test_and_set_bit(0, &adapter->cfg_phy)) | |
e053b628 SH |
1253 | mod_timer(&adapter->phy_config_timer, |
1254 | round_jiffies(jiffies + 5 * HZ)); | |
452c1ce2 CS |
1255 | } |
1256 | ||
1257 | return 0; | |
1258 | } | |
1259 | ||
49ce9c2c | 1260 | /** |
452c1ce2 | 1261 | * atl2_link_chg_task - deal with link change event Out of interrupt context |
452c1ce2 CS |
1262 | */ |
1263 | static void atl2_link_chg_task(struct work_struct *work) | |
1264 | { | |
1265 | struct atl2_adapter *adapter; | |
1266 | unsigned long flags; | |
1267 | ||
1268 | adapter = container_of(work, struct atl2_adapter, link_chg_task); | |
1269 | ||
1270 | spin_lock_irqsave(&adapter->stats_lock, flags); | |
1271 | atl2_check_link(adapter); | |
1272 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | |
1273 | } | |
1274 | ||
1275 | static void atl2_setup_pcicmd(struct pci_dev *pdev) | |
1276 | { | |
1277 | u16 cmd; | |
1278 | ||
1279 | pci_read_config_word(pdev, PCI_COMMAND, &cmd); | |
1280 | ||
1281 | if (cmd & PCI_COMMAND_INTX_DISABLE) | |
1282 | cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
1283 | if (cmd & PCI_COMMAND_IO) | |
1284 | cmd &= ~PCI_COMMAND_IO; | |
1285 | if (0 == (cmd & PCI_COMMAND_MEMORY)) | |
1286 | cmd |= PCI_COMMAND_MEMORY; | |
1287 | if (0 == (cmd & PCI_COMMAND_MASTER)) | |
1288 | cmd |= PCI_COMMAND_MASTER; | |
1289 | pci_write_config_word(pdev, PCI_COMMAND, cmd); | |
1290 | ||
1291 | /* | |
1292 | * some motherboards BIOS(PXE/EFI) driver may set PME | |
1293 | * while they transfer control to OS (Windows/Linux) | |
1294 | * so we should clear this bit before NIC work normally | |
1295 | */ | |
1296 | pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0); | |
1297 | } | |
1298 | ||
8d1b1fc9 KH |
1299 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1300 | static void atl2_poll_controller(struct net_device *netdev) | |
1301 | { | |
1302 | disable_irq(netdev->irq); | |
1303 | atl2_intr(netdev->irq, netdev); | |
1304 | enable_irq(netdev->irq); | |
1305 | } | |
1306 | #endif | |
1307 | ||
825a84d1 SH |
1308 | |
1309 | static const struct net_device_ops atl2_netdev_ops = { | |
1310 | .ndo_open = atl2_open, | |
1311 | .ndo_stop = atl2_close, | |
00829823 | 1312 | .ndo_start_xmit = atl2_xmit_frame, |
afc4b13d | 1313 | .ndo_set_rx_mode = atl2_set_multi, |
825a84d1 SH |
1314 | .ndo_validate_addr = eth_validate_addr, |
1315 | .ndo_set_mac_address = atl2_set_mac, | |
1316 | .ndo_change_mtu = atl2_change_mtu, | |
dc437974 JP |
1317 | .ndo_fix_features = atl2_fix_features, |
1318 | .ndo_set_features = atl2_set_features, | |
825a84d1 SH |
1319 | .ndo_do_ioctl = atl2_ioctl, |
1320 | .ndo_tx_timeout = atl2_tx_timeout, | |
825a84d1 SH |
1321 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1322 | .ndo_poll_controller = atl2_poll_controller, | |
1323 | #endif | |
1324 | }; | |
1325 | ||
49ce9c2c | 1326 | /** |
452c1ce2 CS |
1327 | * atl2_probe - Device Initialization Routine |
1328 | * @pdev: PCI device information struct | |
1329 | * @ent: entry in atl2_pci_tbl | |
1330 | * | |
1331 | * Returns 0 on success, negative on failure | |
1332 | * | |
1333 | * atl2_probe initializes an adapter identified by a pci_dev structure. | |
1334 | * The OS initialization, configuring of the adapter private structure, | |
1335 | * and a hardware reset occur. | |
1336 | */ | |
1dd06ae8 | 1337 | static int atl2_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
452c1ce2 CS |
1338 | { |
1339 | struct net_device *netdev; | |
1340 | struct atl2_adapter *adapter; | |
1341 | static int cards_found; | |
1342 | unsigned long mmio_start; | |
1343 | int mmio_len; | |
1344 | int err; | |
1345 | ||
1346 | cards_found = 0; | |
1347 | ||
1348 | err = pci_enable_device(pdev); | |
1349 | if (err) | |
1350 | return err; | |
1351 | ||
1352 | /* | |
1353 | * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA | |
1354 | * until the kernel has the proper infrastructure to support 64-bit DMA | |
1355 | * on these devices. | |
1356 | */ | |
284901a9 YH |
1357 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) && |
1358 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
452c1ce2 CS |
1359 | printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n"); |
1360 | goto err_dma; | |
1361 | } | |
1362 | ||
1363 | /* Mark all PCI regions associated with PCI device | |
1364 | * pdev as being reserved by owner atl2_driver_name */ | |
1365 | err = pci_request_regions(pdev, atl2_driver_name); | |
1366 | if (err) | |
1367 | goto err_pci_reg; | |
1368 | ||
1369 | /* Enables bus-mastering on the device and calls | |
1370 | * pcibios_set_master to do the needed arch specific settings */ | |
1371 | pci_set_master(pdev); | |
1372 | ||
1373 | err = -ENOMEM; | |
1374 | netdev = alloc_etherdev(sizeof(struct atl2_adapter)); | |
1375 | if (!netdev) | |
1376 | goto err_alloc_etherdev; | |
1377 | ||
1378 | SET_NETDEV_DEV(netdev, &pdev->dev); | |
1379 | ||
1380 | pci_set_drvdata(pdev, netdev); | |
1381 | adapter = netdev_priv(netdev); | |
1382 | adapter->netdev = netdev; | |
1383 | adapter->pdev = pdev; | |
1384 | adapter->hw.back = adapter; | |
1385 | ||
1386 | mmio_start = pci_resource_start(pdev, 0x0); | |
1387 | mmio_len = pci_resource_len(pdev, 0x0); | |
1388 | ||
1389 | adapter->hw.mem_rang = (u32)mmio_len; | |
1390 | adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); | |
1391 | if (!adapter->hw.hw_addr) { | |
1392 | err = -EIO; | |
1393 | goto err_ioremap; | |
1394 | } | |
1395 | ||
1396 | atl2_setup_pcicmd(pdev); | |
1397 | ||
825a84d1 | 1398 | netdev->netdev_ops = &atl2_netdev_ops; |
7ad24ea4 | 1399 | netdev->ethtool_ops = &atl2_ethtool_ops; |
452c1ce2 | 1400 | netdev->watchdog_timeo = 5 * HZ; |
452c1ce2 CS |
1401 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
1402 | ||
1403 | netdev->mem_start = mmio_start; | |
1404 | netdev->mem_end = mmio_start + mmio_len; | |
1405 | adapter->bd_number = cards_found; | |
1406 | adapter->pci_using_64 = false; | |
1407 | ||
1408 | /* setup the private structure */ | |
1409 | err = atl2_sw_init(adapter); | |
1410 | if (err) | |
1411 | goto err_sw_init; | |
1412 | ||
1413 | err = -EIO; | |
1414 | ||
f646968f PM |
1415 | netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_RX; |
1416 | netdev->features |= (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX); | |
452c1ce2 | 1417 | |
452c1ce2 CS |
1418 | /* Init PHY as early as possible due to power saving issue */ |
1419 | atl2_phy_init(&adapter->hw); | |
1420 | ||
1421 | /* reset the controller to | |
1422 | * put the device in a known good starting state */ | |
1423 | ||
1424 | if (atl2_reset_hw(&adapter->hw)) { | |
1425 | err = -EIO; | |
1426 | goto err_reset; | |
1427 | } | |
1428 | ||
1429 | /* copy the MAC address out of the EEPROM */ | |
1430 | atl2_read_mac_addr(&adapter->hw); | |
1431 | memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len); | |
452c1ce2 | 1432 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
452c1ce2 CS |
1433 | err = -EIO; |
1434 | goto err_eeprom; | |
1435 | } | |
1436 | ||
1437 | atl2_check_options(adapter); | |
1438 | ||
1439 | init_timer(&adapter->watchdog_timer); | |
c061b18d | 1440 | adapter->watchdog_timer.function = atl2_watchdog; |
452c1ce2 CS |
1441 | adapter->watchdog_timer.data = (unsigned long) adapter; |
1442 | ||
1443 | init_timer(&adapter->phy_config_timer); | |
c061b18d | 1444 | adapter->phy_config_timer.function = atl2_phy_config; |
452c1ce2 CS |
1445 | adapter->phy_config_timer.data = (unsigned long) adapter; |
1446 | ||
1447 | INIT_WORK(&adapter->reset_task, atl2_reset_task); | |
1448 | INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task); | |
1449 | ||
1450 | strcpy(netdev->name, "eth%d"); /* ?? */ | |
1451 | err = register_netdev(netdev); | |
1452 | if (err) | |
1453 | goto err_register; | |
1454 | ||
1455 | /* assume we have no link for now */ | |
1456 | netif_carrier_off(netdev); | |
1457 | netif_stop_queue(netdev); | |
1458 | ||
1459 | cards_found++; | |
1460 | ||
1461 | return 0; | |
1462 | ||
1463 | err_reset: | |
1464 | err_register: | |
1465 | err_sw_init: | |
1466 | err_eeprom: | |
1467 | iounmap(adapter->hw.hw_addr); | |
1468 | err_ioremap: | |
1469 | free_netdev(netdev); | |
1470 | err_alloc_etherdev: | |
1471 | pci_release_regions(pdev); | |
1472 | err_pci_reg: | |
1473 | err_dma: | |
1474 | pci_disable_device(pdev); | |
1475 | return err; | |
1476 | } | |
1477 | ||
49ce9c2c | 1478 | /** |
452c1ce2 CS |
1479 | * atl2_remove - Device Removal Routine |
1480 | * @pdev: PCI device information struct | |
1481 | * | |
1482 | * atl2_remove is called by the PCI subsystem to alert the driver | |
1483 | * that it should release a PCI device. The could be caused by a | |
1484 | * Hot-Plug event, or because the driver is going to be removed from | |
1485 | * memory. | |
1486 | */ | |
1487 | /* FIXME: write the original MAC address back in case it was changed from a | |
1488 | * BIOS-set value, as in atl1 -- CHS */ | |
093d369d | 1489 | static void atl2_remove(struct pci_dev *pdev) |
452c1ce2 CS |
1490 | { |
1491 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1492 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1493 | ||
1494 | /* flush_scheduled work may reschedule our watchdog task, so | |
1495 | * explicitly disable watchdog tasks from being rescheduled */ | |
1496 | set_bit(__ATL2_DOWN, &adapter->flags); | |
1497 | ||
1498 | del_timer_sync(&adapter->watchdog_timer); | |
1499 | del_timer_sync(&adapter->phy_config_timer); | |
23f333a2 TH |
1500 | cancel_work_sync(&adapter->reset_task); |
1501 | cancel_work_sync(&adapter->link_chg_task); | |
452c1ce2 CS |
1502 | |
1503 | unregister_netdev(netdev); | |
1504 | ||
1505 | atl2_force_ps(&adapter->hw); | |
1506 | ||
1507 | iounmap(adapter->hw.hw_addr); | |
1508 | pci_release_regions(pdev); | |
1509 | ||
1510 | free_netdev(netdev); | |
1511 | ||
1512 | pci_disable_device(pdev); | |
1513 | } | |
1514 | ||
1515 | static int atl2_suspend(struct pci_dev *pdev, pm_message_t state) | |
1516 | { | |
1517 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1518 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1519 | struct atl2_hw *hw = &adapter->hw; | |
1520 | u16 speed, duplex; | |
1521 | u32 ctrl = 0; | |
1522 | u32 wufc = adapter->wol; | |
1523 | ||
1524 | #ifdef CONFIG_PM | |
1525 | int retval = 0; | |
1526 | #endif | |
1527 | ||
1528 | netif_device_detach(netdev); | |
1529 | ||
1530 | if (netif_running(netdev)) { | |
1531 | WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags)); | |
1532 | atl2_down(adapter); | |
1533 | } | |
1534 | ||
1535 | #ifdef CONFIG_PM | |
1536 | retval = pci_save_state(pdev); | |
1537 | if (retval) | |
1538 | return retval; | |
1539 | #endif | |
1540 | ||
1541 | atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); | |
1542 | atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl); | |
1543 | if (ctrl & BMSR_LSTATUS) | |
1544 | wufc &= ~ATLX_WUFC_LNKC; | |
1545 | ||
1546 | if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) { | |
1547 | u32 ret_val; | |
1548 | /* get current link speed & duplex */ | |
1549 | ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex); | |
1550 | if (ret_val) { | |
1551 | printk(KERN_DEBUG | |
1552 | "%s: get speed&duplex error while suspend\n", | |
1553 | atl2_driver_name); | |
1554 | goto wol_dis; | |
1555 | } | |
1556 | ||
1557 | ctrl = 0; | |
1558 | ||
1559 | /* turn on magic packet wol */ | |
1560 | if (wufc & ATLX_WUFC_MAG) | |
1561 | ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN); | |
1562 | ||
1563 | /* ignore Link Chg event when Link is up */ | |
1564 | ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); | |
1565 | ||
1566 | /* Config MAC CTRL Register */ | |
1567 | ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY; | |
1568 | if (FULL_DUPLEX == adapter->link_duplex) | |
1569 | ctrl |= MAC_CTRL_DUPLX; | |
1570 | ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); | |
1571 | ctrl |= (((u32)adapter->hw.preamble_len & | |
1572 | MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT); | |
1573 | ctrl |= (((u32)(adapter->hw.retry_buf & | |
1574 | MAC_CTRL_HALF_LEFT_BUF_MASK)) << | |
1575 | MAC_CTRL_HALF_LEFT_BUF_SHIFT); | |
1576 | if (wufc & ATLX_WUFC_MAG) { | |
1577 | /* magic packet maybe Broadcast&multicast&Unicast */ | |
1578 | ctrl |= MAC_CTRL_BC_EN; | |
1579 | } | |
1580 | ||
1581 | ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl); | |
1582 | ||
1583 | /* pcie patch */ | |
1584 | ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | |
1585 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
1586 | ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | |
1587 | ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | |
1588 | ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | |
1589 | ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | |
1590 | ||
1591 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | |
1592 | goto suspend_exit; | |
1593 | } | |
1594 | ||
1595 | if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) { | |
1596 | /* link is down, so only LINK CHG WOL event enable */ | |
1597 | ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN); | |
1598 | ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl); | |
1599 | ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0); | |
1600 | ||
1601 | /* pcie patch */ | |
1602 | ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | |
1603 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
1604 | ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | |
1605 | ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | |
1606 | ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | |
1607 | ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | |
1608 | ||
1609 | hw->phy_configured = false; /* re-init PHY when resume */ | |
1610 | ||
1611 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 1); | |
1612 | ||
1613 | goto suspend_exit; | |
1614 | } | |
1615 | ||
1616 | wol_dis: | |
1617 | /* WOL disabled */ | |
1618 | ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0); | |
1619 | ||
1620 | /* pcie patch */ | |
1621 | ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC); | |
1622 | ctrl |= PCIE_PHYMISC_FORCE_RCV_DET; | |
1623 | ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl); | |
1624 | ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1); | |
1625 | ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK; | |
1626 | ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl); | |
1627 | ||
1628 | atl2_force_ps(hw); | |
1629 | hw->phy_configured = false; /* re-init PHY when resume */ | |
1630 | ||
1631 | pci_enable_wake(pdev, pci_choose_state(pdev, state), 0); | |
1632 | ||
1633 | suspend_exit: | |
1634 | if (netif_running(netdev)) | |
1635 | atl2_free_irq(adapter); | |
1636 | ||
1637 | pci_disable_device(pdev); | |
1638 | ||
1639 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1640 | ||
1641 | return 0; | |
1642 | } | |
1643 | ||
1644 | #ifdef CONFIG_PM | |
1645 | static int atl2_resume(struct pci_dev *pdev) | |
1646 | { | |
1647 | struct net_device *netdev = pci_get_drvdata(pdev); | |
1648 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1649 | u32 err; | |
1650 | ||
1651 | pci_set_power_state(pdev, PCI_D0); | |
1652 | pci_restore_state(pdev); | |
1653 | ||
1654 | err = pci_enable_device(pdev); | |
1655 | if (err) { | |
1656 | printk(KERN_ERR | |
1657 | "atl2: Cannot enable PCI device from suspend\n"); | |
1658 | return err; | |
1659 | } | |
1660 | ||
1661 | pci_set_master(pdev); | |
1662 | ||
1663 | ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */ | |
1664 | ||
1665 | pci_enable_wake(pdev, PCI_D3hot, 0); | |
1666 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
1667 | ||
1668 | ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0); | |
1669 | ||
a849854f AJ |
1670 | if (netif_running(netdev)) { |
1671 | err = atl2_request_irq(adapter); | |
1672 | if (err) | |
1673 | return err; | |
1674 | } | |
452c1ce2 CS |
1675 | |
1676 | atl2_reset_hw(&adapter->hw); | |
1677 | ||
1678 | if (netif_running(netdev)) | |
1679 | atl2_up(adapter); | |
1680 | ||
1681 | netif_device_attach(netdev); | |
1682 | ||
1683 | return 0; | |
1684 | } | |
1685 | #endif | |
1686 | ||
1687 | static void atl2_shutdown(struct pci_dev *pdev) | |
1688 | { | |
1689 | atl2_suspend(pdev, PMSG_SUSPEND); | |
1690 | } | |
1691 | ||
1692 | static struct pci_driver atl2_driver = { | |
1693 | .name = atl2_driver_name, | |
1694 | .id_table = atl2_pci_tbl, | |
1695 | .probe = atl2_probe, | |
093d369d | 1696 | .remove = atl2_remove, |
25985edc | 1697 | /* Power Management Hooks */ |
452c1ce2 CS |
1698 | .suspend = atl2_suspend, |
1699 | #ifdef CONFIG_PM | |
1700 | .resume = atl2_resume, | |
1701 | #endif | |
1702 | .shutdown = atl2_shutdown, | |
1703 | }; | |
1704 | ||
49ce9c2c | 1705 | /** |
452c1ce2 CS |
1706 | * atl2_init_module - Driver Registration Routine |
1707 | * | |
1708 | * atl2_init_module is the first routine called when the driver is | |
1709 | * loaded. All it does is register with the PCI subsystem. | |
1710 | */ | |
1711 | static int __init atl2_init_module(void) | |
1712 | { | |
1713 | printk(KERN_INFO "%s - version %s\n", atl2_driver_string, | |
1714 | atl2_driver_version); | |
1715 | printk(KERN_INFO "%s\n", atl2_copyright); | |
1716 | return pci_register_driver(&atl2_driver); | |
1717 | } | |
1718 | module_init(atl2_init_module); | |
1719 | ||
49ce9c2c | 1720 | /** |
452c1ce2 CS |
1721 | * atl2_exit_module - Driver Exit Cleanup Routine |
1722 | * | |
1723 | * atl2_exit_module is called just before the driver is removed | |
1724 | * from memory. | |
1725 | */ | |
1726 | static void __exit atl2_exit_module(void) | |
1727 | { | |
1728 | pci_unregister_driver(&atl2_driver); | |
1729 | } | |
1730 | module_exit(atl2_exit_module); | |
1731 | ||
1732 | static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) | |
1733 | { | |
1734 | struct atl2_adapter *adapter = hw->back; | |
1735 | pci_read_config_word(adapter->pdev, reg, value); | |
1736 | } | |
1737 | ||
1738 | static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value) | |
1739 | { | |
1740 | struct atl2_adapter *adapter = hw->back; | |
1741 | pci_write_config_word(adapter->pdev, reg, *value); | |
1742 | } | |
1743 | ||
1744 | static int atl2_get_settings(struct net_device *netdev, | |
1745 | struct ethtool_cmd *ecmd) | |
1746 | { | |
1747 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1748 | struct atl2_hw *hw = &adapter->hw; | |
1749 | ||
1750 | ecmd->supported = (SUPPORTED_10baseT_Half | | |
1751 | SUPPORTED_10baseT_Full | | |
1752 | SUPPORTED_100baseT_Half | | |
1753 | SUPPORTED_100baseT_Full | | |
1754 | SUPPORTED_Autoneg | | |
1755 | SUPPORTED_TP); | |
1756 | ecmd->advertising = ADVERTISED_TP; | |
1757 | ||
1758 | ecmd->advertising |= ADVERTISED_Autoneg; | |
1759 | ecmd->advertising |= hw->autoneg_advertised; | |
1760 | ||
1761 | ecmd->port = PORT_TP; | |
1762 | ecmd->phy_address = 0; | |
1763 | ecmd->transceiver = XCVR_INTERNAL; | |
1764 | ||
1765 | if (adapter->link_speed != SPEED_0) { | |
70739497 | 1766 | ethtool_cmd_speed_set(ecmd, adapter->link_speed); |
452c1ce2 CS |
1767 | if (adapter->link_duplex == FULL_DUPLEX) |
1768 | ecmd->duplex = DUPLEX_FULL; | |
1769 | else | |
1770 | ecmd->duplex = DUPLEX_HALF; | |
1771 | } else { | |
537fae01 JP |
1772 | ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN); |
1773 | ecmd->duplex = DUPLEX_UNKNOWN; | |
452c1ce2 CS |
1774 | } |
1775 | ||
1776 | ecmd->autoneg = AUTONEG_ENABLE; | |
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | static int atl2_set_settings(struct net_device *netdev, | |
1781 | struct ethtool_cmd *ecmd) | |
1782 | { | |
1783 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1784 | struct atl2_hw *hw = &adapter->hw; | |
1785 | ||
1786 | while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags)) | |
1787 | msleep(1); | |
1788 | ||
1789 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
1790 | #define MY_ADV_MASK (ADVERTISE_10_HALF | \ | |
1791 | ADVERTISE_10_FULL | \ | |
1792 | ADVERTISE_100_HALF| \ | |
1793 | ADVERTISE_100_FULL) | |
1794 | ||
1795 | if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) { | |
1796 | hw->MediaType = MEDIA_TYPE_AUTO_SENSOR; | |
1797 | hw->autoneg_advertised = MY_ADV_MASK; | |
1798 | } else if ((ecmd->advertising & MY_ADV_MASK) == | |
1799 | ADVERTISE_100_FULL) { | |
1800 | hw->MediaType = MEDIA_TYPE_100M_FULL; | |
1801 | hw->autoneg_advertised = ADVERTISE_100_FULL; | |
1802 | } else if ((ecmd->advertising & MY_ADV_MASK) == | |
1803 | ADVERTISE_100_HALF) { | |
1804 | hw->MediaType = MEDIA_TYPE_100M_HALF; | |
1805 | hw->autoneg_advertised = ADVERTISE_100_HALF; | |
1806 | } else if ((ecmd->advertising & MY_ADV_MASK) == | |
1807 | ADVERTISE_10_FULL) { | |
1808 | hw->MediaType = MEDIA_TYPE_10M_FULL; | |
1809 | hw->autoneg_advertised = ADVERTISE_10_FULL; | |
1810 | } else if ((ecmd->advertising & MY_ADV_MASK) == | |
1811 | ADVERTISE_10_HALF) { | |
1812 | hw->MediaType = MEDIA_TYPE_10M_HALF; | |
1813 | hw->autoneg_advertised = ADVERTISE_10_HALF; | |
1814 | } else { | |
1815 | clear_bit(__ATL2_RESETTING, &adapter->flags); | |
1816 | return -EINVAL; | |
1817 | } | |
1818 | ecmd->advertising = hw->autoneg_advertised | | |
1819 | ADVERTISED_TP | ADVERTISED_Autoneg; | |
1820 | } else { | |
1821 | clear_bit(__ATL2_RESETTING, &adapter->flags); | |
1822 | return -EINVAL; | |
1823 | } | |
1824 | ||
1825 | /* reset the link */ | |
1826 | if (netif_running(adapter->netdev)) { | |
1827 | atl2_down(adapter); | |
1828 | atl2_up(adapter); | |
1829 | } else | |
1830 | atl2_reset_hw(&adapter->hw); | |
1831 | ||
1832 | clear_bit(__ATL2_RESETTING, &adapter->flags); | |
1833 | return 0; | |
1834 | } | |
1835 | ||
452c1ce2 CS |
1836 | static u32 atl2_get_msglevel(struct net_device *netdev) |
1837 | { | |
1838 | return 0; | |
1839 | } | |
1840 | ||
1841 | /* | |
1842 | * It's sane for this to be empty, but we might want to take advantage of this. | |
1843 | */ | |
1844 | static void atl2_set_msglevel(struct net_device *netdev, u32 data) | |
1845 | { | |
1846 | } | |
1847 | ||
1848 | static int atl2_get_regs_len(struct net_device *netdev) | |
1849 | { | |
1850 | #define ATL2_REGS_LEN 42 | |
1851 | return sizeof(u32) * ATL2_REGS_LEN; | |
1852 | } | |
1853 | ||
1854 | static void atl2_get_regs(struct net_device *netdev, | |
1855 | struct ethtool_regs *regs, void *p) | |
1856 | { | |
1857 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1858 | struct atl2_hw *hw = &adapter->hw; | |
1859 | u32 *regs_buff = p; | |
1860 | u16 phy_data; | |
1861 | ||
1862 | memset(p, 0, sizeof(u32) * ATL2_REGS_LEN); | |
1863 | ||
1864 | regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; | |
1865 | ||
1866 | regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP); | |
1867 | regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | |
1868 | regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG); | |
1869 | regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL); | |
1870 | regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); | |
1871 | regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL); | |
1872 | regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT); | |
1873 | regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); | |
1874 | regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE); | |
1875 | regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER); | |
1876 | regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS); | |
1877 | regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL); | |
1878 | regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK); | |
1879 | regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL); | |
1880 | regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG); | |
1881 | regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); | |
1882 | regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4); | |
1883 | regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE); | |
1884 | regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4); | |
1885 | regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); | |
1886 | regs_buff[20] = ATL2_READ_REG(hw, REG_MTU); | |
1887 | regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL); | |
1888 | regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END); | |
1889 | regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI); | |
1890 | regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO); | |
1891 | regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE); | |
1892 | regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO); | |
1893 | regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE); | |
1894 | regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO); | |
1895 | regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM); | |
1896 | regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR); | |
1897 | regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH); | |
1898 | regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW); | |
1899 | regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH); | |
1900 | regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH); | |
1901 | regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX); | |
1902 | regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX); | |
1903 | regs_buff[38] = ATL2_READ_REG(hw, REG_ISR); | |
1904 | regs_buff[39] = ATL2_READ_REG(hw, REG_IMR); | |
1905 | ||
1906 | atl2_read_phy_reg(hw, MII_BMCR, &phy_data); | |
1907 | regs_buff[40] = (u32)phy_data; | |
1908 | atl2_read_phy_reg(hw, MII_BMSR, &phy_data); | |
1909 | regs_buff[41] = (u32)phy_data; | |
1910 | } | |
1911 | ||
1912 | static int atl2_get_eeprom_len(struct net_device *netdev) | |
1913 | { | |
1914 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1915 | ||
1916 | if (!atl2_check_eeprom_exist(&adapter->hw)) | |
1917 | return 512; | |
1918 | else | |
1919 | return 0; | |
1920 | } | |
1921 | ||
1922 | static int atl2_get_eeprom(struct net_device *netdev, | |
1923 | struct ethtool_eeprom *eeprom, u8 *bytes) | |
1924 | { | |
1925 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1926 | struct atl2_hw *hw = &adapter->hw; | |
1927 | u32 *eeprom_buff; | |
1928 | int first_dword, last_dword; | |
1929 | int ret_val = 0; | |
1930 | int i; | |
1931 | ||
1932 | if (eeprom->len == 0) | |
1933 | return -EINVAL; | |
1934 | ||
1935 | if (atl2_check_eeprom_exist(hw)) | |
1936 | return -EINVAL; | |
1937 | ||
1938 | eeprom->magic = hw->vendor_id | (hw->device_id << 16); | |
1939 | ||
1940 | first_dword = eeprom->offset >> 2; | |
1941 | last_dword = (eeprom->offset + eeprom->len - 1) >> 2; | |
1942 | ||
1943 | eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1), | |
1944 | GFP_KERNEL); | |
1945 | if (!eeprom_buff) | |
1946 | return -ENOMEM; | |
1947 | ||
1948 | for (i = first_dword; i < last_dword; i++) { | |
2467ab95 JS |
1949 | if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword]))) { |
1950 | ret_val = -EIO; | |
1951 | goto free; | |
1952 | } | |
452c1ce2 CS |
1953 | } |
1954 | ||
1955 | memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3), | |
1956 | eeprom->len); | |
2467ab95 | 1957 | free: |
452c1ce2 CS |
1958 | kfree(eeprom_buff); |
1959 | ||
1960 | return ret_val; | |
1961 | } | |
1962 | ||
1963 | static int atl2_set_eeprom(struct net_device *netdev, | |
1964 | struct ethtool_eeprom *eeprom, u8 *bytes) | |
1965 | { | |
1966 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
1967 | struct atl2_hw *hw = &adapter->hw; | |
1968 | u32 *eeprom_buff; | |
1969 | u32 *ptr; | |
1970 | int max_len, first_dword, last_dword, ret_val = 0; | |
1971 | int i; | |
1972 | ||
1973 | if (eeprom->len == 0) | |
1974 | return -EOPNOTSUPP; | |
1975 | ||
1976 | if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) | |
1977 | return -EFAULT; | |
1978 | ||
1979 | max_len = 512; | |
1980 | ||
1981 | first_dword = eeprom->offset >> 2; | |
1982 | last_dword = (eeprom->offset + eeprom->len - 1) >> 2; | |
1983 | eeprom_buff = kmalloc(max_len, GFP_KERNEL); | |
1984 | if (!eeprom_buff) | |
1985 | return -ENOMEM; | |
1986 | ||
ad19031b | 1987 | ptr = eeprom_buff; |
452c1ce2 CS |
1988 | |
1989 | if (eeprom->offset & 3) { | |
1990 | /* need read/modify/write of first changed EEPROM word */ | |
1991 | /* only the second byte of the word is being modified */ | |
ad19031b JJ |
1992 | if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0]))) { |
1993 | ret_val = -EIO; | |
1994 | goto out; | |
1995 | } | |
452c1ce2 CS |
1996 | ptr++; |
1997 | } | |
1998 | if (((eeprom->offset + eeprom->len) & 3)) { | |
1999 | /* | |
2000 | * need read/modify/write of last changed EEPROM word | |
2001 | * only the first byte of the word is being modified | |
2002 | */ | |
2003 | if (!atl2_read_eeprom(hw, last_dword * 4, | |
ad19031b JJ |
2004 | &(eeprom_buff[last_dword - first_dword]))) { |
2005 | ret_val = -EIO; | |
2006 | goto out; | |
2007 | } | |
452c1ce2 CS |
2008 | } |
2009 | ||
2010 | /* Device's eeprom is always little-endian, word addressable */ | |
2011 | memcpy(ptr, bytes, eeprom->len); | |
2012 | ||
2013 | for (i = 0; i < last_dword - first_dword + 1; i++) { | |
ad19031b JJ |
2014 | if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i])) { |
2015 | ret_val = -EIO; | |
2016 | goto out; | |
2017 | } | |
452c1ce2 | 2018 | } |
ad19031b | 2019 | out: |
452c1ce2 CS |
2020 | kfree(eeprom_buff); |
2021 | return ret_val; | |
2022 | } | |
2023 | ||
2024 | static void atl2_get_drvinfo(struct net_device *netdev, | |
2025 | struct ethtool_drvinfo *drvinfo) | |
2026 | { | |
2027 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
2028 | ||
68aad78c RJ |
2029 | strlcpy(drvinfo->driver, atl2_driver_name, sizeof(drvinfo->driver)); |
2030 | strlcpy(drvinfo->version, atl2_driver_version, | |
2031 | sizeof(drvinfo->version)); | |
2032 | strlcpy(drvinfo->fw_version, "L2", sizeof(drvinfo->fw_version)); | |
2033 | strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), | |
2034 | sizeof(drvinfo->bus_info)); | |
452c1ce2 CS |
2035 | drvinfo->n_stats = 0; |
2036 | drvinfo->testinfo_len = 0; | |
2037 | drvinfo->regdump_len = atl2_get_regs_len(netdev); | |
2038 | drvinfo->eedump_len = atl2_get_eeprom_len(netdev); | |
2039 | } | |
2040 | ||
2041 | static void atl2_get_wol(struct net_device *netdev, | |
2042 | struct ethtool_wolinfo *wol) | |
2043 | { | |
2044 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
2045 | ||
2046 | wol->supported = WAKE_MAGIC; | |
2047 | wol->wolopts = 0; | |
2048 | ||
2049 | if (adapter->wol & ATLX_WUFC_EX) | |
2050 | wol->wolopts |= WAKE_UCAST; | |
2051 | if (adapter->wol & ATLX_WUFC_MC) | |
2052 | wol->wolopts |= WAKE_MCAST; | |
2053 | if (adapter->wol & ATLX_WUFC_BC) | |
2054 | wol->wolopts |= WAKE_BCAST; | |
2055 | if (adapter->wol & ATLX_WUFC_MAG) | |
2056 | wol->wolopts |= WAKE_MAGIC; | |
2057 | if (adapter->wol & ATLX_WUFC_LNKC) | |
2058 | wol->wolopts |= WAKE_PHY; | |
2059 | } | |
2060 | ||
2061 | static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
2062 | { | |
2063 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
2064 | ||
2065 | if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) | |
2066 | return -EOPNOTSUPP; | |
2067 | ||
41796e91 | 2068 | if (wol->wolopts & (WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)) |
452c1ce2 CS |
2069 | return -EOPNOTSUPP; |
2070 | ||
2071 | /* these settings will always override what we currently have */ | |
2072 | adapter->wol = 0; | |
2073 | ||
2074 | if (wol->wolopts & WAKE_MAGIC) | |
2075 | adapter->wol |= ATLX_WUFC_MAG; | |
2076 | if (wol->wolopts & WAKE_PHY) | |
2077 | adapter->wol |= ATLX_WUFC_LNKC; | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
2082 | static int atl2_nway_reset(struct net_device *netdev) | |
2083 | { | |
2084 | struct atl2_adapter *adapter = netdev_priv(netdev); | |
2085 | if (netif_running(netdev)) | |
2086 | atl2_reinit_locked(adapter); | |
2087 | return 0; | |
2088 | } | |
2089 | ||
0fc0b732 | 2090 | static const struct ethtool_ops atl2_ethtool_ops = { |
452c1ce2 CS |
2091 | .get_settings = atl2_get_settings, |
2092 | .set_settings = atl2_set_settings, | |
2093 | .get_drvinfo = atl2_get_drvinfo, | |
2094 | .get_regs_len = atl2_get_regs_len, | |
2095 | .get_regs = atl2_get_regs, | |
2096 | .get_wol = atl2_get_wol, | |
2097 | .set_wol = atl2_set_wol, | |
2098 | .get_msglevel = atl2_get_msglevel, | |
2099 | .set_msglevel = atl2_set_msglevel, | |
2100 | .nway_reset = atl2_nway_reset, | |
2101 | .get_link = ethtool_op_get_link, | |
2102 | .get_eeprom_len = atl2_get_eeprom_len, | |
2103 | .get_eeprom = atl2_get_eeprom, | |
2104 | .set_eeprom = atl2_set_eeprom, | |
452c1ce2 CS |
2105 | }; |
2106 | ||
452c1ce2 CS |
2107 | #define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \ |
2108 | (((a) & 0xff00ff00) >> 8)) | |
2109 | #define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16)) | |
2110 | #define SHORTSWAP(a) (((a) << 8) | ((a) >> 8)) | |
2111 | ||
2112 | /* | |
2113 | * Reset the transmit and receive units; mask and clear all interrupts. | |
2114 | * | |
2115 | * hw - Struct containing variables accessed by shared code | |
2116 | * return : 0 or idle status (if error) | |
2117 | */ | |
2118 | static s32 atl2_reset_hw(struct atl2_hw *hw) | |
2119 | { | |
2120 | u32 icr; | |
2121 | u16 pci_cfg_cmd_word; | |
2122 | int i; | |
2123 | ||
2124 | /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */ | |
2125 | atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); | |
2126 | if ((pci_cfg_cmd_word & | |
2127 | (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) != | |
2128 | (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) { | |
2129 | pci_cfg_cmd_word |= | |
2130 | (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER); | |
2131 | atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word); | |
2132 | } | |
2133 | ||
2134 | /* Clear Interrupt mask to stop board from generating | |
2135 | * interrupts & Clear any pending interrupt events | |
2136 | */ | |
2137 | /* FIXME */ | |
2138 | /* ATL2_WRITE_REG(hw, REG_IMR, 0); */ | |
2139 | /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */ | |
2140 | ||
2141 | /* Issue Soft Reset to the MAC. This will reset the chip's | |
2142 | * transmit, receive, DMA. It will not effect | |
2143 | * the current PCI configuration. The global reset bit is self- | |
2144 | * clearing, and should clear within a microsecond. | |
2145 | */ | |
2146 | ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST); | |
2147 | wmb(); | |
2148 | msleep(1); /* delay about 1ms */ | |
2149 | ||
2150 | /* Wait at least 10ms for All module to be Idle */ | |
2151 | for (i = 0; i < 10; i++) { | |
2152 | icr = ATL2_READ_REG(hw, REG_IDLE_STATUS); | |
2153 | if (!icr) | |
2154 | break; | |
2155 | msleep(1); /* delay 1 ms */ | |
2156 | cpu_relax(); | |
2157 | } | |
2158 | ||
2159 | if (icr) | |
2160 | return icr; | |
2161 | ||
2162 | return 0; | |
2163 | } | |
2164 | ||
2165 | #define CUSTOM_SPI_CS_SETUP 2 | |
2166 | #define CUSTOM_SPI_CLK_HI 2 | |
2167 | #define CUSTOM_SPI_CLK_LO 2 | |
2168 | #define CUSTOM_SPI_CS_HOLD 2 | |
2169 | #define CUSTOM_SPI_CS_HI 3 | |
2170 | ||
2171 | static struct atl2_spi_flash_dev flash_table[] = | |
2172 | { | |
2173 | /* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */ | |
2174 | {"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 }, | |
2175 | {"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 }, | |
2176 | {"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 }, | |
2177 | }; | |
2178 | ||
2179 | static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf) | |
2180 | { | |
2181 | int i; | |
2182 | u32 value; | |
2183 | ||
2184 | ATL2_WRITE_REG(hw, REG_SPI_DATA, 0); | |
2185 | ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr); | |
2186 | ||
2187 | value = SPI_FLASH_CTRL_WAIT_READY | | |
2188 | (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) << | |
2189 | SPI_FLASH_CTRL_CS_SETUP_SHIFT | | |
2190 | (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) << | |
2191 | SPI_FLASH_CTRL_CLK_HI_SHIFT | | |
2192 | (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) << | |
2193 | SPI_FLASH_CTRL_CLK_LO_SHIFT | | |
2194 | (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) << | |
2195 | SPI_FLASH_CTRL_CS_HOLD_SHIFT | | |
2196 | (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) << | |
2197 | SPI_FLASH_CTRL_CS_HI_SHIFT | | |
2198 | (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT; | |
2199 | ||
2200 | ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | |
2201 | ||
2202 | value |= SPI_FLASH_CTRL_START; | |
2203 | ||
2204 | ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | |
2205 | ||
2206 | for (i = 0; i < 10; i++) { | |
2207 | msleep(1); | |
2208 | value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | |
2209 | if (!(value & SPI_FLASH_CTRL_START)) | |
2210 | break; | |
2211 | } | |
2212 | ||
2213 | if (value & SPI_FLASH_CTRL_START) | |
2214 | return false; | |
2215 | ||
2216 | *buf = ATL2_READ_REG(hw, REG_SPI_DATA); | |
2217 | ||
2218 | return true; | |
2219 | } | |
2220 | ||
2221 | /* | |
2222 | * get_permanent_address | |
2223 | * return 0 if get valid mac address, | |
2224 | */ | |
2225 | static int get_permanent_address(struct atl2_hw *hw) | |
2226 | { | |
2227 | u32 Addr[2]; | |
2228 | u32 i, Control; | |
2229 | u16 Register; | |
c81f2124 | 2230 | u8 EthAddr[ETH_ALEN]; |
452c1ce2 CS |
2231 | bool KeyValid; |
2232 | ||
2233 | if (is_valid_ether_addr(hw->perm_mac_addr)) | |
2234 | return 0; | |
2235 | ||
2236 | Addr[0] = 0; | |
2237 | Addr[1] = 0; | |
2238 | ||
2239 | if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */ | |
2240 | Register = 0; | |
2241 | KeyValid = false; | |
2242 | ||
2243 | /* Read out all EEPROM content */ | |
2244 | i = 0; | |
2245 | while (1) { | |
2246 | if (atl2_read_eeprom(hw, i + 0x100, &Control)) { | |
2247 | if (KeyValid) { | |
2248 | if (Register == REG_MAC_STA_ADDR) | |
2249 | Addr[0] = Control; | |
2250 | else if (Register == | |
2251 | (REG_MAC_STA_ADDR + 4)) | |
2252 | Addr[1] = Control; | |
2253 | KeyValid = false; | |
2254 | } else if ((Control & 0xff) == 0x5A) { | |
2255 | KeyValid = true; | |
2256 | Register = (u16) (Control >> 16); | |
2257 | } else { | |
2258 | /* assume data end while encount an invalid KEYWORD */ | |
2259 | break; | |
2260 | } | |
2261 | } else { | |
2262 | break; /* read error */ | |
2263 | } | |
2264 | i += 4; | |
2265 | } | |
2266 | ||
2267 | *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); | |
2268 | *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); | |
2269 | ||
2270 | if (is_valid_ether_addr(EthAddr)) { | |
c81f2124 | 2271 | memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); |
452c1ce2 CS |
2272 | return 0; |
2273 | } | |
2274 | return 1; | |
2275 | } | |
2276 | ||
2277 | /* see if SPI flash exists? */ | |
2278 | Addr[0] = 0; | |
2279 | Addr[1] = 0; | |
2280 | Register = 0; | |
2281 | KeyValid = false; | |
2282 | i = 0; | |
2283 | while (1) { | |
2284 | if (atl2_spi_read(hw, i + 0x1f000, &Control)) { | |
2285 | if (KeyValid) { | |
2286 | if (Register == REG_MAC_STA_ADDR) | |
2287 | Addr[0] = Control; | |
2288 | else if (Register == (REG_MAC_STA_ADDR + 4)) | |
2289 | Addr[1] = Control; | |
2290 | KeyValid = false; | |
2291 | } else if ((Control & 0xff) == 0x5A) { | |
2292 | KeyValid = true; | |
2293 | Register = (u16) (Control >> 16); | |
2294 | } else { | |
2295 | break; /* data end */ | |
2296 | } | |
2297 | } else { | |
2298 | break; /* read error */ | |
2299 | } | |
2300 | i += 4; | |
2301 | } | |
2302 | ||
2303 | *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); | |
2304 | *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]); | |
2305 | if (is_valid_ether_addr(EthAddr)) { | |
c81f2124 | 2306 | memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); |
452c1ce2 CS |
2307 | return 0; |
2308 | } | |
2309 | /* maybe MAC-address is from BIOS */ | |
2310 | Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR); | |
2311 | Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4); | |
2312 | *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]); | |
2313 | *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]); | |
2314 | ||
2315 | if (is_valid_ether_addr(EthAddr)) { | |
c81f2124 | 2316 | memcpy(hw->perm_mac_addr, EthAddr, ETH_ALEN); |
452c1ce2 CS |
2317 | return 0; |
2318 | } | |
2319 | ||
2320 | return 1; | |
2321 | } | |
2322 | ||
2323 | /* | |
2324 | * Reads the adapter's MAC address from the EEPROM | |
2325 | * | |
2326 | * hw - Struct containing variables accessed by shared code | |
2327 | */ | |
2328 | static s32 atl2_read_mac_addr(struct atl2_hw *hw) | |
2329 | { | |
452c1ce2 CS |
2330 | if (get_permanent_address(hw)) { |
2331 | /* for test */ | |
7efd26d0 | 2332 | /* FIXME: shouldn't we use eth_random_addr() here? */ |
452c1ce2 CS |
2333 | hw->perm_mac_addr[0] = 0x00; |
2334 | hw->perm_mac_addr[1] = 0x13; | |
2335 | hw->perm_mac_addr[2] = 0x74; | |
2336 | hw->perm_mac_addr[3] = 0x00; | |
2337 | hw->perm_mac_addr[4] = 0x5c; | |
2338 | hw->perm_mac_addr[5] = 0x38; | |
2339 | } | |
2340 | ||
c81f2124 | 2341 | memcpy(hw->mac_addr, hw->perm_mac_addr, ETH_ALEN); |
452c1ce2 CS |
2342 | |
2343 | return 0; | |
2344 | } | |
2345 | ||
2346 | /* | |
2347 | * Hashes an address to determine its location in the multicast table | |
2348 | * | |
2349 | * hw - Struct containing variables accessed by shared code | |
2350 | * mc_addr - the multicast address to hash | |
2351 | * | |
2352 | * atl2_hash_mc_addr | |
2353 | * purpose | |
2354 | * set hash value for a multicast address | |
2355 | * hash calcu processing : | |
2356 | * 1. calcu 32bit CRC for multicast address | |
2357 | * 2. reverse crc with MSB to LSB | |
2358 | */ | |
2359 | static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr) | |
2360 | { | |
2361 | u32 crc32, value; | |
2362 | int i; | |
2363 | ||
2364 | value = 0; | |
2365 | crc32 = ether_crc_le(6, mc_addr); | |
2366 | ||
2367 | for (i = 0; i < 32; i++) | |
2368 | value |= (((crc32 >> i) & 1) << (31 - i)); | |
2369 | ||
2370 | return value; | |
2371 | } | |
2372 | ||
2373 | /* | |
2374 | * Sets the bit in the multicast table corresponding to the hash value. | |
2375 | * | |
2376 | * hw - Struct containing variables accessed by shared code | |
2377 | * hash_value - Multicast address hash value | |
2378 | */ | |
2379 | static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value) | |
2380 | { | |
2381 | u32 hash_bit, hash_reg; | |
2382 | u32 mta; | |
2383 | ||
2384 | /* The HASH Table is a register array of 2 32-bit registers. | |
2385 | * It is treated like an array of 64 bits. We want to set | |
2386 | * bit BitArray[hash_value]. So we figure out what register | |
2387 | * the bit is in, read it, OR in the new bit, then write | |
2388 | * back the new value. The register is determined by the | |
2389 | * upper 7 bits of the hash value and the bit within that | |
2390 | * register are determined by the lower 5 bits of the value. | |
2391 | */ | |
2392 | hash_reg = (hash_value >> 31) & 0x1; | |
2393 | hash_bit = (hash_value >> 26) & 0x1F; | |
2394 | ||
2395 | mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); | |
2396 | ||
2397 | mta |= (1 << hash_bit); | |
2398 | ||
2399 | ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); | |
2400 | } | |
2401 | ||
2402 | /* | |
2403 | * atl2_init_pcie - init PCIE module | |
2404 | */ | |
2405 | static void atl2_init_pcie(struct atl2_hw *hw) | |
2406 | { | |
2407 | u32 value; | |
2408 | value = LTSSM_TEST_MODE_DEF; | |
2409 | ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value); | |
2410 | ||
2411 | value = PCIE_DLL_TX_CTRL1_DEF; | |
2412 | ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value); | |
2413 | } | |
2414 | ||
2415 | static void atl2_init_flash_opcode(struct atl2_hw *hw) | |
2416 | { | |
2417 | if (hw->flash_vendor >= ARRAY_SIZE(flash_table)) | |
2418 | hw->flash_vendor = 0; /* ATMEL */ | |
2419 | ||
2420 | /* Init OP table */ | |
2421 | ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM, | |
2422 | flash_table[hw->flash_vendor].cmdPROGRAM); | |
2423 | ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE, | |
2424 | flash_table[hw->flash_vendor].cmdSECTOR_ERASE); | |
2425 | ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE, | |
2426 | flash_table[hw->flash_vendor].cmdCHIP_ERASE); | |
2427 | ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID, | |
2428 | flash_table[hw->flash_vendor].cmdRDID); | |
2429 | ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN, | |
2430 | flash_table[hw->flash_vendor].cmdWREN); | |
2431 | ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR, | |
2432 | flash_table[hw->flash_vendor].cmdRDSR); | |
2433 | ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR, | |
2434 | flash_table[hw->flash_vendor].cmdWRSR); | |
2435 | ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ, | |
2436 | flash_table[hw->flash_vendor].cmdREAD); | |
2437 | } | |
2438 | ||
2439 | /******************************************************************** | |
2440 | * Performs basic configuration of the adapter. | |
2441 | * | |
2442 | * hw - Struct containing variables accessed by shared code | |
2443 | * Assumes that the controller has previously been reset and is in a | |
2444 | * post-reset uninitialized state. Initializes multicast table, | |
2445 | * and Calls routines to setup link | |
2446 | * Leaves the transmit and receive units disabled and uninitialized. | |
2447 | ********************************************************************/ | |
2448 | static s32 atl2_init_hw(struct atl2_hw *hw) | |
2449 | { | |
2450 | u32 ret_val = 0; | |
2451 | ||
2452 | atl2_init_pcie(hw); | |
2453 | ||
2454 | /* Zero out the Multicast HASH table */ | |
2455 | /* clear the old settings from the multicast hash table */ | |
2456 | ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0); | |
2457 | ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0); | |
2458 | ||
2459 | atl2_init_flash_opcode(hw); | |
2460 | ||
2461 | ret_val = atl2_phy_init(hw); | |
2462 | ||
2463 | return ret_val; | |
2464 | } | |
2465 | ||
2466 | /* | |
2467 | * Detects the current speed and duplex settings of the hardware. | |
2468 | * | |
2469 | * hw - Struct containing variables accessed by shared code | |
2470 | * speed - Speed of the connection | |
2471 | * duplex - Duplex setting of the connection | |
2472 | */ | |
2473 | static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed, | |
2474 | u16 *duplex) | |
2475 | { | |
2476 | s32 ret_val; | |
2477 | u16 phy_data; | |
2478 | ||
2479 | /* Read PHY Specific Status Register (17) */ | |
2480 | ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data); | |
2481 | if (ret_val) | |
2482 | return ret_val; | |
2483 | ||
2484 | if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED)) | |
2485 | return ATLX_ERR_PHY_RES; | |
2486 | ||
2487 | switch (phy_data & MII_ATLX_PSSR_SPEED) { | |
2488 | case MII_ATLX_PSSR_100MBS: | |
2489 | *speed = SPEED_100; | |
2490 | break; | |
2491 | case MII_ATLX_PSSR_10MBS: | |
2492 | *speed = SPEED_10; | |
2493 | break; | |
2494 | default: | |
2495 | return ATLX_ERR_PHY_SPEED; | |
452c1ce2 CS |
2496 | } |
2497 | ||
2498 | if (phy_data & MII_ATLX_PSSR_DPLX) | |
2499 | *duplex = FULL_DUPLEX; | |
2500 | else | |
2501 | *duplex = HALF_DUPLEX; | |
2502 | ||
2503 | return 0; | |
2504 | } | |
2505 | ||
2506 | /* | |
2507 | * Reads the value from a PHY register | |
2508 | * hw - Struct containing variables accessed by shared code | |
2509 | * reg_addr - address of the PHY register to read | |
2510 | */ | |
2511 | static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data) | |
2512 | { | |
2513 | u32 val; | |
2514 | int i; | |
2515 | ||
2516 | val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT | | |
2517 | MDIO_START | | |
2518 | MDIO_SUP_PREAMBLE | | |
2519 | MDIO_RW | | |
2520 | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | |
2521 | ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); | |
2522 | ||
2523 | wmb(); | |
2524 | ||
2525 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { | |
2526 | udelay(2); | |
2527 | val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | |
2528 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
2529 | break; | |
2530 | wmb(); | |
2531 | } | |
2532 | if (!(val & (MDIO_START | MDIO_BUSY))) { | |
2533 | *phy_data = (u16)val; | |
2534 | return 0; | |
2535 | } | |
2536 | ||
2537 | return ATLX_ERR_PHY; | |
2538 | } | |
2539 | ||
2540 | /* | |
2541 | * Writes a value to a PHY register | |
2542 | * hw - Struct containing variables accessed by shared code | |
2543 | * reg_addr - address of the PHY register to write | |
2544 | * data - data to write to the PHY | |
2545 | */ | |
2546 | static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data) | |
2547 | { | |
2548 | int i; | |
2549 | u32 val; | |
2550 | ||
2551 | val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT | | |
2552 | (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT | | |
2553 | MDIO_SUP_PREAMBLE | | |
2554 | MDIO_START | | |
2555 | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT; | |
2556 | ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val); | |
2557 | ||
2558 | wmb(); | |
2559 | ||
2560 | for (i = 0; i < MDIO_WAIT_TIMES; i++) { | |
2561 | udelay(2); | |
2562 | val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | |
2563 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
2564 | break; | |
2565 | ||
2566 | wmb(); | |
2567 | } | |
2568 | ||
2569 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
2570 | return 0; | |
2571 | ||
2572 | return ATLX_ERR_PHY; | |
2573 | } | |
2574 | ||
2575 | /* | |
2576 | * Configures PHY autoneg and flow control advertisement settings | |
2577 | * | |
2578 | * hw - Struct containing variables accessed by shared code | |
2579 | */ | |
2580 | static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw) | |
2581 | { | |
2582 | s32 ret_val; | |
2583 | s16 mii_autoneg_adv_reg; | |
2584 | ||
2585 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
2586 | mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK; | |
2587 | ||
2588 | /* Need to parse autoneg_advertised and set up | |
2589 | * the appropriate PHY registers. First we will parse for | |
2590 | * autoneg_advertised software override. Since we can advertise | |
2591 | * a plethora of combinations, we need to check each bit | |
2592 | * individually. | |
2593 | */ | |
2594 | ||
2595 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg | |
2596 | * Advertisement Register (Address 4) and the 1000 mb speed bits in | |
2597 | * the 1000Base-T Control Register (Address 9). */ | |
2598 | mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK; | |
2599 | ||
2600 | /* Need to parse MediaType and setup the | |
2601 | * appropriate PHY registers. */ | |
2602 | switch (hw->MediaType) { | |
2603 | case MEDIA_TYPE_AUTO_SENSOR: | |
2604 | mii_autoneg_adv_reg |= | |
2605 | (MII_AR_10T_HD_CAPS | | |
2606 | MII_AR_10T_FD_CAPS | | |
2607 | MII_AR_100TX_HD_CAPS| | |
2608 | MII_AR_100TX_FD_CAPS); | |
2609 | hw->autoneg_advertised = | |
2610 | ADVERTISE_10_HALF | | |
2611 | ADVERTISE_10_FULL | | |
2612 | ADVERTISE_100_HALF| | |
2613 | ADVERTISE_100_FULL; | |
2614 | break; | |
2615 | case MEDIA_TYPE_100M_FULL: | |
2616 | mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS; | |
2617 | hw->autoneg_advertised = ADVERTISE_100_FULL; | |
2618 | break; | |
2619 | case MEDIA_TYPE_100M_HALF: | |
2620 | mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS; | |
2621 | hw->autoneg_advertised = ADVERTISE_100_HALF; | |
2622 | break; | |
2623 | case MEDIA_TYPE_10M_FULL: | |
2624 | mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS; | |
2625 | hw->autoneg_advertised = ADVERTISE_10_FULL; | |
2626 | break; | |
2627 | default: | |
2628 | mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS; | |
2629 | hw->autoneg_advertised = ADVERTISE_10_HALF; | |
2630 | break; | |
2631 | } | |
2632 | ||
2633 | /* flow control fixed to enable all */ | |
2634 | mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE); | |
2635 | ||
2636 | hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg; | |
2637 | ||
2638 | ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg); | |
2639 | ||
2640 | if (ret_val) | |
2641 | return ret_val; | |
2642 | ||
2643 | return 0; | |
2644 | } | |
2645 | ||
2646 | /* | |
2647 | * Resets the PHY and make all config validate | |
2648 | * | |
2649 | * hw - Struct containing variables accessed by shared code | |
2650 | * | |
2651 | * Sets bit 15 and 12 of the MII Control regiser (for F001 bug) | |
2652 | */ | |
2653 | static s32 atl2_phy_commit(struct atl2_hw *hw) | |
2654 | { | |
2655 | s32 ret_val; | |
2656 | u16 phy_data; | |
2657 | ||
2658 | phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG; | |
2659 | ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data); | |
2660 | if (ret_val) { | |
2661 | u32 val; | |
2662 | int i; | |
2663 | /* pcie serdes link may be down ! */ | |
2664 | for (i = 0; i < 25; i++) { | |
2665 | msleep(1); | |
2666 | val = ATL2_READ_REG(hw, REG_MDIO_CTRL); | |
2667 | if (!(val & (MDIO_START | MDIO_BUSY))) | |
2668 | break; | |
2669 | } | |
2670 | ||
2671 | if (0 != (val & (MDIO_START | MDIO_BUSY))) { | |
2672 | printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n"); | |
2673 | return ret_val; | |
2674 | } | |
2675 | } | |
2676 | return 0; | |
2677 | } | |
2678 | ||
2679 | static s32 atl2_phy_init(struct atl2_hw *hw) | |
2680 | { | |
2681 | s32 ret_val; | |
2682 | u16 phy_val; | |
2683 | ||
2684 | if (hw->phy_configured) | |
2685 | return 0; | |
2686 | ||
2687 | /* Enable PHY */ | |
2688 | ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1); | |
2689 | ATL2_WRITE_FLUSH(hw); | |
2690 | msleep(1); | |
2691 | ||
2692 | /* check if the PHY is in powersaving mode */ | |
2693 | atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); | |
2694 | atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); | |
2695 | ||
2696 | /* 024E / 124E 0r 0274 / 1274 ? */ | |
2697 | if (phy_val & 0x1000) { | |
2698 | phy_val &= ~0x1000; | |
2699 | atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val); | |
2700 | } | |
2701 | ||
2702 | msleep(1); | |
2703 | ||
2704 | /*Enable PHY LinkChange Interrupt */ | |
2705 | ret_val = atl2_write_phy_reg(hw, 18, 0xC00); | |
2706 | if (ret_val) | |
2707 | return ret_val; | |
2708 | ||
2709 | /* setup AutoNeg parameters */ | |
2710 | ret_val = atl2_phy_setup_autoneg_adv(hw); | |
2711 | if (ret_val) | |
2712 | return ret_val; | |
2713 | ||
2714 | /* SW.Reset & En-Auto-Neg to restart Auto-Neg */ | |
2715 | ret_val = atl2_phy_commit(hw); | |
2716 | if (ret_val) | |
2717 | return ret_val; | |
2718 | ||
2719 | hw->phy_configured = true; | |
2720 | ||
2721 | return ret_val; | |
2722 | } | |
2723 | ||
2724 | static void atl2_set_mac_addr(struct atl2_hw *hw) | |
2725 | { | |
2726 | u32 value; | |
2727 | /* 00-0B-6A-F6-00-DC | |
2728 | * 0: 6AF600DC 1: 000B | |
2729 | * low dword */ | |
2730 | value = (((u32)hw->mac_addr[2]) << 24) | | |
2731 | (((u32)hw->mac_addr[3]) << 16) | | |
2732 | (((u32)hw->mac_addr[4]) << 8) | | |
2733 | (((u32)hw->mac_addr[5])); | |
2734 | ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); | |
2735 | /* hight dword */ | |
2736 | value = (((u32)hw->mac_addr[0]) << 8) | | |
2737 | (((u32)hw->mac_addr[1])); | |
2738 | ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); | |
2739 | } | |
2740 | ||
2741 | /* | |
2742 | * check_eeprom_exist | |
2743 | * return 0 if eeprom exist | |
2744 | */ | |
2745 | static int atl2_check_eeprom_exist(struct atl2_hw *hw) | |
2746 | { | |
2747 | u32 value; | |
2748 | ||
2749 | value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL); | |
2750 | if (value & SPI_FLASH_CTRL_EN_VPD) { | |
2751 | value &= ~SPI_FLASH_CTRL_EN_VPD; | |
2752 | ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value); | |
2753 | } | |
2754 | value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST); | |
2755 | return ((value & 0xFF00) == 0x6C00) ? 0 : 1; | |
2756 | } | |
2757 | ||
2758 | /* FIXME: This doesn't look right. -- CHS */ | |
2759 | static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value) | |
2760 | { | |
2761 | return true; | |
2762 | } | |
2763 | ||
2764 | static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue) | |
2765 | { | |
2766 | int i; | |
2767 | u32 Control; | |
2768 | ||
2769 | if (Offset & 0x3) | |
2770 | return false; /* address do not align */ | |
2771 | ||
2772 | ATL2_WRITE_REG(hw, REG_VPD_DATA, 0); | |
2773 | Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT; | |
2774 | ATL2_WRITE_REG(hw, REG_VPD_CAP, Control); | |
2775 | ||
2776 | for (i = 0; i < 10; i++) { | |
2777 | msleep(2); | |
2778 | Control = ATL2_READ_REG(hw, REG_VPD_CAP); | |
2779 | if (Control & VPD_CAP_VPD_FLAG) | |
2780 | break; | |
2781 | } | |
2782 | ||
2783 | if (Control & VPD_CAP_VPD_FLAG) { | |
2784 | *pValue = ATL2_READ_REG(hw, REG_VPD_DATA); | |
2785 | return true; | |
2786 | } | |
2787 | return false; /* timeout */ | |
2788 | } | |
2789 | ||
2790 | static void atl2_force_ps(struct atl2_hw *hw) | |
2791 | { | |
2792 | u16 phy_val; | |
2793 | ||
2794 | atl2_write_phy_reg(hw, MII_DBG_ADDR, 0); | |
2795 | atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val); | |
2796 | atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000); | |
2797 | ||
2798 | atl2_write_phy_reg(hw, MII_DBG_ADDR, 2); | |
2799 | atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000); | |
2800 | atl2_write_phy_reg(hw, MII_DBG_ADDR, 3); | |
2801 | atl2_write_phy_reg(hw, MII_DBG_DATA, 0); | |
2802 | } | |
2803 | ||
2804 | /* This is the only thing that needs to be changed to adjust the | |
2805 | * maximum number of ports that the driver can manage. | |
2806 | */ | |
2807 | #define ATL2_MAX_NIC 4 | |
2808 | ||
2809 | #define OPTION_UNSET -1 | |
2810 | #define OPTION_DISABLED 0 | |
2811 | #define OPTION_ENABLED 1 | |
2812 | ||
2813 | /* All parameters are treated the same, as an integer array of values. | |
2814 | * This macro just reduces the need to repeat the same declaration code | |
2815 | * over and over (plus this helps to avoid typo bugs). | |
2816 | */ | |
2817 | #define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET} | |
2818 | #ifndef module_param_array | |
2819 | /* Module Parameters are always initialized to -1, so that the driver | |
2820 | * can tell the difference between no user specified value or the | |
2821 | * user asking for the default value. | |
2822 | * The true default values are loaded in when atl2_check_options is called. | |
2823 | * | |
2824 | * This is a GCC extension to ANSI C. | |
2825 | * See the item "Labeled Elements in Initializers" in the section | |
2826 | * "Extensions to the C Language Family" of the GCC documentation. | |
2827 | */ | |
2828 | ||
2829 | #define ATL2_PARAM(X, desc) \ | |
093d369d | 2830 | static const int X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \ |
452c1ce2 CS |
2831 | MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \ |
2832 | MODULE_PARM_DESC(X, desc); | |
2833 | #else | |
2834 | #define ATL2_PARAM(X, desc) \ | |
093d369d | 2835 | static int X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \ |
b79d8fff | 2836 | static unsigned int num_##X; \ |
452c1ce2 CS |
2837 | module_param_array_named(X, X, int, &num_##X, 0); \ |
2838 | MODULE_PARM_DESC(X, desc); | |
2839 | #endif | |
2840 | ||
2841 | /* | |
2842 | * Transmit Memory Size | |
2843 | * Valid Range: 64-2048 | |
2844 | * Default Value: 128 | |
2845 | */ | |
2846 | #define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */ | |
2847 | #define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */ | |
2848 | #define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */ | |
2849 | ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory"); | |
2850 | ||
2851 | /* | |
2852 | * Receive Memory Block Count | |
2853 | * Valid Range: 16-512 | |
2854 | * Default Value: 128 | |
2855 | */ | |
2856 | #define ATL2_MIN_RXD_COUNT 16 | |
2857 | #define ATL2_MAX_RXD_COUNT 512 | |
2858 | #define ATL2_DEFAULT_RXD_COUNT 64 | |
2859 | ATL2_PARAM(RxMemBlock, "Number of receive memory block"); | |
2860 | ||
2861 | /* | |
2862 | * User Specified MediaType Override | |
2863 | * | |
2864 | * Valid Range: 0-5 | |
2865 | * - 0 - auto-negotiate at all supported speeds | |
2866 | * - 1 - only link at 1000Mbps Full Duplex | |
2867 | * - 2 - only link at 100Mbps Full Duplex | |
2868 | * - 3 - only link at 100Mbps Half Duplex | |
2869 | * - 4 - only link at 10Mbps Full Duplex | |
2870 | * - 5 - only link at 10Mbps Half Duplex | |
2871 | * Default Value: 0 | |
2872 | */ | |
2873 | ATL2_PARAM(MediaType, "MediaType Select"); | |
2874 | ||
2875 | /* | |
2876 | * Interrupt Moderate Timer in units of 2048 ns (~2 us) | |
2877 | * Valid Range: 10-65535 | |
2878 | * Default Value: 45000(90ms) | |
2879 | */ | |
2880 | #define INT_MOD_DEFAULT_CNT 100 /* 200us */ | |
2881 | #define INT_MOD_MAX_CNT 65000 | |
2882 | #define INT_MOD_MIN_CNT 50 | |
2883 | ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer"); | |
2884 | ||
2885 | /* | |
2886 | * FlashVendor | |
2887 | * Valid Range: 0-2 | |
2888 | * 0 - Atmel | |
2889 | * 1 - SST | |
2890 | * 2 - ST | |
2891 | */ | |
2892 | ATL2_PARAM(FlashVendor, "SPI Flash Vendor"); | |
2893 | ||
2894 | #define AUTONEG_ADV_DEFAULT 0x2F | |
2895 | #define AUTONEG_ADV_MASK 0x2F | |
2896 | #define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL | |
2897 | ||
2898 | #define FLASH_VENDOR_DEFAULT 0 | |
2899 | #define FLASH_VENDOR_MIN 0 | |
2900 | #define FLASH_VENDOR_MAX 2 | |
2901 | ||
2902 | struct atl2_option { | |
2903 | enum { enable_option, range_option, list_option } type; | |
2904 | char *name; | |
2905 | char *err; | |
2906 | int def; | |
2907 | union { | |
2908 | struct { /* range_option info */ | |
2909 | int min; | |
2910 | int max; | |
2911 | } r; | |
2912 | struct { /* list_option info */ | |
2913 | int nr; | |
2914 | struct atl2_opt_list { int i; char *str; } *p; | |
2915 | } l; | |
2916 | } arg; | |
2917 | }; | |
2918 | ||
093d369d | 2919 | static int atl2_validate_option(int *value, struct atl2_option *opt) |
452c1ce2 CS |
2920 | { |
2921 | int i; | |
2922 | struct atl2_opt_list *ent; | |
2923 | ||
2924 | if (*value == OPTION_UNSET) { | |
2925 | *value = opt->def; | |
2926 | return 0; | |
2927 | } | |
2928 | ||
2929 | switch (opt->type) { | |
2930 | case enable_option: | |
2931 | switch (*value) { | |
2932 | case OPTION_ENABLED: | |
2933 | printk(KERN_INFO "%s Enabled\n", opt->name); | |
2934 | return 0; | |
452c1ce2 CS |
2935 | case OPTION_DISABLED: |
2936 | printk(KERN_INFO "%s Disabled\n", opt->name); | |
2937 | return 0; | |
452c1ce2 CS |
2938 | } |
2939 | break; | |
2940 | case range_option: | |
2941 | if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { | |
2942 | printk(KERN_INFO "%s set to %i\n", opt->name, *value); | |
2943 | return 0; | |
2944 | } | |
2945 | break; | |
2946 | case list_option: | |
2947 | for (i = 0; i < opt->arg.l.nr; i++) { | |
2948 | ent = &opt->arg.l.p[i]; | |
2949 | if (*value == ent->i) { | |
2950 | if (ent->str[0] != '\0') | |
2951 | printk(KERN_INFO "%s\n", ent->str); | |
2952 | return 0; | |
2953 | } | |
2954 | } | |
2955 | break; | |
2956 | default: | |
2957 | BUG(); | |
2958 | } | |
2959 | ||
2960 | printk(KERN_INFO "Invalid %s specified (%i) %s\n", | |
2961 | opt->name, *value, opt->err); | |
2962 | *value = opt->def; | |
2963 | return -1; | |
2964 | } | |
2965 | ||
49ce9c2c | 2966 | /** |
452c1ce2 CS |
2967 | * atl2_check_options - Range Checking for Command Line Parameters |
2968 | * @adapter: board private structure | |
2969 | * | |
2970 | * This routine checks all command line parameters for valid user | |
2971 | * input. If an invalid value is given, or if no user specified | |
2972 | * value exists, a default value is used. The final value is stored | |
2973 | * in a variable in the adapter structure. | |
2974 | */ | |
093d369d | 2975 | static void atl2_check_options(struct atl2_adapter *adapter) |
452c1ce2 CS |
2976 | { |
2977 | int val; | |
2978 | struct atl2_option opt; | |
2979 | int bd = adapter->bd_number; | |
2980 | if (bd >= ATL2_MAX_NIC) { | |
2981 | printk(KERN_NOTICE "Warning: no configuration for board #%i\n", | |
2982 | bd); | |
2983 | printk(KERN_NOTICE "Using defaults for all values\n"); | |
2984 | #ifndef module_param_array | |
2985 | bd = ATL2_MAX_NIC; | |
2986 | #endif | |
2987 | } | |
2988 | ||
2989 | /* Bytes of Transmit Memory */ | |
2990 | opt.type = range_option; | |
2991 | opt.name = "Bytes of Transmit Memory"; | |
2992 | opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE); | |
2993 | opt.def = ATL2_DEFAULT_TX_MEMSIZE; | |
2994 | opt.arg.r.min = ATL2_MIN_TX_MEMSIZE; | |
2995 | opt.arg.r.max = ATL2_MAX_TX_MEMSIZE; | |
2996 | #ifdef module_param_array | |
2997 | if (num_TxMemSize > bd) { | |
2998 | #endif | |
2999 | val = TxMemSize[bd]; | |
3000 | atl2_validate_option(&val, &opt); | |
3001 | adapter->txd_ring_size = ((u32) val) * 1024; | |
3002 | #ifdef module_param_array | |
3003 | } else | |
3004 | adapter->txd_ring_size = ((u32)opt.def) * 1024; | |
3005 | #endif | |
3006 | /* txs ring size: */ | |
3007 | adapter->txs_ring_size = adapter->txd_ring_size / 128; | |
3008 | if (adapter->txs_ring_size > 160) | |
3009 | adapter->txs_ring_size = 160; | |
3010 | ||
3011 | /* Receive Memory Block Count */ | |
3012 | opt.type = range_option; | |
3013 | opt.name = "Number of receive memory block"; | |
3014 | opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT); | |
3015 | opt.def = ATL2_DEFAULT_RXD_COUNT; | |
3016 | opt.arg.r.min = ATL2_MIN_RXD_COUNT; | |
3017 | opt.arg.r.max = ATL2_MAX_RXD_COUNT; | |
3018 | #ifdef module_param_array | |
3019 | if (num_RxMemBlock > bd) { | |
3020 | #endif | |
3021 | val = RxMemBlock[bd]; | |
3022 | atl2_validate_option(&val, &opt); | |
3023 | adapter->rxd_ring_size = (u32)val; | |
3024 | /* FIXME */ | |
3025 | /* ((u16)val)&~1; */ /* even number */ | |
3026 | #ifdef module_param_array | |
3027 | } else | |
3028 | adapter->rxd_ring_size = (u32)opt.def; | |
3029 | #endif | |
3030 | /* init RXD Flow control value */ | |
3031 | adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7; | |
3032 | adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) > | |
3033 | (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) : | |
3034 | (adapter->rxd_ring_size / 12); | |
3035 | ||
3036 | /* Interrupt Moderate Timer */ | |
3037 | opt.type = range_option; | |
3038 | opt.name = "Interrupt Moderate Timer"; | |
3039 | opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT); | |
3040 | opt.def = INT_MOD_DEFAULT_CNT; | |
3041 | opt.arg.r.min = INT_MOD_MIN_CNT; | |
3042 | opt.arg.r.max = INT_MOD_MAX_CNT; | |
3043 | #ifdef module_param_array | |
3044 | if (num_IntModTimer > bd) { | |
3045 | #endif | |
3046 | val = IntModTimer[bd]; | |
3047 | atl2_validate_option(&val, &opt); | |
3048 | adapter->imt = (u16) val; | |
3049 | #ifdef module_param_array | |
3050 | } else | |
3051 | adapter->imt = (u16)(opt.def); | |
3052 | #endif | |
3053 | /* Flash Vendor */ | |
3054 | opt.type = range_option; | |
3055 | opt.name = "SPI Flash Vendor"; | |
3056 | opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT); | |
3057 | opt.def = FLASH_VENDOR_DEFAULT; | |
3058 | opt.arg.r.min = FLASH_VENDOR_MIN; | |
3059 | opt.arg.r.max = FLASH_VENDOR_MAX; | |
3060 | #ifdef module_param_array | |
3061 | if (num_FlashVendor > bd) { | |
3062 | #endif | |
3063 | val = FlashVendor[bd]; | |
3064 | atl2_validate_option(&val, &opt); | |
3065 | adapter->hw.flash_vendor = (u8) val; | |
3066 | #ifdef module_param_array | |
3067 | } else | |
3068 | adapter->hw.flash_vendor = (u8)(opt.def); | |
3069 | #endif | |
3070 | /* MediaType */ | |
3071 | opt.type = range_option; | |
3072 | opt.name = "Speed/Duplex Selection"; | |
3073 | opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR); | |
3074 | opt.def = MEDIA_TYPE_AUTO_SENSOR; | |
3075 | opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR; | |
3076 | opt.arg.r.max = MEDIA_TYPE_10M_HALF; | |
3077 | #ifdef module_param_array | |
3078 | if (num_MediaType > bd) { | |
3079 | #endif | |
3080 | val = MediaType[bd]; | |
3081 | atl2_validate_option(&val, &opt); | |
3082 | adapter->hw.MediaType = (u16) val; | |
3083 | #ifdef module_param_array | |
3084 | } else | |
3085 | adapter->hw.MediaType = (u16)(opt.def); | |
3086 | #endif | |
3087 | } |