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net: systemport: Implement TX coalescing control knobs
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bcmsysport.c
CommitLineData
80105bef
FF		 1/*
2 * Broadcom BCM7xxx System Port Ethernet MAC driver
3 *
4 * Copyright (C) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/netdevice.h>
18#include <linux/etherdevice.h>
19#include <linux/platform_device.h>
20#include <linux/of.h>
21#include <linux/of_net.h>
22#include <linux/of_mdio.h>
23#include <linux/phy.h>
24#include <linux/phy_fixed.h>
25#include <net/ip.h>
26#include <net/ipv6.h>
27
28#include "bcmsysport.h"
29
30/* I/O accessors register helpers */
31#define BCM_SYSPORT_IO_MACRO(name, offset) \
32static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \
33{ \
34 u32 reg = __raw_readl(priv->base + offset + off); \
35 return reg; \
36} \
37static inline void name##_writel(struct bcm_sysport_priv *priv, \
38 u32 val, u32 off) \
39{ \
40 __raw_writel(val, priv->base + offset + off); \
41} \
42
43BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);
44BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET);
45BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET);
46BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET);
47BCM_SYSPORT_IO_MACRO(rdma, SYS_PORT_RDMA_OFFSET);
48BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET);
49BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET);
50BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET);
51BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET);
52BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET);
53
54/* L2-interrupt masking/unmasking helpers, does automatic saving of the applied
55 * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths.
56 */
57#define BCM_SYSPORT_INTR_L2(which) \
58static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \
59 u32 mask) \
60{ \
61 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
62 priv->irq##which##_mask &= ~(mask); \
63} \
64static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \
65 u32 mask) \
66{ \
67 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
68 priv->irq##which##_mask |= (mask); \
69} \
70
71BCM_SYSPORT_INTR_L2(0)
72BCM_SYSPORT_INTR_L2(1)
73
74/* Register accesses to GISB/RBUS registers are expensive (few hundred
75 * nanoseconds), so keep the check for 64-bits explicit here to save
76 * one register write per-packet on 32-bits platforms.
77 */
78static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,
79 void __iomem *d,
80 dma_addr_t addr)
81{
82#ifdef CONFIG_PHYS_ADDR_T_64BIT
83 __raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK,
23acb2fc 84 d + DESC_ADDR_HI_STATUS_LEN);
80105bef
FF		 85#endif
86 __raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO);
87}
88
89static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,
23acb2fc
FF		 90 struct dma_desc *desc,
91 unsigned int port)
80105bef
FF		 92{
93 /* Ports are latched, so write upper address first */
94 tdma_writel(priv, desc->addr_status_len, TDMA_WRITE_PORT_HI(port));
95 tdma_writel(priv, desc->addr_lo, TDMA_WRITE_PORT_LO(port));
96}
97
98/* Ethtool operations */
99static int bcm_sysport_set_settings(struct net_device *dev,
100 struct ethtool_cmd *cmd)
101{
102 struct bcm_sysport_priv *priv = netdev_priv(dev);
103
104 if (!netif_running(dev))
105 return -EINVAL;
106
107 return phy_ethtool_sset(priv->phydev, cmd);
108}
109
110static int bcm_sysport_get_settings(struct net_device *dev,
23acb2fc 111 struct ethtool_cmd *cmd)
80105bef
FF		 112{
113 struct bcm_sysport_priv *priv = netdev_priv(dev);
114
115 if (!netif_running(dev))
116 return -EINVAL;
117
118 return phy_ethtool_gset(priv->phydev, cmd);
119}
120
121static int bcm_sysport_set_rx_csum(struct net_device *dev,
23acb2fc 122 netdev_features_t wanted)
80105bef
FF		 123{
124 struct bcm_sysport_priv *priv = netdev_priv(dev);
125 u32 reg;
126
9d34c1cb 127 priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM);
80105bef 128 reg = rxchk_readl(priv, RXCHK_CONTROL);
9d34c1cb 129 if (priv->rx_chk_en)
80105bef
FF		 130 reg |= RXCHK_EN;
131 else
132 reg &= ~RXCHK_EN;
133
134 /* If UniMAC forwards CRC, we need to skip over it to get
135 * a valid CHK bit to be set in the per-packet status word
136 */
9d34c1cb 137 if (priv->rx_chk_en && priv->crc_fwd)
80105bef
FF		 138 reg |= RXCHK_SKIP_FCS;
139 else
140 reg &= ~RXCHK_SKIP_FCS;
141
d09d3038
FF		 142 /* If Broadcom tags are enabled (e.g: using a switch), make
143 * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
144 * tag after the Ethernet MAC Source Address.
145 */
146 if (netdev_uses_dsa(dev))
147 reg |= RXCHK_BRCM_TAG_EN;
148 else
149 reg &= ~RXCHK_BRCM_TAG_EN;
150
80105bef
FF		 151 rxchk_writel(priv, reg, RXCHK_CONTROL);
152
153 return 0;
154}
155
156static int bcm_sysport_set_tx_csum(struct net_device *dev,
23acb2fc 157 netdev_features_t wanted)
80105bef
FF		 158{
159 struct bcm_sysport_priv *priv = netdev_priv(dev);
160 u32 reg;
161
162 /* Hardware transmit checksum requires us to enable the Transmit status
163 * block prepended to the packet contents
164 */
165 priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
166 reg = tdma_readl(priv, TDMA_CONTROL);
167 if (priv->tsb_en)
168 reg |= TSB_EN;
169 else
170 reg &= ~TSB_EN;
171 tdma_writel(priv, reg, TDMA_CONTROL);
172
173 return 0;
174}
175
176static int bcm_sysport_set_features(struct net_device *dev,
23acb2fc 177 netdev_features_t features)
80105bef
FF		 178{
179 netdev_features_t changed = features ^ dev->features;
180 netdev_features_t wanted = dev->wanted_features;
181 int ret = 0;
182
183 if (changed & NETIF_F_RXCSUM)
184 ret = bcm_sysport_set_rx_csum(dev, wanted);
185 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
186 ret = bcm_sysport_set_tx_csum(dev, wanted);
187
188 return ret;
189}
190
191/* Hardware counters must be kept in sync because the order/offset
192 * is important here (order in structure declaration = order in hardware)
193 */
194static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = {
195 /* general stats */
196 STAT_NETDEV(rx_packets),
197 STAT_NETDEV(tx_packets),
198 STAT_NETDEV(rx_bytes),
199 STAT_NETDEV(tx_bytes),
200 STAT_NETDEV(rx_errors),
201 STAT_NETDEV(tx_errors),
202 STAT_NETDEV(rx_dropped),
203 STAT_NETDEV(tx_dropped),
204 STAT_NETDEV(multicast),
205 /* UniMAC RSV counters */
206 STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
207 STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
208 STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
209 STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
210 STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
211 STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
212 STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
213 STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
214 STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
215 STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
216 STAT_MIB_RX("rx_pkts", mib.rx.pkt),
217 STAT_MIB_RX("rx_bytes", mib.rx.bytes),
218 STAT_MIB_RX("rx_multicast", mib.rx.mca),
219 STAT_MIB_RX("rx_broadcast", mib.rx.bca),
220 STAT_MIB_RX("rx_fcs", mib.rx.fcs),
221 STAT_MIB_RX("rx_control", mib.rx.cf),
222 STAT_MIB_RX("rx_pause", mib.rx.pf),
223 STAT_MIB_RX("rx_unknown", mib.rx.uo),
224 STAT_MIB_RX("rx_align", mib.rx.aln),
225 STAT_MIB_RX("rx_outrange", mib.rx.flr),
226 STAT_MIB_RX("rx_code", mib.rx.cde),
227 STAT_MIB_RX("rx_carrier", mib.rx.fcr),
228 STAT_MIB_RX("rx_oversize", mib.rx.ovr),
229 STAT_MIB_RX("rx_jabber", mib.rx.jbr),
230 STAT_MIB_RX("rx_mtu_err", mib.rx.mtue),
231 STAT_MIB_RX("rx_good_pkts", mib.rx.pok),
232 STAT_MIB_RX("rx_unicast", mib.rx.uc),
233 STAT_MIB_RX("rx_ppp", mib.rx.ppp),
234 STAT_MIB_RX("rx_crc", mib.rx.rcrc),
235 /* UniMAC TSV counters */
236 STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
237 STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
238 STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
239 STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
240 STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
241 STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
242 STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
243 STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
244 STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
245 STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
246 STAT_MIB_TX("tx_pkts", mib.tx.pkts),
247 STAT_MIB_TX("tx_multicast", mib.tx.mca),
248 STAT_MIB_TX("tx_broadcast", mib.tx.bca),
249 STAT_MIB_TX("tx_pause", mib.tx.pf),
250 STAT_MIB_TX("tx_control", mib.tx.cf),
251 STAT_MIB_TX("tx_fcs_err", mib.tx.fcs),
252 STAT_MIB_TX("tx_oversize", mib.tx.ovr),
253 STAT_MIB_TX("tx_defer", mib.tx.drf),
254 STAT_MIB_TX("tx_excess_defer", mib.tx.edf),
255 STAT_MIB_TX("tx_single_col", mib.tx.scl),
256 STAT_MIB_TX("tx_multi_col", mib.tx.mcl),
257 STAT_MIB_TX("tx_late_col", mib.tx.lcl),
258 STAT_MIB_TX("tx_excess_col", mib.tx.ecl),
259 STAT_MIB_TX("tx_frags", mib.tx.frg),
260 STAT_MIB_TX("tx_total_col", mib.tx.ncl),
261 STAT_MIB_TX("tx_jabber", mib.tx.jbr),
262 STAT_MIB_TX("tx_bytes", mib.tx.bytes),
263 STAT_MIB_TX("tx_good_pkts", mib.tx.pok),
264 STAT_MIB_TX("tx_unicast", mib.tx.uc),
265 /* UniMAC RUNT counters */
266 STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
267 STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
268 STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
269 STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
270 /* RXCHK misc statistics */
271 STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR),
272 STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc,
23acb2fc 273 RXCHK_OTHER_DISC_CNTR),
80105bef
FF		 274 /* RBUF misc statistics */
275 STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR),
276 STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR),
55ff4ea9
FF		 277 STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
278 STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed),
279 STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed),
80105bef
FF		 280};
281
282#define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats)
283
284static void bcm_sysport_get_drvinfo(struct net_device *dev,
23acb2fc 285 struct ethtool_drvinfo *info)
80105bef
FF		 286{
287 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
288 strlcpy(info->version, "0.1", sizeof(info->version));
289 strlcpy(info->bus_info, "platform", sizeof(info->bus_info));
290 info->n_stats = BCM_SYSPORT_STATS_LEN;
291}
292
293static u32 bcm_sysport_get_msglvl(struct net_device *dev)
294{
295 struct bcm_sysport_priv *priv = netdev_priv(dev);
296
297 return priv->msg_enable;
298}
299
300static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable)
301{
302 struct bcm_sysport_priv *priv = netdev_priv(dev);
303
304 priv->msg_enable = enable;
305}
306
307static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set)
308{
309 switch (string_set) {
310 case ETH_SS_STATS:
311 return BCM_SYSPORT_STATS_LEN;
312 default:
313 return -EOPNOTSUPP;
314 }
315}
316
317static void bcm_sysport_get_strings(struct net_device *dev,
23acb2fc 318 u32 stringset, u8 *data)
80105bef
FF		 319{
320 int i;
321
322 switch (stringset) {
323 case ETH_SS_STATS:
324 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
325 memcpy(data + i * ETH_GSTRING_LEN,
23acb2fc
FF		 326 bcm_sysport_gstrings_stats[i].stat_string,
327 ETH_GSTRING_LEN);
80105bef
FF		 328 }
329 break;
330 default:
331 break;
332 }
333}
334
335static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv)
336{
337 int i, j = 0;
338
339 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
340 const struct bcm_sysport_stats *s;
341 u8 offset = 0;
342 u32 val = 0;
343 char *p;
344
345 s = &bcm_sysport_gstrings_stats[i];
346 switch (s->type) {
347 case BCM_SYSPORT_STAT_NETDEV:
55ff4ea9 348 case BCM_SYSPORT_STAT_SOFT:
80105bef
FF		 349 continue;
350 case BCM_SYSPORT_STAT_MIB_RX:
351 case BCM_SYSPORT_STAT_MIB_TX:
352 case BCM_SYSPORT_STAT_RUNT:
353 if (s->type != BCM_SYSPORT_STAT_MIB_RX)
354 offset = UMAC_MIB_STAT_OFFSET;
355 val = umac_readl(priv, UMAC_MIB_START + j + offset);
356 break;
357 case BCM_SYSPORT_STAT_RXCHK:
358 val = rxchk_readl(priv, s->reg_offset);
359 if (val == ~0)
360 rxchk_writel(priv, 0, s->reg_offset);
361 break;
362 case BCM_SYSPORT_STAT_RBUF:
363 val = rbuf_readl(priv, s->reg_offset);
364 if (val == ~0)
365 rbuf_writel(priv, 0, s->reg_offset);
366 break;
367 }
368
369 j += s->stat_sizeof;
370 p = (char *)priv + s->stat_offset;
371 *(u32 *)p = val;
372 }
373
374 netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n");
375}
376
377static void bcm_sysport_get_stats(struct net_device *dev,
23acb2fc 378 struct ethtool_stats *stats, u64 *data)
80105bef
FF		 379{
380 struct bcm_sysport_priv *priv = netdev_priv(dev);
381 int i;
382
383 if (netif_running(dev))
384 bcm_sysport_update_mib_counters(priv);
385
386 for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) {
387 const struct bcm_sysport_stats *s;
388 char *p;
389
390 s = &bcm_sysport_gstrings_stats[i];
391 if (s->type == BCM_SYSPORT_STAT_NETDEV)
392 p = (char *)&dev->stats;
393 else
394 p = (char *)priv;
395 p += s->stat_offset;
396 data[i] = *(u32 *)p;
397 }
398}
399
83e82f4c
FF		 400static void bcm_sysport_get_wol(struct net_device *dev,
401 struct ethtool_wolinfo *wol)
402{
403 struct bcm_sysport_priv *priv = netdev_priv(dev);
404 u32 reg;
405
406 wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE;
407 wol->wolopts = priv->wolopts;
408
409 if (!(priv->wolopts & WAKE_MAGICSECURE))
410 return;
411
412 /* Return the programmed SecureOn password */
413 reg = umac_readl(priv, UMAC_PSW_MS);
414 put_unaligned_be16(reg, &wol->sopass[0]);
415 reg = umac_readl(priv, UMAC_PSW_LS);
416 put_unaligned_be32(reg, &wol->sopass[2]);
417}
418
419static int bcm_sysport_set_wol(struct net_device *dev,
23acb2fc 420 struct ethtool_wolinfo *wol)
83e82f4c
FF		 421{
422 struct bcm_sysport_priv *priv = netdev_priv(dev);
423 struct device *kdev = &priv->pdev->dev;
424 u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE;
425
426 if (!device_can_wakeup(kdev))
427 return -ENOTSUPP;
428
429 if (wol->wolopts & ~supported)
430 return -EINVAL;
431
432 /* Program the SecureOn password */
433 if (wol->wolopts & WAKE_MAGICSECURE) {
434 umac_writel(priv, get_unaligned_be16(&wol->sopass[0]),
23acb2fc 435 UMAC_PSW_MS);
83e82f4c 436 umac_writel(priv, get_unaligned_be32(&wol->sopass[2]),
23acb2fc 437 UMAC_PSW_LS);
83e82f4c
FF		 438 }
439
440 /* Flag the device and relevant IRQ as wakeup capable */
441 if (wol->wolopts) {
442 device_set_wakeup_enable(kdev, 1);
61b423a8
FF		 443 if (priv->wol_irq_disabled)
444 enable_irq_wake(priv->wol_irq);
83e82f4c
FF		 445 priv->wol_irq_disabled = 0;
446 } else {
447 device_set_wakeup_enable(kdev, 0);
448 /* Avoid unbalanced disable_irq_wake calls */
449 if (!priv->wol_irq_disabled)
450 disable_irq_wake(priv->wol_irq);
451 priv->wol_irq_disabled = 1;
452 }
453
454 priv->wolopts = wol->wolopts;
455
456 return 0;
457}
458
b1a15e86
FF		 459static int bcm_sysport_get_coalesce(struct net_device *dev,
460 struct ethtool_coalesce *ec)
461{
462 struct bcm_sysport_priv *priv = netdev_priv(dev);
463 u32 reg;
464
465 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0));
466
467 ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000;
468 ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK;
469
470 return 0;
471}
472
473static int bcm_sysport_set_coalesce(struct net_device *dev,
474 struct ethtool_coalesce *ec)
475{
476 struct bcm_sysport_priv *priv = netdev_priv(dev);
477 unsigned int i;
478 u32 reg;
479
480 /* Base system clock is 125Mhz, TDMA timeout is this reference clock
481 * divided by 1024, which yield roughly 8.192 us, our maximum value
482 * has to fit in the RING_TIMEOUT_MASK (16 bits).
483 */
484 if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK ||
485 ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1)
486 return -EINVAL;
487
488 if (ec->tx_coalesce_usecs == 0 &&
489 ec->tx_max_coalesced_frames == 0)
490 return -EINVAL;
491
492 for (i = 0; i < dev->num_tx_queues; i++) {
493 reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i));
494 reg &= ~(RING_INTR_THRESH_MASK |
495 RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT);
496 reg |= ec->tx_max_coalesced_frames;
497 reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) <<
498 RING_TIMEOUT_SHIFT;
499 tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i));
500 }
501
502 return 0;
503}
504
80105bef
FF		 505static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb)
506{
507 dev_kfree_skb_any(cb->skb);
508 cb->skb = NULL;
509 dma_unmap_addr_set(cb, dma_addr, 0);
510}
511
512static int bcm_sysport_rx_refill(struct bcm_sysport_priv *priv,
513 struct bcm_sysport_cb *cb)
514{
515 struct device *kdev = &priv->pdev->dev;
516 struct net_device *ndev = priv->netdev;
517 dma_addr_t mapping;
518 int ret;
519
520 cb->skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH);
521 if (!cb->skb) {
522 netif_err(priv, rx_err, ndev, "SKB alloc failed\n");
523 return -ENOMEM;
524 }
525
526 mapping = dma_map_single(kdev, cb->skb->data,
23acb2fc 527 RX_BUF_LENGTH, DMA_FROM_DEVICE);
80105bef
FF		 528 ret = dma_mapping_error(kdev, mapping);
529 if (ret) {
60b4ea17 530 priv->mib.rx_dma_failed++;
80105bef
FF		 531 bcm_sysport_free_cb(cb);
532 netif_err(priv, rx_err, ndev, "DMA mapping failure\n");
533 return ret;
534 }
535
536 dma_unmap_addr_set(cb, dma_addr, mapping);
537 dma_desc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
538
539 priv->rx_bd_assign_index++;
540 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
541 priv->rx_bd_assign_ptr = priv->rx_bds +
542 (priv->rx_bd_assign_index * DESC_SIZE);
543
544 netif_dbg(priv, rx_status, ndev, "RX refill\n");
545
546 return 0;
547}
548
549static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv)
550{
551 struct bcm_sysport_cb *cb;
552 int ret = 0;
553 unsigned int i;
554
555 for (i = 0; i < priv->num_rx_bds; i++) {
556 cb = &priv->rx_cbs[priv->rx_bd_assign_index];
557 if (cb->skb)
558 continue;
559
560 ret = bcm_sysport_rx_refill(priv, cb);
561 if (ret)
562 break;
563 }
564
565 return ret;
566}
567
568/* Poll the hardware for up to budget packets to process */
569static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv,
570 unsigned int budget)
571{
572 struct device *kdev = &priv->pdev->dev;
573 struct net_device *ndev = priv->netdev;
574 unsigned int processed = 0, to_process;
575 struct bcm_sysport_cb *cb;
576 struct sk_buff *skb;
577 unsigned int p_index;
578 u16 len, status;
3afc557d 579 struct bcm_rsb *rsb;
60b4ea17 580 int ret;
80105bef
FF		 581
582 /* Determine how much we should process since last call */
583 p_index = rdma_readl(priv, RDMA_PROD_INDEX);
584 p_index &= RDMA_PROD_INDEX_MASK;
585
586 if (p_index < priv->rx_c_index)
587 to_process = (RDMA_CONS_INDEX_MASK + 1) -
588 priv->rx_c_index + p_index;
589 else
590 to_process = p_index - priv->rx_c_index;
591
592 netif_dbg(priv, rx_status, ndev,
23acb2fc
FF		 593 "p_index=%d rx_c_index=%d to_process=%d\n",
594 p_index, priv->rx_c_index, to_process);
80105bef 595
23acb2fc 596 while ((processed < to_process) && (processed < budget)) {
80105bef
FF		 597 cb = &priv->rx_cbs[priv->rx_read_ptr];
598 skb = cb->skb;
fe24ba08
FF		 599
600 processed++;
601 priv->rx_read_ptr++;
602
603 if (priv->rx_read_ptr == priv->num_rx_bds)
604 priv->rx_read_ptr = 0;
605
606 /* We do not have a backing SKB, so we do not a corresponding
607 * DMA mapping for this incoming packet since
608 * bcm_sysport_rx_refill always either has both skb and mapping
609 * or none.
610 */
611 if (unlikely(!skb)) {
612 netif_err(priv, rx_err, ndev, "out of memory!\n");
613 ndev->stats.rx_dropped++;
614 ndev->stats.rx_errors++;
615 goto refill;
616 }
617
80105bef 618 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
23acb2fc 619 RX_BUF_LENGTH, DMA_FROM_DEVICE);
80105bef
FF		 620
621 /* Extract the Receive Status Block prepended */
3afc557d 622 rsb = (struct bcm_rsb *)skb->data;
80105bef
FF		 623 len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK;
624 status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) &
23acb2fc 625 DESC_STATUS_MASK;
80105bef 626
80105bef 627 netif_dbg(priv, rx_status, ndev,
23acb2fc
FF		 628 "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n",
629 p_index, priv->rx_c_index, priv->rx_read_ptr,
630 len, status);
80105bef 631
80105bef
FF		 632 if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) {
633 netif_err(priv, rx_status, ndev, "fragmented packet!\n");
634 ndev->stats.rx_dropped++;
635 ndev->stats.rx_errors++;
636 bcm_sysport_free_cb(cb);
637 goto refill;
638 }
639
640 if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) {
641 netif_err(priv, rx_err, ndev, "error packet\n");
ad51c610 642 if (status & RX_STATUS_OVFLOW)
80105bef
FF		 643 ndev->stats.rx_over_errors++;
644 ndev->stats.rx_dropped++;
645 ndev->stats.rx_errors++;
646 bcm_sysport_free_cb(cb);
647 goto refill;
648 }
649
650 skb_put(skb, len);
651
652 /* Hardware validated our checksum */
653 if (likely(status & DESC_L4_CSUM))
654 skb->ip_summed = CHECKSUM_UNNECESSARY;
655
e0ea05d0
FF		 656 /* Hardware pre-pends packets with 2bytes before Ethernet
657 * header plus we have the Receive Status Block, strip off all
658 * of this from the SKB.
80105bef
FF		 659 */
660 skb_pull(skb, sizeof(*rsb) + 2);
661 len -= (sizeof(*rsb) + 2);
662
663 /* UniMAC may forward CRC */
664 if (priv->crc_fwd) {
665 skb_trim(skb, len - ETH_FCS_LEN);
666 len -= ETH_FCS_LEN;
667 }
668
669 skb->protocol = eth_type_trans(skb, ndev);
670 ndev->stats.rx_packets++;
671 ndev->stats.rx_bytes += len;
672
673 napi_gro_receive(&priv->napi, skb);
674refill:
60b4ea17
FF		 675 ret = bcm_sysport_rx_refill(priv, cb);
676 if (ret)
677 priv->mib.alloc_rx_buff_failed++;
80105bef
FF		 678 }
679
680 return processed;
681}
682
683static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_priv *priv,
23acb2fc
FF		 684 struct bcm_sysport_cb *cb,
685 unsigned int *bytes_compl,
686 unsigned int *pkts_compl)
80105bef
FF		 687{
688 struct device *kdev = &priv->pdev->dev;
689 struct net_device *ndev = priv->netdev;
690
691 if (cb->skb) {
692 ndev->stats.tx_bytes += cb->skb->len;
693 *bytes_compl += cb->skb->len;
694 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
23acb2fc
FF		 695 dma_unmap_len(cb, dma_len),
696 DMA_TO_DEVICE);
80105bef
FF		 697 ndev->stats.tx_packets++;
698 (*pkts_compl)++;
699 bcm_sysport_free_cb(cb);
700 /* SKB fragment */
701 } else if (dma_unmap_addr(cb, dma_addr)) {
702 ndev->stats.tx_bytes += dma_unmap_len(cb, dma_len);
703 dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr),
23acb2fc 704 dma_unmap_len(cb, dma_len), DMA_TO_DEVICE);
80105bef
FF		 705 dma_unmap_addr_set(cb, dma_addr, 0);
706 }
707}
708
709/* Reclaim queued SKBs for transmission completion, lockless version */
710static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
711 struct bcm_sysport_tx_ring *ring)
712{
713 struct net_device *ndev = priv->netdev;
714 unsigned int c_index, last_c_index, last_tx_cn, num_tx_cbs;
715 unsigned int pkts_compl = 0, bytes_compl = 0;
716 struct bcm_sysport_cb *cb;
717 struct netdev_queue *txq;
718 u32 hw_ind;
719
720 txq = netdev_get_tx_queue(ndev, ring->index);
721
722 /* Compute how many descriptors have been processed since last call */
723 hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index));
724 c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK;
725 ring->p_index = (hw_ind & RING_PROD_INDEX_MASK);
726
727 last_c_index = ring->c_index;
728 num_tx_cbs = ring->size;
729
730 c_index &= (num_tx_cbs - 1);
731
732 if (c_index >= last_c_index)
733 last_tx_cn = c_index - last_c_index;
734 else
735 last_tx_cn = num_tx_cbs - last_c_index + c_index;
736
737 netif_dbg(priv, tx_done, ndev,
23acb2fc
FF		 738 "ring=%d c_index=%d last_tx_cn=%d last_c_index=%d\n",
739 ring->index, c_index, last_tx_cn, last_c_index);
80105bef
FF		 740
741 while (last_tx_cn-- > 0) {
742 cb = ring->cbs + last_c_index;
743 bcm_sysport_tx_reclaim_one(priv, cb, &bytes_compl, &pkts_compl);
744
745 ring->desc_count++;
746 last_c_index++;
747 last_c_index &= (num_tx_cbs - 1);
748 }
749
750 ring->c_index = c_index;
751
752 if (netif_tx_queue_stopped(txq) && pkts_compl)
753 netif_tx_wake_queue(txq);
754
755 netif_dbg(priv, tx_done, ndev,
23acb2fc
FF		 756 "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n",
757 ring->index, ring->c_index, pkts_compl, bytes_compl);
80105bef
FF		 758
759 return pkts_compl;
760}
761
762/* Locked version of the per-ring TX reclaim routine */
763static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv,
764 struct bcm_sysport_tx_ring *ring)
765{
766 unsigned int released;
d8498088 767 unsigned long flags;
80105bef 768
d8498088 769 spin_lock_irqsave(&ring->lock, flags);
80105bef 770 released = __bcm_sysport_tx_reclaim(priv, ring);
d8498088 771 spin_unlock_irqrestore(&ring->lock, flags);
80105bef
FF		 772
773 return released;
774}
775
776static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget)
777{
778 struct bcm_sysport_tx_ring *ring =
779 container_of(napi, struct bcm_sysport_tx_ring, napi);
780 unsigned int work_done = 0;
781
782 work_done = bcm_sysport_tx_reclaim(ring->priv, ring);
783
16f62d9b 784 if (work_done == 0) {
80105bef
FF		 785 napi_complete(napi);
786 /* re-enable TX interrupt */
787 intrl2_1_mask_clear(ring->priv, BIT(ring->index));
9dfa9a27
FF		 788
789 return 0;
80105bef
FF		 790 }
791
9dfa9a27 792 return budget;
80105bef
FF		 793}
794
795static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv)
796{
797 unsigned int q;
798
799 for (q = 0; q < priv->netdev->num_tx_queues; q++)
800 bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]);
801}
802
803static int bcm_sysport_poll(struct napi_struct *napi, int budget)
804{
805 struct bcm_sysport_priv *priv =
806 container_of(napi, struct bcm_sysport_priv, napi);
807 unsigned int work_done = 0;
808
809 work_done = bcm_sysport_desc_rx(priv, budget);
810
811 priv->rx_c_index += work_done;
812 priv->rx_c_index &= RDMA_CONS_INDEX_MASK;
813 rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX);
814
815 if (work_done < budget) {
816 napi_complete(napi);
817 /* re-enable RX interrupts */
818 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE);
819 }
820
821 return work_done;
822}
823
83e82f4c
FF		 824static void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv)
825{
826 u32 reg;
827
828 /* Stop monitoring MPD interrupt */
829 intrl2_0_mask_set(priv, INTRL2_0_MPD);
830
831 /* Clear the MagicPacket detection logic */
832 reg = umac_readl(priv, UMAC_MPD_CTRL);
833 reg &= ~MPD_EN;
834 umac_writel(priv, reg, UMAC_MPD_CTRL);
835
836 netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n");
837}
80105bef
FF		 838
839/* RX and misc interrupt routine */
840static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id)
841{
842 struct net_device *dev = dev_id;
843 struct bcm_sysport_priv *priv = netdev_priv(dev);
844
845 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
846 ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
847 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
848
849 if (unlikely(priv->irq0_stat == 0)) {
850 netdev_warn(priv->netdev, "spurious RX interrupt\n");
851 return IRQ_NONE;
852 }
853
854 if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) {
855 if (likely(napi_schedule_prep(&priv->napi))) {
856 /* disable RX interrupts */
857 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE);
858 __napi_schedule(&priv->napi);
859 }
860 }
861
862 /* TX ring is full, perform a full reclaim since we do not know
863 * which one would trigger this interrupt
864 */
865 if (priv->irq0_stat & INTRL2_0_TX_RING_FULL)
866 bcm_sysport_tx_reclaim_all(priv);
867
83e82f4c
FF		 868 if (priv->irq0_stat & INTRL2_0_MPD) {
869 netdev_info(priv->netdev, "Wake-on-LAN interrupt!\n");
870 bcm_sysport_resume_from_wol(priv);
871 }
872
80105bef
FF		 873 return IRQ_HANDLED;
874}
875
876/* TX interrupt service routine */
877static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id)
878{
879 struct net_device *dev = dev_id;
880 struct bcm_sysport_priv *priv = netdev_priv(dev);
881 struct bcm_sysport_tx_ring *txr;
882 unsigned int ring;
883
884 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
885 ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
886 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
887
888 if (unlikely(priv->irq1_stat == 0)) {
889 netdev_warn(priv->netdev, "spurious TX interrupt\n");
890 return IRQ_NONE;
891 }
892
893 for (ring = 0; ring < dev->num_tx_queues; ring++) {
894 if (!(priv->irq1_stat & BIT(ring)))
895 continue;
896
897 txr = &priv->tx_rings[ring];
898
899 if (likely(napi_schedule_prep(&txr->napi))) {
900 intrl2_1_mask_set(priv, BIT(ring));
901 __napi_schedule(&txr->napi);
902 }
903 }
904
905 return IRQ_HANDLED;
906}
907
83e82f4c
FF		 908static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id)
909{
910 struct bcm_sysport_priv *priv = dev_id;
911
912 pm_wakeup_event(&priv->pdev->dev, 0);
913
914 return IRQ_HANDLED;
915}
916
e87474a6
FF		 917static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb,
918 struct net_device *dev)
80105bef
FF		 919{
920 struct sk_buff *nskb;
3afc557d 921 struct bcm_tsb *tsb;
80105bef
FF		 922 u32 csum_info;
923 u8 ip_proto;
924 u16 csum_start;
925 u16 ip_ver;
926
927 /* Re-allocate SKB if needed */
928 if (unlikely(skb_headroom(skb) < sizeof(*tsb))) {
929 nskb = skb_realloc_headroom(skb, sizeof(*tsb));
930 dev_kfree_skb(skb);
931 if (!nskb) {
932 dev->stats.tx_errors++;
933 dev->stats.tx_dropped++;
e87474a6 934 return NULL;
80105bef
FF		 935 }
936 skb = nskb;
937 }
938
3afc557d 939 tsb = (struct bcm_tsb *)skb_push(skb, sizeof(*tsb));
80105bef
FF		 940 /* Zero-out TSB by default */
941 memset(tsb, 0, sizeof(*tsb));
942
943 if (skb->ip_summed == CHECKSUM_PARTIAL) {
944 ip_ver = htons(skb->protocol);
945 switch (ip_ver) {
946 case ETH_P_IP:
947 ip_proto = ip_hdr(skb)->protocol;
948 break;
949 case ETH_P_IPV6:
950 ip_proto = ipv6_hdr(skb)->nexthdr;
951 break;
952 default:
e87474a6 953 return skb;
80105bef
FF		 954 }
955
956 /* Get the checksum offset and the L4 (transport) offset */
957 csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb);
958 csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK;
959 csum_info |= (csum_start << L4_PTR_SHIFT);
960
961 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
962 csum_info |= L4_LENGTH_VALID;
963 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
964 csum_info |= L4_UDP;
23acb2fc 965 } else {
80105bef 966 csum_info = 0;
23acb2fc 967 }
80105bef
FF		 968
969 tsb->l4_ptr_dest_map = csum_info;
970 }
971
e87474a6 972 return skb;
80105bef
FF		 973}
974
975static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb,
976 struct net_device *dev)
977{
978 struct bcm_sysport_priv *priv = netdev_priv(dev);
979 struct device *kdev = &priv->pdev->dev;
980 struct bcm_sysport_tx_ring *ring;
981 struct bcm_sysport_cb *cb;
982 struct netdev_queue *txq;
983 struct dma_desc *desc;
dab531b4 984 unsigned int skb_len;
d8498088 985 unsigned long flags;
80105bef
FF		 986 dma_addr_t mapping;
987 u32 len_status;
988 u16 queue;
989 int ret;
990
991 queue = skb_get_queue_mapping(skb);
992 txq = netdev_get_tx_queue(dev, queue);
993 ring = &priv->tx_rings[queue];
994
d8498088
FF		 995 /* lock against tx reclaim in BH context and TX ring full interrupt */
996 spin_lock_irqsave(&ring->lock, flags);
80105bef
FF		 997 if (unlikely(ring->desc_count == 0)) {
998 netif_tx_stop_queue(txq);
999 netdev_err(dev, "queue %d awake and ring full!\n", queue);
1000 ret = NETDEV_TX_BUSY;
1001 goto out;
1002 }
1003
1004 /* Insert TSB and checksum infos */
1005 if (priv->tsb_en) {
e87474a6
FF		 1006 skb = bcm_sysport_insert_tsb(skb, dev);
1007 if (!skb) {
80105bef
FF		 1008 ret = NETDEV_TX_OK;
1009 goto out;
1010 }
1011 }
1012
dab531b4
FF		 1013 /* The Ethernet switch we are interfaced with needs packets to be at
1014 * least 64 bytes (including FCS) otherwise they will be discarded when
1015 * they enter the switch port logic. When Broadcom tags are enabled, we
1016 * need to make sure that packets are at least 68 bytes
1017 * (including FCS and tag) because the length verification is done after
1018 * the Broadcom tag is stripped off the ingress packet.
1019 */
1020 if (skb_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) {
1021 ret = NETDEV_TX_OK;
1022 goto out;
1023 }
1024
1025 skb_len = skb->len < ETH_ZLEN + ENET_BRCM_TAG_LEN ?
1026 ETH_ZLEN + ENET_BRCM_TAG_LEN : skb->len;
1027
1028 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
80105bef 1029 if (dma_mapping_error(kdev, mapping)) {
60b4ea17 1030 priv->mib.tx_dma_failed++;
80105bef 1031 netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n",
23acb2fc 1032 skb->data, skb_len);
80105bef
FF		 1033 ret = NETDEV_TX_OK;
1034 goto out;
1035 }
1036
1037 /* Remember the SKB for future freeing */
1038 cb = &ring->cbs[ring->curr_desc];
1039 cb->skb = skb;
1040 dma_unmap_addr_set(cb, dma_addr, mapping);
dab531b4 1041 dma_unmap_len_set(cb, dma_len, skb_len);
80105bef
FF		 1042
1043 /* Fetch a descriptor entry from our pool */
1044 desc = ring->desc_cpu;
1045
1046 desc->addr_lo = lower_32_bits(mapping);
1047 len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK;
dab531b4 1048 len_status |= (skb_len << DESC_LEN_SHIFT);
80105bef 1049 len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) <<
23acb2fc 1050 DESC_STATUS_SHIFT;
80105bef
FF		 1051 if (skb->ip_summed == CHECKSUM_PARTIAL)
1052 len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT);
1053
1054 ring->curr_desc++;
1055 if (ring->curr_desc == ring->size)
1056 ring->curr_desc = 0;
1057 ring->desc_count--;
1058
1059 /* Ensure write completion of the descriptor status/length
1060 * in DRAM before the System Port WRITE_PORT register latches
1061 * the value
1062 */
1063 wmb();
1064 desc->addr_status_len = len_status;
1065 wmb();
1066
1067 /* Write this descriptor address to the RING write port */
1068 tdma_port_write_desc_addr(priv, desc, ring->index);
1069
1070 /* Check ring space and update SW control flow */
1071 if (ring->desc_count == 0)
1072 netif_tx_stop_queue(txq);
1073
1074 netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n",
23acb2fc 1075 ring->index, ring->desc_count, ring->curr_desc);
80105bef
FF		 1076
1077 ret = NETDEV_TX_OK;
1078out:
d8498088 1079 spin_unlock_irqrestore(&ring->lock, flags);
80105bef
FF		 1080 return ret;
1081}
1082
1083static void bcm_sysport_tx_timeout(struct net_device *dev)
1084{
1085 netdev_warn(dev, "transmit timeout!\n");
1086
1087 dev->trans_start = jiffies;
1088 dev->stats.tx_errors++;
1089
1090 netif_tx_wake_all_queues(dev);
1091}
1092
1093/* phylib adjust link callback */
1094static void bcm_sysport_adj_link(struct net_device *dev)
1095{
1096 struct bcm_sysport_priv *priv = netdev_priv(dev);
1097 struct phy_device *phydev = priv->phydev;
1098 unsigned int changed = 0;
1099 u32 cmd_bits = 0, reg;
1100
1101 if (priv->old_link != phydev->link) {
1102 changed = 1;
1103 priv->old_link = phydev->link;
1104 }
1105
1106 if (priv->old_duplex != phydev->duplex) {
1107 changed = 1;
1108 priv->old_duplex = phydev->duplex;
1109 }
1110
1111 switch (phydev->speed) {
1112 case SPEED_2500:
1113 cmd_bits = CMD_SPEED_2500;
1114 break;
1115 case SPEED_1000:
1116 cmd_bits = CMD_SPEED_1000;
1117 break;
1118 case SPEED_100:
1119 cmd_bits = CMD_SPEED_100;
1120 break;
1121 case SPEED_10:
1122 cmd_bits = CMD_SPEED_10;
1123 break;
1124 default:
1125 break;
1126 }
1127 cmd_bits <<= CMD_SPEED_SHIFT;
1128
1129 if (phydev->duplex == DUPLEX_HALF)
1130 cmd_bits |= CMD_HD_EN;
1131
1132 if (priv->old_pause != phydev->pause) {
1133 changed = 1;
1134 priv->old_pause = phydev->pause;
1135 }
1136
1137 if (!phydev->pause)
1138 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
1139
4a804c01
FF		 1140 if (!changed)
1141 return;
1142
1143 if (phydev->link) {
d5e32cc7
FF		 1144 reg = umac_readl(priv, UMAC_CMD);
1145 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
80105bef
FF		 1146 CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
1147 CMD_TX_PAUSE_IGNORE);
d5e32cc7
FF		 1148 reg |= cmd_bits;
1149 umac_writel(priv, reg, UMAC_CMD);
d5e32cc7 1150 }
4a804c01
FF		 1151
1152 phy_print_status(priv->phydev);
80105bef
FF		 1153}
1154
1155static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
1156 unsigned int index)
1157{
1158 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1159 struct device *kdev = &priv->pdev->dev;
1160 size_t size;
1161 void *p;
1162 u32 reg;
1163
1164 /* Simple descriptors partitioning for now */
1165 size = 256;
1166
1167 /* We just need one DMA descriptor which is DMA-able, since writing to
1168 * the port will allocate a new descriptor in its internal linked-list
1169 */
3e8fc38c
FF		 1170 p = dma_zalloc_coherent(kdev, sizeof(struct dma_desc), &ring->desc_dma,
1171 GFP_KERNEL);
80105bef
FF		 1172 if (!p) {
1173 netif_err(priv, hw, priv->netdev, "DMA alloc failed\n");
1174 return -ENOMEM;
1175 }
1176
40a8a317 1177 ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL);
80105bef
FF		 1178 if (!ring->cbs) {
1179 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1180 return -ENOMEM;
1181 }
1182
1183 /* Initialize SW view of the ring */
1184 spin_lock_init(&ring->lock);
1185 ring->priv = priv;
1186 netif_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64);
1187 ring->index = index;
1188 ring->size = size;
1189 ring->alloc_size = ring->size;
1190 ring->desc_cpu = p;
1191 ring->desc_count = ring->size;
1192 ring->curr_desc = 0;
1193
1194 /* Initialize HW ring */
1195 tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index));
1196 tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index));
1197 tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index));
1198 tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index));
1199 tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index));
1200 tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
1201
1202 /* Program the number of descriptors as MAX_THRESHOLD and half of
1203 * its size for the hysteresis trigger
1204 */
1205 tdma_writel(priv, ring->size |
1206 1 << RING_HYST_THRESH_SHIFT,
1207 TDMA_DESC_RING_MAX_HYST(index));
1208
1209 /* Enable the ring queue in the arbiter */
1210 reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN);
1211 reg |= (1 << index);
1212 tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN);
1213
1214 napi_enable(&ring->napi);
1215
1216 netif_dbg(priv, hw, priv->netdev,
23acb2fc
FF		 1217 "TDMA cfg, size=%d, desc_cpu=%p\n",
1218 ring->size, ring->desc_cpu);
80105bef
FF		 1219
1220 return 0;
1221}
1222
1223static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv,
23acb2fc 1224 unsigned int index)
80105bef
FF		 1225{
1226 struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index];
1227 struct device *kdev = &priv->pdev->dev;
1228 u32 reg;
1229
1230 /* Caller should stop the TDMA engine */
1231 reg = tdma_readl(priv, TDMA_STATUS);
1232 if (!(reg & TDMA_DISABLED))
1233 netdev_warn(priv->netdev, "TDMA not stopped!\n");
1234
914adb55
FF		 1235 /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could
1236 * fail, so by checking this pointer we know whether the TX ring was
1237 * fully initialized or not.
1238 */
1239 if (!ring->cbs)
1240 return;
1241
80105bef
FF		 1242 napi_disable(&ring->napi);
1243 netif_napi_del(&ring->napi);
1244
1245 bcm_sysport_tx_reclaim(priv, ring);
1246
1247 kfree(ring->cbs);
1248 ring->cbs = NULL;
1249
1250 if (ring->desc_dma) {
3e8fc38c
FF		 1251 dma_free_coherent(kdev, sizeof(struct dma_desc),
1252 ring->desc_cpu, ring->desc_dma);
80105bef
FF		 1253 ring->desc_dma = 0;
1254 }
1255 ring->size = 0;
1256 ring->alloc_size = 0;
1257
1258 netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n");
1259}
1260
1261/* RDMA helper */
1262static inline int rdma_enable_set(struct bcm_sysport_priv *priv,
23acb2fc 1263 unsigned int enable)
80105bef
FF		 1264{
1265 unsigned int timeout = 1000;
1266 u32 reg;
1267
1268 reg = rdma_readl(priv, RDMA_CONTROL);
1269 if (enable)
1270 reg |= RDMA_EN;
1271 else
1272 reg &= ~RDMA_EN;
1273 rdma_writel(priv, reg, RDMA_CONTROL);
1274
1275 /* Poll for RMDA disabling completion */
1276 do {
1277 reg = rdma_readl(priv, RDMA_STATUS);
1278 if (!!(reg & RDMA_DISABLED) == !enable)
1279 return 0;
1280 usleep_range(1000, 2000);
1281 } while (timeout-- > 0);
1282
1283 netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n");
1284
1285 return -ETIMEDOUT;
1286}
1287
1288/* TDMA helper */
1289static inline int tdma_enable_set(struct bcm_sysport_priv *priv,
23acb2fc 1290 unsigned int enable)
80105bef
FF		 1291{
1292 unsigned int timeout = 1000;
1293 u32 reg;
1294
1295 reg = tdma_readl(priv, TDMA_CONTROL);
1296 if (enable)
1297 reg |= TDMA_EN;
1298 else
1299 reg &= ~TDMA_EN;
1300 tdma_writel(priv, reg, TDMA_CONTROL);
1301
1302 /* Poll for TMDA disabling completion */
1303 do {
1304 reg = tdma_readl(priv, TDMA_STATUS);
1305 if (!!(reg & TDMA_DISABLED) == !enable)
1306 return 0;
1307
1308 usleep_range(1000, 2000);
1309 } while (timeout-- > 0);
1310
1311 netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n");
1312
1313 return -ETIMEDOUT;
1314}
1315
1316static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv)
1317{
1318 u32 reg;
1319 int ret;
1320
1321 /* Initialize SW view of the RX ring */
1322 priv->num_rx_bds = NUM_RX_DESC;
1323 priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET;
1324 priv->rx_bd_assign_ptr = priv->rx_bds;
1325 priv->rx_bd_assign_index = 0;
1326 priv->rx_c_index = 0;
1327 priv->rx_read_ptr = 0;
40a8a317
FF		 1328 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb),
1329 GFP_KERNEL);
80105bef
FF		 1330 if (!priv->rx_cbs) {
1331 netif_err(priv, hw, priv->netdev, "CB allocation failed\n");
1332 return -ENOMEM;
1333 }
1334
1335 ret = bcm_sysport_alloc_rx_bufs(priv);
1336 if (ret) {
1337 netif_err(priv, hw, priv->netdev, "SKB allocation failed\n");
1338 return ret;
1339 }
1340
1341 /* Initialize HW, ensure RDMA is disabled */
1342 reg = rdma_readl(priv, RDMA_STATUS);
1343 if (!(reg & RDMA_DISABLED))
1344 rdma_enable_set(priv, 0);
1345
1346 rdma_writel(priv, 0, RDMA_WRITE_PTR_LO);
1347 rdma_writel(priv, 0, RDMA_WRITE_PTR_HI);
1348 rdma_writel(priv, 0, RDMA_PROD_INDEX);
1349 rdma_writel(priv, 0, RDMA_CONS_INDEX);
1350 rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT |
1351 RX_BUF_LENGTH, RDMA_RING_BUF_SIZE);
1352 /* Operate the queue in ring mode */
1353 rdma_writel(priv, 0, RDMA_START_ADDR_HI);
1354 rdma_writel(priv, 0, RDMA_START_ADDR_LO);
1355 rdma_writel(priv, 0, RDMA_END_ADDR_HI);
1356 rdma_writel(priv, NUM_HW_RX_DESC_WORDS - 1, RDMA_END_ADDR_LO);
1357
1358 rdma_writel(priv, 1, RDMA_MBDONE_INTR);
1359
1360 netif_dbg(priv, hw, priv->netdev,
23acb2fc
FF		 1361 "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n",
1362 priv->num_rx_bds, priv->rx_bds);
80105bef
FF		 1363
1364 return 0;
1365}
1366
1367static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv)
1368{
1369 struct bcm_sysport_cb *cb;
1370 unsigned int i;
1371 u32 reg;
1372
1373 /* Caller should ensure RDMA is disabled */
1374 reg = rdma_readl(priv, RDMA_STATUS);
1375 if (!(reg & RDMA_DISABLED))
1376 netdev_warn(priv->netdev, "RDMA not stopped!\n");
1377
1378 for (i = 0; i < priv->num_rx_bds; i++) {
1379 cb = &priv->rx_cbs[i];
1380 if (dma_unmap_addr(cb, dma_addr))
1381 dma_unmap_single(&priv->pdev->dev,
23acb2fc
FF		 1382 dma_unmap_addr(cb, dma_addr),
1383 RX_BUF_LENGTH, DMA_FROM_DEVICE);
80105bef
FF		 1384 bcm_sysport_free_cb(cb);
1385 }
1386
1387 kfree(priv->rx_cbs);
1388 priv->rx_cbs = NULL;
1389
1390 netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n");
1391}
1392
1393static void bcm_sysport_set_rx_mode(struct net_device *dev)
1394{
1395 struct bcm_sysport_priv *priv = netdev_priv(dev);
1396 u32 reg;
1397
1398 reg = umac_readl(priv, UMAC_CMD);
1399 if (dev->flags & IFF_PROMISC)
1400 reg |= CMD_PROMISC;
1401 else
1402 reg &= ~CMD_PROMISC;
1403 umac_writel(priv, reg, UMAC_CMD);
1404
1405 /* No support for ALLMULTI */
1406 if (dev->flags & IFF_ALLMULTI)
1407 return;
1408}
1409
1410static inline void umac_enable_set(struct bcm_sysport_priv *priv,
23acb2fc 1411 u32 mask, unsigned int enable)
80105bef
FF		 1412{
1413 u32 reg;
1414
1415 reg = umac_readl(priv, UMAC_CMD);
1416 if (enable)
18e21b01 1417 reg |= mask;
80105bef 1418 else
18e21b01 1419 reg &= ~mask;
80105bef 1420 umac_writel(priv, reg, UMAC_CMD);
00b91c69
FF		 1421
1422 /* UniMAC stops on a packet boundary, wait for a full-sized packet
1423 * to be processed (1 msec).
1424 */
1425 if (enable == 0)
1426 usleep_range(1000, 2000);
80105bef
FF		 1427}
1428
412bce83 1429static inline void umac_reset(struct bcm_sysport_priv *priv)
80105bef 1430{
80105bef 1431 u32 reg;
80105bef 1432
412bce83
FF		 1433 reg = umac_readl(priv, UMAC_CMD);
1434 reg |= CMD_SW_RESET;
1435 umac_writel(priv, reg, UMAC_CMD);
1436 udelay(10);
1437 reg = umac_readl(priv, UMAC_CMD);
1438 reg &= ~CMD_SW_RESET;
1439 umac_writel(priv, reg, UMAC_CMD);
80105bef
FF		 1440}
1441
1442static void umac_set_hw_addr(struct bcm_sysport_priv *priv,
23acb2fc 1443 unsigned char *addr)
80105bef
FF		 1444{
1445 umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
1446 (addr[2] << 8) | addr[3], UMAC_MAC0);
1447 umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
1448}
1449
1450static void topctrl_flush(struct bcm_sysport_priv *priv)
1451{
1452 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
1453 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1454 mdelay(1);
1455 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1456 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
1457}
1458
fb3b596d
FF		 1459static int bcm_sysport_change_mac(struct net_device *dev, void *p)
1460{
1461 struct bcm_sysport_priv *priv = netdev_priv(dev);
1462 struct sockaddr *addr = p;
1463
1464 if (!is_valid_ether_addr(addr->sa_data))
1465 return -EINVAL;
1466
1467 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1468
1469 /* interface is disabled, changes to MAC will be reflected on next
1470 * open call
1471 */
1472 if (!netif_running(dev))
1473 return 0;
1474
1475 umac_set_hw_addr(priv, dev->dev_addr);
1476
1477 return 0;
1478}
1479
b02e6d9b
FF		 1480static void bcm_sysport_netif_start(struct net_device *dev)
1481{
1482 struct bcm_sysport_priv *priv = netdev_priv(dev);
1483
1484 /* Enable NAPI */
1485 napi_enable(&priv->napi);
1486
8edf0047
FF		 1487 /* Enable RX interrupt and TX ring full interrupt */
1488 intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1489
b02e6d9b
FF		 1490 phy_start(priv->phydev);
1491
1492 /* Enable TX interrupts for the 32 TXQs */
1493 intrl2_1_mask_clear(priv, 0xffffffff);
1494
1495 /* Last call before we start the real business */
1496 netif_tx_start_all_queues(dev);
1497}
1498
40755a0f
FF		 1499static void rbuf_init(struct bcm_sysport_priv *priv)
1500{
1501 u32 reg;
1502
1503 reg = rbuf_readl(priv, RBUF_CONTROL);
1504 reg |= RBUF_4B_ALGN | RBUF_RSB_EN;
1505 rbuf_writel(priv, reg, RBUF_CONTROL);
1506}
1507
80105bef
FF		 1508static int bcm_sysport_open(struct net_device *dev)
1509{
1510 struct bcm_sysport_priv *priv = netdev_priv(dev);
1511 unsigned int i;
80105bef
FF		 1512 int ret;
1513
1514 /* Reset UniMAC */
412bce83 1515 umac_reset(priv);
80105bef
FF		 1516
1517 /* Flush TX and RX FIFOs at TOPCTRL level */
1518 topctrl_flush(priv);
1519
1520 /* Disable the UniMAC RX/TX */
18e21b01 1521 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0);
80105bef
FF		 1522
1523 /* Enable RBUF 2bytes alignment and Receive Status Block */
40755a0f 1524 rbuf_init(priv);
80105bef
FF		 1525
1526 /* Set maximum frame length */
1527 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1528
1529 /* Set MAC address */
1530 umac_set_hw_addr(priv, dev->dev_addr);
1531
1532 /* Read CRC forward */
1533 priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD);
1534
186534a3
FF		 1535 priv->phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link,
1536 0, priv->phy_interface);
80105bef
FF		 1537 if (!priv->phydev) {
1538 netdev_err(dev, "could not attach to PHY\n");
1539 return -ENODEV;
1540 }
1541
1542 /* Reset house keeping link status */
1543 priv->old_duplex = -1;
1544 priv->old_link = -1;
1545 priv->old_pause = -1;
1546
1547 /* mask all interrupts and request them */
1548 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1549 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1550 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1551 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
1552 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1553 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1554
1555 ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev);
1556 if (ret) {
1557 netdev_err(dev, "failed to request RX interrupt\n");
1558 goto out_phy_disconnect;
1559 }
1560
1561 ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, dev->name, dev);
1562 if (ret) {
1563 netdev_err(dev, "failed to request TX interrupt\n");
1564 goto out_free_irq0;
1565 }
1566
1567 /* Initialize both hardware and software ring */
1568 for (i = 0; i < dev->num_tx_queues; i++) {
1569 ret = bcm_sysport_init_tx_ring(priv, i);
1570 if (ret) {
1571 netdev_err(dev, "failed to initialize TX ring %d\n",
23acb2fc 1572 i);
80105bef
FF		 1573 goto out_free_tx_ring;
1574 }
1575 }
1576
1577 /* Initialize linked-list */
1578 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1579
1580 /* Initialize RX ring */
1581 ret = bcm_sysport_init_rx_ring(priv);
1582 if (ret) {
1583 netdev_err(dev, "failed to initialize RX ring\n");
1584 goto out_free_rx_ring;
1585 }
1586
1587 /* Turn on RDMA */
1588 ret = rdma_enable_set(priv, 1);
1589 if (ret)
1590 goto out_free_rx_ring;
1591
80105bef
FF		 1592 /* Turn on TDMA */
1593 ret = tdma_enable_set(priv, 1);
1594 if (ret)
1595 goto out_clear_rx_int;
1596
80105bef 1597 /* Turn on UniMAC TX/RX */
18e21b01 1598 umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1);
80105bef 1599
b02e6d9b 1600 bcm_sysport_netif_start(dev);
80105bef
FF		 1601
1602 return 0;
1603
1604out_clear_rx_int:
1605 intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL);
1606out_free_rx_ring:
1607 bcm_sysport_fini_rx_ring(priv);
1608out_free_tx_ring:
1609 for (i = 0; i < dev->num_tx_queues; i++)
1610 bcm_sysport_fini_tx_ring(priv, i);
1611 free_irq(priv->irq1, dev);
1612out_free_irq0:
1613 free_irq(priv->irq0, dev);
1614out_phy_disconnect:
1615 phy_disconnect(priv->phydev);
1616 return ret;
1617}
1618
b02e6d9b 1619static void bcm_sysport_netif_stop(struct net_device *dev)
80105bef
FF		 1620{
1621 struct bcm_sysport_priv *priv = netdev_priv(dev);
80105bef
FF		 1622
1623 /* stop all software from updating hardware */
1624 netif_tx_stop_all_queues(dev);
1625 napi_disable(&priv->napi);
1626 phy_stop(priv->phydev);
1627
1628 /* mask all interrupts */
1629 intrl2_0_mask_set(priv, 0xffffffff);
1630 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
1631 intrl2_1_mask_set(priv, 0xffffffff);
1632 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
b02e6d9b
FF		 1633}
1634
1635static int bcm_sysport_stop(struct net_device *dev)
1636{
1637 struct bcm_sysport_priv *priv = netdev_priv(dev);
1638 unsigned int i;
1639 int ret;
1640
1641 bcm_sysport_netif_stop(dev);
80105bef
FF		 1642
1643 /* Disable UniMAC RX */
18e21b01 1644 umac_enable_set(priv, CMD_RX_EN, 0);
80105bef
FF		 1645
1646 ret = tdma_enable_set(priv, 0);
1647 if (ret) {
1648 netdev_err(dev, "timeout disabling RDMA\n");
1649 return ret;
1650 }
1651
1652 /* Wait for a maximum packet size to be drained */
1653 usleep_range(2000, 3000);
1654
1655 ret = rdma_enable_set(priv, 0);
1656 if (ret) {
1657 netdev_err(dev, "timeout disabling TDMA\n");
1658 return ret;
1659 }
1660
1661 /* Disable UniMAC TX */
18e21b01 1662 umac_enable_set(priv, CMD_TX_EN, 0);
80105bef
FF		 1663
1664 /* Free RX/TX rings SW structures */
1665 for (i = 0; i < dev->num_tx_queues; i++)
1666 bcm_sysport_fini_tx_ring(priv, i);
1667 bcm_sysport_fini_rx_ring(priv);
1668
1669 free_irq(priv->irq0, dev);
1670 free_irq(priv->irq1, dev);
1671
1672 /* Disconnect from PHY */
1673 phy_disconnect(priv->phydev);
1674
1675 return 0;
1676}
1677
1678static struct ethtool_ops bcm_sysport_ethtool_ops = {
1679 .get_settings = bcm_sysport_get_settings,
1680 .set_settings = bcm_sysport_set_settings,
1681 .get_drvinfo = bcm_sysport_get_drvinfo,
1682 .get_msglevel = bcm_sysport_get_msglvl,
1683 .set_msglevel = bcm_sysport_set_msglvl,
1684 .get_link = ethtool_op_get_link,
1685 .get_strings = bcm_sysport_get_strings,
1686 .get_ethtool_stats = bcm_sysport_get_stats,
1687 .get_sset_count = bcm_sysport_get_sset_count,
83e82f4c
FF		 1688 .get_wol = bcm_sysport_get_wol,
1689 .set_wol = bcm_sysport_set_wol,
b1a15e86
FF		 1690 .get_coalesce = bcm_sysport_get_coalesce,
1691 .set_coalesce = bcm_sysport_set_coalesce,
80105bef
FF		 1692};
1693
1694static const struct net_device_ops bcm_sysport_netdev_ops = {
1695 .ndo_start_xmit = bcm_sysport_xmit,
1696 .ndo_tx_timeout = bcm_sysport_tx_timeout,
1697 .ndo_open = bcm_sysport_open,
1698 .ndo_stop = bcm_sysport_stop,
1699 .ndo_set_features = bcm_sysport_set_features,
1700 .ndo_set_rx_mode = bcm_sysport_set_rx_mode,
fb3b596d 1701 .ndo_set_mac_address = bcm_sysport_change_mac,
80105bef
FF		 1702};
1703
1704#define REV_FMT "v%2x.%02x"
1705
1706static int bcm_sysport_probe(struct platform_device *pdev)
1707{
1708 struct bcm_sysport_priv *priv;
1709 struct device_node *dn;
1710 struct net_device *dev;
1711 const void *macaddr;
1712 struct resource *r;
1713 u32 txq, rxq;
1714 int ret;
1715
1716 dn = pdev->dev.of_node;
1717 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1718
1719 /* Read the Transmit/Receive Queue properties */
1720 if (of_property_read_u32(dn, "systemport,num-txq", &txq))
1721 txq = TDMA_NUM_RINGS;
1722 if (of_property_read_u32(dn, "systemport,num-rxq", &rxq))
1723 rxq = 1;
1724
1725 dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq);
1726 if (!dev)
1727 return -ENOMEM;
1728
1729 /* Initialize private members */
1730 priv = netdev_priv(dev);
1731
1732 priv->irq0 = platform_get_irq(pdev, 0);
1733 priv->irq1 = platform_get_irq(pdev, 1);
83e82f4c 1734 priv->wol_irq = platform_get_irq(pdev, 2);
80105bef
FF		 1735 if (priv->irq0 <= 0 || priv->irq1 <= 0) {
1736 dev_err(&pdev->dev, "invalid interrupts\n");
1737 ret = -EINVAL;
1738 goto err;
1739 }
1740
126e6122
JH		 1741 priv->base = devm_ioremap_resource(&pdev->dev, r);
1742 if (IS_ERR(priv->base)) {
1743 ret = PTR_ERR(priv->base);
80105bef
FF		 1744 goto err;
1745 }
1746
1747 priv->netdev = dev;
1748 priv->pdev = pdev;
1749
1750 priv->phy_interface = of_get_phy_mode(dn);
1751 /* Default to GMII interface mode */
1752 if (priv->phy_interface < 0)
1753 priv->phy_interface = PHY_INTERFACE_MODE_GMII;
1754
186534a3
FF		 1755 /* In the case of a fixed PHY, the DT node associated
1756 * to the PHY is the Ethernet MAC DT node.
1757 */
1758 if (of_phy_is_fixed_link(dn)) {
1759 ret = of_phy_register_fixed_link(dn);
1760 if (ret) {
1761 dev_err(&pdev->dev, "failed to register fixed PHY\n");
1762 goto err;
1763 }
1764
1765 priv->phy_dn = dn;
1766 }
1767
80105bef
FF		 1768 /* Initialize netdevice members */
1769 macaddr = of_get_mac_address(dn);
1770 if (!macaddr || !is_valid_ether_addr(macaddr)) {
1771 dev_warn(&pdev->dev, "using random Ethernet MAC\n");
1772 random_ether_addr(dev->dev_addr);
1773 } else {
1774 ether_addr_copy(dev->dev_addr, macaddr);
1775 }
1776
1777 SET_NETDEV_DEV(dev, &pdev->dev);
1778 dev_set_drvdata(&pdev->dev, dev);
7ad24ea4 1779 dev->ethtool_ops = &bcm_sysport_ethtool_ops;
80105bef
FF		 1780 dev->netdev_ops = &bcm_sysport_netdev_ops;
1781 netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64);
1782
1783 /* HW supported features, none enabled by default */
1784 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
1785 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1786
83e82f4c
FF		 1787 /* Request the WOL interrupt and advertise suspend if available */
1788 priv->wol_irq_disabled = 1;
1789 ret = devm_request_irq(&pdev->dev, priv->wol_irq,
23acb2fc 1790 bcm_sysport_wol_isr, 0, dev->name, priv);
83e82f4c
FF		 1791 if (!ret)
1792 device_set_wakeup_capable(&pdev->dev, 1);
1793
80105bef 1794 /* Set the needed headroom once and for all */
3afc557d
PG		 1795 BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8);
1796 dev->needed_headroom += sizeof(struct bcm_tsb);
80105bef 1797
f532e744
FF		 1798 /* libphy will adjust the link state accordingly */
1799 netif_carrier_off(dev);
1800
80105bef
FF		 1801 ret = register_netdev(dev);
1802 if (ret) {
1803 dev_err(&pdev->dev, "failed to register net_device\n");
1804 goto err;
1805 }
1806
1807 priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK;
1808 dev_info(&pdev->dev,
23acb2fc
FF		 1809 "Broadcom SYSTEMPORT" REV_FMT
1810 " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n",
1811 (priv->rev >> 8) & 0xff, priv->rev & 0xff,
1812 priv->base, priv->irq0, priv->irq1, txq, rxq);
80105bef
FF		 1813
1814 return 0;
1815err:
1816 free_netdev(dev);
1817 return ret;
1818}
1819
1820static int bcm_sysport_remove(struct platform_device *pdev)
1821{
1822 struct net_device *dev = dev_get_drvdata(&pdev->dev);
1823
1824 /* Not much to do, ndo_close has been called
1825 * and we use managed allocations
1826 */
1827 unregister_netdev(dev);
1828 free_netdev(dev);
1829 dev_set_drvdata(&pdev->dev, NULL);
1830
1831 return 0;
1832}
1833
40755a0f 1834#ifdef CONFIG_PM_SLEEP
83e82f4c
FF		 1835static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv)
1836{
1837 struct net_device *ndev = priv->netdev;
1838 unsigned int timeout = 1000;
1839 u32 reg;
1840
1841 /* Password has already been programmed */
1842 reg = umac_readl(priv, UMAC_MPD_CTRL);
1843 reg |= MPD_EN;
1844 reg &= ~PSW_EN;
1845 if (priv->wolopts & WAKE_MAGICSECURE)
1846 reg |= PSW_EN;
1847 umac_writel(priv, reg, UMAC_MPD_CTRL);
1848
1849 /* Make sure RBUF entered WoL mode as result */
1850 do {
1851 reg = rbuf_readl(priv, RBUF_STATUS);
1852 if (reg & RBUF_WOL_MODE)
1853 break;
1854
1855 udelay(10);
1856 } while (timeout-- > 0);
1857
1858 /* Do not leave the UniMAC RBUF matching only MPD packets */
1859 if (!timeout) {
1860 reg = umac_readl(priv, UMAC_MPD_CTRL);
1861 reg &= ~MPD_EN;
1862 umac_writel(priv, reg, UMAC_MPD_CTRL);
1863 netif_err(priv, wol, ndev, "failed to enter WOL mode\n");
1864 return -ETIMEDOUT;
1865 }
1866
1867 /* UniMAC receive needs to be turned on */
1868 umac_enable_set(priv, CMD_RX_EN, 1);
1869
1870 /* Enable the interrupt wake-up source */
1871 intrl2_0_mask_clear(priv, INTRL2_0_MPD);
1872
1873 netif_dbg(priv, wol, ndev, "entered WOL mode\n");
1874
1875 return 0;
1876}
1877
40755a0f
FF		 1878static int bcm_sysport_suspend(struct device *d)
1879{
1880 struct net_device *dev = dev_get_drvdata(d);
1881 struct bcm_sysport_priv *priv = netdev_priv(dev);
1882 unsigned int i;
83e82f4c 1883 int ret = 0;
40755a0f
FF		 1884 u32 reg;
1885
1886 if (!netif_running(dev))
1887 return 0;
1888
1889 bcm_sysport_netif_stop(dev);
1890
1891 phy_suspend(priv->phydev);
1892
1893 netif_device_detach(dev);
1894
1895 /* Disable UniMAC RX */
1896 umac_enable_set(priv, CMD_RX_EN, 0);
1897
1898 ret = rdma_enable_set(priv, 0);
1899 if (ret) {
1900 netdev_err(dev, "RDMA timeout!\n");
1901 return ret;
1902 }
1903
1904 /* Disable RXCHK if enabled */
9d34c1cb 1905 if (priv->rx_chk_en) {
40755a0f
FF		 1906 reg = rxchk_readl(priv, RXCHK_CONTROL);
1907 reg &= ~RXCHK_EN;
1908 rxchk_writel(priv, reg, RXCHK_CONTROL);
1909 }
1910
1911 /* Flush RX pipe */
83e82f4c
FF		 1912 if (!priv->wolopts)
1913 topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL);
40755a0f
FF		 1914
1915 ret = tdma_enable_set(priv, 0);
1916 if (ret) {
1917 netdev_err(dev, "TDMA timeout!\n");
1918 return ret;
1919 }
1920
1921 /* Wait for a packet boundary */
1922 usleep_range(2000, 3000);
1923
1924 umac_enable_set(priv, CMD_TX_EN, 0);
1925
1926 topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL);
1927
1928 /* Free RX/TX rings SW structures */
1929 for (i = 0; i < dev->num_tx_queues; i++)
1930 bcm_sysport_fini_tx_ring(priv, i);
1931 bcm_sysport_fini_rx_ring(priv);
1932
83e82f4c
FF		 1933 /* Get prepared for Wake-on-LAN */
1934 if (device_may_wakeup(d) && priv->wolopts)
1935 ret = bcm_sysport_suspend_to_wol(priv);
1936
1937 return ret;
40755a0f
FF		 1938}
1939
1940static int bcm_sysport_resume(struct device *d)
1941{
1942 struct net_device *dev = dev_get_drvdata(d);
1943 struct bcm_sysport_priv *priv = netdev_priv(dev);
1944 unsigned int i;
1945 u32 reg;
1946 int ret;
1947
1948 if (!netif_running(dev))
1949 return 0;
1950
704d33e7
FF		 1951 umac_reset(priv);
1952
83e82f4c
FF		 1953 /* We may have been suspended and never received a WOL event that
1954 * would turn off MPD detection, take care of that now
1955 */
1956 bcm_sysport_resume_from_wol(priv);
1957
40755a0f
FF		 1958 /* Initialize both hardware and software ring */
1959 for (i = 0; i < dev->num_tx_queues; i++) {
1960 ret = bcm_sysport_init_tx_ring(priv, i);
1961 if (ret) {
1962 netdev_err(dev, "failed to initialize TX ring %d\n",
23acb2fc 1963 i);
40755a0f
FF		 1964 goto out_free_tx_rings;
1965 }
1966 }
1967
1968 /* Initialize linked-list */
1969 tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS);
1970
1971 /* Initialize RX ring */
1972 ret = bcm_sysport_init_rx_ring(priv);
1973 if (ret) {
1974 netdev_err(dev, "failed to initialize RX ring\n");
1975 goto out_free_rx_ring;
1976 }
1977
1978 netif_device_attach(dev);
1979
40755a0f
FF		 1980 /* RX pipe enable */
1981 topctrl_writel(priv, 0, RX_FLUSH_CNTL);
1982
1983 ret = rdma_enable_set(priv, 1);
1984 if (ret) {
1985 netdev_err(dev, "failed to enable RDMA\n");
1986 goto out_free_rx_ring;
1987 }
1988
1989 /* Enable rxhck */
9d34c1cb 1990 if (priv->rx_chk_en) {
40755a0f
FF		 1991 reg = rxchk_readl(priv, RXCHK_CONTROL);
1992 reg |= RXCHK_EN;
1993 rxchk_writel(priv, reg, RXCHK_CONTROL);
1994 }
1995
1996 rbuf_init(priv);
1997
1998 /* Set maximum frame length */
1999 umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
2000
2001 /* Set MAC address */
2002 umac_set_hw_addr(priv, dev->dev_addr);
2003
2004 umac_enable_set(priv, CMD_RX_EN, 1);
2005
2006 /* TX pipe enable */
2007 topctrl_writel(priv, 0, TX_FLUSH_CNTL);
2008
2009 umac_enable_set(priv, CMD_TX_EN, 1);
2010
2011 ret = tdma_enable_set(priv, 1);
2012 if (ret) {
2013 netdev_err(dev, "TDMA timeout!\n");
2014 goto out_free_rx_ring;
2015 }
2016
2017 phy_resume(priv->phydev);
2018
2019 bcm_sysport_netif_start(dev);
2020
2021 return 0;
2022
2023out_free_rx_ring:
2024 bcm_sysport_fini_rx_ring(priv);
2025out_free_tx_rings:
2026 for (i = 0; i < dev->num_tx_queues; i++)
2027 bcm_sysport_fini_tx_ring(priv, i);
2028 return ret;
2029}
2030#endif
2031
2032static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops,
2033 bcm_sysport_suspend, bcm_sysport_resume);
2034
80105bef
FF		 2035static const struct of_device_id bcm_sysport_of_match[] = {
2036 { .compatible = "brcm,systemport-v1.00" },
2037 { .compatible = "brcm,systemport" },
2038 { /* sentinel */ }
2039};
2040
2041static struct platform_driver bcm_sysport_driver = {
2042 .probe = bcm_sysport_probe,
2043 .remove = bcm_sysport_remove,
2044 .driver = {
2045 .name = "brcm-systemport",
80105bef 2046 .of_match_table = bcm_sysport_of_match,
40755a0f 2047 .pm = &bcm_sysport_pm_ops,
80105bef
FF		 2048 },
2049};
2050module_platform_driver(bcm_sysport_driver);
2051
2052MODULE_AUTHOR("Broadcom Corporation");
2053MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver");
2054MODULE_ALIAS("platform:brcm-systemport");
2055MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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