Commit | Line | Data |
---|---|---|
dd4544f0 RM |
1 | /* |
2 | * Driver for (BCM4706)? GBit MAC core on BCMA bus. | |
3 | * | |
4 | * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com> | |
5 | * | |
6 | * Licensed under the GNU/GPL. See COPYING for details. | |
7 | */ | |
8 | ||
dd4544f0 | 9 | |
f6a95a24 JM |
10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
11 | ||
12 | #include <linux/bcma/bcma.h> | |
dd4544f0 | 13 | #include <linux/etherdevice.h> |
138173d4 | 14 | #include <linux/bcm47xx_nvram.h> |
f6a95a24 | 15 | #include "bgmac.h" |
dd4544f0 | 16 | |
f6a95a24 | 17 | static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask, |
dd4544f0 RM |
18 | u32 value, int timeout) |
19 | { | |
20 | u32 val; | |
21 | int i; | |
22 | ||
23 | for (i = 0; i < timeout / 10; i++) { | |
f6a95a24 | 24 | val = bgmac_read(bgmac, reg); |
dd4544f0 RM |
25 | if ((val & mask) == value) |
26 | return true; | |
27 | udelay(10); | |
28 | } | |
f6a95a24 | 29 | dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg); |
dd4544f0 RM |
30 | return false; |
31 | } | |
32 | ||
33 | /************************************************** | |
34 | * DMA | |
35 | **************************************************/ | |
36 | ||
37 | static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) | |
38 | { | |
39 | u32 val; | |
40 | int i; | |
41 | ||
42 | if (!ring->mmio_base) | |
43 | return; | |
44 | ||
45 | /* Suspend DMA TX ring first. | |
46 | * bgmac_wait_value doesn't support waiting for any of few values, so | |
47 | * implement whole loop here. | |
48 | */ | |
49 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, | |
50 | BGMAC_DMA_TX_SUSPEND); | |
51 | for (i = 0; i < 10000 / 10; i++) { | |
52 | val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); | |
53 | val &= BGMAC_DMA_TX_STAT; | |
54 | if (val == BGMAC_DMA_TX_STAT_DISABLED || | |
55 | val == BGMAC_DMA_TX_STAT_IDLEWAIT || | |
56 | val == BGMAC_DMA_TX_STAT_STOPPED) { | |
57 | i = 0; | |
58 | break; | |
59 | } | |
60 | udelay(10); | |
61 | } | |
62 | if (i) | |
d00a8281 JM |
63 | dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n", |
64 | ring->mmio_base, val); | |
dd4544f0 RM |
65 | |
66 | /* Remove SUSPEND bit */ | |
67 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); | |
f6a95a24 | 68 | if (!bgmac_wait_value(bgmac, |
dd4544f0 RM |
69 | ring->mmio_base + BGMAC_DMA_TX_STATUS, |
70 | BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED, | |
71 | 10000)) { | |
d00a8281 JM |
72 | dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n", |
73 | ring->mmio_base); | |
dd4544f0 RM |
74 | udelay(300); |
75 | val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); | |
76 | if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED) | |
d00a8281 JM |
77 | dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n", |
78 | ring->mmio_base); | |
dd4544f0 RM |
79 | } |
80 | } | |
81 | ||
82 | static void bgmac_dma_tx_enable(struct bgmac *bgmac, | |
83 | struct bgmac_dma_ring *ring) | |
84 | { | |
85 | u32 ctl; | |
86 | ||
87 | ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); | |
db791eb2 | 88 | if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) { |
56ceecde HM |
89 | ctl &= ~BGMAC_DMA_TX_BL_MASK; |
90 | ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT; | |
91 | ||
92 | ctl &= ~BGMAC_DMA_TX_MR_MASK; | |
93 | ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT; | |
94 | ||
95 | ctl &= ~BGMAC_DMA_TX_PC_MASK; | |
96 | ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT; | |
97 | ||
98 | ctl &= ~BGMAC_DMA_TX_PT_MASK; | |
99 | ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT; | |
100 | } | |
dd4544f0 RM |
101 | ctl |= BGMAC_DMA_TX_ENABLE; |
102 | ctl |= BGMAC_DMA_TX_PARITY_DISABLE; | |
103 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); | |
104 | } | |
105 | ||
9cde9450 FF |
106 | static void |
107 | bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring, | |
108 | int i, int len, u32 ctl0) | |
109 | { | |
110 | struct bgmac_slot_info *slot; | |
111 | struct bgmac_dma_desc *dma_desc; | |
112 | u32 ctl1; | |
113 | ||
29ba877e | 114 | if (i == BGMAC_TX_RING_SLOTS - 1) |
9cde9450 FF |
115 | ctl0 |= BGMAC_DESC_CTL0_EOT; |
116 | ||
117 | ctl1 = len & BGMAC_DESC_CTL1_LEN; | |
118 | ||
119 | slot = &ring->slots[i]; | |
120 | dma_desc = &ring->cpu_base[i]; | |
121 | dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr)); | |
122 | dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr)); | |
123 | dma_desc->ctl0 = cpu_to_le32(ctl0); | |
124 | dma_desc->ctl1 = cpu_to_le32(ctl1); | |
125 | } | |
126 | ||
dd4544f0 RM |
127 | static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac, |
128 | struct bgmac_dma_ring *ring, | |
129 | struct sk_buff *skb) | |
130 | { | |
a0b68486 | 131 | struct device *dma_dev = bgmac->dma_dev; |
dd4544f0 | 132 | struct net_device *net_dev = bgmac->net_dev; |
b38c83dd FF |
133 | int index = ring->end % BGMAC_TX_RING_SLOTS; |
134 | struct bgmac_slot_info *slot = &ring->slots[index]; | |
9cde9450 FF |
135 | int nr_frags; |
136 | u32 flags; | |
9cde9450 | 137 | int i; |
dd4544f0 RM |
138 | |
139 | if (skb->len > BGMAC_DESC_CTL1_LEN) { | |
d00a8281 | 140 | netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len); |
9cde9450 | 141 | goto err_drop; |
dd4544f0 RM |
142 | } |
143 | ||
9cde9450 FF |
144 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
145 | skb_checksum_help(skb); | |
146 | ||
147 | nr_frags = skb_shinfo(skb)->nr_frags; | |
148 | ||
b38c83dd FF |
149 | /* ring->end - ring->start will return the number of valid slots, |
150 | * even when ring->end overflows | |
151 | */ | |
152 | if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) { | |
d00a8281 | 153 | netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n"); |
dd4544f0 RM |
154 | netif_stop_queue(net_dev); |
155 | return NETDEV_TX_BUSY; | |
156 | } | |
157 | ||
9cde9450 | 158 | slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb), |
dd4544f0 | 159 | DMA_TO_DEVICE); |
9cde9450 FF |
160 | if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) |
161 | goto err_dma_head; | |
dd4544f0 | 162 | |
9cde9450 FF |
163 | flags = BGMAC_DESC_CTL0_SOF; |
164 | if (!nr_frags) | |
165 | flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; | |
dd4544f0 | 166 | |
9cde9450 FF |
167 | bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags); |
168 | flags = 0; | |
169 | ||
170 | for (i = 0; i < nr_frags; i++) { | |
171 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i]; | |
172 | int len = skb_frag_size(frag); | |
173 | ||
174 | index = (index + 1) % BGMAC_TX_RING_SLOTS; | |
175 | slot = &ring->slots[index]; | |
176 | slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0, | |
177 | len, DMA_TO_DEVICE); | |
178 | if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr))) | |
179 | goto err_dma; | |
180 | ||
181 | if (i == nr_frags - 1) | |
182 | flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC; | |
183 | ||
184 | bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags); | |
185 | } | |
186 | ||
187 | slot->skb = skb; | |
b38c83dd | 188 | ring->end += nr_frags + 1; |
49a467b4 HM |
189 | netdev_sent_queue(net_dev, skb->len); |
190 | ||
dd4544f0 RM |
191 | wmb(); |
192 | ||
193 | /* Increase ring->end to point empty slot. We tell hardware the first | |
194 | * slot it should *not* read. | |
195 | */ | |
dd4544f0 | 196 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX, |
9900303e | 197 | ring->index_base + |
b38c83dd FF |
198 | (ring->end % BGMAC_TX_RING_SLOTS) * |
199 | sizeof(struct bgmac_dma_desc)); | |
dd4544f0 | 200 | |
b38c83dd | 201 | if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8) |
dd4544f0 RM |
202 | netif_stop_queue(net_dev); |
203 | ||
204 | return NETDEV_TX_OK; | |
205 | ||
9cde9450 FF |
206 | err_dma: |
207 | dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb), | |
208 | DMA_TO_DEVICE); | |
209 | ||
210 | while (i > 0) { | |
211 | int index = (ring->end + i) % BGMAC_TX_RING_SLOTS; | |
212 | struct bgmac_slot_info *slot = &ring->slots[index]; | |
213 | u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1); | |
214 | int len = ctl1 & BGMAC_DESC_CTL1_LEN; | |
215 | ||
216 | dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE); | |
217 | } | |
218 | ||
219 | err_dma_head: | |
d00a8281 JM |
220 | netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n", |
221 | ring->mmio_base); | |
9cde9450 FF |
222 | |
223 | err_drop: | |
dd4544f0 | 224 | dev_kfree_skb(skb); |
6d490f62 FF |
225 | net_dev->stats.tx_dropped++; |
226 | net_dev->stats.tx_errors++; | |
dd4544f0 RM |
227 | return NETDEV_TX_OK; |
228 | } | |
229 | ||
230 | /* Free transmitted packets */ | |
231 | static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring) | |
232 | { | |
a0b68486 | 233 | struct device *dma_dev = bgmac->dma_dev; |
dd4544f0 RM |
234 | int empty_slot; |
235 | bool freed = false; | |
49a467b4 | 236 | unsigned bytes_compl = 0, pkts_compl = 0; |
dd4544f0 RM |
237 | |
238 | /* The last slot that hardware didn't consume yet */ | |
239 | empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); | |
240 | empty_slot &= BGMAC_DMA_TX_STATDPTR; | |
9900303e RM |
241 | empty_slot -= ring->index_base; |
242 | empty_slot &= BGMAC_DMA_TX_STATDPTR; | |
dd4544f0 RM |
243 | empty_slot /= sizeof(struct bgmac_dma_desc); |
244 | ||
b38c83dd FF |
245 | while (ring->start != ring->end) { |
246 | int slot_idx = ring->start % BGMAC_TX_RING_SLOTS; | |
247 | struct bgmac_slot_info *slot = &ring->slots[slot_idx]; | |
d2b13233 | 248 | u32 ctl0, ctl1; |
b38c83dd | 249 | int len; |
dd4544f0 | 250 | |
b38c83dd FF |
251 | if (slot_idx == empty_slot) |
252 | break; | |
9cde9450 | 253 | |
d2b13233 | 254 | ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0); |
b38c83dd FF |
255 | ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1); |
256 | len = ctl1 & BGMAC_DESC_CTL1_LEN; | |
d2b13233 | 257 | if (ctl0 & BGMAC_DESC_CTL0_SOF) |
dd4544f0 | 258 | /* Unmap no longer used buffer */ |
9cde9450 FF |
259 | dma_unmap_single(dma_dev, slot->dma_addr, len, |
260 | DMA_TO_DEVICE); | |
261 | else | |
262 | dma_unmap_page(dma_dev, slot->dma_addr, len, | |
263 | DMA_TO_DEVICE); | |
dd4544f0 | 264 | |
9cde9450 | 265 | if (slot->skb) { |
6d490f62 FF |
266 | bgmac->net_dev->stats.tx_bytes += slot->skb->len; |
267 | bgmac->net_dev->stats.tx_packets++; | |
49a467b4 HM |
268 | bytes_compl += slot->skb->len; |
269 | pkts_compl++; | |
270 | ||
dd4544f0 RM |
271 | /* Free memory! :) */ |
272 | dev_kfree_skb(slot->skb); | |
273 | slot->skb = NULL; | |
dd4544f0 RM |
274 | } |
275 | ||
9cde9450 | 276 | slot->dma_addr = 0; |
b38c83dd | 277 | ring->start++; |
dd4544f0 RM |
278 | freed = true; |
279 | } | |
280 | ||
9cde9450 FF |
281 | if (!pkts_compl) |
282 | return; | |
283 | ||
49a467b4 HM |
284 | netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl); |
285 | ||
9cde9450 | 286 | if (netif_queue_stopped(bgmac->net_dev)) |
dd4544f0 RM |
287 | netif_wake_queue(bgmac->net_dev); |
288 | } | |
289 | ||
290 | static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring) | |
291 | { | |
292 | if (!ring->mmio_base) | |
293 | return; | |
294 | ||
295 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0); | |
f6a95a24 | 296 | if (!bgmac_wait_value(bgmac, |
dd4544f0 RM |
297 | ring->mmio_base + BGMAC_DMA_RX_STATUS, |
298 | BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED, | |
299 | 10000)) | |
d00a8281 JM |
300 | dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n", |
301 | ring->mmio_base); | |
dd4544f0 RM |
302 | } |
303 | ||
304 | static void bgmac_dma_rx_enable(struct bgmac *bgmac, | |
305 | struct bgmac_dma_ring *ring) | |
306 | { | |
307 | u32 ctl; | |
308 | ||
309 | ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); | |
db791eb2 | 310 | if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) { |
56ceecde HM |
311 | ctl &= ~BGMAC_DMA_RX_BL_MASK; |
312 | ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT; | |
313 | ||
314 | ctl &= ~BGMAC_DMA_RX_PC_MASK; | |
315 | ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT; | |
316 | ||
317 | ctl &= ~BGMAC_DMA_RX_PT_MASK; | |
318 | ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT; | |
319 | } | |
dd4544f0 RM |
320 | ctl &= BGMAC_DMA_RX_ADDREXT_MASK; |
321 | ctl |= BGMAC_DMA_RX_ENABLE; | |
322 | ctl |= BGMAC_DMA_RX_PARITY_DISABLE; | |
323 | ctl |= BGMAC_DMA_RX_OVERFLOW_CONT; | |
324 | ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT; | |
325 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl); | |
326 | } | |
327 | ||
328 | static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac, | |
329 | struct bgmac_slot_info *slot) | |
330 | { | |
a0b68486 | 331 | struct device *dma_dev = bgmac->dma_dev; |
b757a62e | 332 | dma_addr_t dma_addr; |
dd4544f0 | 333 | struct bgmac_rx_header *rx; |
45c9b3c0 | 334 | void *buf; |
dd4544f0 RM |
335 | |
336 | /* Alloc skb */ | |
45c9b3c0 FF |
337 | buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE); |
338 | if (!buf) | |
dd4544f0 | 339 | return -ENOMEM; |
dd4544f0 RM |
340 | |
341 | /* Poison - if everything goes fine, hardware will overwrite it */ | |
4b62dce4 | 342 | rx = buf + BGMAC_RX_BUF_OFFSET; |
dd4544f0 RM |
343 | rx->len = cpu_to_le16(0xdead); |
344 | rx->flags = cpu_to_le16(0xbeef); | |
345 | ||
346 | /* Map skb for the DMA */ | |
4b62dce4 FF |
347 | dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET, |
348 | BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); | |
b757a62e | 349 | if (dma_mapping_error(dma_dev, dma_addr)) { |
d00a8281 | 350 | netdev_err(bgmac->net_dev, "DMA mapping error\n"); |
45c9b3c0 | 351 | put_page(virt_to_head_page(buf)); |
dd4544f0 RM |
352 | return -ENOMEM; |
353 | } | |
b757a62e NH |
354 | |
355 | /* Update the slot */ | |
45c9b3c0 | 356 | slot->buf = buf; |
b757a62e NH |
357 | slot->dma_addr = dma_addr; |
358 | ||
dd4544f0 RM |
359 | return 0; |
360 | } | |
361 | ||
4668ae1f FF |
362 | static void bgmac_dma_rx_update_index(struct bgmac *bgmac, |
363 | struct bgmac_dma_ring *ring) | |
364 | { | |
365 | dma_wmb(); | |
366 | ||
367 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX, | |
368 | ring->index_base + | |
369 | ring->end * sizeof(struct bgmac_dma_desc)); | |
370 | } | |
371 | ||
d549c76b RM |
372 | static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac, |
373 | struct bgmac_dma_ring *ring, int desc_idx) | |
374 | { | |
375 | struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx; | |
376 | u32 ctl0 = 0, ctl1 = 0; | |
377 | ||
29ba877e | 378 | if (desc_idx == BGMAC_RX_RING_SLOTS - 1) |
d549c76b RM |
379 | ctl0 |= BGMAC_DESC_CTL0_EOT; |
380 | ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN; | |
381 | /* Is there any BGMAC device that requires extension? */ | |
382 | /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) & | |
383 | * B43_DMA64_DCTL1_ADDREXT_MASK; | |
384 | */ | |
385 | ||
386 | dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr)); | |
387 | dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr)); | |
388 | dma_desc->ctl0 = cpu_to_le32(ctl0); | |
389 | dma_desc->ctl1 = cpu_to_le32(ctl1); | |
4668ae1f FF |
390 | |
391 | ring->end = desc_idx; | |
d549c76b RM |
392 | } |
393 | ||
56faacd0 FF |
394 | static void bgmac_dma_rx_poison_buf(struct device *dma_dev, |
395 | struct bgmac_slot_info *slot) | |
396 | { | |
397 | struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; | |
398 | ||
399 | dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, | |
400 | DMA_FROM_DEVICE); | |
401 | rx->len = cpu_to_le16(0xdead); | |
402 | rx->flags = cpu_to_le16(0xbeef); | |
403 | dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE, | |
404 | DMA_FROM_DEVICE); | |
405 | } | |
406 | ||
dd4544f0 RM |
407 | static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring, |
408 | int weight) | |
409 | { | |
410 | u32 end_slot; | |
411 | int handled = 0; | |
412 | ||
413 | end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS); | |
414 | end_slot &= BGMAC_DMA_RX_STATDPTR; | |
9900303e RM |
415 | end_slot -= ring->index_base; |
416 | end_slot &= BGMAC_DMA_RX_STATDPTR; | |
dd4544f0 RM |
417 | end_slot /= sizeof(struct bgmac_dma_desc); |
418 | ||
4668ae1f | 419 | while (ring->start != end_slot) { |
a0b68486 | 420 | struct device *dma_dev = bgmac->dma_dev; |
dd4544f0 | 421 | struct bgmac_slot_info *slot = &ring->slots[ring->start]; |
4b62dce4 | 422 | struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET; |
45c9b3c0 FF |
423 | struct sk_buff *skb; |
424 | void *buf = slot->buf; | |
56faacd0 | 425 | dma_addr_t dma_addr = slot->dma_addr; |
dd4544f0 RM |
426 | u16 len, flags; |
427 | ||
56faacd0 FF |
428 | do { |
429 | /* Prepare new skb as replacement */ | |
430 | if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) { | |
431 | bgmac_dma_rx_poison_buf(dma_dev, slot); | |
432 | break; | |
433 | } | |
dd4544f0 | 434 | |
56faacd0 FF |
435 | /* Unmap buffer to make it accessible to the CPU */ |
436 | dma_unmap_single(dma_dev, dma_addr, | |
437 | BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE); | |
dd4544f0 | 438 | |
56faacd0 FF |
439 | /* Get info from the header */ |
440 | len = le16_to_cpu(rx->len); | |
441 | flags = le16_to_cpu(rx->flags); | |
92b9ccd3 RM |
442 | |
443 | /* Check for poison and drop or pass the packet */ | |
444 | if (len == 0xdead && flags == 0xbeef) { | |
d00a8281 JM |
445 | netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n", |
446 | ring->start); | |
56faacd0 | 447 | put_page(virt_to_head_page(buf)); |
6d490f62 | 448 | bgmac->net_dev->stats.rx_errors++; |
92b9ccd3 RM |
449 | break; |
450 | } | |
451 | ||
6a6c7084 | 452 | if (len > BGMAC_RX_ALLOC_SIZE) { |
d00a8281 JM |
453 | netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n", |
454 | ring->start); | |
6a6c7084 | 455 | put_page(virt_to_head_page(buf)); |
6d490f62 FF |
456 | bgmac->net_dev->stats.rx_length_errors++; |
457 | bgmac->net_dev->stats.rx_errors++; | |
6a6c7084 FF |
458 | break; |
459 | } | |
460 | ||
02e71127 HM |
461 | /* Omit CRC. */ |
462 | len -= ETH_FCS_LEN; | |
463 | ||
45c9b3c0 | 464 | skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE); |
750afbf8 | 465 | if (unlikely(!skb)) { |
d00a8281 | 466 | netdev_err(bgmac->net_dev, "build_skb failed\n"); |
f1640c3d | 467 | put_page(virt_to_head_page(buf)); |
6d490f62 | 468 | bgmac->net_dev->stats.rx_errors++; |
f1640c3d | 469 | break; |
470 | } | |
4b62dce4 FF |
471 | skb_put(skb, BGMAC_RX_FRAME_OFFSET + |
472 | BGMAC_RX_BUF_OFFSET + len); | |
473 | skb_pull(skb, BGMAC_RX_FRAME_OFFSET + | |
474 | BGMAC_RX_BUF_OFFSET); | |
dd4544f0 | 475 | |
92b9ccd3 RM |
476 | skb_checksum_none_assert(skb); |
477 | skb->protocol = eth_type_trans(skb, bgmac->net_dev); | |
6d490f62 FF |
478 | bgmac->net_dev->stats.rx_bytes += len; |
479 | bgmac->net_dev->stats.rx_packets++; | |
45c9b3c0 | 480 | napi_gro_receive(&bgmac->napi, skb); |
92b9ccd3 RM |
481 | handled++; |
482 | } while (0); | |
dd4544f0 | 483 | |
56faacd0 FF |
484 | bgmac_dma_rx_setup_desc(bgmac, ring, ring->start); |
485 | ||
dd4544f0 RM |
486 | if (++ring->start >= BGMAC_RX_RING_SLOTS) |
487 | ring->start = 0; | |
488 | ||
489 | if (handled >= weight) /* Should never be greater */ | |
490 | break; | |
491 | } | |
492 | ||
4668ae1f FF |
493 | bgmac_dma_rx_update_index(bgmac, ring); |
494 | ||
dd4544f0 RM |
495 | return handled; |
496 | } | |
497 | ||
498 | /* Does ring support unaligned addressing? */ | |
499 | static bool bgmac_dma_unaligned(struct bgmac *bgmac, | |
500 | struct bgmac_dma_ring *ring, | |
501 | enum bgmac_dma_ring_type ring_type) | |
502 | { | |
503 | switch (ring_type) { | |
504 | case BGMAC_DMA_RING_TX: | |
505 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, | |
506 | 0xff0); | |
507 | if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO)) | |
508 | return true; | |
509 | break; | |
510 | case BGMAC_DMA_RING_RX: | |
511 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, | |
512 | 0xff0); | |
513 | if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO)) | |
514 | return true; | |
515 | break; | |
516 | } | |
517 | return false; | |
518 | } | |
519 | ||
45c9b3c0 FF |
520 | static void bgmac_dma_tx_ring_free(struct bgmac *bgmac, |
521 | struct bgmac_dma_ring *ring) | |
dd4544f0 | 522 | { |
a0b68486 | 523 | struct device *dma_dev = bgmac->dma_dev; |
9cde9450 | 524 | struct bgmac_dma_desc *dma_desc = ring->cpu_base; |
dd4544f0 | 525 | struct bgmac_slot_info *slot; |
dd4544f0 RM |
526 | int i; |
527 | ||
29ba877e | 528 | for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) { |
9cde9450 FF |
529 | int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN; |
530 | ||
dd4544f0 | 531 | slot = &ring->slots[i]; |
9cde9450 FF |
532 | dev_kfree_skb(slot->skb); |
533 | ||
534 | if (!slot->dma_addr) | |
535 | continue; | |
536 | ||
537 | if (slot->skb) | |
538 | dma_unmap_single(dma_dev, slot->dma_addr, | |
539 | len, DMA_TO_DEVICE); | |
540 | else | |
541 | dma_unmap_page(dma_dev, slot->dma_addr, | |
542 | len, DMA_TO_DEVICE); | |
dd4544f0 | 543 | } |
45c9b3c0 FF |
544 | } |
545 | ||
546 | static void bgmac_dma_rx_ring_free(struct bgmac *bgmac, | |
547 | struct bgmac_dma_ring *ring) | |
548 | { | |
a0b68486 | 549 | struct device *dma_dev = bgmac->dma_dev; |
45c9b3c0 FF |
550 | struct bgmac_slot_info *slot; |
551 | int i; | |
552 | ||
29ba877e | 553 | for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) { |
45c9b3c0 | 554 | slot = &ring->slots[i]; |
56faacd0 | 555 | if (!slot->dma_addr) |
45c9b3c0 | 556 | continue; |
dd4544f0 | 557 | |
56faacd0 FF |
558 | dma_unmap_single(dma_dev, slot->dma_addr, |
559 | BGMAC_RX_BUF_SIZE, | |
560 | DMA_FROM_DEVICE); | |
45c9b3c0 | 561 | put_page(virt_to_head_page(slot->buf)); |
56faacd0 | 562 | slot->dma_addr = 0; |
dd4544f0 RM |
563 | } |
564 | } | |
565 | ||
45c9b3c0 | 566 | static void bgmac_dma_ring_desc_free(struct bgmac *bgmac, |
29ba877e FF |
567 | struct bgmac_dma_ring *ring, |
568 | int num_slots) | |
45c9b3c0 | 569 | { |
a0b68486 | 570 | struct device *dma_dev = bgmac->dma_dev; |
45c9b3c0 FF |
571 | int size; |
572 | ||
573 | if (!ring->cpu_base) | |
574 | return; | |
575 | ||
576 | /* Free ring of descriptors */ | |
29ba877e | 577 | size = num_slots * sizeof(struct bgmac_dma_desc); |
45c9b3c0 FF |
578 | dma_free_coherent(dma_dev, size, ring->cpu_base, |
579 | ring->dma_base); | |
580 | } | |
581 | ||
74b6f291 | 582 | static void bgmac_dma_cleanup(struct bgmac *bgmac) |
dd4544f0 RM |
583 | { |
584 | int i; | |
585 | ||
74b6f291 | 586 | for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) |
45c9b3c0 | 587 | bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]); |
74b6f291 FF |
588 | |
589 | for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) | |
45c9b3c0 | 590 | bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]); |
74b6f291 FF |
591 | } |
592 | ||
593 | static void bgmac_dma_free(struct bgmac *bgmac) | |
594 | { | |
595 | int i; | |
596 | ||
597 | for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) | |
29ba877e FF |
598 | bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i], |
599 | BGMAC_TX_RING_SLOTS); | |
74b6f291 FF |
600 | |
601 | for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) | |
29ba877e FF |
602 | bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i], |
603 | BGMAC_RX_RING_SLOTS); | |
dd4544f0 RM |
604 | } |
605 | ||
606 | static int bgmac_dma_alloc(struct bgmac *bgmac) | |
607 | { | |
a0b68486 | 608 | struct device *dma_dev = bgmac->dma_dev; |
dd4544f0 RM |
609 | struct bgmac_dma_ring *ring; |
610 | static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1, | |
611 | BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, }; | |
612 | int size; /* ring size: different for Tx and Rx */ | |
613 | int err; | |
614 | int i; | |
615 | ||
616 | BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base)); | |
617 | BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base)); | |
618 | ||
f6a95a24 | 619 | if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) { |
d00a8281 | 620 | dev_err(bgmac->dev, "Core does not report 64-bit DMA\n"); |
dd4544f0 RM |
621 | return -ENOTSUPP; |
622 | } | |
623 | ||
624 | for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { | |
625 | ring = &bgmac->tx_ring[i]; | |
dd4544f0 | 626 | ring->mmio_base = ring_base[i]; |
dd4544f0 RM |
627 | |
628 | /* Alloc ring of descriptors */ | |
29ba877e | 629 | size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc); |
dd4544f0 RM |
630 | ring->cpu_base = dma_zalloc_coherent(dma_dev, size, |
631 | &ring->dma_base, | |
632 | GFP_KERNEL); | |
633 | if (!ring->cpu_base) { | |
d00a8281 JM |
634 | dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n", |
635 | ring->mmio_base); | |
dd4544f0 RM |
636 | goto err_dma_free; |
637 | } | |
dd4544f0 | 638 | |
9900303e RM |
639 | ring->unaligned = bgmac_dma_unaligned(bgmac, ring, |
640 | BGMAC_DMA_RING_TX); | |
641 | if (ring->unaligned) | |
642 | ring->index_base = lower_32_bits(ring->dma_base); | |
643 | else | |
644 | ring->index_base = 0; | |
645 | ||
dd4544f0 RM |
646 | /* No need to alloc TX slots yet */ |
647 | } | |
648 | ||
649 | for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { | |
650 | ring = &bgmac->rx_ring[i]; | |
dd4544f0 | 651 | ring->mmio_base = ring_base[i]; |
dd4544f0 RM |
652 | |
653 | /* Alloc ring of descriptors */ | |
29ba877e | 654 | size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc); |
dd4544f0 RM |
655 | ring->cpu_base = dma_zalloc_coherent(dma_dev, size, |
656 | &ring->dma_base, | |
657 | GFP_KERNEL); | |
658 | if (!ring->cpu_base) { | |
d00a8281 JM |
659 | dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n", |
660 | ring->mmio_base); | |
dd4544f0 RM |
661 | err = -ENOMEM; |
662 | goto err_dma_free; | |
663 | } | |
dd4544f0 | 664 | |
9900303e RM |
665 | ring->unaligned = bgmac_dma_unaligned(bgmac, ring, |
666 | BGMAC_DMA_RING_RX); | |
667 | if (ring->unaligned) | |
668 | ring->index_base = lower_32_bits(ring->dma_base); | |
669 | else | |
670 | ring->index_base = 0; | |
dd4544f0 RM |
671 | } |
672 | ||
673 | return 0; | |
674 | ||
675 | err_dma_free: | |
676 | bgmac_dma_free(bgmac); | |
677 | return -ENOMEM; | |
678 | } | |
679 | ||
74b6f291 | 680 | static int bgmac_dma_init(struct bgmac *bgmac) |
dd4544f0 RM |
681 | { |
682 | struct bgmac_dma_ring *ring; | |
74b6f291 | 683 | int i, err; |
dd4544f0 RM |
684 | |
685 | for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) { | |
686 | ring = &bgmac->tx_ring[i]; | |
687 | ||
9900303e RM |
688 | if (!ring->unaligned) |
689 | bgmac_dma_tx_enable(bgmac, ring); | |
dd4544f0 RM |
690 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO, |
691 | lower_32_bits(ring->dma_base)); | |
692 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI, | |
693 | upper_32_bits(ring->dma_base)); | |
9900303e RM |
694 | if (ring->unaligned) |
695 | bgmac_dma_tx_enable(bgmac, ring); | |
dd4544f0 RM |
696 | |
697 | ring->start = 0; | |
698 | ring->end = 0; /* Points the slot that should *not* be read */ | |
699 | } | |
700 | ||
701 | for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) { | |
70a737b7 RM |
702 | int j; |
703 | ||
dd4544f0 RM |
704 | ring = &bgmac->rx_ring[i]; |
705 | ||
9900303e RM |
706 | if (!ring->unaligned) |
707 | bgmac_dma_rx_enable(bgmac, ring); | |
dd4544f0 RM |
708 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO, |
709 | lower_32_bits(ring->dma_base)); | |
710 | bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI, | |
711 | upper_32_bits(ring->dma_base)); | |
9900303e RM |
712 | if (ring->unaligned) |
713 | bgmac_dma_rx_enable(bgmac, ring); | |
dd4544f0 | 714 | |
4668ae1f FF |
715 | ring->start = 0; |
716 | ring->end = 0; | |
29ba877e | 717 | for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) { |
74b6f291 FF |
718 | err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]); |
719 | if (err) | |
720 | goto error; | |
721 | ||
d549c76b | 722 | bgmac_dma_rx_setup_desc(bgmac, ring, j); |
74b6f291 | 723 | } |
dd4544f0 | 724 | |
4668ae1f | 725 | bgmac_dma_rx_update_index(bgmac, ring); |
dd4544f0 | 726 | } |
74b6f291 FF |
727 | |
728 | return 0; | |
729 | ||
730 | error: | |
731 | bgmac_dma_cleanup(bgmac); | |
732 | return err; | |
dd4544f0 RM |
733 | } |
734 | ||
dd4544f0 RM |
735 | |
736 | /************************************************** | |
737 | * Chip ops | |
738 | **************************************************/ | |
739 | ||
740 | /* TODO: can we just drop @force? Can we don't reset MAC at all if there is | |
741 | * nothing to change? Try if after stabilizng driver. | |
742 | */ | |
743 | static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set, | |
744 | bool force) | |
745 | { | |
746 | u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); | |
747 | u32 new_val = (cmdcfg & mask) | set; | |
db791eb2 | 748 | u32 cmdcfg_sr; |
dd4544f0 | 749 | |
db791eb2 JM |
750 | if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) |
751 | cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; | |
752 | else | |
753 | cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; | |
754 | ||
755 | bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr); | |
dd4544f0 RM |
756 | udelay(2); |
757 | ||
758 | if (new_val != cmdcfg || force) | |
759 | bgmac_write(bgmac, BGMAC_CMDCFG, new_val); | |
760 | ||
db791eb2 | 761 | bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr); |
dd4544f0 RM |
762 | udelay(2); |
763 | } | |
764 | ||
4e209001 HM |
765 | static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr) |
766 | { | |
767 | u32 tmp; | |
768 | ||
769 | tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; | |
770 | bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp); | |
771 | tmp = (addr[4] << 8) | addr[5]; | |
772 | bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp); | |
773 | } | |
774 | ||
c6edfe10 HM |
775 | static void bgmac_set_rx_mode(struct net_device *net_dev) |
776 | { | |
777 | struct bgmac *bgmac = netdev_priv(net_dev); | |
778 | ||
779 | if (net_dev->flags & IFF_PROMISC) | |
e9ba1039 | 780 | bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true); |
c6edfe10 | 781 | else |
e9ba1039 | 782 | bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true); |
c6edfe10 HM |
783 | } |
784 | ||
dd4544f0 RM |
785 | #if 0 /* We don't use that regs yet */ |
786 | static void bgmac_chip_stats_update(struct bgmac *bgmac) | |
787 | { | |
788 | int i; | |
789 | ||
db791eb2 | 790 | if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) { |
dd4544f0 RM |
791 | for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) |
792 | bgmac->mib_tx_regs[i] = | |
793 | bgmac_read(bgmac, | |
794 | BGMAC_TX_GOOD_OCTETS + (i * 4)); | |
795 | for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) | |
796 | bgmac->mib_rx_regs[i] = | |
797 | bgmac_read(bgmac, | |
798 | BGMAC_RX_GOOD_OCTETS + (i * 4)); | |
799 | } | |
800 | ||
801 | /* TODO: what else? how to handle BCM4706? Specs are needed */ | |
802 | } | |
803 | #endif | |
804 | ||
805 | static void bgmac_clear_mib(struct bgmac *bgmac) | |
806 | { | |
807 | int i; | |
808 | ||
db791eb2 | 809 | if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB) |
dd4544f0 RM |
810 | return; |
811 | ||
812 | bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR); | |
813 | for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++) | |
814 | bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4)); | |
815 | for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++) | |
816 | bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4)); | |
817 | } | |
818 | ||
819 | /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */ | |
5824d2d1 | 820 | static void bgmac_mac_speed(struct bgmac *bgmac) |
dd4544f0 RM |
821 | { |
822 | u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD); | |
823 | u32 set = 0; | |
824 | ||
5824d2d1 RM |
825 | switch (bgmac->mac_speed) { |
826 | case SPEED_10: | |
dd4544f0 | 827 | set |= BGMAC_CMDCFG_ES_10; |
5824d2d1 RM |
828 | break; |
829 | case SPEED_100: | |
dd4544f0 | 830 | set |= BGMAC_CMDCFG_ES_100; |
5824d2d1 RM |
831 | break; |
832 | case SPEED_1000: | |
dd4544f0 | 833 | set |= BGMAC_CMDCFG_ES_1000; |
5824d2d1 | 834 | break; |
6df4aff9 HM |
835 | case SPEED_2500: |
836 | set |= BGMAC_CMDCFG_ES_2500; | |
837 | break; | |
5824d2d1 | 838 | default: |
d00a8281 JM |
839 | dev_err(bgmac->dev, "Unsupported speed: %d\n", |
840 | bgmac->mac_speed); | |
5824d2d1 RM |
841 | } |
842 | ||
843 | if (bgmac->mac_duplex == DUPLEX_HALF) | |
dd4544f0 | 844 | set |= BGMAC_CMDCFG_HD; |
5824d2d1 | 845 | |
dd4544f0 RM |
846 | bgmac_cmdcfg_maskset(bgmac, mask, set, true); |
847 | } | |
848 | ||
849 | static void bgmac_miiconfig(struct bgmac *bgmac) | |
850 | { | |
db791eb2 | 851 | if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) { |
f6a95a24 JM |
852 | bgmac_idm_write(bgmac, BCMA_IOCTL, |
853 | bgmac_idm_read(bgmac, BCMA_IOCTL) | 0x40 | | |
854 | BGMAC_BCMA_IOCTL_SW_CLKEN); | |
6df4aff9 | 855 | bgmac->mac_speed = SPEED_2500; |
5824d2d1 RM |
856 | bgmac->mac_duplex = DUPLEX_FULL; |
857 | bgmac_mac_speed(bgmac); | |
6df4aff9 | 858 | } else { |
db791eb2 JM |
859 | u8 imode; |
860 | ||
6df4aff9 HM |
861 | imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & |
862 | BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT; | |
863 | if (imode == 0 || imode == 1) { | |
864 | bgmac->mac_speed = SPEED_100; | |
865 | bgmac->mac_duplex = DUPLEX_FULL; | |
866 | bgmac_mac_speed(bgmac); | |
867 | } | |
dd4544f0 RM |
868 | } |
869 | } | |
870 | ||
871 | /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */ | |
872 | static void bgmac_chip_reset(struct bgmac *bgmac) | |
873 | { | |
db791eb2 | 874 | u32 cmdcfg_sr; |
dd4544f0 RM |
875 | u32 iost; |
876 | int i; | |
877 | ||
f6a95a24 | 878 | if (bgmac_clk_enabled(bgmac)) { |
dd4544f0 RM |
879 | if (!bgmac->stats_grabbed) { |
880 | /* bgmac_chip_stats_update(bgmac); */ | |
881 | bgmac->stats_grabbed = true; | |
882 | } | |
883 | ||
884 | for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) | |
885 | bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]); | |
886 | ||
887 | bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); | |
888 | udelay(1); | |
889 | ||
890 | for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) | |
891 | bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]); | |
892 | ||
893 | /* TODO: Clear software multicast filter list */ | |
894 | } | |
895 | ||
f6a95a24 | 896 | iost = bgmac_idm_read(bgmac, BCMA_IOST); |
db791eb2 | 897 | if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED) |
dd4544f0 RM |
898 | iost &= ~BGMAC_BCMA_IOST_ATTACHED; |
899 | ||
9e4e6206 | 900 | /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */ |
db791eb2 JM |
901 | if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) { |
902 | u32 flags = 0; | |
6df4aff9 HM |
903 | if (iost & BGMAC_BCMA_IOST_ATTACHED) { |
904 | flags = BGMAC_BCMA_IOCTL_SW_CLKEN; | |
905 | if (!bgmac->has_robosw) | |
906 | flags |= BGMAC_BCMA_IOCTL_SW_RESET; | |
907 | } | |
f6a95a24 | 908 | bgmac_clk_enable(bgmac, flags); |
dd4544f0 RM |
909 | } |
910 | ||
6df4aff9 | 911 | /* Request Misc PLL for corerev > 2 */ |
db791eb2 | 912 | if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) { |
1a0ab767 RM |
913 | bgmac_set(bgmac, BCMA_CLKCTLST, |
914 | BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ); | |
f6a95a24 | 915 | bgmac_wait_value(bgmac, BCMA_CLKCTLST, |
1a0ab767 RM |
916 | BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, |
917 | BGMAC_BCMA_CLKCTLST_MISC_PLL_ST, | |
dd4544f0 RM |
918 | 1000); |
919 | } | |
920 | ||
db791eb2 | 921 | if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) { |
dd4544f0 RM |
922 | u8 et_swtype = 0; |
923 | u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY | | |
6a391e7b | 924 | BGMAC_CHIPCTL_1_IF_TYPE_MII; |
3647268d | 925 | char buf[4]; |
dd4544f0 | 926 | |
3647268d | 927 | if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) { |
dd4544f0 | 928 | if (kstrtou8(buf, 0, &et_swtype)) |
d00a8281 JM |
929 | dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n", |
930 | buf); | |
dd4544f0 RM |
931 | et_swtype &= 0x0f; |
932 | et_swtype <<= 4; | |
933 | sw_type = et_swtype; | |
db791eb2 | 934 | } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) { |
dd4544f0 | 935 | sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII; |
db791eb2 | 936 | } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) { |
b5a4c2f3 HM |
937 | sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII | |
938 | BGMAC_CHIPCTL_1_SW_TYPE_RGMII; | |
dd4544f0 | 939 | } |
f6a95a24 JM |
940 | bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK | |
941 | BGMAC_CHIPCTL_1_SW_TYPE_MASK), | |
942 | sw_type); | |
dd4544f0 RM |
943 | } |
944 | ||
945 | if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw) | |
f6a95a24 JM |
946 | bgmac_idm_write(bgmac, BCMA_IOCTL, |
947 | bgmac_idm_read(bgmac, BCMA_IOCTL) & | |
948 | ~BGMAC_BCMA_IOCTL_SW_RESET); | |
dd4544f0 RM |
949 | |
950 | /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset | |
951 | * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine | |
952 | * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to | |
953 | * be keps until taking MAC out of the reset. | |
954 | */ | |
db791eb2 JM |
955 | if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) |
956 | cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; | |
957 | else | |
958 | cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; | |
959 | ||
dd4544f0 RM |
960 | bgmac_cmdcfg_maskset(bgmac, |
961 | ~(BGMAC_CMDCFG_TE | | |
962 | BGMAC_CMDCFG_RE | | |
963 | BGMAC_CMDCFG_RPI | | |
964 | BGMAC_CMDCFG_TAI | | |
965 | BGMAC_CMDCFG_HD | | |
966 | BGMAC_CMDCFG_ML | | |
967 | BGMAC_CMDCFG_CFE | | |
968 | BGMAC_CMDCFG_RL | | |
969 | BGMAC_CMDCFG_RED | | |
970 | BGMAC_CMDCFG_PE | | |
971 | BGMAC_CMDCFG_TPI | | |
972 | BGMAC_CMDCFG_PAD_EN | | |
973 | BGMAC_CMDCFG_PF), | |
974 | BGMAC_CMDCFG_PROM | | |
975 | BGMAC_CMDCFG_NLC | | |
976 | BGMAC_CMDCFG_CFE | | |
db791eb2 | 977 | cmdcfg_sr, |
dd4544f0 | 978 | false); |
d469962f RM |
979 | bgmac->mac_speed = SPEED_UNKNOWN; |
980 | bgmac->mac_duplex = DUPLEX_UNKNOWN; | |
dd4544f0 RM |
981 | |
982 | bgmac_clear_mib(bgmac); | |
db791eb2 | 983 | if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL) |
f6a95a24 JM |
984 | bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0, |
985 | BCMA_GMAC_CMN_PC_MTE); | |
dd4544f0 RM |
986 | else |
987 | bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE); | |
988 | bgmac_miiconfig(bgmac); | |
55954f3b JM |
989 | if (bgmac->mii_bus) |
990 | bgmac->mii_bus->reset(bgmac->mii_bus); | |
dd4544f0 | 991 | |
49a467b4 | 992 | netdev_reset_queue(bgmac->net_dev); |
dd4544f0 RM |
993 | } |
994 | ||
995 | static void bgmac_chip_intrs_on(struct bgmac *bgmac) | |
996 | { | |
997 | bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask); | |
998 | } | |
999 | ||
1000 | static void bgmac_chip_intrs_off(struct bgmac *bgmac) | |
1001 | { | |
1002 | bgmac_write(bgmac, BGMAC_INT_MASK, 0); | |
4160815f | 1003 | bgmac_read(bgmac, BGMAC_INT_MASK); |
dd4544f0 RM |
1004 | } |
1005 | ||
1006 | /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */ | |
1007 | static void bgmac_enable(struct bgmac *bgmac) | |
1008 | { | |
db791eb2 | 1009 | u32 cmdcfg_sr; |
dd4544f0 RM |
1010 | u32 cmdcfg; |
1011 | u32 mode; | |
db791eb2 JM |
1012 | |
1013 | if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4) | |
1014 | cmdcfg_sr = BGMAC_CMDCFG_SR_REV4; | |
1015 | else | |
1016 | cmdcfg_sr = BGMAC_CMDCFG_SR_REV0; | |
dd4544f0 RM |
1017 | |
1018 | cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG); | |
1019 | bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE), | |
db791eb2 | 1020 | cmdcfg_sr, true); |
dd4544f0 RM |
1021 | udelay(2); |
1022 | cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE; | |
1023 | bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg); | |
1024 | ||
1025 | mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >> | |
1026 | BGMAC_DS_MM_SHIFT; | |
db791eb2 | 1027 | if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0) |
dd4544f0 | 1028 | bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT); |
db791eb2 | 1029 | if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST && mode == 2) |
f6a95a24 JM |
1030 | bgmac_cco_ctl_maskset(bgmac, 1, ~0, |
1031 | BGMAC_CHIPCTL_1_RXC_DLL_BYPASS); | |
dd4544f0 | 1032 | |
db791eb2 JM |
1033 | if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 | |
1034 | BGMAC_FEAT_FLW_CTRL2)) { | |
1035 | u32 fl_ctl; | |
1036 | ||
1037 | if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1) | |
dd4544f0 | 1038 | fl_ctl = 0x2300e1; |
db791eb2 JM |
1039 | else |
1040 | fl_ctl = 0x03cb04cb; | |
1041 | ||
dd4544f0 RM |
1042 | bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl); |
1043 | bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff); | |
dd4544f0 RM |
1044 | } |
1045 | ||
db791eb2 JM |
1046 | if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) { |
1047 | u32 rxq_ctl; | |
1048 | u16 bp_clk; | |
1049 | u8 mdp; | |
1050 | ||
6df4aff9 HM |
1051 | rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL); |
1052 | rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK; | |
f6a95a24 | 1053 | bp_clk = bgmac_get_bus_clock(bgmac) / 1000000; |
6df4aff9 HM |
1054 | mdp = (bp_clk * 128 / 1000) - 3; |
1055 | rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT); | |
1056 | bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl); | |
1057 | } | |
dd4544f0 RM |
1058 | } |
1059 | ||
1060 | /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */ | |
74b6f291 | 1061 | static void bgmac_chip_init(struct bgmac *bgmac) |
dd4544f0 | 1062 | { |
dd4544f0 RM |
1063 | /* 1 interrupt per received frame */ |
1064 | bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT); | |
1065 | ||
1066 | /* Enable 802.3x tx flow control (honor received PAUSE frames) */ | |
1067 | bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true); | |
1068 | ||
c6edfe10 | 1069 | bgmac_set_rx_mode(bgmac->net_dev); |
dd4544f0 | 1070 | |
4e209001 | 1071 | bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr); |
dd4544f0 RM |
1072 | |
1073 | if (bgmac->loopback) | |
e9ba1039 | 1074 | bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false); |
dd4544f0 | 1075 | else |
e9ba1039 | 1076 | bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false); |
dd4544f0 RM |
1077 | |
1078 | bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN); | |
1079 | ||
74b6f291 | 1080 | bgmac_chip_intrs_on(bgmac); |
dd4544f0 RM |
1081 | |
1082 | bgmac_enable(bgmac); | |
1083 | } | |
1084 | ||
1085 | static irqreturn_t bgmac_interrupt(int irq, void *dev_id) | |
1086 | { | |
1087 | struct bgmac *bgmac = netdev_priv(dev_id); | |
1088 | ||
1089 | u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS); | |
1090 | int_status &= bgmac->int_mask; | |
1091 | ||
1092 | if (!int_status) | |
1093 | return IRQ_NONE; | |
1094 | ||
eb64e292 FF |
1095 | int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX); |
1096 | if (int_status) | |
d00a8281 | 1097 | dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status); |
dd4544f0 RM |
1098 | |
1099 | /* Disable new interrupts until handling existing ones */ | |
1100 | bgmac_chip_intrs_off(bgmac); | |
1101 | ||
dd4544f0 RM |
1102 | napi_schedule(&bgmac->napi); |
1103 | ||
1104 | return IRQ_HANDLED; | |
1105 | } | |
1106 | ||
1107 | static int bgmac_poll(struct napi_struct *napi, int weight) | |
1108 | { | |
1109 | struct bgmac *bgmac = container_of(napi, struct bgmac, napi); | |
dd4544f0 RM |
1110 | int handled = 0; |
1111 | ||
eb64e292 FF |
1112 | /* Ack */ |
1113 | bgmac_write(bgmac, BGMAC_INT_STATUS, ~0); | |
dd4544f0 | 1114 | |
eb64e292 FF |
1115 | bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]); |
1116 | handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight); | |
dd4544f0 | 1117 | |
eb64e292 FF |
1118 | /* Poll again if more events arrived in the meantime */ |
1119 | if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX)) | |
e580267d | 1120 | return weight; |
dd4544f0 | 1121 | |
43f159c6 | 1122 | if (handled < weight) { |
dd4544f0 | 1123 | napi_complete(napi); |
43f159c6 HM |
1124 | bgmac_chip_intrs_on(bgmac); |
1125 | } | |
dd4544f0 RM |
1126 | |
1127 | return handled; | |
1128 | } | |
1129 | ||
1130 | /************************************************** | |
1131 | * net_device_ops | |
1132 | **************************************************/ | |
1133 | ||
1134 | static int bgmac_open(struct net_device *net_dev) | |
1135 | { | |
1136 | struct bgmac *bgmac = netdev_priv(net_dev); | |
1137 | int err = 0; | |
1138 | ||
1139 | bgmac_chip_reset(bgmac); | |
74b6f291 FF |
1140 | |
1141 | err = bgmac_dma_init(bgmac); | |
1142 | if (err) | |
1143 | return err; | |
1144 | ||
dd4544f0 | 1145 | /* Specs say about reclaiming rings here, but we do that in DMA init */ |
74b6f291 | 1146 | bgmac_chip_init(bgmac); |
dd4544f0 | 1147 | |
f6a95a24 | 1148 | err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED, |
dd4544f0 RM |
1149 | KBUILD_MODNAME, net_dev); |
1150 | if (err < 0) { | |
d00a8281 | 1151 | dev_err(bgmac->dev, "IRQ request error: %d!\n", err); |
74b6f291 FF |
1152 | bgmac_dma_cleanup(bgmac); |
1153 | return err; | |
dd4544f0 RM |
1154 | } |
1155 | napi_enable(&bgmac->napi); | |
1156 | ||
b21fcb25 | 1157 | phy_start(net_dev->phydev); |
4e34da4d | 1158 | |
c3897f2a FF |
1159 | netif_start_queue(net_dev); |
1160 | ||
74b6f291 | 1161 | return 0; |
dd4544f0 RM |
1162 | } |
1163 | ||
1164 | static int bgmac_stop(struct net_device *net_dev) | |
1165 | { | |
1166 | struct bgmac *bgmac = netdev_priv(net_dev); | |
1167 | ||
1168 | netif_carrier_off(net_dev); | |
1169 | ||
b21fcb25 | 1170 | phy_stop(net_dev->phydev); |
4e34da4d | 1171 | |
dd4544f0 RM |
1172 | napi_disable(&bgmac->napi); |
1173 | bgmac_chip_intrs_off(bgmac); | |
f6a95a24 | 1174 | free_irq(bgmac->irq, net_dev); |
dd4544f0 RM |
1175 | |
1176 | bgmac_chip_reset(bgmac); | |
74b6f291 | 1177 | bgmac_dma_cleanup(bgmac); |
dd4544f0 RM |
1178 | |
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb, | |
1183 | struct net_device *net_dev) | |
1184 | { | |
1185 | struct bgmac *bgmac = netdev_priv(net_dev); | |
1186 | struct bgmac_dma_ring *ring; | |
1187 | ||
1188 | /* No QOS support yet */ | |
1189 | ring = &bgmac->tx_ring[0]; | |
1190 | return bgmac_dma_tx_add(bgmac, ring, skb); | |
1191 | } | |
1192 | ||
4e209001 HM |
1193 | static int bgmac_set_mac_address(struct net_device *net_dev, void *addr) |
1194 | { | |
1195 | struct bgmac *bgmac = netdev_priv(net_dev); | |
1196 | int ret; | |
1197 | ||
1198 | ret = eth_prepare_mac_addr_change(net_dev, addr); | |
1199 | if (ret < 0) | |
1200 | return ret; | |
1201 | bgmac_write_mac_address(bgmac, (u8 *)addr); | |
1202 | eth_commit_mac_addr_change(net_dev, addr); | |
1203 | return 0; | |
1204 | } | |
1205 | ||
dd4544f0 RM |
1206 | static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) |
1207 | { | |
69c58852 HM |
1208 | if (!netif_running(net_dev)) |
1209 | return -EINVAL; | |
1210 | ||
b21fcb25 | 1211 | return phy_mii_ioctl(net_dev->phydev, ifr, cmd); |
dd4544f0 RM |
1212 | } |
1213 | ||
1214 | static const struct net_device_ops bgmac_netdev_ops = { | |
1215 | .ndo_open = bgmac_open, | |
1216 | .ndo_stop = bgmac_stop, | |
1217 | .ndo_start_xmit = bgmac_start_xmit, | |
c6edfe10 | 1218 | .ndo_set_rx_mode = bgmac_set_rx_mode, |
4e209001 | 1219 | .ndo_set_mac_address = bgmac_set_mac_address, |
522c5907 | 1220 | .ndo_validate_addr = eth_validate_addr, |
dd4544f0 RM |
1221 | .ndo_do_ioctl = bgmac_ioctl, |
1222 | }; | |
1223 | ||
1224 | /************************************************** | |
1225 | * ethtool_ops | |
1226 | **************************************************/ | |
1227 | ||
f6613d4f FF |
1228 | struct bgmac_stat { |
1229 | u8 size; | |
1230 | u32 offset; | |
1231 | const char *name; | |
1232 | }; | |
1233 | ||
1234 | static struct bgmac_stat bgmac_get_strings_stats[] = { | |
1235 | { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" }, | |
1236 | { 4, BGMAC_TX_GOOD_PKTS, "tx_good" }, | |
1237 | { 8, BGMAC_TX_OCTETS, "tx_octets" }, | |
1238 | { 4, BGMAC_TX_PKTS, "tx_pkts" }, | |
1239 | { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" }, | |
1240 | { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" }, | |
1241 | { 4, BGMAC_TX_LEN_64, "tx_64" }, | |
1242 | { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" }, | |
1243 | { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" }, | |
1244 | { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" }, | |
1245 | { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" }, | |
1246 | { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" }, | |
1247 | { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" }, | |
1248 | { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" }, | |
1249 | { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" }, | |
1250 | { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" }, | |
1251 | { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" }, | |
1252 | { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" }, | |
1253 | { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" }, | |
1254 | { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" }, | |
1255 | { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" }, | |
1256 | { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" }, | |
1257 | { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" }, | |
1258 | { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" }, | |
1259 | { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" }, | |
1260 | { 4, BGMAC_TX_DEFERED, "tx_defered" }, | |
1261 | { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" }, | |
1262 | { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" }, | |
1263 | { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" }, | |
1264 | { 4, BGMAC_TX_Q0_PKTS, "tx_q0" }, | |
1265 | { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" }, | |
1266 | { 4, BGMAC_TX_Q1_PKTS, "tx_q1" }, | |
1267 | { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" }, | |
1268 | { 4, BGMAC_TX_Q2_PKTS, "tx_q2" }, | |
1269 | { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" }, | |
1270 | { 4, BGMAC_TX_Q3_PKTS, "tx_q3" }, | |
1271 | { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" }, | |
1272 | { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" }, | |
1273 | { 4, BGMAC_RX_GOOD_PKTS, "rx_good" }, | |
1274 | { 8, BGMAC_RX_OCTETS, "rx_octets" }, | |
1275 | { 4, BGMAC_RX_PKTS, "rx_pkts" }, | |
1276 | { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" }, | |
1277 | { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" }, | |
1278 | { 4, BGMAC_RX_LEN_64, "rx_64" }, | |
1279 | { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" }, | |
1280 | { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" }, | |
1281 | { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" }, | |
1282 | { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" }, | |
1283 | { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" }, | |
1284 | { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" }, | |
1285 | { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" }, | |
1286 | { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" }, | |
1287 | { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" }, | |
1288 | { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" }, | |
1289 | { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" }, | |
1290 | { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" }, | |
1291 | { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" }, | |
1292 | { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" }, | |
1293 | { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" }, | |
1294 | { 4, BGMAC_RX_CRC_ERRS, "rx_crc" }, | |
1295 | { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" }, | |
1296 | { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" }, | |
1297 | { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" }, | |
1298 | { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" }, | |
1299 | { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" }, | |
1300 | { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" }, | |
1301 | }; | |
1302 | ||
1303 | #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats) | |
1304 | ||
1305 | static int bgmac_get_sset_count(struct net_device *dev, int string_set) | |
1306 | { | |
1307 | switch (string_set) { | |
1308 | case ETH_SS_STATS: | |
1309 | return BGMAC_STATS_LEN; | |
1310 | } | |
1311 | ||
1312 | return -EOPNOTSUPP; | |
1313 | } | |
1314 | ||
1315 | static void bgmac_get_strings(struct net_device *dev, u32 stringset, | |
1316 | u8 *data) | |
1317 | { | |
1318 | int i; | |
1319 | ||
1320 | if (stringset != ETH_SS_STATS) | |
1321 | return; | |
1322 | ||
1323 | for (i = 0; i < BGMAC_STATS_LEN; i++) | |
1324 | strlcpy(data + i * ETH_GSTRING_LEN, | |
1325 | bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN); | |
1326 | } | |
1327 | ||
1328 | static void bgmac_get_ethtool_stats(struct net_device *dev, | |
1329 | struct ethtool_stats *ss, uint64_t *data) | |
1330 | { | |
1331 | struct bgmac *bgmac = netdev_priv(dev); | |
1332 | const struct bgmac_stat *s; | |
1333 | unsigned int i; | |
1334 | u64 val; | |
1335 | ||
1336 | if (!netif_running(dev)) | |
1337 | return; | |
1338 | ||
1339 | for (i = 0; i < BGMAC_STATS_LEN; i++) { | |
1340 | s = &bgmac_get_strings_stats[i]; | |
1341 | val = 0; | |
1342 | if (s->size == 8) | |
1343 | val = (u64)bgmac_read(bgmac, s->offset + 4) << 32; | |
1344 | val |= bgmac_read(bgmac, s->offset); | |
1345 | data[i] = val; | |
1346 | } | |
1347 | } | |
1348 | ||
dd4544f0 RM |
1349 | static void bgmac_get_drvinfo(struct net_device *net_dev, |
1350 | struct ethtool_drvinfo *info) | |
1351 | { | |
1352 | strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); | |
f6a95a24 | 1353 | strlcpy(info->bus_info, "AXI", sizeof(info->bus_info)); |
dd4544f0 RM |
1354 | } |
1355 | ||
1356 | static const struct ethtool_ops bgmac_ethtool_ops = { | |
f6613d4f FF |
1357 | .get_strings = bgmac_get_strings, |
1358 | .get_sset_count = bgmac_get_sset_count, | |
1359 | .get_ethtool_stats = bgmac_get_ethtool_stats, | |
dd4544f0 | 1360 | .get_drvinfo = bgmac_get_drvinfo, |
904632a2 PR |
1361 | .get_link_ksettings = phy_ethtool_get_link_ksettings, |
1362 | .set_link_ksettings = phy_ethtool_set_link_ksettings, | |
dd4544f0 RM |
1363 | }; |
1364 | ||
11e5e76e RM |
1365 | /************************************************** |
1366 | * MII | |
1367 | **************************************************/ | |
1368 | ||
5824d2d1 RM |
1369 | static void bgmac_adjust_link(struct net_device *net_dev) |
1370 | { | |
1371 | struct bgmac *bgmac = netdev_priv(net_dev); | |
b21fcb25 | 1372 | struct phy_device *phy_dev = net_dev->phydev; |
5824d2d1 RM |
1373 | bool update = false; |
1374 | ||
1375 | if (phy_dev->link) { | |
1376 | if (phy_dev->speed != bgmac->mac_speed) { | |
1377 | bgmac->mac_speed = phy_dev->speed; | |
1378 | update = true; | |
1379 | } | |
1380 | ||
1381 | if (phy_dev->duplex != bgmac->mac_duplex) { | |
1382 | bgmac->mac_duplex = phy_dev->duplex; | |
1383 | update = true; | |
1384 | } | |
1385 | } | |
1386 | ||
1387 | if (update) { | |
1388 | bgmac_mac_speed(bgmac); | |
1389 | phy_print_status(phy_dev); | |
1390 | } | |
1391 | } | |
1392 | ||
55954f3b | 1393 | static int bgmac_phy_connect_direct(struct bgmac *bgmac) |
c25b23b8 RM |
1394 | { |
1395 | struct fixed_phy_status fphy_status = { | |
1396 | .link = 1, | |
1397 | .speed = SPEED_1000, | |
1398 | .duplex = DUPLEX_FULL, | |
1399 | }; | |
1400 | struct phy_device *phy_dev; | |
1401 | int err; | |
1402 | ||
4db78d31 | 1403 | phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL); |
c25b23b8 | 1404 | if (!phy_dev || IS_ERR(phy_dev)) { |
d00a8281 | 1405 | dev_err(bgmac->dev, "Failed to register fixed PHY device\n"); |
c25b23b8 RM |
1406 | return -ENODEV; |
1407 | } | |
1408 | ||
1409 | err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link, | |
1410 | PHY_INTERFACE_MODE_MII); | |
1411 | if (err) { | |
d00a8281 | 1412 | dev_err(bgmac->dev, "Connecting PHY failed\n"); |
c25b23b8 RM |
1413 | return err; |
1414 | } | |
1415 | ||
c25b23b8 RM |
1416 | return err; |
1417 | } | |
1418 | ||
55954f3b | 1419 | static int bgmac_phy_connect(struct bgmac *bgmac) |
11e5e76e | 1420 | { |
5824d2d1 RM |
1421 | struct phy_device *phy_dev; |
1422 | char bus_id[MII_BUS_ID_SIZE + 3]; | |
11e5e76e | 1423 | |
5824d2d1 | 1424 | /* Connect to the PHY */ |
55954f3b | 1425 | snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id, |
5824d2d1 RM |
1426 | bgmac->phyaddr); |
1427 | phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link, | |
1428 | PHY_INTERFACE_MODE_MII); | |
1429 | if (IS_ERR(phy_dev)) { | |
d00a8281 | 1430 | dev_err(bgmac->dev, "PHY connecton failed\n"); |
55954f3b | 1431 | return PTR_ERR(phy_dev); |
5824d2d1 | 1432 | } |
5824d2d1 | 1433 | |
55954f3b | 1434 | return 0; |
11e5e76e RM |
1435 | } |
1436 | ||
f6a95a24 | 1437 | int bgmac_enet_probe(struct bgmac *info) |
dd4544f0 RM |
1438 | { |
1439 | struct net_device *net_dev; | |
1440 | struct bgmac *bgmac; | |
dd4544f0 RM |
1441 | int err; |
1442 | ||
dd4544f0 RM |
1443 | /* Allocation and references */ |
1444 | net_dev = alloc_etherdev(sizeof(*bgmac)); | |
1445 | if (!net_dev) | |
1446 | return -ENOMEM; | |
f6a95a24 | 1447 | |
dd4544f0 | 1448 | net_dev->netdev_ops = &bgmac_netdev_ops; |
7ad24ea4 | 1449 | net_dev->ethtool_ops = &bgmac_ethtool_ops; |
dd4544f0 | 1450 | bgmac = netdev_priv(net_dev); |
f6a95a24 | 1451 | memcpy(bgmac, info, sizeof(*bgmac)); |
dd4544f0 | 1452 | bgmac->net_dev = net_dev; |
f6a95a24 JM |
1453 | net_dev->irq = bgmac->irq; |
1454 | SET_NETDEV_DEV(net_dev, bgmac->dev); | |
1455 | ||
1456 | if (!is_valid_ether_addr(bgmac->mac_addr)) { | |
1457 | dev_err(bgmac->dev, "Invalid MAC addr: %pM\n", | |
1458 | bgmac->mac_addr); | |
1459 | eth_random_addr(bgmac->mac_addr); | |
1460 | dev_warn(bgmac->dev, "Using random MAC: %pM\n", | |
1461 | bgmac->mac_addr); | |
dd4544f0 | 1462 | } |
f6a95a24 | 1463 | ether_addr_copy(net_dev->dev_addr, bgmac->mac_addr); |
dd4544f0 | 1464 | |
f6a95a24 JM |
1465 | /* This (reset &) enable is not preset in specs or reference driver but |
1466 | * Broadcom does it in arch PCI code when enabling fake PCI device. | |
1467 | */ | |
1468 | bgmac_clk_enable(bgmac, 0); | |
dd4544f0 RM |
1469 | |
1470 | bgmac_chip_reset(bgmac); | |
1471 | ||
1472 | err = bgmac_dma_alloc(bgmac); | |
1473 | if (err) { | |
d00a8281 | 1474 | dev_err(bgmac->dev, "Unable to alloc memory for DMA\n"); |
dd4544f0 RM |
1475 | goto err_netdev_free; |
1476 | } | |
1477 | ||
1478 | bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK; | |
edb15d83 | 1479 | if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0) |
dd4544f0 RM |
1480 | bgmac->int_mask &= ~BGMAC_IS_TX_MASK; |
1481 | ||
6216642f HM |
1482 | netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT); |
1483 | ||
55954f3b JM |
1484 | if (!bgmac->mii_bus) |
1485 | err = bgmac_phy_connect_direct(bgmac); | |
1486 | else | |
1487 | err = bgmac_phy_connect(bgmac); | |
11e5e76e | 1488 | if (err) { |
d00a8281 | 1489 | dev_err(bgmac->dev, "Cannot connect to phy\n"); |
f6a95a24 | 1490 | goto err_dma_free; |
11e5e76e RM |
1491 | } |
1492 | ||
9cde9450 FF |
1493 | net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
1494 | net_dev->hw_features = net_dev->features; | |
1495 | net_dev->vlan_features = net_dev->features; | |
1496 | ||
dd4544f0 RM |
1497 | err = register_netdev(bgmac->net_dev); |
1498 | if (err) { | |
d00a8281 | 1499 | dev_err(bgmac->dev, "Cannot register net device\n"); |
55954f3b | 1500 | goto err_phy_disconnect; |
dd4544f0 RM |
1501 | } |
1502 | ||
1503 | netif_carrier_off(net_dev); | |
1504 | ||
dd4544f0 RM |
1505 | return 0; |
1506 | ||
55954f3b JM |
1507 | err_phy_disconnect: |
1508 | phy_disconnect(net_dev->phydev); | |
dd4544f0 RM |
1509 | err_dma_free: |
1510 | bgmac_dma_free(bgmac); | |
dd4544f0 | 1511 | err_netdev_free: |
dd4544f0 RM |
1512 | free_netdev(net_dev); |
1513 | ||
1514 | return err; | |
1515 | } | |
f6a95a24 | 1516 | EXPORT_SYMBOL_GPL(bgmac_enet_probe); |
dd4544f0 | 1517 | |
f6a95a24 | 1518 | void bgmac_enet_remove(struct bgmac *bgmac) |
dd4544f0 | 1519 | { |
dd4544f0 | 1520 | unregister_netdev(bgmac->net_dev); |
55954f3b | 1521 | phy_disconnect(bgmac->net_dev->phydev); |
6216642f | 1522 | netif_napi_del(&bgmac->napi); |
dd4544f0 | 1523 | bgmac_dma_free(bgmac); |
dd4544f0 RM |
1524 | free_netdev(bgmac->net_dev); |
1525 | } | |
f6a95a24 | 1526 | EXPORT_SYMBOL_GPL(bgmac_enet_remove); |
dd4544f0 RM |
1527 | |
1528 | MODULE_AUTHOR("Rafał Miłecki"); | |
1529 | MODULE_LICENSE("GPL"); |