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net: bnx2 calls skb_set_hash
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2.c
CommitLineData
b6016b76
MC		 1/* bnx2.c: Broadcom NX2 network driver.
2 *
8a56d243 3 * Copyright (c) 2004-2013 Broadcom Corporation
b6016b76
MC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
3a9c6a49 12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
f2a4f052
MC		 13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
555069da 17#include <linux/stringify.h>
f2a4f052
MC		 18#include <linux/kernel.h>
19#include <linux/timer.h>
20#include <linux/errno.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/vmalloc.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/dma-mapping.h>
1977f032 31#include <linux/bitops.h>
f2a4f052
MC		 32#include <asm/io.h>
33#include <asm/irq.h>
34#include <linux/delay.h>
35#include <asm/byteorder.h>
c86a31f4 36#include <asm/page.h>
f2a4f052
MC		 37#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
01789349 40#include <linux/if.h>
f2a4f052 41#include <linux/if_vlan.h>
f2a4f052 42#include <net/ip.h>
de081fa5 43#include <net/tcp.h>
f2a4f052 44#include <net/checksum.h>
f2a4f052
MC		 45#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
29b12174 48#include <linux/cache.h>
57579f76 49#include <linux/firmware.h>
706bf240 50#include <linux/log2.h>
cd709aa9 51#include <linux/aer.h>
f2a4f052 52
4edd473f
MC		 53#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54#define BCM_CNIC 1
55#include "cnic_if.h"
56#endif
b6016b76
MC		 57#include "bnx2.h"
58#include "bnx2_fw.h"
b3448b0b 59
b6016b76 60#define DRV_MODULE_NAME "bnx2"
8a56d243
MC		 61#define DRV_MODULE_VERSION "2.2.4"
62#define DRV_MODULE_RELDATE "Aug 05, 2013"
c2c20ef4 63#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
22fa159d 64#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
c2c20ef4 65#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
22fa159d
MC		 66#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
67#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
b6016b76
MC		 68
69#define RUN_AT(x) (jiffies + (x))
70
71/* Time in jiffies before concluding the transmitter is hung. */
72#define TX_TIMEOUT (5*HZ)
73
cfd95a63 74static char version[] =
b6016b76
MC		 75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
453a9c6e 78MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
b6016b76
MC		 79MODULE_LICENSE("GPL");
80MODULE_VERSION(DRV_MODULE_VERSION);
57579f76
MC		 81MODULE_FIRMWARE(FW_MIPS_FILE_06);
82MODULE_FIRMWARE(FW_RV2P_FILE_06);
83MODULE_FIRMWARE(FW_MIPS_FILE_09);
84MODULE_FIRMWARE(FW_RV2P_FILE_09);
078b0735 85MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
b6016b76
MC		 86
87static int disable_msi = 0;
88
89module_param(disable_msi, int, 0);
90MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
91
92typedef enum {
93 BCM5706 = 0,
94 NC370T,
95 NC370I,
96 BCM5706S,
97 NC370F,
5b0c76ad
MC		 98 BCM5708,
99 BCM5708S,
bac0dff6 100 BCM5709,
27a005b8 101 BCM5709S,
7bb0a04f 102 BCM5716,
1caacecb 103 BCM5716S,
b6016b76
MC		 104} board_t;
105
106/* indexed by board_t, above */
fefa8645 107static struct {
b6016b76 108 char *name;
cfd95a63 109} board_info[] = {
b6016b76
MC		 110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
5b0c76ad
MC		 115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
bac0dff6 117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
27a005b8 118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
7bb0a04f 119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
1caacecb 120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
b6016b76
MC		 121 };
122
7bb0a04f 123static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
b6016b76
MC		 124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
5b0c76ad
MC		 130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
b6016b76
MC		 132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
5b0c76ad
MC		 136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
bac0dff6
MC		 138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
27a005b8
MC		 140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
7bb0a04f
MC		 142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
1caacecb 144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
1f2435e5 145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
b6016b76
MC		 146 { 0, }
147};
148
0ced9d01 149static const struct flash_spec flash_table[] =
b6016b76 150{
e30372c9
MC		 151#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
b6016b76 153 /* Slow EEPROM */
37137709 154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
b6016b76
MC		 156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 "EEPROM - slow"},
37137709
MC		 158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 "Entry 0001"},
b6016b76
MC		 163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
37137709 165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
37137709 171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
b6016b76
MC		 173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
37137709
MC		 175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 0100"},
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
6aa20a22 181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
e30372c9 187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
37137709
MC		 188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
196 /* Fast EEPROM */
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
e30372c9 198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
37137709
MC		 199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 "EEPROM - fast"},
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1001"},
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1010"},
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1100"},
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
e30372c9 223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
37137709
MC		 224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1101"},
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
e30372c9 233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
37137709
MC		 234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
b6016b76
MC		 236};
237
0ced9d01 238static const struct flash_spec flash_5709 = {
e30372c9
MC		 239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
245};
246
b6016b76
MC		 247MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248
4327ba43 249static void bnx2_init_napi(struct bnx2 *bp);
f048fa9c 250static void bnx2_del_napi(struct bnx2 *bp);
4327ba43 251
35e9010b 252static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
e89bbf10 253{
2f8af120 254 u32 diff;
e89bbf10 255
11848b96
MC		 256 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
257 barrier();
faac9c4b
MC		 258
259 /* The ring uses 256 indices for 255 entries, one of them
260 * needs to be skipped.
261 */
35e9010b 262 diff = txr->tx_prod - txr->tx_cons;
2bc4078e 263 if (unlikely(diff >= BNX2_TX_DESC_CNT)) {
faac9c4b 264 diff &= 0xffff;
2bc4078e
MC		 265 if (diff == BNX2_TX_DESC_CNT)
266 diff = BNX2_MAX_TX_DESC_CNT;
faac9c4b 267 }
807540ba 268 return bp->tx_ring_size - diff;
e89bbf10
MC		 269}
270
b6016b76
MC		 271static u32
272bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
273{
1b8227c4
MC		 274 u32 val;
275
276 spin_lock_bh(&bp->indirect_lock);
e503e066
MC		 277 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
278 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
1b8227c4
MC		 279 spin_unlock_bh(&bp->indirect_lock);
280 return val;
b6016b76
MC		 281}
282
283static void
284bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
285{
1b8227c4 286 spin_lock_bh(&bp->indirect_lock);
e503e066
MC		 287 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
288 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
1b8227c4 289 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 290}
291
2726d6e1
MC		 292static void
293bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
294{
295 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
296}
297
298static u32
299bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
300{
807540ba 301 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
2726d6e1
MC		 302}
303
b6016b76
MC		 304static void
305bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
306{
307 offset += cid_addr;
1b8227c4 308 spin_lock_bh(&bp->indirect_lock);
4ce45e02 309 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
59b47d8a
MC		 310 int i;
311
e503e066
MC		 312 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
313 BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
314 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
59b47d8a 315 for (i = 0; i < 5; i++) {
e503e066 316 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
59b47d8a
MC		 317 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
318 break;
319 udelay(5);
320 }
321 } else {
e503e066
MC		 322 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
323 BNX2_WR(bp, BNX2_CTX_DATA, val);
59b47d8a 324 }
1b8227c4 325 spin_unlock_bh(&bp->indirect_lock);
b6016b76
MC		 326}
327
4edd473f
MC		 328#ifdef BCM_CNIC
329static int
330bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
331{
332 struct bnx2 *bp = netdev_priv(dev);
333 struct drv_ctl_io *io = &info->data.io;
334
335 switch (info->cmd) {
336 case DRV_CTL_IO_WR_CMD:
337 bnx2_reg_wr_ind(bp, io->offset, io->data);
338 break;
339 case DRV_CTL_IO_RD_CMD:
340 io->data = bnx2_reg_rd_ind(bp, io->offset);
341 break;
342 case DRV_CTL_CTX_WR_CMD:
343 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
344 break;
345 default:
346 return -EINVAL;
347 }
348 return 0;
349}
350
351static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
352{
353 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
354 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
355 int sb_id;
356
357 if (bp->flags & BNX2_FLAG_USING_MSIX) {
358 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
359 bnapi->cnic_present = 0;
360 sb_id = bp->irq_nvecs;
361 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
362 } else {
363 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
364 bnapi->cnic_tag = bnapi->last_status_idx;
365 bnapi->cnic_present = 1;
366 sb_id = 0;
367 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
368 }
369
370 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
371 cp->irq_arr[0].status_blk = (void *)
372 ((unsigned long) bnapi->status_blk.msi +
373 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
374 cp->irq_arr[0].status_blk_num = sb_id;
375 cp->num_irq = 1;
376}
377
378static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
379 void *data)
380{
381 struct bnx2 *bp = netdev_priv(dev);
382 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
383
384 if (ops == NULL)
385 return -EINVAL;
386
387 if (cp->drv_state & CNIC_DRV_STATE_REGD)
388 return -EBUSY;
389
41c2178a
MC		 390 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
391 return -ENODEV;
392
4edd473f
MC		 393 bp->cnic_data = data;
394 rcu_assign_pointer(bp->cnic_ops, ops);
395
396 cp->num_irq = 0;
397 cp->drv_state = CNIC_DRV_STATE_REGD;
398
399 bnx2_setup_cnic_irq_info(bp);
400
401 return 0;
402}
403
404static int bnx2_unregister_cnic(struct net_device *dev)
405{
406 struct bnx2 *bp = netdev_priv(dev);
407 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
408 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
409
c5a88950 410 mutex_lock(&bp->cnic_lock);
4edd473f
MC		 411 cp->drv_state = 0;
412 bnapi->cnic_present = 0;
2cfa5a04 413 RCU_INIT_POINTER(bp->cnic_ops, NULL);
c5a88950 414 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 415 synchronize_rcu();
416 return 0;
417}
418
61c2fc4b 419static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
4edd473f
MC		 420{
421 struct bnx2 *bp = netdev_priv(dev);
422 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
423
7625eb2f
MC		 424 if (!cp->max_iscsi_conn)
425 return NULL;
426
4edd473f
MC		 427 cp->drv_owner = THIS_MODULE;
428 cp->chip_id = bp->chip_id;
429 cp->pdev = bp->pdev;
430 cp->io_base = bp->regview;
431 cp->drv_ctl = bnx2_drv_ctl;
432 cp->drv_register_cnic = bnx2_register_cnic;
433 cp->drv_unregister_cnic = bnx2_unregister_cnic;
434
435 return cp;
436}
4edd473f
MC		 437
438static void
439bnx2_cnic_stop(struct bnx2 *bp)
440{
441 struct cnic_ops *c_ops;
442 struct cnic_ctl_info info;
443
c5a88950 444 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 445 c_ops = rcu_dereference_protected(bp->cnic_ops,
446 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 447 if (c_ops) {
448 info.cmd = CNIC_CTL_STOP_CMD;
449 c_ops->cnic_ctl(bp->cnic_data, &info);
450 }
c5a88950 451 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 452}
453
454static void
455bnx2_cnic_start(struct bnx2 *bp)
456{
457 struct cnic_ops *c_ops;
458 struct cnic_ctl_info info;
459
c5a88950 460 mutex_lock(&bp->cnic_lock);
13707f9e
ED		 461 c_ops = rcu_dereference_protected(bp->cnic_ops,
462 lockdep_is_held(&bp->cnic_lock));
4edd473f
MC		 463 if (c_ops) {
464 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
465 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
466
467 bnapi->cnic_tag = bnapi->last_status_idx;
468 }
469 info.cmd = CNIC_CTL_START_CMD;
470 c_ops->cnic_ctl(bp->cnic_data, &info);
471 }
c5a88950 472 mutex_unlock(&bp->cnic_lock);
4edd473f
MC		 473}
474
475#else
476
477static void
478bnx2_cnic_stop(struct bnx2 *bp)
479{
480}
481
482static void
483bnx2_cnic_start(struct bnx2 *bp)
484{
485}
486
487#endif
488
b6016b76
MC		 489static int
490bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
491{
492 u32 val1;
493 int i, ret;
494
583c28e5 495 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
e503e066 496 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 497 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
498
e503e066
MC		 499 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
500 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 501
502 udelay(40);
503 }
504
505 val1 = (bp->phy_addr << 21) | (reg << 16) |
506 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
507 BNX2_EMAC_MDIO_COMM_START_BUSY;
e503e066 508 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
b6016b76
MC		 509
510 for (i = 0; i < 50; i++) {
511 udelay(10);
512
e503e066 513 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
b6016b76
MC		 514 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
515 udelay(5);
516
e503e066 517 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
b6016b76
MC		 518 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
519
520 break;
521 }
522 }
523
524 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
525 *val = 0x0;
526 ret = -EBUSY;
527 }
528 else {
529 *val = val1;
530 ret = 0;
531 }
532
583c28e5 533 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
e503e066 534 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 535 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
536
e503e066
MC		 537 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
538 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 539
540 udelay(40);
541 }
542
543 return ret;
544}
545
546static int
547bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
548{
549 u32 val1;
550 int i, ret;
551
583c28e5 552 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
e503e066 553 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 554 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
555
e503e066
MC		 556 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
557 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 558
559 udelay(40);
560 }
561
562 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
563 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
564 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
e503e066 565 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
6aa20a22 566
b6016b76
MC		 567 for (i = 0; i < 50; i++) {
568 udelay(10);
569
e503e066 570 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
b6016b76
MC		 571 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
572 udelay(5);
573 break;
574 }
575 }
576
577 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
578 ret = -EBUSY;
579 else
580 ret = 0;
581
583c28e5 582 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
e503e066 583 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 584 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
585
e503e066
MC		 586 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
587 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
b6016b76
MC		 588
589 udelay(40);
590 }
591
592 return ret;
593}
594
595static void
596bnx2_disable_int(struct bnx2 *bp)
597{
b4b36042
MC		 598 int i;
599 struct bnx2_napi *bnapi;
600
601 for (i = 0; i < bp->irq_nvecs; i++) {
602 bnapi = &bp->bnx2_napi[i];
e503e066 603 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
b4b36042
MC		 604 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
605 }
e503e066 606 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
b6016b76
MC		 607}
608
609static void
610bnx2_enable_int(struct bnx2 *bp)
611{
b4b36042
MC		 612 int i;
613 struct bnx2_napi *bnapi;
35efa7c1 614
b4b36042
MC		 615 for (i = 0; i < bp->irq_nvecs; i++) {
616 bnapi = &bp->bnx2_napi[i];
1269a8a6 617
e503e066
MC		 618 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
619 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
620 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
621 bnapi->last_status_idx);
b6016b76 622
e503e066
MC		 623 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
625 bnapi->last_status_idx);
b4b36042 626 }
e503e066 627 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
b6016b76
MC		 628}
629
630static void
631bnx2_disable_int_sync(struct bnx2 *bp)
632{
b4b36042
MC		 633 int i;
634
b6016b76 635 atomic_inc(&bp->intr_sem);
3767546c
MC		 636 if (!netif_running(bp->dev))
637 return;
638
b6016b76 639 bnx2_disable_int(bp);
b4b36042
MC		 640 for (i = 0; i < bp->irq_nvecs; i++)
641 synchronize_irq(bp->irq_tbl[i].vector);
b6016b76
MC		 642}
643
35efa7c1
MC		 644static void
645bnx2_napi_disable(struct bnx2 *bp)
646{
b4b36042
MC		 647 int i;
648
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_disable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 651}
652
653static void
654bnx2_napi_enable(struct bnx2 *bp)
655{
b4b36042
MC		 656 int i;
657
658 for (i = 0; i < bp->irq_nvecs; i++)
659 napi_enable(&bp->bnx2_napi[i].napi);
35efa7c1
MC		 660}
661
b6016b76 662static void
212f9934 663bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
b6016b76 664{
212f9934
MC		 665 if (stop_cnic)
666 bnx2_cnic_stop(bp);
b6016b76 667 if (netif_running(bp->dev)) {
35efa7c1 668 bnx2_napi_disable(bp);
b6016b76 669 netif_tx_disable(bp->dev);
b6016b76 670 }
b7466560 671 bnx2_disable_int_sync(bp);
a0ba6760 672 netif_carrier_off(bp->dev); /* prevent tx timeout */
b6016b76
MC		 673}
674
675static void
212f9934 676bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
b6016b76
MC		 677{
678 if (atomic_dec_and_test(&bp->intr_sem)) {
679 if (netif_running(bp->dev)) {
706bf240 680 netif_tx_wake_all_queues(bp->dev);
a0ba6760
MC		 681 spin_lock_bh(&bp->phy_lock);
682 if (bp->link_up)
683 netif_carrier_on(bp->dev);
684 spin_unlock_bh(&bp->phy_lock);
35efa7c1 685 bnx2_napi_enable(bp);
b6016b76 686 bnx2_enable_int(bp);
212f9934
MC		 687 if (start_cnic)
688 bnx2_cnic_start(bp);
b6016b76
MC		 689 }
690 }
691}
692
35e9010b
MC		 693static void
694bnx2_free_tx_mem(struct bnx2 *bp)
695{
696 int i;
697
698 for (i = 0; i < bp->num_tx_rings; i++) {
699 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
700 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
701
702 if (txr->tx_desc_ring) {
36227e88
SG		 703 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
704 txr->tx_desc_ring,
705 txr->tx_desc_mapping);
35e9010b
MC		 706 txr->tx_desc_ring = NULL;
707 }
708 kfree(txr->tx_buf_ring);
709 txr->tx_buf_ring = NULL;
710 }
711}
712
bb4f98ab
MC		 713static void
714bnx2_free_rx_mem(struct bnx2 *bp)
715{
716 int i;
717
718 for (i = 0; i < bp->num_rx_rings; i++) {
719 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
720 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
721 int j;
722
723 for (j = 0; j < bp->rx_max_ring; j++) {
724 if (rxr->rx_desc_ring[j])
36227e88
SG		 725 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
726 rxr->rx_desc_ring[j],
727 rxr->rx_desc_mapping[j]);
bb4f98ab
MC		 728 rxr->rx_desc_ring[j] = NULL;
729 }
25b0b999 730 vfree(rxr->rx_buf_ring);
bb4f98ab
MC		 731 rxr->rx_buf_ring = NULL;
732
733 for (j = 0; j < bp->rx_max_pg_ring; j++) {
734 if (rxr->rx_pg_desc_ring[j])
36227e88
SG		 735 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
736 rxr->rx_pg_desc_ring[j],
737 rxr->rx_pg_desc_mapping[j]);
3298a738 738 rxr->rx_pg_desc_ring[j] = NULL;
bb4f98ab 739 }
25b0b999 740 vfree(rxr->rx_pg_ring);
bb4f98ab
MC		 741 rxr->rx_pg_ring = NULL;
742 }
743}
744
35e9010b
MC		 745static int
746bnx2_alloc_tx_mem(struct bnx2 *bp)
747{
748 int i;
749
750 for (i = 0; i < bp->num_tx_rings; i++) {
751 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
752 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
753
754 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
755 if (txr->tx_buf_ring == NULL)
756 return -ENOMEM;
757
758 txr->tx_desc_ring =
36227e88
SG		 759 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
760 &txr->tx_desc_mapping, GFP_KERNEL);
35e9010b
MC		 761 if (txr->tx_desc_ring == NULL)
762 return -ENOMEM;
763 }
764 return 0;
765}
766
bb4f98ab
MC		 767static int
768bnx2_alloc_rx_mem(struct bnx2 *bp)
769{
770 int i;
771
772 for (i = 0; i < bp->num_rx_rings; i++) {
773 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
774 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
775 int j;
776
777 rxr->rx_buf_ring =
89bf67f1 778 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
bb4f98ab
MC		 779 if (rxr->rx_buf_ring == NULL)
780 return -ENOMEM;
781
bb4f98ab
MC		 782 for (j = 0; j < bp->rx_max_ring; j++) {
783 rxr->rx_desc_ring[j] =
36227e88
SG		 784 dma_alloc_coherent(&bp->pdev->dev,
785 RXBD_RING_SIZE,
786 &rxr->rx_desc_mapping[j],
787 GFP_KERNEL);
bb4f98ab
MC		 788 if (rxr->rx_desc_ring[j] == NULL)
789 return -ENOMEM;
790
791 }
792
793 if (bp->rx_pg_ring_size) {
89bf67f1 794 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
bb4f98ab
MC		 795 bp->rx_max_pg_ring);
796 if (rxr->rx_pg_ring == NULL)
797 return -ENOMEM;
798
bb4f98ab
MC		 799 }
800
801 for (j = 0; j < bp->rx_max_pg_ring; j++) {
802 rxr->rx_pg_desc_ring[j] =
36227e88
SG		 803 dma_alloc_coherent(&bp->pdev->dev,
804 RXBD_RING_SIZE,
805 &rxr->rx_pg_desc_mapping[j],
806 GFP_KERNEL);
bb4f98ab
MC		 807 if (rxr->rx_pg_desc_ring[j] == NULL)
808 return -ENOMEM;
809
810 }
811 }
812 return 0;
813}
814
b6016b76
MC		 815static void
816bnx2_free_mem(struct bnx2 *bp)
817{
13daffa2 818 int i;
43e80b89 819 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
13daffa2 820
35e9010b 821 bnx2_free_tx_mem(bp);
bb4f98ab 822 bnx2_free_rx_mem(bp);
35e9010b 823
59b47d8a
MC		 824 for (i = 0; i < bp->ctx_pages; i++) {
825 if (bp->ctx_blk[i]) {
2bc4078e 826 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,
36227e88
SG		 827 bp->ctx_blk[i],
828 bp->ctx_blk_mapping[i]);
59b47d8a
MC		 829 bp->ctx_blk[i] = NULL;
830 }
831 }
43e80b89 832 if (bnapi->status_blk.msi) {
36227e88
SG		 833 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
834 bnapi->status_blk.msi,
835 bp->status_blk_mapping);
43e80b89 836 bnapi->status_blk.msi = NULL;
0f31f994 837 bp->stats_blk = NULL;
b6016b76 838 }
b6016b76
MC		 839}
840
841static int
842bnx2_alloc_mem(struct bnx2 *bp)
843{
35e9010b 844 int i, status_blk_size, err;
43e80b89
MC		 845 struct bnx2_napi *bnapi;
846 void *status_blk;
b6016b76 847
0f31f994
MC		 848 /* Combine status and statistics blocks into one allocation. */
849 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
f86e82fb 850 if (bp->flags & BNX2_FLAG_MSIX_CAP)
b4b36042
MC		 851 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
852 BNX2_SBLK_MSIX_ALIGN_SIZE);
0f31f994
MC		 853 bp->status_stats_size = status_blk_size +
854 sizeof(struct statistics_block);
855
ede23fa8
JP		 856 status_blk = dma_zalloc_coherent(&bp->pdev->dev, bp->status_stats_size,
857 &bp->status_blk_mapping, GFP_KERNEL);
43e80b89 858 if (status_blk == NULL)
b6016b76
MC		 859 goto alloc_mem_err;
860
43e80b89
MC		 861 bnapi = &bp->bnx2_napi[0];
862 bnapi->status_blk.msi = status_blk;
863 bnapi->hw_tx_cons_ptr =
864 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
865 bnapi->hw_rx_cons_ptr =
866 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
f86e82fb 867 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
379b39a2 868 for (i = 1; i < bp->irq_nvecs; i++) {
43e80b89
MC		 869 struct status_block_msix *sblk;
870
871 bnapi = &bp->bnx2_napi[i];
b4b36042 872
64699336 873 sblk = (status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);
43e80b89
MC		 874 bnapi->status_blk.msix = sblk;
875 bnapi->hw_tx_cons_ptr =
876 &sblk->status_tx_quick_consumer_index;
877 bnapi->hw_rx_cons_ptr =
878 &sblk->status_rx_quick_consumer_index;
b4b36042
MC		 879 bnapi->int_num = i << 24;
880 }
881 }
35efa7c1 882
43e80b89 883 bp->stats_blk = status_blk + status_blk_size;
b6016b76 884
0f31f994 885 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
b6016b76 886
4ce45e02 887 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
2bc4078e 888 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;
59b47d8a
MC		 889 if (bp->ctx_pages == 0)
890 bp->ctx_pages = 1;
891 for (i = 0; i < bp->ctx_pages; i++) {
36227e88 892 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
2bc4078e 893 BNX2_PAGE_SIZE,
36227e88
SG		 894 &bp->ctx_blk_mapping[i],
895 GFP_KERNEL);
59b47d8a
MC		 896 if (bp->ctx_blk[i] == NULL)
897 goto alloc_mem_err;
898 }
899 }
35e9010b 900
bb4f98ab
MC		 901 err = bnx2_alloc_rx_mem(bp);
902 if (err)
903 goto alloc_mem_err;
904
35e9010b
MC		 905 err = bnx2_alloc_tx_mem(bp);
906 if (err)
907 goto alloc_mem_err;
908
b6016b76
MC		 909 return 0;
910
911alloc_mem_err:
912 bnx2_free_mem(bp);
913 return -ENOMEM;
914}
915
e3648b3d
MC		 916static void
917bnx2_report_fw_link(struct bnx2 *bp)
918{
919 u32 fw_link_status = 0;
920
583c28e5 921 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 922 return;
923
e3648b3d
MC		 924 if (bp->link_up) {
925 u32 bmsr;
926
927 switch (bp->line_speed) {
928 case SPEED_10:
929 if (bp->duplex == DUPLEX_HALF)
930 fw_link_status = BNX2_LINK_STATUS_10HALF;
931 else
932 fw_link_status = BNX2_LINK_STATUS_10FULL;
933 break;
934 case SPEED_100:
935 if (bp->duplex == DUPLEX_HALF)
936 fw_link_status = BNX2_LINK_STATUS_100HALF;
937 else
938 fw_link_status = BNX2_LINK_STATUS_100FULL;
939 break;
940 case SPEED_1000:
941 if (bp->duplex == DUPLEX_HALF)
942 fw_link_status = BNX2_LINK_STATUS_1000HALF;
943 else
944 fw_link_status = BNX2_LINK_STATUS_1000FULL;
945 break;
946 case SPEED_2500:
947 if (bp->duplex == DUPLEX_HALF)
948 fw_link_status = BNX2_LINK_STATUS_2500HALF;
949 else
950 fw_link_status = BNX2_LINK_STATUS_2500FULL;
951 break;
952 }
953
954 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
955
956 if (bp->autoneg) {
957 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
958
ca58c3af
MC		 959 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
960 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
e3648b3d
MC		 961
962 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
583c28e5 963 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
e3648b3d
MC		 964 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
965 else
966 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
967 }
968 }
969 else
970 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
971
2726d6e1 972 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
e3648b3d
MC		 973}
974
9b1084b8
MC		 975static char *
976bnx2_xceiver_str(struct bnx2 *bp)
977{
807540ba 978 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
583c28e5 979 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
807540ba 980 "Copper");
9b1084b8
MC		 981}
982
b6016b76
MC		 983static void
984bnx2_report_link(struct bnx2 *bp)
985{
986 if (bp->link_up) {
987 netif_carrier_on(bp->dev);
3a9c6a49
JP		 988 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
989 bnx2_xceiver_str(bp),
990 bp->line_speed,
991 bp->duplex == DUPLEX_FULL ? "full" : "half");
b6016b76
MC		 992
993 if (bp->flow_ctrl) {
994 if (bp->flow_ctrl & FLOW_CTRL_RX) {
3a9c6a49 995 pr_cont(", receive ");
b6016b76 996 if (bp->flow_ctrl & FLOW_CTRL_TX)
3a9c6a49 997 pr_cont("& transmit ");
b6016b76
MC		 998 }
999 else {
3a9c6a49 1000 pr_cont(", transmit ");
b6016b76 1001 }
3a9c6a49 1002 pr_cont("flow control ON");
b6016b76 1003 }
3a9c6a49
JP		 1004 pr_cont("\n");
1005 } else {
b6016b76 1006 netif_carrier_off(bp->dev);
3a9c6a49
JP		 1007 netdev_err(bp->dev, "NIC %s Link is Down\n",
1008 bnx2_xceiver_str(bp));
b6016b76 1009 }
e3648b3d
MC		 1010
1011 bnx2_report_fw_link(bp);
b6016b76
MC		 1012}
1013
1014static void
1015bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1016{
1017 u32 local_adv, remote_adv;
1018
1019 bp->flow_ctrl = 0;
6aa20a22 1020 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
b6016b76
MC		 1021 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1022
1023 if (bp->duplex == DUPLEX_FULL) {
1024 bp->flow_ctrl = bp->req_flow_ctrl;
1025 }
1026 return;
1027 }
1028
1029 if (bp->duplex != DUPLEX_FULL) {
1030 return;
1031 }
1032
583c28e5 1033 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4ce45e02 1034 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
5b0c76ad
MC		 1035 u32 val;
1036
1037 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1038 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1039 bp->flow_ctrl |= FLOW_CTRL_TX;
1040 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1041 bp->flow_ctrl |= FLOW_CTRL_RX;
1042 return;
1043 }
1044
ca58c3af
MC		 1045 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1046 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76 1047
583c28e5 1048 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1049 u32 new_local_adv = 0;
1050 u32 new_remote_adv = 0;
1051
1052 if (local_adv & ADVERTISE_1000XPAUSE)
1053 new_local_adv |= ADVERTISE_PAUSE_CAP;
1054 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1055 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1056 if (remote_adv & ADVERTISE_1000XPAUSE)
1057 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1058 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1059 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1060
1061 local_adv = new_local_adv;
1062 remote_adv = new_remote_adv;
1063 }
1064
1065 /* See Table 28B-3 of 802.3ab-1999 spec. */
1066 if (local_adv & ADVERTISE_PAUSE_CAP) {
1067 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1068 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1069 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1070 }
1071 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1072 bp->flow_ctrl = FLOW_CTRL_RX;
1073 }
1074 }
1075 else {
1076 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1077 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1078 }
1079 }
1080 }
1081 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1082 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1083 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1084
1085 bp->flow_ctrl = FLOW_CTRL_TX;
1086 }
1087 }
1088}
1089
27a005b8
MC		 1090static int
1091bnx2_5709s_linkup(struct bnx2 *bp)
1092{
1093 u32 val, speed;
1094
1095 bp->link_up = 1;
1096
1097 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1098 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1099 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1100
1101 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1102 bp->line_speed = bp->req_line_speed;
1103 bp->duplex = bp->req_duplex;
1104 return 0;
1105 }
1106 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1107 switch (speed) {
1108 case MII_BNX2_GP_TOP_AN_SPEED_10:
1109 bp->line_speed = SPEED_10;
1110 break;
1111 case MII_BNX2_GP_TOP_AN_SPEED_100:
1112 bp->line_speed = SPEED_100;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1115 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1116 bp->line_speed = SPEED_1000;
1117 break;
1118 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1119 bp->line_speed = SPEED_2500;
1120 break;
1121 }
1122 if (val & MII_BNX2_GP_TOP_AN_FD)
1123 bp->duplex = DUPLEX_FULL;
1124 else
1125 bp->duplex = DUPLEX_HALF;
1126 return 0;
1127}
1128
b6016b76 1129static int
5b0c76ad
MC		 1130bnx2_5708s_linkup(struct bnx2 *bp)
1131{
1132 u32 val;
1133
1134 bp->link_up = 1;
1135 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1136 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1137 case BCM5708S_1000X_STAT1_SPEED_10:
1138 bp->line_speed = SPEED_10;
1139 break;
1140 case BCM5708S_1000X_STAT1_SPEED_100:
1141 bp->line_speed = SPEED_100;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_1G:
1144 bp->line_speed = SPEED_1000;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_2G5:
1147 bp->line_speed = SPEED_2500;
1148 break;
1149 }
1150 if (val & BCM5708S_1000X_STAT1_FD)
1151 bp->duplex = DUPLEX_FULL;
1152 else
1153 bp->duplex = DUPLEX_HALF;
1154
1155 return 0;
1156}
1157
1158static int
1159bnx2_5706s_linkup(struct bnx2 *bp)
b6016b76
MC		 1160{
1161 u32 bmcr, local_adv, remote_adv, common;
1162
1163 bp->link_up = 1;
1164 bp->line_speed = SPEED_1000;
1165
ca58c3af 1166 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1167 if (bmcr & BMCR_FULLDPLX) {
1168 bp->duplex = DUPLEX_FULL;
1169 }
1170 else {
1171 bp->duplex = DUPLEX_HALF;
1172 }
1173
1174 if (!(bmcr & BMCR_ANENABLE)) {
1175 return 0;
1176 }
1177
ca58c3af
MC		 1178 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1179 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1180
1181 common = local_adv & remote_adv;
1182 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1183
1184 if (common & ADVERTISE_1000XFULL) {
1185 bp->duplex = DUPLEX_FULL;
1186 }
1187 else {
1188 bp->duplex = DUPLEX_HALF;
1189 }
1190 }
1191
1192 return 0;
1193}
1194
1195static int
1196bnx2_copper_linkup(struct bnx2 *bp)
1197{
1198 u32 bmcr;
1199
ca58c3af 1200 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1201 if (bmcr & BMCR_ANENABLE) {
1202 u32 local_adv, remote_adv, common;
1203
1204 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1205 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1206
1207 common = local_adv & (remote_adv >> 2);
1208 if (common & ADVERTISE_1000FULL) {
1209 bp->line_speed = SPEED_1000;
1210 bp->duplex = DUPLEX_FULL;
1211 }
1212 else if (common & ADVERTISE_1000HALF) {
1213 bp->line_speed = SPEED_1000;
1214 bp->duplex = DUPLEX_HALF;
1215 }
1216 else {
ca58c3af
MC		 1217 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1218 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
b6016b76
MC		 1219
1220 common = local_adv & remote_adv;
1221 if (common & ADVERTISE_100FULL) {
1222 bp->line_speed = SPEED_100;
1223 bp->duplex = DUPLEX_FULL;
1224 }
1225 else if (common & ADVERTISE_100HALF) {
1226 bp->line_speed = SPEED_100;
1227 bp->duplex = DUPLEX_HALF;
1228 }
1229 else if (common & ADVERTISE_10FULL) {
1230 bp->line_speed = SPEED_10;
1231 bp->duplex = DUPLEX_FULL;
1232 }
1233 else if (common & ADVERTISE_10HALF) {
1234 bp->line_speed = SPEED_10;
1235 bp->duplex = DUPLEX_HALF;
1236 }
1237 else {
1238 bp->line_speed = 0;
1239 bp->link_up = 0;
1240 }
1241 }
1242 }
1243 else {
1244 if (bmcr & BMCR_SPEED100) {
1245 bp->line_speed = SPEED_100;
1246 }
1247 else {
1248 bp->line_speed = SPEED_10;
1249 }
1250 if (bmcr & BMCR_FULLDPLX) {
1251 bp->duplex = DUPLEX_FULL;
1252 }
1253 else {
1254 bp->duplex = DUPLEX_HALF;
1255 }
1256 }
1257
1258 return 0;
1259}
1260
83e3fc89 1261static void
bb4f98ab 1262bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
83e3fc89 1263{
bb4f98ab 1264 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
83e3fc89
MC		 1265
1266 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1267 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1268 val |= 0x02 << 8;
1269
22fa159d
MC		 1270 if (bp->flow_ctrl & FLOW_CTRL_TX)
1271 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
83e3fc89 1272
83e3fc89
MC		 1273 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1274}
1275
bb4f98ab
MC		 1276static void
1277bnx2_init_all_rx_contexts(struct bnx2 *bp)
1278{
1279 int i;
1280 u32 cid;
1281
1282 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1283 if (i == 1)
1284 cid = RX_RSS_CID;
1285 bnx2_init_rx_context(bp, cid);
1286 }
1287}
1288
344478db 1289static void
b6016b76
MC		 1290bnx2_set_mac_link(struct bnx2 *bp)
1291{
1292 u32 val;
1293
e503e066 1294 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
b6016b76
MC		 1295 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1296 (bp->duplex == DUPLEX_HALF)) {
e503e066 1297 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
b6016b76
MC		 1298 }
1299
1300 /* Configure the EMAC mode register. */
e503e066 1301 val = BNX2_RD(bp, BNX2_EMAC_MODE);
b6016b76
MC		 1302
1303 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
5b0c76ad 1304 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 1305 BNX2_EMAC_MODE_25G_MODE);
b6016b76
MC		 1306
1307 if (bp->link_up) {
5b0c76ad
MC		 1308 switch (bp->line_speed) {
1309 case SPEED_10:
4ce45e02 1310 if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {
59b47d8a 1311 val |= BNX2_EMAC_MODE_PORT_MII_10M;
5b0c76ad
MC		 1312 break;
1313 }
1314 /* fall through */
1315 case SPEED_100:
1316 val |= BNX2_EMAC_MODE_PORT_MII;
1317 break;
1318 case SPEED_2500:
59b47d8a 1319 val |= BNX2_EMAC_MODE_25G_MODE;
5b0c76ad
MC		 1320 /* fall through */
1321 case SPEED_1000:
1322 val |= BNX2_EMAC_MODE_PORT_GMII;
1323 break;
1324 }
b6016b76
MC		 1325 }
1326 else {
1327 val |= BNX2_EMAC_MODE_PORT_GMII;
1328 }
1329
1330 /* Set the MAC to operate in the appropriate duplex mode. */
1331 if (bp->duplex == DUPLEX_HALF)
1332 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
e503e066 1333 BNX2_WR(bp, BNX2_EMAC_MODE, val);
b6016b76
MC		 1334
1335 /* Enable/disable rx PAUSE. */
1336 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1337
1338 if (bp->flow_ctrl & FLOW_CTRL_RX)
1339 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
e503e066 1340 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
b6016b76
MC		 1341
1342 /* Enable/disable tx PAUSE. */
e503e066 1343 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
b6016b76
MC		 1344 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1345
1346 if (bp->flow_ctrl & FLOW_CTRL_TX)
1347 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
e503e066 1348 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
b6016b76
MC		 1349
1350 /* Acknowledge the interrupt. */
e503e066 1351 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
b6016b76 1352
22fa159d 1353 bnx2_init_all_rx_contexts(bp);
b6016b76
MC		 1354}
1355
27a005b8
MC		 1356static void
1357bnx2_enable_bmsr1(struct bnx2 *bp)
1358{
583c28e5 1359 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4ce45e02 1360 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
27a005b8
MC		 1361 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1362 MII_BNX2_BLK_ADDR_GP_STATUS);
1363}
1364
1365static void
1366bnx2_disable_bmsr1(struct bnx2 *bp)
1367{
583c28e5 1368 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4ce45e02 1369 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
27a005b8
MC		 1370 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1371 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1372}
1373
605a9e20
MC		 1374static int
1375bnx2_test_and_enable_2g5(struct bnx2 *bp)
1376{
1377 u32 up1;
1378 int ret = 1;
1379
583c28e5 1380 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1381 return 0;
1382
1383 if (bp->autoneg & AUTONEG_SPEED)
1384 bp->advertising |= ADVERTISED_2500baseX_Full;
1385
4ce45e02 1386 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8
MC		 1387 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1388
605a9e20
MC		 1389 bnx2_read_phy(bp, bp->mii_up1, &up1);
1390 if (!(up1 & BCM5708S_UP1_2G5)) {
1391 up1 |= BCM5708S_UP1_2G5;
1392 bnx2_write_phy(bp, bp->mii_up1, up1);
1393 ret = 0;
1394 }
1395
4ce45e02 1396 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8
MC		 1397 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1398 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1399
605a9e20
MC		 1400 return ret;
1401}
1402
1403static int
1404bnx2_test_and_disable_2g5(struct bnx2 *bp)
1405{
1406 u32 up1;
1407 int ret = 0;
1408
583c28e5 1409 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1410 return 0;
1411
4ce45e02 1412 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8
MC		 1413 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1414
605a9e20
MC		 1415 bnx2_read_phy(bp, bp->mii_up1, &up1);
1416 if (up1 & BCM5708S_UP1_2G5) {
1417 up1 &= ~BCM5708S_UP1_2G5;
1418 bnx2_write_phy(bp, bp->mii_up1, up1);
1419 ret = 1;
1420 }
1421
4ce45e02 1422 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8
MC		 1423 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1424 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1425
605a9e20
MC		 1426 return ret;
1427}
1428
1429static void
1430bnx2_enable_forced_2g5(struct bnx2 *bp)
1431{
cbd6890c
MC		 1432 u32 uninitialized_var(bmcr);
1433 int err;
605a9e20 1434
583c28e5 1435 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1436 return;
1437
4ce45e02 1438 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
27a005b8
MC		 1439 u32 val;
1440
1441 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1442 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1443 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1444 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1445 val |= MII_BNX2_SD_MISC1_FORCE |
1446 MII_BNX2_SD_MISC1_FORCE_2_5G;
1447 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1448 }
27a005b8
MC		 1449
1450 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1451 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1452 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8 1453
4ce45e02 1454 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
cbd6890c
MC		 1455 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1456 if (!err)
1457 bmcr |= BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1458 } else {
1459 return;
605a9e20
MC		 1460 }
1461
cbd6890c
MC		 1462 if (err)
1463 return;
1464
605a9e20
MC		 1465 if (bp->autoneg & AUTONEG_SPEED) {
1466 bmcr &= ~BMCR_ANENABLE;
1467 if (bp->req_duplex == DUPLEX_FULL)
1468 bmcr |= BMCR_FULLDPLX;
1469 }
1470 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1471}
1472
1473static void
1474bnx2_disable_forced_2g5(struct bnx2 *bp)
1475{
cbd6890c
MC		 1476 u32 uninitialized_var(bmcr);
1477 int err;
605a9e20 1478
583c28e5 1479 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
605a9e20
MC		 1480 return;
1481
4ce45e02 1482 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
27a005b8
MC		 1483 u32 val;
1484
1485 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1486 MII_BNX2_BLK_ADDR_SERDES_DIG);
cbd6890c
MC		 1487 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1488 val &= ~MII_BNX2_SD_MISC1_FORCE;
1489 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1490 }
27a005b8
MC		 1491
1492 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1493 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
cbd6890c 1494 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
27a005b8 1495
4ce45e02 1496 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
cbd6890c
MC		 1497 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1498 if (!err)
1499 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
c7079857
ED		 1500 } else {
1501 return;
605a9e20
MC		 1502 }
1503
cbd6890c
MC		 1504 if (err)
1505 return;
1506
605a9e20
MC		 1507 if (bp->autoneg & AUTONEG_SPEED)
1508 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1509 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1510}
1511
b2fadeae
MC		 1512static void
1513bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1514{
1515 u32 val;
1516
1517 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1518 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1519 if (start)
1520 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1521 else
1522 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1523}
1524
b6016b76
MC		 1525static int
1526bnx2_set_link(struct bnx2 *bp)
1527{
1528 u32 bmsr;
1529 u8 link_up;
1530
80be4434 1531 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
b6016b76
MC		 1532 bp->link_up = 1;
1533 return 0;
1534 }
1535
583c28e5 1536 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 1537 return 0;
1538
b6016b76
MC		 1539 link_up = bp->link_up;
1540
27a005b8
MC		 1541 bnx2_enable_bmsr1(bp);
1542 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1543 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1544 bnx2_disable_bmsr1(bp);
b6016b76 1545
583c28e5 1546 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4ce45e02 1547 (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {
a2724e25 1548 u32 val, an_dbg;
b6016b76 1549
583c28e5 1550 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
b2fadeae 1551 bnx2_5706s_force_link_dn(bp, 0);
583c28e5 1552 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
b2fadeae 1553 }
e503e066 1554 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
a2724e25
MC		 1555
1556 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1557 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1558 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1559
1560 if ((val & BNX2_EMAC_STATUS_LINK) &&
1561 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
b6016b76
MC		 1562 bmsr |= BMSR_LSTATUS;
1563 else
1564 bmsr &= ~BMSR_LSTATUS;
1565 }
1566
1567 if (bmsr & BMSR_LSTATUS) {
1568 bp->link_up = 1;
1569
583c28e5 1570 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
4ce45e02 1571 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
5b0c76ad 1572 bnx2_5706s_linkup(bp);
4ce45e02 1573 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
5b0c76ad 1574 bnx2_5708s_linkup(bp);
4ce45e02 1575 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
27a005b8 1576 bnx2_5709s_linkup(bp);
b6016b76
MC		 1577 }
1578 else {
1579 bnx2_copper_linkup(bp);
1580 }
1581 bnx2_resolve_flow_ctrl(bp);
1582 }
1583 else {
583c28e5 1584 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
605a9e20
MC		 1585 (bp->autoneg & AUTONEG_SPEED))
1586 bnx2_disable_forced_2g5(bp);
b6016b76 1587
583c28e5 1588 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
b2fadeae
MC		 1589 u32 bmcr;
1590
1591 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1592 bmcr |= BMCR_ANENABLE;
1593 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1594
583c28e5 1595 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b2fadeae 1596 }
b6016b76
MC		 1597 bp->link_up = 0;
1598 }
1599
1600 if (bp->link_up != link_up) {
1601 bnx2_report_link(bp);
1602 }
1603
1604 bnx2_set_mac_link(bp);
1605
1606 return 0;
1607}
1608
1609static int
1610bnx2_reset_phy(struct bnx2 *bp)
1611{
1612 int i;
1613 u32 reg;
1614
ca58c3af 1615 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
b6016b76
MC		 1616
1617#define PHY_RESET_MAX_WAIT 100
1618 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1619 udelay(10);
1620
ca58c3af 1621 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
b6016b76
MC		 1622 if (!(reg & BMCR_RESET)) {
1623 udelay(20);
1624 break;
1625 }
1626 }
1627 if (i == PHY_RESET_MAX_WAIT) {
1628 return -EBUSY;
1629 }
1630 return 0;
1631}
1632
1633static u32
1634bnx2_phy_get_pause_adv(struct bnx2 *bp)
1635{
1636 u32 adv = 0;
1637
1638 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1639 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1640
583c28e5 1641 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1642 adv = ADVERTISE_1000XPAUSE;
1643 }
1644 else {
1645 adv = ADVERTISE_PAUSE_CAP;
1646 }
1647 }
1648 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
583c28e5 1649 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1650 adv = ADVERTISE_1000XPSE_ASYM;
1651 }
1652 else {
1653 adv = ADVERTISE_PAUSE_ASYM;
1654 }
1655 }
1656 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
583c28e5 1657 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
b6016b76
MC		 1658 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1659 }
1660 else {
1661 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1662 }
1663 }
1664 return adv;
1665}
1666
a2f13890 1667static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
0d8a6571 1668
b6016b76 1669static int
0d8a6571 1670bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1671__releases(&bp->phy_lock)
1672__acquires(&bp->phy_lock)
0d8a6571
MC		 1673{
1674 u32 speed_arg = 0, pause_adv;
1675
1676 pause_adv = bnx2_phy_get_pause_adv(bp);
1677
1678 if (bp->autoneg & AUTONEG_SPEED) {
1679 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1680 if (bp->advertising & ADVERTISED_10baseT_Half)
1681 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1682 if (bp->advertising & ADVERTISED_10baseT_Full)
1683 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1684 if (bp->advertising & ADVERTISED_100baseT_Half)
1685 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1686 if (bp->advertising & ADVERTISED_100baseT_Full)
1687 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1688 if (bp->advertising & ADVERTISED_1000baseT_Full)
1689 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1690 if (bp->advertising & ADVERTISED_2500baseX_Full)
1691 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1692 } else {
1693 if (bp->req_line_speed == SPEED_2500)
1694 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1695 else if (bp->req_line_speed == SPEED_1000)
1696 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1697 else if (bp->req_line_speed == SPEED_100) {
1698 if (bp->req_duplex == DUPLEX_FULL)
1699 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1700 else
1701 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1702 } else if (bp->req_line_speed == SPEED_10) {
1703 if (bp->req_duplex == DUPLEX_FULL)
1704 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1705 else
1706 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1707 }
1708 }
1709
1710 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1711 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
c26736ec 1712 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
0d8a6571
MC		 1713 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1714
1715 if (port == PORT_TP)
1716 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1717 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1718
2726d6e1 1719 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
0d8a6571
MC		 1720
1721 spin_unlock_bh(&bp->phy_lock);
a2f13890 1722 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
0d8a6571
MC		 1723 spin_lock_bh(&bp->phy_lock);
1724
1725 return 0;
1726}
1727
1728static int
1729bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 1730__releases(&bp->phy_lock)
1731__acquires(&bp->phy_lock)
b6016b76 1732{
605a9e20 1733 u32 adv, bmcr;
b6016b76
MC		 1734 u32 new_adv = 0;
1735
583c28e5 1736 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
807540ba 1737 return bnx2_setup_remote_phy(bp, port);
0d8a6571 1738
b6016b76
MC		 1739 if (!(bp->autoneg & AUTONEG_SPEED)) {
1740 u32 new_bmcr;
5b0c76ad
MC		 1741 int force_link_down = 0;
1742
605a9e20
MC		 1743 if (bp->req_line_speed == SPEED_2500) {
1744 if (!bnx2_test_and_enable_2g5(bp))
1745 force_link_down = 1;
1746 } else if (bp->req_line_speed == SPEED_1000) {
1747 if (bnx2_test_and_disable_2g5(bp))
1748 force_link_down = 1;
1749 }
ca58c3af 1750 bnx2_read_phy(bp, bp->mii_adv, &adv);
80be4434
MC		 1751 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1752
ca58c3af 1753 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
605a9e20 1754 new_bmcr = bmcr & ~BMCR_ANENABLE;
80be4434 1755 new_bmcr |= BMCR_SPEED1000;
605a9e20 1756
4ce45e02 1757 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
27a005b8
MC		 1758 if (bp->req_line_speed == SPEED_2500)
1759 bnx2_enable_forced_2g5(bp);
1760 else if (bp->req_line_speed == SPEED_1000) {
1761 bnx2_disable_forced_2g5(bp);
1762 new_bmcr &= ~0x2000;
1763 }
1764
4ce45e02 1765 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
605a9e20
MC		 1766 if (bp->req_line_speed == SPEED_2500)
1767 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1768 else
1769 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
5b0c76ad
MC		 1770 }
1771
b6016b76 1772 if (bp->req_duplex == DUPLEX_FULL) {
5b0c76ad 1773 adv |= ADVERTISE_1000XFULL;
b6016b76
MC		 1774 new_bmcr |= BMCR_FULLDPLX;
1775 }
1776 else {
5b0c76ad 1777 adv |= ADVERTISE_1000XHALF;
b6016b76
MC		 1778 new_bmcr &= ~BMCR_FULLDPLX;
1779 }
5b0c76ad 1780 if ((new_bmcr != bmcr) || (force_link_down)) {
b6016b76
MC		 1781 /* Force a link down visible on the other side */
1782 if (bp->link_up) {
ca58c3af 1783 bnx2_write_phy(bp, bp->mii_adv, adv &
5b0c76ad
MC		 1784 ~(ADVERTISE_1000XFULL |
1785 ADVERTISE_1000XHALF));
ca58c3af 1786 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
b6016b76
MC		 1787 BMCR_ANRESTART | BMCR_ANENABLE);
1788
1789 bp->link_up = 0;
1790 netif_carrier_off(bp->dev);
ca58c3af 1791 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
80be4434 1792 bnx2_report_link(bp);
b6016b76 1793 }
ca58c3af
MC		 1794 bnx2_write_phy(bp, bp->mii_adv, adv);
1795 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
605a9e20
MC		 1796 } else {
1797 bnx2_resolve_flow_ctrl(bp);
1798 bnx2_set_mac_link(bp);
b6016b76
MC		 1799 }
1800 return 0;
1801 }
1802
605a9e20 1803 bnx2_test_and_enable_2g5(bp);
5b0c76ad 1804
b6016b76
MC		 1805 if (bp->advertising & ADVERTISED_1000baseT_Full)
1806 new_adv |= ADVERTISE_1000XFULL;
1807
1808 new_adv |= bnx2_phy_get_pause_adv(bp);
1809
ca58c3af
MC		 1810 bnx2_read_phy(bp, bp->mii_adv, &adv);
1811 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 1812
1813 bp->serdes_an_pending = 0;
1814 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1815 /* Force a link down visible on the other side */
1816 if (bp->link_up) {
ca58c3af 1817 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
80be4434
MC		 1818 spin_unlock_bh(&bp->phy_lock);
1819 msleep(20);
1820 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 1821 }
1822
ca58c3af
MC		 1823 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1824 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
b6016b76 1825 BMCR_ANENABLE);
f8dd064e
MC		 1826 /* Speed up link-up time when the link partner
1827 * does not autonegotiate which is very common
1828 * in blade servers. Some blade servers use
1829 * IPMI for kerboard input and it's important
1830 * to minimize link disruptions. Autoneg. involves
1831 * exchanging base pages plus 3 next pages and
1832 * normally completes in about 120 msec.
1833 */
40105c0b 1834 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 1835 bp->serdes_an_pending = 1;
1836 mod_timer(&bp->timer, jiffies + bp->current_interval);
605a9e20
MC		 1837 } else {
1838 bnx2_resolve_flow_ctrl(bp);
1839 bnx2_set_mac_link(bp);
b6016b76
MC		 1840 }
1841
1842 return 0;
1843}
1844
1845#define ETHTOOL_ALL_FIBRE_SPEED \
583c28e5 1846 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
deaf391b
MC		 1847 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1848 (ADVERTISED_1000baseT_Full)
b6016b76
MC		 1849
1850#define ETHTOOL_ALL_COPPER_SPEED \
1851 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1852 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1853 ADVERTISED_1000baseT_Full)
1854
1855#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1856 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
6aa20a22 1857
b6016b76
MC		 1858#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1859
0d8a6571
MC		 1860static void
1861bnx2_set_default_remote_link(struct bnx2 *bp)
1862{
1863 u32 link;
1864
1865 if (bp->phy_port == PORT_TP)
2726d6e1 1866 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
0d8a6571 1867 else
2726d6e1 1868 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
0d8a6571
MC		 1869
1870 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1871 bp->req_line_speed = 0;
1872 bp->autoneg |= AUTONEG_SPEED;
1873 bp->advertising = ADVERTISED_Autoneg;
1874 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1875 bp->advertising |= ADVERTISED_10baseT_Half;
1876 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1877 bp->advertising |= ADVERTISED_10baseT_Full;
1878 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1879 bp->advertising |= ADVERTISED_100baseT_Half;
1880 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1881 bp->advertising |= ADVERTISED_100baseT_Full;
1882 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1883 bp->advertising |= ADVERTISED_1000baseT_Full;
1884 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1885 bp->advertising |= ADVERTISED_2500baseX_Full;
1886 } else {
1887 bp->autoneg = 0;
1888 bp->advertising = 0;
1889 bp->req_duplex = DUPLEX_FULL;
1890 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1891 bp->req_line_speed = SPEED_10;
1892 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1893 bp->req_duplex = DUPLEX_HALF;
1894 }
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1896 bp->req_line_speed = SPEED_100;
1897 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1898 bp->req_duplex = DUPLEX_HALF;
1899 }
1900 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1901 bp->req_line_speed = SPEED_1000;
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1903 bp->req_line_speed = SPEED_2500;
1904 }
1905}
1906
deaf391b
MC		 1907static void
1908bnx2_set_default_link(struct bnx2 *bp)
1909{
ab59859d
HH		 1910 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1911 bnx2_set_default_remote_link(bp);
1912 return;
1913 }
0d8a6571 1914
deaf391b
MC		 1915 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1916 bp->req_line_speed = 0;
583c28e5 1917 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
deaf391b
MC		 1918 u32 reg;
1919
1920 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1921
2726d6e1 1922 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
deaf391b
MC		 1923 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1924 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1925 bp->autoneg = 0;
1926 bp->req_line_speed = bp->line_speed = SPEED_1000;
1927 bp->req_duplex = DUPLEX_FULL;
1928 }
1929 } else
1930 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1931}
1932
df149d70
MC		 1933static void
1934bnx2_send_heart_beat(struct bnx2 *bp)
1935{
1936 u32 msg;
1937 u32 addr;
1938
1939 spin_lock(&bp->indirect_lock);
1940 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1941 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
e503e066
MC		 1942 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1943 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
df149d70
MC		 1944 spin_unlock(&bp->indirect_lock);
1945}
1946
0d8a6571
MC		 1947static void
1948bnx2_remote_phy_event(struct bnx2 *bp)
1949{
1950 u32 msg;
1951 u8 link_up = bp->link_up;
1952 u8 old_port;
1953
2726d6e1 1954 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
0d8a6571 1955
df149d70
MC		 1956 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1957 bnx2_send_heart_beat(bp);
1958
1959 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1960
0d8a6571
MC		 1961 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1962 bp->link_up = 0;
1963 else {
1964 u32 speed;
1965
1966 bp->link_up = 1;
1967 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1968 bp->duplex = DUPLEX_FULL;
1969 switch (speed) {
1970 case BNX2_LINK_STATUS_10HALF:
1971 bp->duplex = DUPLEX_HALF;
7947c9ce 1972 /* fall through */
0d8a6571
MC		 1973 case BNX2_LINK_STATUS_10FULL:
1974 bp->line_speed = SPEED_10;
1975 break;
1976 case BNX2_LINK_STATUS_100HALF:
1977 bp->duplex = DUPLEX_HALF;
7947c9ce 1978 /* fall through */
0d8a6571
MC		 1979 case BNX2_LINK_STATUS_100BASE_T4:
1980 case BNX2_LINK_STATUS_100FULL:
1981 bp->line_speed = SPEED_100;
1982 break;
1983 case BNX2_LINK_STATUS_1000HALF:
1984 bp->duplex = DUPLEX_HALF;
7947c9ce 1985 /* fall through */
0d8a6571
MC		 1986 case BNX2_LINK_STATUS_1000FULL:
1987 bp->line_speed = SPEED_1000;
1988 break;
1989 case BNX2_LINK_STATUS_2500HALF:
1990 bp->duplex = DUPLEX_HALF;
7947c9ce 1991 /* fall through */
0d8a6571
MC		 1992 case BNX2_LINK_STATUS_2500FULL:
1993 bp->line_speed = SPEED_2500;
1994 break;
1995 default:
1996 bp->line_speed = 0;
1997 break;
1998 }
1999
0d8a6571
MC		 2000 bp->flow_ctrl = 0;
2001 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2002 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2003 if (bp->duplex == DUPLEX_FULL)
2004 bp->flow_ctrl = bp->req_flow_ctrl;
2005 } else {
2006 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2007 bp->flow_ctrl |= FLOW_CTRL_TX;
2008 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2009 bp->flow_ctrl |= FLOW_CTRL_RX;
2010 }
2011
2012 old_port = bp->phy_port;
2013 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2014 bp->phy_port = PORT_FIBRE;
2015 else
2016 bp->phy_port = PORT_TP;
2017
2018 if (old_port != bp->phy_port)
2019 bnx2_set_default_link(bp);
2020
0d8a6571
MC		 2021 }
2022 if (bp->link_up != link_up)
2023 bnx2_report_link(bp);
2024
2025 bnx2_set_mac_link(bp);
2026}
2027
2028static int
2029bnx2_set_remote_link(struct bnx2 *bp)
2030{
2031 u32 evt_code;
2032
2726d6e1 2033 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
0d8a6571
MC		 2034 switch (evt_code) {
2035 case BNX2_FW_EVT_CODE_LINK_EVENT:
2036 bnx2_remote_phy_event(bp);
2037 break;
2038 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2039 default:
df149d70 2040 bnx2_send_heart_beat(bp);
0d8a6571
MC		 2041 break;
2042 }
2043 return 0;
2044}
2045
b6016b76
MC		 2046static int
2047bnx2_setup_copper_phy(struct bnx2 *bp)
52d07b1f
HH		 2048__releases(&bp->phy_lock)
2049__acquires(&bp->phy_lock)
b6016b76
MC		 2050{
2051 u32 bmcr;
2052 u32 new_bmcr;
2053
ca58c3af 2054 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76
MC		 2055
2056 if (bp->autoneg & AUTONEG_SPEED) {
2057 u32 adv_reg, adv1000_reg;
37f07023
MC		 2058 u32 new_adv = 0;
2059 u32 new_adv1000 = 0;
b6016b76 2060
ca58c3af 2061 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
b6016b76
MC		 2062 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2063 ADVERTISE_PAUSE_ASYM);
2064
2065 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2066 adv1000_reg &= PHY_ALL_1000_SPEED;
2067
37f07023
MC		 2068 new_adv = ethtool_adv_to_mii_adv_t(bp->advertising);
2069 new_adv |= ADVERTISE_CSMA;
2070 new_adv |= bnx2_phy_get_pause_adv(bp);
b6016b76 2071
37f07023 2072 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
28011cf1 2073
37f07023
MC		 2074 if ((adv1000_reg != new_adv1000) ||
2075 (adv_reg != new_adv) ||
b6016b76
MC		 2076 ((bmcr & BMCR_ANENABLE) == 0)) {
2077
37f07023
MC		 2078 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2079 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
ca58c3af 2080 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
b6016b76
MC		 2081 BMCR_ANENABLE);
2082 }
2083 else if (bp->link_up) {
2084 /* Flow ctrl may have changed from auto to forced */
2085 /* or vice-versa. */
2086
2087 bnx2_resolve_flow_ctrl(bp);
2088 bnx2_set_mac_link(bp);
2089 }
2090 return 0;
2091 }
2092
2093 new_bmcr = 0;
2094 if (bp->req_line_speed == SPEED_100) {
2095 new_bmcr |= BMCR_SPEED100;
2096 }
2097 if (bp->req_duplex == DUPLEX_FULL) {
2098 new_bmcr |= BMCR_FULLDPLX;
2099 }
2100 if (new_bmcr != bmcr) {
2101 u32 bmsr;
b6016b76 2102
ca58c3af
MC		 2103 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2104 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
6aa20a22 2105
b6016b76
MC		 2106 if (bmsr & BMSR_LSTATUS) {
2107 /* Force link down */
ca58c3af 2108 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
a16dda0e
MC		 2109 spin_unlock_bh(&bp->phy_lock);
2110 msleep(50);
2111 spin_lock_bh(&bp->phy_lock);
2112
ca58c3af
MC		 2113 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2114 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
b6016b76
MC		 2115 }
2116
ca58c3af 2117 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
b6016b76
MC		 2118
2119 /* Normally, the new speed is setup after the link has
2120 * gone down and up again. In some cases, link will not go
2121 * down so we need to set up the new speed here.
2122 */
2123 if (bmsr & BMSR_LSTATUS) {
2124 bp->line_speed = bp->req_line_speed;
2125 bp->duplex = bp->req_duplex;
2126 bnx2_resolve_flow_ctrl(bp);
2127 bnx2_set_mac_link(bp);
2128 }
27a005b8
MC		 2129 } else {
2130 bnx2_resolve_flow_ctrl(bp);
2131 bnx2_set_mac_link(bp);
b6016b76
MC		 2132 }
2133 return 0;
2134}
2135
2136static int
0d8a6571 2137bnx2_setup_phy(struct bnx2 *bp, u8 port)
52d07b1f
HH		 2138__releases(&bp->phy_lock)
2139__acquires(&bp->phy_lock)
b6016b76
MC		 2140{
2141 if (bp->loopback == MAC_LOOPBACK)
2142 return 0;
2143
583c28e5 2144 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
807540ba 2145 return bnx2_setup_serdes_phy(bp, port);
b6016b76
MC		 2146 }
2147 else {
807540ba 2148 return bnx2_setup_copper_phy(bp);
b6016b76
MC		 2149 }
2150}
2151
27a005b8 2152static int
9a120bc5 2153bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
27a005b8
MC		 2154{
2155 u32 val;
2156
2157 bp->mii_bmcr = MII_BMCR + 0x10;
2158 bp->mii_bmsr = MII_BMSR + 0x10;
2159 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2160 bp->mii_adv = MII_ADVERTISE + 0x10;
2161 bp->mii_lpa = MII_LPA + 0x10;
2162 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2163
2164 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2165 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2166
2167 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
9a120bc5
MC		 2168 if (reset_phy)
2169 bnx2_reset_phy(bp);
27a005b8
MC		 2170
2171 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2172
2173 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2174 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2175 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2176 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2177
2178 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2179 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
583c28e5 2180 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
27a005b8
MC		 2181 val |= BCM5708S_UP1_2G5;
2182 else
2183 val &= ~BCM5708S_UP1_2G5;
2184 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2185
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2187 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2188 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2189 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2190
2191 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2192
2193 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2194 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2195 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2196
2197 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2198
2199 return 0;
2200}
2201
b6016b76 2202static int
9a120bc5 2203bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
5b0c76ad
MC		 2204{
2205 u32 val;
2206
9a120bc5
MC		 2207 if (reset_phy)
2208 bnx2_reset_phy(bp);
27a005b8
MC		 2209
2210 bp->mii_up1 = BCM5708S_UP1;
2211
5b0c76ad
MC		 2212 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2213 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2214 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2215
2216 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2217 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2218 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2219
2220 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2221 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2222 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2223
583c28e5 2224 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
5b0c76ad
MC		 2225 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2226 val |= BCM5708S_UP1_2G5;
2227 bnx2_write_phy(bp, BCM5708S_UP1, val);
2228 }
2229
4ce45e02
MC		 2230 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
2231 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
2232 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {
5b0c76ad
MC		 2233 /* increase tx signal amplitude */
2234 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2235 BCM5708S_BLK_ADDR_TX_MISC);
2236 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2237 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2238 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2239 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2240 }
2241
2726d6e1 2242 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
5b0c76ad
MC		 2243 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2244
2245 if (val) {
2246 u32 is_backplane;
2247
2726d6e1 2248 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
5b0c76ad
MC		 2249 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2250 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2251 BCM5708S_BLK_ADDR_TX_MISC);
2252 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2253 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2254 BCM5708S_BLK_ADDR_DIG);
2255 }
2256 }
2257 return 0;
2258}
2259
2260static int
9a120bc5 2261bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2262{
9a120bc5
MC		 2263 if (reset_phy)
2264 bnx2_reset_phy(bp);
27a005b8 2265
583c28e5 2266 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
b6016b76 2267
4ce45e02 2268 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
e503e066 2269 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
b6016b76
MC		 2270
2271 if (bp->dev->mtu > 1500) {
2272 u32 val;
2273
2274 /* Set extended packet length bit */
2275 bnx2_write_phy(bp, 0x18, 0x7);
2276 bnx2_read_phy(bp, 0x18, &val);
2277 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2278
2279 bnx2_write_phy(bp, 0x1c, 0x6c00);
2280 bnx2_read_phy(bp, 0x1c, &val);
2281 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2282 }
2283 else {
2284 u32 val;
2285
2286 bnx2_write_phy(bp, 0x18, 0x7);
2287 bnx2_read_phy(bp, 0x18, &val);
2288 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2289
2290 bnx2_write_phy(bp, 0x1c, 0x6c00);
2291 bnx2_read_phy(bp, 0x1c, &val);
2292 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2293 }
2294
2295 return 0;
2296}
2297
2298static int
9a120bc5 2299bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
b6016b76 2300{
5b0c76ad
MC		 2301 u32 val;
2302
9a120bc5
MC		 2303 if (reset_phy)
2304 bnx2_reset_phy(bp);
27a005b8 2305
583c28e5 2306 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
b6016b76
MC		 2307 bnx2_write_phy(bp, 0x18, 0x0c00);
2308 bnx2_write_phy(bp, 0x17, 0x000a);
2309 bnx2_write_phy(bp, 0x15, 0x310b);
2310 bnx2_write_phy(bp, 0x17, 0x201f);
2311 bnx2_write_phy(bp, 0x15, 0x9506);
2312 bnx2_write_phy(bp, 0x17, 0x401f);
2313 bnx2_write_phy(bp, 0x15, 0x14e2);
2314 bnx2_write_phy(bp, 0x18, 0x0400);
2315 }
2316
583c28e5 2317 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
b659f44e
MC		 2318 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2319 MII_BNX2_DSP_EXPAND_REG | 0x8);
2320 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2321 val &= ~(1 << 8);
2322 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2323 }
2324
b6016b76 2325 if (bp->dev->mtu > 1500) {
b6016b76
MC		 2326 /* Set extended packet length bit */
2327 bnx2_write_phy(bp, 0x18, 0x7);
2328 bnx2_read_phy(bp, 0x18, &val);
2329 bnx2_write_phy(bp, 0x18, val | 0x4000);
2330
2331 bnx2_read_phy(bp, 0x10, &val);
2332 bnx2_write_phy(bp, 0x10, val | 0x1);
2333 }
2334 else {
b6016b76
MC		 2335 bnx2_write_phy(bp, 0x18, 0x7);
2336 bnx2_read_phy(bp, 0x18, &val);
2337 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2338
2339 bnx2_read_phy(bp, 0x10, &val);
2340 bnx2_write_phy(bp, 0x10, val & ~0x1);
2341 }
2342
5b0c76ad
MC		 2343 /* ethernet@wirespeed */
2344 bnx2_write_phy(bp, 0x18, 0x7007);
2345 bnx2_read_phy(bp, 0x18, &val);
2346 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
b6016b76
MC		 2347 return 0;
2348}
2349
2350
2351static int
9a120bc5 2352bnx2_init_phy(struct bnx2 *bp, int reset_phy)
52d07b1f
HH		 2353__releases(&bp->phy_lock)
2354__acquires(&bp->phy_lock)
b6016b76
MC		 2355{
2356 u32 val;
2357 int rc = 0;
2358
583c28e5
MC		 2359 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2360 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
b6016b76 2361
ca58c3af
MC		 2362 bp->mii_bmcr = MII_BMCR;
2363 bp->mii_bmsr = MII_BMSR;
27a005b8 2364 bp->mii_bmsr1 = MII_BMSR;
ca58c3af
MC		 2365 bp->mii_adv = MII_ADVERTISE;
2366 bp->mii_lpa = MII_LPA;
2367
e503e066 2368 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
b6016b76 2369
583c28e5 2370 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 2371 goto setup_phy;
2372
b6016b76
MC		 2373 bnx2_read_phy(bp, MII_PHYSID1, &val);
2374 bp->phy_id = val << 16;
2375 bnx2_read_phy(bp, MII_PHYSID2, &val);
2376 bp->phy_id |= val & 0xffff;
2377
583c28e5 2378 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
4ce45e02 2379 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
9a120bc5 2380 rc = bnx2_init_5706s_phy(bp, reset_phy);
4ce45e02 2381 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
9a120bc5 2382 rc = bnx2_init_5708s_phy(bp, reset_phy);
4ce45e02 2383 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
9a120bc5 2384 rc = bnx2_init_5709s_phy(bp, reset_phy);
b6016b76
MC		 2385 }
2386 else {
9a120bc5 2387 rc = bnx2_init_copper_phy(bp, reset_phy);
b6016b76
MC		 2388 }
2389
0d8a6571
MC		 2390setup_phy:
2391 if (!rc)
2392 rc = bnx2_setup_phy(bp, bp->phy_port);
b6016b76
MC		 2393
2394 return rc;
2395}
2396
2397static int
2398bnx2_set_mac_loopback(struct bnx2 *bp)
2399{
2400 u32 mac_mode;
2401
e503e066 2402 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
b6016b76
MC		 2403 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2404 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
e503e066 2405 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
b6016b76
MC		 2406 bp->link_up = 1;
2407 return 0;
2408}
2409
bc5a0690
MC		 2410static int bnx2_test_link(struct bnx2 *);
2411
2412static int
2413bnx2_set_phy_loopback(struct bnx2 *bp)
2414{
2415 u32 mac_mode;
2416 int rc, i;
2417
2418 spin_lock_bh(&bp->phy_lock);
ca58c3af 2419 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
bc5a0690
MC		 2420 BMCR_SPEED1000);
2421 spin_unlock_bh(&bp->phy_lock);
2422 if (rc)
2423 return rc;
2424
2425 for (i = 0; i < 10; i++) {
2426 if (bnx2_test_link(bp) == 0)
2427 break;
80be4434 2428 msleep(100);
bc5a0690
MC		 2429 }
2430
e503e066 2431 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
bc5a0690
MC		 2432 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2433 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
59b47d8a 2434 BNX2_EMAC_MODE_25G_MODE);
bc5a0690
MC		 2435
2436 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
e503e066 2437 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
bc5a0690
MC		 2438 bp->link_up = 1;
2439 return 0;
2440}
2441
ecdbf6e0
JH		 2442static void
2443bnx2_dump_mcp_state(struct bnx2 *bp)
2444{
2445 struct net_device *dev = bp->dev;
2446 u32 mcp_p0, mcp_p1;
2447
2448 netdev_err(dev, "<--- start MCP states dump --->\n");
4ce45e02 2449 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
ecdbf6e0
JH		 2450 mcp_p0 = BNX2_MCP_STATE_P0;
2451 mcp_p1 = BNX2_MCP_STATE_P1;
2452 } else {
2453 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2454 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2455 }
2456 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2457 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2458 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2459 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2460 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2461 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2462 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2463 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2464 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2465 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2466 netdev_err(dev, "DEBUG: shmem states:\n");
2467 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2468 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2469 bnx2_shmem_rd(bp, BNX2_FW_MB),
2470 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2471 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2472 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2473 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2474 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2475 pr_cont(" condition[%08x]\n",
2476 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
13e63517 2477 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);
ecdbf6e0
JH		 2478 DP_SHMEM_LINE(bp, 0x3cc);
2479 DP_SHMEM_LINE(bp, 0x3dc);
2480 DP_SHMEM_LINE(bp, 0x3ec);
2481 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2482 netdev_err(dev, "<--- end MCP states dump --->\n");
2483}
2484
b6016b76 2485static int
a2f13890 2486bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
b6016b76
MC		 2487{
2488 int i;
2489 u32 val;
2490
b6016b76
MC		 2491 bp->fw_wr_seq++;
2492 msg_data |= bp->fw_wr_seq;
2493
2726d6e1 2494 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
b6016b76 2495
a2f13890
MC		 2496 if (!ack)
2497 return 0;
2498
b6016b76 2499 /* wait for an acknowledgement. */
40105c0b 2500 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
b090ae2b 2501 msleep(10);
b6016b76 2502
2726d6e1 2503 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
b6016b76
MC		 2504
2505 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2506 break;
2507 }
b090ae2b
MC		 2508 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2509 return 0;
b6016b76
MC		 2510
2511 /* If we timed out, inform the firmware that this is the case. */
b090ae2b 2512 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
b6016b76
MC		 2513 msg_data &= ~BNX2_DRV_MSG_CODE;
2514 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2515
2726d6e1 2516 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
ecdbf6e0
JH		 2517 if (!silent) {
2518 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2519 bnx2_dump_mcp_state(bp);
2520 }
b6016b76 2521
b6016b76
MC		 2522 return -EBUSY;
2523 }
2524
b090ae2b
MC		 2525 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2526 return -EIO;
2527
b6016b76
MC		 2528 return 0;
2529}
2530
59b47d8a
MC		 2531static int
2532bnx2_init_5709_context(struct bnx2 *bp)
2533{
2534 int i, ret = 0;
2535 u32 val;
2536
2537 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2bc4078e 2538 val |= (BNX2_PAGE_BITS - 8) << 16;
e503e066 2539 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
641bdcd5 2540 for (i = 0; i < 10; i++) {
e503e066 2541 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
641bdcd5
MC		 2542 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2543 break;
2544 udelay(2);
2545 }
2546 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2547 return -EBUSY;
2548
59b47d8a
MC		 2549 for (i = 0; i < bp->ctx_pages; i++) {
2550 int j;
2551
352f7687 2552 if (bp->ctx_blk[i])
2bc4078e 2553 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);
352f7687
MC		 2554 else
2555 return -ENOMEM;
2556
e503e066
MC		 2557 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2558 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2559 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2560 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2561 (u64) bp->ctx_blk_mapping[i] >> 32);
2562 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2563 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
59b47d8a
MC		 2564 for (j = 0; j < 10; j++) {
2565
e503e066 2566 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
59b47d8a
MC		 2567 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2568 break;
2569 udelay(5);
2570 }
2571 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2572 ret = -EBUSY;
2573 break;
2574 }
2575 }
2576 return ret;
2577}
2578
b6016b76
MC		 2579static void
2580bnx2_init_context(struct bnx2 *bp)
2581{
2582 u32 vcid;
2583
2584 vcid = 96;
2585 while (vcid) {
2586 u32 vcid_addr, pcid_addr, offset;
7947b20e 2587 int i;
b6016b76
MC		 2588
2589 vcid--;
2590
4ce45e02 2591 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
b6016b76
MC		 2592 u32 new_vcid;
2593
2594 vcid_addr = GET_PCID_ADDR(vcid);
2595 if (vcid & 0x8) {
2596 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2597 }
2598 else {
2599 new_vcid = vcid;
2600 }
2601 pcid_addr = GET_PCID_ADDR(new_vcid);
2602 }
2603 else {
2604 vcid_addr = GET_CID_ADDR(vcid);
2605 pcid_addr = vcid_addr;
2606 }
2607
7947b20e
MC		 2608 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2609 vcid_addr += (i << PHY_CTX_SHIFT);
2610 pcid_addr += (i << PHY_CTX_SHIFT);
b6016b76 2611
e503e066
MC		 2612 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2613 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
b6016b76 2614
7947b20e
MC		 2615 /* Zero out the context. */
2616 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
62a8313c 2617 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
7947b20e 2618 }
b6016b76
MC		 2619 }
2620}
2621
2622static int
2623bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2624{
2625 u16 *good_mbuf;
2626 u32 good_mbuf_cnt;
2627 u32 val;
2628
2629 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
e404decb 2630 if (good_mbuf == NULL)
b6016b76 2631 return -ENOMEM;
b6016b76 2632
e503e066 2633 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
b6016b76
MC		 2634 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2635
2636 good_mbuf_cnt = 0;
2637
2638 /* Allocate a bunch of mbufs and save the good ones in an array. */
2726d6e1 2639 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76 2640 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2726d6e1
MC		 2641 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2642 BNX2_RBUF_COMMAND_ALLOC_REQ);
b6016b76 2643
2726d6e1 2644 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
b6016b76
MC		 2645
2646 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2647
2648 /* The addresses with Bit 9 set are bad memory blocks. */
2649 if (!(val & (1 << 9))) {
2650 good_mbuf[good_mbuf_cnt] = (u16) val;
2651 good_mbuf_cnt++;
2652 }
2653
2726d6e1 2654 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
b6016b76
MC		 2655 }
2656
2657 /* Free the good ones back to the mbuf pool thus discarding
2658 * all the bad ones. */
2659 while (good_mbuf_cnt) {
2660 good_mbuf_cnt--;
2661
2662 val = good_mbuf[good_mbuf_cnt];
2663 val = (val << 9) | val | 1;
2664
2726d6e1 2665 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
b6016b76
MC		 2666 }
2667 kfree(good_mbuf);
2668 return 0;
2669}
2670
2671static void
5fcaed01 2672bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
b6016b76
MC		 2673{
2674 u32 val;
b6016b76
MC		 2675
2676 val = (mac_addr[0] << 8) | mac_addr[1];
2677
e503e066 2678 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
b6016b76 2679
6aa20a22 2680 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
b6016b76
MC		 2681 (mac_addr[4] << 8) | mac_addr[5];
2682
e503e066 2683 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
b6016b76
MC		 2684}
2685
47bf4246 2686static inline int
a2df00aa 2687bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
47bf4246
MC		 2688{
2689 dma_addr_t mapping;
2bc4078e
MC		 2690 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2691 struct bnx2_rx_bd *rxbd =
2692 &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
a2df00aa 2693 struct page *page = alloc_page(gfp);
47bf4246
MC		 2694
2695 if (!page)
2696 return -ENOMEM;
36227e88 2697 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
47bf4246 2698 PCI_DMA_FROMDEVICE);
36227e88 2699 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 2700 __free_page(page);
2701 return -EIO;
2702 }
2703
47bf4246 2704 rx_pg->page = page;
1a4ccc2d 2705 dma_unmap_addr_set(rx_pg, mapping, mapping);
47bf4246
MC		 2706 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2707 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2708 return 0;
2709}
2710
2711static void
bb4f98ab 2712bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
47bf4246 2713{
2bc4078e 2714 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
47bf4246
MC		 2715 struct page *page = rx_pg->page;
2716
2717 if (!page)
2718 return;
2719
36227e88
SG		 2720 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2721 PAGE_SIZE, PCI_DMA_FROMDEVICE);
47bf4246
MC		 2722
2723 __free_page(page);
2724 rx_pg->page = NULL;
2725}
2726
b6016b76 2727static inline int
dd2bc8e9 2728bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
b6016b76 2729{
dd2bc8e9 2730 u8 *data;
2bc4078e 2731 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index];
b6016b76 2732 dma_addr_t mapping;
2bc4078e
MC		 2733 struct bnx2_rx_bd *rxbd =
2734 &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
b6016b76 2735
dd2bc8e9
ED		 2736 data = kmalloc(bp->rx_buf_size, gfp);
2737 if (!data)
b6016b76 2738 return -ENOMEM;
b6016b76 2739
dd2bc8e9
ED		 2740 mapping = dma_map_single(&bp->pdev->dev,
2741 get_l2_fhdr(data),
2742 bp->rx_buf_use_size,
36227e88
SG		 2743 PCI_DMA_FROMDEVICE);
2744 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
dd2bc8e9 2745 kfree(data);
3d16af86
BL		 2746 return -EIO;
2747 }
b6016b76 2748
dd2bc8e9 2749 rx_buf->data = data;
1a4ccc2d 2750 dma_unmap_addr_set(rx_buf, mapping, mapping);
b6016b76
MC		 2751
2752 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2753 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2754
bb4f98ab 2755 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76
MC		 2756
2757 return 0;
2758}
2759
da3e4fbe 2760static int
35efa7c1 2761bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
b6016b76 2762{
43e80b89 2763 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76 2764 u32 new_link_state, old_link_state;
da3e4fbe 2765 int is_set = 1;
b6016b76 2766
da3e4fbe
MC		 2767 new_link_state = sblk->status_attn_bits & event;
2768 old_link_state = sblk->status_attn_bits_ack & event;
b6016b76 2769 if (new_link_state != old_link_state) {
da3e4fbe 2770 if (new_link_state)
e503e066 2771 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
da3e4fbe 2772 else
e503e066 2773 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
da3e4fbe
MC		 2774 } else
2775 is_set = 0;
2776
2777 return is_set;
2778}
2779
2780static void
35efa7c1 2781bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
da3e4fbe 2782{
74ecc62d
MC		 2783 spin_lock(&bp->phy_lock);
2784
2785 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
b6016b76 2786 bnx2_set_link(bp);
35efa7c1 2787 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
0d8a6571
MC		 2788 bnx2_set_remote_link(bp);
2789
74ecc62d
MC		 2790 spin_unlock(&bp->phy_lock);
2791
b6016b76
MC		 2792}
2793
ead7270b 2794static inline u16
35efa7c1 2795bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
ead7270b
MC		 2796{
2797 u16 cons;
2798
43e80b89
MC		 2799 /* Tell compiler that status block fields can change. */
2800 barrier();
2801 cons = *bnapi->hw_tx_cons_ptr;
581daf7e 2802 barrier();
2bc4078e 2803 if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT))
ead7270b
MC		 2804 cons++;
2805 return cons;
2806}
2807
57851d84
MC		 2808static int
2809bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 2810{
35e9010b 2811 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
b6016b76 2812 u16 hw_cons, sw_cons, sw_ring_cons;
706bf240 2813 int tx_pkt = 0, index;
e9831909 2814 unsigned int tx_bytes = 0;
706bf240
BL		 2815 struct netdev_queue *txq;
2816
2817 index = (bnapi - bp->bnx2_napi);
2818 txq = netdev_get_tx_queue(bp->dev, index);
b6016b76 2819
35efa7c1 2820 hw_cons = bnx2_get_hw_tx_cons(bnapi);
35e9010b 2821 sw_cons = txr->tx_cons;
b6016b76
MC		 2822
2823 while (sw_cons != hw_cons) {
2bc4078e 2824 struct bnx2_sw_tx_bd *tx_buf;
b6016b76
MC		 2825 struct sk_buff *skb;
2826 int i, last;
2827
2bc4078e 2828 sw_ring_cons = BNX2_TX_RING_IDX(sw_cons);
b6016b76 2829
35e9010b 2830 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
b6016b76 2831 skb = tx_buf->skb;
1d39ed56 2832
d62fda08
ED		 2833 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2834 prefetch(&skb->end);
2835
b6016b76 2836 /* partial BD completions possible with TSO packets */
d62fda08 2837 if (tx_buf->is_gso) {
b6016b76
MC		 2838 u16 last_idx, last_ring_idx;
2839
d62fda08
ED		 2840 last_idx = sw_cons + tx_buf->nr_frags + 1;
2841 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2bc4078e 2842 if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) {
b6016b76
MC		 2843 last_idx++;
2844 }
2845 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2846 break;
2847 }
2848 }
1d39ed56 2849
36227e88 2850 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7 2851 skb_headlen(skb), PCI_DMA_TODEVICE);
b6016b76
MC		 2852
2853 tx_buf->skb = NULL;
d62fda08 2854 last = tx_buf->nr_frags;
b6016b76
MC		 2855
2856 for (i = 0; i < last; i++) {
2bc4078e 2857 struct bnx2_sw_tx_bd *tx_buf;
e95524a7 2858
2bc4078e
MC		 2859 sw_cons = BNX2_NEXT_TX_BD(sw_cons);
2860
2861 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)];
36227e88 2862 dma_unmap_page(&bp->pdev->dev,
2bc4078e 2863 dma_unmap_addr(tx_buf, mapping),
9e903e08 2864 skb_frag_size(&skb_shinfo(skb)->frags[i]),
e95524a7 2865 PCI_DMA_TODEVICE);
b6016b76
MC		 2866 }
2867
2bc4078e 2868 sw_cons = BNX2_NEXT_TX_BD(sw_cons);
b6016b76 2869
e9831909 2870 tx_bytes += skb->len;
745720e5 2871 dev_kfree_skb(skb);
57851d84
MC		 2872 tx_pkt++;
2873 if (tx_pkt == budget)
2874 break;
b6016b76 2875
d62fda08
ED		 2876 if (hw_cons == sw_cons)
2877 hw_cons = bnx2_get_hw_tx_cons(bnapi);
b6016b76
MC		 2878 }
2879
e9831909 2880 netdev_tx_completed_queue(txq, tx_pkt, tx_bytes);
35e9010b
MC		 2881 txr->hw_tx_cons = hw_cons;
2882 txr->tx_cons = sw_cons;
706bf240 2883
2f8af120 2884 /* Need to make the tx_cons update visible to bnx2_start_xmit()
706bf240 2885 * before checking for netif_tx_queue_stopped(). Without the
2f8af120
MC		 2886 * memory barrier, there is a small possibility that bnx2_start_xmit()
2887 * will miss it and cause the queue to be stopped forever.
2888 */
2889 smp_mb();
b6016b76 2890
706bf240 2891 if (unlikely(netif_tx_queue_stopped(txq)) &&
35e9010b 2892 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
706bf240
BL		 2893 __netif_tx_lock(txq, smp_processor_id());
2894 if ((netif_tx_queue_stopped(txq)) &&
35e9010b 2895 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
706bf240
BL		 2896 netif_tx_wake_queue(txq);
2897 __netif_tx_unlock(txq);
b6016b76 2898 }
706bf240 2899
57851d84 2900 return tx_pkt;
b6016b76
MC		 2901}
2902
1db82f2a 2903static void
bb4f98ab 2904bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
a1f60190 2905 struct sk_buff *skb, int count)
1db82f2a 2906{
2bc4078e
MC		 2907 struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg;
2908 struct bnx2_rx_bd *cons_bd, *prod_bd;
1db82f2a 2909 int i;
3d16af86 2910 u16 hw_prod, prod;
bb4f98ab 2911 u16 cons = rxr->rx_pg_cons;
1db82f2a 2912
3d16af86
BL		 2913 cons_rx_pg = &rxr->rx_pg_ring[cons];
2914
2915 /* The caller was unable to allocate a new page to replace the
2916 * last one in the frags array, so we need to recycle that page
2917 * and then free the skb.
2918 */
2919 if (skb) {
2920 struct page *page;
2921 struct skb_shared_info *shinfo;
2922
2923 shinfo = skb_shinfo(skb);
2924 shinfo->nr_frags--;
b7b6a688
IC		 2925 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2926 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
3d16af86
BL		 2927
2928 cons_rx_pg->page = page;
2929 dev_kfree_skb(skb);
2930 }
2931
2932 hw_prod = rxr->rx_pg_prod;
2933
1db82f2a 2934 for (i = 0; i < count; i++) {
2bc4078e 2935 prod = BNX2_RX_PG_RING_IDX(hw_prod);
1db82f2a 2936
bb4f98ab
MC		 2937 prod_rx_pg = &rxr->rx_pg_ring[prod];
2938 cons_rx_pg = &rxr->rx_pg_ring[cons];
2bc4078e
MC		 2939 cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)]
2940 [BNX2_RX_IDX(cons)];
2941 prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)]
2942 [BNX2_RX_IDX(prod)];
1db82f2a 2943
1db82f2a
MC		 2944 if (prod != cons) {
2945 prod_rx_pg->page = cons_rx_pg->page;
2946 cons_rx_pg->page = NULL;
1a4ccc2d
FT		 2947 dma_unmap_addr_set(prod_rx_pg, mapping,
2948 dma_unmap_addr(cons_rx_pg, mapping));
1db82f2a
MC		 2949
2950 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2951 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2952
2953 }
2bc4078e
MC		 2954 cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons));
2955 hw_prod = BNX2_NEXT_RX_BD(hw_prod);
1db82f2a 2956 }
bb4f98ab
MC		 2957 rxr->rx_pg_prod = hw_prod;
2958 rxr->rx_pg_cons = cons;
1db82f2a
MC		 2959}
2960
b6016b76 2961static inline void
dd2bc8e9
ED		 2962bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2963 u8 *data, u16 cons, u16 prod)
b6016b76 2964{
2bc4078e
MC		 2965 struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf;
2966 struct bnx2_rx_bd *cons_bd, *prod_bd;
236b6394 2967
bb4f98ab
MC		 2968 cons_rx_buf = &rxr->rx_buf_ring[cons];
2969 prod_rx_buf = &rxr->rx_buf_ring[prod];
b6016b76 2970
36227e88 2971 dma_sync_single_for_device(&bp->pdev->dev,
1a4ccc2d 2972 dma_unmap_addr(cons_rx_buf, mapping),
601d3d18 2973 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
b6016b76 2974
bb4f98ab 2975 rxr->rx_prod_bseq += bp->rx_buf_use_size;
b6016b76 2976
dd2bc8e9 2977 prod_rx_buf->data = data;
b6016b76 2978
236b6394
MC		 2979 if (cons == prod)
2980 return;
b6016b76 2981
1a4ccc2d
FT		 2982 dma_unmap_addr_set(prod_rx_buf, mapping,
2983 dma_unmap_addr(cons_rx_buf, mapping));
236b6394 2984
2bc4078e
MC		 2985 cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)];
2986 prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)];
236b6394
MC		 2987 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2988 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
b6016b76
MC		 2989}
2990
dd2bc8e9
ED		 2991static struct sk_buff *
2992bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
a1f60190
MC		 2993 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2994 u32 ring_idx)
85833c62
MC		 2995{
2996 int err;
2997 u16 prod = ring_idx & 0xffff;
dd2bc8e9 2998 struct sk_buff *skb;
85833c62 2999
dd2bc8e9 3000 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
85833c62 3001 if (unlikely(err)) {
dd2bc8e9
ED		 3002 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
3003error:
1db82f2a
MC		 3004 if (hdr_len) {
3005 unsigned int raw_len = len + 4;
3006 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3007
bb4f98ab 3008 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
1db82f2a 3009 }
dd2bc8e9 3010 return NULL;
85833c62
MC		 3011 }
3012
36227e88 3013 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
85833c62 3014 PCI_DMA_FROMDEVICE);
d3836f21 3015 skb = build_skb(data, 0);
dd2bc8e9
ED		 3016 if (!skb) {
3017 kfree(data);
3018 goto error;
3019 }
3020 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET);
1db82f2a
MC		 3021 if (hdr_len == 0) {
3022 skb_put(skb, len);
dd2bc8e9 3023 return skb;
1db82f2a
MC		 3024 } else {
3025 unsigned int i, frag_len, frag_size, pages;
2bc4078e 3026 struct bnx2_sw_pg *rx_pg;
bb4f98ab
MC		 3027 u16 pg_cons = rxr->rx_pg_cons;
3028 u16 pg_prod = rxr->rx_pg_prod;
1db82f2a
MC		 3029
3030 frag_size = len + 4 - hdr_len;
3031 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3032 skb_put(skb, hdr_len);
3033
3034 for (i = 0; i < pages; i++) {
3d16af86
BL		 3035 dma_addr_t mapping_old;
3036
1db82f2a
MC		 3037 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3038 if (unlikely(frag_len <= 4)) {
3039 unsigned int tail = 4 - frag_len;
3040
bb4f98ab
MC		 3041 rxr->rx_pg_cons = pg_cons;
3042 rxr->rx_pg_prod = pg_prod;
3043 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
a1f60190 3044 pages - i);
1db82f2a
MC		 3045 skb->len -= tail;
3046 if (i == 0) {
3047 skb->tail -= tail;
3048 } else {
3049 skb_frag_t *frag =
3050 &skb_shinfo(skb)->frags[i - 1];
9e903e08 3051 skb_frag_size_sub(frag, tail);
1db82f2a 3052 skb->data_len -= tail;
1db82f2a 3053 }
dd2bc8e9 3054 return skb;
1db82f2a 3055 }
bb4f98ab 3056 rx_pg = &rxr->rx_pg_ring[pg_cons];
1db82f2a 3057
3d16af86
BL		 3058 /* Don't unmap yet. If we're unable to allocate a new
3059 * page, we need to recycle the page and the DMA addr.
3060 */
1a4ccc2d 3061 mapping_old = dma_unmap_addr(rx_pg, mapping);
1db82f2a
MC		 3062 if (i == pages - 1)
3063 frag_len -= 4;
3064
3065 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3066 rx_pg->page = NULL;
3067
bb4f98ab 3068 err = bnx2_alloc_rx_page(bp, rxr,
2bc4078e 3069 BNX2_RX_PG_RING_IDX(pg_prod),
a2df00aa 3070 GFP_ATOMIC);
1db82f2a 3071 if (unlikely(err)) {
bb4f98ab
MC		 3072 rxr->rx_pg_cons = pg_cons;
3073 rxr->rx_pg_prod = pg_prod;
3074 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
a1f60190 3075 pages - i);
dd2bc8e9 3076 return NULL;
1db82f2a
MC		 3077 }
3078
36227e88 3079 dma_unmap_page(&bp->pdev->dev, mapping_old,
3d16af86
BL		 3080 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3081
1db82f2a
MC		 3082 frag_size -= frag_len;
3083 skb->data_len += frag_len;
a1f4e8bc 3084 skb->truesize += PAGE_SIZE;
1db82f2a
MC		 3085 skb->len += frag_len;
3086
2bc4078e
MC		 3087 pg_prod = BNX2_NEXT_RX_BD(pg_prod);
3088 pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons));
1db82f2a 3089 }
bb4f98ab
MC		 3090 rxr->rx_pg_prod = pg_prod;
3091 rxr->rx_pg_cons = pg_cons;
1db82f2a 3092 }
dd2bc8e9 3093 return skb;
85833c62
MC		 3094}
3095
c09c2627 3096static inline u16
35efa7c1 3097bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
c09c2627 3098{
bb4f98ab
MC		 3099 u16 cons;
3100
43e80b89
MC		 3101 /* Tell compiler that status block fields can change. */
3102 barrier();
3103 cons = *bnapi->hw_rx_cons_ptr;
581daf7e 3104 barrier();
2bc4078e 3105 if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT))
c09c2627
MC		 3106 cons++;
3107 return cons;
3108}
3109
b6016b76 3110static int
35efa7c1 3111bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
b6016b76 3112{
bb4f98ab 3113 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76
MC		 3114 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3115 struct l2_fhdr *rx_hdr;
1db82f2a 3116 int rx_pkt = 0, pg_ring_used = 0;
b6016b76 3117
35efa7c1 3118 hw_cons = bnx2_get_hw_rx_cons(bnapi);
bb4f98ab
MC		 3119 sw_cons = rxr->rx_cons;
3120 sw_prod = rxr->rx_prod;
b6016b76
MC		 3121
3122 /* Memory barrier necessary as speculative reads of the rx
3123 * buffer can be ahead of the index in the status block
3124 */
3125 rmb();
3126 while (sw_cons != hw_cons) {
1db82f2a 3127 unsigned int len, hdr_len;
ade2bfe7 3128 u32 status;
2bc4078e 3129 struct bnx2_sw_bd *rx_buf, *next_rx_buf;
b6016b76 3130 struct sk_buff *skb;
236b6394 3131 dma_addr_t dma_addr;
dd2bc8e9 3132 u8 *data;
2bc4078e 3133 u16 next_ring_idx;
b6016b76 3134
2bc4078e
MC		 3135 sw_ring_cons = BNX2_RX_RING_IDX(sw_cons);
3136 sw_ring_prod = BNX2_RX_RING_IDX(sw_prod);
b6016b76 3137
bb4f98ab 3138 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
dd2bc8e9
ED		 3139 data = rx_buf->data;
3140 rx_buf->data = NULL;
aabef8b2 3141
dd2bc8e9
ED		 3142 rx_hdr = get_l2_fhdr(data);
3143 prefetch(rx_hdr);
236b6394 3144
1a4ccc2d 3145 dma_addr = dma_unmap_addr(rx_buf, mapping);
236b6394 3146
36227e88 3147 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
601d3d18
BL		 3148 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3149 PCI_DMA_FROMDEVICE);
b6016b76 3150
2bc4078e
MC		 3151 next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons));
3152 next_rx_buf = &rxr->rx_buf_ring[next_ring_idx];
dd2bc8e9
ED		 3153 prefetch(get_l2_fhdr(next_rx_buf->data));
3154
1db82f2a 3155 len = rx_hdr->l2_fhdr_pkt_len;
990ec380 3156 status = rx_hdr->l2_fhdr_status;
b6016b76 3157
1db82f2a
MC		 3158 hdr_len = 0;
3159 if (status & L2_FHDR_STATUS_SPLIT) {
3160 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3161 pg_ring_used = 1;
3162 } else if (len > bp->rx_jumbo_thresh) {
3163 hdr_len = bp->rx_jumbo_thresh;
3164 pg_ring_used = 1;
3165 }
3166
990ec380
MC		 3167 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3168 L2_FHDR_ERRORS_PHY_DECODE |
3169 L2_FHDR_ERRORS_ALIGNMENT |
3170 L2_FHDR_ERRORS_TOO_SHORT |
3171 L2_FHDR_ERRORS_GIANT_FRAME))) {
3172
dd2bc8e9 3173 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
990ec380
MC		 3174 sw_ring_prod);
3175 if (pg_ring_used) {
3176 int pages;
3177
3178 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3179
3180 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3181 }
3182 goto next_rx;
3183 }
3184
1db82f2a 3185 len -= 4;
b6016b76 3186
5d5d0015 3187 if (len <= bp->rx_copy_thresh) {
dd2bc8e9
ED		 3188 skb = netdev_alloc_skb(bp->dev, len + 6);
3189 if (skb == NULL) {
3190 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
85833c62
MC		 3191 sw_ring_prod);
3192 goto next_rx;
3193 }
b6016b76
MC		 3194
3195 /* aligned copy */
dd2bc8e9
ED		 3196 memcpy(skb->data,
3197 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6,
3198 len + 6);
3199 skb_reserve(skb, 6);
3200 skb_put(skb, len);
b6016b76 3201
dd2bc8e9 3202 bnx2_reuse_rx_data(bp, rxr, data,
b6016b76
MC		 3203 sw_ring_cons, sw_ring_prod);
3204
dd2bc8e9
ED		 3205 } else {
3206 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
3207 (sw_ring_cons << 16) | sw_ring_prod);
3208 if (!skb)
3209 goto next_rx;
3210 }
f22828e8 3211 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
7d0fd211 3212 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
86a9bad3 3213 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag);
f22828e8 3214
b6016b76
MC		 3215 skb->protocol = eth_type_trans(skb, bp->dev);
3216
3217 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
d1e100ba 3218 (ntohs(skb->protocol) != 0x8100)) {
b6016b76 3219
745720e5 3220 dev_kfree_skb(skb);
b6016b76
MC		 3221 goto next_rx;
3222
3223 }
3224
bc8acf2c 3225 skb_checksum_none_assert(skb);
8d7dfc2b 3226 if ((bp->dev->features & NETIF_F_RXCSUM) &&
b6016b76
MC		 3227 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3228 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3229
ade2bfe7
MC		 3230 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3231 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
b6016b76
MC		 3232 skb->ip_summed = CHECKSUM_UNNECESSARY;
3233 }
fdc8541d
MC		 3234 if ((bp->dev->features & NETIF_F_RXHASH) &&
3235 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3236 L2_FHDR_STATUS_USE_RXHASH))
cf1bfd6a
TH		 3237 skb_set_hash(skb, rx_hdr->l2_fhdr_hash,
3238 PKT_HASH_TYPE_L3);
b6016b76 3239
0c8dfc83 3240 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
7d0fd211 3241 napi_gro_receive(&bnapi->napi, skb);
b6016b76
MC		 3242 rx_pkt++;
3243
3244next_rx:
2bc4078e
MC		 3245 sw_cons = BNX2_NEXT_RX_BD(sw_cons);
3246 sw_prod = BNX2_NEXT_RX_BD(sw_prod);
b6016b76
MC		 3247
3248 if ((rx_pkt == budget))
3249 break;
f4e418f7
MC		 3250
3251 /* Refresh hw_cons to see if there is new work */
3252 if (sw_cons == hw_cons) {
35efa7c1 3253 hw_cons = bnx2_get_hw_rx_cons(bnapi);
f4e418f7
MC		 3254 rmb();
3255 }
b6016b76 3256 }
bb4f98ab
MC		 3257 rxr->rx_cons = sw_cons;
3258 rxr->rx_prod = sw_prod;
b6016b76 3259
1db82f2a 3260 if (pg_ring_used)
e503e066 3261 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
1db82f2a 3262
e503e066 3263 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);
b6016b76 3264
e503e066 3265 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 3266
3267 mmiowb();
3268
3269 return rx_pkt;
3270
3271}
3272
3273/* MSI ISR - The only difference between this and the INTx ISR
3274 * is that the MSI interrupt is always serviced.
3275 */
3276static irqreturn_t
7d12e780 3277bnx2_msi(int irq, void *dev_instance)
b6016b76 3278{
f0ea2e63
MC		 3279 struct bnx2_napi *bnapi = dev_instance;
3280 struct bnx2 *bp = bnapi->bp;
b6016b76 3281
43e80b89 3282 prefetch(bnapi->status_blk.msi);
e503e066 3283 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
b6016b76
MC		 3284 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3285 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3286
3287 /* Return here if interrupt is disabled. */
73eef4cd
MC		 3288 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3289 return IRQ_HANDLED;
b6016b76 3290
288379f0 3291 napi_schedule(&bnapi->napi);
b6016b76 3292
73eef4cd 3293 return IRQ_HANDLED;
b6016b76
MC		 3294}
3295
8e6a72c4
MC		 3296static irqreturn_t
3297bnx2_msi_1shot(int irq, void *dev_instance)
3298{
f0ea2e63
MC		 3299 struct bnx2_napi *bnapi = dev_instance;
3300 struct bnx2 *bp = bnapi->bp;
8e6a72c4 3301
43e80b89 3302 prefetch(bnapi->status_blk.msi);
8e6a72c4
MC		 3303
3304 /* Return here if interrupt is disabled. */
3305 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3306 return IRQ_HANDLED;
3307
288379f0 3308 napi_schedule(&bnapi->napi);
8e6a72c4
MC		 3309
3310 return IRQ_HANDLED;
3311}
3312
b6016b76 3313static irqreturn_t
7d12e780 3314bnx2_interrupt(int irq, void *dev_instance)
b6016b76 3315{
f0ea2e63
MC		 3316 struct bnx2_napi *bnapi = dev_instance;
3317 struct bnx2 *bp = bnapi->bp;
43e80b89 3318 struct status_block *sblk = bnapi->status_blk.msi;
b6016b76
MC		 3319
3320 /* When using INTx, it is possible for the interrupt to arrive
3321 * at the CPU before the status block posted prior to the
3322 * interrupt. Reading a register will flush the status block.
3323 * When using MSI, the MSI message will always complete after
3324 * the status block write.
3325 */
35efa7c1 3326 if ((sblk->status_idx == bnapi->last_status_idx) &&
e503e066 3327 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
b6016b76 3328 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
73eef4cd 3329 return IRQ_NONE;
b6016b76 3330
e503e066 3331 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
b6016b76
MC		 3332 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3333 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3334
b8a7ce7b
MC		 3335 /* Read back to deassert IRQ immediately to avoid too many
3336 * spurious interrupts.
3337 */
e503e066 3338 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
b8a7ce7b 3339
b6016b76 3340 /* Return here if interrupt is shared and is disabled. */
73eef4cd
MC		 3341 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3342 return IRQ_HANDLED;
b6016b76 3343
288379f0 3344 if (napi_schedule_prep(&bnapi->napi)) {
35efa7c1 3345 bnapi->last_status_idx = sblk->status_idx;
288379f0 3346 __napi_schedule(&bnapi->napi);
b8a7ce7b 3347 }
b6016b76 3348
73eef4cd 3349 return IRQ_HANDLED;
b6016b76
MC		 3350}
3351
f4e418f7 3352static inline int
43e80b89 3353bnx2_has_fast_work(struct bnx2_napi *bnapi)
f4e418f7 3354{
35e9010b 3355 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 3356 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
f4e418f7 3357
bb4f98ab 3358 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
35e9010b 3359 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
f4e418f7 3360 return 1;
43e80b89
MC		 3361 return 0;
3362}
3363
3364#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3365 STATUS_ATTN_BITS_TIMER_ABORT)
3366
3367static inline int
3368bnx2_has_work(struct bnx2_napi *bnapi)
3369{
3370 struct status_block *sblk = bnapi->status_blk.msi;
3371
3372 if (bnx2_has_fast_work(bnapi))
3373 return 1;
f4e418f7 3374
4edd473f
MC		 3375#ifdef BCM_CNIC
3376 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3377 return 1;
3378#endif
3379
da3e4fbe
MC		 3380 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3381 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
f4e418f7
MC		 3382 return 1;
3383
3384 return 0;
3385}
3386
efba0180
MC		 3387static void
3388bnx2_chk_missed_msi(struct bnx2 *bp)
3389{
3390 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3391 u32 msi_ctrl;
3392
3393 if (bnx2_has_work(bnapi)) {
e503e066 3394 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
efba0180
MC		 3395 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3396 return;
3397
3398 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
e503e066
MC		 3399 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3400 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3401 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
efba0180
MC		 3402 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3403 }
3404 }
3405
3406 bp->idle_chk_status_idx = bnapi->last_status_idx;
3407}
3408
4edd473f
MC		 3409#ifdef BCM_CNIC
3410static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3411{
3412 struct cnic_ops *c_ops;
3413
3414 if (!bnapi->cnic_present)
3415 return;
3416
3417 rcu_read_lock();
3418 c_ops = rcu_dereference(bp->cnic_ops);
3419 if (c_ops)
3420 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3421 bnapi->status_blk.msi);
3422 rcu_read_unlock();
3423}
3424#endif
3425
43e80b89 3426static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
b6016b76 3427{
43e80b89 3428 struct status_block *sblk = bnapi->status_blk.msi;
da3e4fbe
MC		 3429 u32 status_attn_bits = sblk->status_attn_bits;
3430 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
b6016b76 3431
da3e4fbe
MC		 3432 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3433 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
b6016b76 3434
35efa7c1 3435 bnx2_phy_int(bp, bnapi);
bf5295bb
MC		 3436
3437 /* This is needed to take care of transient status
3438 * during link changes.
3439 */
e503e066
MC		 3440 BNX2_WR(bp, BNX2_HC_COMMAND,
3441 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3442 BNX2_RD(bp, BNX2_HC_COMMAND);
b6016b76 3443 }
43e80b89
MC		 3444}
3445
3446static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3447 int work_done, int budget)
3448{
3449 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3450 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
b6016b76 3451
35e9010b 3452 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
57851d84 3453 bnx2_tx_int(bp, bnapi, 0);
b6016b76 3454
bb4f98ab 3455 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
35efa7c1 3456 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
6aa20a22 3457
6f535763
DM		 3458 return work_done;
3459}
3460
f0ea2e63
MC		 3461static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3462{
3463 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3464 struct bnx2 *bp = bnapi->bp;
3465 int work_done = 0;
3466 struct status_block_msix *sblk = bnapi->status_blk.msix;
3467
3468 while (1) {
3469 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3470 if (unlikely(work_done >= budget))
3471 break;
3472
3473 bnapi->last_status_idx = sblk->status_idx;
3474 /* status idx must be read before checking for more work. */
3475 rmb();
3476 if (likely(!bnx2_has_fast_work(bnapi))) {
3477
288379f0 3478 napi_complete(napi);
e503e066
MC		 3479 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3480 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3481 bnapi->last_status_idx);
f0ea2e63
MC		 3482 break;
3483 }
3484 }
3485 return work_done;
3486}
3487
6f535763
DM		 3488static int bnx2_poll(struct napi_struct *napi, int budget)
3489{
35efa7c1
MC		 3490 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3491 struct bnx2 *bp = bnapi->bp;
6f535763 3492 int work_done = 0;
43e80b89 3493 struct status_block *sblk = bnapi->status_blk.msi;
6f535763
DM		 3494
3495 while (1) {
43e80b89
MC		 3496 bnx2_poll_link(bp, bnapi);
3497
35efa7c1 3498 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
f4e418f7 3499
4edd473f
MC		 3500#ifdef BCM_CNIC
3501 bnx2_poll_cnic(bp, bnapi);
3502#endif
3503
35efa7c1 3504 /* bnapi->last_status_idx is used below to tell the hw how
6dee6421
MC		 3505 * much work has been processed, so we must read it before
3506 * checking for more work.
3507 */
35efa7c1 3508 bnapi->last_status_idx = sblk->status_idx;
efba0180
MC		 3509
3510 if (unlikely(work_done >= budget))
3511 break;
3512
6dee6421 3513 rmb();
35efa7c1 3514 if (likely(!bnx2_has_work(bnapi))) {
288379f0 3515 napi_complete(napi);
f86e82fb 3516 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
e503e066
MC		 3517 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3518 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3519 bnapi->last_status_idx);
6dee6421 3520 break;
6f535763 3521 }
e503e066
MC		 3522 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3523 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3524 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3525 bnapi->last_status_idx);
3526
3527 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3528 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3529 bnapi->last_status_idx);
6f535763
DM		 3530 break;
3531 }
b6016b76
MC		 3532 }
3533
bea3348e 3534 return work_done;
b6016b76
MC		 3535}
3536
932ff279 3537/* Called with rtnl_lock from vlan functions and also netif_tx_lock
b6016b76
MC		 3538 * from set_multicast.
3539 */
3540static void
3541bnx2_set_rx_mode(struct net_device *dev)
3542{
972ec0d4 3543 struct bnx2 *bp = netdev_priv(dev);
b6016b76 3544 u32 rx_mode, sort_mode;
ccffad25 3545 struct netdev_hw_addr *ha;
b6016b76 3546 int i;
b6016b76 3547
9f52b564
MC		 3548 if (!netif_running(dev))
3549 return;
3550
c770a65c 3551 spin_lock_bh(&bp->phy_lock);
b6016b76
MC		 3552
3553 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3554 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3555 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
f646968f 3556 if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
7d0fd211 3557 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
b6016b76 3558 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
b6016b76
MC		 3559 if (dev->flags & IFF_PROMISC) {
3560 /* Promiscuous mode. */
3561 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
7510873d
MC		 3562 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3563 BNX2_RPM_SORT_USER0_PROM_VLAN;
b6016b76
MC		 3564 }
3565 else if (dev->flags & IFF_ALLMULTI) {
3566 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
e503e066
MC		 3567 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3568 0xffffffff);
b6016b76
MC		 3569 }
3570 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3571 }
3572 else {
3573 /* Accept one or more multicast(s). */
b6016b76
MC		 3574 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3575 u32 regidx;
3576 u32 bit;
3577 u32 crc;
3578
3579 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3580
22bedad3
JP		 3581 netdev_for_each_mc_addr(ha, dev) {
3582 crc = ether_crc_le(ETH_ALEN, ha->addr);
b6016b76
MC		 3583 bit = crc & 0xff;
3584 regidx = (bit & 0xe0) >> 5;
3585 bit &= 0x1f;
3586 mc_filter[regidx] |= (1 << bit);
3587 }
3588
3589 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
e503e066
MC		 3590 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3591 mc_filter[i]);
b6016b76
MC		 3592 }
3593
3594 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3595 }
3596
32e7bfc4 3597 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
5fcaed01
BL		 3598 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3599 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3600 BNX2_RPM_SORT_USER0_PROM_VLAN;
3601 } else if (!(dev->flags & IFF_PROMISC)) {
5fcaed01 3602 /* Add all entries into to the match filter list */
ccffad25 3603 i = 0;
32e7bfc4 3604 netdev_for_each_uc_addr(ha, dev) {
ccffad25 3605 bnx2_set_mac_addr(bp, ha->addr,
5fcaed01
BL		 3606 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3607 sort_mode |= (1 <<
3608 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
ccffad25 3609 i++;
5fcaed01
BL		 3610 }
3611
3612 }
3613
b6016b76
MC		 3614 if (rx_mode != bp->rx_mode) {
3615 bp->rx_mode = rx_mode;
e503e066 3616 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
b6016b76
MC		 3617 }
3618
e503e066
MC		 3619 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3620 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3621 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
b6016b76 3622
c770a65c 3623 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 3624}
3625
7880b72e 3626static int
57579f76
MC		 3627check_fw_section(const struct firmware *fw,
3628 const struct bnx2_fw_file_section *section,
3629 u32 alignment, bool non_empty)
3630{
3631 u32 offset = be32_to_cpu(section->offset);
3632 u32 len = be32_to_cpu(section->len);
3633
3634 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3635 return -EINVAL;
3636 if ((non_empty && len == 0) || len > fw->size - offset ||
3637 len & (alignment - 1))
3638 return -EINVAL;
3639 return 0;
3640}
3641
7880b72e 3642static int
57579f76
MC		 3643check_mips_fw_entry(const struct firmware *fw,
3644 const struct bnx2_mips_fw_file_entry *entry)
3645{
3646 if (check_fw_section(fw, &entry->text, 4, true) ||
3647 check_fw_section(fw, &entry->data, 4, false) ||
3648 check_fw_section(fw, &entry->rodata, 4, false))
3649 return -EINVAL;
3650 return 0;
3651}
3652
7880b72e 3653static void bnx2_release_firmware(struct bnx2 *bp)
3654{
3655 if (bp->rv2p_firmware) {
3656 release_firmware(bp->mips_firmware);
3657 release_firmware(bp->rv2p_firmware);
3658 bp->rv2p_firmware = NULL;
3659 }
3660}
3661
3662static int bnx2_request_uncached_firmware(struct bnx2 *bp)
b6016b76 3663{
57579f76 3664 const char *mips_fw_file, *rv2p_fw_file;
5ee1c326
BB		 3665 const struct bnx2_mips_fw_file *mips_fw;
3666 const struct bnx2_rv2p_fw_file *rv2p_fw;
57579f76
MC		 3667 int rc;
3668
4ce45e02 3669 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
57579f76 3670 mips_fw_file = FW_MIPS_FILE_09;
4ce45e02
MC		 3671 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||
3672 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))
078b0735
MC		 3673 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3674 else
3675 rv2p_fw_file = FW_RV2P_FILE_09;
57579f76
MC		 3676 } else {
3677 mips_fw_file = FW_MIPS_FILE_06;
3678 rv2p_fw_file = FW_RV2P_FILE_06;
3679 }
3680
3681 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3682 if (rc) {
3a9c6a49 3683 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
7880b72e 3684 goto out;
57579f76
MC		 3685 }
3686
3687 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3688 if (rc) {
3a9c6a49 3689 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
7880b72e 3690 goto err_release_mips_firmware;
57579f76 3691 }
5ee1c326
BB		 3692 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3693 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3694 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3695 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3696 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3697 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3698 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3699 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3a9c6a49 3700 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
7880b72e 3701 rc = -EINVAL;
3702 goto err_release_firmware;
57579f76 3703 }
5ee1c326
BB		 3704 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3705 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3706 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3a9c6a49 3707 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
7880b72e 3708 rc = -EINVAL;
3709 goto err_release_firmware;
57579f76 3710 }
7880b72e 3711out:
3712 return rc;
57579f76 3713
7880b72e 3714err_release_firmware:
3715 release_firmware(bp->rv2p_firmware);
3716 bp->rv2p_firmware = NULL;
3717err_release_mips_firmware:
3718 release_firmware(bp->mips_firmware);
3719 goto out;
3720}
3721
3722static int bnx2_request_firmware(struct bnx2 *bp)
3723{
3724 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
57579f76
MC		 3725}
3726
3727static u32
3728rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3729{
3730 switch (idx) {
3731 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3732 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3733 rv2p_code |= RV2P_BD_PAGE_SIZE;
3734 break;
3735 }
3736 return rv2p_code;
3737}
3738
3739static int
3740load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3741 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3742{
3743 u32 rv2p_code_len, file_offset;
3744 __be32 *rv2p_code;
b6016b76 3745 int i;
57579f76
MC		 3746 u32 val, cmd, addr;
3747
3748 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3749 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3750
3751 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
b6016b76 3752
57579f76
MC		 3753 if (rv2p_proc == RV2P_PROC1) {
3754 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3755 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3756 } else {
3757 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3758 addr = BNX2_RV2P_PROC2_ADDR_CMD;
d25be1d3 3759 }
b6016b76
MC		 3760
3761 for (i = 0; i < rv2p_code_len; i += 8) {
e503e066 3762 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
b6016b76 3763 rv2p_code++;
e503e066 3764 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
b6016b76
MC		 3765 rv2p_code++;
3766
57579f76 3767 val = (i / 8) | cmd;
e503e066 3768 BNX2_WR(bp, addr, val);
57579f76
MC		 3769 }
3770
3771 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3772 for (i = 0; i < 8; i++) {
3773 u32 loc, code;
3774
3775 loc = be32_to_cpu(fw_entry->fixup[i]);
3776 if (loc && ((loc * 4) < rv2p_code_len)) {
3777 code = be32_to_cpu(*(rv2p_code + loc - 1));
e503e066 3778 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
57579f76
MC		 3779 code = be32_to_cpu(*(rv2p_code + loc));
3780 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
e503e066 3781 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
57579f76
MC		 3782
3783 val = (loc / 2) | cmd;
e503e066 3784 BNX2_WR(bp, addr, val);
b6016b76
MC		 3785 }
3786 }
3787
3788 /* Reset the processor, un-stall is done later. */
3789 if (rv2p_proc == RV2P_PROC1) {
e503e066 3790 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
b6016b76
MC		 3791 }
3792 else {
e503e066 3793 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
b6016b76 3794 }
57579f76
MC		 3795
3796 return 0;
b6016b76
MC		 3797}
3798
af3ee519 3799static int
57579f76
MC		 3800load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3801 const struct bnx2_mips_fw_file_entry *fw_entry)
b6016b76 3802{
57579f76
MC		 3803 u32 addr, len, file_offset;
3804 __be32 *data;
b6016b76
MC		 3805 u32 offset;
3806 u32 val;
3807
3808 /* Halt the CPU. */
2726d6e1 3809 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3810 val |= cpu_reg->mode_value_halt;
2726d6e1
MC		 3811 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3812 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
b6016b76
MC		 3813
3814 /* Load the Text area. */
57579f76
MC		 3815 addr = be32_to_cpu(fw_entry->text.addr);
3816 len = be32_to_cpu(fw_entry->text.len);
3817 file_offset = be32_to_cpu(fw_entry->text.offset);
3818 data = (__be32 *)(bp->mips_firmware->data + file_offset);
ea1f8d5c 3819
57579f76
MC		 3820 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3821 if (len) {
b6016b76
MC		 3822 int j;
3823
57579f76
MC		 3824 for (j = 0; j < (len / 4); j++, offset += 4)
3825 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3826 }
3827
57579f76
MC		 3828 /* Load the Data area. */
3829 addr = be32_to_cpu(fw_entry->data.addr);
3830 len = be32_to_cpu(fw_entry->data.len);
3831 file_offset = be32_to_cpu(fw_entry->data.offset);
3832 data = (__be32 *)(bp->mips_firmware->data + file_offset);
b6016b76 3833
57579f76
MC		 3834 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3835 if (len) {
b6016b76
MC		 3836 int j;
3837
57579f76
MC		 3838 for (j = 0; j < (len / 4); j++, offset += 4)
3839 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3840 }
3841
3842 /* Load the Read-Only area. */
57579f76
MC		 3843 addr = be32_to_cpu(fw_entry->rodata.addr);
3844 len = be32_to_cpu(fw_entry->rodata.len);
3845 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3846 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3847
3848 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3849 if (len) {
b6016b76
MC		 3850 int j;
3851
57579f76
MC		 3852 for (j = 0; j < (len / 4); j++, offset += 4)
3853 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
b6016b76
MC		 3854 }
3855
3856 /* Clear the pre-fetch instruction. */
2726d6e1 3857 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
57579f76
MC		 3858
3859 val = be32_to_cpu(fw_entry->start_addr);
3860 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
b6016b76
MC		 3861
3862 /* Start the CPU. */
2726d6e1 3863 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
b6016b76 3864 val &= ~cpu_reg->mode_value_halt;
2726d6e1
MC		 3865 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3866 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
af3ee519
MC		 3867
3868 return 0;
b6016b76
MC		 3869}
3870
fba9fe91 3871static int
b6016b76
MC		 3872bnx2_init_cpus(struct bnx2 *bp)
3873{
57579f76
MC		 3874 const struct bnx2_mips_fw_file *mips_fw =
3875 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3876 const struct bnx2_rv2p_fw_file *rv2p_fw =
3877 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3878 int rc;
b6016b76
MC		 3879
3880 /* Initialize the RV2P processor. */
57579f76
MC		 3881 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3882 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
b6016b76
MC		 3883
3884 /* Initialize the RX Processor. */
57579f76 3885 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
fba9fe91
MC		 3886 if (rc)
3887 goto init_cpu_err;
3888
b6016b76 3889 /* Initialize the TX Processor. */
57579f76 3890 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
fba9fe91
MC		 3891 if (rc)
3892 goto init_cpu_err;
3893
b6016b76 3894 /* Initialize the TX Patch-up Processor. */
57579f76 3895 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
fba9fe91
MC		 3896 if (rc)
3897 goto init_cpu_err;
3898
b6016b76 3899 /* Initialize the Completion Processor. */
57579f76 3900 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
fba9fe91
MC		 3901 if (rc)
3902 goto init_cpu_err;
3903
d43584c8 3904 /* Initialize the Command Processor. */
57579f76 3905 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
b6016b76 3906
fba9fe91 3907init_cpu_err:
fba9fe91 3908 return rc;
b6016b76
MC		 3909}
3910
b6a23e91
MC		 3911static void
3912bnx2_setup_wol(struct bnx2 *bp)
3913{
3914 int i;
3915 u32 val, wol_msg;
3916
3917 if (bp->wol) {
3918 u32 advertising;
3919 u8 autoneg;
3920
3921 autoneg = bp->autoneg;
3922 advertising = bp->advertising;
3923
3924 if (bp->phy_port == PORT_TP) {
3925 bp->autoneg = AUTONEG_SPEED;
3926 bp->advertising = ADVERTISED_10baseT_Half |
3927 ADVERTISED_10baseT_Full |
3928 ADVERTISED_100baseT_Half |
3929 ADVERTISED_100baseT_Full |
3930 ADVERTISED_Autoneg;
3931 }
3932
3933 spin_lock_bh(&bp->phy_lock);
3934 bnx2_setup_phy(bp, bp->phy_port);
3935 spin_unlock_bh(&bp->phy_lock);
3936
3937 bp->autoneg = autoneg;
3938 bp->advertising = advertising;
3939
3940 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3941
3942 val = BNX2_RD(bp, BNX2_EMAC_MODE);
3943
3944 /* Enable port mode. */
3945 val &= ~BNX2_EMAC_MODE_PORT;
3946 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3947 BNX2_EMAC_MODE_ACPI_RCVD |
3948 BNX2_EMAC_MODE_MPKT;
3949 if (bp->phy_port == PORT_TP) {
3950 val |= BNX2_EMAC_MODE_PORT_MII;
3951 } else {
3952 val |= BNX2_EMAC_MODE_PORT_GMII;
3953 if (bp->line_speed == SPEED_2500)
3954 val |= BNX2_EMAC_MODE_25G_MODE;
3955 }
3956
3957 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3958
3959 /* receive all multicast */
3960 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3961 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3962 0xffffffff);
3963 }
3964 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
3965
3966 val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN;
3967 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3968 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
3969 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
3970
3971 /* Need to enable EMAC and RPM for WOL. */
3972 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3973 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3974 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3975 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3976
3977 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
3978 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3979 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
3980
3981 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3982 } else {
3983 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3984 }
3985
3986 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3987 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 1, 0);
3988
3989}
3990
b6016b76 3991static int
829ca9a3 3992bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
b6016b76 3993{
b6016b76 3994 switch (state) {
829ca9a3 3995 case PCI_D0: {
b6016b76
MC		 3996 u32 val;
3997
6d5e85c7
MC		 3998 pci_enable_wake(bp->pdev, PCI_D0, false);
3999 pci_set_power_state(bp->pdev, PCI_D0);
b6016b76 4000
e503e066 4001 val = BNX2_RD(bp, BNX2_EMAC_MODE);
b6016b76
MC		 4002 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
4003 val &= ~BNX2_EMAC_MODE_MPKT;
e503e066 4004 BNX2_WR(bp, BNX2_EMAC_MODE, val);
b6016b76 4005
e503e066 4006 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
b6016b76 4007 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
e503e066 4008 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
b6016b76
MC		 4009 break;
4010 }
829ca9a3 4011 case PCI_D3hot: {
b6a23e91 4012 bnx2_setup_wol(bp);
6d5e85c7 4013 pci_wake_from_d3(bp->pdev, bp->wol);
4ce45e02
MC		 4014 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4015 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {
b6016b76
MC		 4016
4017 if (bp->wol)
6d5e85c7
MC		 4018 pci_set_power_state(bp->pdev, PCI_D3hot);
4019 } else {
4020 pci_set_power_state(bp->pdev, PCI_D3hot);
b6016b76 4021 }
b6016b76
MC		 4022
4023 /* No more memory access after this point until
4024 * device is brought back to D0.
4025 */
b6016b76
MC		 4026 break;
4027 }
4028 default:
4029 return -EINVAL;
4030 }
4031 return 0;
4032}
4033
4034static int
4035bnx2_acquire_nvram_lock(struct bnx2 *bp)
4036{
4037 u32 val;
4038 int j;
4039
4040 /* Request access to the flash interface. */
e503e066 4041 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
b6016b76 4042 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
e503e066 4043 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
b6016b76
MC		 4044 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4045 break;
4046
4047 udelay(5);
4048 }
4049
4050 if (j >= NVRAM_TIMEOUT_COUNT)
4051 return -EBUSY;
4052
4053 return 0;
4054}
4055
4056static int
4057bnx2_release_nvram_lock(struct bnx2 *bp)
4058{
4059 int j;
4060 u32 val;
4061
4062 /* Relinquish nvram interface. */
e503e066 4063 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
b6016b76
MC		 4064
4065 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
e503e066 4066 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
b6016b76
MC		 4067 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4068 break;
4069
4070 udelay(5);
4071 }
4072
4073 if (j >= NVRAM_TIMEOUT_COUNT)
4074 return -EBUSY;
4075
4076 return 0;
4077}
4078
4079
4080static int
4081bnx2_enable_nvram_write(struct bnx2 *bp)
4082{
4083 u32 val;
4084
e503e066
MC		 4085 val = BNX2_RD(bp, BNX2_MISC_CFG);
4086 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
b6016b76 4087
e30372c9 4088 if (bp->flash_info->flags & BNX2_NV_WREN) {
b6016b76
MC		 4089 int j;
4090
e503e066
MC		 4091 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4092 BNX2_WR(bp, BNX2_NVM_COMMAND,
4093 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
b6016b76
MC		 4094
4095 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4096 udelay(5);
4097
e503e066 4098 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
b6016b76
MC		 4099 if (val & BNX2_NVM_COMMAND_DONE)
4100 break;
4101 }
4102
4103 if (j >= NVRAM_TIMEOUT_COUNT)
4104 return -EBUSY;
4105 }
4106 return 0;
4107}
4108
4109static void
4110bnx2_disable_nvram_write(struct bnx2 *bp)
4111{
4112 u32 val;
4113
e503e066
MC		 4114 val = BNX2_RD(bp, BNX2_MISC_CFG);
4115 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
b6016b76
MC		 4116}
4117
4118
4119static void
4120bnx2_enable_nvram_access(struct bnx2 *bp)
4121{
4122 u32 val;
4123
e503e066 4124 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
b6016b76 4125 /* Enable both bits, even on read. */
e503e066
MC		 4126 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4127 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
b6016b76
MC		 4128}
4129
4130static void
4131bnx2_disable_nvram_access(struct bnx2 *bp)
4132{
4133 u32 val;
4134
e503e066 4135 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
b6016b76 4136 /* Disable both bits, even after read. */
e503e066 4137 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
b6016b76
MC		 4138 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4139 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4140}
4141
4142static int
4143bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4144{
4145 u32 cmd;
4146 int j;
4147
e30372c9 4148 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
b6016b76
MC		 4149 /* Buffered flash, no erase needed */
4150 return 0;
4151
4152 /* Build an erase command */
4153 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4154 BNX2_NVM_COMMAND_DOIT;
4155
4156 /* Need to clear DONE bit separately. */
e503e066 4157 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
b6016b76
MC		 4158
4159 /* Address of the NVRAM to read from. */
e503e066 4160 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
b6016b76
MC		 4161
4162 /* Issue an erase command. */
e503e066 4163 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
b6016b76
MC		 4164
4165 /* Wait for completion. */
4166 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4167 u32 val;
4168
4169 udelay(5);
4170
e503e066 4171 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
b6016b76
MC		 4172 if (val & BNX2_NVM_COMMAND_DONE)
4173 break;
4174 }
4175
4176 if (j >= NVRAM_TIMEOUT_COUNT)
4177 return -EBUSY;
4178
4179 return 0;
4180}
4181
4182static int
4183bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4184{
4185 u32 cmd;
4186 int j;
4187
4188 /* Build the command word. */
4189 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4190
e30372c9
MC		 4191 /* Calculate an offset of a buffered flash, not needed for 5709. */
4192 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4193 offset = ((offset / bp->flash_info->page_size) <<
4194 bp->flash_info->page_bits) +
4195 (offset % bp->flash_info->page_size);
4196 }
4197
4198 /* Need to clear DONE bit separately. */
e503e066 4199 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
b6016b76
MC		 4200
4201 /* Address of the NVRAM to read from. */
e503e066 4202 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
b6016b76
MC		 4203
4204 /* Issue a read command. */
e503e066 4205 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
b6016b76
MC		 4206
4207 /* Wait for completion. */
4208 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4209 u32 val;
4210
4211 udelay(5);
4212
e503e066 4213 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
b6016b76 4214 if (val & BNX2_NVM_COMMAND_DONE) {
e503e066 4215 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
b491edd5 4216 memcpy(ret_val, &v, 4);
b6016b76
MC		 4217 break;
4218 }
4219 }
4220 if (j >= NVRAM_TIMEOUT_COUNT)
4221 return -EBUSY;
4222
4223 return 0;
4224}
4225
4226
4227static int
4228bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4229{
b491edd5
AV		 4230 u32 cmd;
4231 __be32 val32;
b6016b76
MC		 4232 int j;
4233
4234 /* Build the command word. */
4235 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4236
e30372c9
MC		 4237 /* Calculate an offset of a buffered flash, not needed for 5709. */
4238 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
b6016b76
MC		 4239 offset = ((offset / bp->flash_info->page_size) <<
4240 bp->flash_info->page_bits) +
4241 (offset % bp->flash_info->page_size);
4242 }
4243
4244 /* Need to clear DONE bit separately. */
e503e066 4245 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
b6016b76
MC		 4246
4247 memcpy(&val32, val, 4);
b6016b76
MC		 4248
4249 /* Write the data. */
e503e066 4250 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
b6016b76
MC		 4251
4252 /* Address of the NVRAM to write to. */
e503e066 4253 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
b6016b76
MC		 4254
4255 /* Issue the write command. */
e503e066 4256 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
b6016b76
MC		 4257
4258 /* Wait for completion. */
4259 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4260 udelay(5);
4261
e503e066 4262 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
b6016b76
MC		 4263 break;
4264 }
4265 if (j >= NVRAM_TIMEOUT_COUNT)
4266 return -EBUSY;
4267
4268 return 0;
4269}
4270
4271static int
4272bnx2_init_nvram(struct bnx2 *bp)
4273{
4274 u32 val;
e30372c9 4275 int j, entry_count, rc = 0;
0ced9d01 4276 const struct flash_spec *flash;
b6016b76 4277
4ce45e02 4278 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e30372c9
MC		 4279 bp->flash_info = &flash_5709;
4280 goto get_flash_size;
4281 }
4282
b6016b76 4283 /* Determine the selected interface. */
e503e066 4284 val = BNX2_RD(bp, BNX2_NVM_CFG1);
b6016b76 4285
ff8ac609 4286 entry_count = ARRAY_SIZE(flash_table);
b6016b76 4287
b6016b76
MC		 4288 if (val & 0x40000000) {
4289
4290 /* Flash interface has been reconfigured */
4291 for (j = 0, flash = &flash_table[0]; j < entry_count;
37137709
MC		 4292 j++, flash++) {
4293 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4294 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
b6016b76
MC		 4295 bp->flash_info = flash;
4296 break;
4297 }
4298 }
4299 }
4300 else {
37137709 4301 u32 mask;
b6016b76
MC		 4302 /* Not yet been reconfigured */
4303
37137709
MC		 4304 if (val & (1 << 23))
4305 mask = FLASH_BACKUP_STRAP_MASK;
4306 else
4307 mask = FLASH_STRAP_MASK;
4308
b6016b76
MC		 4309 for (j = 0, flash = &flash_table[0]; j < entry_count;
4310 j++, flash++) {
4311
37137709 4312 if ((val & mask) == (flash->strapping & mask)) {
b6016b76
MC		 4313 bp->flash_info = flash;
4314
4315 /* Request access to the flash interface. */
4316 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4317 return rc;
4318
4319 /* Enable access to flash interface */
4320 bnx2_enable_nvram_access(bp);
4321
4322 /* Reconfigure the flash interface */
e503e066
MC		 4323 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
4324 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
4325 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
4326 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
b6016b76
MC		 4327
4328 /* Disable access to flash interface */
4329 bnx2_disable_nvram_access(bp);
4330 bnx2_release_nvram_lock(bp);
4331
4332 break;
4333 }
4334 }
4335 } /* if (val & 0x40000000) */
4336
4337 if (j == entry_count) {
4338 bp->flash_info = NULL;
3a9c6a49 4339 pr_alert("Unknown flash/EEPROM type\n");
1122db71 4340 return -ENODEV;
b6016b76
MC		 4341 }
4342
e30372c9 4343get_flash_size:
2726d6e1 4344 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
1122db71
MC		 4345 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4346 if (val)
4347 bp->flash_size = val;
4348 else
4349 bp->flash_size = bp->flash_info->total_size;
4350
b6016b76
MC		 4351 return rc;
4352}
4353
4354static int
4355bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4356 int buf_size)
4357{
4358 int rc = 0;
4359 u32 cmd_flags, offset32, len32, extra;
4360
4361 if (buf_size == 0)
4362 return 0;
4363
4364 /* Request access to the flash interface. */
4365 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4366 return rc;
4367
4368 /* Enable access to flash interface */
4369 bnx2_enable_nvram_access(bp);
4370
4371 len32 = buf_size;
4372 offset32 = offset;
4373 extra = 0;
4374
4375 cmd_flags = 0;
4376
4377 if (offset32 & 3) {
4378 u8 buf[4];
4379 u32 pre_len;
4380
4381 offset32 &= ~3;
4382 pre_len = 4 - (offset & 3);
4383
4384 if (pre_len >= len32) {
4385 pre_len = len32;
4386 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4387 BNX2_NVM_COMMAND_LAST;
4388 }
4389 else {
4390 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4391 }
4392
4393 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4394
4395 if (rc)
4396 return rc;
4397
4398 memcpy(ret_buf, buf + (offset & 3), pre_len);
4399
4400 offset32 += 4;
4401 ret_buf += pre_len;
4402 len32 -= pre_len;
4403 }
4404 if (len32 & 3) {
4405 extra = 4 - (len32 & 3);
4406 len32 = (len32 + 4) & ~3;
4407 }
4408
4409 if (len32 == 4) {
4410 u8 buf[4];
4411
4412 if (cmd_flags)
4413 cmd_flags = BNX2_NVM_COMMAND_LAST;
4414 else
4415 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4416 BNX2_NVM_COMMAND_LAST;
4417
4418 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4419
4420 memcpy(ret_buf, buf, 4 - extra);
4421 }
4422 else if (len32 > 0) {
4423 u8 buf[4];
4424
4425 /* Read the first word. */
4426 if (cmd_flags)
4427 cmd_flags = 0;
4428 else
4429 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4430
4431 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4432
4433 /* Advance to the next dword. */
4434 offset32 += 4;
4435 ret_buf += 4;
4436 len32 -= 4;
4437
4438 while (len32 > 4 && rc == 0) {
4439 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4440
4441 /* Advance to the next dword. */
4442 offset32 += 4;
4443 ret_buf += 4;
4444 len32 -= 4;
4445 }
4446
4447 if (rc)
4448 return rc;
4449
4450 cmd_flags = BNX2_NVM_COMMAND_LAST;
4451 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4452
4453 memcpy(ret_buf, buf, 4 - extra);
4454 }
4455
4456 /* Disable access to flash interface */
4457 bnx2_disable_nvram_access(bp);
4458
4459 bnx2_release_nvram_lock(bp);
4460
4461 return rc;
4462}
4463
4464static int
4465bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4466 int buf_size)
4467{
4468 u32 written, offset32, len32;
e6be763f 4469 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
b6016b76
MC		 4470 int rc = 0;
4471 int align_start, align_end;
4472
4473 buf = data_buf;
4474 offset32 = offset;
4475 len32 = buf_size;
4476 align_start = align_end = 0;
4477
4478 if ((align_start = (offset32 & 3))) {
4479 offset32 &= ~3;
c873879c
MC		 4480 len32 += align_start;
4481 if (len32 < 4)
4482 len32 = 4;
b6016b76
MC		 4483 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4484 return rc;
4485 }
4486
4487 if (len32 & 3) {
c873879c
MC		 4488 align_end = 4 - (len32 & 3);
4489 len32 += align_end;
4490 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4491 return rc;
b6016b76
MC		 4492 }
4493
4494 if (align_start || align_end) {
e6be763f
MC		 4495 align_buf = kmalloc(len32, GFP_KERNEL);
4496 if (align_buf == NULL)
b6016b76
MC		 4497 return -ENOMEM;
4498 if (align_start) {
e6be763f 4499 memcpy(align_buf, start, 4);
b6016b76
MC		 4500 }
4501 if (align_end) {
e6be763f 4502 memcpy(align_buf + len32 - 4, end, 4);
b6016b76 4503 }
e6be763f
MC		 4504 memcpy(align_buf + align_start, data_buf, buf_size);
4505 buf = align_buf;
b6016b76
MC		 4506 }
4507
e30372c9 4508 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
ae181bc4
MC		 4509 flash_buffer = kmalloc(264, GFP_KERNEL);
4510 if (flash_buffer == NULL) {
4511 rc = -ENOMEM;
4512 goto nvram_write_end;
4513 }
4514 }
4515
b6016b76
MC		 4516 written = 0;
4517 while ((written < len32) && (rc == 0)) {
4518 u32 page_start, page_end, data_start, data_end;
4519 u32 addr, cmd_flags;
4520 int i;
b6016b76
MC		 4521
4522 /* Find the page_start addr */
4523 page_start = offset32 + written;
4524 page_start -= (page_start % bp->flash_info->page_size);
4525 /* Find the page_end addr */
4526 page_end = page_start + bp->flash_info->page_size;
4527 /* Find the data_start addr */
4528 data_start = (written == 0) ? offset32 : page_start;
4529 /* Find the data_end addr */
6aa20a22 4530 data_end = (page_end > offset32 + len32) ?
b6016b76
MC		 4531 (offset32 + len32) : page_end;
4532
4533 /* Request access to the flash interface. */
4534 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4535 goto nvram_write_end;
4536
4537 /* Enable access to flash interface */
4538 bnx2_enable_nvram_access(bp);
4539
4540 cmd_flags = BNX2_NVM_COMMAND_FIRST;
e30372c9 4541 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4542 int j;
4543
4544 /* Read the whole page into the buffer
4545 * (non-buffer flash only) */
4546 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4547 if (j == (bp->flash_info->page_size - 4)) {
4548 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4549 }
4550 rc = bnx2_nvram_read_dword(bp,
6aa20a22
JG		 4551 page_start + j,
4552 &flash_buffer[j],
b6016b76
MC		 4553 cmd_flags);
4554
4555 if (rc)
4556 goto nvram_write_end;
4557
4558 cmd_flags = 0;
4559 }
4560 }
4561
4562 /* Enable writes to flash interface (unlock write-protect) */
4563 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4564 goto nvram_write_end;
4565
b6016b76
MC		 4566 /* Loop to write back the buffer data from page_start to
4567 * data_start */
4568 i = 0;
e30372c9 4569 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
c873879c
MC		 4570 /* Erase the page */
4571 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4572 goto nvram_write_end;
4573
4574 /* Re-enable the write again for the actual write */
4575 bnx2_enable_nvram_write(bp);
4576
b6016b76
MC		 4577 for (addr = page_start; addr < data_start;
4578 addr += 4, i += 4) {
6aa20a22 4579
b6016b76
MC		 4580 rc = bnx2_nvram_write_dword(bp, addr,
4581 &flash_buffer[i], cmd_flags);
4582
4583 if (rc != 0)
4584 goto nvram_write_end;
4585
4586 cmd_flags = 0;
4587 }
4588 }
4589
4590 /* Loop to write the new data from data_start to data_end */
bae25761 4591 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
b6016b76 4592 if ((addr == page_end - 4) ||
e30372c9 4593 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
b6016b76
MC		 4594 (addr == data_end - 4))) {
4595
4596 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4597 }
4598 rc = bnx2_nvram_write_dword(bp, addr, buf,
4599 cmd_flags);
4600
4601 if (rc != 0)
4602 goto nvram_write_end;
4603
4604 cmd_flags = 0;
4605 buf += 4;
4606 }
4607
4608 /* Loop to write back the buffer data from data_end
4609 * to page_end */
e30372c9 4610 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
b6016b76
MC		 4611 for (addr = data_end; addr < page_end;
4612 addr += 4, i += 4) {
6aa20a22 4613
b6016b76
MC		 4614 if (addr == page_end-4) {
4615 cmd_flags = BNX2_NVM_COMMAND_LAST;
4616 }
4617 rc = bnx2_nvram_write_dword(bp, addr,
4618 &flash_buffer[i], cmd_flags);
4619
4620 if (rc != 0)
4621 goto nvram_write_end;
4622
4623 cmd_flags = 0;
4624 }
4625 }
4626
4627 /* Disable writes to flash interface (lock write-protect) */
4628 bnx2_disable_nvram_write(bp);
4629
4630 /* Disable access to flash interface */
4631 bnx2_disable_nvram_access(bp);
4632 bnx2_release_nvram_lock(bp);
4633
4634 /* Increment written */
4635 written += data_end - data_start;
4636 }
4637
4638nvram_write_end:
e6be763f
MC		 4639 kfree(flash_buffer);
4640 kfree(align_buf);
b6016b76
MC		 4641 return rc;
4642}
4643
0d8a6571 4644static void
7c62e83b 4645bnx2_init_fw_cap(struct bnx2 *bp)
0d8a6571 4646{
7c62e83b 4647 u32 val, sig = 0;
0d8a6571 4648
583c28e5 4649 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
7c62e83b
MC		 4650 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4651
4652 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4653 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
0d8a6571 4654
2726d6e1 4655 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
0d8a6571
MC		 4656 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4657 return;
4658
7c62e83b
MC		 4659 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4660 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4661 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4662 }
4663
4664 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4665 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4666 u32 link;
4667
583c28e5 4668 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
0d8a6571 4669
7c62e83b
MC		 4670 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4671 if (link & BNX2_LINK_STATUS_SERDES_LINK)
0d8a6571
MC		 4672 bp->phy_port = PORT_FIBRE;
4673 else
4674 bp->phy_port = PORT_TP;
489310a4 4675
7c62e83b
MC		 4676 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4677 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
0d8a6571 4678 }
7c62e83b
MC		 4679
4680 if (netif_running(bp->dev) && sig)
4681 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
0d8a6571
MC		 4682}
4683
b4b36042
MC		 4684static void
4685bnx2_setup_msix_tbl(struct bnx2 *bp)
4686{
e503e066 4687 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
b4b36042 4688
e503e066
MC		 4689 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4690 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
b4b36042
MC		 4691}
4692
b6016b76
MC		 4693static int
4694bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4695{
4696 u32 val;
4697 int i, rc = 0;
489310a4 4698 u8 old_port;
b6016b76
MC		 4699
4700 /* Wait for the current PCI transaction to complete before
4701 * issuing a reset. */
4ce45e02
MC		 4702 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
4703 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
e503e066
MC		 4704 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4705 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4706 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4707 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4708 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4709 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
a5dac108
EW		 4710 udelay(5);
4711 } else { /* 5709 */
e503e066 4712 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
a5dac108 4713 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
e503e066
MC		 4714 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4715 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
a5dac108
EW		 4716
4717 for (i = 0; i < 100; i++) {
4718 msleep(1);
e503e066 4719 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
a5dac108
EW		 4720 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4721 break;
4722 }
4723 }
b6016b76 4724
b090ae2b 4725 /* Wait for the firmware to tell us it is ok to issue a reset. */
a2f13890 4726 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
b090ae2b 4727
b6016b76
MC		 4728 /* Deposit a driver reset signature so the firmware knows that
4729 * this is a soft reset. */
2726d6e1
MC		 4730 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4731 BNX2_DRV_RESET_SIGNATURE_MAGIC);
b6016b76 4732
b6016b76
MC		 4733 /* Do a dummy read to force the chip to complete all current transaction
4734 * before we issue a reset. */
e503e066 4735 val = BNX2_RD(bp, BNX2_MISC_ID);
b6016b76 4736
4ce45e02 4737 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e503e066
MC		 4738 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4739 BNX2_RD(bp, BNX2_MISC_COMMAND);
234754d5 4740 udelay(5);
b6016b76 4741
234754d5
MC		 4742 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4743 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
b6016b76 4744
e503e066 4745 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
b6016b76 4746
234754d5
MC		 4747 } else {
4748 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4749 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4750 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4751
4752 /* Chip reset. */
e503e066 4753 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
234754d5 4754
594a9dfa
MC		 4755 /* Reading back any register after chip reset will hang the
4756 * bus on 5706 A0 and A1. The msleep below provides plenty
4757 * of margin for write posting.
4758 */
4ce45e02
MC		 4759 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4760 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))
8e545881 4761 msleep(20);
b6016b76 4762
234754d5
MC		 4763 /* Reset takes approximate 30 usec */
4764 for (i = 0; i < 10; i++) {
e503e066 4765 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
234754d5
MC		 4766 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4767 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4768 break;
4769 udelay(10);
4770 }
4771
4772 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4773 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3a9c6a49 4774 pr_err("Chip reset did not complete\n");
234754d5
MC		 4775 return -EBUSY;
4776 }
b6016b76
MC		 4777 }
4778
4779 /* Make sure byte swapping is properly configured. */
e503e066 4780 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
b6016b76 4781 if (val != 0x01020304) {
3a9c6a49 4782 pr_err("Chip not in correct endian mode\n");
b6016b76
MC		 4783 return -ENODEV;
4784 }
4785
b6016b76 4786 /* Wait for the firmware to finish its initialization. */
a2f13890 4787 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
b090ae2b
MC		 4788 if (rc)
4789 return rc;
b6016b76 4790
0d8a6571 4791 spin_lock_bh(&bp->phy_lock);
489310a4 4792 old_port = bp->phy_port;
7c62e83b 4793 bnx2_init_fw_cap(bp);
583c28e5
MC		 4794 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4795 old_port != bp->phy_port)
0d8a6571
MC		 4796 bnx2_set_default_remote_link(bp);
4797 spin_unlock_bh(&bp->phy_lock);
4798
4ce45e02 4799 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
b6016b76
MC		 4800 /* Adjust the voltage regular to two steps lower. The default
4801 * of this register is 0x0000000e. */
e503e066 4802 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
b6016b76
MC		 4803
4804 /* Remove bad rbuf memory from the free pool. */
4805 rc = bnx2_alloc_bad_rbuf(bp);
4806 }
4807
c441b8d2 4808 if (bp->flags & BNX2_FLAG_USING_MSIX) {
b4b36042 4809 bnx2_setup_msix_tbl(bp);
c441b8d2 4810 /* Prevent MSIX table reads and write from timing out */
e503e066 4811 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
c441b8d2
MC		 4812 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4813 }
b4b36042 4814
b6016b76
MC		 4815 return rc;
4816}
4817
4818static int
4819bnx2_init_chip(struct bnx2 *bp)
4820{
d8026d93 4821 u32 val, mtu;
b4b36042 4822 int rc, i;
b6016b76
MC		 4823
4824 /* Make sure the interrupt is not active. */
e503e066 4825 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
b6016b76
MC		 4826
4827 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4828 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4829#ifdef __BIG_ENDIAN
6aa20a22 4830 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
b6016b76 4831#endif
6aa20a22 4832 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
b6016b76
MC		 4833 DMA_READ_CHANS << 12 |
4834 DMA_WRITE_CHANS << 16;
4835
4836 val |= (0x2 << 20) | (1 << 11);
4837
f86e82fb 4838 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
b6016b76
MC		 4839 val |= (1 << 23);
4840
4ce45e02
MC		 4841 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&
4842 (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&
4843 !(bp->flags & BNX2_FLAG_PCIX))
b6016b76
MC		 4844 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4845
e503e066 4846 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
b6016b76 4847
4ce45e02 4848 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
e503e066 4849 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
b6016b76 4850 val |= BNX2_TDMA_CONFIG_ONE_DMA;
e503e066 4851 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
b6016b76
MC		 4852 }
4853
f86e82fb 4854 if (bp->flags & BNX2_FLAG_PCIX) {
b6016b76
MC		 4855 u16 val16;
4856
4857 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4858 &val16);
4859 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4860 val16 & ~PCI_X_CMD_ERO);
4861 }
4862
e503e066
MC		 4863 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4864 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4865 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4866 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
b6016b76
MC		 4867
4868 /* Initialize context mapping and zero out the quick contexts. The
4869 * context block must have already been enabled. */
4ce45e02 4870 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
641bdcd5
MC		 4871 rc = bnx2_init_5709_context(bp);
4872 if (rc)
4873 return rc;
4874 } else
59b47d8a 4875 bnx2_init_context(bp);
b6016b76 4876
fba9fe91
MC		 4877 if ((rc = bnx2_init_cpus(bp)) != 0)
4878 return rc;
4879
b6016b76
MC		 4880 bnx2_init_nvram(bp);
4881
5fcaed01 4882 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76 4883
e503e066 4884 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
b6016b76
MC		 4885 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4886 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4ce45e02 4887 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
4edd473f 4888 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4ce45e02 4889 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
4edd473f
MC		 4890 val |= BNX2_MQ_CONFIG_HALT_DIS;
4891 }
68c9f75a 4892
e503e066 4893 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
b6016b76
MC		 4894
4895 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
e503e066
MC		 4896 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4897 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
b6016b76 4898
2bc4078e 4899 val = (BNX2_PAGE_BITS - 8) << 24;
e503e066 4900 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
b6016b76
MC		 4901
4902 /* Configure page size. */
e503e066 4903 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
b6016b76 4904 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2bc4078e 4905 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40;
e503e066 4906 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
b6016b76
MC		 4907
4908 val = bp->mac_addr[0] +
4909 (bp->mac_addr[1] << 8) +
4910 (bp->mac_addr[2] << 16) +
4911 bp->mac_addr[3] +
4912 (bp->mac_addr[4] << 8) +
4913 (bp->mac_addr[5] << 16);
e503e066 4914 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
b6016b76
MC		 4915
4916 /* Program the MTU. Also include 4 bytes for CRC32. */
d8026d93
MC		 4917 mtu = bp->dev->mtu;
4918 val = mtu + ETH_HLEN + ETH_FCS_LEN;
b6016b76
MC		 4919 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4920 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
e503e066 4921 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
b6016b76 4922
d8026d93
MC		 4923 if (mtu < 1500)
4924 mtu = 1500;
4925
4926 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4927 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4928 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4929
155d5561 4930 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
b4b36042
MC		 4931 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4932 bp->bnx2_napi[i].last_status_idx = 0;
4933
efba0180
MC		 4934 bp->idle_chk_status_idx = 0xffff;
4935
b6016b76
MC		 4936 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4937
4938 /* Set up how to generate a link change interrupt. */
e503e066 4939 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
b6016b76 4940
e503e066
MC		 4941 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
4942 (u64) bp->status_blk_mapping & 0xffffffff);
4943 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
b6016b76 4944
e503e066
MC		 4945 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4946 (u64) bp->stats_blk_mapping & 0xffffffff);
4947 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4948 (u64) bp->stats_blk_mapping >> 32);
b6016b76 4949
e503e066
MC		 4950 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4951 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
b6016b76 4952
e503e066
MC		 4953 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4954 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
b6016b76 4955
e503e066
MC		 4956 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4957 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
b6016b76 4958
e503e066 4959 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
b6016b76 4960
e503e066 4961 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
b6016b76 4962
e503e066
MC		 4963 BNX2_WR(bp, BNX2_HC_COM_TICKS,
4964 (bp->com_ticks_int << 16) | bp->com_ticks);
b6016b76 4965
e503e066
MC		 4966 BNX2_WR(bp, BNX2_HC_CMD_TICKS,
4967 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
b6016b76 4968
61d9e3fa 4969 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
e503e066 4970 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
02537b06 4971 else
e503e066
MC		 4972 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4973 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
b6016b76 4974
4ce45e02 4975 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)
8e6a72c4 4976 val = BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76 4977 else {
8e6a72c4
MC		 4978 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4979 BNX2_HC_CONFIG_COLLECT_STATS;
b6016b76
MC		 4980 }
4981
efde73a3 4982 if (bp->flags & BNX2_FLAG_USING_MSIX) {
e503e066
MC		 4983 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4984 BNX2_HC_MSIX_BIT_VECTOR_VAL);
c76c0475 4985
5e9ad9e1
MC		 4986 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4987 }
4988
4989 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
cf7474a6 4990 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
5e9ad9e1 4991
e503e066 4992 BNX2_WR(bp, BNX2_HC_CONFIG, val);
5e9ad9e1 4993
22fa159d
MC		 4994 if (bp->rx_ticks < 25)
4995 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
4996 else
4997 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
4998
5e9ad9e1
MC		 4999 for (i = 1; i < bp->irq_nvecs; i++) {
5000 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5001 BNX2_HC_SB_CONFIG_1;
5002
e503e066 5003 BNX2_WR(bp, base,
c76c0475 5004 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
5e9ad9e1 5005 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
c76c0475
MC		 5006 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5007
e503e066 5008 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
c76c0475
MC		 5009 (bp->tx_quick_cons_trip_int << 16) |
5010 bp->tx_quick_cons_trip);
5011
e503e066 5012 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
c76c0475
MC		 5013 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5014
e503e066
MC		 5015 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5016 (bp->rx_quick_cons_trip_int << 16) |
5e9ad9e1 5017 bp->rx_quick_cons_trip);
8e6a72c4 5018
e503e066 5019 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
5e9ad9e1
MC		 5020 (bp->rx_ticks_int << 16) | bp->rx_ticks);
5021 }
8e6a72c4 5022
b6016b76 5023 /* Clear internal stats counters. */
e503e066 5024 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
b6016b76 5025
e503e066 5026 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
b6016b76
MC		 5027
5028 /* Initialize the receive filter. */
5029 bnx2_set_rx_mode(bp->dev);
5030
4ce45e02 5031 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e503e066 5032 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
0aa38df7 5033 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
e503e066 5034 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
0aa38df7 5035 }
b090ae2b 5036 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
a2f13890 5037 1, 0);
b6016b76 5038
e503e066
MC		 5039 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5040 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
b6016b76
MC		 5041
5042 udelay(20);
5043
e503e066 5044 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
bf5295bb 5045
b090ae2b 5046 return rc;
b6016b76
MC		 5047}
5048
c76c0475
MC		 5049static void
5050bnx2_clear_ring_states(struct bnx2 *bp)
5051{
5052 struct bnx2_napi *bnapi;
35e9010b 5053 struct bnx2_tx_ring_info *txr;
bb4f98ab 5054 struct bnx2_rx_ring_info *rxr;
c76c0475
MC		 5055 int i;
5056
5057 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5058 bnapi = &bp->bnx2_napi[i];
35e9010b 5059 txr = &bnapi->tx_ring;
bb4f98ab 5060 rxr = &bnapi->rx_ring;
c76c0475 5061
35e9010b
MC		 5062 txr->tx_cons = 0;
5063 txr->hw_tx_cons = 0;
bb4f98ab
MC		 5064 rxr->rx_prod_bseq = 0;
5065 rxr->rx_prod = 0;
5066 rxr->rx_cons = 0;
5067 rxr->rx_pg_prod = 0;
5068 rxr->rx_pg_cons = 0;
c76c0475
MC		 5069 }
5070}
5071
59b47d8a 5072static void
35e9010b 5073bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
59b47d8a
MC		 5074{
5075 u32 val, offset0, offset1, offset2, offset3;
62a8313c 5076 u32 cid_addr = GET_CID_ADDR(cid);
59b47d8a 5077
4ce45e02 5078 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
59b47d8a
MC		 5079 offset0 = BNX2_L2CTX_TYPE_XI;
5080 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5081 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5082 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5083 } else {
5084 offset0 = BNX2_L2CTX_TYPE;
5085 offset1 = BNX2_L2CTX_CMD_TYPE;
5086 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5087 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5088 }
5089 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
62a8313c 5090 bnx2_ctx_wr(bp, cid_addr, offset0, val);
59b47d8a
MC		 5091
5092 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
62a8313c 5093 bnx2_ctx_wr(bp, cid_addr, offset1, val);
59b47d8a 5094
35e9010b 5095 val = (u64) txr->tx_desc_mapping >> 32;
62a8313c 5096 bnx2_ctx_wr(bp, cid_addr, offset2, val);
59b47d8a 5097
35e9010b 5098 val = (u64) txr->tx_desc_mapping & 0xffffffff;
62a8313c 5099 bnx2_ctx_wr(bp, cid_addr, offset3, val);
59b47d8a 5100}
b6016b76
MC		 5101
5102static void
35e9010b 5103bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
b6016b76 5104{
2bc4078e 5105 struct bnx2_tx_bd *txbd;
c76c0475
MC		 5106 u32 cid = TX_CID;
5107 struct bnx2_napi *bnapi;
35e9010b 5108 struct bnx2_tx_ring_info *txr;
c76c0475 5109
35e9010b
MC		 5110 bnapi = &bp->bnx2_napi[ring_num];
5111 txr = &bnapi->tx_ring;
5112
5113 if (ring_num == 0)
5114 cid = TX_CID;
5115 else
5116 cid = TX_TSS_CID + ring_num - 1;
b6016b76 5117
2f8af120
MC		 5118 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5119
2bc4078e 5120 txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT];
6aa20a22 5121
35e9010b
MC		 5122 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5123 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
b6016b76 5124
35e9010b
MC		 5125 txr->tx_prod = 0;
5126 txr->tx_prod_bseq = 0;
6aa20a22 5127
35e9010b
MC		 5128 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5129 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
b6016b76 5130
35e9010b 5131 bnx2_init_tx_context(bp, cid, txr);
b6016b76
MC		 5132}
5133
5134static void
2bc4078e
MC		 5135bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[],
5136 u32 buf_size, int num_rings)
b6016b76 5137{
b6016b76 5138 int i;
2bc4078e 5139 struct bnx2_rx_bd *rxbd;
6aa20a22 5140
5d5d0015 5141 for (i = 0; i < num_rings; i++) {
13daffa2 5142 int j;
b6016b76 5143
5d5d0015 5144 rxbd = &rx_ring[i][0];
2bc4078e 5145 for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) {
5d5d0015 5146 rxbd->rx_bd_len = buf_size;
13daffa2
MC		 5147 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5148 }
5d5d0015 5149 if (i == (num_rings - 1))
13daffa2
MC		 5150 j = 0;
5151 else
5152 j = i + 1;
5d5d0015
MC		 5153 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5154 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
13daffa2 5155 }
5d5d0015
MC		 5156}
5157
5158static void
bb4f98ab 5159bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5d5d0015
MC		 5160{
5161 int i;
5162 u16 prod, ring_prod;
bb4f98ab
MC		 5163 u32 cid, rx_cid_addr, val;
5164 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5165 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5166
5167 if (ring_num == 0)
5168 cid = RX_CID;
5169 else
5170 cid = RX_RSS_CID + ring_num - 1;
5171
5172 rx_cid_addr = GET_CID_ADDR(cid);
5d5d0015 5173
bb4f98ab 5174 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5d5d0015
MC		 5175 bp->rx_buf_use_size, bp->rx_max_ring);
5176
bb4f98ab 5177 bnx2_init_rx_context(bp, cid);
83e3fc89 5178
4ce45e02 5179 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e503e066
MC		 5180 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5181 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
83e3fc89
MC		 5182 }
5183
62a8313c 5184 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
47bf4246 5185 if (bp->rx_pg_ring_size) {
bb4f98ab
MC		 5186 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5187 rxr->rx_pg_desc_mapping,
47bf4246
MC		 5188 PAGE_SIZE, bp->rx_max_pg_ring);
5189 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
62a8313c
MC		 5190 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5191 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5e9ad9e1 5192 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
47bf4246 5193
bb4f98ab 5194 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
62a8313c 5195 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
47bf4246 5196
bb4f98ab 5197 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
62a8313c 5198 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
47bf4246 5199
4ce45e02 5200 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
e503e066 5201 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
47bf4246 5202 }
b6016b76 5203
bb4f98ab 5204 val = (u64) rxr->rx_desc_mapping[0] >> 32;
62a8313c 5205 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
b6016b76 5206
bb4f98ab 5207 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
62a8313c 5208 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
b6016b76 5209
bb4f98ab 5210 ring_prod = prod = rxr->rx_pg_prod;
47bf4246 5211 for (i = 0; i < bp->rx_pg_ring_size; i++) {
a2df00aa 5212 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5213 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5214 ring_num, i, bp->rx_pg_ring_size);
47bf4246 5215 break;
b929e53c 5216 }
2bc4078e
MC		 5217 prod = BNX2_NEXT_RX_BD(prod);
5218 ring_prod = BNX2_RX_PG_RING_IDX(prod);
47bf4246 5219 }
bb4f98ab 5220 rxr->rx_pg_prod = prod;
47bf4246 5221
bb4f98ab 5222 ring_prod = prod = rxr->rx_prod;
236b6394 5223 for (i = 0; i < bp->rx_ring_size; i++) {
dd2bc8e9 5224 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
3a9c6a49
JP		 5225 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5226 ring_num, i, bp->rx_ring_size);
b6016b76 5227 break;
b929e53c 5228 }
2bc4078e
MC		 5229 prod = BNX2_NEXT_RX_BD(prod);
5230 ring_prod = BNX2_RX_RING_IDX(prod);
b6016b76 5231 }
bb4f98ab 5232 rxr->rx_prod = prod;
b6016b76 5233
bb4f98ab
MC		 5234 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5235 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5236 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
b6016b76 5237
e503e066
MC		 5238 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5239 BNX2_WR16(bp, rxr->rx_bidx_addr, prod);
bb4f98ab 5240
e503e066 5241 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
b6016b76
MC		 5242}
5243
35e9010b
MC		 5244static void
5245bnx2_init_all_rings(struct bnx2 *bp)
5246{
5247 int i;
5e9ad9e1 5248 u32 val;
35e9010b
MC		 5249
5250 bnx2_clear_ring_states(bp);
5251
e503e066 5252 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
35e9010b
MC		 5253 for (i = 0; i < bp->num_tx_rings; i++)
5254 bnx2_init_tx_ring(bp, i);
5255
5256 if (bp->num_tx_rings > 1)
e503e066
MC		 5257 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5258 (TX_TSS_CID << 7));
35e9010b 5259
e503e066 5260 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5e9ad9e1
MC		 5261 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5262
bb4f98ab
MC		 5263 for (i = 0; i < bp->num_rx_rings; i++)
5264 bnx2_init_rx_ring(bp, i);
5e9ad9e1
MC		 5265
5266 if (bp->num_rx_rings > 1) {
22fa159d 5267 u32 tbl_32 = 0;
5e9ad9e1
MC		 5268
5269 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
22fa159d
MC		 5270 int shift = (i % 8) << 2;
5271
5272 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5273 if ((i % 8) == 7) {
e503e066
MC		 5274 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5275 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
22fa159d
MC		 5276 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5277 BNX2_RLUP_RSS_COMMAND_WRITE |
5278 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5279 tbl_32 = 0;
5280 }
5e9ad9e1
MC		 5281 }
5282
5283 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5284 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5285
e503e066 5286 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5e9ad9e1
MC		 5287
5288 }
35e9010b
MC		 5289}
5290
5d5d0015 5291static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
13daffa2 5292{
5d5d0015 5293 u32 max, num_rings = 1;
13daffa2 5294
2bc4078e
MC		 5295 while (ring_size > BNX2_MAX_RX_DESC_CNT) {
5296 ring_size -= BNX2_MAX_RX_DESC_CNT;
13daffa2
MC		 5297 num_rings++;
5298 }
5299 /* round to next power of 2 */
5d5d0015 5300 max = max_size;
13daffa2
MC		 5301 while ((max & num_rings) == 0)
5302 max >>= 1;
5303
5304 if (num_rings != max)
5305 max <<= 1;
5306
5d5d0015
MC		 5307 return max;
5308}
5309
5310static void
5311bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5312{
84eaa187 5313 u32 rx_size, rx_space, jumbo_size;
5d5d0015
MC		 5314
5315 /* 8 for CRC and VLAN */
d89cb6af 5316 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5d5d0015 5317
84eaa187 5318 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
dd2bc8e9 5319 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
84eaa187 5320
601d3d18 5321 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
47bf4246
MC		 5322 bp->rx_pg_ring_size = 0;
5323 bp->rx_max_pg_ring = 0;
5324 bp->rx_max_pg_ring_idx = 0;
f86e82fb 5325 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
84eaa187
MC		 5326 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5327
5328 jumbo_size = size * pages;
2bc4078e
MC		 5329 if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT)
5330 jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
84eaa187
MC		 5331
5332 bp->rx_pg_ring_size = jumbo_size;
5333 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
2bc4078e
MC		 5334 BNX2_MAX_RX_PG_RINGS);
5335 bp->rx_max_pg_ring_idx =
5336 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;
601d3d18 5337 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
84eaa187
MC		 5338 bp->rx_copy_thresh = 0;
5339 }
5d5d0015
MC		 5340
5341 bp->rx_buf_use_size = rx_size;
dd2bc8e9
ED		 5342 /* hw alignment + build_skb() overhead*/
5343 bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
5344 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
d89cb6af 5345 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5d5d0015 5346 bp->rx_ring_size = size;
2bc4078e
MC		 5347 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);
5348 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;
13daffa2
MC		 5349}
5350
b6016b76
MC		 5351static void
5352bnx2_free_tx_skbs(struct bnx2 *bp)
5353{
5354 int i;
5355
35e9010b
MC		 5356 for (i = 0; i < bp->num_tx_rings; i++) {
5357 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5358 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5359 int j;
b6016b76 5360
35e9010b 5361 if (txr->tx_buf_ring == NULL)
b6016b76 5362 continue;
b6016b76 5363
2bc4078e
MC		 5364 for (j = 0; j < BNX2_TX_DESC_CNT; ) {
5365 struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
35e9010b 5366 struct sk_buff *skb = tx_buf->skb;
e95524a7 5367 int k, last;
35e9010b
MC		 5368
5369 if (skb == NULL) {
2bc4078e 5370 j = BNX2_NEXT_TX_BD(j);
35e9010b
MC		 5371 continue;
5372 }
5373
36227e88 5374 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5375 dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 5376 skb_headlen(skb),
5377 PCI_DMA_TODEVICE);
b6016b76 5378
35e9010b 5379 tx_buf->skb = NULL;
b6016b76 5380
e95524a7 5381 last = tx_buf->nr_frags;
2bc4078e
MC		 5382 j = BNX2_NEXT_TX_BD(j);
5383 for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) {
5384 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)];
36227e88 5385 dma_unmap_page(&bp->pdev->dev,
1a4ccc2d 5386 dma_unmap_addr(tx_buf, mapping),
9e903e08 5387 skb_frag_size(&skb_shinfo(skb)->frags[k]),
e95524a7
AD		 5388 PCI_DMA_TODEVICE);
5389 }
35e9010b 5390 dev_kfree_skb(skb);
b6016b76 5391 }
e9831909 5392 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
b6016b76 5393 }
b6016b76
MC		 5394}
5395
5396static void
5397bnx2_free_rx_skbs(struct bnx2 *bp)
5398{
5399 int i;
5400
bb4f98ab
MC		 5401 for (i = 0; i < bp->num_rx_rings; i++) {
5402 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5403 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5404 int j;
b6016b76 5405
bb4f98ab
MC		 5406 if (rxr->rx_buf_ring == NULL)
5407 return;
b6016b76 5408
bb4f98ab 5409 for (j = 0; j < bp->rx_max_ring_idx; j++) {
2bc4078e 5410 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j];
dd2bc8e9 5411 u8 *data = rx_buf->data;
b6016b76 5412
dd2bc8e9 5413 if (data == NULL)
bb4f98ab 5414 continue;
b6016b76 5415
36227e88 5416 dma_unmap_single(&bp->pdev->dev,
1a4ccc2d 5417 dma_unmap_addr(rx_buf, mapping),
bb4f98ab
MC		 5418 bp->rx_buf_use_size,
5419 PCI_DMA_FROMDEVICE);
b6016b76 5420
dd2bc8e9 5421 rx_buf->data = NULL;
bb4f98ab 5422
dd2bc8e9 5423 kfree(data);
bb4f98ab
MC		 5424 }
5425 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5426 bnx2_free_rx_page(bp, rxr, j);
b6016b76
MC		 5427 }
5428}
5429
5430static void
5431bnx2_free_skbs(struct bnx2 *bp)
5432{
5433 bnx2_free_tx_skbs(bp);
5434 bnx2_free_rx_skbs(bp);
5435}
5436
5437static int
5438bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5439{
5440 int rc;
5441
5442 rc = bnx2_reset_chip(bp, reset_code);
5443 bnx2_free_skbs(bp);
5444 if (rc)
5445 return rc;
5446
fba9fe91
MC		 5447 if ((rc = bnx2_init_chip(bp)) != 0)
5448 return rc;
5449
35e9010b 5450 bnx2_init_all_rings(bp);
b6016b76
MC		 5451 return 0;
5452}
5453
5454static int
9a120bc5 5455bnx2_init_nic(struct bnx2 *bp, int reset_phy)
b6016b76
MC		 5456{
5457 int rc;
5458
5459 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5460 return rc;
5461
80be4434 5462 spin_lock_bh(&bp->phy_lock);
9a120bc5 5463 bnx2_init_phy(bp, reset_phy);
b6016b76 5464 bnx2_set_link(bp);
543a827d
MC		 5465 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5466 bnx2_remote_phy_event(bp);
0d8a6571 5467 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 5468 return 0;
5469}
5470
74bf4ba3
MC		 5471static int
5472bnx2_shutdown_chip(struct bnx2 *bp)
5473{
5474 u32 reset_code;
5475
5476 if (bp->flags & BNX2_FLAG_NO_WOL)
5477 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5478 else if (bp->wol)
5479 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5480 else
5481 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5482
5483 return bnx2_reset_chip(bp, reset_code);
5484}
5485
b6016b76
MC		 5486static int
5487bnx2_test_registers(struct bnx2 *bp)
5488{
5489 int ret;
5bae30c9 5490 int i, is_5709;
f71e1309 5491 static const struct {
b6016b76
MC		 5492 u16 offset;
5493 u16 flags;
5bae30c9 5494#define BNX2_FL_NOT_5709 1
b6016b76
MC		 5495 u32 rw_mask;
5496 u32 ro_mask;
5497 } reg_tbl[] = {
5498 { 0x006c, 0, 0x00000000, 0x0000003f },
5499 { 0x0090, 0, 0xffffffff, 0x00000000 },
5500 { 0x0094, 0, 0x00000000, 0x00000000 },
5501
5bae30c9
MC		 5502 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5503 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5504 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5505 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5506 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5507 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5508 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5509 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5510 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5511
5512 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5513 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5514 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5515 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5516 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5517 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5518
5519 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5520 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5521 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
b6016b76
MC		 5522
5523 { 0x1000, 0, 0x00000000, 0x00000001 },
15b169cc 5524 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
b6016b76
MC		 5525
5526 { 0x1408, 0, 0x01c00800, 0x00000000 },
5527 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5528 { 0x14a8, 0, 0x00000000, 0x000001ff },
5b0c76ad 5529 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
b6016b76
MC		 5530 { 0x14b0, 0, 0x00000002, 0x00000001 },
5531 { 0x14b8, 0, 0x00000000, 0x00000000 },
5532 { 0x14c0, 0, 0x00000000, 0x00000009 },
5533 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5534 { 0x14cc, 0, 0x00000000, 0x00000001 },
5535 { 0x14d0, 0, 0xffffffff, 0x00000000 },
b6016b76
MC		 5536
5537 { 0x1800, 0, 0x00000000, 0x00000001 },
5538 { 0x1804, 0, 0x00000000, 0x00000003 },
b6016b76
MC		 5539
5540 { 0x2800, 0, 0x00000000, 0x00000001 },
5541 { 0x2804, 0, 0x00000000, 0x00003f01 },
5542 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5543 { 0x2810, 0, 0xffff0000, 0x00000000 },
5544 { 0x2814, 0, 0xffff0000, 0x00000000 },
5545 { 0x2818, 0, 0xffff0000, 0x00000000 },
5546 { 0x281c, 0, 0xffff0000, 0x00000000 },
5547 { 0x2834, 0, 0xffffffff, 0x00000000 },
5548 { 0x2840, 0, 0x00000000, 0xffffffff },
5549 { 0x2844, 0, 0x00000000, 0xffffffff },
5550 { 0x2848, 0, 0xffffffff, 0x00000000 },
5551 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5552
5553 { 0x2c00, 0, 0x00000000, 0x00000011 },
5554 { 0x2c04, 0, 0x00000000, 0x00030007 },
5555
b6016b76
MC		 5556 { 0x3c00, 0, 0x00000000, 0x00000001 },
5557 { 0x3c04, 0, 0x00000000, 0x00070000 },
5558 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5559 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5560 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5561 { 0x3c14, 0, 0x00000000, 0xffffffff },
5562 { 0x3c18, 0, 0x00000000, 0xffffffff },
5563 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5564 { 0x3c20, 0, 0xffffff00, 0x00000000 },
b6016b76
MC		 5565
5566 { 0x5004, 0, 0x00000000, 0x0000007f },
5567 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
b6016b76 5568
b6016b76
MC		 5569 { 0x5c00, 0, 0x00000000, 0x00000001 },
5570 { 0x5c04, 0, 0x00000000, 0x0003000f },
5571 { 0x5c08, 0, 0x00000003, 0x00000000 },
5572 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5573 { 0x5c10, 0, 0x00000000, 0xffffffff },
5574 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5575 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5576 { 0x5c88, 0, 0x00000000, 0x00077373 },
5577 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5578
5579 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5580 { 0x680c, 0, 0xffffffff, 0x00000000 },
5581 { 0x6810, 0, 0xffffffff, 0x00000000 },
5582 { 0x6814, 0, 0xffffffff, 0x00000000 },
5583 { 0x6818, 0, 0xffffffff, 0x00000000 },
5584 { 0x681c, 0, 0xffffffff, 0x00000000 },
5585 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5586 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5587 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5588 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5589 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5590 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5591 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5592 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5593 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5594 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5595 { 0x684c, 0, 0xffffffff, 0x00000000 },
5596 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5597 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5598 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5599 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5600 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5601 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5602
5603 { 0xffff, 0, 0x00000000, 0x00000000 },
5604 };
5605
5606 ret = 0;
5bae30c9 5607 is_5709 = 0;
4ce45e02 5608 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5bae30c9
MC		 5609 is_5709 = 1;
5610
b6016b76
MC		 5611 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5612 u32 offset, rw_mask, ro_mask, save_val, val;
5bae30c9
MC		 5613 u16 flags = reg_tbl[i].flags;
5614
5615 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5616 continue;
b6016b76
MC		 5617
5618 offset = (u32) reg_tbl[i].offset;
5619 rw_mask = reg_tbl[i].rw_mask;
5620 ro_mask = reg_tbl[i].ro_mask;
5621
14ab9b86 5622 save_val = readl(bp->regview + offset);
b6016b76 5623
14ab9b86 5624 writel(0, bp->regview + offset);
b6016b76 5625
14ab9b86 5626 val = readl(bp->regview + offset);
b6016b76
MC		 5627 if ((val & rw_mask) != 0) {
5628 goto reg_test_err;
5629 }
5630
5631 if ((val & ro_mask) != (save_val & ro_mask)) {
5632 goto reg_test_err;
5633 }
5634
14ab9b86 5635 writel(0xffffffff, bp->regview + offset);
b6016b76 5636
14ab9b86 5637 val = readl(bp->regview + offset);
b6016b76
MC		 5638 if ((val & rw_mask) != rw_mask) {
5639 goto reg_test_err;
5640 }
5641
5642 if ((val & ro_mask) != (save_val & ro_mask)) {
5643 goto reg_test_err;
5644 }
5645
14ab9b86 5646 writel(save_val, bp->regview + offset);
b6016b76
MC		 5647 continue;
5648
5649reg_test_err:
14ab9b86 5650 writel(save_val, bp->regview + offset);
b6016b76
MC		 5651 ret = -ENODEV;
5652 break;
5653 }
5654 return ret;
5655}
5656
5657static int
5658bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5659{
f71e1309 5660 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
b6016b76
MC		 5661 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5662 int i;
5663
5664 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5665 u32 offset;
5666
5667 for (offset = 0; offset < size; offset += 4) {
5668
2726d6e1 5669 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
b6016b76 5670
2726d6e1 5671 if (bnx2_reg_rd_ind(bp, start + offset) !=
b6016b76
MC		 5672 test_pattern[i]) {
5673 return -ENODEV;
5674 }
5675 }
5676 }
5677 return 0;
5678}
5679
5680static int
5681bnx2_test_memory(struct bnx2 *bp)
5682{
5683 int ret = 0;
5684 int i;
5bae30c9 5685 static struct mem_entry {
b6016b76
MC		 5686 u32 offset;
5687 u32 len;
5bae30c9 5688 } mem_tbl_5706[] = {
b6016b76 5689 { 0x60000, 0x4000 },
5b0c76ad 5690 { 0xa0000, 0x3000 },
b6016b76
MC		 5691 { 0xe0000, 0x4000 },
5692 { 0x120000, 0x4000 },
5693 { 0x1a0000, 0x4000 },
5694 { 0x160000, 0x4000 },
5695 { 0xffffffff, 0 },
5bae30c9
MC		 5696 },
5697 mem_tbl_5709[] = {
5698 { 0x60000, 0x4000 },
5699 { 0xa0000, 0x3000 },
5700 { 0xe0000, 0x4000 },
5701 { 0x120000, 0x4000 },
5702 { 0x1a0000, 0x4000 },
5703 { 0xffffffff, 0 },
b6016b76 5704 };
5bae30c9
MC		 5705 struct mem_entry *mem_tbl;
5706
4ce45e02 5707 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
5bae30c9
MC		 5708 mem_tbl = mem_tbl_5709;
5709 else
5710 mem_tbl = mem_tbl_5706;
b6016b76
MC		 5711
5712 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5713 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5714 mem_tbl[i].len)) != 0) {
5715 return ret;
5716 }
5717 }
6aa20a22 5718
b6016b76
MC		 5719 return ret;
5720}
5721
bc5a0690
MC		 5722#define BNX2_MAC_LOOPBACK 0
5723#define BNX2_PHY_LOOPBACK 1
5724
b6016b76 5725static int
bc5a0690 5726bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
b6016b76
MC		 5727{
5728 unsigned int pkt_size, num_pkts, i;
dd2bc8e9
ED		 5729 struct sk_buff *skb;
5730 u8 *data;
b6016b76 5731 unsigned char *packet;
bc5a0690 5732 u16 rx_start_idx, rx_idx;
b6016b76 5733 dma_addr_t map;
2bc4078e
MC		 5734 struct bnx2_tx_bd *txbd;
5735 struct bnx2_sw_bd *rx_buf;
b6016b76
MC		 5736 struct l2_fhdr *rx_hdr;
5737 int ret = -ENODEV;
c76c0475 5738 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
35e9010b 5739 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
bb4f98ab 5740 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
c76c0475
MC		 5741
5742 tx_napi = bnapi;
b6016b76 5743
35e9010b 5744 txr = &tx_napi->tx_ring;
bb4f98ab 5745 rxr = &bnapi->rx_ring;
bc5a0690
MC		 5746 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5747 bp->loopback = MAC_LOOPBACK;
5748 bnx2_set_mac_loopback(bp);
5749 }
5750 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
583c28e5 5751 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
489310a4
MC		 5752 return 0;
5753
80be4434 5754 bp->loopback = PHY_LOOPBACK;
bc5a0690
MC		 5755 bnx2_set_phy_loopback(bp);
5756 }
5757 else
5758 return -EINVAL;
b6016b76 5759
84eaa187 5760 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
932f3772 5761 skb = netdev_alloc_skb(bp->dev, pkt_size);
b6cbc3b6
JL		 5762 if (!skb)
5763 return -ENOMEM;
b6016b76 5764 packet = skb_put(skb, pkt_size);
d458cdf7
JP		 5765 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
5766 memset(packet + ETH_ALEN, 0x0, 8);
b6016b76
MC		 5767 for (i = 14; i < pkt_size; i++)
5768 packet[i] = (unsigned char) (i & 0xff);
5769
36227e88
SG		 5770 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5771 PCI_DMA_TODEVICE);
5772 if (dma_mapping_error(&bp->pdev->dev, map)) {
3d16af86
BL		 5773 dev_kfree_skb(skb);
5774 return -EIO;
5775 }
b6016b76 5776
e503e066
MC		 5777 BNX2_WR(bp, BNX2_HC_COMMAND,
5778 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
bf5295bb 5779
e503e066 5780 BNX2_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 5781
5782 udelay(5);
35efa7c1 5783 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76 5784
b6016b76
MC		 5785 num_pkts = 0;
5786
2bc4078e 5787 txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)];
b6016b76
MC		 5788
5789 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5790 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5791 txbd->tx_bd_mss_nbytes = pkt_size;
5792 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5793
5794 num_pkts++;
2bc4078e 5795 txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod);
35e9010b 5796 txr->tx_prod_bseq += pkt_size;
b6016b76 5797
e503e066
MC		 5798 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5799 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 5800
5801 udelay(100);
5802
e503e066
MC		 5803 BNX2_WR(bp, BNX2_HC_COMMAND,
5804 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
bf5295bb 5805
e503e066 5806 BNX2_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 5807
5808 udelay(5);
5809
36227e88 5810 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
745720e5 5811 dev_kfree_skb(skb);
b6016b76 5812
35e9010b 5813 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
b6016b76 5814 goto loopback_test_done;
b6016b76 5815
35efa7c1 5816 rx_idx = bnx2_get_hw_rx_cons(bnapi);
b6016b76
MC		 5817 if (rx_idx != rx_start_idx + num_pkts) {
5818 goto loopback_test_done;
5819 }
5820
bb4f98ab 5821 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
dd2bc8e9 5822 data = rx_buf->data;
b6016b76 5823
dd2bc8e9
ED		 5824 rx_hdr = get_l2_fhdr(data);
5825 data = (u8 *)rx_hdr + BNX2_RX_OFFSET;
b6016b76 5826
36227e88 5827 dma_sync_single_for_cpu(&bp->pdev->dev,
1a4ccc2d 5828 dma_unmap_addr(rx_buf, mapping),
dd2bc8e9 5829 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
b6016b76 5830
ade2bfe7 5831 if (rx_hdr->l2_fhdr_status &
b6016b76
MC		 5832 (L2_FHDR_ERRORS_BAD_CRC |
5833 L2_FHDR_ERRORS_PHY_DECODE |
5834 L2_FHDR_ERRORS_ALIGNMENT |
5835 L2_FHDR_ERRORS_TOO_SHORT |
5836 L2_FHDR_ERRORS_GIANT_FRAME)) {
5837
5838 goto loopback_test_done;
5839 }
5840
5841 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5842 goto loopback_test_done;
5843 }
5844
5845 for (i = 14; i < pkt_size; i++) {
dd2bc8e9 5846 if (*(data + i) != (unsigned char) (i & 0xff)) {
b6016b76
MC		 5847 goto loopback_test_done;
5848 }
5849 }
5850
5851 ret = 0;
5852
5853loopback_test_done:
5854 bp->loopback = 0;
5855 return ret;
5856}
5857
bc5a0690
MC		 5858#define BNX2_MAC_LOOPBACK_FAILED 1
5859#define BNX2_PHY_LOOPBACK_FAILED 2
5860#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5861 BNX2_PHY_LOOPBACK_FAILED)
5862
5863static int
5864bnx2_test_loopback(struct bnx2 *bp)
5865{
5866 int rc = 0;
5867
5868 if (!netif_running(bp->dev))
5869 return BNX2_LOOPBACK_FAILED;
5870
5871 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5872 spin_lock_bh(&bp->phy_lock);
9a120bc5 5873 bnx2_init_phy(bp, 1);
bc5a0690
MC		 5874 spin_unlock_bh(&bp->phy_lock);
5875 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5876 rc |= BNX2_MAC_LOOPBACK_FAILED;
5877 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5878 rc |= BNX2_PHY_LOOPBACK_FAILED;
5879 return rc;
5880}
5881
b6016b76
MC		 5882#define NVRAM_SIZE 0x200
5883#define CRC32_RESIDUAL 0xdebb20e3
5884
5885static int
5886bnx2_test_nvram(struct bnx2 *bp)
5887{
b491edd5 5888 __be32 buf[NVRAM_SIZE / 4];
b6016b76
MC		 5889 u8 *data = (u8 *) buf;
5890 int rc = 0;
5891 u32 magic, csum;
5892
5893 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5894 goto test_nvram_done;
5895
5896 magic = be32_to_cpu(buf[0]);
5897 if (magic != 0x669955aa) {
5898 rc = -ENODEV;
5899 goto test_nvram_done;
5900 }
5901
5902 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5903 goto test_nvram_done;
5904
5905 csum = ether_crc_le(0x100, data);
5906 if (csum != CRC32_RESIDUAL) {
5907 rc = -ENODEV;
5908 goto test_nvram_done;
5909 }
5910
5911 csum = ether_crc_le(0x100, data + 0x100);
5912 if (csum != CRC32_RESIDUAL) {
5913 rc = -ENODEV;
5914 }
5915
5916test_nvram_done:
5917 return rc;
5918}
5919
5920static int
5921bnx2_test_link(struct bnx2 *bp)
5922{
5923 u32 bmsr;
5924
9f52b564
MC		 5925 if (!netif_running(bp->dev))
5926 return -ENODEV;
5927
583c28e5 5928 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
489310a4
MC		 5929 if (bp->link_up)
5930 return 0;
5931 return -ENODEV;
5932 }
c770a65c 5933 spin_lock_bh(&bp->phy_lock);
27a005b8
MC		 5934 bnx2_enable_bmsr1(bp);
5935 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5936 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5937 bnx2_disable_bmsr1(bp);
c770a65c 5938 spin_unlock_bh(&bp->phy_lock);
6aa20a22 5939
b6016b76
MC		 5940 if (bmsr & BMSR_LSTATUS) {
5941 return 0;
5942 }
5943 return -ENODEV;
5944}
5945
5946static int
5947bnx2_test_intr(struct bnx2 *bp)
5948{
5949 int i;
b6016b76
MC		 5950 u16 status_idx;
5951
5952 if (!netif_running(bp->dev))
5953 return -ENODEV;
5954
e503e066 5955 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
b6016b76
MC		 5956
5957 /* This register is not touched during run-time. */
e503e066
MC		 5958 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5959 BNX2_RD(bp, BNX2_HC_COMMAND);
b6016b76
MC		 5960
5961 for (i = 0; i < 10; i++) {
e503e066 5962 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
b6016b76
MC		 5963 status_idx) {
5964
5965 break;
5966 }
5967
5968 msleep_interruptible(10);
5969 }
5970 if (i < 10)
5971 return 0;
5972
5973 return -ENODEV;
5974}
5975
38ea3686 5976/* Determining link for parallel detection. */
b2fadeae
MC		 5977static int
5978bnx2_5706_serdes_has_link(struct bnx2 *bp)
5979{
5980 u32 mode_ctl, an_dbg, exp;
5981
38ea3686
MC		 5982 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5983 return 0;
5984
b2fadeae
MC		 5985 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5986 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5987
5988 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5989 return 0;
5990
5991 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5992 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5993 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5994
f3014c0c 5995 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
b2fadeae
MC		 5996 return 0;
5997
5998 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5999 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6000 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6001
6002 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6003 return 0;
6004
6005 return 1;
6006}
6007
b6016b76 6008static void
48b01e2d 6009bnx2_5706_serdes_timer(struct bnx2 *bp)
b6016b76 6010{
b2fadeae
MC		 6011 int check_link = 1;
6012
48b01e2d 6013 spin_lock(&bp->phy_lock);
b2fadeae 6014 if (bp->serdes_an_pending) {
48b01e2d 6015 bp->serdes_an_pending--;
b2fadeae
MC		 6016 check_link = 0;
6017 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
48b01e2d 6018 u32 bmcr;
b6016b76 6019
ac392abc 6020 bp->current_interval = BNX2_TIMER_INTERVAL;
cd339a0e 6021
ca58c3af 6022 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 6023
48b01e2d 6024 if (bmcr & BMCR_ANENABLE) {
b2fadeae 6025 if (bnx2_5706_serdes_has_link(bp)) {
48b01e2d
MC		 6026 bmcr &= ~BMCR_ANENABLE;
6027 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
ca58c3af 6028 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
583c28e5 6029 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d 6030 }
b6016b76 6031 }
48b01e2d
MC		 6032 }
6033 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
583c28e5 6034 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
48b01e2d 6035 u32 phy2;
b6016b76 6036
48b01e2d
MC		 6037 bnx2_write_phy(bp, 0x17, 0x0f01);
6038 bnx2_read_phy(bp, 0x15, &phy2);
6039 if (phy2 & 0x20) {
6040 u32 bmcr;
cd339a0e 6041
ca58c3af 6042 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
48b01e2d 6043 bmcr |= BMCR_ANENABLE;
ca58c3af 6044 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
b6016b76 6045
583c28e5 6046 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
48b01e2d
MC		 6047 }
6048 } else
ac392abc 6049 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6050
a2724e25 6051 if (check_link) {
b2fadeae
MC		 6052 u32 val;
6053
6054 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6055 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6056 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6057
a2724e25
MC		 6058 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6059 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6060 bnx2_5706s_force_link_dn(bp, 1);
6061 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6062 } else
6063 bnx2_set_link(bp);
6064 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6065 bnx2_set_link(bp);
b2fadeae 6066 }
48b01e2d
MC		 6067 spin_unlock(&bp->phy_lock);
6068}
b6016b76 6069
f8dd064e
MC		 6070static void
6071bnx2_5708_serdes_timer(struct bnx2 *bp)
6072{
583c28e5 6073 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
0d8a6571
MC		 6074 return;
6075
583c28e5 6076 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
f8dd064e
MC		 6077 bp->serdes_an_pending = 0;
6078 return;
6079 }
b6016b76 6080
f8dd064e
MC		 6081 spin_lock(&bp->phy_lock);
6082 if (bp->serdes_an_pending)
6083 bp->serdes_an_pending--;
6084 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6085 u32 bmcr;
b6016b76 6086
ca58c3af 6087 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
f8dd064e 6088 if (bmcr & BMCR_ANENABLE) {
605a9e20 6089 bnx2_enable_forced_2g5(bp);
40105c0b 6090 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
f8dd064e 6091 } else {
605a9e20 6092 bnx2_disable_forced_2g5(bp);
f8dd064e 6093 bp->serdes_an_pending = 2;
ac392abc 6094 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6095 }
b6016b76 6096
f8dd064e 6097 } else
ac392abc 6098 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 6099
f8dd064e
MC		 6100 spin_unlock(&bp->phy_lock);
6101}
6102
48b01e2d
MC		 6103static void
6104bnx2_timer(unsigned long data)
6105{
6106 struct bnx2 *bp = (struct bnx2 *) data;
b6016b76 6107
48b01e2d
MC		 6108 if (!netif_running(bp->dev))
6109 return;
b6016b76 6110
48b01e2d
MC		 6111 if (atomic_read(&bp->intr_sem) != 0)
6112 goto bnx2_restart_timer;
b6016b76 6113
efba0180
MC		 6114 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6115 BNX2_FLAG_USING_MSI)
6116 bnx2_chk_missed_msi(bp);
6117
df149d70 6118 bnx2_send_heart_beat(bp);
b6016b76 6119
2726d6e1
MC		 6120 bp->stats_blk->stat_FwRxDrop =
6121 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
b6016b76 6122
02537b06 6123 /* workaround occasional corrupted counters */
61d9e3fa 6124 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
e503e066
MC		 6125 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6126 BNX2_HC_COMMAND_STATS_NOW);
02537b06 6127
583c28e5 6128 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
4ce45e02 6129 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
f8dd064e 6130 bnx2_5706_serdes_timer(bp);
27a005b8 6131 else
f8dd064e 6132 bnx2_5708_serdes_timer(bp);
b6016b76
MC		 6133 }
6134
6135bnx2_restart_timer:
cd339a0e 6136 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6137}
6138
8e6a72c4
MC		 6139static int
6140bnx2_request_irq(struct bnx2 *bp)
6141{
6d866ffc 6142 unsigned long flags;
b4b36042
MC		 6143 struct bnx2_irq *irq;
6144 int rc = 0, i;
8e6a72c4 6145
f86e82fb 6146 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6d866ffc
MC		 6147 flags = 0;
6148 else
6149 flags = IRQF_SHARED;
b4b36042
MC		 6150
6151 for (i = 0; i < bp->irq_nvecs; i++) {
6152 irq = &bp->irq_tbl[i];
c76c0475 6153 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
f0ea2e63 6154 &bp->bnx2_napi[i]);
b4b36042
MC		 6155 if (rc)
6156 break;
6157 irq->requested = 1;
6158 }
8e6a72c4
MC		 6159 return rc;
6160}
6161
6162static void
a29ba9d2 6163__bnx2_free_irq(struct bnx2 *bp)
8e6a72c4 6164{
b4b36042
MC		 6165 struct bnx2_irq *irq;
6166 int i;
8e6a72c4 6167
b4b36042
MC		 6168 for (i = 0; i < bp->irq_nvecs; i++) {
6169 irq = &bp->irq_tbl[i];
6170 if (irq->requested)
f0ea2e63 6171 free_irq(irq->vector, &bp->bnx2_napi[i]);
b4b36042 6172 irq->requested = 0;
6d866ffc 6173 }
a29ba9d2
MC		 6174}
6175
6176static void
6177bnx2_free_irq(struct bnx2 *bp)
6178{
6179
6180 __bnx2_free_irq(bp);
f86e82fb 6181 if (bp->flags & BNX2_FLAG_USING_MSI)
b4b36042 6182 pci_disable_msi(bp->pdev);
f86e82fb 6183 else if (bp->flags & BNX2_FLAG_USING_MSIX)
b4b36042
MC		 6184 pci_disable_msix(bp->pdev);
6185
f86e82fb 6186 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
b4b36042
MC		 6187}
6188
6189static void
5e9ad9e1 6190bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
b4b36042 6191{
379b39a2 6192 int i, total_vecs, rc;
57851d84 6193 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
4e1d0de9
MC		 6194 struct net_device *dev = bp->dev;
6195 const int len = sizeof(bp->irq_tbl[0].name);
57851d84 6196
b4b36042 6197 bnx2_setup_msix_tbl(bp);
e503e066
MC		 6198 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6199 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6200 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
57851d84 6201
e2eb8e38
BL		 6202 /* Need to flush the previous three writes to ensure MSI-X
6203 * is setup properly */
e503e066 6204 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
e2eb8e38 6205
57851d84
MC		 6206 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6207 msix_ent[i].entry = i;
6208 msix_ent[i].vector = 0;
6209 }
6210
379b39a2
MC		 6211 total_vecs = msix_vecs;
6212#ifdef BCM_CNIC
6213 total_vecs++;
6214#endif
6215 rc = -ENOSPC;
6216 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6217 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6218 if (rc <= 0)
6219 break;
6220 if (rc > 0)
6221 total_vecs = rc;
6222 }
6223
57851d84
MC		 6224 if (rc != 0)
6225 return;
6226
379b39a2
MC		 6227 msix_vecs = total_vecs;
6228#ifdef BCM_CNIC
6229 msix_vecs--;
6230#endif
5e9ad9e1 6231 bp->irq_nvecs = msix_vecs;
f86e82fb 6232 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
379b39a2 6233 for (i = 0; i < total_vecs; i++) {
57851d84 6234 bp->irq_tbl[i].vector = msix_ent[i].vector;
69010313
MC		 6235 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6236 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6237 }
6d866ffc
MC		 6238}
6239
657d92fe 6240static int
6d866ffc
MC		 6241bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6242{
0a742128 6243 int cpus = netif_get_num_default_rss_queues();
b033281f
MC		 6244 int msix_vecs;
6245
6246 if (!bp->num_req_rx_rings)
6247 msix_vecs = max(cpus + 1, bp->num_req_tx_rings);
6248 else if (!bp->num_req_tx_rings)
6249 msix_vecs = max(cpus, bp->num_req_rx_rings);
6250 else
6251 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);
6252
6253 msix_vecs = min(msix_vecs, RX_MAX_RINGS);
5e9ad9e1 6254
6d866ffc
MC		 6255 bp->irq_tbl[0].handler = bnx2_interrupt;
6256 strcpy(bp->irq_tbl[0].name, bp->dev->name);
b4b36042
MC		 6257 bp->irq_nvecs = 1;
6258 bp->irq_tbl[0].vector = bp->pdev->irq;
6259
3d5f3a7b 6260 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
5e9ad9e1 6261 bnx2_enable_msix(bp, msix_vecs);
6d866ffc 6262
f86e82fb
DM		 6263 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6264 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6d866ffc 6265 if (pci_enable_msi(bp->pdev) == 0) {
f86e82fb 6266 bp->flags |= BNX2_FLAG_USING_MSI;
4ce45e02 6267 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
f86e82fb 6268 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6d866ffc
MC		 6269 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6270 } else
6271 bp->irq_tbl[0].handler = bnx2_msi;
b4b36042
MC		 6272
6273 bp->irq_tbl[0].vector = bp->pdev->irq;
6d866ffc
MC		 6274 }
6275 }
706bf240 6276
b033281f
MC		 6277 if (!bp->num_req_tx_rings)
6278 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6279 else
6280 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);
6281
6282 if (!bp->num_req_rx_rings)
6283 bp->num_rx_rings = bp->irq_nvecs;
6284 else
6285 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);
6286
657d92fe 6287 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
706bf240 6288
657d92fe 6289 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
8e6a72c4
MC		 6290}
6291
b6016b76
MC		 6292/* Called with rtnl_lock */
6293static int
6294bnx2_open(struct net_device *dev)
6295{
972ec0d4 6296 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6297 int rc;
6298
7880b72e 6299 rc = bnx2_request_firmware(bp);
6300 if (rc < 0)
6301 goto out;
6302
1b2f922f
MC		 6303 netif_carrier_off(dev);
6304
b6016b76
MC		 6305 bnx2_disable_int(bp);
6306
657d92fe
BH		 6307 rc = bnx2_setup_int_mode(bp, disable_msi);
6308 if (rc)
6309 goto open_err;
4327ba43 6310 bnx2_init_napi(bp);
35e9010b 6311 bnx2_napi_enable(bp);
b6016b76 6312 rc = bnx2_alloc_mem(bp);
2739a8bb
MC		 6313 if (rc)
6314 goto open_err;
b6016b76 6315
8e6a72c4 6316 rc = bnx2_request_irq(bp);
2739a8bb
MC		 6317 if (rc)
6318 goto open_err;
b6016b76 6319
9a120bc5 6320 rc = bnx2_init_nic(bp, 1);
2739a8bb
MC		 6321 if (rc)
6322 goto open_err;
6aa20a22 6323
cd339a0e 6324 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 6325
6326 atomic_set(&bp->intr_sem, 0);
6327
354fcd77
MC		 6328 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6329
b6016b76
MC		 6330 bnx2_enable_int(bp);
6331
f86e82fb 6332 if (bp->flags & BNX2_FLAG_USING_MSI) {
b6016b76
MC		 6333 /* Test MSI to make sure it is working
6334 * If MSI test fails, go back to INTx mode
6335 */
6336 if (bnx2_test_intr(bp) != 0) {
3a9c6a49 6337 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
b6016b76
MC		 6338
6339 bnx2_disable_int(bp);
8e6a72c4 6340 bnx2_free_irq(bp);
b6016b76 6341
6d866ffc
MC		 6342 bnx2_setup_int_mode(bp, 1);
6343
9a120bc5 6344 rc = bnx2_init_nic(bp, 0);
b6016b76 6345
8e6a72c4
MC		 6346 if (!rc)
6347 rc = bnx2_request_irq(bp);
6348
b6016b76 6349 if (rc) {
b6016b76 6350 del_timer_sync(&bp->timer);
2739a8bb 6351 goto open_err;
b6016b76
MC		 6352 }
6353 bnx2_enable_int(bp);
6354 }
6355 }
f86e82fb 6356 if (bp->flags & BNX2_FLAG_USING_MSI)
3a9c6a49 6357 netdev_info(dev, "using MSI\n");
f86e82fb 6358 else if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6359 netdev_info(dev, "using MSIX\n");
b6016b76 6360
706bf240 6361 netif_tx_start_all_queues(dev);
7880b72e 6362out:
6363 return rc;
2739a8bb
MC		 6364
6365open_err:
6366 bnx2_napi_disable(bp);
6367 bnx2_free_skbs(bp);
6368 bnx2_free_irq(bp);
6369 bnx2_free_mem(bp);
f048fa9c 6370 bnx2_del_napi(bp);
7880b72e 6371 bnx2_release_firmware(bp);
6372 goto out;
b6016b76
MC		 6373}
6374
6375static void
c4028958 6376bnx2_reset_task(struct work_struct *work)
b6016b76 6377{
c4028958 6378 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
cd634019 6379 int rc;
efdfad32 6380 u16 pcicmd;
b6016b76 6381
51bf6bb4
MC		 6382 rtnl_lock();
6383 if (!netif_running(bp->dev)) {
6384 rtnl_unlock();
afdc08b9 6385 return;
51bf6bb4 6386 }
afdc08b9 6387
212f9934 6388 bnx2_netif_stop(bp, true);
b6016b76 6389
efdfad32
MC		 6390 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);
6391 if (!(pcicmd & PCI_COMMAND_MEMORY)) {
6392 /* in case PCI block has reset */
6393 pci_restore_state(bp->pdev);
6394 pci_save_state(bp->pdev);
6395 }
cd634019
MC		 6396 rc = bnx2_init_nic(bp, 1);
6397 if (rc) {
6398 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6399 bnx2_napi_enable(bp);
6400 dev_close(bp->dev);
6401 rtnl_unlock();
6402 return;
6403 }
b6016b76
MC		 6404
6405 atomic_set(&bp->intr_sem, 1);
212f9934 6406 bnx2_netif_start(bp, true);
51bf6bb4 6407 rtnl_unlock();
b6016b76
MC		 6408}
6409
555069da
MC		 6410#define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL }
6411
6412static void
6413bnx2_dump_ftq(struct bnx2 *bp)
6414{
6415 int i;
6416 u32 reg, bdidx, cid, valid;
6417 struct net_device *dev = bp->dev;
6418 static const struct ftq_reg {
6419 char *name;
6420 u32 off;
6421 } ftq_arr[] = {
6422 BNX2_FTQ_ENTRY(RV2P_P),
6423 BNX2_FTQ_ENTRY(RV2P_T),
6424 BNX2_FTQ_ENTRY(RV2P_M),
6425 BNX2_FTQ_ENTRY(TBDR_),
6426 BNX2_FTQ_ENTRY(TDMA_),
6427 BNX2_FTQ_ENTRY(TXP_),
6428 BNX2_FTQ_ENTRY(TXP_),
6429 BNX2_FTQ_ENTRY(TPAT_),
6430 BNX2_FTQ_ENTRY(RXP_C),
6431 BNX2_FTQ_ENTRY(RXP_),
6432 BNX2_FTQ_ENTRY(COM_COMXQ_),
6433 BNX2_FTQ_ENTRY(COM_COMTQ_),
6434 BNX2_FTQ_ENTRY(COM_COMQ_),
6435 BNX2_FTQ_ENTRY(CP_CPQ_),
6436 };
6437
6438 netdev_err(dev, "<--- start FTQ dump --->\n");
6439 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++)
6440 netdev_err(dev, "%s %08x\n", ftq_arr[i].name,
6441 bnx2_reg_rd_ind(bp, ftq_arr[i].off));
6442
6443 netdev_err(dev, "CPU states:\n");
6444 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000)
6445 netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n",
6446 reg, bnx2_reg_rd_ind(bp, reg),
6447 bnx2_reg_rd_ind(bp, reg + 4),
6448 bnx2_reg_rd_ind(bp, reg + 8),
6449 bnx2_reg_rd_ind(bp, reg + 0x1c),
6450 bnx2_reg_rd_ind(bp, reg + 0x1c),
6451 bnx2_reg_rd_ind(bp, reg + 0x20));
6452
6453 netdev_err(dev, "<--- end FTQ dump --->\n");
6454 netdev_err(dev, "<--- start TBDC dump --->\n");
6455 netdev_err(dev, "TBDC free cnt: %ld\n",
e503e066 6456 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
555069da
MC		 6457 netdev_err(dev, "LINE CID BIDX CMD VALIDS\n");
6458 for (i = 0; i < 0x20; i++) {
6459 int j = 0;
6460
e503e066
MC		 6461 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
6462 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
6463 BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ);
6464 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6465 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
555069da
MC		 6466 BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100)
6467 j++;
6468
e503e066
MC		 6469 cid = BNX2_RD(bp, BNX2_TBDC_CID);
6470 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
6471 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
555069da
MC		 6472 netdev_err(dev, "%02x %06x %04lx %02x [%x]\n",
6473 i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX,
6474 bdidx >> 24, (valid >> 8) & 0x0ff);
6475 }
6476 netdev_err(dev, "<--- end TBDC dump --->\n");
6477}
6478
20175c57
MC		 6479static void
6480bnx2_dump_state(struct bnx2 *bp)
6481{
6482 struct net_device *dev = bp->dev;
ecdbf6e0 6483 u32 val1, val2;
5804a8fb
MC		 6484
6485 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6486 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6487 atomic_read(&bp->intr_sem), val1);
6488 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6489 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6490 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
b98eba52 6491 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
e503e066
MC		 6492 BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
6493 BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
b98eba52 6494 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
e503e066 6495 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
3a9c6a49 6496 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
e503e066 6497 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
20175c57 6498 if (bp->flags & BNX2_FLAG_USING_MSIX)
3a9c6a49 6499 netdev_err(dev, "DEBUG: PBA[%08x]\n",
e503e066 6500 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
20175c57
MC		 6501}
6502
b6016b76
MC		 6503static void
6504bnx2_tx_timeout(struct net_device *dev)
6505{
972ec0d4 6506 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6507
555069da 6508 bnx2_dump_ftq(bp);
20175c57 6509 bnx2_dump_state(bp);
ecdbf6e0 6510 bnx2_dump_mcp_state(bp);
20175c57 6511
b6016b76
MC		 6512 /* This allows the netif to be shutdown gracefully before resetting */
6513 schedule_work(&bp->reset_task);
6514}
6515
932ff279 6516/* Called with netif_tx_lock.
2f8af120
MC		 6517 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6518 * netif_wake_queue().
b6016b76 6519 */
61357325 6520static netdev_tx_t
b6016b76
MC		 6521bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6522{
972ec0d4 6523 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6524 dma_addr_t mapping;
2bc4078e
MC		 6525 struct bnx2_tx_bd *txbd;
6526 struct bnx2_sw_tx_bd *tx_buf;
b6016b76
MC		 6527 u32 len, vlan_tag_flags, last_frag, mss;
6528 u16 prod, ring_prod;
6529 int i;
706bf240
BL		 6530 struct bnx2_napi *bnapi;
6531 struct bnx2_tx_ring_info *txr;
6532 struct netdev_queue *txq;
6533
6534 /* Determine which tx ring we will be placed on */
6535 i = skb_get_queue_mapping(skb);
6536 bnapi = &bp->bnx2_napi[i];
6537 txr = &bnapi->tx_ring;
6538 txq = netdev_get_tx_queue(dev, i);
b6016b76 6539
35e9010b 6540 if (unlikely(bnx2_tx_avail(bp, txr) <
a550c99b 6541 (skb_shinfo(skb)->nr_frags + 1))) {
706bf240 6542 netif_tx_stop_queue(txq);
3a9c6a49 6543 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
b6016b76
MC		 6544
6545 return NETDEV_TX_BUSY;
6546 }
6547 len = skb_headlen(skb);
35e9010b 6548 prod = txr->tx_prod;
2bc4078e 6549 ring_prod = BNX2_TX_RING_IDX(prod);
b6016b76
MC		 6550
6551 vlan_tag_flags = 0;
84fa7933 6552 if (skb->ip_summed == CHECKSUM_PARTIAL) {
b6016b76
MC		 6553 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6554 }
6555
eab6d18d 6556 if (vlan_tx_tag_present(skb)) {
b6016b76
MC		 6557 vlan_tag_flags |=
6558 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6559 }
7d0fd211 6560
fde82055 6561 if ((mss = skb_shinfo(skb)->gso_size)) {
a1efb4b6 6562 u32 tcp_opt_len;
eddc9ec5 6563 struct iphdr *iph;
b6016b76 6564
b6016b76
MC		 6565 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6566
4666f87a
MC		 6567 tcp_opt_len = tcp_optlen(skb);
6568
6569 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6570 u32 tcp_off = skb_transport_offset(skb) -
6571 sizeof(struct ipv6hdr) - ETH_HLEN;
ab6a5bb6 6572
4666f87a
MC		 6573 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6574 TX_BD_FLAGS_SW_FLAGS;
6575 if (likely(tcp_off == 0))
6576 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6577 else {
6578 tcp_off >>= 3;
6579 vlan_tag_flags |= ((tcp_off & 0x3) <<
6580 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6581 ((tcp_off & 0x10) <<
6582 TX_BD_FLAGS_TCP6_OFF4_SHL);
6583 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6584 }
6585 } else {
4666f87a 6586 iph = ip_hdr(skb);
4666f87a
MC		 6587 if (tcp_opt_len || (iph->ihl > 5)) {
6588 vlan_tag_flags |= ((iph->ihl - 5) +
6589 (tcp_opt_len >> 2)) << 8;
6590 }
b6016b76 6591 }
4666f87a 6592 } else
b6016b76 6593 mss = 0;
b6016b76 6594
36227e88
SG		 6595 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6596 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
3d16af86
BL		 6597 dev_kfree_skb(skb);
6598 return NETDEV_TX_OK;
6599 }
6600
35e9010b 6601 tx_buf = &txr->tx_buf_ring[ring_prod];
b6016b76 6602 tx_buf->skb = skb;
1a4ccc2d 6603 dma_unmap_addr_set(tx_buf, mapping, mapping);
b6016b76 6604
35e9010b 6605 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76
MC		 6606
6607 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6608 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6609 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6610 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6611
6612 last_frag = skb_shinfo(skb)->nr_frags;
d62fda08
ED		 6613 tx_buf->nr_frags = last_frag;
6614 tx_buf->is_gso = skb_is_gso(skb);
b6016b76
MC		 6615
6616 for (i = 0; i < last_frag; i++) {
9e903e08 6617 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
b6016b76 6618
2bc4078e
MC		 6619 prod = BNX2_NEXT_TX_BD(prod);
6620 ring_prod = BNX2_TX_RING_IDX(prod);
35e9010b 6621 txbd = &txr->tx_desc_ring[ring_prod];
b6016b76 6622
9e903e08 6623 len = skb_frag_size(frag);
b7b6a688 6624 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
5d6bcdfe 6625 DMA_TO_DEVICE);
36227e88 6626 if (dma_mapping_error(&bp->pdev->dev, mapping))
e95524a7 6627 goto dma_error;
1a4ccc2d 6628 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
e95524a7 6629 mapping);
b6016b76
MC		 6630
6631 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6632 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6633 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6634 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6635
6636 }
6637 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6638
94bf91ba
VZ		 6639 /* Sync BD data before updating TX mailbox */
6640 wmb();
6641
e9831909
ED		 6642 netdev_tx_sent_queue(txq, skb->len);
6643
2bc4078e 6644 prod = BNX2_NEXT_TX_BD(prod);
35e9010b 6645 txr->tx_prod_bseq += skb->len;
b6016b76 6646
e503e066
MC		 6647 BNX2_WR16(bp, txr->tx_bidx_addr, prod);
6648 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
b6016b76
MC		 6649
6650 mmiowb();
6651
35e9010b 6652 txr->tx_prod = prod;
b6016b76 6653
35e9010b 6654 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
706bf240 6655 netif_tx_stop_queue(txq);
11848b96
MC		 6656
6657 /* netif_tx_stop_queue() must be done before checking
6658 * tx index in bnx2_tx_avail() below, because in
6659 * bnx2_tx_int(), we update tx index before checking for
6660 * netif_tx_queue_stopped().
6661 */
6662 smp_mb();
35e9010b 6663 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
706bf240 6664 netif_tx_wake_queue(txq);
b6016b76
MC		 6665 }
6666
e95524a7
AD		 6667 return NETDEV_TX_OK;
6668dma_error:
6669 /* save value of frag that failed */
6670 last_frag = i;
6671
6672 /* start back at beginning and unmap skb */
6673 prod = txr->tx_prod;
2bc4078e 6674 ring_prod = BNX2_TX_RING_IDX(prod);
e95524a7
AD		 6675 tx_buf = &txr->tx_buf_ring[ring_prod];
6676 tx_buf->skb = NULL;
36227e88 6677 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
e95524a7
AD		 6678 skb_headlen(skb), PCI_DMA_TODEVICE);
6679
6680 /* unmap remaining mapped pages */
6681 for (i = 0; i < last_frag; i++) {
2bc4078e
MC		 6682 prod = BNX2_NEXT_TX_BD(prod);
6683 ring_prod = BNX2_TX_RING_IDX(prod);
e95524a7 6684 tx_buf = &txr->tx_buf_ring[ring_prod];
36227e88 6685 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
9e903e08 6686 skb_frag_size(&skb_shinfo(skb)->frags[i]),
e95524a7
AD		 6687 PCI_DMA_TODEVICE);
6688 }
6689
6690 dev_kfree_skb(skb);
b6016b76
MC		 6691 return NETDEV_TX_OK;
6692}
6693
6694/* Called with rtnl_lock */
6695static int
6696bnx2_close(struct net_device *dev)
6697{
972ec0d4 6698 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6699
bea3348e 6700 bnx2_disable_int_sync(bp);
35efa7c1 6701 bnx2_napi_disable(bp);
d2e553bc 6702 netif_tx_disable(dev);
b6016b76 6703 del_timer_sync(&bp->timer);
74bf4ba3 6704 bnx2_shutdown_chip(bp);
8e6a72c4 6705 bnx2_free_irq(bp);
b6016b76
MC		 6706 bnx2_free_skbs(bp);
6707 bnx2_free_mem(bp);
f048fa9c 6708 bnx2_del_napi(bp);
b6016b76
MC		 6709 bp->link_up = 0;
6710 netif_carrier_off(bp->dev);
b6016b76
MC		 6711 return 0;
6712}
6713
354fcd77
MC		 6714static void
6715bnx2_save_stats(struct bnx2 *bp)
6716{
6717 u32 *hw_stats = (u32 *) bp->stats_blk;
6718 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6719 int i;
6720
6721 /* The 1st 10 counters are 64-bit counters */
6722 for (i = 0; i < 20; i += 2) {
6723 u32 hi;
6724 u64 lo;
6725
c9885fe5
PR		 6726 hi = temp_stats[i] + hw_stats[i];
6727 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
354fcd77
MC		 6728 if (lo > 0xffffffff)
6729 hi++;
c9885fe5
PR		 6730 temp_stats[i] = hi;
6731 temp_stats[i + 1] = lo & 0xffffffff;
354fcd77
MC		 6732 }
6733
6734 for ( ; i < sizeof(struct statistics_block) / 4; i++)
c9885fe5 6735 temp_stats[i] += hw_stats[i];
354fcd77
MC		 6736}
6737
5d07bf26
ED		 6738#define GET_64BIT_NET_STATS64(ctr) \
6739 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
b6016b76 6740
a4743058 6741#define GET_64BIT_NET_STATS(ctr) \
354fcd77
MC		 6742 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6743 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
b6016b76 6744
a4743058 6745#define GET_32BIT_NET_STATS(ctr) \
354fcd77
MC		 6746 (unsigned long) (bp->stats_blk->ctr + \
6747 bp->temp_stats_blk->ctr)
a4743058 6748
5d07bf26
ED		 6749static struct rtnl_link_stats64 *
6750bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
b6016b76 6751{
972ec0d4 6752 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6753
5d07bf26 6754 if (bp->stats_blk == NULL)
b6016b76 6755 return net_stats;
5d07bf26 6756
b6016b76 6757 net_stats->rx_packets =
a4743058
MC		 6758 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6759 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6760 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
b6016b76
MC		 6761
6762 net_stats->tx_packets =
a4743058
MC		 6763 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6764 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6765 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
b6016b76
MC		 6766
6767 net_stats->rx_bytes =
a4743058 6768 GET_64BIT_NET_STATS(stat_IfHCInOctets);
b6016b76
MC		 6769
6770 net_stats->tx_bytes =
a4743058 6771 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
b6016b76 6772
6aa20a22 6773 net_stats->multicast =
6fdae995 6774 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
b6016b76 6775
6aa20a22 6776 net_stats->collisions =
a4743058 6777 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
b6016b76 6778
6aa20a22 6779 net_stats->rx_length_errors =
a4743058
MC		 6780 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6781 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
b6016b76 6782
6aa20a22 6783 net_stats->rx_over_errors =
a4743058
MC		 6784 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6785 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
b6016b76 6786
6aa20a22 6787 net_stats->rx_frame_errors =
a4743058 6788 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
b6016b76 6789
6aa20a22 6790 net_stats->rx_crc_errors =
a4743058 6791 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
b6016b76
MC		 6792
6793 net_stats->rx_errors = net_stats->rx_length_errors +
6794 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6795 net_stats->rx_crc_errors;
6796
6797 net_stats->tx_aborted_errors =
a4743058
MC		 6798 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6799 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
b6016b76 6800
4ce45e02
MC		 6801 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
6802 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
b6016b76
MC		 6803 net_stats->tx_carrier_errors = 0;
6804 else {
6805 net_stats->tx_carrier_errors =
a4743058 6806 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
b6016b76
MC		 6807 }
6808
6809 net_stats->tx_errors =
a4743058 6810 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
b6016b76
MC		 6811 net_stats->tx_aborted_errors +
6812 net_stats->tx_carrier_errors;
6813
cea94db9 6814 net_stats->rx_missed_errors =
a4743058
MC		 6815 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6816 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6817 GET_32BIT_NET_STATS(stat_FwRxDrop);
cea94db9 6818
b6016b76
MC		 6819 return net_stats;
6820}
6821
6822/* All ethtool functions called with rtnl_lock */
6823
6824static int
6825bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6826{
972ec0d4 6827 struct bnx2 *bp = netdev_priv(dev);
7b6b8347 6828 int support_serdes = 0, support_copper = 0;
b6016b76
MC		 6829
6830 cmd->supported = SUPPORTED_Autoneg;
583c28e5 6831 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 6832 support_serdes = 1;
6833 support_copper = 1;
6834 } else if (bp->phy_port == PORT_FIBRE)
6835 support_serdes = 1;
6836 else
6837 support_copper = 1;
6838
6839 if (support_serdes) {
b6016b76
MC		 6840 cmd->supported |= SUPPORTED_1000baseT_Full |
6841 SUPPORTED_FIBRE;
583c28e5 6842 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
605a9e20 6843 cmd->supported |= SUPPORTED_2500baseX_Full;
b6016b76 6844
b6016b76 6845 }
7b6b8347 6846 if (support_copper) {
b6016b76
MC		 6847 cmd->supported |= SUPPORTED_10baseT_Half |
6848 SUPPORTED_10baseT_Full |
6849 SUPPORTED_100baseT_Half |
6850 SUPPORTED_100baseT_Full |
6851 SUPPORTED_1000baseT_Full |
6852 SUPPORTED_TP;
6853
b6016b76
MC		 6854 }
6855
7b6b8347
MC		 6856 spin_lock_bh(&bp->phy_lock);
6857 cmd->port = bp->phy_port;
b6016b76
MC		 6858 cmd->advertising = bp->advertising;
6859
6860 if (bp->autoneg & AUTONEG_SPEED) {
6861 cmd->autoneg = AUTONEG_ENABLE;
70739497 6862 } else {
b6016b76
MC		 6863 cmd->autoneg = AUTONEG_DISABLE;
6864 }
6865
6866 if (netif_carrier_ok(dev)) {
70739497 6867 ethtool_cmd_speed_set(cmd, bp->line_speed);
b6016b76
MC		 6868 cmd->duplex = bp->duplex;
6869 }
6870 else {
70739497 6871 ethtool_cmd_speed_set(cmd, -1);
b6016b76
MC		 6872 cmd->duplex = -1;
6873 }
7b6b8347 6874 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 6875
6876 cmd->transceiver = XCVR_INTERNAL;
6877 cmd->phy_address = bp->phy_addr;
6878
6879 return 0;
6880}
6aa20a22 6881
b6016b76
MC		 6882static int
6883bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6884{
972ec0d4 6885 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 6886 u8 autoneg = bp->autoneg;
6887 u8 req_duplex = bp->req_duplex;
6888 u16 req_line_speed = bp->req_line_speed;
6889 u32 advertising = bp->advertising;
7b6b8347
MC		 6890 int err = -EINVAL;
6891
6892 spin_lock_bh(&bp->phy_lock);
6893
6894 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6895 goto err_out_unlock;
6896
583c28e5
MC		 6897 if (cmd->port != bp->phy_port &&
6898 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
7b6b8347 6899 goto err_out_unlock;
b6016b76 6900
d6b14486
MC		 6901 /* If device is down, we can store the settings only if the user
6902 * is setting the currently active port.
6903 */
6904 if (!netif_running(dev) && cmd->port != bp->phy_port)
6905 goto err_out_unlock;
6906
b6016b76
MC		 6907 if (cmd->autoneg == AUTONEG_ENABLE) {
6908 autoneg |= AUTONEG_SPEED;
6909
beb499af
MC		 6910 advertising = cmd->advertising;
6911 if (cmd->port == PORT_TP) {
6912 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6913 if (!advertising)
b6016b76 6914 advertising = ETHTOOL_ALL_COPPER_SPEED;
beb499af
MC		 6915 } else {
6916 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6917 if (!advertising)
6918 advertising = ETHTOOL_ALL_FIBRE_SPEED;
b6016b76
MC		 6919 }
6920 advertising |= ADVERTISED_Autoneg;
6921 }
6922 else {
25db0338 6923 u32 speed = ethtool_cmd_speed(cmd);
7b6b8347 6924 if (cmd->port == PORT_FIBRE) {
25db0338
DD		 6925 if ((speed != SPEED_1000 &&
6926 speed != SPEED_2500) ||
80be4434 6927 (cmd->duplex != DUPLEX_FULL))
7b6b8347 6928 goto err_out_unlock;
80be4434 6929
25db0338 6930 if (speed == SPEED_2500 &&
583c28e5 6931 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
7b6b8347 6932 goto err_out_unlock;
25db0338 6933 } else if (speed == SPEED_1000 || speed == SPEED_2500)
7b6b8347
MC		 6934 goto err_out_unlock;
6935
b6016b76 6936 autoneg &= ~AUTONEG_SPEED;
25db0338 6937 req_line_speed = speed;
b6016b76
MC		 6938 req_duplex = cmd->duplex;
6939 advertising = 0;
6940 }
6941
6942 bp->autoneg = autoneg;
6943 bp->advertising = advertising;
6944 bp->req_line_speed = req_line_speed;
6945 bp->req_duplex = req_duplex;
6946
d6b14486
MC		 6947 err = 0;
6948 /* If device is down, the new settings will be picked up when it is
6949 * brought up.
6950 */
6951 if (netif_running(dev))
6952 err = bnx2_setup_phy(bp, cmd->port);
b6016b76 6953
7b6b8347 6954err_out_unlock:
c770a65c 6955 spin_unlock_bh(&bp->phy_lock);
b6016b76 6956
7b6b8347 6957 return err;
b6016b76
MC		 6958}
6959
6960static void
6961bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6962{
972ec0d4 6963 struct bnx2 *bp = netdev_priv(dev);
b6016b76 6964
68aad78c
RJ		 6965 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6966 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6967 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
6968 strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
b6016b76
MC		 6969}
6970
244ac4f4
MC		 6971#define BNX2_REGDUMP_LEN (32 * 1024)
6972
6973static int
6974bnx2_get_regs_len(struct net_device *dev)
6975{
6976 return BNX2_REGDUMP_LEN;
6977}
6978
6979static void
6980bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6981{
6982 u32 *p = _p, i, offset;
6983 u8 *orig_p = _p;
6984 struct bnx2 *bp = netdev_priv(dev);
b6bc7650
JP		 6985 static const u32 reg_boundaries[] = {
6986 0x0000, 0x0098, 0x0400, 0x045c,
6987 0x0800, 0x0880, 0x0c00, 0x0c10,
6988 0x0c30, 0x0d08, 0x1000, 0x101c,
6989 0x1040, 0x1048, 0x1080, 0x10a4,
6990 0x1400, 0x1490, 0x1498, 0x14f0,
6991 0x1500, 0x155c, 0x1580, 0x15dc,
6992 0x1600, 0x1658, 0x1680, 0x16d8,
6993 0x1800, 0x1820, 0x1840, 0x1854,
6994 0x1880, 0x1894, 0x1900, 0x1984,
6995 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6996 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6997 0x2000, 0x2030, 0x23c0, 0x2400,
6998 0x2800, 0x2820, 0x2830, 0x2850,
6999 0x2b40, 0x2c10, 0x2fc0, 0x3058,
7000 0x3c00, 0x3c94, 0x4000, 0x4010,
7001 0x4080, 0x4090, 0x43c0, 0x4458,
7002 0x4c00, 0x4c18, 0x4c40, 0x4c54,
7003 0x4fc0, 0x5010, 0x53c0, 0x5444,
7004 0x5c00, 0x5c18, 0x5c80, 0x5c90,
7005 0x5fc0, 0x6000, 0x6400, 0x6428,
7006 0x6800, 0x6848, 0x684c, 0x6860,
7007 0x6888, 0x6910, 0x8000
7008 };
244ac4f4
MC		 7009
7010 regs->version = 0;
7011
7012 memset(p, 0, BNX2_REGDUMP_LEN);
7013
7014 if (!netif_running(bp->dev))
7015 return;
7016
7017 i = 0;
7018 offset = reg_boundaries[0];
7019 p += offset;
7020 while (offset < BNX2_REGDUMP_LEN) {
e503e066 7021 *p++ = BNX2_RD(bp, offset);
244ac4f4
MC		 7022 offset += 4;
7023 if (offset == reg_boundaries[i + 1]) {
7024 offset = reg_boundaries[i + 2];
7025 p = (u32 *) (orig_p + offset);
7026 i += 2;
7027 }
7028 }
7029}
7030
b6016b76
MC		 7031static void
7032bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7033{
972ec0d4 7034 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7035
f86e82fb 7036 if (bp->flags & BNX2_FLAG_NO_WOL) {
b6016b76
MC		 7037 wol->supported = 0;
7038 wol->wolopts = 0;
7039 }
7040 else {
7041 wol->supported = WAKE_MAGIC;
7042 if (bp->wol)
7043 wol->wolopts = WAKE_MAGIC;
7044 else
7045 wol->wolopts = 0;
7046 }
7047 memset(&wol->sopass, 0, sizeof(wol->sopass));
7048}
7049
7050static int
7051bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7052{
972ec0d4 7053 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7054
7055 if (wol->wolopts & ~WAKE_MAGIC)
7056 return -EINVAL;
7057
7058 if (wol->wolopts & WAKE_MAGIC) {
f86e82fb 7059 if (bp->flags & BNX2_FLAG_NO_WOL)
b6016b76
MC		 7060 return -EINVAL;
7061
7062 bp->wol = 1;
7063 }
7064 else {
7065 bp->wol = 0;
7066 }
6d5e85c7
MC		 7067
7068 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
7069
b6016b76
MC		 7070 return 0;
7071}
7072
7073static int
7074bnx2_nway_reset(struct net_device *dev)
7075{
972ec0d4 7076 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7077 u32 bmcr;
7078
9f52b564
MC		 7079 if (!netif_running(dev))
7080 return -EAGAIN;
7081
b6016b76
MC		 7082 if (!(bp->autoneg & AUTONEG_SPEED)) {
7083 return -EINVAL;
7084 }
7085
c770a65c 7086 spin_lock_bh(&bp->phy_lock);
b6016b76 7087
583c28e5 7088 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
7b6b8347
MC		 7089 int rc;
7090
7091 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
7092 spin_unlock_bh(&bp->phy_lock);
7093 return rc;
7094 }
7095
b6016b76 7096 /* Force a link down visible on the other side */
583c28e5 7097 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
ca58c3af 7098 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
c770a65c 7099 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7100
7101 msleep(20);
7102
c770a65c 7103 spin_lock_bh(&bp->phy_lock);
f8dd064e 7104
40105c0b 7105 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
f8dd064e
MC		 7106 bp->serdes_an_pending = 1;
7107 mod_timer(&bp->timer, jiffies + bp->current_interval);
b6016b76
MC		 7108 }
7109
ca58c3af 7110 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
b6016b76 7111 bmcr &= ~BMCR_LOOPBACK;
ca58c3af 7112 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
b6016b76 7113
c770a65c 7114 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7115
7116 return 0;
7117}
7118
7959ea25
ON		 7119static u32
7120bnx2_get_link(struct net_device *dev)
7121{
7122 struct bnx2 *bp = netdev_priv(dev);
7123
7124 return bp->link_up;
7125}
7126
b6016b76
MC		 7127static int
7128bnx2_get_eeprom_len(struct net_device *dev)
7129{
972ec0d4 7130 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7131
1122db71 7132 if (bp->flash_info == NULL)
b6016b76
MC		 7133 return 0;
7134
1122db71 7135 return (int) bp->flash_size;
b6016b76
MC		 7136}
7137
7138static int
7139bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7140 u8 *eebuf)
7141{
972ec0d4 7142 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7143 int rc;
7144
1064e944 7145 /* parameters already validated in ethtool_get_eeprom */
b6016b76
MC		 7146
7147 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7148
7149 return rc;
7150}
7151
7152static int
7153bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7154 u8 *eebuf)
7155{
972ec0d4 7156 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7157 int rc;
7158
1064e944 7159 /* parameters already validated in ethtool_set_eeprom */
b6016b76
MC		 7160
7161 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7162
7163 return rc;
7164}
7165
7166static int
7167bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7168{
972ec0d4 7169 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7170
7171 memset(coal, 0, sizeof(struct ethtool_coalesce));
7172
7173 coal->rx_coalesce_usecs = bp->rx_ticks;
7174 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7175 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7176 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7177
7178 coal->tx_coalesce_usecs = bp->tx_ticks;
7179 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7180 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7181 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7182
7183 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7184
7185 return 0;
7186}
7187
7188static int
7189bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7190{
972ec0d4 7191 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7192
7193 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7194 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7195
6aa20a22 7196 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
b6016b76
MC		 7197 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7198
7199 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7200 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7201
7202 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7203 if (bp->rx_quick_cons_trip_int > 0xff)
7204 bp->rx_quick_cons_trip_int = 0xff;
7205
7206 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7207 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7208
7209 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7210 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7211
7212 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7213 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7214
7215 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7216 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7217 0xff;
7218
7219 bp->stats_ticks = coal->stats_block_coalesce_usecs;
61d9e3fa 7220 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
02537b06
MC		 7221 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7222 bp->stats_ticks = USEC_PER_SEC;
7223 }
7ea6920e
MC		 7224 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7225 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7226 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76
MC		 7227
7228 if (netif_running(bp->dev)) {
212f9934 7229 bnx2_netif_stop(bp, true);
9a120bc5 7230 bnx2_init_nic(bp, 0);
212f9934 7231 bnx2_netif_start(bp, true);
b6016b76
MC		 7232 }
7233
7234 return 0;
7235}
7236
7237static void
7238bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7239{
972ec0d4 7240 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7241
2bc4078e
MC		 7242 ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT;
7243 ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
b6016b76
MC		 7244
7245 ering->rx_pending = bp->rx_ring_size;
47bf4246 7246 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
b6016b76 7247
2bc4078e 7248 ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT;
b6016b76
MC		 7249 ering->tx_pending = bp->tx_ring_size;
7250}
7251
7252static int
b033281f 7253bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)
b6016b76 7254{
13daffa2 7255 if (netif_running(bp->dev)) {
354fcd77
MC		 7256 /* Reset will erase chipset stats; save them */
7257 bnx2_save_stats(bp);
7258
212f9934 7259 bnx2_netif_stop(bp, true);
13daffa2 7260 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
b033281f
MC		 7261 if (reset_irq) {
7262 bnx2_free_irq(bp);
7263 bnx2_del_napi(bp);
7264 } else {
7265 __bnx2_free_irq(bp);
7266 }
13daffa2
MC		 7267 bnx2_free_skbs(bp);
7268 bnx2_free_mem(bp);
7269 }
7270
5d5d0015
MC		 7271 bnx2_set_rx_ring_size(bp, rx);
7272 bp->tx_ring_size = tx;
b6016b76
MC		 7273
7274 if (netif_running(bp->dev)) {
b033281f
MC		 7275 int rc = 0;
7276
7277 if (reset_irq) {
7278 rc = bnx2_setup_int_mode(bp, disable_msi);
7279 bnx2_init_napi(bp);
7280 }
7281
7282 if (!rc)
7283 rc = bnx2_alloc_mem(bp);
13daffa2 7284
a29ba9d2
MC		 7285 if (!rc)
7286 rc = bnx2_request_irq(bp);
7287
6fefb65e
MC		 7288 if (!rc)
7289 rc = bnx2_init_nic(bp, 0);
7290
7291 if (rc) {
7292 bnx2_napi_enable(bp);
7293 dev_close(bp->dev);
13daffa2 7294 return rc;
6fefb65e 7295 }
e9f26c49
MC		 7296#ifdef BCM_CNIC
7297 mutex_lock(&bp->cnic_lock);
7298 /* Let cnic know about the new status block. */
7299 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7300 bnx2_setup_cnic_irq_info(bp);
7301 mutex_unlock(&bp->cnic_lock);
7302#endif
212f9934 7303 bnx2_netif_start(bp, true);
b6016b76 7304 }
b6016b76
MC		 7305 return 0;
7306}
7307
5d5d0015
MC		 7308static int
7309bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7310{
7311 struct bnx2 *bp = netdev_priv(dev);
7312 int rc;
7313
2bc4078e
MC		 7314 if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) ||
7315 (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) ||
5d5d0015
MC		 7316 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7317
7318 return -EINVAL;
7319 }
b033281f
MC		 7320 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,
7321 false);
5d5d0015
MC		 7322 return rc;
7323}
7324
b6016b76
MC		 7325static void
7326bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7327{
972ec0d4 7328 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7329
7330 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7331 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7332 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7333}
7334
7335static int
7336bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7337{
972ec0d4 7338 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7339
7340 bp->req_flow_ctrl = 0;
7341 if (epause->rx_pause)
7342 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7343 if (epause->tx_pause)
7344 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7345
7346 if (epause->autoneg) {
7347 bp->autoneg |= AUTONEG_FLOW_CTRL;
7348 }
7349 else {
7350 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7351 }
7352
9f52b564
MC		 7353 if (netif_running(dev)) {
7354 spin_lock_bh(&bp->phy_lock);
7355 bnx2_setup_phy(bp, bp->phy_port);
7356 spin_unlock_bh(&bp->phy_lock);
7357 }
b6016b76
MC		 7358
7359 return 0;
7360}
7361
14ab9b86 7362static struct {
b6016b76 7363 char string[ETH_GSTRING_LEN];
790dab2f 7364} bnx2_stats_str_arr[] = {
b6016b76
MC		 7365 { "rx_bytes" },
7366 { "rx_error_bytes" },
7367 { "tx_bytes" },
7368 { "tx_error_bytes" },
7369 { "rx_ucast_packets" },
7370 { "rx_mcast_packets" },
7371 { "rx_bcast_packets" },
7372 { "tx_ucast_packets" },
7373 { "tx_mcast_packets" },
7374 { "tx_bcast_packets" },
7375 { "tx_mac_errors" },
7376 { "tx_carrier_errors" },
7377 { "rx_crc_errors" },
7378 { "rx_align_errors" },
7379 { "tx_single_collisions" },
7380 { "tx_multi_collisions" },
7381 { "tx_deferred" },
7382 { "tx_excess_collisions" },
7383 { "tx_late_collisions" },
7384 { "tx_total_collisions" },
7385 { "rx_fragments" },
7386 { "rx_jabbers" },
7387 { "rx_undersize_packets" },
7388 { "rx_oversize_packets" },
7389 { "rx_64_byte_packets" },
7390 { "rx_65_to_127_byte_packets" },
7391 { "rx_128_to_255_byte_packets" },
7392 { "rx_256_to_511_byte_packets" },
7393 { "rx_512_to_1023_byte_packets" },
7394 { "rx_1024_to_1522_byte_packets" },
7395 { "rx_1523_to_9022_byte_packets" },
7396 { "tx_64_byte_packets" },
7397 { "tx_65_to_127_byte_packets" },
7398 { "tx_128_to_255_byte_packets" },
7399 { "tx_256_to_511_byte_packets" },
7400 { "tx_512_to_1023_byte_packets" },
7401 { "tx_1024_to_1522_byte_packets" },
7402 { "tx_1523_to_9022_byte_packets" },
7403 { "rx_xon_frames" },
7404 { "rx_xoff_frames" },
7405 { "tx_xon_frames" },
7406 { "tx_xoff_frames" },
7407 { "rx_mac_ctrl_frames" },
7408 { "rx_filtered_packets" },
790dab2f 7409 { "rx_ftq_discards" },
b6016b76 7410 { "rx_discards" },
cea94db9 7411 { "rx_fw_discards" },
b6016b76
MC		 7412};
7413
0db83cd8 7414#define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr)
790dab2f 7415
b6016b76
MC		 7416#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7417
f71e1309 7418static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7419 STATS_OFFSET32(stat_IfHCInOctets_hi),
7420 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7421 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7422 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7423 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7424 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7425 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7426 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7427 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7428 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7429 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6aa20a22
JG		 7430 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7431 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7432 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7433 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7434 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7435 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7436 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7437 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7438 STATS_OFFSET32(stat_EtherStatsCollisions),
7439 STATS_OFFSET32(stat_EtherStatsFragments),
7440 STATS_OFFSET32(stat_EtherStatsJabbers),
7441 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7442 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7443 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7444 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7445 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7446 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7447 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7448 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7449 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7450 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7451 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7452 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7453 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7454 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7455 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7456 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7457 STATS_OFFSET32(stat_XonPauseFramesReceived),
7458 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7459 STATS_OFFSET32(stat_OutXonSent),
7460 STATS_OFFSET32(stat_OutXoffSent),
7461 STATS_OFFSET32(stat_MacControlFramesReceived),
7462 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
790dab2f 7463 STATS_OFFSET32(stat_IfInFTQDiscards),
6aa20a22 7464 STATS_OFFSET32(stat_IfInMBUFDiscards),
cea94db9 7465 STATS_OFFSET32(stat_FwRxDrop),
b6016b76
MC		 7466};
7467
7468/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7469 * skipped because of errata.
6aa20a22 7470 */
14ab9b86 7471static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
b6016b76
MC		 7472 8,0,8,8,8,8,8,8,8,8,
7473 4,0,4,4,4,4,4,4,4,4,
7474 4,4,4,4,4,4,4,4,4,4,
7475 4,4,4,4,4,4,4,4,4,4,
790dab2f 7476 4,4,4,4,4,4,4,
b6016b76
MC		 7477};
7478
5b0c76ad
MC		 7479static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7480 8,0,8,8,8,8,8,8,8,8,
7481 4,4,4,4,4,4,4,4,4,4,
7482 4,4,4,4,4,4,4,4,4,4,
7483 4,4,4,4,4,4,4,4,4,4,
790dab2f 7484 4,4,4,4,4,4,4,
5b0c76ad
MC		 7485};
7486
b6016b76
MC		 7487#define BNX2_NUM_TESTS 6
7488
14ab9b86 7489static struct {
b6016b76
MC		 7490 char string[ETH_GSTRING_LEN];
7491} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7492 { "register_test (offline)" },
7493 { "memory_test (offline)" },
7494 { "loopback_test (offline)" },
7495 { "nvram_test (online)" },
7496 { "interrupt_test (online)" },
7497 { "link_test (online)" },
7498};
7499
7500static int
b9f2c044 7501bnx2_get_sset_count(struct net_device *dev, int sset)
b6016b76 7502{
b9f2c044
JG		 7503 switch (sset) {
7504 case ETH_SS_TEST:
7505 return BNX2_NUM_TESTS;
7506 case ETH_SS_STATS:
7507 return BNX2_NUM_STATS;
7508 default:
7509 return -EOPNOTSUPP;
7510 }
b6016b76
MC		 7511}
7512
7513static void
7514bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7515{
972ec0d4 7516 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7517
7518 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7519 if (etest->flags & ETH_TEST_FL_OFFLINE) {
80be4434
MC		 7520 int i;
7521
212f9934 7522 bnx2_netif_stop(bp, true);
b6016b76
MC		 7523 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7524 bnx2_free_skbs(bp);
7525
7526 if (bnx2_test_registers(bp) != 0) {
7527 buf[0] = 1;
7528 etest->flags |= ETH_TEST_FL_FAILED;
7529 }
7530 if (bnx2_test_memory(bp) != 0) {
7531 buf[1] = 1;
7532 etest->flags |= ETH_TEST_FL_FAILED;
7533 }
bc5a0690 7534 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
b6016b76 7535 etest->flags |= ETH_TEST_FL_FAILED;
b6016b76 7536
9f52b564
MC		 7537 if (!netif_running(bp->dev))
7538 bnx2_shutdown_chip(bp);
b6016b76 7539 else {
9a120bc5 7540 bnx2_init_nic(bp, 1);
212f9934 7541 bnx2_netif_start(bp, true);
b6016b76
MC		 7542 }
7543
7544 /* wait for link up */
80be4434
MC		 7545 for (i = 0; i < 7; i++) {
7546 if (bp->link_up)
7547 break;
7548 msleep_interruptible(1000);
7549 }
b6016b76
MC		 7550 }
7551
7552 if (bnx2_test_nvram(bp) != 0) {
7553 buf[3] = 1;
7554 etest->flags |= ETH_TEST_FL_FAILED;
7555 }
7556 if (bnx2_test_intr(bp) != 0) {
7557 buf[4] = 1;
7558 etest->flags |= ETH_TEST_FL_FAILED;
7559 }
7560
7561 if (bnx2_test_link(bp) != 0) {
7562 buf[5] = 1;
7563 etest->flags |= ETH_TEST_FL_FAILED;
7564
7565 }
7566}
7567
7568static void
7569bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7570{
7571 switch (stringset) {
7572 case ETH_SS_STATS:
7573 memcpy(buf, bnx2_stats_str_arr,
7574 sizeof(bnx2_stats_str_arr));
7575 break;
7576 case ETH_SS_TEST:
7577 memcpy(buf, bnx2_tests_str_arr,
7578 sizeof(bnx2_tests_str_arr));
7579 break;
7580 }
7581}
7582
b6016b76
MC		 7583static void
7584bnx2_get_ethtool_stats(struct net_device *dev,
7585 struct ethtool_stats *stats, u64 *buf)
7586{
972ec0d4 7587 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7588 int i;
7589 u32 *hw_stats = (u32 *) bp->stats_blk;
354fcd77 7590 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
14ab9b86 7591 u8 *stats_len_arr = NULL;
b6016b76
MC		 7592
7593 if (hw_stats == NULL) {
7594 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7595 return;
7596 }
7597
4ce45e02
MC		 7598 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
7599 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||
7600 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||
7601 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
b6016b76 7602 stats_len_arr = bnx2_5706_stats_len_arr;
5b0c76ad
MC		 7603 else
7604 stats_len_arr = bnx2_5708_stats_len_arr;
b6016b76
MC		 7605
7606 for (i = 0; i < BNX2_NUM_STATS; i++) {
354fcd77
MC		 7607 unsigned long offset;
7608
b6016b76
MC		 7609 if (stats_len_arr[i] == 0) {
7610 /* skip this counter */
7611 buf[i] = 0;
7612 continue;
7613 }
354fcd77
MC		 7614
7615 offset = bnx2_stats_offset_arr[i];
b6016b76
MC		 7616 if (stats_len_arr[i] == 4) {
7617 /* 4-byte counter */
354fcd77
MC		 7618 buf[i] = (u64) *(hw_stats + offset) +
7619 *(temp_stats + offset);
b6016b76
MC		 7620 continue;
7621 }
7622 /* 8-byte counter */
354fcd77
MC		 7623 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7624 *(hw_stats + offset + 1) +
7625 (((u64) *(temp_stats + offset)) << 32) +
7626 *(temp_stats + offset + 1);
b6016b76
MC		 7627 }
7628}
7629
7630static int
2e17e1aa 7631bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
b6016b76 7632{
972ec0d4 7633 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7634
2e17e1aa 7635 switch (state) {
7636 case ETHTOOL_ID_ACTIVE:
e503e066
MC		 7637 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
7638 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
fce55922 7639 return 1; /* cycle on/off once per second */
b6016b76 7640
2e17e1aa 7641 case ETHTOOL_ID_ON:
e503e066
MC		 7642 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7643 BNX2_EMAC_LED_1000MB_OVERRIDE |
7644 BNX2_EMAC_LED_100MB_OVERRIDE |
7645 BNX2_EMAC_LED_10MB_OVERRIDE |
7646 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7647 BNX2_EMAC_LED_TRAFFIC);
2e17e1aa 7648 break;
b6016b76 7649
2e17e1aa 7650 case ETHTOOL_ID_OFF:
e503e066 7651 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
2e17e1aa 7652 break;
9f52b564 7653
2e17e1aa 7654 case ETHTOOL_ID_INACTIVE:
e503e066
MC		 7655 BNX2_WR(bp, BNX2_EMAC_LED, 0);
7656 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
2e17e1aa 7657 break;
7658 }
9f52b564 7659
b6016b76
MC		 7660 return 0;
7661}
7662
c8f44aff
MM		 7663static netdev_features_t
7664bnx2_fix_features(struct net_device *dev, netdev_features_t features)
4666f87a
MC		 7665{
7666 struct bnx2 *bp = netdev_priv(dev);
7667
8d7dfc2b 7668 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
f646968f 7669 features |= NETIF_F_HW_VLAN_CTAG_RX;
8d7dfc2b
MM		 7670
7671 return features;
4666f87a
MC		 7672}
7673
fdc8541d 7674static int
c8f44aff 7675bnx2_set_features(struct net_device *dev, netdev_features_t features)
fdc8541d 7676{
7d0fd211 7677 struct bnx2 *bp = netdev_priv(dev);
7d0fd211 7678
7c810477 7679 /* TSO with VLAN tag won't work with current firmware */
f646968f 7680 if (features & NETIF_F_HW_VLAN_CTAG_TX)
8d7dfc2b
MM		 7681 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7682 else
7683 dev->vlan_features &= ~NETIF_F_ALL_TSO;
7d0fd211 7684
f646968f 7685 if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) !=
7d0fd211
JG		 7686 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7687 netif_running(dev)) {
7688 bnx2_netif_stop(bp, false);
8d7dfc2b 7689 dev->features = features;
7d0fd211
JG		 7690 bnx2_set_rx_mode(dev);
7691 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7692 bnx2_netif_start(bp, false);
8d7dfc2b 7693 return 1;
7d0fd211
JG		 7694 }
7695
7696 return 0;
fdc8541d
MC		 7697}
7698
b033281f
MC		 7699static void bnx2_get_channels(struct net_device *dev,
7700 struct ethtool_channels *channels)
7701{
7702 struct bnx2 *bp = netdev_priv(dev);
7703 u32 max_rx_rings = 1;
7704 u32 max_tx_rings = 1;
7705
7706 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7707 max_rx_rings = RX_MAX_RINGS;
7708 max_tx_rings = TX_MAX_RINGS;
7709 }
7710
7711 channels->max_rx = max_rx_rings;
7712 channels->max_tx = max_tx_rings;
7713 channels->max_other = 0;
7714 channels->max_combined = 0;
7715 channels->rx_count = bp->num_rx_rings;
7716 channels->tx_count = bp->num_tx_rings;
7717 channels->other_count = 0;
7718 channels->combined_count = 0;
7719}
7720
7721static int bnx2_set_channels(struct net_device *dev,
7722 struct ethtool_channels *channels)
7723{
7724 struct bnx2 *bp = netdev_priv(dev);
7725 u32 max_rx_rings = 1;
7726 u32 max_tx_rings = 1;
7727 int rc = 0;
7728
7729 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7730 max_rx_rings = RX_MAX_RINGS;
7731 max_tx_rings = TX_MAX_RINGS;
7732 }
7733 if (channels->rx_count > max_rx_rings ||
7734 channels->tx_count > max_tx_rings)
7735 return -EINVAL;
7736
7737 bp->num_req_rx_rings = channels->rx_count;
7738 bp->num_req_tx_rings = channels->tx_count;
7739
7740 if (netif_running(dev))
7741 rc = bnx2_change_ring_size(bp, bp->rx_ring_size,
7742 bp->tx_ring_size, true);
7743
7744 return rc;
7745}
7746
7282d491 7747static const struct ethtool_ops bnx2_ethtool_ops = {
b6016b76
MC		 7748 .get_settings = bnx2_get_settings,
7749 .set_settings = bnx2_set_settings,
7750 .get_drvinfo = bnx2_get_drvinfo,
244ac4f4
MC		 7751 .get_regs_len = bnx2_get_regs_len,
7752 .get_regs = bnx2_get_regs,
b6016b76
MC		 7753 .get_wol = bnx2_get_wol,
7754 .set_wol = bnx2_set_wol,
7755 .nway_reset = bnx2_nway_reset,
7959ea25 7756 .get_link = bnx2_get_link,
b6016b76
MC		 7757 .get_eeprom_len = bnx2_get_eeprom_len,
7758 .get_eeprom = bnx2_get_eeprom,
7759 .set_eeprom = bnx2_set_eeprom,
7760 .get_coalesce = bnx2_get_coalesce,
7761 .set_coalesce = bnx2_set_coalesce,
7762 .get_ringparam = bnx2_get_ringparam,
7763 .set_ringparam = bnx2_set_ringparam,
7764 .get_pauseparam = bnx2_get_pauseparam,
7765 .set_pauseparam = bnx2_set_pauseparam,
b6016b76
MC		 7766 .self_test = bnx2_self_test,
7767 .get_strings = bnx2_get_strings,
2e17e1aa 7768 .set_phys_id = bnx2_set_phys_id,
b6016b76 7769 .get_ethtool_stats = bnx2_get_ethtool_stats,
b9f2c044 7770 .get_sset_count = bnx2_get_sset_count,
b033281f
MC		 7771 .get_channels = bnx2_get_channels,
7772 .set_channels = bnx2_set_channels,
b6016b76
MC		 7773};
7774
7775/* Called with rtnl_lock */
7776static int
7777bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7778{
14ab9b86 7779 struct mii_ioctl_data *data = if_mii(ifr);
972ec0d4 7780 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7781 int err;
7782
7783 switch(cmd) {
7784 case SIOCGMIIPHY:
7785 data->phy_id = bp->phy_addr;
7786
7787 /* fallthru */
7788 case SIOCGMIIREG: {
7789 u32 mii_regval;
7790
583c28e5 7791 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7792 return -EOPNOTSUPP;
7793
dad3e452
MC		 7794 if (!netif_running(dev))
7795 return -EAGAIN;
7796
c770a65c 7797 spin_lock_bh(&bp->phy_lock);
b6016b76 7798 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
c770a65c 7799 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7800
7801 data->val_out = mii_regval;
7802
7803 return err;
7804 }
7805
7806 case SIOCSMIIREG:
583c28e5 7807 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7b6b8347
MC		 7808 return -EOPNOTSUPP;
7809
dad3e452
MC		 7810 if (!netif_running(dev))
7811 return -EAGAIN;
7812
c770a65c 7813 spin_lock_bh(&bp->phy_lock);
b6016b76 7814 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
c770a65c 7815 spin_unlock_bh(&bp->phy_lock);
b6016b76
MC		 7816
7817 return err;
7818
7819 default:
7820 /* do nothing */
7821 break;
7822 }
7823 return -EOPNOTSUPP;
7824}
7825
7826/* Called with rtnl_lock */
7827static int
7828bnx2_change_mac_addr(struct net_device *dev, void *p)
7829{
7830 struct sockaddr *addr = p;
972ec0d4 7831 struct bnx2 *bp = netdev_priv(dev);
b6016b76 7832
73eef4cd 7833 if (!is_valid_ether_addr(addr->sa_data))
504f9b5a 7834 return -EADDRNOTAVAIL;
73eef4cd 7835
b6016b76
MC		 7836 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7837 if (netif_running(dev))
5fcaed01 7838 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
b6016b76
MC		 7839
7840 return 0;
7841}
7842
7843/* Called with rtnl_lock */
7844static int
7845bnx2_change_mtu(struct net_device *dev, int new_mtu)
7846{
972ec0d4 7847 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 7848
7849 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7850 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7851 return -EINVAL;
7852
7853 dev->mtu = new_mtu;
b033281f
MC		 7854 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
7855 false);
b6016b76
MC		 7856}
7857
257ddbda 7858#ifdef CONFIG_NET_POLL_CONTROLLER
b6016b76
MC		 7859static void
7860poll_bnx2(struct net_device *dev)
7861{
972ec0d4 7862 struct bnx2 *bp = netdev_priv(dev);
b2af2c1d 7863 int i;
b6016b76 7864
b2af2c1d 7865 for (i = 0; i < bp->irq_nvecs; i++) {
1bf1e347
MC		 7866 struct bnx2_irq *irq = &bp->irq_tbl[i];
7867
7868 disable_irq(irq->vector);
7869 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7870 enable_irq(irq->vector);
b2af2c1d 7871 }
b6016b76
MC		 7872}
7873#endif
7874
cfd95a63 7875static void
253c8b75
MC		 7876bnx2_get_5709_media(struct bnx2 *bp)
7877{
e503e066 7878 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
253c8b75
MC		 7879 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7880 u32 strap;
7881
7882 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7883 return;
7884 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
583c28e5 7885 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7886 return;
7887 }
7888
7889 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7890 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7891 else
7892 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7893
aefd90e4 7894 if (bp->func == 0) {
253c8b75
MC		 7895 switch (strap) {
7896 case 0x4:
7897 case 0x5:
7898 case 0x6:
583c28e5 7899 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7900 return;
7901 }
7902 } else {
7903 switch (strap) {
7904 case 0x1:
7905 case 0x2:
7906 case 0x4:
583c28e5 7907 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
253c8b75
MC		 7908 return;
7909 }
7910 }
7911}
7912
cfd95a63 7913static void
883e5151
MC		 7914bnx2_get_pci_speed(struct bnx2 *bp)
7915{
7916 u32 reg;
7917
e503e066 7918 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
883e5151
MC		 7919 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7920 u32 clkreg;
7921
f86e82fb 7922 bp->flags |= BNX2_FLAG_PCIX;
883e5151 7923
e503e066 7924 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
883e5151
MC		 7925
7926 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7927 switch (clkreg) {
7928 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7929 bp->bus_speed_mhz = 133;
7930 break;
7931
7932 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7933 bp->bus_speed_mhz = 100;
7934 break;
7935
7936 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7937 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7938 bp->bus_speed_mhz = 66;
7939 break;
7940
7941 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7942 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7943 bp->bus_speed_mhz = 50;
7944 break;
7945
7946 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7947 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7948 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7949 bp->bus_speed_mhz = 33;
7950 break;
7951 }
7952 }
7953 else {
7954 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7955 bp->bus_speed_mhz = 66;
7956 else
7957 bp->bus_speed_mhz = 33;
7958 }
7959
7960 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
f86e82fb 7961 bp->flags |= BNX2_FLAG_PCI_32BIT;
883e5151
MC		 7962
7963}
7964
cfd95a63 7965static void
76d99061
MC		 7966bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7967{
df25bc38 7968 int rc, i, j;
76d99061 7969 u8 *data;
df25bc38 7970 unsigned int block_end, rosize, len;
76d99061 7971
012093f6
MC		 7972#define BNX2_VPD_NVRAM_OFFSET 0x300
7973#define BNX2_VPD_LEN 128
76d99061
MC		 7974#define BNX2_MAX_VER_SLEN 30
7975
7976 data = kmalloc(256, GFP_KERNEL);
7977 if (!data)
7978 return;
7979
012093f6
MC		 7980 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7981 BNX2_VPD_LEN);
76d99061
MC		 7982 if (rc)
7983 goto vpd_done;
7984
012093f6
MC		 7985 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7986 data[i] = data[i + BNX2_VPD_LEN + 3];
7987 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7988 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7989 data[i + 3] = data[i + BNX2_VPD_LEN];
76d99061
MC		 7990 }
7991
df25bc38
MC		 7992 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7993 if (i < 0)
7994 goto vpd_done;
76d99061 7995
df25bc38
MC		 7996 rosize = pci_vpd_lrdt_size(&data[i]);
7997 i += PCI_VPD_LRDT_TAG_SIZE;
7998 block_end = i + rosize;
76d99061 7999
df25bc38
MC		 8000 if (block_end > BNX2_VPD_LEN)
8001 goto vpd_done;
76d99061 8002
df25bc38
MC		 8003 j = pci_vpd_find_info_keyword(data, i, rosize,
8004 PCI_VPD_RO_KEYWORD_MFR_ID);
8005 if (j < 0)
8006 goto vpd_done;
76d99061 8007
df25bc38 8008 len = pci_vpd_info_field_size(&data[j]);
76d99061 8009
df25bc38
MC		 8010 j += PCI_VPD_INFO_FLD_HDR_SIZE;
8011 if (j + len > block_end || len != 4 ||
8012 memcmp(&data[j], "1028", 4))
8013 goto vpd_done;
4067a854 8014
df25bc38
MC		 8015 j = pci_vpd_find_info_keyword(data, i, rosize,
8016 PCI_VPD_RO_KEYWORD_VENDOR0);
8017 if (j < 0)
8018 goto vpd_done;
4067a854 8019
df25bc38 8020 len = pci_vpd_info_field_size(&data[j]);
4067a854 8021
df25bc38
MC		 8022 j += PCI_VPD_INFO_FLD_HDR_SIZE;
8023 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
76d99061 8024 goto vpd_done;
df25bc38
MC		 8025
8026 memcpy(bp->fw_version, &data[j], len);
8027 bp->fw_version[len] = ' ';
76d99061
MC		 8028
8029vpd_done:
8030 kfree(data);
8031}
8032
cfd95a63 8033static int
b6016b76
MC		 8034bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
8035{
8036 struct bnx2 *bp;
58fc2ea4 8037 int rc, i, j;
b6016b76 8038 u32 reg;
40453c83 8039 u64 dma_mask, persist_dma_mask;
cd709aa9 8040 int err;
b6016b76 8041
b6016b76 8042 SET_NETDEV_DEV(dev, &pdev->dev);
972ec0d4 8043 bp = netdev_priv(dev);
b6016b76
MC		 8044
8045 bp->flags = 0;
8046 bp->phy_flags = 0;
8047
354fcd77
MC		 8048 bp->temp_stats_blk =
8049 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
8050
8051 if (bp->temp_stats_blk == NULL) {
8052 rc = -ENOMEM;
8053 goto err_out;
8054 }
8055
b6016b76
MC		 8056 /* enable device (incl. PCI PM wakeup), and bus-mastering */
8057 rc = pci_enable_device(pdev);
8058 if (rc) {
3a9c6a49 8059 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
b6016b76
MC		 8060 goto err_out;
8061 }
8062
8063 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9b91cf9d 8064 dev_err(&pdev->dev,
3a9c6a49 8065 "Cannot find PCI device base address, aborting\n");
b6016b76
MC		 8066 rc = -ENODEV;
8067 goto err_out_disable;
8068 }
8069
8070 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8071 if (rc) {
3a9c6a49 8072 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
b6016b76
MC		 8073 goto err_out_disable;
8074 }
8075
8076 pci_set_master(pdev);
8077
85768271 8078 bp->pm_cap = pdev->pm_cap;
b6016b76 8079 if (bp->pm_cap == 0) {
9b91cf9d 8080 dev_err(&pdev->dev,
3a9c6a49 8081 "Cannot find power management capability, aborting\n");
b6016b76
MC		 8082 rc = -EIO;
8083 goto err_out_release;
8084 }
8085
b6016b76
MC		 8086 bp->dev = dev;
8087 bp->pdev = pdev;
8088
8089 spin_lock_init(&bp->phy_lock);
1b8227c4 8090 spin_lock_init(&bp->indirect_lock);
c5a88950
MC		 8091#ifdef BCM_CNIC
8092 mutex_init(&bp->cnic_lock);
8093#endif
c4028958 8094 INIT_WORK(&bp->reset_task, bnx2_reset_task);
b6016b76 8095
c0357e97
FR		 8096 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +
8097 TX_MAX_TSS_RINGS + 1));
b6016b76 8098 if (!bp->regview) {
3a9c6a49 8099 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
b6016b76
MC		 8100 rc = -ENOMEM;
8101 goto err_out_release;
8102 }
8103
8104 /* Configure byte swap and enable write to the reg_window registers.
8105 * Rely on CPU to do target byte swapping on big endian systems
8106 * The chip's target access swapping will not swap all accesses
8107 */
e503e066
MC		 8108 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
8109 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
8110 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
b6016b76 8111
e503e066 8112 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
b6016b76 8113
4ce45e02 8114 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
e82760e7
JM		 8115 if (!pci_is_pcie(pdev)) {
8116 dev_err(&pdev->dev, "Not PCIE, aborting\n");
883e5151
MC		 8117 rc = -EIO;
8118 goto err_out_unmap;
8119 }
f86e82fb 8120 bp->flags |= BNX2_FLAG_PCIE;
4ce45e02 8121 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
f86e82fb 8122 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
c239f279
MC		 8123
8124 /* AER (Advanced Error Reporting) hooks */
8125 err = pci_enable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8126 if (!err)
8127 bp->flags |= BNX2_FLAG_AER_ENABLED;
c239f279 8128
883e5151 8129 } else {
59b47d8a
MC		 8130 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
8131 if (bp->pcix_cap == 0) {
8132 dev_err(&pdev->dev,
3a9c6a49 8133 "Cannot find PCIX capability, aborting\n");
59b47d8a
MC		 8134 rc = -EIO;
8135 goto err_out_unmap;
8136 }
61d9e3fa 8137 bp->flags |= BNX2_FLAG_BROKEN_STATS;
59b47d8a
MC		 8138 }
8139
4ce45e02
MC		 8140 if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8141 BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {
555a8428 8142 if (pdev->msix_cap)
f86e82fb 8143 bp->flags |= BNX2_FLAG_MSIX_CAP;
b4b36042
MC		 8144 }
8145
4ce45e02
MC		 8146 if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&
8147 BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {
555a8428 8148 if (pdev->msi_cap)
f86e82fb 8149 bp->flags |= BNX2_FLAG_MSI_CAP;
8e6a72c4
MC		 8150 }
8151
40453c83 8152 /* 5708 cannot support DMA addresses > 40-bit. */
4ce45e02 8153 if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
50cf156a 8154 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
40453c83 8155 else
6a35528a 8156 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
40453c83
MC		 8157
8158 /* Configure DMA attributes. */
8159 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8160 dev->features |= NETIF_F_HIGHDMA;
8161 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8162 if (rc) {
8163 dev_err(&pdev->dev,
3a9c6a49 8164 "pci_set_consistent_dma_mask failed, aborting\n");
40453c83
MC		 8165 goto err_out_unmap;
8166 }
284901a9 8167 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
3a9c6a49 8168 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
40453c83
MC		 8169 goto err_out_unmap;
8170 }
8171
f86e82fb 8172 if (!(bp->flags & BNX2_FLAG_PCIE))
883e5151 8173 bnx2_get_pci_speed(bp);
b6016b76
MC		 8174
8175 /* 5706A0 may falsely detect SERR and PERR. */
4ce45e02 8176 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
e503e066 8177 reg = BNX2_RD(bp, PCI_COMMAND);
b6016b76 8178 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
e503e066 8179 BNX2_WR(bp, PCI_COMMAND, reg);
4ce45e02 8180 } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&
f86e82fb 8181 !(bp->flags & BNX2_FLAG_PCIX)) {
b6016b76 8182
9b91cf9d 8183 dev_err(&pdev->dev,
3a9c6a49 8184 "5706 A1 can only be used in a PCIX bus, aborting\n");
b6016b76
MC		 8185 goto err_out_unmap;
8186 }
8187
8188 bnx2_init_nvram(bp);
8189
2726d6e1 8190 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
e3648b3d 8191
aefd90e4
MC		 8192 if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)
8193 bp->func = 1;
8194
e3648b3d 8195 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
24cb230b 8196 BNX2_SHM_HDR_SIGNATURE_SIG) {
aefd90e4 8197 u32 off = bp->func << 2;
24cb230b 8198
2726d6e1 8199 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
24cb230b 8200 } else
e3648b3d
MC		 8201 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8202
b6016b76
MC		 8203 /* Get the permanent MAC address. First we need to make sure the
8204 * firmware is actually running.
8205 */
2726d6e1 8206 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
b6016b76
MC		 8207
8208 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8209 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
3a9c6a49 8210 dev_err(&pdev->dev, "Firmware not running, aborting\n");
b6016b76
MC		 8211 rc = -ENODEV;
8212 goto err_out_unmap;
8213 }
8214
76d99061
MC		 8215 bnx2_read_vpd_fw_ver(bp);
8216
8217 j = strlen(bp->fw_version);
2726d6e1 8218 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
76d99061 8219 for (i = 0; i < 3 && j < 24; i++) {
58fc2ea4
MC		 8220 u8 num, k, skip0;
8221
76d99061
MC		 8222 if (i == 0) {
8223 bp->fw_version[j++] = 'b';
8224 bp->fw_version[j++] = 'c';
8225 bp->fw_version[j++] = ' ';
8226 }
58fc2ea4
MC		 8227 num = (u8) (reg >> (24 - (i * 8)));
8228 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8229 if (num >= k || !skip0 || k == 1) {
8230 bp->fw_version[j++] = (num / k) + '0';
8231 skip0 = 0;
8232 }
8233 }
8234 if (i != 2)
8235 bp->fw_version[j++] = '.';
8236 }
2726d6e1 8237 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
846f5c62
MC		 8238 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8239 bp->wol = 1;
8240
8241 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
f86e82fb 8242 bp->flags |= BNX2_FLAG_ASF_ENABLE;
c2d3db8c
MC		 8243
8244 for (i = 0; i < 30; i++) {
2726d6e1 8245 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
c2d3db8c
MC		 8246 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8247 break;
8248 msleep(10);
8249 }
8250 }
2726d6e1 8251 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
58fc2ea4
MC		 8252 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8253 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8254 reg != BNX2_CONDITION_MFW_RUN_NONE) {
2726d6e1 8255 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
58fc2ea4 8256
76d99061
MC		 8257 if (j < 32)
8258 bp->fw_version[j++] = ' ';
8259 for (i = 0; i < 3 && j < 28; i++) {
2726d6e1 8260 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
3aeb7d22 8261 reg = be32_to_cpu(reg);
58fc2ea4
MC		 8262 memcpy(&bp->fw_version[j], &reg, 4);
8263 j += 4;
8264 }
8265 }
b6016b76 8266
2726d6e1 8267 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
b6016b76
MC		 8268 bp->mac_addr[0] = (u8) (reg >> 8);
8269 bp->mac_addr[1] = (u8) reg;
8270
2726d6e1 8271 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
b6016b76
MC		 8272 bp->mac_addr[2] = (u8) (reg >> 24);
8273 bp->mac_addr[3] = (u8) (reg >> 16);
8274 bp->mac_addr[4] = (u8) (reg >> 8);
8275 bp->mac_addr[5] = (u8) reg;
8276
2bc4078e 8277 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;
932f3772 8278 bnx2_set_rx_ring_size(bp, 255);
b6016b76 8279
cf7474a6 8280 bp->tx_quick_cons_trip_int = 2;
b6016b76 8281 bp->tx_quick_cons_trip = 20;
cf7474a6 8282 bp->tx_ticks_int = 18;
b6016b76 8283 bp->tx_ticks = 80;
6aa20a22 8284
cf7474a6
MC		 8285 bp->rx_quick_cons_trip_int = 2;
8286 bp->rx_quick_cons_trip = 12;
b6016b76
MC		 8287 bp->rx_ticks_int = 18;
8288 bp->rx_ticks = 18;
8289
7ea6920e 8290 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
b6016b76 8291
ac392abc 8292 bp->current_interval = BNX2_TIMER_INTERVAL;
b6016b76 8293
5b0c76ad
MC		 8294 bp->phy_addr = 1;
8295
b6016b76 8296 /* Disable WOL support if we are running on a SERDES chip. */
4ce45e02 8297 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
253c8b75 8298 bnx2_get_5709_media(bp);
4ce45e02 8299 else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)
583c28e5 8300 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
bac0dff6 8301
0d8a6571 8302 bp->phy_port = PORT_TP;
583c28e5 8303 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
0d8a6571 8304 bp->phy_port = PORT_FIBRE;
2726d6e1 8305 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
846f5c62 8306 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
f86e82fb 8307 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8308 bp->wol = 0;
8309 }
4ce45e02 8310 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {
38ea3686
MC		 8311 /* Don't do parallel detect on this board because of
8312 * some board problems. The link will not go down
8313 * if we do parallel detect.
8314 */
8315 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8316 pdev->subsystem_device == 0x310c)
8317 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8318 } else {
5b0c76ad 8319 bp->phy_addr = 2;
5b0c76ad 8320 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
583c28e5 8321 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
5b0c76ad 8322 }
4ce45e02
MC		 8323 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||
8324 BNX2_CHIP(bp) == BNX2_CHIP_5708)
583c28e5 8325 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
4ce45e02
MC		 8326 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8327 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||
8328 BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))
583c28e5 8329 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
b6016b76 8330
7c62e83b
MC		 8331 bnx2_init_fw_cap(bp);
8332
4ce45e02
MC		 8333 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
8334 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
8335 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||
e503e066 8336 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
f86e82fb 8337 bp->flags |= BNX2_FLAG_NO_WOL;
846f5c62
MC		 8338 bp->wol = 0;
8339 }
dda1e390 8340
6d5e85c7
MC		 8341 if (bp->flags & BNX2_FLAG_NO_WOL)
8342 device_set_wakeup_capable(&bp->pdev->dev, false);
8343 else
8344 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
8345
4ce45e02 8346 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
b6016b76
MC		 8347 bp->tx_quick_cons_trip_int =
8348 bp->tx_quick_cons_trip;
8349 bp->tx_ticks_int = bp->tx_ticks;
8350 bp->rx_quick_cons_trip_int =
8351 bp->rx_quick_cons_trip;
8352 bp->rx_ticks_int = bp->rx_ticks;
8353 bp->comp_prod_trip_int = bp->comp_prod_trip;
8354 bp->com_ticks_int = bp->com_ticks;
8355 bp->cmd_ticks_int = bp->cmd_ticks;
8356 }
8357
f9317a40
MC		 8358 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8359 *
8360 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8361 * with byte enables disabled on the unused 32-bit word. This is legal
8362 * but causes problems on the AMD 8132 which will eventually stop
8363 * responding after a while.
8364 *
8365 * AMD believes this incompatibility is unique to the 5706, and
88187dfa 8366 * prefers to locally disable MSI rather than globally disabling it.
f9317a40 8367 */
4ce45e02 8368 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {
f9317a40
MC		 8369 struct pci_dev *amd_8132 = NULL;
8370
8371 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8372 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8373 amd_8132))) {
f9317a40 8374
44c10138
AK		 8375 if (amd_8132->revision >= 0x10 &&
8376 amd_8132->revision <= 0x13) {
f9317a40
MC		 8377 disable_msi = 1;
8378 pci_dev_put(amd_8132);
8379 break;
8380 }
8381 }
8382 }
8383
deaf391b 8384 bnx2_set_default_link(bp);
b6016b76
MC		 8385 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8386
cd339a0e 8387 init_timer(&bp->timer);
ac392abc 8388 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
cd339a0e
MC		 8389 bp->timer.data = (unsigned long) bp;
8390 bp->timer.function = bnx2_timer;
8391
7625eb2f 8392#ifdef BCM_CNIC
41c2178a
MC		 8393 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8394 bp->cnic_eth_dev.max_iscsi_conn =
8395 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8396 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
4bd9b0ff 8397 bp->cnic_probe = bnx2_cnic_probe;
7625eb2f 8398#endif
c239f279
MC		 8399 pci_save_state(pdev);
8400
b6016b76
MC		 8401 return 0;
8402
8403err_out_unmap:
4bb9ebc7 8404 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8405 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8406 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8407 }
c239f279 8408
c0357e97
FR		 8409 pci_iounmap(pdev, bp->regview);
8410 bp->regview = NULL;
b6016b76
MC		 8411
8412err_out_release:
8413 pci_release_regions(pdev);
8414
8415err_out_disable:
8416 pci_disable_device(pdev);
b6016b76
MC		 8417
8418err_out:
8419 return rc;
8420}
8421
cfd95a63 8422static char *
883e5151
MC		 8423bnx2_bus_string(struct bnx2 *bp, char *str)
8424{
8425 char *s = str;
8426
f86e82fb 8427 if (bp->flags & BNX2_FLAG_PCIE) {
883e5151
MC		 8428 s += sprintf(s, "PCI Express");
8429 } else {
8430 s += sprintf(s, "PCI");
f86e82fb 8431 if (bp->flags & BNX2_FLAG_PCIX)
883e5151 8432 s += sprintf(s, "-X");
f86e82fb 8433 if (bp->flags & BNX2_FLAG_PCI_32BIT)
883e5151
MC		 8434 s += sprintf(s, " 32-bit");
8435 else
8436 s += sprintf(s, " 64-bit");
8437 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8438 }
8439 return str;
8440}
8441
f048fa9c
MC		 8442static void
8443bnx2_del_napi(struct bnx2 *bp)
8444{
8445 int i;
8446
8447 for (i = 0; i < bp->irq_nvecs; i++)
8448 netif_napi_del(&bp->bnx2_napi[i].napi);
8449}
8450
8451static void
35efa7c1
MC		 8452bnx2_init_napi(struct bnx2 *bp)
8453{
b4b36042 8454 int i;
35efa7c1 8455
4327ba43 8456 for (i = 0; i < bp->irq_nvecs; i++) {
35e9010b
MC		 8457 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8458 int (*poll)(struct napi_struct *, int);
8459
8460 if (i == 0)
8461 poll = bnx2_poll;
8462 else
f0ea2e63 8463 poll = bnx2_poll_msix;
35e9010b
MC		 8464
8465 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
b4b36042
MC		 8466 bnapi->bp = bp;
8467 }
35efa7c1
MC		 8468}
8469
0421eae6
SH		 8470static const struct net_device_ops bnx2_netdev_ops = {
8471 .ndo_open = bnx2_open,
8472 .ndo_start_xmit = bnx2_start_xmit,
8473 .ndo_stop = bnx2_close,
5d07bf26 8474 .ndo_get_stats64 = bnx2_get_stats64,
0421eae6
SH		 8475 .ndo_set_rx_mode = bnx2_set_rx_mode,
8476 .ndo_do_ioctl = bnx2_ioctl,
8477 .ndo_validate_addr = eth_validate_addr,
8478 .ndo_set_mac_address = bnx2_change_mac_addr,
8479 .ndo_change_mtu = bnx2_change_mtu,
8d7dfc2b
MM		 8480 .ndo_fix_features = bnx2_fix_features,
8481 .ndo_set_features = bnx2_set_features,
0421eae6 8482 .ndo_tx_timeout = bnx2_tx_timeout,
257ddbda 8483#ifdef CONFIG_NET_POLL_CONTROLLER
0421eae6
SH		 8484 .ndo_poll_controller = poll_bnx2,
8485#endif
8486};
8487
cfd95a63 8488static int
b6016b76
MC		 8489bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8490{
8491 static int version_printed = 0;
c0357e97 8492 struct net_device *dev;
b6016b76 8493 struct bnx2 *bp;
0795af57 8494 int rc;
883e5151 8495 char str[40];
b6016b76
MC		 8496
8497 if (version_printed++ == 0)
3a9c6a49 8498 pr_info("%s", version);
b6016b76
MC		 8499
8500 /* dev zeroed in init_etherdev */
706bf240 8501 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
b6016b76
MC		 8502 if (!dev)
8503 return -ENOMEM;
8504
8505 rc = bnx2_init_board(pdev, dev);
c0357e97
FR		 8506 if (rc < 0)
8507 goto err_free;
b6016b76 8508
0421eae6 8509 dev->netdev_ops = &bnx2_netdev_ops;
b6016b76 8510 dev->watchdog_timeo = TX_TIMEOUT;
b6016b76 8511 dev->ethtool_ops = &bnx2_ethtool_ops;
b6016b76 8512
972ec0d4 8513 bp = netdev_priv(dev);
b6016b76 8514
1b2f922f
MC		 8515 pci_set_drvdata(pdev, dev);
8516
d458cdf7 8517 memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN);
1b2f922f 8518
8d7dfc2b
MM		 8519 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8520 NETIF_F_TSO | NETIF_F_TSO_ECN |
8521 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8522
4ce45e02 8523 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
8d7dfc2b
MM		 8524 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8525
8526 dev->vlan_features = dev->hw_features;
f646968f 8527 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8d7dfc2b 8528 dev->features |= dev->hw_features;
01789349 8529 dev->priv_flags |= IFF_UNICAST_FLT;
8d7dfc2b 8530
b6016b76 8531 if ((rc = register_netdev(dev))) {
9b91cf9d 8532 dev_err(&pdev->dev, "Cannot register net device\n");
57579f76 8533 goto error;
b6016b76
MC		 8534 }
8535
c0357e97
FR		 8536 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, "
8537 "node addr %pM\n", board_info[ent->driver_data].name,
4ce45e02
MC		 8538 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8539 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),
c0357e97
FR		 8540 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),
8541 pdev->irq, dev->dev_addr);
b6016b76 8542
b6016b76 8543 return 0;
57579f76
MC		 8544
8545error:
fda4d85d 8546 pci_iounmap(pdev, bp->regview);
57579f76
MC		 8547 pci_release_regions(pdev);
8548 pci_disable_device(pdev);
c0357e97 8549err_free:
57579f76
MC		 8550 free_netdev(dev);
8551 return rc;
b6016b76
MC		 8552}
8553
cfd95a63 8554static void
b6016b76
MC		 8555bnx2_remove_one(struct pci_dev *pdev)
8556{
8557 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8558 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8559
8560 unregister_netdev(dev);
8561
8333a46a 8562 del_timer_sync(&bp->timer);
cd634019 8563 cancel_work_sync(&bp->reset_task);
8333a46a 8564
c0357e97 8565 pci_iounmap(bp->pdev, bp->regview);
b6016b76 8566
354fcd77
MC		 8567 kfree(bp->temp_stats_blk);
8568
4bb9ebc7 8569 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
c239f279 8570 pci_disable_pcie_error_reporting(pdev);
4bb9ebc7
MC		 8571 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8572 }
cd709aa9 8573
7880b72e 8574 bnx2_release_firmware(bp);
8575
c239f279 8576 free_netdev(dev);
cd709aa9 8577
b6016b76
MC		 8578 pci_release_regions(pdev);
8579 pci_disable_device(pdev);
b6016b76
MC		 8580}
8581
8582static int
28fb4eb4 8583bnx2_suspend(struct device *device)
b6016b76 8584{
28fb4eb4 8585 struct pci_dev *pdev = to_pci_dev(device);
b6016b76 8586 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8587 struct bnx2 *bp = netdev_priv(dev);
b6016b76 8588
28fb4eb4
MC		 8589 if (netif_running(dev)) {
8590 cancel_work_sync(&bp->reset_task);
8591 bnx2_netif_stop(bp, true);
8592 netif_device_detach(dev);
8593 del_timer_sync(&bp->timer);
8594 bnx2_shutdown_chip(bp);
8595 __bnx2_free_irq(bp);
8596 bnx2_free_skbs(bp);
8597 }
8598 bnx2_setup_wol(bp);
b6016b76
MC		 8599 return 0;
8600}
8601
8602static int
28fb4eb4 8603bnx2_resume(struct device *device)
b6016b76 8604{
28fb4eb4 8605 struct pci_dev *pdev = to_pci_dev(device);
b6016b76 8606 struct net_device *dev = pci_get_drvdata(pdev);
972ec0d4 8607 struct bnx2 *bp = netdev_priv(dev);
b6016b76
MC		 8608
8609 if (!netif_running(dev))
8610 return 0;
8611
829ca9a3 8612 bnx2_set_power_state(bp, PCI_D0);
b6016b76 8613 netif_device_attach(dev);
28fb4eb4 8614 bnx2_request_irq(bp);
9a120bc5 8615 bnx2_init_nic(bp, 1);
212f9934 8616 bnx2_netif_start(bp, true);
b6016b76
MC		 8617 return 0;
8618}
8619
28fb4eb4
MC		 8620#ifdef CONFIG_PM_SLEEP
8621static SIMPLE_DEV_PM_OPS(bnx2_pm_ops, bnx2_suspend, bnx2_resume);
8622#define BNX2_PM_OPS (&bnx2_pm_ops)
8623
8624#else
8625
8626#define BNX2_PM_OPS NULL
8627
8628#endif /* CONFIG_PM_SLEEP */
6ff2da49
WX		 8629/**
8630 * bnx2_io_error_detected - called when PCI error is detected
8631 * @pdev: Pointer to PCI device
8632 * @state: The current pci connection state
8633 *
8634 * This function is called after a PCI bus error affecting
8635 * this device has been detected.
8636 */
8637static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8638 pci_channel_state_t state)
8639{
8640 struct net_device *dev = pci_get_drvdata(pdev);
8641 struct bnx2 *bp = netdev_priv(dev);
8642
8643 rtnl_lock();
8644 netif_device_detach(dev);
8645
2ec3de26
DN		 8646 if (state == pci_channel_io_perm_failure) {
8647 rtnl_unlock();
8648 return PCI_ERS_RESULT_DISCONNECT;
8649 }
8650
6ff2da49 8651 if (netif_running(dev)) {
212f9934 8652 bnx2_netif_stop(bp, true);
6ff2da49
WX		 8653 del_timer_sync(&bp->timer);
8654 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8655 }
8656
8657 pci_disable_device(pdev);
8658 rtnl_unlock();
8659
8660 /* Request a slot slot reset. */
8661 return PCI_ERS_RESULT_NEED_RESET;
8662}
8663
8664/**
8665 * bnx2_io_slot_reset - called after the pci bus has been reset.
8666 * @pdev: Pointer to PCI device
8667 *
8668 * Restart the card from scratch, as if from a cold-boot.
8669 */
8670static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8671{
8672 struct net_device *dev = pci_get_drvdata(pdev);
8673 struct bnx2 *bp = netdev_priv(dev);
02481bc6
MC		 8674 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8675 int err = 0;
6ff2da49
WX		 8676
8677 rtnl_lock();
8678 if (pci_enable_device(pdev)) {
8679 dev_err(&pdev->dev,
3a9c6a49 8680 "Cannot re-enable PCI device after reset\n");
cd709aa9
JF		 8681 } else {
8682 pci_set_master(pdev);
8683 pci_restore_state(pdev);
8684 pci_save_state(pdev);
8685
25bfb1dd 8686 if (netif_running(dev))
02481bc6 8687 err = bnx2_init_nic(bp, 1);
25bfb1dd 8688
02481bc6
MC		 8689 if (!err)
8690 result = PCI_ERS_RESULT_RECOVERED;
8691 }
8692
8693 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) {
8694 bnx2_napi_enable(bp);
8695 dev_close(dev);
6ff2da49 8696 }
cd709aa9 8697 rtnl_unlock();
6ff2da49 8698
4bb9ebc7 8699 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
c239f279
MC		 8700 return result;
8701
cd709aa9
JF		 8702 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8703 if (err) {
8704 dev_err(&pdev->dev,
8705 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8706 err); /* non-fatal, continue */
6ff2da49
WX		 8707 }
8708
cd709aa9 8709 return result;
6ff2da49
WX		 8710}
8711
8712/**
8713 * bnx2_io_resume - called when traffic can start flowing again.
8714 * @pdev: Pointer to PCI device
8715 *
8716 * This callback is called when the error recovery driver tells us that
8717 * its OK to resume normal operation.
8718 */
8719static void bnx2_io_resume(struct pci_dev *pdev)
8720{
8721 struct net_device *dev = pci_get_drvdata(pdev);
8722 struct bnx2 *bp = netdev_priv(dev);
8723
8724 rtnl_lock();
8725 if (netif_running(dev))
212f9934 8726 bnx2_netif_start(bp, true);
6ff2da49
WX		 8727
8728 netif_device_attach(dev);
8729 rtnl_unlock();
8730}
8731
25bfb1dd
MC		 8732static void bnx2_shutdown(struct pci_dev *pdev)
8733{
8734 struct net_device *dev = pci_get_drvdata(pdev);
8735 struct bnx2 *bp;
8736
8737 if (!dev)
8738 return;
8739
8740 bp = netdev_priv(dev);
8741 if (!bp)
8742 return;
8743
8744 rtnl_lock();
8745 if (netif_running(dev))
8746 dev_close(bp->dev);
8747
8748 if (system_state == SYSTEM_POWER_OFF)
8749 bnx2_set_power_state(bp, PCI_D3hot);
8750
8751 rtnl_unlock();
8752}
8753
fda4d85d 8754static const struct pci_error_handlers bnx2_err_handler = {
6ff2da49
WX		 8755 .error_detected = bnx2_io_error_detected,
8756 .slot_reset = bnx2_io_slot_reset,
8757 .resume = bnx2_io_resume,
8758};
8759
b6016b76 8760static struct pci_driver bnx2_pci_driver = {
14ab9b86
PH		 8761 .name = DRV_MODULE_NAME,
8762 .id_table = bnx2_pci_tbl,
8763 .probe = bnx2_init_one,
cfd95a63 8764 .remove = bnx2_remove_one,
28fb4eb4 8765 .driver.pm = BNX2_PM_OPS,
6ff2da49 8766 .err_handler = &bnx2_err_handler,
25bfb1dd 8767 .shutdown = bnx2_shutdown,
b6016b76
MC		 8768};
8769
5a4123f3 8770module_pci_driver(bnx2_pci_driver);
Linux kernel - Deliverables
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