Commit | Line | Data |
---|---|---|
a2fbb9ea ET |
1 | /* bnx2x.h: Broadcom Everest network driver. |
2 | * | |
247fa82b | 3 | * Copyright (c) 2007-2013 Broadcom Corporation |
a2fbb9ea ET |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
24e3fcef EG |
9 | * Maintained by: Eilon Greenstein <eilong@broadcom.com> |
10 | * Written by: Eliezer Tamir | |
a2fbb9ea ET |
11 | * Based on code from Michael Chan's bnx2 driver |
12 | */ | |
13 | ||
14 | #ifndef BNX2X_H | |
15 | #define BNX2X_H | |
290ca2bb AE |
16 | |
17 | #include <linux/pci.h> | |
ec6ba945 | 18 | #include <linux/netdevice.h> |
b7f080cf | 19 | #include <linux/dma-mapping.h> |
ec6ba945 | 20 | #include <linux/types.h> |
290ca2bb | 21 | #include <linux/pci_regs.h> |
a2fbb9ea | 22 | |
34f80b04 EG |
23 | /* compilation time flags */ |
24 | ||
25 | /* define this to make the driver freeze on error to allow getting debug info | |
26 | * (you will need to reboot afterwards) */ | |
27 | /* #define BNX2X_STOP_ON_ERROR */ | |
28 | ||
26f26b3a DK |
29 | #define DRV_MODULE_VERSION "1.78.17-0" |
30 | #define DRV_MODULE_RELDATE "2013/04/11" | |
de0c62db DK |
31 | #define BNX2X_BC_VER 0x040200 |
32 | ||
785b9b1a | 33 | #if defined(CONFIG_DCB) |
98507672 | 34 | #define BCM_DCBNL |
785b9b1a | 35 | #endif |
b475d78f | 36 | |
b475d78f YM |
37 | #include "bnx2x_hsi.h" |
38 | ||
5d1e859c | 39 | #include "../cnic_if.h" |
0c6671b0 | 40 | |
55c11941 | 41 | #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) |
01cd4528 EG |
42 | |
43 | #include <linux/mdio.h> | |
619c5cb6 | 44 | |
359d8b15 EG |
45 | #include "bnx2x_reg.h" |
46 | #include "bnx2x_fw_defs.h" | |
2e499d3c | 47 | #include "bnx2x_mfw_req.h" |
359d8b15 | 48 | #include "bnx2x_link.h" |
619c5cb6 | 49 | #include "bnx2x_sp.h" |
e4901dde | 50 | #include "bnx2x_dcb.h" |
6c719d00 | 51 | #include "bnx2x_stats.h" |
be1f1ffa | 52 | #include "bnx2x_vfpf.h" |
359d8b15 | 53 | |
1ab4434c AE |
54 | enum bnx2x_int_mode { |
55 | BNX2X_INT_MODE_MSIX, | |
56 | BNX2X_INT_MODE_INTX, | |
57 | BNX2X_INT_MODE_MSI | |
58 | }; | |
59 | ||
a2fbb9ea ET |
60 | /* error/debug prints */ |
61 | ||
34f80b04 | 62 | #define DRV_MODULE_NAME "bnx2x" |
a2fbb9ea ET |
63 | |
64 | /* for messages that are currently off */ | |
51c1a580 MS |
65 | #define BNX2X_MSG_OFF 0x0 |
66 | #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ | |
67 | #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ | |
68 | #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ | |
69 | #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ | |
70 | #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ | |
71 | #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ | |
72 | #define BNX2X_MSG_IOV 0x0800000 | |
73 | #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ | |
74 | #define BNX2X_MSG_ETHTOOL 0x4000000 | |
75 | #define BNX2X_MSG_DCB 0x8000000 | |
a2fbb9ea | 76 | |
a2fbb9ea | 77 | /* regular debug print */ |
f1deab50 | 78 | #define DP(__mask, fmt, ...) \ |
7995c64e | 79 | do { \ |
51c1a580 | 80 | if (unlikely(bp->msg_enable & (__mask))) \ |
f1deab50 JP |
81 | pr_notice("[%s:%d(%s)]" fmt, \ |
82 | __func__, __LINE__, \ | |
83 | bp->dev ? (bp->dev->name) : "?", \ | |
84 | ##__VA_ARGS__); \ | |
7995c64e | 85 | } while (0) |
a2fbb9ea | 86 | |
f1deab50 | 87 | #define DP_CONT(__mask, fmt, ...) \ |
619c5cb6 | 88 | do { \ |
51c1a580 | 89 | if (unlikely(bp->msg_enable & (__mask))) \ |
f1deab50 | 90 | pr_cont(fmt, ##__VA_ARGS__); \ |
619c5cb6 VZ |
91 | } while (0) |
92 | ||
34f80b04 | 93 | /* errors debug print */ |
f1deab50 | 94 | #define BNX2X_DBG_ERR(fmt, ...) \ |
7995c64e | 95 | do { \ |
51c1a580 | 96 | if (unlikely(netif_msg_probe(bp))) \ |
f1deab50 | 97 | pr_err("[%s:%d(%s)]" fmt, \ |
7995c64e JP |
98 | __func__, __LINE__, \ |
99 | bp->dev ? (bp->dev->name) : "?", \ | |
f1deab50 | 100 | ##__VA_ARGS__); \ |
7995c64e | 101 | } while (0) |
a2fbb9ea | 102 | |
34f80b04 | 103 | /* for errors (never masked) */ |
f1deab50 | 104 | #define BNX2X_ERR(fmt, ...) \ |
7995c64e | 105 | do { \ |
f1deab50 | 106 | pr_err("[%s:%d(%s)]" fmt, \ |
7995c64e JP |
107 | __func__, __LINE__, \ |
108 | bp->dev ? (bp->dev->name) : "?", \ | |
f1deab50 JP |
109 | ##__VA_ARGS__); \ |
110 | } while (0) | |
cdaa7cb8 | 111 | |
f1deab50 JP |
112 | #define BNX2X_ERROR(fmt, ...) \ |
113 | pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) | |
cdaa7cb8 | 114 | |
a2fbb9ea | 115 | /* before we have a dev->name use dev_info() */ |
f1deab50 | 116 | #define BNX2X_DEV_INFO(fmt, ...) \ |
7995c64e | 117 | do { \ |
51c1a580 | 118 | if (unlikely(netif_msg_probe(bp))) \ |
f1deab50 | 119 | dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ |
7995c64e | 120 | } while (0) |
a2fbb9ea | 121 | |
ca9bdb9b YM |
122 | /* Error handling */ |
123 | void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); | |
a2fbb9ea | 124 | #ifdef BNX2X_STOP_ON_ERROR |
f1deab50 JP |
125 | #define bnx2x_panic() \ |
126 | do { \ | |
127 | bp->panic = 1; \ | |
128 | BNX2X_ERR("driver assert\n"); \ | |
823e1d90 | 129 | bnx2x_panic_dump(bp, true); \ |
f1deab50 | 130 | } while (0) |
a2fbb9ea | 131 | #else |
f1deab50 JP |
132 | #define bnx2x_panic() \ |
133 | do { \ | |
134 | bp->panic = 1; \ | |
135 | BNX2X_ERR("driver assert\n"); \ | |
823e1d90 | 136 | bnx2x_panic_dump(bp, false); \ |
f1deab50 | 137 | } while (0) |
a2fbb9ea ET |
138 | #endif |
139 | ||
523224a3 | 140 | #define bnx2x_mc_addr(ha) ((ha)->addr) |
6e30dd4e | 141 | #define bnx2x_uc_addr(ha) ((ha)->addr) |
a2fbb9ea | 142 | |
2de67439 YM |
143 | #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) |
144 | #define U64_HI(x) ((u32)(((u64)(x)) >> 32)) | |
34f80b04 | 145 | #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) |
a2fbb9ea | 146 | |
523224a3 | 147 | #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) |
a2fbb9ea | 148 | |
34f80b04 EG |
149 | #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) |
150 | #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) | |
523224a3 | 151 | #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) |
34f80b04 EG |
152 | |
153 | #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) | |
a2fbb9ea | 154 | #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) |
34f80b04 | 155 | #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) |
a2fbb9ea | 156 | |
34f80b04 EG |
157 | #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) |
158 | #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) | |
a2fbb9ea | 159 | |
c18487ee YR |
160 | #define REG_RD_DMAE(bp, offset, valp, len32) \ |
161 | do { \ | |
162 | bnx2x_read_dmae(bp, offset, len32);\ | |
573f2035 | 163 | memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ |
c18487ee YR |
164 | } while (0) |
165 | ||
34f80b04 | 166 | #define REG_WR_DMAE(bp, offset, valp, len32) \ |
a2fbb9ea | 167 | do { \ |
573f2035 | 168 | memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ |
a2fbb9ea ET |
169 | bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ |
170 | offset, len32); \ | |
171 | } while (0) | |
172 | ||
523224a3 DK |
173 | #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ |
174 | REG_WR_DMAE(bp, offset, valp, len32) | |
175 | ||
3359fced | 176 | #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ |
573f2035 EG |
177 | do { \ |
178 | memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ | |
179 | bnx2x_write_big_buf_wb(bp, addr, len32); \ | |
180 | } while (0) | |
181 | ||
34f80b04 EG |
182 | #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ |
183 | offsetof(struct shmem_region, field)) | |
184 | #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) | |
185 | #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) | |
a2fbb9ea | 186 | |
2691d51d EG |
187 | #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ |
188 | offsetof(struct shmem2_region, field)) | |
189 | #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) | |
190 | #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) | |
523224a3 DK |
191 | #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ |
192 | offsetof(struct mf_cfg, field)) | |
f85582f8 | 193 | #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ |
f2e0899f | 194 | offsetof(struct mf2_cfg, field)) |
2691d51d | 195 | |
523224a3 DK |
196 | #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) |
197 | #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ | |
198 | MF_CFG_ADDR(bp, field), (val)) | |
f2e0899f | 199 | #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) |
f85582f8 | 200 | |
f2e0899f DK |
201 | #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ |
202 | (SHMEM2_RD((bp), size) > \ | |
203 | offsetof(struct shmem2_region, field))) | |
72fd0718 | 204 | |
345b5d52 | 205 | #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) |
3196a88a | 206 | #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) |
a2fbb9ea | 207 | |
523224a3 DK |
208 | /* SP SB indices */ |
209 | ||
210 | /* General SP events - stats query, cfc delete, etc */ | |
211 | #define HC_SP_INDEX_ETH_DEF_CONS 3 | |
212 | ||
213 | /* EQ completions */ | |
214 | #define HC_SP_INDEX_EQ_CONS 7 | |
215 | ||
ec6ba945 VZ |
216 | /* FCoE L2 connection completions */ |
217 | #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 | |
218 | #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 | |
523224a3 DK |
219 | /* iSCSI L2 */ |
220 | #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 | |
221 | #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 | |
222 | ||
ec6ba945 VZ |
223 | /* Special clients parameters */ |
224 | ||
225 | /* SB indices */ | |
226 | /* FCoE L2 */ | |
227 | #define BNX2X_FCOE_L2_RX_INDEX \ | |
228 | (&bp->def_status_blk->sp_sb.\ | |
229 | index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) | |
230 | ||
231 | #define BNX2X_FCOE_L2_TX_INDEX \ | |
232 | (&bp->def_status_blk->sp_sb.\ | |
233 | index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) | |
234 | ||
523224a3 DK |
235 | /** |
236 | * CIDs and CLIDs: | |
237 | * CLIDs below is a CLID for func 0, then the CLID for other | |
238 | * functions will be calculated by the formula: | |
239 | * | |
240 | * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X | |
241 | * | |
242 | */ | |
134d0f97 DK |
243 | enum { |
244 | BNX2X_ISCSI_ETH_CL_ID_IDX, | |
245 | BNX2X_FCOE_ETH_CL_ID_IDX, | |
246 | BNX2X_MAX_CNIC_ETH_CL_ID_IDX, | |
247 | }; | |
248 | ||
37ae41a9 MS |
249 | #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\ |
250 | (bp)->max_cos) | |
134d0f97 | 251 | /* iSCSI L2 */ |
37ae41a9 | 252 | #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) |
134d0f97 | 253 | /* FCoE L2 */ |
37ae41a9 | 254 | #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) |
ec6ba945 | 255 | |
55c11941 MS |
256 | #define CNIC_SUPPORT(bp) ((bp)->cnic_support) |
257 | #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) | |
258 | #define CNIC_LOADED(bp) ((bp)->cnic_loaded) | |
259 | #define FCOE_INIT(bp) ((bp)->fcoe_init) | |
523224a3 | 260 | |
72fd0718 VZ |
261 | #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ |
262 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | |
263 | ||
523224a3 DK |
264 | #define SM_RX_ID 0 |
265 | #define SM_TX_ID 1 | |
a2fbb9ea | 266 | |
6383c0b3 AE |
267 | /* defines for multiple tx priority indices */ |
268 | #define FIRST_TX_ONLY_COS_INDEX 1 | |
269 | #define FIRST_TX_COS_INDEX 0 | |
270 | ||
6383c0b3 | 271 | /* rules for calculating the cids of tx-only connections */ |
65565884 MS |
272 | #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) |
273 | #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ | |
274 | (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) | |
6383c0b3 AE |
275 | |
276 | /* fp index inside class of service range */ | |
65565884 MS |
277 | #define FP_COS_TO_TXQ(fp, cos, bp) \ |
278 | ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) | |
279 | ||
280 | /* Indexes for transmission queues array: | |
281 | * txdata for RSS i CoS j is at location i + (j * num of RSS) | |
282 | * txdata for FCoE (if exist) is at location max cos * num of RSS | |
283 | * txdata for FWD (if exist) is one location after FCoE | |
284 | * txdata for OOO (if exist) is one location after FWD | |
6383c0b3 | 285 | */ |
65565884 MS |
286 | enum { |
287 | FCOE_TXQ_IDX_OFFSET, | |
288 | FWD_TXQ_IDX_OFFSET, | |
289 | OOO_TXQ_IDX_OFFSET, | |
290 | }; | |
291 | #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) | |
65565884 | 292 | #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) |
a2fbb9ea | 293 | |
6383c0b3 | 294 | /* fast path */ |
e52fcb24 ED |
295 | /* |
296 | * This driver uses new build_skb() API : | |
297 | * RX ring buffer contains pointer to kmalloc() data only, | |
298 | * skb are built only after Hardware filled the frame. | |
299 | */ | |
a2fbb9ea | 300 | struct sw_rx_bd { |
e52fcb24 | 301 | u8 *data; |
1a983142 | 302 | DEFINE_DMA_UNMAP_ADDR(mapping); |
a2fbb9ea ET |
303 | }; |
304 | ||
305 | struct sw_tx_bd { | |
34f80b04 EG |
306 | struct sk_buff *skb; |
307 | u16 first_bd; | |
ca00392c EG |
308 | u8 flags; |
309 | /* Set on the first BD descriptor when there is a split BD */ | |
310 | #define BNX2X_TSO_SPLIT_BD (1<<0) | |
a2fbb9ea ET |
311 | }; |
312 | ||
7a9b2557 VZ |
313 | struct sw_rx_page { |
314 | struct page *page; | |
1a983142 | 315 | DEFINE_DMA_UNMAP_ADDR(mapping); |
7a9b2557 VZ |
316 | }; |
317 | ||
ca00392c EG |
318 | union db_prod { |
319 | struct doorbell_set_prod data; | |
320 | u32 raw; | |
321 | }; | |
322 | ||
dfacf138 DK |
323 | /* dropless fc FW/HW related params */ |
324 | #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) | |
325 | #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ | |
326 | ETH_MAX_AGGREGATION_QUEUES_E1 :\ | |
327 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2) | |
328 | #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) | |
329 | #define FW_PREFETCH_CNT 16 | |
330 | #define DROPLESS_FC_HEADROOM 100 | |
7a9b2557 VZ |
331 | |
332 | /* MC hsi */ | |
619c5cb6 VZ |
333 | #define BCM_PAGE_SHIFT 12 |
334 | #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) | |
335 | #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) | |
7a9b2557 VZ |
336 | #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) |
337 | ||
619c5cb6 VZ |
338 | #define PAGES_PER_SGE_SHIFT 0 |
339 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | |
340 | #define SGE_PAGE_SIZE PAGE_SIZE | |
341 | #define SGE_PAGE_SHIFT PAGE_SHIFT | |
342 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) | |
8d9ac297 AE |
343 | #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) |
344 | #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ | |
345 | SGE_PAGES), 0xffff) | |
7a9b2557 VZ |
346 | |
347 | /* SGE ring related macros */ | |
619c5cb6 | 348 | #define NUM_RX_SGE_PAGES 2 |
7a9b2557 | 349 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
dfacf138 DK |
350 | #define NEXT_PAGE_SGE_DESC_CNT 2 |
351 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) | |
33471629 | 352 | /* RX_SGE_CNT is promised to be a power of 2 */ |
619c5cb6 VZ |
353 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
354 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | |
355 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | |
7a9b2557 | 356 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ |
dfacf138 DK |
357 | (MAX_RX_SGE_CNT - 1)) ? \ |
358 | (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ | |
359 | (x) + 1) | |
619c5cb6 VZ |
360 | #define RX_SGE(x) ((x) & MAX_RX_SGE) |
361 | ||
dfacf138 DK |
362 | /* |
363 | * Number of required SGEs is the sum of two: | |
364 | * 1. Number of possible opened aggregations (next packet for | |
16a5fd92 | 365 | * these aggregations will probably consume SGE immediately) |
dfacf138 DK |
366 | * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only |
367 | * after placement on BD for new TPA aggregation) | |
368 | * | |
369 | * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page | |
370 | */ | |
371 | #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ | |
372 | (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) | |
373 | #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ | |
374 | MAX_RX_SGE_CNT) | |
375 | #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ | |
376 | NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) | |
377 | #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
378 | ||
619c5cb6 | 379 | /* Manipulate a bit vector defined as an array of u64 */ |
7a9b2557 | 380 | |
7a9b2557 | 381 | /* Number of bits in one sge_mask array element */ |
619c5cb6 VZ |
382 | #define BIT_VEC64_ELEM_SZ 64 |
383 | #define BIT_VEC64_ELEM_SHIFT 6 | |
384 | #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) | |
385 | ||
619c5cb6 VZ |
386 | #define __BIT_VEC64_SET_BIT(el, bit) \ |
387 | do { \ | |
388 | el = ((el) | ((u64)0x1 << (bit))); \ | |
389 | } while (0) | |
390 | ||
391 | #define __BIT_VEC64_CLEAR_BIT(el, bit) \ | |
392 | do { \ | |
393 | el = ((el) & (~((u64)0x1 << (bit)))); \ | |
394 | } while (0) | |
395 | ||
619c5cb6 VZ |
396 | #define BIT_VEC64_SET_BIT(vec64, idx) \ |
397 | __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ | |
398 | (idx) & BIT_VEC64_ELEM_MASK) | |
399 | ||
400 | #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ | |
401 | __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ | |
402 | (idx) & BIT_VEC64_ELEM_MASK) | |
403 | ||
404 | #define BIT_VEC64_TEST_BIT(vec64, idx) \ | |
405 | (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ | |
406 | ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) | |
7a9b2557 VZ |
407 | |
408 | /* Creates a bitmask of all ones in less significant bits. | |
409 | idx - index of the most significant bit in the created mask */ | |
619c5cb6 VZ |
410 | #define BIT_VEC64_ONES_MASK(idx) \ |
411 | (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) | |
412 | #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) | |
413 | ||
414 | /*******************************************************/ | |
415 | ||
7a9b2557 | 416 | /* Number of u64 elements in SGE mask array */ |
b3637827 | 417 | #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) |
7a9b2557 VZ |
418 | #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) |
419 | #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) | |
420 | ||
523224a3 DK |
421 | union host_hc_status_block { |
422 | /* pointer to fp status block e1x */ | |
423 | struct host_hc_status_block_e1x *e1x_sb; | |
f2e0899f DK |
424 | /* pointer to fp status block e2 */ |
425 | struct host_hc_status_block_e2 *e2_sb; | |
523224a3 | 426 | }; |
7a9b2557 | 427 | |
619c5cb6 VZ |
428 | struct bnx2x_agg_info { |
429 | /* | |
e52fcb24 ED |
430 | * First aggregation buffer is a data buffer, the following - are pages. |
431 | * We will preallocate the data buffer for each aggregation when | |
619c5cb6 VZ |
432 | * we open the interface and will replace the BD at the consumer |
433 | * with this one when we receive the TPA_START CQE in order to | |
434 | * keep the Rx BD ring consistent. | |
435 | */ | |
436 | struct sw_rx_bd first_buf; | |
437 | u8 tpa_state; | |
438 | #define BNX2X_TPA_START 1 | |
439 | #define BNX2X_TPA_STOP 2 | |
440 | #define BNX2X_TPA_ERROR 3 | |
441 | u8 placement_offset; | |
442 | u16 parsing_flags; | |
443 | u16 vlan_tag; | |
444 | u16 len_on_bd; | |
e52fcb24 | 445 | u32 rxhash; |
a334b5fb | 446 | bool l4_rxhash; |
621b4d66 DK |
447 | u16 gro_size; |
448 | u16 full_page; | |
619c5cb6 VZ |
449 | }; |
450 | ||
451 | #define Q_STATS_OFFSET32(stat_name) \ | |
452 | (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) | |
453 | ||
6383c0b3 AE |
454 | struct bnx2x_fp_txdata { |
455 | ||
456 | struct sw_tx_bd *tx_buf_ring; | |
457 | ||
458 | union eth_tx_bd_types *tx_desc_ring; | |
459 | dma_addr_t tx_desc_mapping; | |
460 | ||
461 | u32 cid; | |
462 | ||
463 | union db_prod tx_db; | |
464 | ||
465 | u16 tx_pkt_prod; | |
466 | u16 tx_pkt_cons; | |
467 | u16 tx_bd_prod; | |
468 | u16 tx_bd_cons; | |
469 | ||
470 | unsigned long tx_pkt; | |
471 | ||
472 | __le16 *tx_cons_sb; | |
473 | ||
474 | int txq_index; | |
65565884 MS |
475 | struct bnx2x_fastpath *parent_fp; |
476 | int tx_ring_size; | |
6383c0b3 AE |
477 | }; |
478 | ||
621b4d66 DK |
479 | enum bnx2x_tpa_mode_t { |
480 | TPA_MODE_LRO, | |
481 | TPA_MODE_GRO | |
482 | }; | |
483 | ||
a2fbb9ea | 484 | struct bnx2x_fastpath { |
619c5cb6 | 485 | struct bnx2x *bp; /* parent */ |
a2fbb9ea | 486 | |
34f80b04 | 487 | struct napi_struct napi; |
f85582f8 | 488 | union host_hc_status_block status_blk; |
16a5fd92 | 489 | /* chip independent shortcuts into sb structure */ |
523224a3 DK |
490 | __le16 *sb_index_values; |
491 | __le16 *sb_running_index; | |
16a5fd92 | 492 | /* chip independent shortcut into rx_prods_offset memory */ |
523224a3 DK |
493 | u32 ustorm_rx_prods_offset; |
494 | ||
a8c94b91 | 495 | u32 rx_buf_size; |
d46d132c | 496 | u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ |
34f80b04 | 497 | dma_addr_t status_blk_mapping; |
a2fbb9ea | 498 | |
621b4d66 DK |
499 | enum bnx2x_tpa_mode_t mode; |
500 | ||
6383c0b3 | 501 | u8 max_cos; /* actual number of active tx coses */ |
65565884 | 502 | struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; |
a2fbb9ea | 503 | |
7a9b2557 VZ |
504 | struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ |
505 | struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ | |
a2fbb9ea ET |
506 | |
507 | struct eth_rx_bd *rx_desc_ring; | |
34f80b04 | 508 | dma_addr_t rx_desc_mapping; |
a2fbb9ea ET |
509 | |
510 | union eth_rx_cqe *rx_comp_ring; | |
34f80b04 EG |
511 | dma_addr_t rx_comp_mapping; |
512 | ||
7a9b2557 VZ |
513 | /* SGE ring */ |
514 | struct eth_rx_sge *rx_sge_ring; | |
515 | dma_addr_t rx_sge_mapping; | |
516 | ||
517 | u64 sge_mask[RX_SGE_MASK_LEN]; | |
518 | ||
619c5cb6 | 519 | u32 cid; |
34f80b04 | 520 | |
6383c0b3 AE |
521 | __le16 fp_hc_idx; |
522 | ||
f85582f8 | 523 | u8 index; /* number in fp array */ |
f233cafe | 524 | u8 rx_queue; /* index for skb_record */ |
f85582f8 | 525 | u8 cl_id; /* eth client id */ |
523224a3 DK |
526 | u8 cl_qzone_id; |
527 | u8 fw_sb_id; /* status block number in FW */ | |
528 | u8 igu_sb_id; /* status block number in HW */ | |
34f80b04 EG |
529 | |
530 | u16 rx_bd_prod; | |
531 | u16 rx_bd_cons; | |
532 | u16 rx_comp_prod; | |
533 | u16 rx_comp_cons; | |
7a9b2557 VZ |
534 | u16 rx_sge_prod; |
535 | /* The last maximal completed SGE */ | |
536 | u16 last_max_sge; | |
4781bfad | 537 | __le16 *rx_cons_sb; |
6383c0b3 | 538 | unsigned long rx_pkt, |
66e855f3 | 539 | rx_calls; |
ab6ad5a4 | 540 | |
7a9b2557 | 541 | /* TPA related */ |
15192a8c | 542 | struct bnx2x_agg_info *tpa_info; |
7a9b2557 VZ |
543 | u8 disable_tpa; |
544 | #ifdef BNX2X_STOP_ON_ERROR | |
545 | u64 tpa_queue_used; | |
546 | #endif | |
ca00392c EG |
547 | /* The size is calculated using the following: |
548 | sizeof name field from netdev structure + | |
549 | 4 ('-Xx-' string) + | |
550 | 4 (for the digits and to make it DWORD aligned) */ | |
551 | #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) | |
552 | char name[FP_NAME_SIZE]; | |
a2fbb9ea ET |
553 | }; |
554 | ||
15192a8c BW |
555 | #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) |
556 | #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) | |
557 | #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) | |
558 | #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) | |
a8c94b91 VZ |
559 | |
560 | /* Use 2500 as a mini-jumbo MTU for FCoE */ | |
561 | #define BNX2X_FCOE_MINI_JUMBO_MTU 2500 | |
562 | ||
65565884 MS |
563 | #define FCOE_IDX_OFFSET 0 |
564 | ||
565 | #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ | |
566 | FCOE_IDX_OFFSET) | |
567 | #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) | |
568 | #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) | |
15192a8c BW |
569 | #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) |
570 | #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) | |
65565884 MS |
571 | #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ |
572 | txdata_ptr[FIRST_TX_COS_INDEX] \ | |
573 | ->var) | |
619c5cb6 | 574 | |
55c11941 MS |
575 | #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) |
576 | #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) | |
577 | #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) | |
7a9b2557 | 578 | |
7a9b2557 | 579 | /* MC hsi */ |
619c5cb6 VZ |
580 | #define MAX_FETCH_BD 13 /* HW max BDs per packet */ |
581 | #define RX_COPY_THRESH 92 | |
7a9b2557 | 582 | |
619c5cb6 | 583 | #define NUM_TX_RINGS 16 |
ca00392c | 584 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
dfacf138 DK |
585 | #define NEXT_PAGE_TX_DESC_CNT 1 |
586 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) | |
619c5cb6 VZ |
587 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) |
588 | #define MAX_TX_BD (NUM_TX_BD - 1) | |
589 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | |
7a9b2557 | 590 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
dfacf138 DK |
591 | (MAX_TX_DESC_CNT - 1)) ? \ |
592 | (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ | |
593 | (x) + 1) | |
619c5cb6 VZ |
594 | #define TX_BD(x) ((x) & MAX_TX_BD) |
595 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | |
7a9b2557 | 596 | |
7df2dc6b DK |
597 | /* number of NEXT_PAGE descriptors may be required during placement */ |
598 | #define NEXT_CNT_PER_TX_PKT(bds) \ | |
599 | (((bds) + MAX_TX_DESC_CNT - 1) / \ | |
600 | MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) | |
601 | /* max BDs per tx packet w/o next_pages: | |
602 | * START_BD - describes packed | |
603 | * START_BD(splitted) - includes unpaged data segment for GSO | |
604 | * PARSING_BD - for TSO and CSUM data | |
a848ade4 | 605 | * PARSING_BD2 - for encapsulation data |
16a5fd92 | 606 | * Frag BDs - describes pages for frags |
7df2dc6b | 607 | */ |
a848ade4 | 608 | #define BDS_PER_TX_PKT 4 |
7df2dc6b DK |
609 | #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) |
610 | /* max BDs per tx packet including next pages */ | |
611 | #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ | |
612 | NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) | |
613 | ||
7a9b2557 | 614 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ |
619c5cb6 | 615 | #define NUM_RX_RINGS 8 |
7a9b2557 | 616 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
dfacf138 DK |
617 | #define NEXT_PAGE_RX_DESC_CNT 2 |
618 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) | |
619c5cb6 VZ |
619 | #define RX_DESC_MASK (RX_DESC_CNT - 1) |
620 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | |
621 | #define MAX_RX_BD (NUM_RX_BD - 1) | |
622 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | |
dfacf138 DK |
623 | |
624 | /* dropless fc calculations for BDs | |
625 | * | |
626 | * Number of BDs should as number of buffers in BRB: | |
627 | * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT | |
628 | * "next" elements on each page | |
629 | */ | |
630 | #define NUM_BD_REQ BRB_SIZE(bp) | |
631 | #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ | |
632 | MAX_RX_DESC_CNT) | |
633 | #define BD_TH_LO(bp) (NUM_BD_REQ + \ | |
634 | NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ | |
635 | FW_DROP_LEVEL(bp)) | |
636 | #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
637 | ||
638 | #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) | |
619c5cb6 VZ |
639 | |
640 | #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ | |
641 | ETH_MIN_RX_CQES_WITH_TPA_E1 : \ | |
642 | ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) | |
643 | #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA | |
644 | #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) | |
645 | #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ | |
646 | MIN_RX_AVAIL)) | |
647 | ||
7a9b2557 | 648 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
dfacf138 DK |
649 | (MAX_RX_DESC_CNT - 1)) ? \ |
650 | (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ | |
651 | (x) + 1) | |
619c5cb6 | 652 | #define RX_BD(x) ((x) & MAX_RX_BD) |
7a9b2557 | 653 | |
619c5cb6 VZ |
654 | /* |
655 | * As long as CQE is X times bigger than BD entry we have to allocate X times | |
656 | * more pages for CQ ring in order to keep it balanced with BD ring | |
657 | */ | |
658 | #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) | |
659 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) | |
7a9b2557 | 660 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
dfacf138 DK |
661 | #define NEXT_PAGE_RCQ_DESC_CNT 1 |
662 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) | |
619c5cb6 VZ |
663 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) |
664 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | |
665 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | |
7a9b2557 | 666 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ |
dfacf138 DK |
667 | (MAX_RCQ_DESC_CNT - 1)) ? \ |
668 | (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ | |
669 | (x) + 1) | |
619c5cb6 | 670 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) |
7a9b2557 | 671 | |
dfacf138 DK |
672 | /* dropless fc calculations for RCQs |
673 | * | |
674 | * Number of RCQs should be as number of buffers in BRB: | |
675 | * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT | |
676 | * "next" elements on each page | |
677 | */ | |
678 | #define NUM_RCQ_REQ BRB_SIZE(bp) | |
679 | #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ | |
680 | MAX_RCQ_DESC_CNT) | |
681 | #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ | |
682 | NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ | |
683 | FW_DROP_LEVEL(bp)) | |
684 | #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) | |
685 | ||
33471629 | 686 | /* This is needed for determining of last_max */ |
619c5cb6 VZ |
687 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
688 | #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) | |
7a9b2557 | 689 | |
619c5cb6 VZ |
690 | #define BNX2X_SWCID_SHIFT 17 |
691 | #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) | |
7a9b2557 VZ |
692 | |
693 | /* used on a CID received from the HW */ | |
619c5cb6 | 694 | #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) |
7a9b2557 VZ |
695 | #define CQE_CMD(x) (le32_to_cpu(x) >> \ |
696 | COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) | |
697 | ||
bb2a0f7a YG |
698 | #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ |
699 | le32_to_cpu((bd)->addr_lo)) | |
700 | #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) | |
701 | ||
523224a3 DK |
702 | #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ |
703 | #define BNX2X_DB_SHIFT 7 /* 128 bytes*/ | |
619c5cb6 VZ |
704 | #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) |
705 | #error "Min DB doorbell stride is 8" | |
706 | #endif | |
7a9b2557 VZ |
707 | #define DPM_TRIGER_TYPE 0x40 |
708 | #define DOORBELL(bp, cid, val) \ | |
709 | do { \ | |
523224a3 | 710 | writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ |
7a9b2557 VZ |
711 | DPM_TRIGER_TYPE); \ |
712 | } while (0) | |
713 | ||
7a9b2557 VZ |
714 | /* TX CSUM helpers */ |
715 | #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ | |
716 | skb->csum_offset) | |
717 | #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ | |
718 | skb->csum_offset)) | |
719 | ||
91226790 | 720 | #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) |
7a9b2557 | 721 | |
a848ade4 DK |
722 | #define XMIT_PLAIN 0 |
723 | #define XMIT_CSUM_V4 (1 << 0) | |
724 | #define XMIT_CSUM_V6 (1 << 1) | |
725 | #define XMIT_CSUM_TCP (1 << 2) | |
726 | #define XMIT_GSO_V4 (1 << 3) | |
727 | #define XMIT_GSO_V6 (1 << 4) | |
728 | #define XMIT_CSUM_ENC_V4 (1 << 5) | |
729 | #define XMIT_CSUM_ENC_V6 (1 << 6) | |
730 | #define XMIT_GSO_ENC_V4 (1 << 7) | |
731 | #define XMIT_GSO_ENC_V6 (1 << 8) | |
732 | ||
733 | #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) | |
734 | #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) | |
735 | ||
736 | #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) | |
737 | #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) | |
7a9b2557 | 738 | |
34f80b04 | 739 | /* stuff added to make the code fit 80Col */ |
619c5cb6 VZ |
740 | #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) |
741 | #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) | |
742 | #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) | |
743 | #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) | |
744 | #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) | |
7a9b2557 | 745 | |
1adcd8be EG |
746 | #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG |
747 | ||
052a38e0 EG |
748 | #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ |
749 | (((le16_to_cpu(flags) & \ | |
750 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ | |
751 | PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ | |
752 | == PRS_FLAG_OVERETH_IPV4) | |
7a9b2557 | 753 | #define BNX2X_RX_SUM_FIX(cqe) \ |
052a38e0 | 754 | BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) |
7a9b2557 | 755 | |
619c5cb6 VZ |
756 | #define FP_USB_FUNC_OFF \ |
757 | offsetof(struct cstorm_status_block_u, func) | |
758 | #define FP_CSB_FUNC_OFF \ | |
759 | offsetof(struct cstorm_status_block_c, func) | |
760 | ||
150966ad | 761 | #define HC_INDEX_ETH_RX_CQ_CONS 1 |
619c5cb6 | 762 | |
150966ad | 763 | #define HC_INDEX_OOO_TX_CQ_CONS 4 |
6383c0b3 | 764 | |
150966ad AE |
765 | #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 |
766 | ||
767 | #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 | |
6383c0b3 | 768 | |
150966ad AE |
769 | #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 |
770 | ||
771 | #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 | |
a2fbb9ea | 772 | |
34f80b04 | 773 | #define BNX2X_RX_SB_INDEX \ |
619c5cb6 | 774 | (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) |
a2fbb9ea | 775 | |
6383c0b3 AE |
776 | #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 |
777 | ||
778 | #define BNX2X_TX_SB_INDEX_COS0 \ | |
779 | (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) | |
7a9b2557 VZ |
780 | |
781 | /* end of fast path */ | |
782 | ||
34f80b04 | 783 | /* common */ |
a2fbb9ea | 784 | |
34f80b04 | 785 | struct bnx2x_common { |
a2fbb9ea | 786 | |
ad8d3948 | 787 | u32 chip_id; |
a2fbb9ea | 788 | /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ |
34f80b04 | 789 | #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) |
ad8d3948 | 790 | |
34f80b04 | 791 | #define CHIP_NUM(bp) (bp->common.chip_id >> 16) |
ad8d3948 EG |
792 | #define CHIP_NUM_57710 0x164e |
793 | #define CHIP_NUM_57711 0x164f | |
794 | #define CHIP_NUM_57711E 0x1650 | |
f2e0899f | 795 | #define CHIP_NUM_57712 0x1662 |
619c5cb6 | 796 | #define CHIP_NUM_57712_MF 0x1663 |
8395be5e | 797 | #define CHIP_NUM_57712_VF 0x166f |
619c5cb6 VZ |
798 | #define CHIP_NUM_57713 0x1651 |
799 | #define CHIP_NUM_57713E 0x1652 | |
800 | #define CHIP_NUM_57800 0x168a | |
801 | #define CHIP_NUM_57800_MF 0x16a5 | |
8395be5e | 802 | #define CHIP_NUM_57800_VF 0x16a9 |
619c5cb6 VZ |
803 | #define CHIP_NUM_57810 0x168e |
804 | #define CHIP_NUM_57810_MF 0x16ae | |
8395be5e | 805 | #define CHIP_NUM_57810_VF 0x16af |
7e8e02df BW |
806 | #define CHIP_NUM_57811 0x163d |
807 | #define CHIP_NUM_57811_MF 0x163e | |
8395be5e | 808 | #define CHIP_NUM_57811_VF 0x163f |
2de67439 | 809 | #define CHIP_NUM_57840_OBSOLETE 0x168d |
c3def943 YM |
810 | #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab |
811 | #define CHIP_NUM_57840_4_10 0x16a1 | |
812 | #define CHIP_NUM_57840_2_20 0x16a2 | |
813 | #define CHIP_NUM_57840_MF 0x16a4 | |
8395be5e | 814 | #define CHIP_NUM_57840_VF 0x16ad |
ad8d3948 EG |
815 | #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) |
816 | #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) | |
817 | #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) | |
f2e0899f | 818 | #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) |
8395be5e | 819 | #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) |
619c5cb6 VZ |
820 | #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) |
821 | #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) | |
822 | #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) | |
8395be5e | 823 | #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) |
619c5cb6 VZ |
824 | #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) |
825 | #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) | |
8395be5e | 826 | #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) |
7e8e02df BW |
827 | #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) |
828 | #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) | |
8395be5e | 829 | #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) |
c3def943 YM |
830 | #define CHIP_IS_57840(bp) \ |
831 | ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ | |
832 | (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ | |
833 | (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) | |
834 | #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ | |
835 | (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) | |
8395be5e | 836 | #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) |
ad8d3948 EG |
837 | #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ |
838 | CHIP_IS_57711E(bp)) | |
edb944d2 DK |
839 | #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ |
840 | CHIP_IS_57811_MF(bp) || \ | |
841 | CHIP_IS_57811_VF(bp)) | |
f2e0899f | 842 | #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ |
6ab20355 YM |
843 | CHIP_IS_57712_MF(bp) || \ |
844 | CHIP_IS_57712_VF(bp)) | |
619c5cb6 VZ |
845 | #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ |
846 | CHIP_IS_57800_MF(bp) || \ | |
6ab20355 | 847 | CHIP_IS_57800_VF(bp) || \ |
619c5cb6 VZ |
848 | CHIP_IS_57810(bp) || \ |
849 | CHIP_IS_57810_MF(bp) || \ | |
8395be5e | 850 | CHIP_IS_57810_VF(bp) || \ |
edb944d2 | 851 | CHIP_IS_57811xx(bp) || \ |
619c5cb6 | 852 | CHIP_IS_57840(bp) || \ |
8395be5e AE |
853 | CHIP_IS_57840_MF(bp) || \ |
854 | CHIP_IS_57840_VF(bp)) | |
f2e0899f | 855 | #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) |
619c5cb6 VZ |
856 | #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) |
857 | #define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) | |
858 | ||
859 | #define CHIP_REV_SHIFT 12 | |
860 | #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) | |
861 | #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) | |
862 | #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) | |
863 | #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) | |
ad8d3948 | 864 | /* assume maximum 5 revisions */ |
619c5cb6 | 865 | #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) |
ad8d3948 EG |
866 | /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ |
867 | #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
619c5cb6 | 868 | !(CHIP_REV_VAL(bp) & 0x00001000)) |
ad8d3948 EG |
869 | /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ |
870 | #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ | |
619c5cb6 | 871 | (CHIP_REV_VAL(bp) & 0x00001000)) |
ad8d3948 EG |
872 | |
873 | #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ | |
874 | ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) | |
875 | ||
34f80b04 EG |
876 | #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) |
877 | #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) | |
619c5cb6 VZ |
878 | #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ |
879 | (CHIP_REV_SHIFT + 1)) \ | |
880 | << CHIP_REV_SHIFT) | |
881 | #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ | |
882 | CHIP_REV_SIM(bp) :\ | |
883 | CHIP_REV_VAL(bp)) | |
884 | #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ | |
885 | (CHIP_REV(bp) == CHIP_REV_Bx)) | |
886 | #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ | |
887 | (CHIP_REV(bp) == CHIP_REV_Ax)) | |
55c11941 | 888 | /* This define is used in two main places: |
16a5fd92 | 889 | * 1. In the early stages of nic_load, to know if to configure Parser / Searcher |
55c11941 MS |
890 | * to nic-only mode or to offload mode. Offload mode is configured if either the |
891 | * chip is E1x (where MIC_MODE register is not applicable), or if cnic already | |
892 | * registered for this port (which means that the user wants storage services). | |
893 | * 2. During cnic-related load, to know if offload mode is already configured in | |
16a5fd92 | 894 | * the HW or needs to be configured. |
55c11941 | 895 | * Since the transition from nic-mode to offload-mode in HW causes traffic |
16a5fd92 | 896 | * corruption, nic-mode is configured only in ports on which storage services |
55c11941 MS |
897 | * where never requested. |
898 | */ | |
899 | #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) | |
a2fbb9ea | 900 | |
34f80b04 | 901 | int flash_size; |
754a2f52 DK |
902 | #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ |
903 | #define BNX2X_NVRAM_TIMEOUT_COUNT 30000 | |
904 | #define BNX2X_NVRAM_PAGE_SIZE 256 | |
a2fbb9ea | 905 | |
34f80b04 | 906 | u32 shmem_base; |
2691d51d | 907 | u32 shmem2_base; |
523224a3 | 908 | u32 mf_cfg_base; |
f2e0899f | 909 | u32 mf2_cfg_base; |
34f80b04 EG |
910 | |
911 | u32 hw_config; | |
c18487ee | 912 | |
34f80b04 | 913 | u32 bc_ver; |
523224a3 DK |
914 | |
915 | u8 int_block; | |
916 | #define INT_BLOCK_HC 0 | |
f2e0899f DK |
917 | #define INT_BLOCK_IGU 1 |
918 | #define INT_BLOCK_MODE_NORMAL 0 | |
919 | #define INT_BLOCK_MODE_BW_COMP 2 | |
920 | #define CHIP_INT_MODE_IS_NBC(bp) \ | |
619c5cb6 | 921 | (!CHIP_IS_E1x(bp) && \ |
f2e0899f DK |
922 | !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) |
923 | #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) | |
924 | ||
523224a3 | 925 | u8 chip_port_mode; |
f2e0899f DK |
926 | #define CHIP_4_PORT_MODE 0x0 |
927 | #define CHIP_2_PORT_MODE 0x1 | |
523224a3 | 928 | #define CHIP_PORT_MODE_NONE 0x2 |
f2e0899f DK |
929 | #define CHIP_MODE(bp) (bp->common.chip_port_mode) |
930 | #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) | |
1d187b34 BW |
931 | |
932 | u32 boot_mode; | |
34f80b04 | 933 | }; |
c18487ee | 934 | |
f2e0899f DK |
935 | /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ |
936 | #define BNX2X_IGU_STAS_MSG_VF_CNT 64 | |
937 | #define BNX2X_IGU_STAS_MSG_PF_CNT 4 | |
34f80b04 | 938 | |
27c1151c | 939 | #define MAX_IGU_ATTN_ACK_TO 100 |
34f80b04 EG |
940 | /* end of common */ |
941 | ||
942 | /* port */ | |
943 | ||
944 | struct bnx2x_port { | |
945 | u32 pmf; | |
c18487ee | 946 | |
a22f0788 | 947 | u32 link_config[LINK_CONFIG_SIZE]; |
a2fbb9ea | 948 | |
a22f0788 | 949 | u32 supported[LINK_CONFIG_SIZE]; |
34f80b04 EG |
950 | /* link settings - missing defines */ |
951 | #define SUPPORTED_2500baseX_Full (1 << 15) | |
952 | ||
a22f0788 | 953 | u32 advertising[LINK_CONFIG_SIZE]; |
a2fbb9ea | 954 | /* link settings - missing defines */ |
34f80b04 | 955 | #define ADVERTISED_2500baseX_Full (1 << 15) |
a2fbb9ea | 956 | |
34f80b04 | 957 | u32 phy_addr; |
c18487ee YR |
958 | |
959 | /* used to synchronize phy accesses */ | |
960 | struct mutex phy_mutex; | |
961 | ||
34f80b04 | 962 | u32 port_stx; |
a2fbb9ea | 963 | |
34f80b04 EG |
964 | struct nig_stats old_nig_stats; |
965 | }; | |
a2fbb9ea | 966 | |
34f80b04 EG |
967 | /* end of port */ |
968 | ||
619c5cb6 VZ |
969 | #define STATS_OFFSET32(stat_name) \ |
970 | (offsetof(struct bnx2x_eth_stats, stat_name) / 4) | |
bb2a0f7a | 971 | |
619c5cb6 VZ |
972 | /* slow path */ |
973 | ||
974 | /* slow path work-queue */ | |
975 | extern struct workqueue_struct *bnx2x_wq; | |
976 | ||
977 | #define BNX2X_MAX_NUM_OF_VFS 64 | |
1ab4434c AE |
978 | #define BNX2X_VF_CID_WND 0 |
979 | #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) | |
8db573ba | 980 | #define BNX2X_CLIENTS_PER_VF 1 |
290ca2bb | 981 | #define BNX2X_FIRST_VF_CID 256 |
1ab4434c | 982 | #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) |
523224a3 | 983 | #define BNX2X_VF_ID_INVALID 0xFF |
34f80b04 | 984 | |
523224a3 DK |
985 | /* |
986 | * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is | |
987 | * control by the number of fast-path status blocks supported by the | |
988 | * device (HW/FW). Each fast-path status block (FP-SB) aka non-default | |
989 | * status block represents an independent interrupts context that can | |
990 | * serve a regular L2 networking queue. However special L2 queues such | |
991 | * as the FCoE queue do not require a FP-SB and other components like | |
992 | * the CNIC may consume FP-SB reducing the number of possible L2 queues | |
993 | * | |
994 | * If the maximum number of FP-SB available is X then: | |
995 | * a. If CNIC is supported it consumes 1 FP-SB thus the max number of | |
996 | * regular L2 queues is Y=X-1 | |
16a5fd92 | 997 | * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) |
523224a3 DK |
998 | * c. If the FCoE L2 queue is supported the actual number of L2 queues |
999 | * is Y+1 | |
1000 | * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for | |
1001 | * slow-path interrupts) or Y+2 if CNIC is supported (one additional | |
1002 | * FP interrupt context for the CNIC). | |
1003 | * e. The number of HW context (CID count) is always X or X+1 if FCoE | |
16a5fd92 | 1004 | * L2 queue is supported. The cid for the FCoE L2 queue is always X. |
523224a3 DK |
1005 | */ |
1006 | ||
619c5cb6 VZ |
1007 | /* fast-path interrupt contexts E1x */ |
1008 | #define FP_SB_MAX_E1x 16 | |
1009 | /* fast-path interrupt contexts E2 */ | |
1010 | #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 | |
523224a3 | 1011 | |
34f80b04 EG |
1012 | union cdu_context { |
1013 | struct eth_context eth; | |
1014 | char pad[1024]; | |
1015 | }; | |
1016 | ||
523224a3 | 1017 | /* CDU host DB constants */ |
a052997e MS |
1018 | #define CDU_ILT_PAGE_SZ_HW 2 |
1019 | #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ | |
523224a3 DK |
1020 | #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) |
1021 | ||
523224a3 | 1022 | #define CNIC_ISCSI_CID_MAX 256 |
ec6ba945 VZ |
1023 | #define CNIC_FCOE_CID_MAX 2048 |
1024 | #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) | |
523224a3 | 1025 | #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) |
523224a3 | 1026 | |
619c5cb6 VZ |
1027 | #define QM_ILT_PAGE_SZ_HW 0 |
1028 | #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
1029 | #define QM_CID_ROUND 1024 |
1030 | ||
523224a3 | 1031 | /* TM (timers) host DB constants */ |
619c5cb6 VZ |
1032 | #define TM_ILT_PAGE_SZ_HW 0 |
1033 | #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
1034 | /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ |
1035 | #define TM_CONN_NUM 1024 | |
1036 | #define TM_ILT_SZ (8 * TM_CONN_NUM) | |
1037 | #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) | |
1038 | ||
1039 | /* SRC (Searcher) host DB constants */ | |
619c5cb6 VZ |
1040 | #define SRC_ILT_PAGE_SZ_HW 0 |
1041 | #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ | |
523224a3 DK |
1042 | #define SRC_HASH_BITS 10 |
1043 | #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ | |
1044 | #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) | |
1045 | #define SRC_T2_SZ SRC_ILT_SZ | |
1046 | #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) | |
619c5cb6 | 1047 | |
619c5cb6 | 1048 | #define MAX_DMAE_C 8 |
34f80b04 EG |
1049 | |
1050 | /* DMA memory not used in fastpath */ | |
1051 | struct bnx2x_slowpath { | |
619c5cb6 VZ |
1052 | union { |
1053 | struct mac_configuration_cmd e1x; | |
1054 | struct eth_classify_rules_ramrod_data e2; | |
1055 | } mac_rdata; | |
1056 | ||
619c5cb6 VZ |
1057 | union { |
1058 | struct tstorm_eth_mac_filter_config e1x; | |
1059 | struct eth_filter_rules_ramrod_data e2; | |
1060 | } rx_mode_rdata; | |
1061 | ||
1062 | union { | |
1063 | struct mac_configuration_cmd e1; | |
1064 | struct eth_multicast_rules_ramrod_data e2; | |
1065 | } mcast_rdata; | |
1066 | ||
1067 | struct eth_rss_update_ramrod_data rss_rdata; | |
1068 | ||
1069 | /* Queue State related ramrods are always sent under rtnl_lock */ | |
1070 | union { | |
1071 | struct client_init_ramrod_data init_data; | |
1072 | struct client_update_ramrod_data update_data; | |
1073 | } q_rdata; | |
1074 | ||
1075 | union { | |
1076 | struct function_start_data func_start; | |
6debea87 DK |
1077 | /* pfc configuration for DCBX ramrod */ |
1078 | struct flow_control_configuration pfc_config; | |
619c5cb6 | 1079 | } func_rdata; |
34f80b04 | 1080 | |
a3348722 BW |
1081 | /* afex ramrod can not be a part of func_rdata union because these |
1082 | * events might arrive in parallel to other events from func_rdata. | |
1083 | * Therefore, if they would have been defined in the same union, | |
1084 | * data can get corrupted. | |
1085 | */ | |
1086 | struct afex_vif_list_ramrod_data func_afex_rdata; | |
1087 | ||
34f80b04 EG |
1088 | /* used by dmae command executer */ |
1089 | struct dmae_command dmae[MAX_DMAE_C]; | |
1090 | ||
bb2a0f7a YG |
1091 | u32 stats_comp; |
1092 | union mac_stats mac_stats; | |
1093 | struct nig_stats nig_stats; | |
1094 | struct host_port_stats port_stats; | |
1095 | struct host_func_stats func_stats; | |
34f80b04 EG |
1096 | |
1097 | u32 wb_comp; | |
34f80b04 | 1098 | u32 wb_data[4]; |
1d187b34 BW |
1099 | |
1100 | union drv_info_to_mcp drv_info_to_mcp; | |
34f80b04 EG |
1101 | }; |
1102 | ||
1103 | #define bnx2x_sp(bp, var) (&bp->slowpath->var) | |
1104 | #define bnx2x_sp_mapping(bp, var) \ | |
1105 | (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) | |
1106 | ||
34f80b04 EG |
1107 | /* attn group wiring */ |
1108 | #define MAX_DYNAMIC_ATTN_GRPS 8 | |
1109 | ||
1110 | struct attn_route { | |
619c5cb6 | 1111 | u32 sig[5]; |
34f80b04 EG |
1112 | }; |
1113 | ||
523224a3 DK |
1114 | struct iro { |
1115 | u32 base; | |
1116 | u16 m1; | |
1117 | u16 m2; | |
1118 | u16 m3; | |
1119 | u16 size; | |
1120 | }; | |
1121 | ||
1122 | struct hw_context { | |
1123 | union cdu_context *vcxt; | |
1124 | dma_addr_t cxt_mapping; | |
1125 | size_t size; | |
1126 | }; | |
1127 | ||
1128 | /* forward */ | |
1129 | struct bnx2x_ilt; | |
1130 | ||
290ca2bb | 1131 | struct bnx2x_vfdb; |
c9ee9206 VZ |
1132 | |
1133 | enum bnx2x_recovery_state { | |
72fd0718 VZ |
1134 | BNX2X_RECOVERY_DONE, |
1135 | BNX2X_RECOVERY_INIT, | |
1136 | BNX2X_RECOVERY_WAIT, | |
95c6c616 AE |
1137 | BNX2X_RECOVERY_FAILED, |
1138 | BNX2X_RECOVERY_NIC_LOADING | |
c9ee9206 | 1139 | }; |
72fd0718 | 1140 | |
619c5cb6 | 1141 | /* |
523224a3 DK |
1142 | * Event queue (EQ or event ring) MC hsi |
1143 | * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 | |
1144 | */ | |
1145 | #define NUM_EQ_PAGES 1 | |
1146 | #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) | |
1147 | #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) | |
1148 | #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) | |
1149 | #define EQ_DESC_MASK (NUM_EQ_DESC - 1) | |
1150 | #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) | |
1151 | ||
1152 | /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ | |
1153 | #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ | |
1154 | (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) | |
1155 | ||
1156 | /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ | |
1157 | #define EQ_DESC(x) ((x) & EQ_DESC_MASK) | |
1158 | ||
1159 | #define BNX2X_EQ_INDEX \ | |
1160 | (&bp->def_status_blk->sp_sb.\ | |
1161 | index_values[HC_SP_INDEX_EQ_CONS]) | |
1162 | ||
2ae17f66 VZ |
1163 | /* This is a data that will be used to create a link report message. |
1164 | * We will keep the data used for the last link report in order | |
1165 | * to prevent reporting the same link parameters twice. | |
1166 | */ | |
1167 | struct bnx2x_link_report_data { | |
1168 | u16 line_speed; /* Effective line speed */ | |
1169 | unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ | |
1170 | }; | |
1171 | ||
1172 | enum { | |
1173 | BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ | |
1174 | BNX2X_LINK_REPORT_LINK_DOWN, | |
1175 | BNX2X_LINK_REPORT_RX_FC_ON, | |
1176 | BNX2X_LINK_REPORT_TX_FC_ON, | |
1177 | }; | |
1178 | ||
619c5cb6 VZ |
1179 | enum { |
1180 | BNX2X_PORT_QUERY_IDX, | |
1181 | BNX2X_PF_QUERY_IDX, | |
50f0a562 | 1182 | BNX2X_FCOE_QUERY_IDX, |
619c5cb6 VZ |
1183 | BNX2X_FIRST_QUEUE_QUERY_IDX, |
1184 | }; | |
1185 | ||
1186 | struct bnx2x_fw_stats_req { | |
1187 | struct stats_query_header hdr; | |
50f0a562 BW |
1188 | struct stats_query_entry query[FP_SB_MAX_E1x+ |
1189 | BNX2X_FIRST_QUEUE_QUERY_IDX]; | |
619c5cb6 VZ |
1190 | }; |
1191 | ||
1192 | struct bnx2x_fw_stats_data { | |
2de67439 YM |
1193 | struct stats_counter storm_counters; |
1194 | struct per_port_stats port; | |
1195 | struct per_pf_stats pf; | |
50f0a562 | 1196 | struct fcoe_statistics_params fcoe; |
2de67439 | 1197 | struct per_queue_stats queue_stats[1]; |
619c5cb6 VZ |
1198 | }; |
1199 | ||
7be08a72 AE |
1200 | /* Public slow path states */ |
1201 | enum { | |
6383c0b3 | 1202 | BNX2X_SP_RTNL_SETUP_TC, |
7be08a72 | 1203 | BNX2X_SP_RTNL_TX_TIMEOUT, |
8304859a | 1204 | BNX2X_SP_RTNL_FAN_FAILURE, |
8395be5e AE |
1205 | BNX2X_SP_RTNL_AFEX_F_UPDATE, |
1206 | BNX2X_SP_RTNL_ENABLE_SRIOV, | |
381ac16b AE |
1207 | BNX2X_SP_RTNL_VFPF_MCAST, |
1208 | BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, | |
3ec9f9ca | 1209 | BNX2X_SP_RTNL_HYPERVISOR_VLAN, |
7be08a72 AE |
1210 | }; |
1211 | ||
452427b0 | 1212 | struct bnx2x_prev_path_list { |
7fa6f340 | 1213 | struct list_head list; |
452427b0 YM |
1214 | u8 bus; |
1215 | u8 slot; | |
1216 | u8 path; | |
7fa6f340 | 1217 | u8 aer; |
c63da990 | 1218 | u8 undi; |
452427b0 YM |
1219 | }; |
1220 | ||
15192a8c BW |
1221 | struct bnx2x_sp_objs { |
1222 | /* MACs object */ | |
1223 | struct bnx2x_vlan_mac_obj mac_obj; | |
1224 | ||
1225 | /* Queue State object */ | |
1226 | struct bnx2x_queue_sp_obj q_obj; | |
1227 | }; | |
1228 | ||
1229 | struct bnx2x_fp_stats { | |
1230 | struct tstorm_per_queue_stats old_tclient; | |
1231 | struct ustorm_per_queue_stats old_uclient; | |
1232 | struct xstorm_per_queue_stats old_xclient; | |
1233 | struct bnx2x_eth_q_stats eth_q_stats; | |
1234 | struct bnx2x_eth_q_stats_old eth_q_stats_old; | |
1235 | }; | |
1236 | ||
34f80b04 EG |
1237 | struct bnx2x { |
1238 | /* Fields used in the tx and intr/napi performance paths | |
1239 | * are grouped together in the beginning of the structure | |
1240 | */ | |
523224a3 | 1241 | struct bnx2x_fastpath *fp; |
15192a8c BW |
1242 | struct bnx2x_sp_objs *sp_objs; |
1243 | struct bnx2x_fp_stats *fp_stats; | |
65565884 | 1244 | struct bnx2x_fp_txdata *bnx2x_txq; |
34f80b04 EG |
1245 | void __iomem *regview; |
1246 | void __iomem *doorbells; | |
523224a3 | 1247 | u16 db_size; |
34f80b04 | 1248 | |
619c5cb6 VZ |
1249 | u8 pf_num; /* absolute PF number */ |
1250 | u8 pfid; /* per-path PF number */ | |
1251 | int base_fw_ndsb; /**/ | |
1252 | #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) | |
1253 | #define BP_PORT(bp) (bp->pfid & 1) | |
1254 | #define BP_FUNC(bp) (bp->pfid) | |
1255 | #define BP_ABS_FUNC(bp) (bp->pf_num) | |
3395a033 DK |
1256 | #define BP_VN(bp) ((bp)->pfid >> 1) |
1257 | #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) | |
1258 | #define BP_L_ID(bp) (BP_VN(bp) << 2) | |
1259 | #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ | |
1260 | (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) | |
1261 | #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) | |
619c5cb6 | 1262 | |
6411280a | 1263 | #ifdef CONFIG_BNX2X_SRIOV |
1d6f3cd8 DK |
1264 | /* protects vf2pf mailbox from simultaneous access */ |
1265 | struct mutex vf2pf_mutex; | |
1ab4434c AE |
1266 | /* vf pf channel mailbox contains request and response buffers */ |
1267 | struct bnx2x_vf_mbx_msg *vf2pf_mbox; | |
1268 | dma_addr_t vf2pf_mbox_mapping; | |
1269 | ||
be1f1ffa AE |
1270 | /* we set aside a copy of the acquire response */ |
1271 | struct pfvf_acquire_resp_tlv acquire_resp; | |
1272 | ||
abc5a021 AE |
1273 | /* bulletin board for messages from pf to vf */ |
1274 | union pf_vf_bulletin *pf2vf_bulletin; | |
1275 | dma_addr_t pf2vf_bulletin_mapping; | |
1276 | ||
1277 | struct pf_vf_bulletin_content old_bulletin; | |
3c76feff AE |
1278 | |
1279 | u16 requested_nr_virtfn; | |
6411280a | 1280 | #endif /* CONFIG_BNX2X_SRIOV */ |
abc5a021 | 1281 | |
34f80b04 EG |
1282 | struct net_device *dev; |
1283 | struct pci_dev *pdev; | |
1284 | ||
619c5cb6 | 1285 | const struct iro *iro_arr; |
523224a3 DK |
1286 | #define IRO (bp->iro_arr) |
1287 | ||
c9ee9206 | 1288 | enum bnx2x_recovery_state recovery_state; |
72fd0718 | 1289 | int is_leader; |
523224a3 | 1290 | struct msix_entry *msix_table; |
34f80b04 EG |
1291 | |
1292 | int tx_ring_size; | |
1293 | ||
523224a3 DK |
1294 | /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ |
1295 | #define ETH_OVREHEAD (ETH_HLEN + 8 + 8) | |
34f80b04 EG |
1296 | #define ETH_MIN_PACKET_SIZE 60 |
1297 | #define ETH_MAX_PACKET_SIZE 1500 | |
1298 | #define ETH_MAX_JUMBO_PACKET_SIZE 9600 | |
621b4d66 DK |
1299 | /* TCP with Timestamp Option (32) + IPv6 (40) */ |
1300 | #define ETH_MAX_TPA_HEADER_SIZE 72 | |
a2fbb9ea | 1301 | |
0f00846d | 1302 | /* Max supported alignment is 256 (8 shift) */ |
e52fcb24 ED |
1303 | #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) |
1304 | ||
1305 | /* FW uses 2 Cache lines Alignment for start packet and size | |
1306 | * | |
1307 | * We assume skb_build() uses sizeof(struct skb_shared_info) bytes | |
1308 | * at the end of skb->data, to avoid wasting a full cache line. | |
1309 | * This reduces memory use (skb->truesize). | |
1310 | */ | |
1311 | #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) | |
1312 | ||
1313 | #define BNX2X_FW_RX_ALIGN_END \ | |
f57b07c0 | 1314 | max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ |
e52fcb24 ED |
1315 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) |
1316 | ||
523224a3 | 1317 | #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) |
0f00846d | 1318 | |
523224a3 DK |
1319 | struct host_sp_status_block *def_status_blk; |
1320 | #define DEF_SB_IGU_ID 16 | |
1321 | #define DEF_SB_ID HC_SP_SB_ID | |
1322 | __le16 def_idx; | |
4781bfad | 1323 | __le16 def_att_idx; |
34f80b04 EG |
1324 | u32 attn_state; |
1325 | struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; | |
34f80b04 EG |
1326 | |
1327 | /* slow path ring */ | |
1328 | struct eth_spe *spq; | |
1329 | dma_addr_t spq_mapping; | |
1330 | u16 spq_prod_idx; | |
1331 | struct eth_spe *spq_prod_bd; | |
1332 | struct eth_spe *spq_last_bd; | |
4781bfad | 1333 | __le16 *dsb_sp_prod; |
6e30dd4e | 1334 | atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ |
34f80b04 EG |
1335 | /* used to synchronize spq accesses */ |
1336 | spinlock_t spq_lock; | |
1337 | ||
523224a3 DK |
1338 | /* event queue */ |
1339 | union event_ring_elem *eq_ring; | |
1340 | dma_addr_t eq_mapping; | |
1341 | u16 eq_prod; | |
1342 | u16 eq_cons; | |
1343 | __le16 *eq_cons_sb; | |
6e30dd4e | 1344 | atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ |
523224a3 | 1345 | |
619c5cb6 VZ |
1346 | /* Counter for marking that there is a STAT_QUERY ramrod pending */ |
1347 | u16 stats_pending; | |
1348 | /* Counter for completed statistics ramrods */ | |
1349 | u16 stats_comp; | |
34f80b04 | 1350 | |
33471629 | 1351 | /* End of fields used in the performance code paths */ |
34f80b04 EG |
1352 | |
1353 | int panic; | |
7995c64e | 1354 | int msg_enable; |
34f80b04 EG |
1355 | |
1356 | u32 flags; | |
619c5cb6 VZ |
1357 | #define PCIX_FLAG (1 << 0) |
1358 | #define PCI_32BIT_FLAG (1 << 1) | |
1359 | #define ONE_PORT_FLAG (1 << 2) | |
1360 | #define NO_WOL_FLAG (1 << 3) | |
1361 | #define USING_DAC_FLAG (1 << 4) | |
1362 | #define USING_MSIX_FLAG (1 << 5) | |
1363 | #define USING_MSI_FLAG (1 << 6) | |
1364 | #define DISABLE_MSI_FLAG (1 << 7) | |
1365 | #define TPA_ENABLE_FLAG (1 << 8) | |
1366 | #define NO_MCP_FLAG (1 << 9) | |
621b4d66 | 1367 | #define GRO_ENABLE_FLAG (1 << 10) |
619c5cb6 VZ |
1368 | #define MF_FUNC_DIS (1 << 11) |
1369 | #define OWN_CNIC_IRQ (1 << 12) | |
1370 | #define NO_ISCSI_OOO_FLAG (1 << 13) | |
1371 | #define NO_ISCSI_FLAG (1 << 14) | |
1372 | #define NO_FCOE_FLAG (1 << 15) | |
0e898dd7 | 1373 | #define BC_SUPPORTS_PFC_STATS (1 << 17) |
2e499d3c | 1374 | #define BC_SUPPORTS_FCOE_FEATURES (1 << 19) |
30a5de77 | 1375 | #define USING_SINGLE_MSIX_FLAG (1 << 20) |
9876879f | 1376 | #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) |
1ab4434c AE |
1377 | #define IS_VF_FLAG (1 << 22) |
1378 | ||
1379 | #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) | |
6411280a AE |
1380 | |
1381 | #ifdef CONFIG_BNX2X_SRIOV | |
1ab4434c AE |
1382 | #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) |
1383 | #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) | |
6411280a AE |
1384 | #else |
1385 | #define IS_VF(bp) false | |
1386 | #define IS_PF(bp) true | |
1387 | #endif | |
ec6ba945 | 1388 | |
2ba45142 VZ |
1389 | #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) |
1390 | #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) | |
619c5cb6 | 1391 | #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) |
37b091ba | 1392 | |
55c11941 MS |
1393 | u8 cnic_support; |
1394 | bool cnic_enabled; | |
1395 | bool cnic_loaded; | |
4bd9b0ff | 1396 | struct cnic_eth_dev *(*cnic_probe)(struct net_device *); |
55c11941 MS |
1397 | |
1398 | /* Flag that indicates that we can start looking for FCoE L2 queue | |
1399 | * completions in the default status block. | |
1400 | */ | |
1401 | bool fcoe_init; | |
1402 | ||
34f80b04 | 1403 | int pm_cap; |
8d5726c4 | 1404 | int mrrs; |
34f80b04 | 1405 | |
1cf167f2 | 1406 | struct delayed_work sp_task; |
fd1fc79d | 1407 | atomic_t interrupt_occurred; |
7be08a72 | 1408 | struct delayed_work sp_rtnl_task; |
3deb8167 YR |
1409 | |
1410 | struct delayed_work period_task; | |
34f80b04 | 1411 | struct timer_list timer; |
34f80b04 EG |
1412 | int current_interval; |
1413 | ||
1414 | u16 fw_seq; | |
1415 | u16 fw_drv_pulse_wr_seq; | |
1416 | u32 func_stx; | |
1417 | ||
1418 | struct link_params link_params; | |
1419 | struct link_vars link_vars; | |
2ae17f66 VZ |
1420 | u32 link_cnt; |
1421 | struct bnx2x_link_report_data last_reported_link; | |
1422 | ||
01cd4528 | 1423 | struct mdio_if_info mdio; |
a2fbb9ea | 1424 | |
34f80b04 EG |
1425 | struct bnx2x_common common; |
1426 | struct bnx2x_port port; | |
1427 | ||
b475d78f YM |
1428 | struct cmng_init cmng; |
1429 | ||
f2e0899f | 1430 | u32 mf_config[E1HVN_MAX]; |
a3348722 | 1431 | u32 mf_ext_config; |
619c5cb6 | 1432 | u32 path_has_ovlan; /* E3 */ |
fb3bff17 DK |
1433 | u16 mf_ov; |
1434 | u8 mf_mode; | |
f85582f8 | 1435 | #define IS_MF(bp) (bp->mf_mode != 0) |
0793f83f DK |
1436 | #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) |
1437 | #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) | |
a3348722 | 1438 | #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) |
a2fbb9ea | 1439 | |
f1410647 ET |
1440 | u8 wol; |
1441 | ||
34f80b04 | 1442 | int rx_ring_size; |
a2fbb9ea | 1443 | |
34f80b04 EG |
1444 | u16 tx_quick_cons_trip_int; |
1445 | u16 tx_quick_cons_trip; | |
1446 | u16 tx_ticks_int; | |
1447 | u16 tx_ticks; | |
a2fbb9ea | 1448 | |
34f80b04 EG |
1449 | u16 rx_quick_cons_trip_int; |
1450 | u16 rx_quick_cons_trip; | |
1451 | u16 rx_ticks_int; | |
1452 | u16 rx_ticks; | |
cdaa7cb8 VZ |
1453 | /* Maximal coalescing timeout in us */ |
1454 | #define BNX2X_MAX_COALESCE_TOUT (0xf0*12) | |
a2fbb9ea | 1455 | |
34f80b04 | 1456 | u32 lin_cnt; |
a2fbb9ea | 1457 | |
619c5cb6 | 1458 | u16 state; |
356e2385 | 1459 | #define BNX2X_STATE_CLOSED 0 |
34f80b04 EG |
1460 | #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 |
1461 | #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 | |
a2fbb9ea | 1462 | #define BNX2X_STATE_OPEN 0x3000 |
34f80b04 | 1463 | #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 |
a2fbb9ea | 1464 | #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 |
619c5cb6 | 1465 | |
34f80b04 EG |
1466 | #define BNX2X_STATE_DIAG 0xe000 |
1467 | #define BNX2X_STATE_ERROR 0xf000 | |
a2fbb9ea | 1468 | |
6383c0b3 AE |
1469 | #define BNX2X_MAX_PRIORITY 8 |
1470 | #define BNX2X_MAX_ENTRIES_PER_PRI 16 | |
1471 | #define BNX2X_MAX_COS 3 | |
1472 | #define BNX2X_MAX_TX_COS 2 | |
54b9ddaa | 1473 | int num_queues; |
55c11941 MS |
1474 | uint num_ethernet_queues; |
1475 | uint num_cnic_queues; | |
0e8d2ec5 | 1476 | int num_napi_queues; |
5d7cd496 | 1477 | int disable_tpa; |
523224a3 | 1478 | |
34f80b04 EG |
1479 | u32 rx_mode; |
1480 | #define BNX2X_RX_MODE_NONE 0 | |
1481 | #define BNX2X_RX_MODE_NORMAL 1 | |
1482 | #define BNX2X_RX_MODE_ALLMULTI 2 | |
1483 | #define BNX2X_RX_MODE_PROMISC 3 | |
1484 | #define BNX2X_MAX_MULTICAST 64 | |
a2fbb9ea | 1485 | |
523224a3 DK |
1486 | u8 igu_dsb_id; |
1487 | u8 igu_base_sb; | |
1488 | u8 igu_sb_cnt; | |
55c11941 | 1489 | u8 min_msix_vec_cnt; |
65565884 | 1490 | |
1ab4434c | 1491 | u32 igu_base_addr; |
34f80b04 | 1492 | dma_addr_t def_status_blk_mapping; |
a2fbb9ea | 1493 | |
34f80b04 EG |
1494 | struct bnx2x_slowpath *slowpath; |
1495 | dma_addr_t slowpath_mapping; | |
619c5cb6 VZ |
1496 | |
1497 | /* Total number of FW statistics requests */ | |
1498 | u8 fw_stats_num; | |
1499 | ||
1500 | /* | |
1501 | * This is a memory buffer that will contain both statistics | |
1502 | * ramrod request and data. | |
1503 | */ | |
1504 | void *fw_stats; | |
1505 | dma_addr_t fw_stats_mapping; | |
1506 | ||
1507 | /* | |
1508 | * FW statistics request shortcut (points at the | |
1509 | * beginning of fw_stats buffer). | |
1510 | */ | |
1511 | struct bnx2x_fw_stats_req *fw_stats_req; | |
1512 | dma_addr_t fw_stats_req_mapping; | |
1513 | int fw_stats_req_sz; | |
1514 | ||
1515 | /* | |
4907cb7b | 1516 | * FW statistics data shortcut (points at the beginning of |
619c5cb6 VZ |
1517 | * fw_stats buffer + fw_stats_req_sz). |
1518 | */ | |
1519 | struct bnx2x_fw_stats_data *fw_stats_data; | |
1520 | dma_addr_t fw_stats_data_mapping; | |
1521 | int fw_stats_data_sz; | |
1522 | ||
a052997e MS |
1523 | /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB |
1524 | * context size we need 8 ILT entries. | |
1525 | */ | |
1526 | #define ILT_MAX_L2_LINES 8 | |
1527 | struct hw_context context[ILT_MAX_L2_LINES]; | |
523224a3 DK |
1528 | |
1529 | struct bnx2x_ilt *ilt; | |
1530 | #define BP_ILT(bp) ((bp)->ilt) | |
619c5cb6 | 1531 | #define ILT_MAX_LINES 256 |
6383c0b3 AE |
1532 | /* |
1533 | * Maximum supported number of RSS queues: number of IGU SBs minus one that goes | |
1534 | * to CNIC. | |
1535 | */ | |
55c11941 | 1536 | #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) |
523224a3 | 1537 | |
6383c0b3 AE |
1538 | /* |
1539 | * Maximum CID count that might be required by the bnx2x: | |
37ae41a9 | 1540 | * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI |
6383c0b3 | 1541 | */ |
37ae41a9 | 1542 | #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ |
55c11941 | 1543 | + 2 * CNIC_SUPPORT(bp)) |
37ae41a9 | 1544 | #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ |
55c11941 | 1545 | + 2 * CNIC_SUPPORT(bp)) |
6383c0b3 AE |
1546 | #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ |
1547 | ILT_PAGE_CIDS)) | |
523224a3 DK |
1548 | |
1549 | int qm_cid_count; | |
a2fbb9ea | 1550 | |
7964211d | 1551 | bool dropless_fc; |
a18f5128 | 1552 | |
37b091ba MC |
1553 | void *t2; |
1554 | dma_addr_t t2_mapping; | |
13707f9e | 1555 | struct cnic_ops __rcu *cnic_ops; |
37b091ba MC |
1556 | void *cnic_data; |
1557 | u32 cnic_tag; | |
1558 | struct cnic_eth_dev cnic_eth_dev; | |
523224a3 | 1559 | union host_hc_status_block cnic_sb; |
37b091ba | 1560 | dma_addr_t cnic_sb_mapping; |
37b091ba MC |
1561 | struct eth_spe *cnic_kwq; |
1562 | struct eth_spe *cnic_kwq_prod; | |
1563 | struct eth_spe *cnic_kwq_cons; | |
1564 | struct eth_spe *cnic_kwq_last; | |
1565 | u16 cnic_kwq_pending; | |
1566 | u16 cnic_spq_pending; | |
ec6ba945 | 1567 | u8 fip_mac[ETH_ALEN]; |
619c5cb6 VZ |
1568 | struct mutex cnic_mutex; |
1569 | struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; | |
1570 | ||
16a5fd92 | 1571 | /* Start index of the "special" (CNIC related) L2 clients */ |
619c5cb6 | 1572 | u8 cnic_base_cl_id; |
37b091ba | 1573 | |
ad8d3948 EG |
1574 | int dmae_ready; |
1575 | /* used to synchronize dmae accesses */ | |
6e30dd4e | 1576 | spinlock_t dmae_lock; |
ad8d3948 | 1577 | |
c4ff7cbf EG |
1578 | /* used to protect the FW mail box */ |
1579 | struct mutex fw_mb_mutex; | |
1580 | ||
bb2a0f7a YG |
1581 | /* used to synchronize stats collecting */ |
1582 | int stats_state; | |
a13773a5 VZ |
1583 | |
1584 | /* used for synchronization of concurrent threads statistics handling */ | |
1585 | spinlock_t stats_lock; | |
1586 | ||
bb2a0f7a YG |
1587 | /* used by dmae command loader */ |
1588 | struct dmae_command stats_dmae; | |
1589 | int executer_idx; | |
ad8d3948 | 1590 | |
bb2a0f7a | 1591 | u16 stats_counter; |
bb2a0f7a | 1592 | struct bnx2x_eth_stats eth_stats; |
cb4dca27 | 1593 | struct host_func_stats func_stats; |
1355b704 MY |
1594 | struct bnx2x_eth_stats_old eth_stats_old; |
1595 | struct bnx2x_net_stats_old net_stats_old; | |
1596 | struct bnx2x_fw_port_stats_old fw_stats_old; | |
1597 | bool stats_init; | |
bb2a0f7a YG |
1598 | |
1599 | struct z_stream_s *strm; | |
1600 | void *gunzip_buf; | |
1601 | dma_addr_t gunzip_mapping; | |
1602 | int gunzip_outlen; | |
ad8d3948 | 1603 | #define FW_BUF_SIZE 0x8000 |
573f2035 EG |
1604 | #define GUNZIP_BUF(bp) (bp->gunzip_buf) |
1605 | #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) | |
1606 | #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) | |
a2fbb9ea | 1607 | |
ab6ad5a4 | 1608 | struct raw_op *init_ops; |
94a78b79 | 1609 | /* Init blocks offsets inside init_ops */ |
ab6ad5a4 | 1610 | u16 *init_ops_offsets; |
94a78b79 | 1611 | /* Data blob - has 32 bit granularity */ |
ab6ad5a4 | 1612 | u32 *init_data; |
619c5cb6 VZ |
1613 | u32 init_mode_flags; |
1614 | #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) | |
94a78b79 | 1615 | /* Zipped PRAM blobs - raw data */ |
ab6ad5a4 EG |
1616 | const u8 *tsem_int_table_data; |
1617 | const u8 *tsem_pram_data; | |
1618 | const u8 *usem_int_table_data; | |
1619 | const u8 *usem_pram_data; | |
1620 | const u8 *xsem_int_table_data; | |
1621 | const u8 *xsem_pram_data; | |
1622 | const u8 *csem_int_table_data; | |
1623 | const u8 *csem_pram_data; | |
573f2035 EG |
1624 | #define INIT_OPS(bp) (bp->init_ops) |
1625 | #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) | |
1626 | #define INIT_DATA(bp) (bp->init_data) | |
1627 | #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) | |
1628 | #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) | |
1629 | #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) | |
1630 | #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) | |
1631 | #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) | |
1632 | #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) | |
1633 | #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) | |
1634 | #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) | |
1635 | ||
619c5cb6 | 1636 | #define PHY_FW_VER_LEN 20 |
34f24c7f | 1637 | char fw_ver[32]; |
ab6ad5a4 | 1638 | const struct firmware *firmware; |
619c5cb6 | 1639 | |
290ca2bb AE |
1640 | struct bnx2x_vfdb *vfdb; |
1641 | #define IS_SRIOV(bp) ((bp)->vfdb) | |
1642 | ||
785b9b1a SR |
1643 | /* DCB support on/off */ |
1644 | u16 dcb_state; | |
1645 | #define BNX2X_DCB_STATE_OFF 0 | |
1646 | #define BNX2X_DCB_STATE_ON 1 | |
1647 | ||
1648 | /* DCBX engine mode */ | |
1649 | int dcbx_enabled; | |
1650 | #define BNX2X_DCBX_ENABLED_OFF 0 | |
1651 | #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 | |
1652 | #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 | |
1653 | #define BNX2X_DCBX_ENABLED_INVALID (-1) | |
1654 | ||
1655 | bool dcbx_mode_uset; | |
1656 | ||
e4901dde | 1657 | struct bnx2x_config_dcbx_params dcbx_config_params; |
e4901dde VZ |
1658 | struct bnx2x_dcbx_port_params dcbx_port_params; |
1659 | int dcb_version; | |
1660 | ||
619c5cb6 | 1661 | /* CAM credit pools */ |
b56e9670 AE |
1662 | |
1663 | /* used only in sriov */ | |
1664 | struct bnx2x_credit_pool_obj vlans_pool; | |
1665 | ||
619c5cb6 VZ |
1666 | struct bnx2x_credit_pool_obj macs_pool; |
1667 | ||
1668 | /* RX_MODE object */ | |
1669 | struct bnx2x_rx_mode_obj rx_mode_obj; | |
1670 | ||
1671 | /* MCAST object */ | |
1672 | struct bnx2x_mcast_obj mcast_obj; | |
1673 | ||
1674 | /* RSS configuration object */ | |
1675 | struct bnx2x_rss_config_obj rss_conf_obj; | |
1676 | ||
1677 | /* Function State controlling object */ | |
1678 | struct bnx2x_func_sp_obj func_obj; | |
1679 | ||
1680 | unsigned long sp_state; | |
1681 | ||
7be08a72 AE |
1682 | /* operation indication for the sp_rtnl task */ |
1683 | unsigned long sp_rtnl_state; | |
1684 | ||
16a5fd92 | 1685 | /* DCBX Negotiation results */ |
e4901dde VZ |
1686 | struct dcbx_features dcbx_local_feat; |
1687 | u32 dcbx_error; | |
619c5cb6 | 1688 | |
0be6bc62 SR |
1689 | #ifdef BCM_DCBNL |
1690 | struct dcbx_features dcbx_remote_feat; | |
1691 | u32 dcbx_remote_flags; | |
1692 | #endif | |
a3348722 BW |
1693 | /* AFEX: store default vlan used */ |
1694 | int afex_def_vlan_tag; | |
1695 | enum mf_cfg_afex_vlan_mode afex_vlan_mode; | |
e3835b99 | 1696 | u32 pending_max; |
6383c0b3 AE |
1697 | |
1698 | /* multiple tx classes of service */ | |
1699 | u8 max_cos; | |
1700 | ||
1701 | /* priority to cos mapping */ | |
1702 | u8 prio_to_cos[8]; | |
c3146eb6 DK |
1703 | |
1704 | int fp_array_size; | |
07ba6af4 | 1705 | u32 dump_preset_idx; |
a2fbb9ea ET |
1706 | }; |
1707 | ||
619c5cb6 VZ |
1708 | /* Tx queues may be less or equal to Rx queues */ |
1709 | extern int num_queues; | |
54b9ddaa | 1710 | #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) |
55c11941 | 1711 | #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) |
65565884 | 1712 | #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ |
55c11941 | 1713 | (bp)->num_cnic_queues) |
6383c0b3 | 1714 | #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) |
ec6ba945 | 1715 | |
54b9ddaa | 1716 | #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) |
3196a88a | 1717 | |
6383c0b3 AE |
1718 | #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) |
1719 | /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ | |
523224a3 DK |
1720 | |
1721 | #define RSS_IPV4_CAP_MASK \ | |
1722 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | |
1723 | ||
1724 | #define RSS_IPV4_TCP_CAP_MASK \ | |
1725 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | |
1726 | ||
1727 | #define RSS_IPV6_CAP_MASK \ | |
1728 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | |
1729 | ||
1730 | #define RSS_IPV6_TCP_CAP_MASK \ | |
1731 | TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | |
1732 | ||
1733 | /* func init flags */ | |
619c5cb6 VZ |
1734 | #define FUNC_FLG_RSS 0x0001 |
1735 | #define FUNC_FLG_STATS 0x0002 | |
1736 | /* removed FUNC_FLG_UNMATCHED 0x0004 */ | |
1737 | #define FUNC_FLG_TPA 0x0008 | |
1738 | #define FUNC_FLG_SPQ 0x0010 | |
1739 | #define FUNC_FLG_LEADING 0x0020 /* PF only */ | |
523224a3 | 1740 | |
523224a3 | 1741 | struct bnx2x_func_init_params { |
523224a3 DK |
1742 | /* dma */ |
1743 | dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ | |
1744 | dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ | |
1745 | ||
1746 | u16 func_flgs; | |
1747 | u16 func_id; /* abs fid */ | |
1748 | u16 pf_id; | |
1749 | u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ | |
1750 | }; | |
1751 | ||
55c11941 MS |
1752 | #define for_each_cnic_queue(bp, var) \ |
1753 | for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ | |
1754 | (var)++) \ | |
1755 | if (skip_queue(bp, var)) \ | |
1756 | continue; \ | |
1757 | else | |
1758 | ||
ec6ba945 | 1759 | #define for_each_eth_queue(bp, var) \ |
6383c0b3 | 1760 | for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
ec6ba945 VZ |
1761 | |
1762 | #define for_each_nondefault_eth_queue(bp, var) \ | |
6383c0b3 | 1763 | for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) |
ec6ba945 | 1764 | |
555f6c78 | 1765 | #define for_each_queue(bp, var) \ |
6383c0b3 | 1766 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1767 | if (skip_queue(bp, var)) \ |
1768 | continue; \ | |
1769 | else | |
1770 | ||
6383c0b3 | 1771 | /* Skip forwarding FP */ |
55c11941 MS |
1772 | #define for_each_valid_rx_queue(bp, var) \ |
1773 | for ((var) = 0; \ | |
1774 | (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ | |
1775 | BNX2X_NUM_ETH_QUEUES(bp)); \ | |
1776 | (var)++) \ | |
1777 | if (skip_rx_queue(bp, var)) \ | |
1778 | continue; \ | |
1779 | else | |
1780 | ||
1781 | #define for_each_rx_queue_cnic(bp, var) \ | |
1782 | for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ | |
1783 | (var)++) \ | |
1784 | if (skip_rx_queue(bp, var)) \ | |
1785 | continue; \ | |
1786 | else | |
1787 | ||
ec6ba945 | 1788 | #define for_each_rx_queue(bp, var) \ |
6383c0b3 | 1789 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1790 | if (skip_rx_queue(bp, var)) \ |
1791 | continue; \ | |
1792 | else | |
1793 | ||
6383c0b3 | 1794 | /* Skip OOO FP */ |
55c11941 MS |
1795 | #define for_each_valid_tx_queue(bp, var) \ |
1796 | for ((var) = 0; \ | |
1797 | (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ | |
1798 | BNX2X_NUM_ETH_QUEUES(bp)); \ | |
1799 | (var)++) \ | |
1800 | if (skip_tx_queue(bp, var)) \ | |
1801 | continue; \ | |
1802 | else | |
1803 | ||
1804 | #define for_each_tx_queue_cnic(bp, var) \ | |
1805 | for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ | |
1806 | (var)++) \ | |
1807 | if (skip_tx_queue(bp, var)) \ | |
1808 | continue; \ | |
1809 | else | |
1810 | ||
ec6ba945 | 1811 | #define for_each_tx_queue(bp, var) \ |
6383c0b3 | 1812 | for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1813 | if (skip_tx_queue(bp, var)) \ |
1814 | continue; \ | |
1815 | else | |
1816 | ||
3196a88a | 1817 | #define for_each_nondefault_queue(bp, var) \ |
6383c0b3 | 1818 | for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ |
ec6ba945 VZ |
1819 | if (skip_queue(bp, var)) \ |
1820 | continue; \ | |
1821 | else | |
3196a88a | 1822 | |
6383c0b3 AE |
1823 | #define for_each_cos_in_tx_queue(fp, var) \ |
1824 | for ((var) = 0; (var) < (fp)->max_cos; (var)++) | |
1825 | ||
ec6ba945 | 1826 | /* skip rx queue |
008d23e4 | 1827 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1828 | */ |
1829 | #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1830 | ||
1831 | /* skip tx queue | |
008d23e4 | 1832 | * if FCOE l2 support is disabled and this is the fcoe L2 queue |
ec6ba945 VZ |
1833 | */ |
1834 | #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
1835 | ||
1836 | #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) | |
3196a88a | 1837 | |
619c5cb6 VZ |
1838 | /** |
1839 | * bnx2x_set_mac_one - configure a single MAC address | |
1840 | * | |
1841 | * @bp: driver handle | |
1842 | * @mac: MAC to configure | |
1843 | * @obj: MAC object handle | |
1844 | * @set: if 'true' add a new MAC, otherwise - delete | |
1845 | * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) | |
1846 | * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) | |
1847 | * | |
1848 | * Configures one MAC according to provided parameters or continues the | |
1849 | * execution of previously scheduled commands if RAMROD_CONT is set in | |
1850 | * ramrod_flags. | |
1851 | * | |
1852 | * Returns zero if operation has successfully completed, a positive value if the | |
1853 | * operation has been successfully scheduled and a negative - if a requested | |
1854 | * operations has failed. | |
1855 | */ | |
1856 | int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, | |
1857 | struct bnx2x_vlan_mac_obj *obj, bool set, | |
1858 | int mac_type, unsigned long *ramrod_flags); | |
619c5cb6 VZ |
1859 | /** |
1860 | * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object | |
1861 | * | |
1862 | * @bp: driver handle | |
1863 | * @mac_obj: MAC object handle | |
1864 | * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) | |
1865 | * @wait_for_comp: if 'true' block until completion | |
1866 | * | |
1867 | * Deletes all MACs of the specific type (e.g. ETH, UC list). | |
1868 | * | |
1869 | * Returns zero if operation has successfully completed, a positive value if the | |
1870 | * operation has been successfully scheduled and a negative - if a requested | |
1871 | * operations has failed. | |
1872 | */ | |
1873 | int bnx2x_del_all_macs(struct bnx2x *bp, | |
1874 | struct bnx2x_vlan_mac_obj *mac_obj, | |
1875 | int mac_type, bool wait_for_comp); | |
1876 | ||
1877 | /* Init Function API */ | |
1878 | void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); | |
b93288d5 AE |
1879 | void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
1880 | u8 vf_valid, int fw_sb_id, int igu_sb_id); | |
b56e9670 | 1881 | u32 bnx2x_get_pretend_reg(struct bnx2x *bp); |
619c5cb6 VZ |
1882 | int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); |
1883 | int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); | |
1884 | int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); | |
1885 | int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); | |
2ae17f66 VZ |
1886 | void bnx2x_read_mf_cfg(struct bnx2x *bp); |
1887 | ||
b56e9670 | 1888 | int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); |
619c5cb6 | 1889 | |
f85582f8 | 1890 | /* dmae */ |
c18487ee YR |
1891 | void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); |
1892 | void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, | |
1893 | u32 len32); | |
f85582f8 DK |
1894 | void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); |
1895 | u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); | |
1896 | u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); | |
1897 | u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, | |
1898 | bool with_comp, u8 comp_type); | |
1899 | ||
fd1fc79d AE |
1900 | void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, |
1901 | u8 src_type, u8 dst_type); | |
1902 | int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae); | |
fd1fc79d | 1903 | |
d16132ce AE |
1904 | /* FLR related routines */ |
1905 | u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); | |
1906 | void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); | |
1907 | int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); | |
b56e9670 | 1908 | u8 bnx2x_is_pcie_pending(struct pci_dev *dev); |
d16132ce AE |
1909 | int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, |
1910 | char *msg, u32 poll_cnt); | |
f85582f8 | 1911 | |
de0c62db DK |
1912 | void bnx2x_calc_fc_adv(struct bnx2x *bp); |
1913 | int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, | |
619c5cb6 | 1914 | u32 data_hi, u32 data_lo, int cmd_type); |
de0c62db | 1915 | void bnx2x_update_coalesce(struct bnx2x *bp); |
1ac9e428 | 1916 | int bnx2x_get_cur_phy_idx(struct bnx2x *bp); |
f85582f8 | 1917 | |
178135c1 DK |
1918 | bool bnx2x_port_after_undi(struct bnx2x *bp); |
1919 | ||
34f80b04 EG |
1920 | static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, |
1921 | int wait) | |
1922 | { | |
1923 | u32 val; | |
1924 | ||
1925 | do { | |
1926 | val = REG_RD(bp, reg); | |
1927 | if (val == expected) | |
1928 | break; | |
1929 | ms -= wait; | |
1930 | msleep(wait); | |
1931 | ||
1932 | } while (ms > 0); | |
1933 | ||
1934 | return val; | |
1935 | } | |
f85582f8 | 1936 | |
b56e9670 AE |
1937 | void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, |
1938 | bool is_pf); | |
1939 | ||
1f9061d2 JP |
1940 | #define BNX2X_ILT_ZALLOC(x, y, size) \ |
1941 | x = dma_alloc_coherent(&bp->pdev->dev, size, y, \ | |
1942 | GFP_KERNEL | __GFP_ZERO) | |
523224a3 DK |
1943 | |
1944 | #define BNX2X_ILT_FREE(x, y, size) \ | |
1945 | do { \ | |
1946 | if (x) { \ | |
d245a111 | 1947 | dma_free_coherent(&bp->pdev->dev, size, x, y); \ |
523224a3 DK |
1948 | x = NULL; \ |
1949 | y = 0; \ | |
1950 | } \ | |
1951 | } while (0) | |
1952 | ||
1953 | #define ILOG2(x) (ilog2((x))) | |
1954 | ||
1955 | #define ILT_NUM_PAGE_ENTRIES (3072) | |
1956 | /* In 57710/11 we use whole table since we have 8 func | |
f85582f8 DK |
1957 | * In 57712 we have only 4 func, but use same size per func, then only half of |
1958 | * the table in use | |
523224a3 DK |
1959 | */ |
1960 | #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) | |
1961 | ||
1962 | #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) | |
1963 | /* | |
1964 | * the phys address is shifted right 12 bits and has an added | |
1965 | * 1=valid bit added to the 53rd bit | |
1966 | * then since this is a wide register(TM) | |
1967 | * we split it into two 32 bit writes | |
1968 | */ | |
1969 | #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) | |
1970 | #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) | |
34f80b04 | 1971 | |
34f80b04 EG |
1972 | /* load/unload mode */ |
1973 | #define LOAD_NORMAL 0 | |
1974 | #define LOAD_OPEN 1 | |
1975 | #define LOAD_DIAG 2 | |
8970b2e4 | 1976 | #define LOAD_LOOPBACK_EXT 3 |
34f80b04 EG |
1977 | #define UNLOAD_NORMAL 0 |
1978 | #define UNLOAD_CLOSE 1 | |
f85582f8 | 1979 | #define UNLOAD_RECOVERY 2 |
34f80b04 | 1980 | |
ad8d3948 | 1981 | /* DMAE command defines */ |
f2e0899f DK |
1982 | #define DMAE_TIMEOUT -1 |
1983 | #define DMAE_PCI_ERROR -2 /* E2 and onward */ | |
1984 | #define DMAE_NOT_RDY -3 | |
1985 | #define DMAE_PCI_ERR_FLAG 0x80000000 | |
1986 | ||
1987 | #define DMAE_SRC_PCI 0 | |
1988 | #define DMAE_SRC_GRC 1 | |
1989 | ||
1990 | #define DMAE_DST_NONE 0 | |
1991 | #define DMAE_DST_PCI 1 | |
1992 | #define DMAE_DST_GRC 2 | |
1993 | ||
1994 | #define DMAE_COMP_PCI 0 | |
1995 | #define DMAE_COMP_GRC 1 | |
1996 | ||
1997 | /* E2 and onward - PCI error handling in the completion */ | |
1998 | ||
1999 | #define DMAE_COMP_REGULAR 0 | |
2000 | #define DMAE_COM_SET_ERR 1 | |
ad8d3948 | 2001 | |
f2e0899f DK |
2002 | #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ |
2003 | DMAE_COMMAND_SRC_SHIFT) | |
2004 | #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ | |
2005 | DMAE_COMMAND_SRC_SHIFT) | |
ad8d3948 | 2006 | |
f2e0899f DK |
2007 | #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ |
2008 | DMAE_COMMAND_DST_SHIFT) | |
2009 | #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ | |
2010 | DMAE_COMMAND_DST_SHIFT) | |
2011 | ||
2012 | #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ | |
2013 | DMAE_COMMAND_C_DST_SHIFT) | |
2014 | #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ | |
2015 | DMAE_COMMAND_C_DST_SHIFT) | |
ad8d3948 EG |
2016 | |
2017 | #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE | |
2018 | ||
2019 | #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
2020 | #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
2021 | #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
2022 | #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) | |
2023 | ||
2024 | #define DMAE_CMD_PORT_0 0 | |
2025 | #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT | |
2026 | ||
2027 | #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET | |
2028 | #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET | |
2029 | #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT | |
2030 | ||
f2e0899f DK |
2031 | #define DMAE_SRC_PF 0 |
2032 | #define DMAE_SRC_VF 1 | |
2033 | ||
2034 | #define DMAE_DST_PF 0 | |
2035 | #define DMAE_DST_VF 1 | |
2036 | ||
2037 | #define DMAE_C_SRC 0 | |
2038 | #define DMAE_C_DST 1 | |
2039 | ||
ad8d3948 | 2040 | #define DMAE_LEN32_RD_MAX 0x80 |
02e3c6cb | 2041 | #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) |
ad8d3948 | 2042 | |
f2e0899f | 2043 | #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit |
16a5fd92 YM |
2044 | * indicates error |
2045 | */ | |
ad8d3948 EG |
2046 | |
2047 | #define MAX_DMAE_C_PER_PORT 8 | |
ab6ad5a4 | 2048 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
3395a033 | 2049 | BP_VN(bp)) |
ab6ad5a4 | 2050 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
ad8d3948 EG |
2051 | E1HVN_MAX) |
2052 | ||
25047950 ET |
2053 | /* PCIE link and speed */ |
2054 | #define PCICFG_LINK_WIDTH 0x1f00000 | |
2055 | #define PCICFG_LINK_WIDTH_SHIFT 20 | |
2056 | #define PCICFG_LINK_SPEED 0xf0000 | |
2057 | #define PCICFG_LINK_SPEED_SHIFT 16 | |
a2fbb9ea | 2058 | |
cf2c1df6 MS |
2059 | #define BNX2X_NUM_TESTS_SF 7 |
2060 | #define BNX2X_NUM_TESTS_MF 3 | |
2061 | #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ | |
2062 | BNX2X_NUM_TESTS_SF) | |
bb2a0f7a | 2063 | |
b5bf9068 EG |
2064 | #define BNX2X_PHY_LOOPBACK 0 |
2065 | #define BNX2X_MAC_LOOPBACK 1 | |
8970b2e4 | 2066 | #define BNX2X_EXT_LOOPBACK 2 |
b5bf9068 EG |
2067 | #define BNX2X_PHY_LOOPBACK_FAILED 1 |
2068 | #define BNX2X_MAC_LOOPBACK_FAILED 2 | |
8970b2e4 | 2069 | #define BNX2X_EXT_LOOPBACK_FAILED 3 |
bb2a0f7a YG |
2070 | #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ |
2071 | BNX2X_PHY_LOOPBACK_FAILED) | |
96fc1784 | 2072 | |
7a9b2557 VZ |
2073 | #define STROM_ASSERT_ARRAY_SIZE 50 |
2074 | ||
34f80b04 | 2075 | /* must be used on a CID before placing it on a HW ring */ |
ab6ad5a4 | 2076 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
3395a033 | 2077 | (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ |
619c5cb6 | 2078 | (x)) |
7a9b2557 VZ |
2079 | |
2080 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | |
2081 | #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) | |
2082 | ||
523224a3 | 2083 | #define BNX2X_BTR 4 |
7a9b2557 | 2084 | #define MAX_SPQ_PENDING 8 |
a2fbb9ea | 2085 | |
ff80ee02 DK |
2086 | /* CMNG constants, as derived from system spec calculations */ |
2087 | /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ | |
2088 | #define DEF_MIN_RATE 100 | |
9b3de1ef DK |
2089 | /* resolution of the rate shaping timer - 400 usec */ |
2090 | #define RS_PERIODIC_TIMEOUT_USEC 400 | |
34f80b04 | 2091 | /* number of bytes in single QM arbitration cycle - |
ff80ee02 DK |
2092 | * coefficient for calculating the fairness timer */ |
2093 | #define QM_ARB_BYTES 160000 | |
2094 | /* resolution of Min algorithm 1:100 */ | |
2095 | #define MIN_RES 100 | |
2096 | /* how many bytes above threshold for the minimal credit of Min algorithm*/ | |
2097 | #define MIN_ABOVE_THRESH 32768 | |
2098 | /* Fairness algorithm integration time coefficient - | |
2099 | * for calculating the actual Tfair */ | |
2100 | #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) | |
2101 | /* Memory of fairness algorithm . 2 cycles */ | |
2102 | #define FAIR_MEM 2 | |
34f80b04 | 2103 | |
34f80b04 EG |
2104 | #define ATTN_NIG_FOR_FUNC (1L << 8) |
2105 | #define ATTN_SW_TIMER_4_FUNC (1L << 9) | |
2106 | #define GPIO_2_FUNC (1L << 10) | |
2107 | #define GPIO_3_FUNC (1L << 11) | |
2108 | #define GPIO_4_FUNC (1L << 12) | |
2109 | #define ATTN_GENERAL_ATTN_1 (1L << 13) | |
2110 | #define ATTN_GENERAL_ATTN_2 (1L << 14) | |
2111 | #define ATTN_GENERAL_ATTN_3 (1L << 15) | |
2112 | #define ATTN_GENERAL_ATTN_4 (1L << 13) | |
2113 | #define ATTN_GENERAL_ATTN_5 (1L << 14) | |
2114 | #define ATTN_GENERAL_ATTN_6 (1L << 15) | |
2115 | ||
2116 | #define ATTN_HARD_WIRED_MASK 0xff00 | |
2117 | #define ATTENTION_ID 4 | |
a2fbb9ea | 2118 | |
3521b419 YM |
2119 | #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \ |
2120 | IS_MF_FCOE_AFEX(bp)) | |
a2fbb9ea | 2121 | |
34f80b04 EG |
2122 | /* stuff added to make the code fit 80Col */ |
2123 | ||
2124 | #define BNX2X_PMF_LINK_ASSERT \ | |
2125 | GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) | |
2126 | ||
a2fbb9ea ET |
2127 | #define BNX2X_MC_ASSERT_BITS \ |
2128 | (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
2129 | GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
2130 | GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ | |
2131 | GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) | |
2132 | ||
2133 | #define BNX2X_MCP_ASSERT \ | |
2134 | GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) | |
2135 | ||
34f80b04 EG |
2136 | #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) |
2137 | #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ | |
2138 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ | |
2139 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ | |
2140 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ | |
2141 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ | |
2142 | GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) | |
2143 | ||
a2fbb9ea ET |
2144 | #define HW_INTERRUT_ASSERT_SET_0 \ |
2145 | (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ | |
2146 | AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ | |
2147 | AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ | |
c14a09b7 | 2148 | AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ |
c9ee9206 | 2149 | AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) |
34f80b04 | 2150 | #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ |
a2fbb9ea ET |
2151 | AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ |
2152 | AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ | |
2153 | AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ | |
c9ee9206 VZ |
2154 | AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ |
2155 | AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ | |
2156 | AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) | |
a2fbb9ea ET |
2157 | #define HW_INTERRUT_ASSERT_SET_1 \ |
2158 | (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ | |
2159 | AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ | |
2160 | AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ | |
2161 | AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ | |
2162 | AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ | |
2163 | AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ | |
2164 | AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ | |
2165 | AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ | |
2166 | AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ | |
2167 | AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ | |
2168 | AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) | |
c9ee9206 | 2169 | #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ |
a2fbb9ea | 2170 | AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ |
c9ee9206 | 2171 | AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ |
a2fbb9ea | 2172 | AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ |
c9ee9206 | 2173 | AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ |
a2fbb9ea | 2174 | AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ |
ab6ad5a4 | 2175 | AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ |
c9ee9206 | 2176 | AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ |
ab6ad5a4 | 2177 | AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ |
a2fbb9ea ET |
2178 | AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ |
2179 | AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ | |
c9ee9206 | 2180 | AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ |
a2fbb9ea ET |
2181 | AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ |
2182 | AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ | |
c9ee9206 VZ |
2183 | AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ |
2184 | AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) | |
a2fbb9ea ET |
2185 | #define HW_INTERRUT_ASSERT_SET_2 \ |
2186 | (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ | |
2187 | AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ | |
2188 | AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ | |
2189 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ | |
2190 | AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) | |
34f80b04 | 2191 | #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ |
a2fbb9ea ET |
2192 | AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ |
2193 | AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ | |
2194 | AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ | |
2195 | AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ | |
c9ee9206 | 2196 | AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ |
a2fbb9ea ET |
2197 | AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ |
2198 | AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) | |
2199 | ||
72fd0718 VZ |
2200 | #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ |
2201 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ | |
2202 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ | |
2203 | AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) | |
a2fbb9ea | 2204 | |
8736c826 VZ |
2205 | #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ |
2206 | AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) | |
2207 | ||
34f80b04 | 2208 | #define MULTI_MASK 0x7f |
a2fbb9ea | 2209 | |
619c5cb6 VZ |
2210 | #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) |
2211 | #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) | |
2212 | #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) | |
2213 | #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) | |
2214 | ||
2215 | #define DEF_USB_IGU_INDEX_OFF \ | |
2216 | offsetof(struct cstorm_def_status_block_u, igu_index) | |
2217 | #define DEF_CSB_IGU_INDEX_OFF \ | |
2218 | offsetof(struct cstorm_def_status_block_c, igu_index) | |
2219 | #define DEF_XSB_IGU_INDEX_OFF \ | |
2220 | offsetof(struct xstorm_def_status_block, igu_index) | |
2221 | #define DEF_TSB_IGU_INDEX_OFF \ | |
2222 | offsetof(struct tstorm_def_status_block, igu_index) | |
2223 | ||
2224 | #define DEF_USB_SEGMENT_OFF \ | |
2225 | offsetof(struct cstorm_def_status_block_u, segment) | |
2226 | #define DEF_CSB_SEGMENT_OFF \ | |
2227 | offsetof(struct cstorm_def_status_block_c, segment) | |
2228 | #define DEF_XSB_SEGMENT_OFF \ | |
2229 | offsetof(struct xstorm_def_status_block, segment) | |
2230 | #define DEF_TSB_SEGMENT_OFF \ | |
2231 | offsetof(struct tstorm_def_status_block, segment) | |
2232 | ||
a2fbb9ea | 2233 | #define BNX2X_SP_DSB_INDEX \ |
523224a3 DK |
2234 | (&bp->def_status_blk->sp_sb.\ |
2235 | index_values[HC_SP_INDEX_ETH_DEF_CONS]) | |
f85582f8 | 2236 | |
a2fbb9ea | 2237 | #define CAM_IS_INVALID(x) \ |
523224a3 DK |
2238 | (GET_FLAG(x.flags, \ |
2239 | MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ | |
2240 | (T_ETH_MAC_COMMAND_INVALIDATE)) | |
a2fbb9ea | 2241 | |
34f80b04 EG |
2242 | /* Number of u32 elements in MC hash array */ |
2243 | #define MC_HASH_SIZE 8 | |
2244 | #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ | |
2245 | TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) | |
a2fbb9ea | 2246 | |
34f80b04 EG |
2247 | #ifndef PXP2_REG_PXP2_INT_STS |
2248 | #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 | |
2249 | #endif | |
2250 | ||
f2e0899f DK |
2251 | #ifndef ETH_MAX_RX_CLIENTS_E2 |
2252 | #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H | |
2253 | #endif | |
f85582f8 | 2254 | |
34f24c7f VZ |
2255 | #define BNX2X_VPD_LEN 128 |
2256 | #define VENDOR_ID_LEN 4 | |
2257 | ||
be1f1ffa AE |
2258 | #define VF_ACQUIRE_THRESH 3 |
2259 | #define VF_ACQUIRE_MAC_FILTERS 1 | |
2260 | #define VF_ACQUIRE_MC_FILTERS 10 | |
2261 | ||
2262 | #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ | |
2263 | (!((me_reg) & ME_REG_VF_ERR))) | |
ad5afc89 | 2264 | int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code); |
523224a3 | 2265 | /* Congestion management fairness mode */ |
2de67439 YM |
2266 | #define CMNG_FNS_NONE 0 |
2267 | #define CMNG_FNS_MINMAX 1 | |
523224a3 DK |
2268 | |
2269 | #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ | |
2270 | #define HC_SEG_ACCESS_ATTN 4 | |
2271 | #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ | |
2272 | ||
619c5cb6 VZ |
2273 | static const u32 dmae_reg_go_c[] = { |
2274 | DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, | |
2275 | DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, | |
2276 | DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, | |
2277 | DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 | |
2278 | }; | |
de0c62db | 2279 | |
005a07ba | 2280 | void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); |
3deb8167 | 2281 | void bnx2x_notify_link_changed(struct bnx2x *bp); |
614c76df | 2282 | |
9e62e912 | 2283 | #define BNX2X_MF_SD_PROTOCOL(bp) \ |
614c76df DK |
2284 | ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) |
2285 | ||
9e62e912 DK |
2286 | #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ |
2287 | (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) | |
614c76df | 2288 | |
9e62e912 DK |
2289 | #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ |
2290 | (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) | |
2291 | ||
2292 | #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) | |
2293 | #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) | |
2294 | ||
a3348722 BW |
2295 | #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ |
2296 | MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) | |
2297 | ||
2298 | #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) | |
9e62e912 DK |
2299 | #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ |
2300 | (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ | |
2301 | BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) | |
614c76df | 2302 | |
2de67439 YM |
2303 | #define SET_FLAG(value, mask, flag) \ |
2304 | do {\ | |
2305 | (value) &= ~(mask);\ | |
2306 | (value) |= ((flag) << (mask##_SHIFT));\ | |
2307 | } while (0) | |
2308 | ||
2309 | #define GET_FLAG(value, mask) \ | |
2310 | (((value) & (mask)) >> (mask##_SHIFT)) | |
2311 | ||
2312 | #define GET_FIELD(value, fname) \ | |
2313 | (((value) & (fname##_MASK)) >> (fname##_SHIFT)) | |
2314 | ||
55c11941 MS |
2315 | enum { |
2316 | SWITCH_UPDATE, | |
2317 | AFEX_UPDATE, | |
2318 | }; | |
2319 | ||
2320 | #define NUM_MACS 8 | |
a3348722 | 2321 | |
ca1ee4b2 DK |
2322 | enum bnx2x_pci_bus_speed { |
2323 | BNX2X_PCI_LINK_SPEED_2500 = 2500, | |
2324 | BNX2X_PCI_LINK_SPEED_5000 = 5000, | |
2325 | BNX2X_PCI_LINK_SPEED_8000 = 8000 | |
2326 | }; | |
a2fbb9ea | 2327 | #endif /* bnx2x.h */ |